1 /* 2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/interrupt.h> 35 #include <linux/slab.h> 36 #include <linux/export.h> 37 #include <linux/mm.h> 38 #include <linux/dma-mapping.h> 39 40 #include <linux/mlx4/cmd.h> 41 #include <linux/cpu_rmap.h> 42 43 #include "mlx4.h" 44 #include "fw.h" 45 46 enum { 47 MLX4_IRQNAME_SIZE = 32 48 }; 49 50 enum { 51 MLX4_NUM_ASYNC_EQE = 0x100, 52 MLX4_NUM_SPARE_EQE = 0x80, 53 MLX4_EQ_ENTRY_SIZE = 0x20 54 }; 55 56 #define MLX4_EQ_STATUS_OK ( 0 << 28) 57 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28) 58 #define MLX4_EQ_OWNER_SW ( 0 << 24) 59 #define MLX4_EQ_OWNER_HW ( 1 << 24) 60 #define MLX4_EQ_FLAG_EC ( 1 << 18) 61 #define MLX4_EQ_FLAG_OI ( 1 << 17) 62 #define MLX4_EQ_STATE_ARMED ( 9 << 8) 63 #define MLX4_EQ_STATE_FIRED (10 << 8) 64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8) 65 66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \ 67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \ 68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \ 69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \ 70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \ 71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \ 72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \ 73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \ 76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \ 77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ 79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \ 80 (1ull << MLX4_EVENT_TYPE_CMD) | \ 81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \ 82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \ 83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \ 84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING)) 85 86 static u64 get_async_ev_mask(struct mlx4_dev *dev) 87 { 88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK; 89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT); 91 92 return async_ev_mask; 93 } 94 95 static void eq_set_ci(struct mlx4_eq *eq, int req_not) 96 { 97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | 98 req_not << 31), 99 eq->doorbell); 100 /* We still want ordering, just not swabbing, so add a barrier */ 101 mb(); 102 } 103 104 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor) 105 { 106 /* (entry & (eq->nent - 1)) gives us a cyclic array */ 107 unsigned long offset = (entry & (eq->nent - 1)) * (MLX4_EQ_ENTRY_SIZE << eqe_factor); 108 /* CX3 is capable of extending the EQE from 32 to 64 bytes. 109 * When this feature is enabled, the first (in the lower addresses) 110 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes 111 * contain the legacy EQE information. 112 */ 113 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE; 114 } 115 116 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor) 117 { 118 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor); 119 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; 120 } 121 122 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq) 123 { 124 struct mlx4_eqe *eqe = 125 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)]; 126 return (!!(eqe->owner & 0x80) ^ 127 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ? 128 eqe : NULL; 129 } 130 131 void mlx4_gen_slave_eqe(struct work_struct *work) 132 { 133 struct mlx4_mfunc_master_ctx *master = 134 container_of(work, struct mlx4_mfunc_master_ctx, 135 slave_event_work); 136 struct mlx4_mfunc *mfunc = 137 container_of(master, struct mlx4_mfunc, master); 138 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc); 139 struct mlx4_dev *dev = &priv->dev; 140 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq; 141 struct mlx4_eqe *eqe; 142 u8 slave; 143 int i; 144 145 for (eqe = next_slave_event_eqe(slave_eq); eqe; 146 eqe = next_slave_event_eqe(slave_eq)) { 147 slave = eqe->slave_id; 148 149 /* All active slaves need to receive the event */ 150 if (slave == ALL_SLAVES) { 151 for (i = 0; i < dev->num_slaves; i++) { 152 if (i != dev->caps.function && 153 master->slave_state[i].active) 154 if (mlx4_GEN_EQE(dev, i, eqe)) 155 mlx4_warn(dev, "Failed to generate event for slave %d\n", 156 i); 157 } 158 } else { 159 if (mlx4_GEN_EQE(dev, slave, eqe)) 160 mlx4_warn(dev, "Failed to generate event for slave %d\n", 161 slave); 162 } 163 ++slave_eq->cons; 164 } 165 } 166 167 168 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe) 169 { 170 struct mlx4_priv *priv = mlx4_priv(dev); 171 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq; 172 struct mlx4_eqe *s_eqe; 173 unsigned long flags; 174 175 spin_lock_irqsave(&slave_eq->event_lock, flags); 176 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)]; 177 if ((!!(s_eqe->owner & 0x80)) ^ 178 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) { 179 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n", 180 slave); 181 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 182 return; 183 } 184 185 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1); 186 s_eqe->slave_id = slave; 187 /* ensure all information is written before setting the ownersip bit */ 188 wmb(); 189 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80; 190 ++slave_eq->prod; 191 192 queue_work(priv->mfunc.master.comm_wq, 193 &priv->mfunc.master.slave_event_work); 194 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 195 } 196 197 static void mlx4_slave_event(struct mlx4_dev *dev, int slave, 198 struct mlx4_eqe *eqe) 199 { 200 struct mlx4_priv *priv = mlx4_priv(dev); 201 struct mlx4_slave_state *s_slave = 202 &priv->mfunc.master.slave_state[slave]; 203 204 if (!s_slave->active) { 205 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/ 206 return; 207 } 208 209 slave_event(dev, slave, eqe); 210 } 211 212 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port) 213 { 214 struct mlx4_eqe eqe; 215 216 struct mlx4_priv *priv = mlx4_priv(dev); 217 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave]; 218 219 if (!s_slave->active) 220 return 0; 221 222 memset(&eqe, 0, sizeof eqe); 223 224 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 225 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE; 226 eqe.event.port_mgmt_change.port = port; 227 228 return mlx4_GEN_EQE(dev, slave, &eqe); 229 } 230 EXPORT_SYMBOL(mlx4_gen_pkey_eqe); 231 232 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port) 233 { 234 struct mlx4_eqe eqe; 235 236 /*don't send if we don't have the that slave */ 237 if (dev->num_vfs < slave) 238 return 0; 239 memset(&eqe, 0, sizeof eqe); 240 241 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 242 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO; 243 eqe.event.port_mgmt_change.port = port; 244 245 return mlx4_GEN_EQE(dev, slave, &eqe); 246 } 247 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe); 248 249 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, 250 u8 port_subtype_change) 251 { 252 struct mlx4_eqe eqe; 253 254 /*don't send if we don't have the that slave */ 255 if (dev->num_vfs < slave) 256 return 0; 257 memset(&eqe, 0, sizeof eqe); 258 259 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE; 260 eqe.subtype = port_subtype_change; 261 eqe.event.port_change.port = cpu_to_be32(port << 28); 262 263 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__, 264 port_subtype_change, slave, port); 265 return mlx4_GEN_EQE(dev, slave, &eqe); 266 } 267 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe); 268 269 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port) 270 { 271 struct mlx4_priv *priv = mlx4_priv(dev); 272 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 273 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 274 275 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 276 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 277 pr_err("%s: Error: asking for slave:%d, port:%d\n", 278 __func__, slave, port); 279 return SLAVE_PORT_DOWN; 280 } 281 return s_state[slave].port_state[port]; 282 } 283 EXPORT_SYMBOL(mlx4_get_slave_port_state); 284 285 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, 286 enum slave_port_state state) 287 { 288 struct mlx4_priv *priv = mlx4_priv(dev); 289 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 290 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 291 292 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 293 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 294 pr_err("%s: Error: asking for slave:%d, port:%d\n", 295 __func__, slave, port); 296 return -1; 297 } 298 s_state[slave].port_state[port] = state; 299 300 return 0; 301 } 302 303 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event) 304 { 305 int i; 306 enum slave_port_gen_event gen_event; 307 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev, 308 port); 309 310 for (i = 0; i < dev->num_vfs + 1; i++) 311 if (test_bit(i, slaves_pport.slaves)) 312 set_and_calc_slave_port_state(dev, i, port, 313 event, &gen_event); 314 } 315 /************************************************************************** 316 The function get as input the new event to that port, 317 and according to the prev state change the slave's port state. 318 The events are: 319 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 320 MLX4_PORT_STATE_DEV_EVENT_PORT_UP 321 MLX4_PORT_STATE_IB_EVENT_GID_VALID 322 MLX4_PORT_STATE_IB_EVENT_GID_INVALID 323 ***************************************************************************/ 324 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, 325 u8 port, int event, 326 enum slave_port_gen_event *gen_event) 327 { 328 struct mlx4_priv *priv = mlx4_priv(dev); 329 struct mlx4_slave_state *ctx = NULL; 330 unsigned long flags; 331 int ret = -1; 332 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 333 enum slave_port_state cur_state = 334 mlx4_get_slave_port_state(dev, slave, port); 335 336 *gen_event = SLAVE_PORT_GEN_EVENT_NONE; 337 338 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 339 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 340 pr_err("%s: Error: asking for slave:%d, port:%d\n", 341 __func__, slave, port); 342 return ret; 343 } 344 345 ctx = &priv->mfunc.master.slave_state[slave]; 346 spin_lock_irqsave(&ctx->lock, flags); 347 348 switch (cur_state) { 349 case SLAVE_PORT_DOWN: 350 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event) 351 mlx4_set_slave_port_state(dev, slave, port, 352 SLAVE_PENDING_UP); 353 break; 354 case SLAVE_PENDING_UP: 355 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) 356 mlx4_set_slave_port_state(dev, slave, port, 357 SLAVE_PORT_DOWN); 358 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) { 359 mlx4_set_slave_port_state(dev, slave, port, 360 SLAVE_PORT_UP); 361 *gen_event = SLAVE_PORT_GEN_EVENT_UP; 362 } 363 break; 364 case SLAVE_PORT_UP: 365 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) { 366 mlx4_set_slave_port_state(dev, slave, port, 367 SLAVE_PORT_DOWN); 368 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 369 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID == 370 event) { 371 mlx4_set_slave_port_state(dev, slave, port, 372 SLAVE_PENDING_UP); 373 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 374 } 375 break; 376 default: 377 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n", 378 __func__, slave, port); 379 goto out; 380 } 381 ret = mlx4_get_slave_port_state(dev, slave, port); 382 383 out: 384 spin_unlock_irqrestore(&ctx->lock, flags); 385 return ret; 386 } 387 388 EXPORT_SYMBOL(set_and_calc_slave_port_state); 389 390 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr) 391 { 392 struct mlx4_eqe eqe; 393 394 memset(&eqe, 0, sizeof eqe); 395 396 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 397 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO; 398 eqe.event.port_mgmt_change.port = port; 399 eqe.event.port_mgmt_change.params.port_info.changed_attr = 400 cpu_to_be32((u32) attr); 401 402 slave_event(dev, ALL_SLAVES, &eqe); 403 return 0; 404 } 405 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev); 406 407 void mlx4_master_handle_slave_flr(struct work_struct *work) 408 { 409 struct mlx4_mfunc_master_ctx *master = 410 container_of(work, struct mlx4_mfunc_master_ctx, 411 slave_flr_event_work); 412 struct mlx4_mfunc *mfunc = 413 container_of(master, struct mlx4_mfunc, master); 414 struct mlx4_priv *priv = 415 container_of(mfunc, struct mlx4_priv, mfunc); 416 struct mlx4_dev *dev = &priv->dev; 417 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 418 int i; 419 int err; 420 unsigned long flags; 421 422 mlx4_dbg(dev, "mlx4_handle_slave_flr\n"); 423 424 for (i = 0 ; i < dev->num_slaves; i++) { 425 426 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) { 427 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n", 428 i); 429 430 mlx4_delete_all_resources_for_slave(dev, i); 431 /*return the slave to running mode*/ 432 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 433 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET; 434 slave_state[i].is_slave_going_down = 0; 435 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 436 /*notify the FW:*/ 437 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE, 438 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 439 if (err) 440 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n", 441 i); 442 } 443 } 444 } 445 446 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq) 447 { 448 struct mlx4_priv *priv = mlx4_priv(dev); 449 struct mlx4_eqe *eqe; 450 int cqn; 451 int eqes_found = 0; 452 int set_ci = 0; 453 int port; 454 int slave = 0; 455 int ret; 456 u32 flr_slave; 457 u8 update_slave_state; 458 int i; 459 enum slave_port_gen_event gen_event; 460 unsigned long flags; 461 struct mlx4_vport_state *s_info; 462 463 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor))) { 464 /* 465 * Make sure we read EQ entry contents after we've 466 * checked the ownership bit. 467 */ 468 rmb(); 469 470 switch (eqe->type) { 471 case MLX4_EVENT_TYPE_COMP: 472 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 473 mlx4_cq_completion(dev, cqn); 474 break; 475 476 case MLX4_EVENT_TYPE_PATH_MIG: 477 case MLX4_EVENT_TYPE_COMM_EST: 478 case MLX4_EVENT_TYPE_SQ_DRAINED: 479 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 480 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 481 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 482 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 483 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 484 mlx4_dbg(dev, "event %d arrived\n", eqe->type); 485 if (mlx4_is_master(dev)) { 486 /* forward only to slave owning the QP */ 487 ret = mlx4_get_slave_from_resource_id(dev, 488 RES_QP, 489 be32_to_cpu(eqe->event.qp.qpn) 490 & 0xffffff, &slave); 491 if (ret && ret != -ENOENT) { 492 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 493 eqe->type, eqe->subtype, 494 eq->eqn, eq->cons_index, ret); 495 break; 496 } 497 498 if (!ret && slave != dev->caps.function) { 499 mlx4_slave_event(dev, slave, eqe); 500 break; 501 } 502 503 } 504 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 505 0xffffff, eqe->type); 506 break; 507 508 case MLX4_EVENT_TYPE_SRQ_LIMIT: 509 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n", 510 __func__); 511 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR: 512 if (mlx4_is_master(dev)) { 513 /* forward only to slave owning the SRQ */ 514 ret = mlx4_get_slave_from_resource_id(dev, 515 RES_SRQ, 516 be32_to_cpu(eqe->event.srq.srqn) 517 & 0xffffff, 518 &slave); 519 if (ret && ret != -ENOENT) { 520 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 521 eqe->type, eqe->subtype, 522 eq->eqn, eq->cons_index, ret); 523 break; 524 } 525 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n", 526 __func__, slave, 527 be32_to_cpu(eqe->event.srq.srqn), 528 eqe->type, eqe->subtype); 529 530 if (!ret && slave != dev->caps.function) { 531 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n", 532 __func__, eqe->type, 533 eqe->subtype, slave); 534 mlx4_slave_event(dev, slave, eqe); 535 break; 536 } 537 } 538 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 539 0xffffff, eqe->type); 540 break; 541 542 case MLX4_EVENT_TYPE_CMD: 543 mlx4_cmd_event(dev, 544 be16_to_cpu(eqe->event.cmd.token), 545 eqe->event.cmd.status, 546 be64_to_cpu(eqe->event.cmd.out_param)); 547 break; 548 549 case MLX4_EVENT_TYPE_PORT_CHANGE: { 550 struct mlx4_slaves_pport slaves_port; 551 port = be32_to_cpu(eqe->event.port_change.port) >> 28; 552 slaves_port = mlx4_phys_to_slaves_pport(dev, port); 553 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) { 554 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN, 555 port); 556 mlx4_priv(dev)->sense.do_sense_port[port] = 1; 557 if (!mlx4_is_master(dev)) 558 break; 559 for (i = 0; i < dev->num_vfs + 1; i++) { 560 if (!test_bit(i, slaves_port.slaves)) 561 continue; 562 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { 563 if (i == mlx4_master_func_num(dev)) 564 continue; 565 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n", 566 __func__, i, port); 567 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state; 568 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 569 eqe->event.port_change.port = 570 cpu_to_be32( 571 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 572 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 573 mlx4_slave_event(dev, i, eqe); 574 } 575 } else { /* IB port */ 576 set_and_calc_slave_port_state(dev, i, port, 577 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 578 &gen_event); 579 /*we can be in pending state, then do not send port_down event*/ 580 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) { 581 if (i == mlx4_master_func_num(dev)) 582 continue; 583 mlx4_slave_event(dev, i, eqe); 584 } 585 } 586 } 587 } else { 588 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port); 589 590 mlx4_priv(dev)->sense.do_sense_port[port] = 0; 591 592 if (!mlx4_is_master(dev)) 593 break; 594 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 595 for (i = 0; i < dev->num_vfs + 1; i++) { 596 if (!test_bit(i, slaves_port.slaves)) 597 continue; 598 if (i == mlx4_master_func_num(dev)) 599 continue; 600 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state; 601 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 602 eqe->event.port_change.port = 603 cpu_to_be32( 604 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 605 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 606 mlx4_slave_event(dev, i, eqe); 607 } 608 } 609 else /* IB port */ 610 /* port-up event will be sent to a slave when the 611 * slave's alias-guid is set. This is done in alias_GUID.c 612 */ 613 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP); 614 } 615 break; 616 } 617 618 case MLX4_EVENT_TYPE_CQ_ERROR: 619 mlx4_warn(dev, "CQ %s on CQN %06x\n", 620 eqe->event.cq_err.syndrome == 1 ? 621 "overrun" : "access violation", 622 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 623 if (mlx4_is_master(dev)) { 624 ret = mlx4_get_slave_from_resource_id(dev, 625 RES_CQ, 626 be32_to_cpu(eqe->event.cq_err.cqn) 627 & 0xffffff, &slave); 628 if (ret && ret != -ENOENT) { 629 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 630 eqe->type, eqe->subtype, 631 eq->eqn, eq->cons_index, ret); 632 break; 633 } 634 635 if (!ret && slave != dev->caps.function) { 636 mlx4_slave_event(dev, slave, eqe); 637 break; 638 } 639 } 640 mlx4_cq_event(dev, 641 be32_to_cpu(eqe->event.cq_err.cqn) 642 & 0xffffff, 643 eqe->type); 644 break; 645 646 case MLX4_EVENT_TYPE_EQ_OVERFLOW: 647 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); 648 break; 649 650 case MLX4_EVENT_TYPE_OP_REQUIRED: 651 atomic_inc(&priv->opreq_count); 652 /* FW commands can't be executed from interrupt context 653 * working in deferred task 654 */ 655 queue_work(mlx4_wq, &priv->opreq_task); 656 break; 657 658 case MLX4_EVENT_TYPE_COMM_CHANNEL: 659 if (!mlx4_is_master(dev)) { 660 mlx4_warn(dev, "Received comm channel event for non master device\n"); 661 break; 662 } 663 memcpy(&priv->mfunc.master.comm_arm_bit_vector, 664 eqe->event.comm_channel_arm.bit_vec, 665 sizeof eqe->event.comm_channel_arm.bit_vec); 666 queue_work(priv->mfunc.master.comm_wq, 667 &priv->mfunc.master.comm_work); 668 break; 669 670 case MLX4_EVENT_TYPE_FLR_EVENT: 671 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id); 672 if (!mlx4_is_master(dev)) { 673 mlx4_warn(dev, "Non-master function received FLR event\n"); 674 break; 675 } 676 677 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave); 678 679 if (flr_slave >= dev->num_slaves) { 680 mlx4_warn(dev, 681 "Got FLR for unknown function: %d\n", 682 flr_slave); 683 update_slave_state = 0; 684 } else 685 update_slave_state = 1; 686 687 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 688 if (update_slave_state) { 689 priv->mfunc.master.slave_state[flr_slave].active = false; 690 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR; 691 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1; 692 } 693 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 694 queue_work(priv->mfunc.master.comm_wq, 695 &priv->mfunc.master.slave_flr_event_work); 696 break; 697 698 case MLX4_EVENT_TYPE_FATAL_WARNING: 699 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) { 700 if (mlx4_is_master(dev)) 701 for (i = 0; i < dev->num_slaves; i++) { 702 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n", 703 __func__, i); 704 if (i == dev->caps.function) 705 continue; 706 mlx4_slave_event(dev, i, eqe); 707 } 708 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n", 709 be16_to_cpu(eqe->event.warming.warning_threshold), 710 be16_to_cpu(eqe->event.warming.current_temperature)); 711 } else 712 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 713 eqe->type, eqe->subtype, eq->eqn, 714 eq->cons_index, eqe->owner, eq->nent, 715 eqe->slave_id, 716 !!(eqe->owner & 0x80) ^ 717 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 718 719 break; 720 721 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT: 722 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE, 723 (unsigned long) eqe); 724 break; 725 726 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR: 727 case MLX4_EVENT_TYPE_ECC_DETECT: 728 default: 729 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 730 eqe->type, eqe->subtype, eq->eqn, 731 eq->cons_index, eqe->owner, eq->nent, 732 eqe->slave_id, 733 !!(eqe->owner & 0x80) ^ 734 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 735 break; 736 }; 737 738 ++eq->cons_index; 739 eqes_found = 1; 740 ++set_ci; 741 742 /* 743 * The HCA will think the queue has overflowed if we 744 * don't tell it we've been processing events. We 745 * create our EQs with MLX4_NUM_SPARE_EQE extra 746 * entries, so we must update our consumer index at 747 * least that often. 748 */ 749 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) { 750 eq_set_ci(eq, 0); 751 set_ci = 0; 752 } 753 } 754 755 eq_set_ci(eq, 1); 756 757 return eqes_found; 758 } 759 760 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr) 761 { 762 struct mlx4_dev *dev = dev_ptr; 763 struct mlx4_priv *priv = mlx4_priv(dev); 764 int work = 0; 765 int i; 766 767 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); 768 769 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 770 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); 771 772 return IRQ_RETVAL(work); 773 } 774 775 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr) 776 { 777 struct mlx4_eq *eq = eq_ptr; 778 struct mlx4_dev *dev = eq->dev; 779 780 mlx4_eq_int(dev, eq); 781 782 /* MSI-X vectors always belong to us */ 783 return IRQ_HANDLED; 784 } 785 786 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 787 struct mlx4_vhcr *vhcr, 788 struct mlx4_cmd_mailbox *inbox, 789 struct mlx4_cmd_mailbox *outbox, 790 struct mlx4_cmd_info *cmd) 791 { 792 struct mlx4_priv *priv = mlx4_priv(dev); 793 struct mlx4_slave_event_eq_info *event_eq = 794 priv->mfunc.master.slave_state[slave].event_eq; 795 u32 in_modifier = vhcr->in_modifier; 796 u32 eqn = in_modifier & 0x3FF; 797 u64 in_param = vhcr->in_param; 798 int err = 0; 799 int i; 800 801 if (slave == dev->caps.function) 802 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn, 803 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 804 MLX4_CMD_NATIVE); 805 if (!err) 806 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) 807 if (in_param & (1LL << i)) 808 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn; 809 810 return err; 811 } 812 813 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap, 814 int eq_num) 815 { 816 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num, 817 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 818 MLX4_CMD_WRAPPED); 819 } 820 821 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 822 int eq_num) 823 { 824 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, 825 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A, 826 MLX4_CMD_WRAPPED); 827 } 828 829 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 830 int eq_num) 831 { 832 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 833 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A, 834 MLX4_CMD_WRAPPED); 835 } 836 837 static int mlx4_num_eq_uar(struct mlx4_dev *dev) 838 { 839 /* 840 * Each UAR holds 4 EQ doorbells. To figure out how many UARs 841 * we need to map, take the difference of highest index and 842 * the lowest index we'll use and add 1. 843 */ 844 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs + 845 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1; 846 } 847 848 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq) 849 { 850 struct mlx4_priv *priv = mlx4_priv(dev); 851 int index; 852 853 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4; 854 855 if (!priv->eq_table.uar_map[index]) { 856 priv->eq_table.uar_map[index] = 857 ioremap(pci_resource_start(dev->pdev, 2) + 858 ((eq->eqn / 4) << PAGE_SHIFT), 859 PAGE_SIZE); 860 if (!priv->eq_table.uar_map[index]) { 861 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n", 862 eq->eqn); 863 return NULL; 864 } 865 } 866 867 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4); 868 } 869 870 static void mlx4_unmap_uar(struct mlx4_dev *dev) 871 { 872 struct mlx4_priv *priv = mlx4_priv(dev); 873 int i; 874 875 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 876 if (priv->eq_table.uar_map[i]) { 877 iounmap(priv->eq_table.uar_map[i]); 878 priv->eq_table.uar_map[i] = NULL; 879 } 880 } 881 882 static int mlx4_create_eq(struct mlx4_dev *dev, int nent, 883 u8 intr, struct mlx4_eq *eq) 884 { 885 struct mlx4_priv *priv = mlx4_priv(dev); 886 struct mlx4_cmd_mailbox *mailbox; 887 struct mlx4_eq_context *eq_context; 888 int npages; 889 u64 *dma_list = NULL; 890 dma_addr_t t; 891 u64 mtt_addr; 892 int err = -ENOMEM; 893 int i; 894 895 eq->dev = dev; 896 eq->nent = roundup_pow_of_two(max(nent, 2)); 897 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */ 898 npages = PAGE_ALIGN(eq->nent * (MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor)) / PAGE_SIZE; 899 900 eq->page_list = kmalloc(npages * sizeof *eq->page_list, 901 GFP_KERNEL); 902 if (!eq->page_list) 903 goto err_out; 904 905 for (i = 0; i < npages; ++i) 906 eq->page_list[i].buf = NULL; 907 908 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); 909 if (!dma_list) 910 goto err_out_free; 911 912 mailbox = mlx4_alloc_cmd_mailbox(dev); 913 if (IS_ERR(mailbox)) 914 goto err_out_free; 915 eq_context = mailbox->buf; 916 917 for (i = 0; i < npages; ++i) { 918 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev, 919 PAGE_SIZE, &t, GFP_KERNEL); 920 if (!eq->page_list[i].buf) 921 goto err_out_free_pages; 922 923 dma_list[i] = t; 924 eq->page_list[i].map = t; 925 926 memset(eq->page_list[i].buf, 0, PAGE_SIZE); 927 } 928 929 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap); 930 if (eq->eqn == -1) 931 goto err_out_free_pages; 932 933 eq->doorbell = mlx4_get_eq_uar(dev, eq); 934 if (!eq->doorbell) { 935 err = -ENOMEM; 936 goto err_out_free_eq; 937 } 938 939 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt); 940 if (err) 941 goto err_out_free_eq; 942 943 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list); 944 if (err) 945 goto err_out_free_mtt; 946 947 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | 948 MLX4_EQ_STATE_ARMED); 949 eq_context->log_eq_size = ilog2(eq->nent); 950 eq_context->intr = intr; 951 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT; 952 953 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt); 954 eq_context->mtt_base_addr_h = mtt_addr >> 32; 955 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 956 957 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn); 958 if (err) { 959 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err); 960 goto err_out_free_mtt; 961 } 962 963 kfree(dma_list); 964 mlx4_free_cmd_mailbox(dev, mailbox); 965 966 eq->cons_index = 0; 967 968 return err; 969 970 err_out_free_mtt: 971 mlx4_mtt_cleanup(dev, &eq->mtt); 972 973 err_out_free_eq: 974 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 975 976 err_out_free_pages: 977 for (i = 0; i < npages; ++i) 978 if (eq->page_list[i].buf) 979 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, 980 eq->page_list[i].buf, 981 eq->page_list[i].map); 982 983 mlx4_free_cmd_mailbox(dev, mailbox); 984 985 err_out_free: 986 kfree(eq->page_list); 987 kfree(dma_list); 988 989 err_out: 990 return err; 991 } 992 993 static void mlx4_free_eq(struct mlx4_dev *dev, 994 struct mlx4_eq *eq) 995 { 996 struct mlx4_priv *priv = mlx4_priv(dev); 997 struct mlx4_cmd_mailbox *mailbox; 998 int err; 999 int i; 1000 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */ 1001 int npages = PAGE_ALIGN((MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor) * eq->nent) / PAGE_SIZE; 1002 1003 mailbox = mlx4_alloc_cmd_mailbox(dev); 1004 if (IS_ERR(mailbox)) 1005 return; 1006 1007 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn); 1008 if (err) 1009 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err); 1010 1011 if (0) { 1012 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn); 1013 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) { 1014 if (i % 4 == 0) 1015 pr_cont("[%02x] ", i * 4); 1016 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4)); 1017 if ((i + 1) % 4 == 0) 1018 pr_cont("\n"); 1019 } 1020 } 1021 1022 mlx4_mtt_cleanup(dev, &eq->mtt); 1023 for (i = 0; i < npages; ++i) 1024 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, 1025 eq->page_list[i].buf, 1026 eq->page_list[i].map); 1027 1028 kfree(eq->page_list); 1029 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1030 mlx4_free_cmd_mailbox(dev, mailbox); 1031 } 1032 1033 static void mlx4_free_irqs(struct mlx4_dev *dev) 1034 { 1035 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table; 1036 struct mlx4_priv *priv = mlx4_priv(dev); 1037 int i, vec; 1038 1039 if (eq_table->have_irq) 1040 free_irq(dev->pdev->irq, dev); 1041 1042 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1043 if (eq_table->eq[i].have_irq) { 1044 free_irq(eq_table->eq[i].irq, eq_table->eq + i); 1045 eq_table->eq[i].have_irq = 0; 1046 } 1047 1048 for (i = 0; i < dev->caps.comp_pool; i++) { 1049 /* 1050 * Freeing the assigned irq's 1051 * all bits should be 0, but we need to validate 1052 */ 1053 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1054 /* NO need protecting*/ 1055 vec = dev->caps.num_comp_vectors + 1 + i; 1056 free_irq(priv->eq_table.eq[vec].irq, 1057 &priv->eq_table.eq[vec]); 1058 } 1059 } 1060 1061 1062 kfree(eq_table->irq_names); 1063 } 1064 1065 static int mlx4_map_clr_int(struct mlx4_dev *dev) 1066 { 1067 struct mlx4_priv *priv = mlx4_priv(dev); 1068 1069 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) + 1070 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE); 1071 if (!priv->clr_base) { 1072 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n"); 1073 return -ENOMEM; 1074 } 1075 1076 return 0; 1077 } 1078 1079 static void mlx4_unmap_clr_int(struct mlx4_dev *dev) 1080 { 1081 struct mlx4_priv *priv = mlx4_priv(dev); 1082 1083 iounmap(priv->clr_base); 1084 } 1085 1086 int mlx4_alloc_eq_table(struct mlx4_dev *dev) 1087 { 1088 struct mlx4_priv *priv = mlx4_priv(dev); 1089 1090 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs, 1091 sizeof *priv->eq_table.eq, GFP_KERNEL); 1092 if (!priv->eq_table.eq) 1093 return -ENOMEM; 1094 1095 return 0; 1096 } 1097 1098 void mlx4_free_eq_table(struct mlx4_dev *dev) 1099 { 1100 kfree(mlx4_priv(dev)->eq_table.eq); 1101 } 1102 1103 int mlx4_init_eq_table(struct mlx4_dev *dev) 1104 { 1105 struct mlx4_priv *priv = mlx4_priv(dev); 1106 int err; 1107 int i; 1108 1109 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev), 1110 sizeof *priv->eq_table.uar_map, 1111 GFP_KERNEL); 1112 if (!priv->eq_table.uar_map) { 1113 err = -ENOMEM; 1114 goto err_out_free; 1115 } 1116 1117 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs, 1118 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0); 1119 if (err) 1120 goto err_out_free; 1121 1122 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 1123 priv->eq_table.uar_map[i] = NULL; 1124 1125 if (!mlx4_is_slave(dev)) { 1126 err = mlx4_map_clr_int(dev); 1127 if (err) 1128 goto err_out_bitmap; 1129 1130 priv->eq_table.clr_mask = 1131 swab32(1 << (priv->eq_table.inta_pin & 31)); 1132 priv->eq_table.clr_int = priv->clr_base + 1133 (priv->eq_table.inta_pin < 32 ? 4 : 0); 1134 } 1135 1136 priv->eq_table.irq_names = 1137 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 + 1138 dev->caps.comp_pool), 1139 GFP_KERNEL); 1140 if (!priv->eq_table.irq_names) { 1141 err = -ENOMEM; 1142 goto err_out_bitmap; 1143 } 1144 1145 for (i = 0; i < dev->caps.num_comp_vectors; ++i) { 1146 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1147 dev->caps.reserved_cqs + 1148 MLX4_NUM_SPARE_EQE, 1149 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0, 1150 &priv->eq_table.eq[i]); 1151 if (err) { 1152 --i; 1153 goto err_out_unmap; 1154 } 1155 } 1156 1157 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE, 1158 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0, 1159 &priv->eq_table.eq[dev->caps.num_comp_vectors]); 1160 if (err) 1161 goto err_out_comp; 1162 1163 /*if additional completion vectors poolsize is 0 this loop will not run*/ 1164 for (i = dev->caps.num_comp_vectors + 1; 1165 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) { 1166 1167 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1168 dev->caps.reserved_cqs + 1169 MLX4_NUM_SPARE_EQE, 1170 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0, 1171 &priv->eq_table.eq[i]); 1172 if (err) { 1173 --i; 1174 goto err_out_unmap; 1175 } 1176 } 1177 1178 1179 if (dev->flags & MLX4_FLAG_MSI_X) { 1180 const char *eq_name; 1181 1182 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) { 1183 if (i < dev->caps.num_comp_vectors) { 1184 snprintf(priv->eq_table.irq_names + 1185 i * MLX4_IRQNAME_SIZE, 1186 MLX4_IRQNAME_SIZE, 1187 "mlx4-comp-%d@pci:%s", i, 1188 pci_name(dev->pdev)); 1189 } else { 1190 snprintf(priv->eq_table.irq_names + 1191 i * MLX4_IRQNAME_SIZE, 1192 MLX4_IRQNAME_SIZE, 1193 "mlx4-async@pci:%s", 1194 pci_name(dev->pdev)); 1195 } 1196 1197 eq_name = priv->eq_table.irq_names + 1198 i * MLX4_IRQNAME_SIZE; 1199 err = request_irq(priv->eq_table.eq[i].irq, 1200 mlx4_msi_x_interrupt, 0, eq_name, 1201 priv->eq_table.eq + i); 1202 if (err) 1203 goto err_out_async; 1204 1205 priv->eq_table.eq[i].have_irq = 1; 1206 } 1207 } else { 1208 snprintf(priv->eq_table.irq_names, 1209 MLX4_IRQNAME_SIZE, 1210 DRV_NAME "@pci:%s", 1211 pci_name(dev->pdev)); 1212 err = request_irq(dev->pdev->irq, mlx4_interrupt, 1213 IRQF_SHARED, priv->eq_table.irq_names, dev); 1214 if (err) 1215 goto err_out_async; 1216 1217 priv->eq_table.have_irq = 1; 1218 } 1219 1220 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1221 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1222 if (err) 1223 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", 1224 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err); 1225 1226 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1227 eq_set_ci(&priv->eq_table.eq[i], 1); 1228 1229 return 0; 1230 1231 err_out_async: 1232 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]); 1233 1234 err_out_comp: 1235 i = dev->caps.num_comp_vectors - 1; 1236 1237 err_out_unmap: 1238 while (i >= 0) { 1239 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1240 --i; 1241 } 1242 if (!mlx4_is_slave(dev)) 1243 mlx4_unmap_clr_int(dev); 1244 mlx4_free_irqs(dev); 1245 1246 err_out_bitmap: 1247 mlx4_unmap_uar(dev); 1248 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1249 1250 err_out_free: 1251 kfree(priv->eq_table.uar_map); 1252 1253 return err; 1254 } 1255 1256 void mlx4_cleanup_eq_table(struct mlx4_dev *dev) 1257 { 1258 struct mlx4_priv *priv = mlx4_priv(dev); 1259 int i; 1260 1261 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1, 1262 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1263 1264 mlx4_free_irqs(dev); 1265 1266 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) 1267 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1268 1269 if (!mlx4_is_slave(dev)) 1270 mlx4_unmap_clr_int(dev); 1271 1272 mlx4_unmap_uar(dev); 1273 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1274 1275 kfree(priv->eq_table.uar_map); 1276 } 1277 1278 /* A test that verifies that we can accept interrupts on all 1279 * the irq vectors of the device. 1280 * Interrupts are checked using the NOP command. 1281 */ 1282 int mlx4_test_interrupts(struct mlx4_dev *dev) 1283 { 1284 struct mlx4_priv *priv = mlx4_priv(dev); 1285 int i; 1286 int err; 1287 1288 err = mlx4_NOP(dev); 1289 /* When not in MSI_X, there is only one irq to check */ 1290 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev)) 1291 return err; 1292 1293 /* A loop over all completion vectors, for each vector we will check 1294 * whether it works by mapping command completions to that vector 1295 * and performing a NOP command 1296 */ 1297 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) { 1298 /* Temporary use polling for command completions */ 1299 mlx4_cmd_use_polling(dev); 1300 1301 /* Map the new eq to handle all asynchronous events */ 1302 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1303 priv->eq_table.eq[i].eqn); 1304 if (err) { 1305 mlx4_warn(dev, "Failed mapping eq for interrupt test\n"); 1306 mlx4_cmd_use_events(dev); 1307 break; 1308 } 1309 1310 /* Go back to using events */ 1311 mlx4_cmd_use_events(dev); 1312 err = mlx4_NOP(dev); 1313 } 1314 1315 /* Return to default */ 1316 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1317 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1318 return err; 1319 } 1320 EXPORT_SYMBOL(mlx4_test_interrupts); 1321 1322 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 1323 int *vector) 1324 { 1325 1326 struct mlx4_priv *priv = mlx4_priv(dev); 1327 int vec = 0, err = 0, i; 1328 1329 mutex_lock(&priv->msix_ctl.pool_lock); 1330 for (i = 0; !vec && i < dev->caps.comp_pool; i++) { 1331 if (~priv->msix_ctl.pool_bm & 1ULL << i) { 1332 priv->msix_ctl.pool_bm |= 1ULL << i; 1333 vec = dev->caps.num_comp_vectors + 1 + i; 1334 snprintf(priv->eq_table.irq_names + 1335 vec * MLX4_IRQNAME_SIZE, 1336 MLX4_IRQNAME_SIZE, "%s", name); 1337 #ifdef CONFIG_RFS_ACCEL 1338 if (rmap) { 1339 err = irq_cpu_rmap_add(rmap, 1340 priv->eq_table.eq[vec].irq); 1341 if (err) 1342 mlx4_warn(dev, "Failed adding irq rmap\n"); 1343 } 1344 #endif 1345 err = request_irq(priv->eq_table.eq[vec].irq, 1346 mlx4_msi_x_interrupt, 0, 1347 &priv->eq_table.irq_names[vec<<5], 1348 priv->eq_table.eq + vec); 1349 if (err) { 1350 /*zero out bit by fliping it*/ 1351 priv->msix_ctl.pool_bm ^= 1 << i; 1352 vec = 0; 1353 continue; 1354 /*we dont want to break here*/ 1355 } 1356 1357 eq_set_ci(&priv->eq_table.eq[vec], 1); 1358 } 1359 } 1360 mutex_unlock(&priv->msix_ctl.pool_lock); 1361 1362 if (vec) { 1363 *vector = vec; 1364 } else { 1365 *vector = 0; 1366 err = (i == dev->caps.comp_pool) ? -ENOSPC : err; 1367 } 1368 return err; 1369 } 1370 EXPORT_SYMBOL(mlx4_assign_eq); 1371 1372 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec) 1373 { 1374 struct mlx4_priv *priv = mlx4_priv(dev); 1375 1376 return priv->eq_table.eq[vec].irq; 1377 } 1378 EXPORT_SYMBOL(mlx4_eq_get_irq); 1379 1380 void mlx4_release_eq(struct mlx4_dev *dev, int vec) 1381 { 1382 struct mlx4_priv *priv = mlx4_priv(dev); 1383 /*bm index*/ 1384 int i = vec - dev->caps.num_comp_vectors - 1; 1385 1386 if (likely(i >= 0)) { 1387 /*sanity check , making sure were not trying to free irq's 1388 Belonging to a legacy EQ*/ 1389 mutex_lock(&priv->msix_ctl.pool_lock); 1390 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1391 free_irq(priv->eq_table.eq[vec].irq, 1392 &priv->eq_table.eq[vec]); 1393 priv->msix_ctl.pool_bm &= ~(1ULL << i); 1394 } 1395 mutex_unlock(&priv->msix_ctl.pool_lock); 1396 } 1397 1398 } 1399 EXPORT_SYMBOL(mlx4_release_eq); 1400 1401