1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/prefetch.h> 41 #include <linux/vmalloc.h> 42 #include <linux/tcp.h> 43 #include <linux/ip.h> 44 #include <linux/moduleparam.h> 45 46 #include "mlx4_en.h" 47 48 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 49 struct mlx4_en_tx_ring **pring, u32 size, 50 u16 stride, int node, int queue_index) 51 { 52 struct mlx4_en_dev *mdev = priv->mdev; 53 struct mlx4_en_tx_ring *ring; 54 int tmp; 55 int err; 56 57 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 58 if (!ring) { 59 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 60 if (!ring) { 61 en_err(priv, "Failed allocating TX ring\n"); 62 return -ENOMEM; 63 } 64 } 65 66 ring->size = size; 67 ring->size_mask = size - 1; 68 ring->stride = stride; 69 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; 70 71 tmp = size * sizeof(struct mlx4_en_tx_info); 72 ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node); 73 if (!ring->tx_info) { 74 ring->tx_info = vmalloc(tmp); 75 if (!ring->tx_info) { 76 err = -ENOMEM; 77 goto err_ring; 78 } 79 } 80 81 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 82 ring->tx_info, tmp); 83 84 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 85 if (!ring->bounce_buf) { 86 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 87 if (!ring->bounce_buf) { 88 err = -ENOMEM; 89 goto err_info; 90 } 91 } 92 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); 93 94 /* Allocate HW buffers on provided NUMA node */ 95 set_dev_node(&mdev->dev->persist->pdev->dev, node); 96 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, 97 2 * PAGE_SIZE); 98 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 99 if (err) { 100 en_err(priv, "Failed allocating hwq resources\n"); 101 goto err_bounce; 102 } 103 104 err = mlx4_en_map_buffer(&ring->wqres.buf); 105 if (err) { 106 en_err(priv, "Failed to map TX buffer\n"); 107 goto err_hwq_res; 108 } 109 110 ring->buf = ring->wqres.buf.direct.buf; 111 112 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", 113 ring, ring->buf, ring->size, ring->buf_size, 114 (unsigned long long) ring->wqres.buf.direct.map); 115 116 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, 117 MLX4_RESERVE_ETH_BF_QP); 118 if (err) { 119 en_err(priv, "failed reserving qp for TX ring\n"); 120 goto err_map; 121 } 122 123 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL); 124 if (err) { 125 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 126 goto err_reserve; 127 } 128 ring->qp.event = mlx4_en_sqp_event; 129 130 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 131 if (err) { 132 en_dbg(DRV, priv, "working without blueflame (%d)\n", err); 133 ring->bf.uar = &mdev->priv_uar; 134 ring->bf.uar->map = mdev->uar_map; 135 ring->bf_enabled = false; 136 ring->bf_alloced = false; 137 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 138 } else { 139 ring->bf_alloced = true; 140 ring->bf_enabled = !!(priv->pflags & 141 MLX4_EN_PRIV_FLAGS_BLUEFLAME); 142 } 143 144 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 145 ring->queue_index = queue_index; 146 147 if (queue_index < priv->num_tx_rings_p_up) 148 cpumask_set_cpu(cpumask_local_spread(queue_index, 149 priv->mdev->dev->numa_node), 150 &ring->affinity_mask); 151 152 *pring = ring; 153 return 0; 154 155 err_reserve: 156 mlx4_qp_release_range(mdev->dev, ring->qpn, 1); 157 err_map: 158 mlx4_en_unmap_buffer(&ring->wqres.buf); 159 err_hwq_res: 160 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 161 err_bounce: 162 kfree(ring->bounce_buf); 163 ring->bounce_buf = NULL; 164 err_info: 165 kvfree(ring->tx_info); 166 ring->tx_info = NULL; 167 err_ring: 168 kfree(ring); 169 *pring = NULL; 170 return err; 171 } 172 173 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 174 struct mlx4_en_tx_ring **pring) 175 { 176 struct mlx4_en_dev *mdev = priv->mdev; 177 struct mlx4_en_tx_ring *ring = *pring; 178 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 179 180 if (ring->bf_alloced) 181 mlx4_bf_free(mdev->dev, &ring->bf); 182 mlx4_qp_remove(mdev->dev, &ring->qp); 183 mlx4_qp_free(mdev->dev, &ring->qp); 184 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); 185 mlx4_en_unmap_buffer(&ring->wqres.buf); 186 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 187 kfree(ring->bounce_buf); 188 ring->bounce_buf = NULL; 189 kvfree(ring->tx_info); 190 ring->tx_info = NULL; 191 kfree(ring); 192 *pring = NULL; 193 } 194 195 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 196 struct mlx4_en_tx_ring *ring, 197 int cq, int user_prio) 198 { 199 struct mlx4_en_dev *mdev = priv->mdev; 200 int err; 201 202 ring->cqn = cq; 203 ring->prod = 0; 204 ring->cons = 0xffffffff; 205 ring->last_nr_txbb = 1; 206 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 207 memset(ring->buf, 0, ring->buf_size); 208 209 ring->qp_state = MLX4_QP_STATE_RST; 210 ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8); 211 ring->mr_key = cpu_to_be32(mdev->mr.key); 212 213 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, 214 ring->cqn, user_prio, &ring->context); 215 if (ring->bf_alloced) 216 ring->context.usr_page = 217 cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, 218 ring->bf.uar->index)); 219 220 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, 221 &ring->qp, &ring->qp_state); 222 if (!cpumask_empty(&ring->affinity_mask)) 223 netif_set_xps_queue(priv->dev, &ring->affinity_mask, 224 ring->queue_index); 225 226 return err; 227 } 228 229 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 230 struct mlx4_en_tx_ring *ring) 231 { 232 struct mlx4_en_dev *mdev = priv->mdev; 233 234 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, 235 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); 236 } 237 238 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) 239 { 240 return ring->prod - ring->cons > ring->full_size; 241 } 242 243 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 244 struct mlx4_en_tx_ring *ring, int index, 245 u8 owner) 246 { 247 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 248 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 249 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 250 void *end = ring->buf + ring->buf_size; 251 __be32 *ptr = (__be32 *)tx_desc; 252 int i; 253 254 /* Optimize the common case when there are no wraparounds */ 255 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 256 /* Stamp the freed descriptor */ 257 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 258 i += STAMP_STRIDE) { 259 *ptr = stamp; 260 ptr += STAMP_DWORDS; 261 } 262 } else { 263 /* Stamp the freed descriptor */ 264 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 265 i += STAMP_STRIDE) { 266 *ptr = stamp; 267 ptr += STAMP_DWORDS; 268 if ((void *)ptr >= end) { 269 ptr = ring->buf; 270 stamp ^= cpu_to_be32(0x80000000); 271 } 272 } 273 } 274 } 275 276 277 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 278 struct mlx4_en_tx_ring *ring, 279 int index, u8 owner, u64 timestamp, 280 int napi_mode) 281 { 282 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 283 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 284 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 285 void *end = ring->buf + ring->buf_size; 286 struct sk_buff *skb = tx_info->skb; 287 int nr_maps = tx_info->nr_maps; 288 int i; 289 290 /* We do not touch skb here, so prefetch skb->users location 291 * to speedup consume_skb() 292 */ 293 prefetchw(&skb->users); 294 295 if (unlikely(timestamp)) { 296 struct skb_shared_hwtstamps hwts; 297 298 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); 299 skb_tstamp_tx(skb, &hwts); 300 } 301 302 /* Optimize the common case when there are no wraparounds */ 303 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 304 if (!tx_info->inl) { 305 if (tx_info->linear) 306 dma_unmap_single(priv->ddev, 307 tx_info->map0_dma, 308 tx_info->map0_byte_count, 309 PCI_DMA_TODEVICE); 310 else 311 dma_unmap_page(priv->ddev, 312 tx_info->map0_dma, 313 tx_info->map0_byte_count, 314 PCI_DMA_TODEVICE); 315 for (i = 1; i < nr_maps; i++) { 316 data++; 317 dma_unmap_page(priv->ddev, 318 (dma_addr_t)be64_to_cpu(data->addr), 319 be32_to_cpu(data->byte_count), 320 PCI_DMA_TODEVICE); 321 } 322 } 323 } else { 324 if (!tx_info->inl) { 325 if ((void *) data >= end) { 326 data = ring->buf + ((void *)data - end); 327 } 328 329 if (tx_info->linear) 330 dma_unmap_single(priv->ddev, 331 tx_info->map0_dma, 332 tx_info->map0_byte_count, 333 PCI_DMA_TODEVICE); 334 else 335 dma_unmap_page(priv->ddev, 336 tx_info->map0_dma, 337 tx_info->map0_byte_count, 338 PCI_DMA_TODEVICE); 339 for (i = 1; i < nr_maps; i++) { 340 data++; 341 /* Check for wraparound before unmapping */ 342 if ((void *) data >= end) 343 data = ring->buf; 344 dma_unmap_page(priv->ddev, 345 (dma_addr_t)be64_to_cpu(data->addr), 346 be32_to_cpu(data->byte_count), 347 PCI_DMA_TODEVICE); 348 } 349 } 350 } 351 napi_consume_skb(skb, napi_mode); 352 353 return tx_info->nr_txbb; 354 } 355 356 357 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 358 { 359 struct mlx4_en_priv *priv = netdev_priv(dev); 360 int cnt = 0; 361 362 /* Skip last polled descriptor */ 363 ring->cons += ring->last_nr_txbb; 364 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 365 ring->cons, ring->prod); 366 367 if ((u32) (ring->prod - ring->cons) > ring->size) { 368 if (netif_msg_tx_err(priv)) 369 en_warn(priv, "Tx consumer passed producer!\n"); 370 return 0; 371 } 372 373 while (ring->cons != ring->prod) { 374 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, 375 ring->cons & ring->size_mask, 376 !!(ring->cons & ring->size), 0, 377 0 /* Non-NAPI caller */); 378 ring->cons += ring->last_nr_txbb; 379 cnt++; 380 } 381 382 netdev_tx_reset_queue(ring->tx_queue); 383 384 if (cnt) 385 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 386 387 return cnt; 388 } 389 390 static bool mlx4_en_process_tx_cq(struct net_device *dev, 391 struct mlx4_en_cq *cq, int napi_budget) 392 { 393 struct mlx4_en_priv *priv = netdev_priv(dev); 394 struct mlx4_cq *mcq = &cq->mcq; 395 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; 396 struct mlx4_cqe *cqe; 397 u16 index; 398 u16 new_index, ring_index, stamp_index; 399 u32 txbbs_skipped = 0; 400 u32 txbbs_stamp = 0; 401 u32 cons_index = mcq->cons_index; 402 int size = cq->size; 403 u32 size_mask = ring->size_mask; 404 struct mlx4_cqe *buf = cq->buf; 405 u32 packets = 0; 406 u32 bytes = 0; 407 int factor = priv->cqe_factor; 408 u64 timestamp = 0; 409 int done = 0; 410 int budget = priv->tx_work_limit; 411 u32 last_nr_txbb; 412 u32 ring_cons; 413 414 if (!priv->port_up) 415 return true; 416 417 netdev_txq_bql_complete_prefetchw(ring->tx_queue); 418 419 index = cons_index & size_mask; 420 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 421 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); 422 ring_cons = ACCESS_ONCE(ring->cons); 423 ring_index = ring_cons & size_mask; 424 stamp_index = ring_index; 425 426 /* Process all completed CQEs */ 427 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 428 cons_index & size) && (done < budget)) { 429 /* 430 * make sure we read the CQE after we read the 431 * ownership bit 432 */ 433 dma_rmb(); 434 435 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 436 MLX4_CQE_OPCODE_ERROR)) { 437 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; 438 439 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", 440 cqe_err->vendor_err_syndrome, 441 cqe_err->syndrome); 442 } 443 444 /* Skip over last polled CQE */ 445 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 446 447 do { 448 txbbs_skipped += last_nr_txbb; 449 ring_index = (ring_index + last_nr_txbb) & size_mask; 450 if (ring->tx_info[ring_index].ts_requested) 451 timestamp = mlx4_en_get_cqe_ts(cqe); 452 453 /* free next descriptor */ 454 last_nr_txbb = mlx4_en_free_tx_desc( 455 priv, ring, ring_index, 456 !!((ring_cons + txbbs_skipped) & 457 ring->size), timestamp, napi_budget); 458 459 mlx4_en_stamp_wqe(priv, ring, stamp_index, 460 !!((ring_cons + txbbs_stamp) & 461 ring->size)); 462 stamp_index = ring_index; 463 txbbs_stamp = txbbs_skipped; 464 packets++; 465 bytes += ring->tx_info[ring_index].nr_bytes; 466 } while ((++done < budget) && (ring_index != new_index)); 467 468 ++cons_index; 469 index = cons_index & size_mask; 470 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 471 } 472 473 474 /* 475 * To prevent CQ overflow we first update CQ consumer and only then 476 * the ring consumer. 477 */ 478 mcq->cons_index = cons_index; 479 mlx4_cq_set_ci(mcq); 480 wmb(); 481 482 /* we want to dirty this cache line once */ 483 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; 484 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; 485 486 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 487 488 /* Wakeup Tx queue if this stopped, and ring is not full. 489 */ 490 if (netif_tx_queue_stopped(ring->tx_queue) && 491 !mlx4_en_is_tx_ring_full(ring)) { 492 netif_tx_wake_queue(ring->tx_queue); 493 ring->wake_queue++; 494 } 495 return done < budget; 496 } 497 498 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 499 { 500 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 501 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 502 503 if (likely(priv->port_up)) 504 napi_schedule_irqoff(&cq->napi); 505 else 506 mlx4_en_arm_cq(priv, cq); 507 } 508 509 /* TX CQ polling - called by NAPI */ 510 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) 511 { 512 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 513 struct net_device *dev = cq->dev; 514 struct mlx4_en_priv *priv = netdev_priv(dev); 515 int clean_complete; 516 517 clean_complete = mlx4_en_process_tx_cq(dev, cq, budget); 518 if (!clean_complete) 519 return budget; 520 521 napi_complete(napi); 522 mlx4_en_arm_cq(priv, cq); 523 524 return 0; 525 } 526 527 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 528 struct mlx4_en_tx_ring *ring, 529 u32 index, 530 unsigned int desc_size) 531 { 532 u32 copy = (ring->size - index) * TXBB_SIZE; 533 int i; 534 535 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 536 if ((i & (TXBB_SIZE - 1)) == 0) 537 wmb(); 538 539 *((u32 *) (ring->buf + i)) = 540 *((u32 *) (ring->bounce_buf + copy + i)); 541 } 542 543 for (i = copy - 4; i >= 4 ; i -= 4) { 544 if ((i & (TXBB_SIZE - 1)) == 0) 545 wmb(); 546 547 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = 548 *((u32 *) (ring->bounce_buf + i)); 549 } 550 551 /* Return real descriptor location */ 552 return ring->buf + index * TXBB_SIZE; 553 } 554 555 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping 556 * 557 * It seems strange we do not simply use skb_copy_bits(). 558 * This would allow to inline all skbs iff skb->len <= inline_thold 559 * 560 * Note that caller already checked skb was not a gso packet 561 */ 562 static bool is_inline(int inline_thold, const struct sk_buff *skb, 563 const struct skb_shared_info *shinfo, 564 void **pfrag) 565 { 566 void *ptr; 567 568 if (skb->len > inline_thold || !inline_thold) 569 return false; 570 571 if (shinfo->nr_frags == 1) { 572 ptr = skb_frag_address_safe(&shinfo->frags[0]); 573 if (unlikely(!ptr)) 574 return false; 575 *pfrag = ptr; 576 return true; 577 } 578 if (shinfo->nr_frags) 579 return false; 580 return true; 581 } 582 583 static int inline_size(const struct sk_buff *skb) 584 { 585 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 586 <= MLX4_INLINE_ALIGN) 587 return ALIGN(skb->len + CTRL_SIZE + 588 sizeof(struct mlx4_wqe_inline_seg), 16); 589 else 590 return ALIGN(skb->len + CTRL_SIZE + 2 * 591 sizeof(struct mlx4_wqe_inline_seg), 16); 592 } 593 594 static int get_real_size(const struct sk_buff *skb, 595 const struct skb_shared_info *shinfo, 596 struct net_device *dev, 597 int *lso_header_size, 598 bool *inline_ok, 599 void **pfrag) 600 { 601 struct mlx4_en_priv *priv = netdev_priv(dev); 602 int real_size; 603 604 if (shinfo->gso_size) { 605 *inline_ok = false; 606 if (skb->encapsulation) 607 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); 608 else 609 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 610 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + 611 ALIGN(*lso_header_size + 4, DS_SIZE); 612 if (unlikely(*lso_header_size != skb_headlen(skb))) { 613 /* We add a segment for the skb linear buffer only if 614 * it contains data */ 615 if (*lso_header_size < skb_headlen(skb)) 616 real_size += DS_SIZE; 617 else { 618 if (netif_msg_tx_err(priv)) 619 en_warn(priv, "Non-linear headers\n"); 620 return 0; 621 } 622 } 623 } else { 624 *lso_header_size = 0; 625 *inline_ok = is_inline(priv->prof->inline_thold, skb, 626 shinfo, pfrag); 627 628 if (*inline_ok) 629 real_size = inline_size(skb); 630 else 631 real_size = CTRL_SIZE + 632 (shinfo->nr_frags + 1) * DS_SIZE; 633 } 634 635 return real_size; 636 } 637 638 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, 639 const struct sk_buff *skb, 640 const struct skb_shared_info *shinfo, 641 int real_size, u16 *vlan_tag, 642 int tx_ind, void *fragptr) 643 { 644 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 645 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; 646 unsigned int hlen = skb_headlen(skb); 647 648 if (skb->len <= spc) { 649 if (likely(skb->len >= MIN_PKT_LEN)) { 650 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 651 } else { 652 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); 653 memset(((void *)(inl + 1)) + skb->len, 0, 654 MIN_PKT_LEN - skb->len); 655 } 656 skb_copy_from_linear_data(skb, inl + 1, hlen); 657 if (shinfo->nr_frags) 658 memcpy(((void *)(inl + 1)) + hlen, fragptr, 659 skb_frag_size(&shinfo->frags[0])); 660 661 } else { 662 inl->byte_count = cpu_to_be32(1 << 31 | spc); 663 if (hlen <= spc) { 664 skb_copy_from_linear_data(skb, inl + 1, hlen); 665 if (hlen < spc) { 666 memcpy(((void *)(inl + 1)) + hlen, 667 fragptr, spc - hlen); 668 fragptr += spc - hlen; 669 } 670 inl = (void *) (inl + 1) + spc; 671 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 672 } else { 673 skb_copy_from_linear_data(skb, inl + 1, spc); 674 inl = (void *) (inl + 1) + spc; 675 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 676 hlen - spc); 677 if (shinfo->nr_frags) 678 memcpy(((void *)(inl + 1)) + hlen - spc, 679 fragptr, 680 skb_frag_size(&shinfo->frags[0])); 681 } 682 683 dma_wmb(); 684 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 685 } 686 } 687 688 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 689 void *accel_priv, select_queue_fallback_t fallback) 690 { 691 struct mlx4_en_priv *priv = netdev_priv(dev); 692 u16 rings_p_up = priv->num_tx_rings_p_up; 693 u8 up = 0; 694 695 if (dev->num_tc) 696 return skb_tx_hash(dev, skb); 697 698 if (skb_vlan_tag_present(skb)) 699 up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT; 700 701 return fallback(dev, skb) % rings_p_up + up * rings_p_up; 702 } 703 704 static void mlx4_bf_copy(void __iomem *dst, const void *src, 705 unsigned int bytecnt) 706 { 707 __iowrite64_copy(dst, src, bytecnt / 8); 708 } 709 710 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 711 { 712 struct skb_shared_info *shinfo = skb_shinfo(skb); 713 struct mlx4_en_priv *priv = netdev_priv(dev); 714 struct device *ddev = priv->ddev; 715 struct mlx4_en_tx_ring *ring; 716 struct mlx4_en_tx_desc *tx_desc; 717 struct mlx4_wqe_data_seg *data; 718 struct mlx4_en_tx_info *tx_info; 719 int tx_ind = 0; 720 int nr_txbb; 721 int desc_size; 722 int real_size; 723 u32 index, bf_index; 724 __be32 op_own; 725 u16 vlan_tag = 0; 726 u16 vlan_proto = 0; 727 int i_frag; 728 int lso_header_size; 729 void *fragptr = NULL; 730 bool bounce = false; 731 bool send_doorbell; 732 bool stop_queue; 733 bool inline_ok; 734 u32 ring_cons; 735 736 if (!priv->port_up) 737 goto tx_drop; 738 739 tx_ind = skb_get_queue_mapping(skb); 740 ring = priv->tx_ring[tx_ind]; 741 742 /* fetch ring->cons far ahead before needing it to avoid stall */ 743 ring_cons = ACCESS_ONCE(ring->cons); 744 745 real_size = get_real_size(skb, shinfo, dev, &lso_header_size, 746 &inline_ok, &fragptr); 747 if (unlikely(!real_size)) 748 goto tx_drop; 749 750 /* Align descriptor to TXBB size */ 751 desc_size = ALIGN(real_size, TXBB_SIZE); 752 nr_txbb = desc_size / TXBB_SIZE; 753 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 754 if (netif_msg_tx_err(priv)) 755 en_warn(priv, "Oversized header or SG list\n"); 756 goto tx_drop; 757 } 758 759 if (skb_vlan_tag_present(skb)) { 760 vlan_tag = skb_vlan_tag_get(skb); 761 vlan_proto = be16_to_cpu(skb->vlan_proto); 762 } 763 764 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); 765 766 /* Track current inflight packets for performance analysis */ 767 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 768 (u32)(ring->prod - ring_cons - 1)); 769 770 /* Packet is good - grab an index and transmit it */ 771 index = ring->prod & ring->size_mask; 772 bf_index = ring->prod; 773 774 /* See if we have enough space for whole descriptor TXBB for setting 775 * SW ownership on next descriptor; if not, use a bounce buffer. */ 776 if (likely(index + nr_txbb <= ring->size)) 777 tx_desc = ring->buf + index * TXBB_SIZE; 778 else { 779 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 780 bounce = true; 781 } 782 783 /* Save skb in tx_info ring */ 784 tx_info = &ring->tx_info[index]; 785 tx_info->skb = skb; 786 tx_info->nr_txbb = nr_txbb; 787 788 data = &tx_desc->data; 789 if (lso_header_size) 790 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, 791 DS_SIZE)); 792 793 /* valid only for none inline segments */ 794 tx_info->data_offset = (void *)data - (void *)tx_desc; 795 796 tx_info->inl = inline_ok; 797 798 tx_info->linear = (lso_header_size < skb_headlen(skb) && 799 !inline_ok) ? 1 : 0; 800 801 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; 802 data += tx_info->nr_maps - 1; 803 804 if (!tx_info->inl) { 805 dma_addr_t dma = 0; 806 u32 byte_count = 0; 807 808 /* Map fragments if any */ 809 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { 810 const struct skb_frag_struct *frag; 811 812 frag = &shinfo->frags[i_frag]; 813 byte_count = skb_frag_size(frag); 814 dma = skb_frag_dma_map(ddev, frag, 815 0, byte_count, 816 DMA_TO_DEVICE); 817 if (dma_mapping_error(ddev, dma)) 818 goto tx_drop_unmap; 819 820 data->addr = cpu_to_be64(dma); 821 data->lkey = ring->mr_key; 822 dma_wmb(); 823 data->byte_count = cpu_to_be32(byte_count); 824 --data; 825 } 826 827 /* Map linear part if needed */ 828 if (tx_info->linear) { 829 byte_count = skb_headlen(skb) - lso_header_size; 830 831 dma = dma_map_single(ddev, skb->data + 832 lso_header_size, byte_count, 833 PCI_DMA_TODEVICE); 834 if (dma_mapping_error(ddev, dma)) 835 goto tx_drop_unmap; 836 837 data->addr = cpu_to_be64(dma); 838 data->lkey = ring->mr_key; 839 dma_wmb(); 840 data->byte_count = cpu_to_be32(byte_count); 841 } 842 /* tx completion can avoid cache line miss for common cases */ 843 tx_info->map0_dma = dma; 844 tx_info->map0_byte_count = byte_count; 845 } 846 847 /* 848 * For timestamping add flag to skb_shinfo and 849 * set flag for further reference 850 */ 851 tx_info->ts_requested = 0; 852 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 853 shinfo->tx_flags & SKBTX_HW_TSTAMP)) { 854 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 855 tx_info->ts_requested = 1; 856 } 857 858 /* Prepare ctrl segement apart opcode+ownership, which depends on 859 * whether LSO is used */ 860 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 861 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 862 if (!skb->encapsulation) 863 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 864 MLX4_WQE_CTRL_TCP_UDP_CSUM); 865 else 866 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); 867 ring->tx_csum++; 868 } 869 870 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 871 struct ethhdr *ethh; 872 873 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 874 * so that VFs and PF can communicate with each other 875 */ 876 ethh = (struct ethhdr *)skb->data; 877 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 878 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 879 } 880 881 /* Handle LSO (TSO) packets */ 882 if (lso_header_size) { 883 int i; 884 885 /* Mark opcode as LSO */ 886 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 887 ((ring->prod & ring->size) ? 888 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 889 890 /* Fill in the LSO prefix */ 891 tx_desc->lso.mss_hdr_size = cpu_to_be32( 892 shinfo->gso_size << 16 | lso_header_size); 893 894 /* Copy headers; 895 * note that we already verified that it is linear */ 896 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 897 898 ring->tso_packets++; 899 900 i = ((skb->len - lso_header_size) / shinfo->gso_size) + 901 !!((skb->len - lso_header_size) % shinfo->gso_size); 902 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 903 ring->packets += i; 904 } else { 905 /* Normal (Non LSO) packet */ 906 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 907 ((ring->prod & ring->size) ? 908 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 909 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 910 ring->packets++; 911 } 912 ring->bytes += tx_info->nr_bytes; 913 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); 914 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 915 916 if (tx_info->inl) 917 build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag, 918 tx_ind, fragptr); 919 920 if (skb->encapsulation) { 921 struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb); 922 if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP) 923 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); 924 else 925 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); 926 } 927 928 ring->prod += nr_txbb; 929 930 /* If we used a bounce buffer then copy descriptor back into place */ 931 if (unlikely(bounce)) 932 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 933 934 skb_tx_timestamp(skb); 935 936 /* Check available TXBBs And 2K spare for prefetch */ 937 stop_queue = mlx4_en_is_tx_ring_full(ring); 938 if (unlikely(stop_queue)) { 939 netif_tx_stop_queue(ring->tx_queue); 940 ring->queue_stopped++; 941 } 942 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); 943 944 real_size = (real_size / 16) & 0x3f; 945 946 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && 947 !skb_vlan_tag_present(skb) && send_doorbell) { 948 tx_desc->ctrl.bf_qpn = ring->doorbell_qpn | 949 cpu_to_be32(real_size); 950 951 op_own |= htonl((bf_index & 0xffff) << 8); 952 /* Ensure new descriptor hits memory 953 * before setting ownership of this descriptor to HW 954 */ 955 dma_wmb(); 956 tx_desc->ctrl.owner_opcode = op_own; 957 958 wmb(); 959 960 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, 961 desc_size); 962 963 wmb(); 964 965 ring->bf.offset ^= ring->bf.buf_size; 966 } else { 967 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); 968 if (vlan_proto == ETH_P_8021AD) 969 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; 970 else if (vlan_proto == ETH_P_8021Q) 971 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; 972 else 973 tx_desc->ctrl.ins_vlan = 0; 974 975 tx_desc->ctrl.fence_size = real_size; 976 977 /* Ensure new descriptor hits memory 978 * before setting ownership of this descriptor to HW 979 */ 980 dma_wmb(); 981 tx_desc->ctrl.owner_opcode = op_own; 982 if (send_doorbell) { 983 wmb(); 984 /* Since there is no iowrite*_native() that writes the 985 * value as is, without byteswapping - using the one 986 * the doesn't do byteswapping in the relevant arch 987 * endianness. 988 */ 989 #if defined(__LITTLE_ENDIAN) 990 iowrite32( 991 #else 992 iowrite32be( 993 #endif 994 ring->doorbell_qpn, 995 ring->bf.uar->map + MLX4_SEND_DOORBELL); 996 } else { 997 ring->xmit_more++; 998 } 999 } 1000 1001 if (unlikely(stop_queue)) { 1002 /* If queue was emptied after the if (stop_queue) , and before 1003 * the netif_tx_stop_queue() - need to wake the queue, 1004 * or else it will remain stopped forever. 1005 * Need a memory barrier to make sure ring->cons was not 1006 * updated before queue was stopped. 1007 */ 1008 smp_rmb(); 1009 1010 ring_cons = ACCESS_ONCE(ring->cons); 1011 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { 1012 netif_tx_wake_queue(ring->tx_queue); 1013 ring->wake_queue++; 1014 } 1015 } 1016 return NETDEV_TX_OK; 1017 1018 tx_drop_unmap: 1019 en_err(priv, "DMA mapping error\n"); 1020 1021 while (++i_frag < shinfo->nr_frags) { 1022 ++data; 1023 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), 1024 be32_to_cpu(data->byte_count), 1025 PCI_DMA_TODEVICE); 1026 } 1027 1028 tx_drop: 1029 dev_kfree_skb_any(skb); 1030 priv->stats.tx_dropped++; 1031 return NETDEV_TX_OK; 1032 } 1033 1034