1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <asm/page.h> 35 #include <linux/mlx4/cq.h> 36 #include <linux/slab.h> 37 #include <linux/mlx4/qp.h> 38 #include <linux/skbuff.h> 39 #include <linux/if_vlan.h> 40 #include <linux/prefetch.h> 41 #include <linux/vmalloc.h> 42 #include <linux/tcp.h> 43 #include <linux/ip.h> 44 #include <linux/ipv6.h> 45 #include <linux/moduleparam.h> 46 47 #include "mlx4_en.h" 48 49 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 50 struct mlx4_en_tx_ring **pring, u32 size, 51 u16 stride, int node, int queue_index) 52 { 53 struct mlx4_en_dev *mdev = priv->mdev; 54 struct mlx4_en_tx_ring *ring; 55 int tmp; 56 int err; 57 58 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 59 if (!ring) { 60 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 61 if (!ring) { 62 en_err(priv, "Failed allocating TX ring\n"); 63 return -ENOMEM; 64 } 65 } 66 67 ring->size = size; 68 ring->size_mask = size - 1; 69 ring->stride = stride; 70 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; 71 72 tmp = size * sizeof(struct mlx4_en_tx_info); 73 ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node); 74 if (!ring->tx_info) { 75 ring->tx_info = vmalloc(tmp); 76 if (!ring->tx_info) { 77 err = -ENOMEM; 78 goto err_ring; 79 } 80 } 81 82 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 83 ring->tx_info, tmp); 84 85 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 86 if (!ring->bounce_buf) { 87 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 88 if (!ring->bounce_buf) { 89 err = -ENOMEM; 90 goto err_info; 91 } 92 } 93 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); 94 95 /* Allocate HW buffers on provided NUMA node */ 96 set_dev_node(&mdev->dev->persist->pdev->dev, node); 97 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 98 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 99 if (err) { 100 en_err(priv, "Failed allocating hwq resources\n"); 101 goto err_bounce; 102 } 103 104 ring->buf = ring->wqres.buf.direct.buf; 105 106 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", 107 ring, ring->buf, ring->size, ring->buf_size, 108 (unsigned long long) ring->wqres.buf.direct.map); 109 110 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, 111 MLX4_RESERVE_ETH_BF_QP); 112 if (err) { 113 en_err(priv, "failed reserving qp for TX ring\n"); 114 goto err_hwq_res; 115 } 116 117 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL); 118 if (err) { 119 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 120 goto err_reserve; 121 } 122 ring->qp.event = mlx4_en_sqp_event; 123 124 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 125 if (err) { 126 en_dbg(DRV, priv, "working without blueflame (%d)\n", err); 127 ring->bf.uar = &mdev->priv_uar; 128 ring->bf.uar->map = mdev->uar_map; 129 ring->bf_enabled = false; 130 ring->bf_alloced = false; 131 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 132 } else { 133 ring->bf_alloced = true; 134 ring->bf_enabled = !!(priv->pflags & 135 MLX4_EN_PRIV_FLAGS_BLUEFLAME); 136 } 137 138 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 139 ring->queue_index = queue_index; 140 141 if (queue_index < priv->num_tx_rings_p_up) 142 cpumask_set_cpu(cpumask_local_spread(queue_index, 143 priv->mdev->dev->numa_node), 144 &ring->affinity_mask); 145 146 *pring = ring; 147 return 0; 148 149 err_reserve: 150 mlx4_qp_release_range(mdev->dev, ring->qpn, 1); 151 err_hwq_res: 152 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 153 err_bounce: 154 kfree(ring->bounce_buf); 155 ring->bounce_buf = NULL; 156 err_info: 157 kvfree(ring->tx_info); 158 ring->tx_info = NULL; 159 err_ring: 160 kfree(ring); 161 *pring = NULL; 162 return err; 163 } 164 165 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 166 struct mlx4_en_tx_ring **pring) 167 { 168 struct mlx4_en_dev *mdev = priv->mdev; 169 struct mlx4_en_tx_ring *ring = *pring; 170 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 171 172 if (ring->bf_alloced) 173 mlx4_bf_free(mdev->dev, &ring->bf); 174 mlx4_qp_remove(mdev->dev, &ring->qp); 175 mlx4_qp_free(mdev->dev, &ring->qp); 176 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); 177 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 178 kfree(ring->bounce_buf); 179 ring->bounce_buf = NULL; 180 kvfree(ring->tx_info); 181 ring->tx_info = NULL; 182 kfree(ring); 183 *pring = NULL; 184 } 185 186 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 187 struct mlx4_en_tx_ring *ring, 188 int cq, int user_prio) 189 { 190 struct mlx4_en_dev *mdev = priv->mdev; 191 int err; 192 193 ring->cqn = cq; 194 ring->prod = 0; 195 ring->cons = 0xffffffff; 196 ring->last_nr_txbb = 1; 197 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); 198 memset(ring->buf, 0, ring->buf_size); 199 200 ring->qp_state = MLX4_QP_STATE_RST; 201 ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8); 202 ring->mr_key = cpu_to_be32(mdev->mr.key); 203 204 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, 205 ring->cqn, user_prio, &ring->context); 206 if (ring->bf_alloced) 207 ring->context.usr_page = 208 cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, 209 ring->bf.uar->index)); 210 211 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, 212 &ring->qp, &ring->qp_state); 213 if (!cpumask_empty(&ring->affinity_mask)) 214 netif_set_xps_queue(priv->dev, &ring->affinity_mask, 215 ring->queue_index); 216 217 return err; 218 } 219 220 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 221 struct mlx4_en_tx_ring *ring) 222 { 223 struct mlx4_en_dev *mdev = priv->mdev; 224 225 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, 226 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); 227 } 228 229 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) 230 { 231 return ring->prod - ring->cons > ring->full_size; 232 } 233 234 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 235 struct mlx4_en_tx_ring *ring, int index, 236 u8 owner) 237 { 238 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); 239 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 240 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 241 void *end = ring->buf + ring->buf_size; 242 __be32 *ptr = (__be32 *)tx_desc; 243 int i; 244 245 /* Optimize the common case when there are no wraparounds */ 246 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 247 /* Stamp the freed descriptor */ 248 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 249 i += STAMP_STRIDE) { 250 *ptr = stamp; 251 ptr += STAMP_DWORDS; 252 } 253 } else { 254 /* Stamp the freed descriptor */ 255 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; 256 i += STAMP_STRIDE) { 257 *ptr = stamp; 258 ptr += STAMP_DWORDS; 259 if ((void *)ptr >= end) { 260 ptr = ring->buf; 261 stamp ^= cpu_to_be32(0x80000000); 262 } 263 } 264 } 265 } 266 267 268 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 269 struct mlx4_en_tx_ring *ring, 270 int index, u8 owner, u64 timestamp, 271 int napi_mode) 272 { 273 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 274 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; 275 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; 276 void *end = ring->buf + ring->buf_size; 277 struct sk_buff *skb = tx_info->skb; 278 int nr_maps = tx_info->nr_maps; 279 int i; 280 281 /* We do not touch skb here, so prefetch skb->users location 282 * to speedup consume_skb() 283 */ 284 prefetchw(&skb->users); 285 286 if (unlikely(timestamp)) { 287 struct skb_shared_hwtstamps hwts; 288 289 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); 290 skb_tstamp_tx(skb, &hwts); 291 } 292 293 /* Optimize the common case when there are no wraparounds */ 294 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { 295 if (!tx_info->inl) { 296 if (tx_info->linear) 297 dma_unmap_single(priv->ddev, 298 tx_info->map0_dma, 299 tx_info->map0_byte_count, 300 PCI_DMA_TODEVICE); 301 else 302 dma_unmap_page(priv->ddev, 303 tx_info->map0_dma, 304 tx_info->map0_byte_count, 305 PCI_DMA_TODEVICE); 306 for (i = 1; i < nr_maps; i++) { 307 data++; 308 dma_unmap_page(priv->ddev, 309 (dma_addr_t)be64_to_cpu(data->addr), 310 be32_to_cpu(data->byte_count), 311 PCI_DMA_TODEVICE); 312 } 313 } 314 } else { 315 if (!tx_info->inl) { 316 if ((void *) data >= end) { 317 data = ring->buf + ((void *)data - end); 318 } 319 320 if (tx_info->linear) 321 dma_unmap_single(priv->ddev, 322 tx_info->map0_dma, 323 tx_info->map0_byte_count, 324 PCI_DMA_TODEVICE); 325 else 326 dma_unmap_page(priv->ddev, 327 tx_info->map0_dma, 328 tx_info->map0_byte_count, 329 PCI_DMA_TODEVICE); 330 for (i = 1; i < nr_maps; i++) { 331 data++; 332 /* Check for wraparound before unmapping */ 333 if ((void *) data >= end) 334 data = ring->buf; 335 dma_unmap_page(priv->ddev, 336 (dma_addr_t)be64_to_cpu(data->addr), 337 be32_to_cpu(data->byte_count), 338 PCI_DMA_TODEVICE); 339 } 340 } 341 } 342 napi_consume_skb(skb, napi_mode); 343 344 return tx_info->nr_txbb; 345 } 346 347 348 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 349 { 350 struct mlx4_en_priv *priv = netdev_priv(dev); 351 int cnt = 0; 352 353 /* Skip last polled descriptor */ 354 ring->cons += ring->last_nr_txbb; 355 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 356 ring->cons, ring->prod); 357 358 if ((u32) (ring->prod - ring->cons) > ring->size) { 359 if (netif_msg_tx_err(priv)) 360 en_warn(priv, "Tx consumer passed producer!\n"); 361 return 0; 362 } 363 364 while (ring->cons != ring->prod) { 365 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, 366 ring->cons & ring->size_mask, 367 !!(ring->cons & ring->size), 0, 368 0 /* Non-NAPI caller */); 369 ring->cons += ring->last_nr_txbb; 370 cnt++; 371 } 372 373 netdev_tx_reset_queue(ring->tx_queue); 374 375 if (cnt) 376 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 377 378 return cnt; 379 } 380 381 static bool mlx4_en_process_tx_cq(struct net_device *dev, 382 struct mlx4_en_cq *cq, int napi_budget) 383 { 384 struct mlx4_en_priv *priv = netdev_priv(dev); 385 struct mlx4_cq *mcq = &cq->mcq; 386 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; 387 struct mlx4_cqe *cqe; 388 u16 index; 389 u16 new_index, ring_index, stamp_index; 390 u32 txbbs_skipped = 0; 391 u32 txbbs_stamp = 0; 392 u32 cons_index = mcq->cons_index; 393 int size = cq->size; 394 u32 size_mask = ring->size_mask; 395 struct mlx4_cqe *buf = cq->buf; 396 u32 packets = 0; 397 u32 bytes = 0; 398 int factor = priv->cqe_factor; 399 int done = 0; 400 int budget = priv->tx_work_limit; 401 u32 last_nr_txbb; 402 u32 ring_cons; 403 404 if (!priv->port_up) 405 return true; 406 407 netdev_txq_bql_complete_prefetchw(ring->tx_queue); 408 409 index = cons_index & size_mask; 410 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 411 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); 412 ring_cons = ACCESS_ONCE(ring->cons); 413 ring_index = ring_cons & size_mask; 414 stamp_index = ring_index; 415 416 /* Process all completed CQEs */ 417 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 418 cons_index & size) && (done < budget)) { 419 /* 420 * make sure we read the CQE after we read the 421 * ownership bit 422 */ 423 dma_rmb(); 424 425 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 426 MLX4_CQE_OPCODE_ERROR)) { 427 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; 428 429 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", 430 cqe_err->vendor_err_syndrome, 431 cqe_err->syndrome); 432 } 433 434 /* Skip over last polled CQE */ 435 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 436 437 do { 438 u64 timestamp = 0; 439 440 txbbs_skipped += last_nr_txbb; 441 ring_index = (ring_index + last_nr_txbb) & size_mask; 442 443 if (unlikely(ring->tx_info[ring_index].ts_requested)) 444 timestamp = mlx4_en_get_cqe_ts(cqe); 445 446 /* free next descriptor */ 447 last_nr_txbb = mlx4_en_free_tx_desc( 448 priv, ring, ring_index, 449 !!((ring_cons + txbbs_skipped) & 450 ring->size), timestamp, napi_budget); 451 452 mlx4_en_stamp_wqe(priv, ring, stamp_index, 453 !!((ring_cons + txbbs_stamp) & 454 ring->size)); 455 stamp_index = ring_index; 456 txbbs_stamp = txbbs_skipped; 457 packets++; 458 bytes += ring->tx_info[ring_index].nr_bytes; 459 } while ((++done < budget) && (ring_index != new_index)); 460 461 ++cons_index; 462 index = cons_index & size_mask; 463 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; 464 } 465 466 467 /* 468 * To prevent CQ overflow we first update CQ consumer and only then 469 * the ring consumer. 470 */ 471 mcq->cons_index = cons_index; 472 mlx4_cq_set_ci(mcq); 473 wmb(); 474 475 /* we want to dirty this cache line once */ 476 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; 477 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; 478 479 netdev_tx_completed_queue(ring->tx_queue, packets, bytes); 480 481 /* Wakeup Tx queue if this stopped, and ring is not full. 482 */ 483 if (netif_tx_queue_stopped(ring->tx_queue) && 484 !mlx4_en_is_tx_ring_full(ring)) { 485 netif_tx_wake_queue(ring->tx_queue); 486 ring->wake_queue++; 487 } 488 return done < budget; 489 } 490 491 void mlx4_en_tx_irq(struct mlx4_cq *mcq) 492 { 493 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 494 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 495 496 if (likely(priv->port_up)) 497 napi_schedule_irqoff(&cq->napi); 498 else 499 mlx4_en_arm_cq(priv, cq); 500 } 501 502 /* TX CQ polling - called by NAPI */ 503 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) 504 { 505 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 506 struct net_device *dev = cq->dev; 507 struct mlx4_en_priv *priv = netdev_priv(dev); 508 int clean_complete; 509 510 clean_complete = mlx4_en_process_tx_cq(dev, cq, budget); 511 if (!clean_complete) 512 return budget; 513 514 napi_complete(napi); 515 mlx4_en_arm_cq(priv, cq); 516 517 return 0; 518 } 519 520 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, 521 struct mlx4_en_tx_ring *ring, 522 u32 index, 523 unsigned int desc_size) 524 { 525 u32 copy = (ring->size - index) * TXBB_SIZE; 526 int i; 527 528 for (i = desc_size - copy - 4; i >= 0; i -= 4) { 529 if ((i & (TXBB_SIZE - 1)) == 0) 530 wmb(); 531 532 *((u32 *) (ring->buf + i)) = 533 *((u32 *) (ring->bounce_buf + copy + i)); 534 } 535 536 for (i = copy - 4; i >= 4 ; i -= 4) { 537 if ((i & (TXBB_SIZE - 1)) == 0) 538 wmb(); 539 540 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = 541 *((u32 *) (ring->bounce_buf + i)); 542 } 543 544 /* Return real descriptor location */ 545 return ring->buf + index * TXBB_SIZE; 546 } 547 548 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping 549 * 550 * It seems strange we do not simply use skb_copy_bits(). 551 * This would allow to inline all skbs iff skb->len <= inline_thold 552 * 553 * Note that caller already checked skb was not a gso packet 554 */ 555 static bool is_inline(int inline_thold, const struct sk_buff *skb, 556 const struct skb_shared_info *shinfo, 557 void **pfrag) 558 { 559 void *ptr; 560 561 if (skb->len > inline_thold || !inline_thold) 562 return false; 563 564 if (shinfo->nr_frags == 1) { 565 ptr = skb_frag_address_safe(&shinfo->frags[0]); 566 if (unlikely(!ptr)) 567 return false; 568 *pfrag = ptr; 569 return true; 570 } 571 if (shinfo->nr_frags) 572 return false; 573 return true; 574 } 575 576 static int inline_size(const struct sk_buff *skb) 577 { 578 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) 579 <= MLX4_INLINE_ALIGN) 580 return ALIGN(skb->len + CTRL_SIZE + 581 sizeof(struct mlx4_wqe_inline_seg), 16); 582 else 583 return ALIGN(skb->len + CTRL_SIZE + 2 * 584 sizeof(struct mlx4_wqe_inline_seg), 16); 585 } 586 587 static int get_real_size(const struct sk_buff *skb, 588 const struct skb_shared_info *shinfo, 589 struct net_device *dev, 590 int *lso_header_size, 591 bool *inline_ok, 592 void **pfrag) 593 { 594 struct mlx4_en_priv *priv = netdev_priv(dev); 595 int real_size; 596 597 if (shinfo->gso_size) { 598 *inline_ok = false; 599 if (skb->encapsulation) 600 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); 601 else 602 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); 603 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + 604 ALIGN(*lso_header_size + 4, DS_SIZE); 605 if (unlikely(*lso_header_size != skb_headlen(skb))) { 606 /* We add a segment for the skb linear buffer only if 607 * it contains data */ 608 if (*lso_header_size < skb_headlen(skb)) 609 real_size += DS_SIZE; 610 else { 611 if (netif_msg_tx_err(priv)) 612 en_warn(priv, "Non-linear headers\n"); 613 return 0; 614 } 615 } 616 } else { 617 *lso_header_size = 0; 618 *inline_ok = is_inline(priv->prof->inline_thold, skb, 619 shinfo, pfrag); 620 621 if (*inline_ok) 622 real_size = inline_size(skb); 623 else 624 real_size = CTRL_SIZE + 625 (shinfo->nr_frags + 1) * DS_SIZE; 626 } 627 628 return real_size; 629 } 630 631 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, 632 const struct sk_buff *skb, 633 const struct skb_shared_info *shinfo, 634 int real_size, u16 *vlan_tag, 635 int tx_ind, void *fragptr) 636 { 637 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; 638 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; 639 unsigned int hlen = skb_headlen(skb); 640 641 if (skb->len <= spc) { 642 if (likely(skb->len >= MIN_PKT_LEN)) { 643 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); 644 } else { 645 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); 646 memset(((void *)(inl + 1)) + skb->len, 0, 647 MIN_PKT_LEN - skb->len); 648 } 649 skb_copy_from_linear_data(skb, inl + 1, hlen); 650 if (shinfo->nr_frags) 651 memcpy(((void *)(inl + 1)) + hlen, fragptr, 652 skb_frag_size(&shinfo->frags[0])); 653 654 } else { 655 inl->byte_count = cpu_to_be32(1 << 31 | spc); 656 if (hlen <= spc) { 657 skb_copy_from_linear_data(skb, inl + 1, hlen); 658 if (hlen < spc) { 659 memcpy(((void *)(inl + 1)) + hlen, 660 fragptr, spc - hlen); 661 fragptr += spc - hlen; 662 } 663 inl = (void *) (inl + 1) + spc; 664 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); 665 } else { 666 skb_copy_from_linear_data(skb, inl + 1, spc); 667 inl = (void *) (inl + 1) + spc; 668 skb_copy_from_linear_data_offset(skb, spc, inl + 1, 669 hlen - spc); 670 if (shinfo->nr_frags) 671 memcpy(((void *)(inl + 1)) + hlen - spc, 672 fragptr, 673 skb_frag_size(&shinfo->frags[0])); 674 } 675 676 dma_wmb(); 677 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); 678 } 679 } 680 681 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 682 void *accel_priv, select_queue_fallback_t fallback) 683 { 684 struct mlx4_en_priv *priv = netdev_priv(dev); 685 u16 rings_p_up = priv->num_tx_rings_p_up; 686 u8 up = 0; 687 688 if (dev->num_tc) 689 return skb_tx_hash(dev, skb); 690 691 if (skb_vlan_tag_present(skb)) 692 up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT; 693 694 return fallback(dev, skb) % rings_p_up + up * rings_p_up; 695 } 696 697 static void mlx4_bf_copy(void __iomem *dst, const void *src, 698 unsigned int bytecnt) 699 { 700 __iowrite64_copy(dst, src, bytecnt / 8); 701 } 702 703 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) 704 { 705 struct skb_shared_info *shinfo = skb_shinfo(skb); 706 struct mlx4_en_priv *priv = netdev_priv(dev); 707 struct device *ddev = priv->ddev; 708 struct mlx4_en_tx_ring *ring; 709 struct mlx4_en_tx_desc *tx_desc; 710 struct mlx4_wqe_data_seg *data; 711 struct mlx4_en_tx_info *tx_info; 712 int tx_ind = 0; 713 int nr_txbb; 714 int desc_size; 715 int real_size; 716 u32 index, bf_index; 717 __be32 op_own; 718 u16 vlan_tag = 0; 719 u16 vlan_proto = 0; 720 int i_frag; 721 int lso_header_size; 722 void *fragptr = NULL; 723 bool bounce = false; 724 bool send_doorbell; 725 bool stop_queue; 726 bool inline_ok; 727 u32 ring_cons; 728 729 tx_ind = skb_get_queue_mapping(skb); 730 ring = priv->tx_ring[tx_ind]; 731 732 if (!priv->port_up) 733 goto tx_drop; 734 735 /* fetch ring->cons far ahead before needing it to avoid stall */ 736 ring_cons = ACCESS_ONCE(ring->cons); 737 738 real_size = get_real_size(skb, shinfo, dev, &lso_header_size, 739 &inline_ok, &fragptr); 740 if (unlikely(!real_size)) 741 goto tx_drop; 742 743 /* Align descriptor to TXBB size */ 744 desc_size = ALIGN(real_size, TXBB_SIZE); 745 nr_txbb = desc_size / TXBB_SIZE; 746 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { 747 if (netif_msg_tx_err(priv)) 748 en_warn(priv, "Oversized header or SG list\n"); 749 goto tx_drop; 750 } 751 752 if (skb_vlan_tag_present(skb)) { 753 vlan_tag = skb_vlan_tag_get(skb); 754 vlan_proto = be16_to_cpu(skb->vlan_proto); 755 } 756 757 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); 758 759 /* Track current inflight packets for performance analysis */ 760 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 761 (u32)(ring->prod - ring_cons - 1)); 762 763 /* Packet is good - grab an index and transmit it */ 764 index = ring->prod & ring->size_mask; 765 bf_index = ring->prod; 766 767 /* See if we have enough space for whole descriptor TXBB for setting 768 * SW ownership on next descriptor; if not, use a bounce buffer. */ 769 if (likely(index + nr_txbb <= ring->size)) 770 tx_desc = ring->buf + index * TXBB_SIZE; 771 else { 772 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; 773 bounce = true; 774 } 775 776 /* Save skb in tx_info ring */ 777 tx_info = &ring->tx_info[index]; 778 tx_info->skb = skb; 779 tx_info->nr_txbb = nr_txbb; 780 781 data = &tx_desc->data; 782 if (lso_header_size) 783 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, 784 DS_SIZE)); 785 786 /* valid only for none inline segments */ 787 tx_info->data_offset = (void *)data - (void *)tx_desc; 788 789 tx_info->inl = inline_ok; 790 791 tx_info->linear = (lso_header_size < skb_headlen(skb) && 792 !inline_ok) ? 1 : 0; 793 794 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; 795 data += tx_info->nr_maps - 1; 796 797 if (!tx_info->inl) { 798 dma_addr_t dma = 0; 799 u32 byte_count = 0; 800 801 /* Map fragments if any */ 802 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { 803 const struct skb_frag_struct *frag; 804 805 frag = &shinfo->frags[i_frag]; 806 byte_count = skb_frag_size(frag); 807 dma = skb_frag_dma_map(ddev, frag, 808 0, byte_count, 809 DMA_TO_DEVICE); 810 if (dma_mapping_error(ddev, dma)) 811 goto tx_drop_unmap; 812 813 data->addr = cpu_to_be64(dma); 814 data->lkey = ring->mr_key; 815 dma_wmb(); 816 data->byte_count = cpu_to_be32(byte_count); 817 --data; 818 } 819 820 /* Map linear part if needed */ 821 if (tx_info->linear) { 822 byte_count = skb_headlen(skb) - lso_header_size; 823 824 dma = dma_map_single(ddev, skb->data + 825 lso_header_size, byte_count, 826 PCI_DMA_TODEVICE); 827 if (dma_mapping_error(ddev, dma)) 828 goto tx_drop_unmap; 829 830 data->addr = cpu_to_be64(dma); 831 data->lkey = ring->mr_key; 832 dma_wmb(); 833 data->byte_count = cpu_to_be32(byte_count); 834 } 835 /* tx completion can avoid cache line miss for common cases */ 836 tx_info->map0_dma = dma; 837 tx_info->map0_byte_count = byte_count; 838 } 839 840 /* 841 * For timestamping add flag to skb_shinfo and 842 * set flag for further reference 843 */ 844 tx_info->ts_requested = 0; 845 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && 846 shinfo->tx_flags & SKBTX_HW_TSTAMP)) { 847 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 848 tx_info->ts_requested = 1; 849 } 850 851 /* Prepare ctrl segement apart opcode+ownership, which depends on 852 * whether LSO is used */ 853 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; 854 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 855 if (!skb->encapsulation) 856 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 857 MLX4_WQE_CTRL_TCP_UDP_CSUM); 858 else 859 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); 860 ring->tx_csum++; 861 } 862 863 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { 864 struct ethhdr *ethh; 865 866 /* Copy dst mac address to wqe. This allows loopback in eSwitch, 867 * so that VFs and PF can communicate with each other 868 */ 869 ethh = (struct ethhdr *)skb->data; 870 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); 871 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); 872 } 873 874 /* Handle LSO (TSO) packets */ 875 if (lso_header_size) { 876 int i; 877 878 /* Mark opcode as LSO */ 879 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | 880 ((ring->prod & ring->size) ? 881 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 882 883 /* Fill in the LSO prefix */ 884 tx_desc->lso.mss_hdr_size = cpu_to_be32( 885 shinfo->gso_size << 16 | lso_header_size); 886 887 /* Copy headers; 888 * note that we already verified that it is linear */ 889 memcpy(tx_desc->lso.header, skb->data, lso_header_size); 890 891 ring->tso_packets++; 892 893 i = ((skb->len - lso_header_size) / shinfo->gso_size) + 894 !!((skb->len - lso_header_size) % shinfo->gso_size); 895 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; 896 ring->packets += i; 897 } else { 898 /* Normal (Non LSO) packet */ 899 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | 900 ((ring->prod & ring->size) ? 901 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); 902 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 903 ring->packets++; 904 } 905 ring->bytes += tx_info->nr_bytes; 906 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); 907 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); 908 909 if (tx_info->inl) 910 build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag, 911 tx_ind, fragptr); 912 913 if (skb->encapsulation) { 914 union { 915 struct iphdr *v4; 916 struct ipv6hdr *v6; 917 unsigned char *hdr; 918 } ip; 919 u8 proto; 920 921 ip.hdr = skb_inner_network_header(skb); 922 proto = (ip.v4->version == 4) ? ip.v4->protocol : 923 ip.v6->nexthdr; 924 925 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) 926 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); 927 else 928 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); 929 } 930 931 ring->prod += nr_txbb; 932 933 /* If we used a bounce buffer then copy descriptor back into place */ 934 if (unlikely(bounce)) 935 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); 936 937 skb_tx_timestamp(skb); 938 939 /* Check available TXBBs And 2K spare for prefetch */ 940 stop_queue = mlx4_en_is_tx_ring_full(ring); 941 if (unlikely(stop_queue)) { 942 netif_tx_stop_queue(ring->tx_queue); 943 ring->queue_stopped++; 944 } 945 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); 946 947 real_size = (real_size / 16) & 0x3f; 948 949 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && 950 !skb_vlan_tag_present(skb) && send_doorbell) { 951 tx_desc->ctrl.bf_qpn = ring->doorbell_qpn | 952 cpu_to_be32(real_size); 953 954 op_own |= htonl((bf_index & 0xffff) << 8); 955 /* Ensure new descriptor hits memory 956 * before setting ownership of this descriptor to HW 957 */ 958 dma_wmb(); 959 tx_desc->ctrl.owner_opcode = op_own; 960 961 wmb(); 962 963 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, 964 desc_size); 965 966 wmb(); 967 968 ring->bf.offset ^= ring->bf.buf_size; 969 } else { 970 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); 971 if (vlan_proto == ETH_P_8021AD) 972 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; 973 else if (vlan_proto == ETH_P_8021Q) 974 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; 975 else 976 tx_desc->ctrl.ins_vlan = 0; 977 978 tx_desc->ctrl.fence_size = real_size; 979 980 /* Ensure new descriptor hits memory 981 * before setting ownership of this descriptor to HW 982 */ 983 dma_wmb(); 984 tx_desc->ctrl.owner_opcode = op_own; 985 if (send_doorbell) { 986 wmb(); 987 /* Since there is no iowrite*_native() that writes the 988 * value as is, without byteswapping - using the one 989 * the doesn't do byteswapping in the relevant arch 990 * endianness. 991 */ 992 #if defined(__LITTLE_ENDIAN) 993 iowrite32( 994 #else 995 iowrite32be( 996 #endif 997 ring->doorbell_qpn, 998 ring->bf.uar->map + MLX4_SEND_DOORBELL); 999 } else { 1000 ring->xmit_more++; 1001 } 1002 } 1003 1004 if (unlikely(stop_queue)) { 1005 /* If queue was emptied after the if (stop_queue) , and before 1006 * the netif_tx_stop_queue() - need to wake the queue, 1007 * or else it will remain stopped forever. 1008 * Need a memory barrier to make sure ring->cons was not 1009 * updated before queue was stopped. 1010 */ 1011 smp_rmb(); 1012 1013 ring_cons = ACCESS_ONCE(ring->cons); 1014 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { 1015 netif_tx_wake_queue(ring->tx_queue); 1016 ring->wake_queue++; 1017 } 1018 } 1019 return NETDEV_TX_OK; 1020 1021 tx_drop_unmap: 1022 en_err(priv, "DMA mapping error\n"); 1023 1024 while (++i_frag < shinfo->nr_frags) { 1025 ++data; 1026 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), 1027 be32_to_cpu(data->byte_count), 1028 PCI_DMA_TODEVICE); 1029 } 1030 1031 tx_drop: 1032 dev_kfree_skb_any(skb); 1033 ring->tx_dropped++; 1034 return NETDEV_TX_OK; 1035 } 1036 1037