1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <linux/bpf.h> 35 #include <linux/bpf_trace.h> 36 #include <linux/mlx4/cq.h> 37 #include <linux/slab.h> 38 #include <linux/mlx4/qp.h> 39 #include <linux/skbuff.h> 40 #include <linux/rculist.h> 41 #include <linux/if_ether.h> 42 #include <linux/if_vlan.h> 43 #include <linux/vmalloc.h> 44 #include <linux/irq.h> 45 #include <linux/skbuff_ref.h> 46 47 #include <net/ip.h> 48 #if IS_ENABLED(CONFIG_IPV6) 49 #include <net/ip6_checksum.h> 50 #endif 51 #include <net/page_pool/helpers.h> 52 53 #include "mlx4_en.h" 54 55 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, 56 struct mlx4_en_rx_ring *ring, 57 struct mlx4_en_rx_desc *rx_desc, 58 struct mlx4_en_rx_alloc *frags, 59 gfp_t gfp) 60 { 61 dma_addr_t dma; 62 int i; 63 64 for (i = 0; i < priv->num_frags; i++, frags++) { 65 if (!frags->page) { 66 frags->page = page_pool_alloc_pages(ring->pp, gfp); 67 if (!frags->page) { 68 ring->alloc_fail++; 69 return -ENOMEM; 70 } 71 page_pool_fragment_page(frags->page, 1); 72 frags->page_offset = priv->rx_headroom; 73 74 ring->rx_alloc_pages++; 75 } 76 dma = page_pool_get_dma_addr(frags->page); 77 rx_desc->data[i].addr = cpu_to_be64(dma + frags->page_offset); 78 } 79 return 0; 80 } 81 82 static void mlx4_en_free_frag(const struct mlx4_en_priv *priv, 83 struct mlx4_en_rx_ring *ring, 84 struct mlx4_en_rx_alloc *frag) 85 { 86 if (frag->page) 87 page_pool_put_full_page(ring->pp, frag->page, false); 88 /* We need to clear all fields, otherwise a change of priv->log_rx_info 89 * could lead to see garbage later in frag->page. 90 */ 91 memset(frag, 0, sizeof(*frag)); 92 } 93 94 static void mlx4_en_init_rx_desc(const struct mlx4_en_priv *priv, 95 struct mlx4_en_rx_ring *ring, int index) 96 { 97 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; 98 int possible_frags; 99 int i; 100 101 /* Set size and memtype fields */ 102 for (i = 0; i < priv->num_frags; i++) { 103 rx_desc->data[i].byte_count = 104 cpu_to_be32(priv->frag_info[i].frag_size); 105 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); 106 } 107 108 /* If the number of used fragments does not fill up the ring stride, 109 * remaining (unused) fragments must be padded with null address/size 110 * and a special memory key */ 111 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; 112 for (i = priv->num_frags; i < possible_frags; i++) { 113 rx_desc->data[i].byte_count = 0; 114 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); 115 rx_desc->data[i].addr = 0; 116 } 117 } 118 119 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, 120 struct mlx4_en_rx_ring *ring, int index, 121 gfp_t gfp) 122 { 123 struct mlx4_en_rx_desc *rx_desc = ring->buf + 124 (index << ring->log_stride); 125 struct mlx4_en_rx_alloc *frags = ring->rx_info + 126 (index << priv->log_rx_info); 127 128 return mlx4_en_alloc_frags(priv, ring, rx_desc, frags, gfp); 129 } 130 131 static bool mlx4_en_is_ring_empty(const struct mlx4_en_rx_ring *ring) 132 { 133 return ring->prod == ring->cons; 134 } 135 136 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) 137 { 138 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); 139 } 140 141 /* slow path */ 142 static void mlx4_en_free_rx_desc(const struct mlx4_en_priv *priv, 143 struct mlx4_en_rx_ring *ring, 144 int index) 145 { 146 struct mlx4_en_rx_alloc *frags; 147 int nr; 148 149 frags = ring->rx_info + (index << priv->log_rx_info); 150 for (nr = 0; nr < priv->num_frags; nr++) { 151 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); 152 mlx4_en_free_frag(priv, ring, frags + nr); 153 } 154 } 155 156 /* Function not in fast-path */ 157 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) 158 { 159 struct mlx4_en_rx_ring *ring; 160 int ring_ind; 161 int buf_ind; 162 int new_size; 163 164 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { 165 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 166 ring = priv->rx_ring[ring_ind]; 167 168 if (mlx4_en_prepare_rx_desc(priv, ring, 169 ring->actual_size, 170 GFP_KERNEL)) { 171 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { 172 en_err(priv, "Failed to allocate enough rx buffers\n"); 173 return -ENOMEM; 174 } else { 175 new_size = rounddown_pow_of_two(ring->actual_size); 176 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", 177 ring->actual_size, new_size); 178 goto reduce_rings; 179 } 180 } 181 ring->actual_size++; 182 ring->prod++; 183 } 184 } 185 return 0; 186 187 reduce_rings: 188 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 189 ring = priv->rx_ring[ring_ind]; 190 while (ring->actual_size > new_size) { 191 ring->actual_size--; 192 ring->prod--; 193 mlx4_en_free_rx_desc(priv, ring, ring->actual_size); 194 } 195 } 196 197 return 0; 198 } 199 200 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, 201 struct mlx4_en_rx_ring *ring) 202 { 203 int index; 204 205 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", 206 ring->cons, ring->prod); 207 208 /* Unmap and free Rx buffers */ 209 for (index = 0; index < ring->size; index++) { 210 en_dbg(DRV, priv, "Processing descriptor:%d\n", index); 211 mlx4_en_free_rx_desc(priv, ring, index); 212 } 213 ring->cons = 0; 214 ring->prod = 0; 215 } 216 217 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) 218 { 219 int i; 220 int num_of_eqs; 221 int num_rx_rings; 222 struct mlx4_dev *dev = mdev->dev; 223 224 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { 225 num_of_eqs = max_t(int, MIN_RX_RINGS, 226 min_t(int, 227 mlx4_get_eqs_per_port(mdev->dev, i), 228 DEF_RX_RINGS)); 229 230 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : 231 min_t(int, num_of_eqs, num_online_cpus()); 232 mdev->profile.prof[i].rx_ring_num = 233 rounddown_pow_of_two(num_rx_rings); 234 } 235 } 236 237 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 238 struct mlx4_en_rx_ring **pring, 239 u32 size, u16 stride, int node, int queue_index) 240 { 241 struct mlx4_en_dev *mdev = priv->mdev; 242 struct page_pool_params pp = {}; 243 struct mlx4_en_rx_ring *ring; 244 int err = -ENOMEM; 245 int tmp; 246 247 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 248 if (!ring) { 249 en_err(priv, "Failed to allocate RX ring structure\n"); 250 return -ENOMEM; 251 } 252 253 ring->prod = 0; 254 ring->cons = 0; 255 ring->size = size; 256 ring->size_mask = size - 1; 257 ring->stride = stride; 258 ring->log_stride = ffs(ring->stride) - 1; 259 ring->buf_size = ring->size * ring->stride + TXBB_SIZE; 260 261 pp.flags = PP_FLAG_DMA_MAP; 262 pp.pool_size = size * DIV_ROUND_UP(priv->rx_skb_size, PAGE_SIZE); 263 pp.nid = node; 264 pp.napi = &priv->rx_cq[queue_index]->napi; 265 pp.netdev = priv->dev; 266 pp.dev = &mdev->dev->persist->pdev->dev; 267 pp.dma_dir = priv->dma_dir; 268 269 ring->pp = page_pool_create(&pp); 270 if (!ring->pp) 271 goto err_ring; 272 273 if (xdp_rxq_info_reg(&ring->xdp_rxq, priv->dev, queue_index, 0) < 0) 274 goto err_pp; 275 276 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, MEM_TYPE_PAGE_POOL, 277 ring->pp); 278 if (err) 279 goto err_xdp_info; 280 281 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * 282 sizeof(struct mlx4_en_rx_alloc)); 283 ring->rx_info = kvzalloc_node(tmp, GFP_KERNEL, node); 284 if (!ring->rx_info) { 285 err = -ENOMEM; 286 goto err_xdp_info; 287 } 288 289 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", 290 ring->rx_info, tmp); 291 292 /* Allocate HW buffers on provided NUMA node */ 293 set_dev_node(&mdev->dev->persist->pdev->dev, node); 294 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 295 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); 296 if (err) 297 goto err_info; 298 299 ring->buf = ring->wqres.buf.direct.buf; 300 301 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; 302 303 *pring = ring; 304 return 0; 305 306 err_info: 307 kvfree(ring->rx_info); 308 ring->rx_info = NULL; 309 err_xdp_info: 310 xdp_rxq_info_unreg(&ring->xdp_rxq); 311 err_pp: 312 page_pool_destroy(ring->pp); 313 err_ring: 314 kfree(ring); 315 *pring = NULL; 316 317 return err; 318 } 319 320 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) 321 { 322 struct mlx4_en_rx_ring *ring; 323 int i; 324 int ring_ind; 325 int err; 326 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + 327 DS_SIZE * priv->num_frags); 328 329 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 330 ring = priv->rx_ring[ring_ind]; 331 332 ring->prod = 0; 333 ring->cons = 0; 334 ring->actual_size = 0; 335 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; 336 337 ring->stride = stride; 338 if (ring->stride <= TXBB_SIZE) { 339 /* Stamp first unused send wqe */ 340 __be32 *ptr = (__be32 *)ring->buf; 341 __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT); 342 *ptr = stamp; 343 /* Move pointer to start of rx section */ 344 ring->buf += TXBB_SIZE; 345 } 346 347 ring->log_stride = ffs(ring->stride) - 1; 348 ring->buf_size = ring->size * ring->stride; 349 350 memset(ring->buf, 0, ring->buf_size); 351 mlx4_en_update_rx_prod_db(ring); 352 353 /* Initialize all descriptors */ 354 for (i = 0; i < ring->size; i++) 355 mlx4_en_init_rx_desc(priv, ring, i); 356 } 357 err = mlx4_en_fill_rx_buffers(priv); 358 if (err) 359 goto err_buffers; 360 361 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 362 ring = priv->rx_ring[ring_ind]; 363 364 ring->size_mask = ring->actual_size - 1; 365 mlx4_en_update_rx_prod_db(ring); 366 } 367 368 return 0; 369 370 err_buffers: 371 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) 372 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); 373 374 ring_ind = priv->rx_ring_num - 1; 375 while (ring_ind >= 0) { 376 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) 377 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; 378 ring_ind--; 379 } 380 return err; 381 } 382 383 /* We recover from out of memory by scheduling our napi poll 384 * function (mlx4_en_process_cq), which tries to allocate 385 * all missing RX buffers (call to mlx4_en_refill_rx_buffers). 386 */ 387 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) 388 { 389 int ring; 390 391 if (!priv->port_up) 392 return; 393 394 for (ring = 0; ring < priv->rx_ring_num; ring++) { 395 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) { 396 local_bh_disable(); 397 napi_schedule(&priv->rx_cq[ring]->napi); 398 local_bh_enable(); 399 } 400 } 401 } 402 403 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 404 struct mlx4_en_rx_ring **pring, 405 u32 size, u16 stride) 406 { 407 struct mlx4_en_dev *mdev = priv->mdev; 408 struct mlx4_en_rx_ring *ring = *pring; 409 struct bpf_prog *old_prog; 410 411 old_prog = rcu_dereference_protected( 412 ring->xdp_prog, 413 lockdep_is_held(&mdev->state_lock)); 414 if (old_prog) 415 bpf_prog_put(old_prog); 416 xdp_rxq_info_unreg(&ring->xdp_rxq); 417 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); 418 kvfree(ring->rx_info); 419 page_pool_destroy(ring->pp); 420 ring->rx_info = NULL; 421 kfree(ring); 422 *pring = NULL; 423 } 424 425 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 426 struct mlx4_en_rx_ring *ring) 427 { 428 mlx4_en_free_rx_buf(priv, ring); 429 if (ring->stride <= TXBB_SIZE) 430 ring->buf -= TXBB_SIZE; 431 } 432 433 434 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, 435 struct mlx4_en_rx_alloc *frags, 436 struct sk_buff *skb, 437 int length) 438 { 439 const struct mlx4_en_frag_info *frag_info = priv->frag_info; 440 unsigned int truesize = 0; 441 bool release = true; 442 int nr, frag_size; 443 struct page *page; 444 dma_addr_t dma; 445 446 /* Collect used fragments while replacing them in the HW descriptors */ 447 for (nr = 0;; frags++) { 448 frag_size = min_t(int, length, frag_info->frag_size); 449 450 page = frags->page; 451 if (unlikely(!page)) 452 goto fail; 453 454 dma = page_pool_get_dma_addr(page); 455 dma_sync_single_range_for_cpu(priv->ddev, dma, frags->page_offset, 456 frag_size, priv->dma_dir); 457 458 __skb_fill_page_desc(skb, nr, page, frags->page_offset, 459 frag_size); 460 461 truesize += frag_info->frag_stride; 462 if (frag_info->frag_stride == PAGE_SIZE / 2) { 463 struct netmem_desc *desc = pp_page_to_nmdesc(page); 464 465 frags->page_offset ^= PAGE_SIZE / 2; 466 release = page_count(page) != 1 || 467 atomic_long_read(&desc->pp_ref_count) != 1 || 468 page_is_pfmemalloc(page) || 469 page_to_nid(page) != numa_mem_id(); 470 } else if (!priv->rx_headroom) { 471 /* rx_headroom for non XDP setup is always 0. 472 * When XDP is set, the above condition will 473 * guarantee page is always released. 474 */ 475 u32 sz_align = ALIGN(frag_size, SMP_CACHE_BYTES); 476 477 frags->page_offset += sz_align; 478 release = frags->page_offset + frag_info->frag_size > PAGE_SIZE; 479 } 480 if (release) { 481 frags->page = NULL; 482 } else { 483 page_pool_ref_page(page); 484 } 485 486 nr++; 487 length -= frag_size; 488 if (!length) 489 break; 490 frag_info++; 491 } 492 skb->truesize += truesize; 493 return nr; 494 495 fail: 496 while (nr > 0) { 497 nr--; 498 __skb_frag_unref(skb_shinfo(skb)->frags + nr, false); 499 } 500 return 0; 501 } 502 503 static void validate_loopback(struct mlx4_en_priv *priv, void *va) 504 { 505 const unsigned char *data = va + ETH_HLEN; 506 int i; 507 508 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++) { 509 if (data[i] != (unsigned char)i) 510 return; 511 } 512 /* Loopback found */ 513 priv->loopback_ok = 1; 514 } 515 516 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, 517 struct mlx4_en_rx_ring *ring) 518 { 519 u32 missing = ring->actual_size - (ring->prod - ring->cons); 520 521 /* Try to batch allocations, but not too much. */ 522 if (missing < 8) 523 return; 524 do { 525 if (mlx4_en_prepare_rx_desc(priv, ring, 526 ring->prod & ring->size_mask, 527 GFP_ATOMIC | __GFP_MEMALLOC)) 528 break; 529 ring->prod++; 530 } while (likely(--missing)); 531 532 mlx4_en_update_rx_prod_db(ring); 533 } 534 535 /* When hardware doesn't strip the vlan, we need to calculate the checksum 536 * over it and add it to the hardware's checksum calculation 537 */ 538 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, 539 struct vlan_hdr *vlanh) 540 { 541 return csum_add(hw_checksum, *(__wsum *)vlanh); 542 } 543 544 /* Although the stack expects checksum which doesn't include the pseudo 545 * header, the HW adds it. To address that, we are subtracting the pseudo 546 * header checksum from the checksum value provided by the HW. 547 */ 548 static int get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, 549 struct iphdr *iph) 550 { 551 __u16 length_for_csum = 0; 552 __wsum csum_pseudo_header = 0; 553 __u8 ipproto = iph->protocol; 554 555 if (unlikely(ipproto == IPPROTO_SCTP)) 556 return -1; 557 558 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); 559 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, 560 length_for_csum, ipproto, 0); 561 skb->csum = csum_sub(hw_checksum, csum_pseudo_header); 562 return 0; 563 } 564 565 #if IS_ENABLED(CONFIG_IPV6) 566 /* In IPv6 packets, hw_checksum lacks 6 bytes from IPv6 header: 567 * 4 first bytes : priority, version, flow_lbl 568 * and 2 additional bytes : nexthdr, hop_limit. 569 */ 570 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, 571 struct ipv6hdr *ipv6h) 572 { 573 __u8 nexthdr = ipv6h->nexthdr; 574 __wsum temp; 575 576 if (unlikely(nexthdr == IPPROTO_FRAGMENT || 577 nexthdr == IPPROTO_HOPOPTS || 578 nexthdr == IPPROTO_SCTP)) 579 return -1; 580 581 /* priority, version, flow_lbl */ 582 temp = csum_add(hw_checksum, *(__wsum *)ipv6h); 583 /* nexthdr and hop_limit */ 584 skb->csum = csum_add(temp, (__force __wsum)*(__be16 *)&ipv6h->nexthdr); 585 return 0; 586 } 587 #endif 588 589 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN) 590 591 /* We reach this function only after checking that any of 592 * the (IPv4 | IPv6) bits are set in cqe->status. 593 */ 594 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, 595 netdev_features_t dev_features) 596 { 597 __wsum hw_checksum = 0; 598 void *hdr; 599 600 /* CQE csum doesn't cover padding octets in short ethernet 601 * frames. And the pad field is appended prior to calculating 602 * and appending the FCS field. 603 * 604 * Detecting these padded frames requires to verify and parse 605 * IP headers, so we simply force all those small frames to skip 606 * checksum complete. 607 */ 608 if (short_frame(skb->len)) 609 return -EINVAL; 610 611 hdr = (u8 *)va + sizeof(struct ethhdr); 612 hw_checksum = csum_unfold((__force __sum16)cqe->checksum); 613 614 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) && 615 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) { 616 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); 617 hdr += sizeof(struct vlan_hdr); 618 } 619 620 #if IS_ENABLED(CONFIG_IPV6) 621 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) 622 return get_fixed_ipv6_csum(hw_checksum, skb, hdr); 623 #endif 624 return get_fixed_ipv4_csum(hw_checksum, skb, hdr); 625 } 626 627 #if IS_ENABLED(CONFIG_IPV6) 628 #define MLX4_CQE_STATUS_IP_ANY (MLX4_CQE_STATUS_IPV4 | MLX4_CQE_STATUS_IPV6) 629 #else 630 #define MLX4_CQE_STATUS_IP_ANY (MLX4_CQE_STATUS_IPV4) 631 #endif 632 633 struct mlx4_en_xdp_buff { 634 struct xdp_buff xdp; 635 struct mlx4_cqe *cqe; 636 struct mlx4_en_dev *mdev; 637 struct mlx4_en_rx_ring *ring; 638 struct net_device *dev; 639 }; 640 641 int mlx4_en_xdp_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp) 642 { 643 struct mlx4_en_xdp_buff *_ctx = (void *)ctx; 644 645 if (unlikely(_ctx->ring->hwtstamp_rx_filter != HWTSTAMP_FILTER_ALL)) 646 return -ENODATA; 647 648 *timestamp = mlx4_en_get_hwtstamp(_ctx->mdev, 649 mlx4_en_get_cqe_ts(_ctx->cqe)); 650 return 0; 651 } 652 653 int mlx4_en_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash, 654 enum xdp_rss_hash_type *rss_type) 655 { 656 struct mlx4_en_xdp_buff *_ctx = (void *)ctx; 657 struct mlx4_cqe *cqe = _ctx->cqe; 658 enum xdp_rss_hash_type xht = 0; 659 __be16 status; 660 661 if (unlikely(!(_ctx->dev->features & NETIF_F_RXHASH))) 662 return -ENODATA; 663 664 *hash = be32_to_cpu(cqe->immed_rss_invalid); 665 status = cqe->status; 666 if (status & cpu_to_be16(MLX4_CQE_STATUS_TCP)) 667 xht = XDP_RSS_L4_TCP; 668 if (status & cpu_to_be16(MLX4_CQE_STATUS_UDP)) 669 xht = XDP_RSS_L4_UDP; 670 if (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | MLX4_CQE_STATUS_IPV4F)) 671 xht |= XDP_RSS_L3_IPV4; 672 if (status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) { 673 xht |= XDP_RSS_L3_IPV6; 674 if (cqe->ipv6_ext_mask) 675 xht |= XDP_RSS_L3_DYNHDR; 676 } 677 *rss_type = xht; 678 679 return 0; 680 } 681 682 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) 683 { 684 struct mlx4_en_priv *priv = netdev_priv(dev); 685 struct mlx4_en_xdp_buff mxbuf = {}; 686 int factor = priv->cqe_factor; 687 struct mlx4_en_rx_ring *ring; 688 struct bpf_prog *xdp_prog; 689 int cq_ring = cq->ring; 690 bool doorbell_pending; 691 bool xdp_redir_flush; 692 struct mlx4_cqe *cqe; 693 int polled = 0; 694 int index; 695 696 if (unlikely(!priv->port_up || budget <= 0)) 697 return 0; 698 699 ring = priv->rx_ring[cq_ring]; 700 701 xdp_prog = rcu_dereference_bh(ring->xdp_prog); 702 xdp_init_buff(&mxbuf.xdp, priv->frag_info[0].frag_stride, &ring->xdp_rxq); 703 doorbell_pending = false; 704 xdp_redir_flush = false; 705 706 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx 707 * descriptor offset can be deduced from the CQE index instead of 708 * reading 'cqe->index' */ 709 index = cq->mcq.cons_index & ring->size_mask; 710 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 711 712 /* Process all completed CQEs */ 713 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 714 cq->mcq.cons_index & cq->size)) { 715 struct mlx4_en_rx_alloc *frags; 716 enum pkt_hash_types hash_type; 717 struct sk_buff *skb; 718 unsigned int length; 719 int ip_summed; 720 void *va; 721 int nr; 722 723 frags = ring->rx_info + (index << priv->log_rx_info); 724 va = page_address(frags[0].page) + frags[0].page_offset; 725 net_prefetchw(va); 726 /* 727 * make sure we read the CQE after we read the ownership bit 728 */ 729 dma_rmb(); 730 731 /* Drop packet on bad receive or bad checksum */ 732 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 733 MLX4_CQE_OPCODE_ERROR)) { 734 en_err(priv, "CQE completed in error - vendor syndrome:%d syndrome:%d\n", 735 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, 736 ((struct mlx4_err_cqe *)cqe)->syndrome); 737 goto next; 738 } 739 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { 740 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); 741 goto next; 742 } 743 744 /* Check if we need to drop the packet if SRIOV is not enabled 745 * and not performing the selftest or flb disabled 746 */ 747 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { 748 const struct ethhdr *ethh = va; 749 dma_addr_t dma; 750 /* Get pointer to first fragment since we haven't 751 * skb yet and cast it to ethhdr struct 752 */ 753 dma = page_pool_get_dma_addr(frags[0].page); 754 dma += frags[0].page_offset; 755 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), 756 DMA_FROM_DEVICE); 757 758 if (is_multicast_ether_addr(ethh->h_dest)) { 759 struct mlx4_mac_entry *entry; 760 struct hlist_head *bucket; 761 unsigned int mac_hash; 762 763 /* Drop the packet, since HW loopback-ed it */ 764 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; 765 bucket = &priv->mac_hash[mac_hash]; 766 hlist_for_each_entry_rcu_bh(entry, bucket, hlist) { 767 if (ether_addr_equal_64bits(entry->mac, 768 ethh->h_source)) 769 goto next; 770 } 771 } 772 } 773 774 if (unlikely(priv->validate_loopback)) { 775 validate_loopback(priv, va); 776 goto next; 777 } 778 779 /* 780 * Packet is OK - process it. 781 */ 782 length = be32_to_cpu(cqe->byte_cnt); 783 length -= ring->fcs_del; 784 785 /* A bpf program gets first chance to drop the packet. It may 786 * read bytes but not past the end of the frag. 787 */ 788 if (xdp_prog) { 789 dma_addr_t dma; 790 void *orig_data; 791 u32 act; 792 793 dma = page_pool_get_dma_addr(frags[0].page); 794 dma += frags[0].page_offset; 795 dma_sync_single_for_cpu(priv->ddev, dma, 796 priv->frag_info[0].frag_size, 797 DMA_FROM_DEVICE); 798 799 xdp_prepare_buff(&mxbuf.xdp, va - frags[0].page_offset, 800 frags[0].page_offset, length, true); 801 orig_data = mxbuf.xdp.data; 802 mxbuf.cqe = cqe; 803 mxbuf.mdev = priv->mdev; 804 mxbuf.ring = ring; 805 mxbuf.dev = dev; 806 807 act = bpf_prog_run_xdp(xdp_prog, &mxbuf.xdp); 808 809 length = mxbuf.xdp.data_end - mxbuf.xdp.data; 810 if (mxbuf.xdp.data != orig_data) { 811 frags[0].page_offset = mxbuf.xdp.data - 812 mxbuf.xdp.data_hard_start; 813 va = mxbuf.xdp.data; 814 } 815 816 switch (act) { 817 case XDP_PASS: 818 break; 819 case XDP_REDIRECT: 820 if (likely(!xdp_do_redirect(dev, &mxbuf.xdp, xdp_prog))) { 821 ring->xdp_redirect++; 822 xdp_redir_flush = true; 823 frags[0].page = NULL; 824 goto next; 825 } 826 ring->xdp_redirect_fail++; 827 trace_xdp_exception(dev, xdp_prog, act); 828 goto xdp_drop_no_cnt; 829 case XDP_TX: 830 if (likely(!mlx4_en_xmit_frame(ring, frags, priv, 831 length, cq_ring, 832 &doorbell_pending))) { 833 frags[0].page = NULL; 834 goto next; 835 } 836 trace_xdp_exception(dev, xdp_prog, act); 837 goto xdp_drop_no_cnt; /* Drop on xmit failure */ 838 default: 839 bpf_warn_invalid_xdp_action(dev, xdp_prog, act); 840 fallthrough; 841 case XDP_ABORTED: 842 trace_xdp_exception(dev, xdp_prog, act); 843 fallthrough; 844 case XDP_DROP: 845 ring->xdp_drop++; 846 xdp_drop_no_cnt: 847 goto next; 848 } 849 } 850 851 ring->bytes += length; 852 ring->packets++; 853 854 skb = napi_get_frags(&cq->napi); 855 if (unlikely(!skb)) 856 goto next; 857 skb_mark_for_recycle(skb); 858 859 if (unlikely(ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL)) { 860 u64 timestamp = mlx4_en_get_cqe_ts(cqe); 861 862 mlx4_en_fill_hwtstamps(priv->mdev, skb_hwtstamps(skb), 863 timestamp); 864 } 865 skb_record_rx_queue(skb, cq_ring); 866 867 if (likely(dev->features & NETIF_F_RXCSUM)) { 868 /* TODO: For IP non TCP/UDP packets when csum complete is 869 * not an option (not supported or any other reason) we can 870 * actually check cqe IPOK status bit and report 871 * CHECKSUM_UNNECESSARY rather than CHECKSUM_NONE 872 */ 873 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | 874 MLX4_CQE_STATUS_UDP)) && 875 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 876 cqe->checksum == cpu_to_be16(0xffff)) { 877 bool l2_tunnel; 878 879 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && 880 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); 881 ip_summed = CHECKSUM_UNNECESSARY; 882 hash_type = PKT_HASH_TYPE_L4; 883 if (l2_tunnel) 884 skb->csum_level = 1; 885 ring->csum_ok++; 886 } else { 887 if (!(priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && 888 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IP_ANY)))) 889 goto csum_none; 890 if (check_csum(cqe, skb, va, dev->features)) 891 goto csum_none; 892 ip_summed = CHECKSUM_COMPLETE; 893 hash_type = PKT_HASH_TYPE_L3; 894 ring->csum_complete++; 895 } 896 } else { 897 csum_none: 898 ip_summed = CHECKSUM_NONE; 899 hash_type = PKT_HASH_TYPE_L3; 900 ring->csum_none++; 901 } 902 skb->ip_summed = ip_summed; 903 if (dev->features & NETIF_F_RXHASH) 904 skb_set_hash(skb, 905 be32_to_cpu(cqe->immed_rss_invalid), 906 hash_type); 907 908 if ((cqe->vlan_my_qpn & 909 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) && 910 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) 911 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 912 be16_to_cpu(cqe->sl_vid)); 913 else if ((cqe->vlan_my_qpn & 914 cpu_to_be32(MLX4_CQE_SVLAN_PRESENT_MASK)) && 915 (dev->features & NETIF_F_HW_VLAN_STAG_RX)) 916 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), 917 be16_to_cpu(cqe->sl_vid)); 918 919 nr = mlx4_en_complete_rx_desc(priv, frags, skb, length); 920 if (likely(nr)) { 921 skb_shinfo(skb)->nr_frags = nr; 922 skb->len = length; 923 skb->data_len = length; 924 napi_gro_frags(&cq->napi); 925 } else { 926 __vlan_hwaccel_clear_tag(skb); 927 skb_clear_hash(skb); 928 } 929 next: 930 ++cq->mcq.cons_index; 931 index = (cq->mcq.cons_index) & ring->size_mask; 932 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; 933 if (unlikely(++polled == budget)) 934 break; 935 } 936 937 if (xdp_redir_flush) 938 xdp_do_flush(); 939 940 if (likely(polled)) { 941 if (doorbell_pending) { 942 priv->tx_cq[TX_XDP][cq_ring]->xdp_busy = true; 943 mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq_ring]); 944 } 945 946 mlx4_cq_set_ci(&cq->mcq); 947 wmb(); /* ensure HW sees CQ consumer before we post new buffers */ 948 ring->cons = cq->mcq.cons_index; 949 } 950 951 mlx4_en_refill_rx_buffers(priv, ring); 952 953 return polled; 954 } 955 956 957 void mlx4_en_rx_irq(struct mlx4_cq *mcq) 958 { 959 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 960 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 961 962 if (likely(priv->port_up)) 963 napi_schedule_irqoff(&cq->napi); 964 else 965 mlx4_en_arm_cq(priv, cq); 966 } 967 968 /* Rx CQ polling - called by NAPI */ 969 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) 970 { 971 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 972 struct net_device *dev = cq->dev; 973 struct mlx4_en_priv *priv = netdev_priv(dev); 974 struct mlx4_en_cq *xdp_tx_cq = NULL; 975 bool clean_complete = true; 976 int done; 977 978 if (!budget) 979 return 0; 980 981 if (priv->tx_ring_num[TX_XDP]) { 982 xdp_tx_cq = priv->tx_cq[TX_XDP][cq->ring]; 983 if (xdp_tx_cq->xdp_busy) { 984 clean_complete = mlx4_en_process_tx_cq(dev, xdp_tx_cq, 985 budget) < budget; 986 xdp_tx_cq->xdp_busy = !clean_complete; 987 } 988 } 989 990 done = mlx4_en_process_rx_cq(dev, cq, budget); 991 992 /* If we used up all the quota - we're probably not done yet... */ 993 if (done == budget || !clean_complete) { 994 int cpu_curr; 995 996 /* in case we got here because of !clean_complete */ 997 done = budget; 998 999 cpu_curr = smp_processor_id(); 1000 1001 if (likely(cpumask_test_cpu(cpu_curr, cq->aff_mask))) 1002 return budget; 1003 1004 /* Current cpu is not according to smp_irq_affinity - 1005 * probably affinity changed. Need to stop this NAPI 1006 * poll, and restart it on the right CPU. 1007 * Try to avoid returning a too small value (like 0), 1008 * to not fool net_rx_action() and its netdev_budget 1009 */ 1010 if (done) 1011 done--; 1012 } 1013 /* Done for now */ 1014 if (likely(napi_complete_done(napi, done))) 1015 mlx4_en_arm_cq(priv, cq); 1016 return done; 1017 } 1018 1019 void mlx4_en_calc_rx_buf(struct net_device *dev) 1020 { 1021 struct mlx4_en_priv *priv = netdev_priv(dev); 1022 int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu); 1023 int i = 0; 1024 1025 /* bpf requires buffers to be set up as 1 packet per page. 1026 * This only works when num_frags == 1. 1027 */ 1028 if (priv->tx_ring_num[TX_XDP]) { 1029 priv->frag_info[0].frag_size = eff_mtu; 1030 /* This will gain efficient xdp frame recycling at the 1031 * expense of more costly truesize accounting 1032 */ 1033 priv->frag_info[0].frag_stride = PAGE_SIZE; 1034 priv->dma_dir = DMA_BIDIRECTIONAL; 1035 priv->rx_headroom = XDP_PACKET_HEADROOM; 1036 i = 1; 1037 } else { 1038 int frag_size_max = 2048, buf_size = 0; 1039 1040 /* should not happen, right ? */ 1041 if (eff_mtu > PAGE_SIZE + (MLX4_EN_MAX_RX_FRAGS - 1) * 2048) 1042 frag_size_max = PAGE_SIZE; 1043 1044 while (buf_size < eff_mtu) { 1045 int frag_stride, frag_size = eff_mtu - buf_size; 1046 int pad, nb; 1047 1048 if (i < MLX4_EN_MAX_RX_FRAGS - 1) 1049 frag_size = min(frag_size, frag_size_max); 1050 1051 priv->frag_info[i].frag_size = frag_size; 1052 frag_stride = ALIGN(frag_size, SMP_CACHE_BYTES); 1053 /* We can only pack 2 1536-bytes frames in on 4K page 1054 * Therefore, each frame would consume more bytes (truesize) 1055 */ 1056 nb = PAGE_SIZE / frag_stride; 1057 pad = (PAGE_SIZE - nb * frag_stride) / nb; 1058 pad &= ~(SMP_CACHE_BYTES - 1); 1059 priv->frag_info[i].frag_stride = frag_stride + pad; 1060 1061 buf_size += frag_size; 1062 i++; 1063 } 1064 priv->dma_dir = DMA_FROM_DEVICE; 1065 priv->rx_headroom = 0; 1066 } 1067 1068 priv->num_frags = i; 1069 priv->rx_skb_size = eff_mtu; 1070 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); 1071 1072 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", 1073 eff_mtu, priv->num_frags); 1074 for (i = 0; i < priv->num_frags; i++) { 1075 en_dbg(DRV, 1076 priv, 1077 " frag:%d - size:%d stride:%d\n", 1078 i, 1079 priv->frag_info[i].frag_size, 1080 priv->frag_info[i].frag_stride); 1081 } 1082 } 1083 1084 /* RSS related functions */ 1085 1086 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, 1087 struct mlx4_en_rx_ring *ring, 1088 enum mlx4_qp_state *state, 1089 struct mlx4_qp *qp) 1090 { 1091 struct mlx4_en_dev *mdev = priv->mdev; 1092 struct mlx4_qp_context *context; 1093 int err = 0; 1094 1095 context = kzalloc(sizeof(*context), GFP_KERNEL); 1096 if (!context) 1097 return -ENOMEM; 1098 1099 err = mlx4_qp_alloc(mdev->dev, qpn, qp); 1100 if (err) { 1101 en_err(priv, "Failed to allocate qp #%x\n", qpn); 1102 goto out; 1103 } 1104 qp->event = mlx4_en_sqp_event; 1105 1106 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, 1107 qpn, ring->cqn, -1, context); 1108 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); 1109 1110 /* Cancel FCS removal if FW allows */ 1111 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { 1112 context->param3 |= cpu_to_be32(1 << 29); 1113 if (priv->dev->features & NETIF_F_RXFCS) 1114 ring->fcs_del = 0; 1115 else 1116 ring->fcs_del = ETH_FCS_LEN; 1117 } else 1118 ring->fcs_del = 0; 1119 1120 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); 1121 if (err) { 1122 mlx4_qp_remove(mdev->dev, qp); 1123 mlx4_qp_free(mdev->dev, qp); 1124 } 1125 mlx4_en_update_rx_prod_db(ring); 1126 out: 1127 kfree(context); 1128 return err; 1129 } 1130 1131 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) 1132 { 1133 int err; 1134 u32 qpn; 1135 1136 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, 1137 MLX4_RESERVE_A0_QP, 1138 MLX4_RES_USAGE_DRIVER); 1139 if (err) { 1140 en_err(priv, "Failed reserving drop qpn\n"); 1141 return err; 1142 } 1143 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp); 1144 if (err) { 1145 en_err(priv, "Failed allocating drop qp\n"); 1146 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1147 return err; 1148 } 1149 1150 return 0; 1151 } 1152 1153 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) 1154 { 1155 u32 qpn; 1156 1157 qpn = priv->drop_qp.qpn; 1158 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); 1159 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); 1160 mlx4_qp_release_range(priv->mdev->dev, qpn, 1); 1161 } 1162 1163 /* Allocate rx qp's and configure them according to rss map */ 1164 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) 1165 { 1166 struct mlx4_en_dev *mdev = priv->mdev; 1167 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1168 struct mlx4_qp_context context; 1169 struct mlx4_rss_context *rss_context; 1170 int rss_rings; 1171 void *ptr; 1172 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | 1173 MLX4_RSS_TCP_IPV6); 1174 int i, qpn; 1175 int err = 0; 1176 int good_qps = 0; 1177 u8 flags; 1178 1179 en_dbg(DRV, priv, "Configuring rss steering\n"); 1180 1181 flags = priv->rx_ring_num == 1 ? MLX4_RESERVE_A0_QP : 0; 1182 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, 1183 priv->rx_ring_num, 1184 &rss_map->base_qpn, flags, 1185 MLX4_RES_USAGE_DRIVER); 1186 if (err) { 1187 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); 1188 return err; 1189 } 1190 1191 for (i = 0; i < priv->rx_ring_num; i++) { 1192 qpn = rss_map->base_qpn + i; 1193 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], 1194 &rss_map->state[i], 1195 &rss_map->qps[i]); 1196 if (err) 1197 goto rss_err; 1198 1199 ++good_qps; 1200 } 1201 1202 if (priv->rx_ring_num == 1) { 1203 rss_map->indir_qp = &rss_map->qps[0]; 1204 priv->base_qpn = rss_map->indir_qp->qpn; 1205 en_info(priv, "Optimized Non-RSS steering\n"); 1206 return 0; 1207 } 1208 1209 rss_map->indir_qp = kzalloc(sizeof(*rss_map->indir_qp), GFP_KERNEL); 1210 if (!rss_map->indir_qp) { 1211 err = -ENOMEM; 1212 goto rss_err; 1213 } 1214 1215 /* Configure RSS indirection qp */ 1216 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, rss_map->indir_qp); 1217 if (err) { 1218 en_err(priv, "Failed to allocate RSS indirection QP\n"); 1219 goto qp_alloc_err; 1220 } 1221 1222 rss_map->indir_qp->event = mlx4_en_sqp_event; 1223 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, 1224 priv->rx_ring[0]->cqn, -1, &context); 1225 1226 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) 1227 rss_rings = priv->rx_ring_num; 1228 else 1229 rss_rings = priv->prof->rss_rings; 1230 1231 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) 1232 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 1233 rss_context = ptr; 1234 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | 1235 (rss_map->base_qpn)); 1236 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); 1237 if (priv->mdev->profile.udp_rss) { 1238 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; 1239 rss_context->base_qpn_udp = rss_context->default_qpn; 1240 } 1241 1242 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 1243 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); 1244 rss_mask |= MLX4_RSS_BY_INNER_HEADERS; 1245 } 1246 1247 rss_context->flags = rss_mask; 1248 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1249 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { 1250 rss_context->hash_fn = MLX4_RSS_HASH_XOR; 1251 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { 1252 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 1253 memcpy(rss_context->rss_key, priv->rss_key, 1254 MLX4_EN_RSS_KEY_SIZE); 1255 } else { 1256 en_err(priv, "Unknown RSS hash function requested\n"); 1257 err = -EINVAL; 1258 goto indir_err; 1259 } 1260 1261 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, 1262 rss_map->indir_qp, &rss_map->indir_state); 1263 if (err) 1264 goto indir_err; 1265 1266 return 0; 1267 1268 indir_err: 1269 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1270 MLX4_QP_STATE_RST, NULL, 0, 0, rss_map->indir_qp); 1271 mlx4_qp_remove(mdev->dev, rss_map->indir_qp); 1272 mlx4_qp_free(mdev->dev, rss_map->indir_qp); 1273 qp_alloc_err: 1274 kfree(rss_map->indir_qp); 1275 rss_map->indir_qp = NULL; 1276 rss_err: 1277 for (i = 0; i < good_qps; i++) { 1278 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1279 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1280 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1281 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1282 } 1283 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1284 return err; 1285 } 1286 1287 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) 1288 { 1289 struct mlx4_en_dev *mdev = priv->mdev; 1290 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1291 int i; 1292 1293 if (priv->rx_ring_num > 1) { 1294 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, 1295 MLX4_QP_STATE_RST, NULL, 0, 0, 1296 rss_map->indir_qp); 1297 mlx4_qp_remove(mdev->dev, rss_map->indir_qp); 1298 mlx4_qp_free(mdev->dev, rss_map->indir_qp); 1299 kfree(rss_map->indir_qp); 1300 rss_map->indir_qp = NULL; 1301 } 1302 1303 for (i = 0; i < priv->rx_ring_num; i++) { 1304 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], 1305 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); 1306 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); 1307 mlx4_qp_free(mdev->dev, &rss_map->qps[i]); 1308 } 1309 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); 1310 } 1311