1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/ethtool.h> 36 #include <linux/netdevice.h> 37 #include <linux/mlx4/driver.h> 38 #include <linux/mlx4/device.h> 39 #include <linux/in.h> 40 #include <net/ip.h> 41 #include <linux/bitmap.h> 42 43 #include "mlx4_en.h" 44 #include "en_port.h" 45 46 #define EN_ETHTOOL_QP_ATTACH (1ull << 63) 47 #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff) 48 #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff) 49 50 static int mlx4_en_moderation_update(struct mlx4_en_priv *priv) 51 { 52 int i, t; 53 int err = 0; 54 55 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) { 56 for (i = 0; i < priv->tx_ring_num[t]; i++) { 57 priv->tx_cq[t][i]->moder_cnt = priv->tx_frames; 58 priv->tx_cq[t][i]->moder_time = priv->tx_usecs; 59 if (priv->port_up) { 60 err = mlx4_en_set_cq_moder(priv, 61 priv->tx_cq[t][i]); 62 if (err) 63 return err; 64 } 65 } 66 } 67 68 if (priv->adaptive_rx_coal) 69 return 0; 70 71 for (i = 0; i < priv->rx_ring_num; i++) { 72 priv->rx_cq[i]->moder_cnt = priv->rx_frames; 73 priv->rx_cq[i]->moder_time = priv->rx_usecs; 74 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; 75 if (priv->port_up) { 76 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]); 77 if (err) 78 return err; 79 } 80 } 81 82 return err; 83 } 84 85 static void 86 mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) 87 { 88 struct mlx4_en_priv *priv = netdev_priv(dev); 89 struct mlx4_en_dev *mdev = priv->mdev; 90 91 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); 92 strlcpy(drvinfo->version, DRV_VERSION, 93 sizeof(drvinfo->version)); 94 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 95 "%d.%d.%d", 96 (u16) (mdev->dev->caps.fw_ver >> 32), 97 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff), 98 (u16) (mdev->dev->caps.fw_ver & 0xffff)); 99 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev), 100 sizeof(drvinfo->bus_info)); 101 } 102 103 static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = { 104 "blueflame", 105 "phv-bit" 106 }; 107 108 static const char main_strings[][ETH_GSTRING_LEN] = { 109 /* main statistics */ 110 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", 111 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", 112 "rx_length_errors", "rx_over_errors", "rx_crc_errors", 113 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", 114 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", 115 "tx_heartbeat_errors", "tx_window_errors", 116 117 /* port statistics */ 118 "tso_packets", 119 "xmit_more", 120 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_pages", 121 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload", 122 123 /* pf statistics */ 124 "pf_rx_packets", 125 "pf_rx_bytes", 126 "pf_tx_packets", 127 "pf_tx_bytes", 128 129 /* priority flow control statistics rx */ 130 "rx_pause_prio_0", "rx_pause_duration_prio_0", 131 "rx_pause_transition_prio_0", 132 "rx_pause_prio_1", "rx_pause_duration_prio_1", 133 "rx_pause_transition_prio_1", 134 "rx_pause_prio_2", "rx_pause_duration_prio_2", 135 "rx_pause_transition_prio_2", 136 "rx_pause_prio_3", "rx_pause_duration_prio_3", 137 "rx_pause_transition_prio_3", 138 "rx_pause_prio_4", "rx_pause_duration_prio_4", 139 "rx_pause_transition_prio_4", 140 "rx_pause_prio_5", "rx_pause_duration_prio_5", 141 "rx_pause_transition_prio_5", 142 "rx_pause_prio_6", "rx_pause_duration_prio_6", 143 "rx_pause_transition_prio_6", 144 "rx_pause_prio_7", "rx_pause_duration_prio_7", 145 "rx_pause_transition_prio_7", 146 147 /* flow control statistics rx */ 148 "rx_pause", "rx_pause_duration", "rx_pause_transition", 149 150 /* priority flow control statistics tx */ 151 "tx_pause_prio_0", "tx_pause_duration_prio_0", 152 "tx_pause_transition_prio_0", 153 "tx_pause_prio_1", "tx_pause_duration_prio_1", 154 "tx_pause_transition_prio_1", 155 "tx_pause_prio_2", "tx_pause_duration_prio_2", 156 "tx_pause_transition_prio_2", 157 "tx_pause_prio_3", "tx_pause_duration_prio_3", 158 "tx_pause_transition_prio_3", 159 "tx_pause_prio_4", "tx_pause_duration_prio_4", 160 "tx_pause_transition_prio_4", 161 "tx_pause_prio_5", "tx_pause_duration_prio_5", 162 "tx_pause_transition_prio_5", 163 "tx_pause_prio_6", "tx_pause_duration_prio_6", 164 "tx_pause_transition_prio_6", 165 "tx_pause_prio_7", "tx_pause_duration_prio_7", 166 "tx_pause_transition_prio_7", 167 168 /* flow control statistics tx */ 169 "tx_pause", "tx_pause_duration", "tx_pause_transition", 170 171 /* packet statistics */ 172 "rx_multicast_packets", 173 "rx_broadcast_packets", 174 "rx_jabbers", 175 "rx_in_range_length_error", 176 "rx_out_range_length_error", 177 "tx_multicast_packets", 178 "tx_broadcast_packets", 179 "rx_prio_0_packets", "rx_prio_0_bytes", 180 "rx_prio_1_packets", "rx_prio_1_bytes", 181 "rx_prio_2_packets", "rx_prio_2_bytes", 182 "rx_prio_3_packets", "rx_prio_3_bytes", 183 "rx_prio_4_packets", "rx_prio_4_bytes", 184 "rx_prio_5_packets", "rx_prio_5_bytes", 185 "rx_prio_6_packets", "rx_prio_6_bytes", 186 "rx_prio_7_packets", "rx_prio_7_bytes", 187 "rx_novlan_packets", "rx_novlan_bytes", 188 "tx_prio_0_packets", "tx_prio_0_bytes", 189 "tx_prio_1_packets", "tx_prio_1_bytes", 190 "tx_prio_2_packets", "tx_prio_2_bytes", 191 "tx_prio_3_packets", "tx_prio_3_bytes", 192 "tx_prio_4_packets", "tx_prio_4_bytes", 193 "tx_prio_5_packets", "tx_prio_5_bytes", 194 "tx_prio_6_packets", "tx_prio_6_bytes", 195 "tx_prio_7_packets", "tx_prio_7_bytes", 196 "tx_novlan_packets", "tx_novlan_bytes", 197 198 /* xdp statistics */ 199 "rx_xdp_drop", 200 "rx_xdp_tx", 201 "rx_xdp_tx_full", 202 }; 203 204 static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= { 205 "Interrupt Test", 206 "Link Test", 207 "Speed Test", 208 "Register Test", 209 "Loopback Test", 210 }; 211 212 static u32 mlx4_en_get_msglevel(struct net_device *dev) 213 { 214 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable; 215 } 216 217 static void mlx4_en_set_msglevel(struct net_device *dev, u32 val) 218 { 219 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val; 220 } 221 222 static void mlx4_en_get_wol(struct net_device *netdev, 223 struct ethtool_wolinfo *wol) 224 { 225 struct mlx4_en_priv *priv = netdev_priv(netdev); 226 struct mlx4_caps *caps = &priv->mdev->dev->caps; 227 int err = 0; 228 u64 config = 0; 229 u64 mask; 230 231 if ((priv->port < 1) || (priv->port > 2)) { 232 en_err(priv, "Failed to get WoL information\n"); 233 return; 234 } 235 236 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : 237 MLX4_DEV_CAP_FLAG_WOL_PORT2; 238 239 if (!(caps->flags & mask)) { 240 wol->supported = 0; 241 wol->wolopts = 0; 242 return; 243 } 244 245 if (caps->wol_port[priv->port]) 246 wol->supported = WAKE_MAGIC; 247 else 248 wol->supported = 0; 249 250 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); 251 if (err) { 252 en_err(priv, "Failed to get WoL information\n"); 253 return; 254 } 255 256 if ((config & MLX4_EN_WOL_ENABLED) && (config & MLX4_EN_WOL_MAGIC)) 257 wol->wolopts = WAKE_MAGIC; 258 else 259 wol->wolopts = 0; 260 } 261 262 static int mlx4_en_set_wol(struct net_device *netdev, 263 struct ethtool_wolinfo *wol) 264 { 265 struct mlx4_en_priv *priv = netdev_priv(netdev); 266 u64 config = 0; 267 int err = 0; 268 u64 mask; 269 270 if ((priv->port < 1) || (priv->port > 2)) 271 return -EOPNOTSUPP; 272 273 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : 274 MLX4_DEV_CAP_FLAG_WOL_PORT2; 275 276 if (!(priv->mdev->dev->caps.flags & mask)) 277 return -EOPNOTSUPP; 278 279 if (wol->supported & ~WAKE_MAGIC) 280 return -EINVAL; 281 282 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); 283 if (err) { 284 en_err(priv, "Failed to get WoL info, unable to modify\n"); 285 return err; 286 } 287 288 if (wol->wolopts & WAKE_MAGIC) { 289 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED | 290 MLX4_EN_WOL_MAGIC; 291 } else { 292 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC); 293 config |= MLX4_EN_WOL_DO_MODIFY; 294 } 295 296 err = mlx4_wol_write(priv->mdev->dev, config, priv->port); 297 if (err) 298 en_err(priv, "Failed to set WoL information\n"); 299 300 return err; 301 } 302 303 struct bitmap_iterator { 304 unsigned long *stats_bitmap; 305 unsigned int count; 306 unsigned int iterator; 307 bool advance_array; /* if set, force no increments */ 308 }; 309 310 static inline void bitmap_iterator_init(struct bitmap_iterator *h, 311 unsigned long *stats_bitmap, 312 int count) 313 { 314 h->iterator = 0; 315 h->advance_array = !bitmap_empty(stats_bitmap, count); 316 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count) 317 : count; 318 h->stats_bitmap = stats_bitmap; 319 } 320 321 static inline int bitmap_iterator_test(struct bitmap_iterator *h) 322 { 323 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap); 324 } 325 326 static inline int bitmap_iterator_inc(struct bitmap_iterator *h) 327 { 328 return h->iterator++; 329 } 330 331 static inline unsigned int 332 bitmap_iterator_count(struct bitmap_iterator *h) 333 { 334 return h->count; 335 } 336 337 static int mlx4_en_get_sset_count(struct net_device *dev, int sset) 338 { 339 struct mlx4_en_priv *priv = netdev_priv(dev); 340 struct bitmap_iterator it; 341 342 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 343 344 switch (sset) { 345 case ETH_SS_STATS: 346 return bitmap_iterator_count(&it) + 347 (priv->tx_ring_num[TX] * 2) + 348 (priv->rx_ring_num * (3 + NUM_XDP_STATS)); 349 case ETH_SS_TEST: 350 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags 351 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2; 352 case ETH_SS_PRIV_FLAGS: 353 return ARRAY_SIZE(mlx4_en_priv_flags); 354 default: 355 return -EOPNOTSUPP; 356 } 357 } 358 359 static void mlx4_en_get_ethtool_stats(struct net_device *dev, 360 struct ethtool_stats *stats, uint64_t *data) 361 { 362 struct mlx4_en_priv *priv = netdev_priv(dev); 363 int index = 0; 364 int i; 365 struct bitmap_iterator it; 366 367 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 368 369 spin_lock_bh(&priv->stats_lock); 370 371 mlx4_en_fold_software_stats(dev); 372 373 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it)) 374 if (bitmap_iterator_test(&it)) 375 data[index++] = ((unsigned long *)&dev->stats)[i]; 376 377 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it)) 378 if (bitmap_iterator_test(&it)) 379 data[index++] = ((unsigned long *)&priv->port_stats)[i]; 380 381 for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it)) 382 if (bitmap_iterator_test(&it)) 383 data[index++] = 384 ((unsigned long *)&priv->pf_stats)[i]; 385 386 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX; 387 i++, bitmap_iterator_inc(&it)) 388 if (bitmap_iterator_test(&it)) 389 data[index++] = 390 ((u64 *)&priv->rx_priority_flowstats)[i]; 391 392 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it)) 393 if (bitmap_iterator_test(&it)) 394 data[index++] = ((u64 *)&priv->rx_flowstats)[i]; 395 396 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX; 397 i++, bitmap_iterator_inc(&it)) 398 if (bitmap_iterator_test(&it)) 399 data[index++] = 400 ((u64 *)&priv->tx_priority_flowstats)[i]; 401 402 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it)) 403 if (bitmap_iterator_test(&it)) 404 data[index++] = ((u64 *)&priv->tx_flowstats)[i]; 405 406 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it)) 407 if (bitmap_iterator_test(&it)) 408 data[index++] = ((unsigned long *)&priv->pkstats)[i]; 409 410 for (i = 0; i < NUM_XDP_STATS; i++, bitmap_iterator_inc(&it)) 411 if (bitmap_iterator_test(&it)) 412 data[index++] = ((unsigned long *)&priv->xdp_stats)[i]; 413 414 for (i = 0; i < priv->tx_ring_num[TX]; i++) { 415 data[index++] = priv->tx_ring[TX][i]->packets; 416 data[index++] = priv->tx_ring[TX][i]->bytes; 417 } 418 for (i = 0; i < priv->rx_ring_num; i++) { 419 data[index++] = priv->rx_ring[i]->packets; 420 data[index++] = priv->rx_ring[i]->bytes; 421 data[index++] = priv->rx_ring[i]->dropped; 422 data[index++] = priv->rx_ring[i]->xdp_drop; 423 data[index++] = priv->rx_ring[i]->xdp_tx; 424 data[index++] = priv->rx_ring[i]->xdp_tx_full; 425 } 426 spin_unlock_bh(&priv->stats_lock); 427 428 } 429 430 static void mlx4_en_self_test(struct net_device *dev, 431 struct ethtool_test *etest, u64 *buf) 432 { 433 mlx4_en_ex_selftest(dev, &etest->flags, buf); 434 } 435 436 static void mlx4_en_get_strings(struct net_device *dev, 437 uint32_t stringset, uint8_t *data) 438 { 439 struct mlx4_en_priv *priv = netdev_priv(dev); 440 int index = 0; 441 int i, strings = 0; 442 struct bitmap_iterator it; 443 444 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 445 446 switch (stringset) { 447 case ETH_SS_TEST: 448 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++) 449 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); 450 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) 451 for (; i < MLX4_EN_NUM_SELF_TEST; i++) 452 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); 453 break; 454 455 case ETH_SS_STATS: 456 /* Add main counters */ 457 for (i = 0; i < NUM_MAIN_STATS; i++, strings++, 458 bitmap_iterator_inc(&it)) 459 if (bitmap_iterator_test(&it)) 460 strcpy(data + (index++) * ETH_GSTRING_LEN, 461 main_strings[strings]); 462 463 for (i = 0; i < NUM_PORT_STATS; i++, strings++, 464 bitmap_iterator_inc(&it)) 465 if (bitmap_iterator_test(&it)) 466 strcpy(data + (index++) * ETH_GSTRING_LEN, 467 main_strings[strings]); 468 469 for (i = 0; i < NUM_PF_STATS; i++, strings++, 470 bitmap_iterator_inc(&it)) 471 if (bitmap_iterator_test(&it)) 472 strcpy(data + (index++) * ETH_GSTRING_LEN, 473 main_strings[strings]); 474 475 for (i = 0; i < NUM_FLOW_STATS; i++, strings++, 476 bitmap_iterator_inc(&it)) 477 if (bitmap_iterator_test(&it)) 478 strcpy(data + (index++) * ETH_GSTRING_LEN, 479 main_strings[strings]); 480 481 for (i = 0; i < NUM_PKT_STATS; i++, strings++, 482 bitmap_iterator_inc(&it)) 483 if (bitmap_iterator_test(&it)) 484 strcpy(data + (index++) * ETH_GSTRING_LEN, 485 main_strings[strings]); 486 487 for (i = 0; i < NUM_XDP_STATS; i++, strings++, 488 bitmap_iterator_inc(&it)) 489 if (bitmap_iterator_test(&it)) 490 strcpy(data + (index++) * ETH_GSTRING_LEN, 491 main_strings[strings]); 492 493 for (i = 0; i < priv->tx_ring_num[TX]; i++) { 494 sprintf(data + (index++) * ETH_GSTRING_LEN, 495 "tx%d_packets", i); 496 sprintf(data + (index++) * ETH_GSTRING_LEN, 497 "tx%d_bytes", i); 498 } 499 for (i = 0; i < priv->rx_ring_num; i++) { 500 sprintf(data + (index++) * ETH_GSTRING_LEN, 501 "rx%d_packets", i); 502 sprintf(data + (index++) * ETH_GSTRING_LEN, 503 "rx%d_bytes", i); 504 sprintf(data + (index++) * ETH_GSTRING_LEN, 505 "rx%d_dropped", i); 506 sprintf(data + (index++) * ETH_GSTRING_LEN, 507 "rx%d_xdp_drop", i); 508 sprintf(data + (index++) * ETH_GSTRING_LEN, 509 "rx%d_xdp_tx", i); 510 sprintf(data + (index++) * ETH_GSTRING_LEN, 511 "rx%d_xdp_tx_full", i); 512 } 513 break; 514 case ETH_SS_PRIV_FLAGS: 515 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++) 516 strcpy(data + i * ETH_GSTRING_LEN, 517 mlx4_en_priv_flags[i]); 518 break; 519 520 } 521 } 522 523 static u32 mlx4_en_autoneg_get(struct net_device *dev) 524 { 525 struct mlx4_en_priv *priv = netdev_priv(dev); 526 struct mlx4_en_dev *mdev = priv->mdev; 527 u32 autoneg = AUTONEG_DISABLE; 528 529 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) && 530 (priv->port_state.flags & MLX4_EN_PORT_ANE)) 531 autoneg = AUTONEG_ENABLE; 532 533 return autoneg; 534 } 535 536 static void ptys2ethtool_update_supported_port(unsigned long *mask, 537 struct mlx4_ptys_reg *ptys_reg) 538 { 539 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); 540 541 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) 542 | MLX4_PROT_MASK(MLX4_1000BASE_T) 543 | MLX4_PROT_MASK(MLX4_100BASE_TX))) { 544 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask); 545 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) 546 | MLX4_PROT_MASK(MLX4_10GBASE_SR) 547 | MLX4_PROT_MASK(MLX4_56GBASE_SR4) 548 | MLX4_PROT_MASK(MLX4_40GBASE_CR4) 549 | MLX4_PROT_MASK(MLX4_40GBASE_SR4) 550 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { 551 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask); 552 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) 553 | MLX4_PROT_MASK(MLX4_40GBASE_KR4) 554 | MLX4_PROT_MASK(MLX4_20GBASE_KR2) 555 | MLX4_PROT_MASK(MLX4_10GBASE_KR) 556 | MLX4_PROT_MASK(MLX4_10GBASE_KX4) 557 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { 558 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask); 559 } 560 } 561 562 static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg) 563 { 564 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper); 565 566 if (!eth_proto) /* link down */ 567 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); 568 569 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) 570 | MLX4_PROT_MASK(MLX4_1000BASE_T) 571 | MLX4_PROT_MASK(MLX4_100BASE_TX))) { 572 return PORT_TP; 573 } 574 575 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR) 576 | MLX4_PROT_MASK(MLX4_56GBASE_SR4) 577 | MLX4_PROT_MASK(MLX4_40GBASE_SR4) 578 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { 579 return PORT_FIBRE; 580 } 581 582 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) 583 | MLX4_PROT_MASK(MLX4_56GBASE_CR4) 584 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) { 585 return PORT_DA; 586 } 587 588 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) 589 | MLX4_PROT_MASK(MLX4_40GBASE_KR4) 590 | MLX4_PROT_MASK(MLX4_20GBASE_KR2) 591 | MLX4_PROT_MASK(MLX4_10GBASE_KR) 592 | MLX4_PROT_MASK(MLX4_10GBASE_KX4) 593 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { 594 return PORT_NONE; 595 } 596 return PORT_OTHER; 597 } 598 599 #define MLX4_LINK_MODES_SZ \ 600 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8) 601 602 enum ethtool_report { 603 SUPPORTED = 0, 604 ADVERTISED = 1, 605 }; 606 607 struct ptys2ethtool_config { 608 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 609 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); 610 u32 speed; 611 }; 612 613 static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg, 614 enum ethtool_report report) 615 { 616 switch (report) { 617 case SUPPORTED: 618 return cfg->supported; 619 case ADVERTISED: 620 return cfg->advertised; 621 } 622 return NULL; 623 } 624 625 #define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \ 626 ({ \ 627 struct ptys2ethtool_config *cfg; \ 628 const unsigned int modes[] = { __VA_ARGS__ }; \ 629 unsigned int i; \ 630 cfg = &ptys2ethtool_map[reg_]; \ 631 cfg->speed = speed_; \ 632 bitmap_zero(cfg->supported, \ 633 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 634 bitmap_zero(cfg->advertised, \ 635 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 636 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ 637 __set_bit(modes[i], cfg->supported); \ 638 __set_bit(modes[i], cfg->advertised); \ 639 } \ 640 }) 641 642 /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */ 643 static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ]; 644 645 void __init mlx4_en_init_ptys2ethtool_map(void) 646 { 647 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100, 648 ETHTOOL_LINK_MODE_100baseT_Full_BIT); 649 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000, 650 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 651 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000, 652 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 653 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000, 654 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 655 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000, 656 ETHTOOL_LINK_MODE_10000baseT_Full_BIT); 657 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000, 658 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 659 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000, 660 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 661 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000, 662 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 663 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000, 664 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 665 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000, 666 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 667 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000, 668 ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT, 669 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); 670 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000, 671 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); 672 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000, 673 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); 674 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000, 675 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); 676 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000, 677 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); 678 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000, 679 ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT); 680 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000, 681 ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT); 682 }; 683 684 static void ptys2ethtool_update_link_modes(unsigned long *link_modes, 685 u32 eth_proto, 686 enum ethtool_report report) 687 { 688 int i; 689 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 690 if (eth_proto & MLX4_PROT_MASK(i)) 691 bitmap_or(link_modes, link_modes, 692 ptys2ethtool_link_mode(&ptys2ethtool_map[i], 693 report), 694 __ETHTOOL_LINK_MODE_MASK_NBITS); 695 } 696 } 697 698 static u32 ethtool2ptys_link_modes(const unsigned long *link_modes, 699 enum ethtool_report report) 700 { 701 int i; 702 u32 ptys_modes = 0; 703 704 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 705 if (bitmap_intersects( 706 ptys2ethtool_link_mode(&ptys2ethtool_map[i], 707 report), 708 link_modes, 709 __ETHTOOL_LINK_MODE_MASK_NBITS)) 710 ptys_modes |= 1 << i; 711 } 712 return ptys_modes; 713 } 714 715 /* Convert actual speed (SPEED_XXX) to ptys link modes */ 716 static u32 speed2ptys_link_modes(u32 speed) 717 { 718 int i; 719 u32 ptys_modes = 0; 720 721 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 722 if (ptys2ethtool_map[i].speed == speed) 723 ptys_modes |= 1 << i; 724 } 725 return ptys_modes; 726 } 727 728 static int 729 ethtool_get_ptys_link_ksettings(struct net_device *dev, 730 struct ethtool_link_ksettings *link_ksettings) 731 { 732 struct mlx4_en_priv *priv = netdev_priv(dev); 733 struct mlx4_ptys_reg ptys_reg; 734 u32 eth_proto; 735 int ret; 736 737 memset(&ptys_reg, 0, sizeof(ptys_reg)); 738 ptys_reg.local_port = priv->port; 739 ptys_reg.proto_mask = MLX4_PTYS_EN; 740 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, 741 MLX4_ACCESS_REG_QUERY, &ptys_reg); 742 if (ret) { 743 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)", 744 ret); 745 return ret; 746 } 747 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n", 748 ptys_reg.proto_mask); 749 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n", 750 be32_to_cpu(ptys_reg.eth_proto_cap)); 751 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n", 752 be32_to_cpu(ptys_reg.eth_proto_admin)); 753 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n", 754 be32_to_cpu(ptys_reg.eth_proto_oper)); 755 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n", 756 be32_to_cpu(ptys_reg.eth_proto_lp_adv)); 757 758 /* reset supported/advertising masks */ 759 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); 760 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); 761 762 ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported, 763 &ptys_reg); 764 765 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap); 766 ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported, 767 eth_proto, SUPPORTED); 768 769 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin); 770 ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising, 771 eth_proto, ADVERTISED); 772 773 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 774 Pause); 775 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 776 Asym_Pause); 777 778 if (priv->prof->tx_pause) 779 ethtool_link_ksettings_add_link_mode(link_ksettings, 780 advertising, Pause); 781 if (priv->prof->tx_pause ^ priv->prof->rx_pause) 782 ethtool_link_ksettings_add_link_mode(link_ksettings, 783 advertising, Asym_Pause); 784 785 link_ksettings->base.port = ptys_get_active_port(&ptys_reg); 786 787 if (mlx4_en_autoneg_get(dev)) { 788 ethtool_link_ksettings_add_link_mode(link_ksettings, 789 supported, Autoneg); 790 ethtool_link_ksettings_add_link_mode(link_ksettings, 791 advertising, Autoneg); 792 } 793 794 link_ksettings->base.autoneg 795 = (priv->port_state.flags & MLX4_EN_PORT_ANC) ? 796 AUTONEG_ENABLE : AUTONEG_DISABLE; 797 798 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv); 799 800 ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising); 801 ptys2ethtool_update_link_modes( 802 link_ksettings->link_modes.lp_advertising, 803 eth_proto, ADVERTISED); 804 if (priv->port_state.flags & MLX4_EN_PORT_ANC) 805 ethtool_link_ksettings_add_link_mode(link_ksettings, 806 lp_advertising, Autoneg); 807 808 link_ksettings->base.phy_address = 0; 809 link_ksettings->base.mdio_support = 0; 810 link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID; 811 link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 812 813 return ret; 814 } 815 816 static void 817 ethtool_get_default_link_ksettings( 818 struct net_device *dev, struct ethtool_link_ksettings *link_ksettings) 819 { 820 struct mlx4_en_priv *priv = netdev_priv(dev); 821 int trans_type; 822 823 link_ksettings->base.autoneg = AUTONEG_DISABLE; 824 825 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); 826 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 827 10000baseT_Full); 828 829 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); 830 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, 831 10000baseT_Full); 832 833 trans_type = priv->port_state.transceiver; 834 if (trans_type > 0 && trans_type <= 0xC) { 835 link_ksettings->base.port = PORT_FIBRE; 836 ethtool_link_ksettings_add_link_mode(link_ksettings, 837 supported, FIBRE); 838 ethtool_link_ksettings_add_link_mode(link_ksettings, 839 advertising, FIBRE); 840 } else if (trans_type == 0x80 || trans_type == 0) { 841 link_ksettings->base.port = PORT_TP; 842 ethtool_link_ksettings_add_link_mode(link_ksettings, 843 supported, TP); 844 ethtool_link_ksettings_add_link_mode(link_ksettings, 845 advertising, TP); 846 } else { 847 link_ksettings->base.port = -1; 848 } 849 } 850 851 static int 852 mlx4_en_get_link_ksettings(struct net_device *dev, 853 struct ethtool_link_ksettings *link_ksettings) 854 { 855 struct mlx4_en_priv *priv = netdev_priv(dev); 856 int ret = -EINVAL; 857 858 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port)) 859 return -ENOMEM; 860 861 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n", 862 priv->port_state.flags & MLX4_EN_PORT_ANC, 863 priv->port_state.flags & MLX4_EN_PORT_ANE); 864 865 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) 866 ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings); 867 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */ 868 ethtool_get_default_link_ksettings(dev, link_ksettings); 869 870 if (netif_carrier_ok(dev)) { 871 link_ksettings->base.speed = priv->port_state.link_speed; 872 link_ksettings->base.duplex = DUPLEX_FULL; 873 } else { 874 link_ksettings->base.speed = SPEED_UNKNOWN; 875 link_ksettings->base.duplex = DUPLEX_UNKNOWN; 876 } 877 return 0; 878 } 879 880 /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */ 881 static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed, 882 __be32 proto_cap) 883 { 884 __be32 proto_admin = 0; 885 886 if (!speed) { /* Speed = 0 ==> Reset Link modes */ 887 proto_admin = proto_cap; 888 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n", 889 be32_to_cpu(proto_cap)); 890 } else { 891 u32 ptys_link_modes = speed2ptys_link_modes(speed); 892 893 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap; 894 en_info(priv, "Setting Speed to %d\n", speed); 895 } 896 return proto_admin; 897 } 898 899 static int 900 mlx4_en_set_link_ksettings(struct net_device *dev, 901 const struct ethtool_link_ksettings *link_ksettings) 902 { 903 struct mlx4_en_priv *priv = netdev_priv(dev); 904 struct mlx4_ptys_reg ptys_reg; 905 __be32 proto_admin; 906 u8 cur_autoneg; 907 int ret; 908 909 u32 ptys_adv = ethtool2ptys_link_modes( 910 link_ksettings->link_modes.advertising, ADVERTISED); 911 const int speed = link_ksettings->base.speed; 912 913 en_dbg(DRV, priv, 914 "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n", 915 speed, __ETHTOOL_LINK_MODE_MASK_NBITS, 916 link_ksettings->link_modes.advertising, 917 link_ksettings->base.autoneg, 918 link_ksettings->base.duplex); 919 920 if (!(priv->mdev->dev->caps.flags2 & 921 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) || 922 (link_ksettings->base.duplex == DUPLEX_HALF)) 923 return -EINVAL; 924 925 memset(&ptys_reg, 0, sizeof(ptys_reg)); 926 ptys_reg.local_port = priv->port; 927 ptys_reg.proto_mask = MLX4_PTYS_EN; 928 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, 929 MLX4_ACCESS_REG_QUERY, &ptys_reg); 930 if (ret) { 931 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n", 932 ret); 933 return 0; 934 } 935 936 cur_autoneg = ptys_reg.flags & MLX4_PTYS_AN_DISABLE_ADMIN ? 937 AUTONEG_DISABLE : AUTONEG_ENABLE; 938 939 if (link_ksettings->base.autoneg == AUTONEG_DISABLE) { 940 proto_admin = speed_set_ptys_admin(priv, speed, 941 ptys_reg.eth_proto_cap); 942 if ((be32_to_cpu(proto_admin) & 943 (MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII) | 944 MLX4_PROT_MASK(MLX4_1000BASE_KX))) && 945 (ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP)) 946 ptys_reg.flags |= MLX4_PTYS_AN_DISABLE_ADMIN; 947 } else { 948 proto_admin = cpu_to_be32(ptys_adv); 949 ptys_reg.flags &= ~MLX4_PTYS_AN_DISABLE_ADMIN; 950 } 951 952 proto_admin &= ptys_reg.eth_proto_cap; 953 if (!proto_admin) { 954 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n"); 955 return -EINVAL; /* nothing to change due to bad input */ 956 } 957 958 if ((proto_admin == ptys_reg.eth_proto_admin) && 959 ((ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP) && 960 (link_ksettings->base.autoneg == cur_autoneg))) 961 return 0; /* Nothing to change */ 962 963 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n", 964 be32_to_cpu(proto_admin)); 965 966 ptys_reg.eth_proto_admin = proto_admin; 967 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE, 968 &ptys_reg); 969 if (ret) { 970 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)", 971 be32_to_cpu(ptys_reg.eth_proto_admin), ret); 972 return ret; 973 } 974 975 mutex_lock(&priv->mdev->state_lock); 976 if (priv->port_up) { 977 en_warn(priv, "Port link mode changed, restarting port...\n"); 978 mlx4_en_stop_port(dev, 1); 979 if (mlx4_en_start_port(dev)) 980 en_err(priv, "Failed restarting port %d\n", priv->port); 981 } 982 mutex_unlock(&priv->mdev->state_lock); 983 return 0; 984 } 985 986 static int mlx4_en_get_coalesce(struct net_device *dev, 987 struct ethtool_coalesce *coal) 988 { 989 struct mlx4_en_priv *priv = netdev_priv(dev); 990 991 coal->tx_coalesce_usecs = priv->tx_usecs; 992 coal->tx_max_coalesced_frames = priv->tx_frames; 993 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit; 994 995 coal->rx_coalesce_usecs = priv->rx_usecs; 996 coal->rx_max_coalesced_frames = priv->rx_frames; 997 998 coal->pkt_rate_low = priv->pkt_rate_low; 999 coal->rx_coalesce_usecs_low = priv->rx_usecs_low; 1000 coal->pkt_rate_high = priv->pkt_rate_high; 1001 coal->rx_coalesce_usecs_high = priv->rx_usecs_high; 1002 coal->rate_sample_interval = priv->sample_interval; 1003 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal; 1004 1005 return 0; 1006 } 1007 1008 static int mlx4_en_set_coalesce(struct net_device *dev, 1009 struct ethtool_coalesce *coal) 1010 { 1011 struct mlx4_en_priv *priv = netdev_priv(dev); 1012 1013 if (!coal->tx_max_coalesced_frames_irq) 1014 return -EINVAL; 1015 1016 priv->rx_frames = (coal->rx_max_coalesced_frames == 1017 MLX4_EN_AUTO_CONF) ? 1018 MLX4_EN_RX_COAL_TARGET : 1019 coal->rx_max_coalesced_frames; 1020 priv->rx_usecs = (coal->rx_coalesce_usecs == 1021 MLX4_EN_AUTO_CONF) ? 1022 MLX4_EN_RX_COAL_TIME : 1023 coal->rx_coalesce_usecs; 1024 1025 /* Setting TX coalescing parameters */ 1026 if (coal->tx_coalesce_usecs != priv->tx_usecs || 1027 coal->tx_max_coalesced_frames != priv->tx_frames) { 1028 priv->tx_usecs = coal->tx_coalesce_usecs; 1029 priv->tx_frames = coal->tx_max_coalesced_frames; 1030 } 1031 1032 /* Set adaptive coalescing params */ 1033 priv->pkt_rate_low = coal->pkt_rate_low; 1034 priv->rx_usecs_low = coal->rx_coalesce_usecs_low; 1035 priv->pkt_rate_high = coal->pkt_rate_high; 1036 priv->rx_usecs_high = coal->rx_coalesce_usecs_high; 1037 priv->sample_interval = coal->rate_sample_interval; 1038 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce; 1039 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq; 1040 1041 return mlx4_en_moderation_update(priv); 1042 } 1043 1044 static int mlx4_en_set_pauseparam(struct net_device *dev, 1045 struct ethtool_pauseparam *pause) 1046 { 1047 struct mlx4_en_priv *priv = netdev_priv(dev); 1048 struct mlx4_en_dev *mdev = priv->mdev; 1049 int err; 1050 1051 if (pause->autoneg) 1052 return -EINVAL; 1053 1054 priv->prof->tx_pause = pause->tx_pause != 0; 1055 priv->prof->rx_pause = pause->rx_pause != 0; 1056 err = mlx4_SET_PORT_general(mdev->dev, priv->port, 1057 priv->rx_skb_size + ETH_FCS_LEN, 1058 priv->prof->tx_pause, 1059 priv->prof->tx_ppp, 1060 priv->prof->rx_pause, 1061 priv->prof->rx_ppp); 1062 if (err) 1063 en_err(priv, "Failed setting pause params\n"); 1064 else 1065 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap, 1066 priv->prof->rx_ppp, 1067 priv->prof->rx_pause, 1068 priv->prof->tx_ppp, 1069 priv->prof->tx_pause); 1070 1071 return err; 1072 } 1073 1074 static void mlx4_en_get_pauseparam(struct net_device *dev, 1075 struct ethtool_pauseparam *pause) 1076 { 1077 struct mlx4_en_priv *priv = netdev_priv(dev); 1078 1079 pause->tx_pause = priv->prof->tx_pause; 1080 pause->rx_pause = priv->prof->rx_pause; 1081 } 1082 1083 static int mlx4_en_set_ringparam(struct net_device *dev, 1084 struct ethtool_ringparam *param) 1085 { 1086 struct mlx4_en_priv *priv = netdev_priv(dev); 1087 struct mlx4_en_dev *mdev = priv->mdev; 1088 struct mlx4_en_port_profile new_prof; 1089 struct mlx4_en_priv *tmp; 1090 u32 rx_size, tx_size; 1091 int port_up = 0; 1092 int err = 0; 1093 1094 if (param->rx_jumbo_pending || param->rx_mini_pending) 1095 return -EINVAL; 1096 1097 if (param->rx_pending < MLX4_EN_MIN_RX_SIZE) { 1098 en_warn(priv, "%s: rx_pending (%d) < min (%d)\n", 1099 __func__, param->rx_pending, 1100 MLX4_EN_MIN_RX_SIZE); 1101 return -EINVAL; 1102 } 1103 if (param->tx_pending < MLX4_EN_MIN_TX_SIZE) { 1104 en_warn(priv, "%s: tx_pending (%d) < min (%lu)\n", 1105 __func__, param->tx_pending, 1106 MLX4_EN_MIN_TX_SIZE); 1107 return -EINVAL; 1108 } 1109 1110 rx_size = roundup_pow_of_two(param->rx_pending); 1111 tx_size = roundup_pow_of_two(param->tx_pending); 1112 1113 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size : 1114 priv->rx_ring[0]->size) && 1115 tx_size == priv->tx_ring[TX][0]->size) 1116 return 0; 1117 1118 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 1119 if (!tmp) 1120 return -ENOMEM; 1121 1122 mutex_lock(&mdev->state_lock); 1123 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile)); 1124 new_prof.tx_ring_size = tx_size; 1125 new_prof.rx_ring_size = rx_size; 1126 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true); 1127 if (err) 1128 goto out; 1129 1130 if (priv->port_up) { 1131 port_up = 1; 1132 mlx4_en_stop_port(dev, 1); 1133 } 1134 1135 mlx4_en_safe_replace_resources(priv, tmp); 1136 1137 if (port_up) { 1138 err = mlx4_en_start_port(dev); 1139 if (err) 1140 en_err(priv, "Failed starting port\n"); 1141 } 1142 1143 err = mlx4_en_moderation_update(priv); 1144 out: 1145 kfree(tmp); 1146 mutex_unlock(&mdev->state_lock); 1147 return err; 1148 } 1149 1150 static void mlx4_en_get_ringparam(struct net_device *dev, 1151 struct ethtool_ringparam *param) 1152 { 1153 struct mlx4_en_priv *priv = netdev_priv(dev); 1154 1155 memset(param, 0, sizeof(*param)); 1156 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE; 1157 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE; 1158 param->rx_pending = priv->port_up ? 1159 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size; 1160 param->tx_pending = priv->tx_ring[TX][0]->size; 1161 } 1162 1163 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev) 1164 { 1165 struct mlx4_en_priv *priv = netdev_priv(dev); 1166 1167 return rounddown_pow_of_two(priv->rx_ring_num); 1168 } 1169 1170 static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev) 1171 { 1172 return MLX4_EN_RSS_KEY_SIZE; 1173 } 1174 1175 static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc) 1176 { 1177 struct mlx4_en_priv *priv = netdev_priv(dev); 1178 1179 /* check if requested function is supported by the device */ 1180 if (hfunc == ETH_RSS_HASH_TOP) { 1181 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) 1182 return -EINVAL; 1183 if (!(dev->features & NETIF_F_RXHASH)) 1184 en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n"); 1185 return 0; 1186 } else if (hfunc == ETH_RSS_HASH_XOR) { 1187 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR)) 1188 return -EINVAL; 1189 if (dev->features & NETIF_F_RXHASH) 1190 en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n"); 1191 return 0; 1192 } 1193 1194 return -EINVAL; 1195 } 1196 1197 static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key, 1198 u8 *hfunc) 1199 { 1200 struct mlx4_en_priv *priv = netdev_priv(dev); 1201 u32 n = mlx4_en_get_rxfh_indir_size(dev); 1202 u32 i, rss_rings; 1203 int err = 0; 1204 1205 rss_rings = priv->prof->rss_rings ?: n; 1206 rss_rings = rounddown_pow_of_two(rss_rings); 1207 1208 for (i = 0; i < n; i++) { 1209 if (!ring_index) 1210 break; 1211 ring_index[i] = i % rss_rings; 1212 } 1213 if (key) 1214 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE); 1215 if (hfunc) 1216 *hfunc = priv->rss_hash_fn; 1217 return err; 1218 } 1219 1220 static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index, 1221 const u8 *key, const u8 hfunc) 1222 { 1223 struct mlx4_en_priv *priv = netdev_priv(dev); 1224 u32 n = mlx4_en_get_rxfh_indir_size(dev); 1225 struct mlx4_en_dev *mdev = priv->mdev; 1226 int port_up = 0; 1227 int err = 0; 1228 int i; 1229 int rss_rings = 0; 1230 1231 /* Calculate RSS table size and make sure flows are spread evenly 1232 * between rings 1233 */ 1234 for (i = 0; i < n; i++) { 1235 if (!ring_index) 1236 break; 1237 if (i > 0 && !ring_index[i] && !rss_rings) 1238 rss_rings = i; 1239 1240 if (ring_index[i] != (i % (rss_rings ?: n))) 1241 return -EINVAL; 1242 } 1243 1244 if (!rss_rings) 1245 rss_rings = n; 1246 1247 /* RSS table size must be an order of 2 */ 1248 if (!is_power_of_2(rss_rings)) 1249 return -EINVAL; 1250 1251 if (hfunc != ETH_RSS_HASH_NO_CHANGE) { 1252 err = mlx4_en_check_rxfh_func(dev, hfunc); 1253 if (err) 1254 return err; 1255 } 1256 1257 mutex_lock(&mdev->state_lock); 1258 if (priv->port_up) { 1259 port_up = 1; 1260 mlx4_en_stop_port(dev, 1); 1261 } 1262 1263 if (ring_index) 1264 priv->prof->rss_rings = rss_rings; 1265 if (key) 1266 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE); 1267 if (hfunc != ETH_RSS_HASH_NO_CHANGE) 1268 priv->rss_hash_fn = hfunc; 1269 1270 if (port_up) { 1271 err = mlx4_en_start_port(dev); 1272 if (err) 1273 en_err(priv, "Failed starting port\n"); 1274 } 1275 1276 mutex_unlock(&mdev->state_lock); 1277 return err; 1278 } 1279 1280 #define all_zeros_or_all_ones(field) \ 1281 ((field) == 0 || (field) == (__force typeof(field))-1) 1282 1283 static int mlx4_en_validate_flow(struct net_device *dev, 1284 struct ethtool_rxnfc *cmd) 1285 { 1286 struct ethtool_usrip4_spec *l3_mask; 1287 struct ethtool_tcpip4_spec *l4_mask; 1288 struct ethhdr *eth_mask; 1289 1290 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1291 return -EINVAL; 1292 1293 if (cmd->fs.flow_type & FLOW_MAC_EXT) { 1294 /* dest mac mask must be ff:ff:ff:ff:ff:ff */ 1295 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest)) 1296 return -EINVAL; 1297 } 1298 1299 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1300 case TCP_V4_FLOW: 1301 case UDP_V4_FLOW: 1302 if (cmd->fs.m_u.tcp_ip4_spec.tos) 1303 return -EINVAL; 1304 l4_mask = &cmd->fs.m_u.tcp_ip4_spec; 1305 /* don't allow mask which isn't all 0 or 1 */ 1306 if (!all_zeros_or_all_ones(l4_mask->ip4src) || 1307 !all_zeros_or_all_ones(l4_mask->ip4dst) || 1308 !all_zeros_or_all_ones(l4_mask->psrc) || 1309 !all_zeros_or_all_ones(l4_mask->pdst)) 1310 return -EINVAL; 1311 break; 1312 case IP_USER_FLOW: 1313 l3_mask = &cmd->fs.m_u.usr_ip4_spec; 1314 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto || 1315 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 || 1316 (!l3_mask->ip4src && !l3_mask->ip4dst) || 1317 !all_zeros_or_all_ones(l3_mask->ip4src) || 1318 !all_zeros_or_all_ones(l3_mask->ip4dst)) 1319 return -EINVAL; 1320 break; 1321 case ETHER_FLOW: 1322 eth_mask = &cmd->fs.m_u.ether_spec; 1323 /* source mac mask must not be set */ 1324 if (!is_zero_ether_addr(eth_mask->h_source)) 1325 return -EINVAL; 1326 1327 /* dest mac mask must be ff:ff:ff:ff:ff:ff */ 1328 if (!is_broadcast_ether_addr(eth_mask->h_dest)) 1329 return -EINVAL; 1330 1331 if (!all_zeros_or_all_ones(eth_mask->h_proto)) 1332 return -EINVAL; 1333 break; 1334 default: 1335 return -EINVAL; 1336 } 1337 1338 if ((cmd->fs.flow_type & FLOW_EXT)) { 1339 if (cmd->fs.m_ext.vlan_etype || 1340 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == 1341 0 || 1342 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == 1343 cpu_to_be16(VLAN_VID_MASK))) 1344 return -EINVAL; 1345 1346 if (cmd->fs.m_ext.vlan_tci) { 1347 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID) 1348 return -EINVAL; 1349 1350 } 1351 } 1352 1353 return 0; 1354 } 1355 1356 static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd, 1357 struct list_head *rule_list_h, 1358 struct mlx4_spec_list *spec_l2, 1359 unsigned char *mac) 1360 { 1361 int err = 0; 1362 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16); 1363 1364 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH; 1365 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN); 1366 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN); 1367 1368 if ((cmd->fs.flow_type & FLOW_EXT) && 1369 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) { 1370 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci; 1371 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK); 1372 } 1373 1374 list_add_tail(&spec_l2->list, rule_list_h); 1375 1376 return err; 1377 } 1378 1379 static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv, 1380 struct ethtool_rxnfc *cmd, 1381 struct list_head *rule_list_h, 1382 struct mlx4_spec_list *spec_l2, 1383 __be32 ipv4_dst) 1384 { 1385 #ifdef CONFIG_INET 1386 unsigned char mac[ETH_ALEN]; 1387 1388 if (!ipv4_is_multicast(ipv4_dst)) { 1389 if (cmd->fs.flow_type & FLOW_MAC_EXT) 1390 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN); 1391 else 1392 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN); 1393 } else { 1394 ip_eth_mc_map(ipv4_dst, mac); 1395 } 1396 1397 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]); 1398 #else 1399 return -EINVAL; 1400 #endif 1401 } 1402 1403 static int add_ip_rule(struct mlx4_en_priv *priv, 1404 struct ethtool_rxnfc *cmd, 1405 struct list_head *list_h) 1406 { 1407 int err; 1408 struct mlx4_spec_list *spec_l2 = NULL; 1409 struct mlx4_spec_list *spec_l3 = NULL; 1410 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec; 1411 1412 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); 1413 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1414 if (!spec_l2 || !spec_l3) { 1415 err = -ENOMEM; 1416 goto free_spec; 1417 } 1418 1419 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2, 1420 cmd->fs.h_u. 1421 usr_ip4_spec.ip4dst); 1422 if (err) 1423 goto free_spec; 1424 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; 1425 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src; 1426 if (l3_mask->ip4src) 1427 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; 1428 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst; 1429 if (l3_mask->ip4dst) 1430 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; 1431 list_add_tail(&spec_l3->list, list_h); 1432 1433 return 0; 1434 1435 free_spec: 1436 kfree(spec_l2); 1437 kfree(spec_l3); 1438 return err; 1439 } 1440 1441 static int add_tcp_udp_rule(struct mlx4_en_priv *priv, 1442 struct ethtool_rxnfc *cmd, 1443 struct list_head *list_h, int proto) 1444 { 1445 int err; 1446 struct mlx4_spec_list *spec_l2 = NULL; 1447 struct mlx4_spec_list *spec_l3 = NULL; 1448 struct mlx4_spec_list *spec_l4 = NULL; 1449 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec; 1450 1451 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1452 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); 1453 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL); 1454 if (!spec_l2 || !spec_l3 || !spec_l4) { 1455 err = -ENOMEM; 1456 goto free_spec; 1457 } 1458 1459 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; 1460 1461 if (proto == TCP_V4_FLOW) { 1462 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, 1463 spec_l2, 1464 cmd->fs.h_u. 1465 tcp_ip4_spec.ip4dst); 1466 if (err) 1467 goto free_spec; 1468 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP; 1469 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src; 1470 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst; 1471 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc; 1472 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst; 1473 } else { 1474 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, 1475 spec_l2, 1476 cmd->fs.h_u. 1477 udp_ip4_spec.ip4dst); 1478 if (err) 1479 goto free_spec; 1480 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP; 1481 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src; 1482 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst; 1483 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc; 1484 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst; 1485 } 1486 1487 if (l4_mask->ip4src) 1488 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; 1489 if (l4_mask->ip4dst) 1490 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; 1491 1492 if (l4_mask->psrc) 1493 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK; 1494 if (l4_mask->pdst) 1495 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK; 1496 1497 list_add_tail(&spec_l3->list, list_h); 1498 list_add_tail(&spec_l4->list, list_h); 1499 1500 return 0; 1501 1502 free_spec: 1503 kfree(spec_l2); 1504 kfree(spec_l3); 1505 kfree(spec_l4); 1506 return err; 1507 } 1508 1509 static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev, 1510 struct ethtool_rxnfc *cmd, 1511 struct list_head *rule_list_h) 1512 { 1513 int err; 1514 struct ethhdr *eth_spec; 1515 struct mlx4_spec_list *spec_l2; 1516 struct mlx4_en_priv *priv = netdev_priv(dev); 1517 1518 err = mlx4_en_validate_flow(dev, cmd); 1519 if (err) 1520 return err; 1521 1522 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1523 case ETHER_FLOW: 1524 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1525 if (!spec_l2) 1526 return -ENOMEM; 1527 1528 eth_spec = &cmd->fs.h_u.ether_spec; 1529 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, 1530 ð_spec->h_dest[0]); 1531 spec_l2->eth.ether_type = eth_spec->h_proto; 1532 if (eth_spec->h_proto) 1533 spec_l2->eth.ether_type_enable = 1; 1534 break; 1535 case IP_USER_FLOW: 1536 err = add_ip_rule(priv, cmd, rule_list_h); 1537 break; 1538 case TCP_V4_FLOW: 1539 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW); 1540 break; 1541 case UDP_V4_FLOW: 1542 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW); 1543 break; 1544 } 1545 1546 return err; 1547 } 1548 1549 static int mlx4_en_flow_replace(struct net_device *dev, 1550 struct ethtool_rxnfc *cmd) 1551 { 1552 int err; 1553 struct mlx4_en_priv *priv = netdev_priv(dev); 1554 struct ethtool_flow_id *loc_rule; 1555 struct mlx4_spec_list *spec, *tmp_spec; 1556 u32 qpn; 1557 u64 reg_id; 1558 1559 struct mlx4_net_trans_rule rule = { 1560 .queue_mode = MLX4_NET_TRANS_Q_FIFO, 1561 .exclusive = 0, 1562 .allow_loopback = 1, 1563 .promisc_mode = MLX4_FS_REGULAR, 1564 }; 1565 1566 rule.port = priv->port; 1567 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location; 1568 INIT_LIST_HEAD(&rule.list); 1569 1570 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */ 1571 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC) 1572 qpn = priv->drop_qp.qpn; 1573 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) { 1574 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1); 1575 } else { 1576 if (cmd->fs.ring_cookie >= priv->rx_ring_num) { 1577 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n", 1578 cmd->fs.ring_cookie); 1579 return -EINVAL; 1580 } 1581 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn; 1582 if (!qpn) { 1583 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n", 1584 cmd->fs.ring_cookie); 1585 return -EINVAL; 1586 } 1587 } 1588 rule.qpn = qpn; 1589 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list); 1590 if (err) 1591 goto out_free_list; 1592 1593 loc_rule = &priv->ethtool_rules[cmd->fs.location]; 1594 if (loc_rule->id) { 1595 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id); 1596 if (err) { 1597 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n", 1598 cmd->fs.location, loc_rule->id); 1599 goto out_free_list; 1600 } 1601 loc_rule->id = 0; 1602 memset(&loc_rule->flow_spec, 0, 1603 sizeof(struct ethtool_rx_flow_spec)); 1604 list_del(&loc_rule->list); 1605 } 1606 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id); 1607 if (err) { 1608 en_err(priv, "Fail to attach network rule at location %d\n", 1609 cmd->fs.location); 1610 goto out_free_list; 1611 } 1612 loc_rule->id = reg_id; 1613 memcpy(&loc_rule->flow_spec, &cmd->fs, 1614 sizeof(struct ethtool_rx_flow_spec)); 1615 list_add_tail(&loc_rule->list, &priv->ethtool_list); 1616 1617 out_free_list: 1618 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) { 1619 list_del(&spec->list); 1620 kfree(spec); 1621 } 1622 return err; 1623 } 1624 1625 static int mlx4_en_flow_detach(struct net_device *dev, 1626 struct ethtool_rxnfc *cmd) 1627 { 1628 int err = 0; 1629 struct ethtool_flow_id *rule; 1630 struct mlx4_en_priv *priv = netdev_priv(dev); 1631 1632 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1633 return -EINVAL; 1634 1635 rule = &priv->ethtool_rules[cmd->fs.location]; 1636 if (!rule->id) { 1637 err = -ENOENT; 1638 goto out; 1639 } 1640 1641 err = mlx4_flow_detach(priv->mdev->dev, rule->id); 1642 if (err) { 1643 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n", 1644 cmd->fs.location, rule->id); 1645 goto out; 1646 } 1647 rule->id = 0; 1648 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec)); 1649 list_del(&rule->list); 1650 out: 1651 return err; 1652 1653 } 1654 1655 static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1656 int loc) 1657 { 1658 int err = 0; 1659 struct ethtool_flow_id *rule; 1660 struct mlx4_en_priv *priv = netdev_priv(dev); 1661 1662 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1663 return -EINVAL; 1664 1665 rule = &priv->ethtool_rules[loc]; 1666 if (rule->id) 1667 memcpy(&cmd->fs, &rule->flow_spec, 1668 sizeof(struct ethtool_rx_flow_spec)); 1669 else 1670 err = -ENOENT; 1671 1672 return err; 1673 } 1674 1675 static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv) 1676 { 1677 1678 int i, res = 0; 1679 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 1680 if (priv->ethtool_rules[i].id) 1681 res++; 1682 } 1683 return res; 1684 1685 } 1686 1687 static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1688 u32 *rule_locs) 1689 { 1690 struct mlx4_en_priv *priv = netdev_priv(dev); 1691 struct mlx4_en_dev *mdev = priv->mdev; 1692 int err = 0; 1693 int i = 0, priority = 0; 1694 1695 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT || 1696 cmd->cmd == ETHTOOL_GRXCLSRULE || 1697 cmd->cmd == ETHTOOL_GRXCLSRLALL) && 1698 (mdev->dev->caps.steering_mode != 1699 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)) 1700 return -EINVAL; 1701 1702 switch (cmd->cmd) { 1703 case ETHTOOL_GRXRINGS: 1704 cmd->data = priv->rx_ring_num; 1705 break; 1706 case ETHTOOL_GRXCLSRLCNT: 1707 cmd->rule_cnt = mlx4_en_get_num_flows(priv); 1708 break; 1709 case ETHTOOL_GRXCLSRULE: 1710 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location); 1711 break; 1712 case ETHTOOL_GRXCLSRLALL: 1713 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) { 1714 err = mlx4_en_get_flow(dev, cmd, i); 1715 if (!err) 1716 rule_locs[priority++] = i; 1717 i++; 1718 } 1719 err = 0; 1720 break; 1721 default: 1722 err = -EOPNOTSUPP; 1723 break; 1724 } 1725 1726 return err; 1727 } 1728 1729 static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1730 { 1731 int err = 0; 1732 struct mlx4_en_priv *priv = netdev_priv(dev); 1733 struct mlx4_en_dev *mdev = priv->mdev; 1734 1735 if (mdev->dev->caps.steering_mode != 1736 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up) 1737 return -EINVAL; 1738 1739 switch (cmd->cmd) { 1740 case ETHTOOL_SRXCLSRLINS: 1741 err = mlx4_en_flow_replace(dev, cmd); 1742 break; 1743 case ETHTOOL_SRXCLSRLDEL: 1744 err = mlx4_en_flow_detach(dev, cmd); 1745 break; 1746 default: 1747 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd); 1748 return -EINVAL; 1749 } 1750 1751 return err; 1752 } 1753 1754 static int mlx4_en_get_max_num_rx_rings(struct net_device *dev) 1755 { 1756 return min_t(int, num_online_cpus(), MAX_RX_RINGS); 1757 } 1758 1759 static void mlx4_en_get_channels(struct net_device *dev, 1760 struct ethtool_channels *channel) 1761 { 1762 struct mlx4_en_priv *priv = netdev_priv(dev); 1763 1764 channel->max_rx = mlx4_en_get_max_num_rx_rings(dev); 1765 channel->max_tx = priv->mdev->profile.max_num_tx_rings_p_up; 1766 1767 channel->rx_count = priv->rx_ring_num; 1768 channel->tx_count = priv->tx_ring_num[TX] / 1769 priv->prof->num_up; 1770 } 1771 1772 static int mlx4_en_set_channels(struct net_device *dev, 1773 struct ethtool_channels *channel) 1774 { 1775 struct mlx4_en_priv *priv = netdev_priv(dev); 1776 struct mlx4_en_dev *mdev = priv->mdev; 1777 struct mlx4_en_port_profile new_prof; 1778 struct mlx4_en_priv *tmp; 1779 int port_up = 0; 1780 int xdp_count; 1781 int err = 0; 1782 u8 up; 1783 1784 if (!channel->tx_count || !channel->rx_count) 1785 return -EINVAL; 1786 1787 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 1788 if (!tmp) 1789 return -ENOMEM; 1790 1791 mutex_lock(&mdev->state_lock); 1792 xdp_count = priv->tx_ring_num[TX_XDP] ? channel->rx_count : 0; 1793 if (channel->tx_count * priv->prof->num_up + xdp_count > 1794 priv->mdev->profile.max_num_tx_rings_p_up * priv->prof->num_up) { 1795 err = -EINVAL; 1796 en_err(priv, 1797 "Total number of TX and XDP rings (%d) exceeds the maximum supported (%d)\n", 1798 channel->tx_count * priv->prof->num_up + xdp_count, 1799 MAX_TX_RINGS); 1800 goto out; 1801 } 1802 1803 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile)); 1804 new_prof.num_tx_rings_p_up = channel->tx_count; 1805 new_prof.tx_ring_num[TX] = channel->tx_count * priv->prof->num_up; 1806 new_prof.tx_ring_num[TX_XDP] = xdp_count; 1807 new_prof.rx_ring_num = channel->rx_count; 1808 1809 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true); 1810 if (err) 1811 goto out; 1812 1813 if (priv->port_up) { 1814 port_up = 1; 1815 mlx4_en_stop_port(dev, 1); 1816 } 1817 1818 mlx4_en_safe_replace_resources(priv, tmp); 1819 1820 netif_set_real_num_rx_queues(dev, priv->rx_ring_num); 1821 1822 up = (priv->prof->num_up == MLX4_EN_NUM_UP_LOW) ? 1823 0 : priv->prof->num_up; 1824 mlx4_en_setup_tc(dev, up); 1825 1826 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num[TX]); 1827 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num); 1828 1829 if (port_up) { 1830 err = mlx4_en_start_port(dev); 1831 if (err) 1832 en_err(priv, "Failed starting port\n"); 1833 } 1834 1835 err = mlx4_en_moderation_update(priv); 1836 out: 1837 mutex_unlock(&mdev->state_lock); 1838 kfree(tmp); 1839 return err; 1840 } 1841 1842 static int mlx4_en_get_ts_info(struct net_device *dev, 1843 struct ethtool_ts_info *info) 1844 { 1845 struct mlx4_en_priv *priv = netdev_priv(dev); 1846 struct mlx4_en_dev *mdev = priv->mdev; 1847 int ret; 1848 1849 ret = ethtool_op_get_ts_info(dev, info); 1850 if (ret) 1851 return ret; 1852 1853 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 1854 info->so_timestamping |= 1855 SOF_TIMESTAMPING_TX_HARDWARE | 1856 SOF_TIMESTAMPING_RX_HARDWARE | 1857 SOF_TIMESTAMPING_RAW_HARDWARE; 1858 1859 info->tx_types = 1860 (1 << HWTSTAMP_TX_OFF) | 1861 (1 << HWTSTAMP_TX_ON); 1862 1863 info->rx_filters = 1864 (1 << HWTSTAMP_FILTER_NONE) | 1865 (1 << HWTSTAMP_FILTER_ALL); 1866 1867 if (mdev->ptp_clock) 1868 info->phc_index = ptp_clock_index(mdev->ptp_clock); 1869 } 1870 1871 return ret; 1872 } 1873 1874 static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags) 1875 { 1876 struct mlx4_en_priv *priv = netdev_priv(dev); 1877 struct mlx4_en_dev *mdev = priv->mdev; 1878 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); 1879 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); 1880 bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV); 1881 bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV); 1882 int i; 1883 int ret = 0; 1884 1885 if (bf_enabled_new != bf_enabled_old) { 1886 int t; 1887 1888 if (bf_enabled_new) { 1889 bool bf_supported = true; 1890 1891 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) 1892 for (i = 0; i < priv->tx_ring_num[t]; i++) 1893 bf_supported &= 1894 priv->tx_ring[t][i]->bf_alloced; 1895 1896 if (!bf_supported) { 1897 en_err(priv, "BlueFlame is not supported\n"); 1898 return -EINVAL; 1899 } 1900 1901 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME; 1902 } else { 1903 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 1904 } 1905 1906 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) 1907 for (i = 0; i < priv->tx_ring_num[t]; i++) 1908 priv->tx_ring[t][i]->bf_enabled = 1909 bf_enabled_new; 1910 1911 en_info(priv, "BlueFlame %s\n", 1912 bf_enabled_new ? "Enabled" : "Disabled"); 1913 } 1914 1915 if (phv_enabled_new != phv_enabled_old) { 1916 ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new); 1917 if (ret) 1918 return ret; 1919 else if (phv_enabled_new) 1920 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV; 1921 else 1922 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV; 1923 en_info(priv, "PHV bit %s\n", 1924 phv_enabled_new ? "Enabled" : "Disabled"); 1925 } 1926 return 0; 1927 } 1928 1929 static u32 mlx4_en_get_priv_flags(struct net_device *dev) 1930 { 1931 struct mlx4_en_priv *priv = netdev_priv(dev); 1932 1933 return priv->pflags; 1934 } 1935 1936 static int mlx4_en_get_tunable(struct net_device *dev, 1937 const struct ethtool_tunable *tuna, 1938 void *data) 1939 { 1940 const struct mlx4_en_priv *priv = netdev_priv(dev); 1941 int ret = 0; 1942 1943 switch (tuna->id) { 1944 case ETHTOOL_TX_COPYBREAK: 1945 *(u32 *)data = priv->prof->inline_thold; 1946 break; 1947 default: 1948 ret = -EINVAL; 1949 break; 1950 } 1951 1952 return ret; 1953 } 1954 1955 static int mlx4_en_set_tunable(struct net_device *dev, 1956 const struct ethtool_tunable *tuna, 1957 const void *data) 1958 { 1959 struct mlx4_en_priv *priv = netdev_priv(dev); 1960 int val, ret = 0; 1961 1962 switch (tuna->id) { 1963 case ETHTOOL_TX_COPYBREAK: 1964 val = *(u32 *)data; 1965 if (val < MIN_PKT_LEN || val > MAX_INLINE) 1966 ret = -EINVAL; 1967 else 1968 priv->prof->inline_thold = val; 1969 break; 1970 default: 1971 ret = -EINVAL; 1972 break; 1973 } 1974 1975 return ret; 1976 } 1977 1978 static int mlx4_en_get_module_info(struct net_device *dev, 1979 struct ethtool_modinfo *modinfo) 1980 { 1981 struct mlx4_en_priv *priv = netdev_priv(dev); 1982 struct mlx4_en_dev *mdev = priv->mdev; 1983 int ret; 1984 u8 data[4]; 1985 1986 /* Read first 2 bytes to get Module & REV ID */ 1987 ret = mlx4_get_module_info(mdev->dev, priv->port, 1988 0/*offset*/, 2/*size*/, data); 1989 if (ret < 2) 1990 return -EIO; 1991 1992 switch (data[0] /* identifier */) { 1993 case MLX4_MODULE_ID_QSFP: 1994 modinfo->type = ETH_MODULE_SFF_8436; 1995 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 1996 break; 1997 case MLX4_MODULE_ID_QSFP_PLUS: 1998 if (data[1] >= 0x3) { /* revision id */ 1999 modinfo->type = ETH_MODULE_SFF_8636; 2000 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2001 } else { 2002 modinfo->type = ETH_MODULE_SFF_8436; 2003 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2004 } 2005 break; 2006 case MLX4_MODULE_ID_QSFP28: 2007 modinfo->type = ETH_MODULE_SFF_8636; 2008 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2009 break; 2010 case MLX4_MODULE_ID_SFP: 2011 modinfo->type = ETH_MODULE_SFF_8472; 2012 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2013 break; 2014 default: 2015 return -EINVAL; 2016 } 2017 2018 return 0; 2019 } 2020 2021 static int mlx4_en_get_module_eeprom(struct net_device *dev, 2022 struct ethtool_eeprom *ee, 2023 u8 *data) 2024 { 2025 struct mlx4_en_priv *priv = netdev_priv(dev); 2026 struct mlx4_en_dev *mdev = priv->mdev; 2027 int offset = ee->offset; 2028 int i = 0, ret; 2029 2030 if (ee->len == 0) 2031 return -EINVAL; 2032 2033 memset(data, 0, ee->len); 2034 2035 while (i < ee->len) { 2036 en_dbg(DRV, priv, 2037 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n", 2038 i, offset, ee->len - i); 2039 2040 ret = mlx4_get_module_info(mdev->dev, priv->port, 2041 offset, ee->len - i, data + i); 2042 2043 if (!ret) /* Done reading */ 2044 return 0; 2045 2046 if (ret < 0) { 2047 en_err(priv, 2048 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n", 2049 i, offset, ee->len - i, ret); 2050 return 0; 2051 } 2052 2053 i += ret; 2054 offset += ret; 2055 } 2056 return 0; 2057 } 2058 2059 static int mlx4_en_set_phys_id(struct net_device *dev, 2060 enum ethtool_phys_id_state state) 2061 { 2062 int err; 2063 u16 beacon_duration; 2064 struct mlx4_en_priv *priv = netdev_priv(dev); 2065 struct mlx4_en_dev *mdev = priv->mdev; 2066 2067 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON)) 2068 return -EOPNOTSUPP; 2069 2070 switch (state) { 2071 case ETHTOOL_ID_ACTIVE: 2072 beacon_duration = PORT_BEACON_MAX_LIMIT; 2073 break; 2074 case ETHTOOL_ID_INACTIVE: 2075 beacon_duration = 0; 2076 break; 2077 default: 2078 return -EOPNOTSUPP; 2079 } 2080 2081 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration); 2082 return err; 2083 } 2084 2085 const struct ethtool_ops mlx4_en_ethtool_ops = { 2086 .get_drvinfo = mlx4_en_get_drvinfo, 2087 .get_link_ksettings = mlx4_en_get_link_ksettings, 2088 .set_link_ksettings = mlx4_en_set_link_ksettings, 2089 .get_link = ethtool_op_get_link, 2090 .get_strings = mlx4_en_get_strings, 2091 .get_sset_count = mlx4_en_get_sset_count, 2092 .get_ethtool_stats = mlx4_en_get_ethtool_stats, 2093 .self_test = mlx4_en_self_test, 2094 .set_phys_id = mlx4_en_set_phys_id, 2095 .get_wol = mlx4_en_get_wol, 2096 .set_wol = mlx4_en_set_wol, 2097 .get_msglevel = mlx4_en_get_msglevel, 2098 .set_msglevel = mlx4_en_set_msglevel, 2099 .get_coalesce = mlx4_en_get_coalesce, 2100 .set_coalesce = mlx4_en_set_coalesce, 2101 .get_pauseparam = mlx4_en_get_pauseparam, 2102 .set_pauseparam = mlx4_en_set_pauseparam, 2103 .get_ringparam = mlx4_en_get_ringparam, 2104 .set_ringparam = mlx4_en_set_ringparam, 2105 .get_rxnfc = mlx4_en_get_rxnfc, 2106 .set_rxnfc = mlx4_en_set_rxnfc, 2107 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size, 2108 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size, 2109 .get_rxfh = mlx4_en_get_rxfh, 2110 .set_rxfh = mlx4_en_set_rxfh, 2111 .get_channels = mlx4_en_get_channels, 2112 .set_channels = mlx4_en_set_channels, 2113 .get_ts_info = mlx4_en_get_ts_info, 2114 .set_priv_flags = mlx4_en_set_priv_flags, 2115 .get_priv_flags = mlx4_en_get_priv_flags, 2116 .get_tunable = mlx4_en_get_tunable, 2117 .set_tunable = mlx4_en_set_tunable, 2118 .get_module_info = mlx4_en_get_module_info, 2119 .get_module_eeprom = mlx4_en_get_module_eeprom 2120 }; 2121 2122 2123 2124 2125 2126