1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/ethtool.h> 36 #include <linux/netdevice.h> 37 #include <linux/mlx4/driver.h> 38 #include <linux/mlx4/device.h> 39 #include <linux/in.h> 40 #include <net/ip.h> 41 #include <linux/bitmap.h> 42 43 #include "mlx4_en.h" 44 #include "en_port.h" 45 46 #define EN_ETHTOOL_QP_ATTACH (1ull << 63) 47 #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff) 48 #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff) 49 50 static int mlx4_en_moderation_update(struct mlx4_en_priv *priv) 51 { 52 int i; 53 int err = 0; 54 55 for (i = 0; i < priv->tx_ring_num; i++) { 56 priv->tx_cq[i]->moder_cnt = priv->tx_frames; 57 priv->tx_cq[i]->moder_time = priv->tx_usecs; 58 if (priv->port_up) { 59 err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]); 60 if (err) 61 return err; 62 } 63 } 64 65 if (priv->adaptive_rx_coal) 66 return 0; 67 68 for (i = 0; i < priv->rx_ring_num; i++) { 69 priv->rx_cq[i]->moder_cnt = priv->rx_frames; 70 priv->rx_cq[i]->moder_time = priv->rx_usecs; 71 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; 72 if (priv->port_up) { 73 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]); 74 if (err) 75 return err; 76 } 77 } 78 79 return err; 80 } 81 82 static void 83 mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) 84 { 85 struct mlx4_en_priv *priv = netdev_priv(dev); 86 struct mlx4_en_dev *mdev = priv->mdev; 87 88 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); 89 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")", 90 sizeof(drvinfo->version)); 91 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 92 "%d.%d.%d", 93 (u16) (mdev->dev->caps.fw_ver >> 32), 94 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff), 95 (u16) (mdev->dev->caps.fw_ver & 0xffff)); 96 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev), 97 sizeof(drvinfo->bus_info)); 98 drvinfo->n_stats = 0; 99 drvinfo->regdump_len = 0; 100 drvinfo->eedump_len = 0; 101 } 102 103 static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = { 104 "blueflame", 105 "phv-bit" 106 }; 107 108 static const char main_strings[][ETH_GSTRING_LEN] = { 109 /* main statistics */ 110 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", 111 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", 112 "rx_length_errors", "rx_over_errors", "rx_crc_errors", 113 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", 114 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", 115 "tx_heartbeat_errors", "tx_window_errors", 116 117 /* port statistics */ 118 "tso_packets", 119 "xmit_more", 120 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed", 121 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload", 122 123 /* pf statistics */ 124 "pf_rx_packets", 125 "pf_rx_bytes", 126 "pf_tx_packets", 127 "pf_tx_bytes", 128 129 /* priority flow control statistics rx */ 130 "rx_pause_prio_0", "rx_pause_duration_prio_0", 131 "rx_pause_transition_prio_0", 132 "rx_pause_prio_1", "rx_pause_duration_prio_1", 133 "rx_pause_transition_prio_1", 134 "rx_pause_prio_2", "rx_pause_duration_prio_2", 135 "rx_pause_transition_prio_2", 136 "rx_pause_prio_3", "rx_pause_duration_prio_3", 137 "rx_pause_transition_prio_3", 138 "rx_pause_prio_4", "rx_pause_duration_prio_4", 139 "rx_pause_transition_prio_4", 140 "rx_pause_prio_5", "rx_pause_duration_prio_5", 141 "rx_pause_transition_prio_5", 142 "rx_pause_prio_6", "rx_pause_duration_prio_6", 143 "rx_pause_transition_prio_6", 144 "rx_pause_prio_7", "rx_pause_duration_prio_7", 145 "rx_pause_transition_prio_7", 146 147 /* flow control statistics rx */ 148 "rx_pause", "rx_pause_duration", "rx_pause_transition", 149 150 /* priority flow control statistics tx */ 151 "tx_pause_prio_0", "tx_pause_duration_prio_0", 152 "tx_pause_transition_prio_0", 153 "tx_pause_prio_1", "tx_pause_duration_prio_1", 154 "tx_pause_transition_prio_1", 155 "tx_pause_prio_2", "tx_pause_duration_prio_2", 156 "tx_pause_transition_prio_2", 157 "tx_pause_prio_3", "tx_pause_duration_prio_3", 158 "tx_pause_transition_prio_3", 159 "tx_pause_prio_4", "tx_pause_duration_prio_4", 160 "tx_pause_transition_prio_4", 161 "tx_pause_prio_5", "tx_pause_duration_prio_5", 162 "tx_pause_transition_prio_5", 163 "tx_pause_prio_6", "tx_pause_duration_prio_6", 164 "tx_pause_transition_prio_6", 165 "tx_pause_prio_7", "tx_pause_duration_prio_7", 166 "tx_pause_transition_prio_7", 167 168 /* flow control statistics tx */ 169 "tx_pause", "tx_pause_duration", "tx_pause_transition", 170 171 /* packet statistics */ 172 "rx_multicast_packets", 173 "rx_broadcast_packets", 174 "rx_jabbers", 175 "rx_in_range_length_error", 176 "rx_out_range_length_error", 177 "tx_multicast_packets", 178 "tx_broadcast_packets", 179 "rx_prio_0_packets", "rx_prio_0_bytes", 180 "rx_prio_1_packets", "rx_prio_1_bytes", 181 "rx_prio_2_packets", "rx_prio_2_bytes", 182 "rx_prio_3_packets", "rx_prio_3_bytes", 183 "rx_prio_4_packets", "rx_prio_4_bytes", 184 "rx_prio_5_packets", "rx_prio_5_bytes", 185 "rx_prio_6_packets", "rx_prio_6_bytes", 186 "rx_prio_7_packets", "rx_prio_7_bytes", 187 "rx_novlan_packets", "rx_novlan_bytes", 188 "tx_prio_0_packets", "tx_prio_0_bytes", 189 "tx_prio_1_packets", "tx_prio_1_bytes", 190 "tx_prio_2_packets", "tx_prio_2_bytes", 191 "tx_prio_3_packets", "tx_prio_3_bytes", 192 "tx_prio_4_packets", "tx_prio_4_bytes", 193 "tx_prio_5_packets", "tx_prio_5_bytes", 194 "tx_prio_6_packets", "tx_prio_6_bytes", 195 "tx_prio_7_packets", "tx_prio_7_bytes", 196 "tx_novlan_packets", "tx_novlan_bytes", 197 198 }; 199 200 static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= { 201 "Interrupt Test", 202 "Link Test", 203 "Speed Test", 204 "Register Test", 205 "Loopback Test", 206 }; 207 208 static u32 mlx4_en_get_msglevel(struct net_device *dev) 209 { 210 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable; 211 } 212 213 static void mlx4_en_set_msglevel(struct net_device *dev, u32 val) 214 { 215 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val; 216 } 217 218 static void mlx4_en_get_wol(struct net_device *netdev, 219 struct ethtool_wolinfo *wol) 220 { 221 struct mlx4_en_priv *priv = netdev_priv(netdev); 222 int err = 0; 223 u64 config = 0; 224 u64 mask; 225 226 if ((priv->port < 1) || (priv->port > 2)) { 227 en_err(priv, "Failed to get WoL information\n"); 228 return; 229 } 230 231 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : 232 MLX4_DEV_CAP_FLAG_WOL_PORT2; 233 234 if (!(priv->mdev->dev->caps.flags & mask)) { 235 wol->supported = 0; 236 wol->wolopts = 0; 237 return; 238 } 239 240 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); 241 if (err) { 242 en_err(priv, "Failed to get WoL information\n"); 243 return; 244 } 245 246 if (config & MLX4_EN_WOL_MAGIC) 247 wol->supported = WAKE_MAGIC; 248 else 249 wol->supported = 0; 250 251 if (config & MLX4_EN_WOL_ENABLED) 252 wol->wolopts = WAKE_MAGIC; 253 else 254 wol->wolopts = 0; 255 } 256 257 static int mlx4_en_set_wol(struct net_device *netdev, 258 struct ethtool_wolinfo *wol) 259 { 260 struct mlx4_en_priv *priv = netdev_priv(netdev); 261 u64 config = 0; 262 int err = 0; 263 u64 mask; 264 265 if ((priv->port < 1) || (priv->port > 2)) 266 return -EOPNOTSUPP; 267 268 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : 269 MLX4_DEV_CAP_FLAG_WOL_PORT2; 270 271 if (!(priv->mdev->dev->caps.flags & mask)) 272 return -EOPNOTSUPP; 273 274 if (wol->supported & ~WAKE_MAGIC) 275 return -EINVAL; 276 277 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); 278 if (err) { 279 en_err(priv, "Failed to get WoL info, unable to modify\n"); 280 return err; 281 } 282 283 if (wol->wolopts & WAKE_MAGIC) { 284 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED | 285 MLX4_EN_WOL_MAGIC; 286 } else { 287 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC); 288 config |= MLX4_EN_WOL_DO_MODIFY; 289 } 290 291 err = mlx4_wol_write(priv->mdev->dev, config, priv->port); 292 if (err) 293 en_err(priv, "Failed to set WoL information\n"); 294 295 return err; 296 } 297 298 struct bitmap_iterator { 299 unsigned long *stats_bitmap; 300 unsigned int count; 301 unsigned int iterator; 302 bool advance_array; /* if set, force no increments */ 303 }; 304 305 static inline void bitmap_iterator_init(struct bitmap_iterator *h, 306 unsigned long *stats_bitmap, 307 int count) 308 { 309 h->iterator = 0; 310 h->advance_array = !bitmap_empty(stats_bitmap, count); 311 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count) 312 : count; 313 h->stats_bitmap = stats_bitmap; 314 } 315 316 static inline int bitmap_iterator_test(struct bitmap_iterator *h) 317 { 318 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap); 319 } 320 321 static inline int bitmap_iterator_inc(struct bitmap_iterator *h) 322 { 323 return h->iterator++; 324 } 325 326 static inline unsigned int 327 bitmap_iterator_count(struct bitmap_iterator *h) 328 { 329 return h->count; 330 } 331 332 static int mlx4_en_get_sset_count(struct net_device *dev, int sset) 333 { 334 struct mlx4_en_priv *priv = netdev_priv(dev); 335 struct bitmap_iterator it; 336 337 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 338 339 switch (sset) { 340 case ETH_SS_STATS: 341 return bitmap_iterator_count(&it) + 342 (priv->tx_ring_num * 2) + 343 #ifdef CONFIG_NET_RX_BUSY_POLL 344 (priv->rx_ring_num * 5); 345 #else 346 (priv->rx_ring_num * 2); 347 #endif 348 case ETH_SS_TEST: 349 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags 350 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2; 351 case ETH_SS_PRIV_FLAGS: 352 return ARRAY_SIZE(mlx4_en_priv_flags); 353 default: 354 return -EOPNOTSUPP; 355 } 356 } 357 358 static void mlx4_en_get_ethtool_stats(struct net_device *dev, 359 struct ethtool_stats *stats, uint64_t *data) 360 { 361 struct mlx4_en_priv *priv = netdev_priv(dev); 362 int index = 0; 363 int i; 364 struct bitmap_iterator it; 365 366 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 367 368 spin_lock_bh(&priv->stats_lock); 369 370 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it)) 371 if (bitmap_iterator_test(&it)) 372 data[index++] = ((unsigned long *)&priv->stats)[i]; 373 374 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it)) 375 if (bitmap_iterator_test(&it)) 376 data[index++] = ((unsigned long *)&priv->port_stats)[i]; 377 378 for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it)) 379 if (bitmap_iterator_test(&it)) 380 data[index++] = 381 ((unsigned long *)&priv->pf_stats)[i]; 382 383 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX; 384 i++, bitmap_iterator_inc(&it)) 385 if (bitmap_iterator_test(&it)) 386 data[index++] = 387 ((u64 *)&priv->rx_priority_flowstats)[i]; 388 389 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it)) 390 if (bitmap_iterator_test(&it)) 391 data[index++] = ((u64 *)&priv->rx_flowstats)[i]; 392 393 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX; 394 i++, bitmap_iterator_inc(&it)) 395 if (bitmap_iterator_test(&it)) 396 data[index++] = 397 ((u64 *)&priv->tx_priority_flowstats)[i]; 398 399 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it)) 400 if (bitmap_iterator_test(&it)) 401 data[index++] = ((u64 *)&priv->tx_flowstats)[i]; 402 403 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it)) 404 if (bitmap_iterator_test(&it)) 405 data[index++] = ((unsigned long *)&priv->pkstats)[i]; 406 407 for (i = 0; i < priv->tx_ring_num; i++) { 408 data[index++] = priv->tx_ring[i]->packets; 409 data[index++] = priv->tx_ring[i]->bytes; 410 } 411 for (i = 0; i < priv->rx_ring_num; i++) { 412 data[index++] = priv->rx_ring[i]->packets; 413 data[index++] = priv->rx_ring[i]->bytes; 414 #ifdef CONFIG_NET_RX_BUSY_POLL 415 data[index++] = priv->rx_ring[i]->yields; 416 data[index++] = priv->rx_ring[i]->misses; 417 data[index++] = priv->rx_ring[i]->cleaned; 418 #endif 419 } 420 spin_unlock_bh(&priv->stats_lock); 421 422 } 423 424 static void mlx4_en_self_test(struct net_device *dev, 425 struct ethtool_test *etest, u64 *buf) 426 { 427 mlx4_en_ex_selftest(dev, &etest->flags, buf); 428 } 429 430 static void mlx4_en_get_strings(struct net_device *dev, 431 uint32_t stringset, uint8_t *data) 432 { 433 struct mlx4_en_priv *priv = netdev_priv(dev); 434 int index = 0; 435 int i, strings = 0; 436 struct bitmap_iterator it; 437 438 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 439 440 switch (stringset) { 441 case ETH_SS_TEST: 442 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++) 443 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); 444 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) 445 for (; i < MLX4_EN_NUM_SELF_TEST; i++) 446 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); 447 break; 448 449 case ETH_SS_STATS: 450 /* Add main counters */ 451 for (i = 0; i < NUM_MAIN_STATS; i++, strings++, 452 bitmap_iterator_inc(&it)) 453 if (bitmap_iterator_test(&it)) 454 strcpy(data + (index++) * ETH_GSTRING_LEN, 455 main_strings[strings]); 456 457 for (i = 0; i < NUM_PORT_STATS; i++, strings++, 458 bitmap_iterator_inc(&it)) 459 if (bitmap_iterator_test(&it)) 460 strcpy(data + (index++) * ETH_GSTRING_LEN, 461 main_strings[strings]); 462 463 for (i = 0; i < NUM_PF_STATS; i++, strings++, 464 bitmap_iterator_inc(&it)) 465 if (bitmap_iterator_test(&it)) 466 strcpy(data + (index++) * ETH_GSTRING_LEN, 467 main_strings[strings]); 468 469 for (i = 0; i < NUM_FLOW_STATS; i++, strings++, 470 bitmap_iterator_inc(&it)) 471 if (bitmap_iterator_test(&it)) 472 strcpy(data + (index++) * ETH_GSTRING_LEN, 473 main_strings[strings]); 474 475 for (i = 0; i < NUM_PKT_STATS; i++, strings++, 476 bitmap_iterator_inc(&it)) 477 if (bitmap_iterator_test(&it)) 478 strcpy(data + (index++) * ETH_GSTRING_LEN, 479 main_strings[strings]); 480 481 for (i = 0; i < priv->tx_ring_num; i++) { 482 sprintf(data + (index++) * ETH_GSTRING_LEN, 483 "tx%d_packets", i); 484 sprintf(data + (index++) * ETH_GSTRING_LEN, 485 "tx%d_bytes", i); 486 } 487 for (i = 0; i < priv->rx_ring_num; i++) { 488 sprintf(data + (index++) * ETH_GSTRING_LEN, 489 "rx%d_packets", i); 490 sprintf(data + (index++) * ETH_GSTRING_LEN, 491 "rx%d_bytes", i); 492 #ifdef CONFIG_NET_RX_BUSY_POLL 493 sprintf(data + (index++) * ETH_GSTRING_LEN, 494 "rx%d_napi_yield", i); 495 sprintf(data + (index++) * ETH_GSTRING_LEN, 496 "rx%d_misses", i); 497 sprintf(data + (index++) * ETH_GSTRING_LEN, 498 "rx%d_cleaned", i); 499 #endif 500 } 501 break; 502 case ETH_SS_PRIV_FLAGS: 503 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++) 504 strcpy(data + i * ETH_GSTRING_LEN, 505 mlx4_en_priv_flags[i]); 506 break; 507 508 } 509 } 510 511 static u32 mlx4_en_autoneg_get(struct net_device *dev) 512 { 513 struct mlx4_en_priv *priv = netdev_priv(dev); 514 struct mlx4_en_dev *mdev = priv->mdev; 515 u32 autoneg = AUTONEG_DISABLE; 516 517 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) && 518 (priv->port_state.flags & MLX4_EN_PORT_ANE)) 519 autoneg = AUTONEG_ENABLE; 520 521 return autoneg; 522 } 523 524 static u32 ptys_get_supported_port(struct mlx4_ptys_reg *ptys_reg) 525 { 526 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); 527 528 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) 529 | MLX4_PROT_MASK(MLX4_1000BASE_T) 530 | MLX4_PROT_MASK(MLX4_100BASE_TX))) { 531 return SUPPORTED_TP; 532 } 533 534 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) 535 | MLX4_PROT_MASK(MLX4_10GBASE_SR) 536 | MLX4_PROT_MASK(MLX4_56GBASE_SR4) 537 | MLX4_PROT_MASK(MLX4_40GBASE_CR4) 538 | MLX4_PROT_MASK(MLX4_40GBASE_SR4) 539 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { 540 return SUPPORTED_FIBRE; 541 } 542 543 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) 544 | MLX4_PROT_MASK(MLX4_40GBASE_KR4) 545 | MLX4_PROT_MASK(MLX4_20GBASE_KR2) 546 | MLX4_PROT_MASK(MLX4_10GBASE_KR) 547 | MLX4_PROT_MASK(MLX4_10GBASE_KX4) 548 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { 549 return SUPPORTED_Backplane; 550 } 551 return 0; 552 } 553 554 static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg) 555 { 556 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper); 557 558 if (!eth_proto) /* link down */ 559 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); 560 561 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) 562 | MLX4_PROT_MASK(MLX4_1000BASE_T) 563 | MLX4_PROT_MASK(MLX4_100BASE_TX))) { 564 return PORT_TP; 565 } 566 567 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR) 568 | MLX4_PROT_MASK(MLX4_56GBASE_SR4) 569 | MLX4_PROT_MASK(MLX4_40GBASE_SR4) 570 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { 571 return PORT_FIBRE; 572 } 573 574 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) 575 | MLX4_PROT_MASK(MLX4_56GBASE_CR4) 576 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) { 577 return PORT_DA; 578 } 579 580 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) 581 | MLX4_PROT_MASK(MLX4_40GBASE_KR4) 582 | MLX4_PROT_MASK(MLX4_20GBASE_KR2) 583 | MLX4_PROT_MASK(MLX4_10GBASE_KR) 584 | MLX4_PROT_MASK(MLX4_10GBASE_KX4) 585 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { 586 return PORT_NONE; 587 } 588 return PORT_OTHER; 589 } 590 591 #define MLX4_LINK_MODES_SZ \ 592 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8) 593 594 enum ethtool_report { 595 SUPPORTED = 0, 596 ADVERTISED = 1, 597 SPEED = 2 598 }; 599 600 /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */ 601 static u32 ptys2ethtool_map[MLX4_LINK_MODES_SZ][3] = { 602 [MLX4_100BASE_TX] = { 603 SUPPORTED_100baseT_Full, 604 ADVERTISED_100baseT_Full, 605 SPEED_100 606 }, 607 608 [MLX4_1000BASE_T] = { 609 SUPPORTED_1000baseT_Full, 610 ADVERTISED_1000baseT_Full, 611 SPEED_1000 612 }, 613 [MLX4_1000BASE_CX_SGMII] = { 614 SUPPORTED_1000baseKX_Full, 615 ADVERTISED_1000baseKX_Full, 616 SPEED_1000 617 }, 618 [MLX4_1000BASE_KX] = { 619 SUPPORTED_1000baseKX_Full, 620 ADVERTISED_1000baseKX_Full, 621 SPEED_1000 622 }, 623 624 [MLX4_10GBASE_T] = { 625 SUPPORTED_10000baseT_Full, 626 ADVERTISED_10000baseT_Full, 627 SPEED_10000 628 }, 629 [MLX4_10GBASE_CX4] = { 630 SUPPORTED_10000baseKX4_Full, 631 ADVERTISED_10000baseKX4_Full, 632 SPEED_10000 633 }, 634 [MLX4_10GBASE_KX4] = { 635 SUPPORTED_10000baseKX4_Full, 636 ADVERTISED_10000baseKX4_Full, 637 SPEED_10000 638 }, 639 [MLX4_10GBASE_KR] = { 640 SUPPORTED_10000baseKR_Full, 641 ADVERTISED_10000baseKR_Full, 642 SPEED_10000 643 }, 644 [MLX4_10GBASE_CR] = { 645 SUPPORTED_10000baseKR_Full, 646 ADVERTISED_10000baseKR_Full, 647 SPEED_10000 648 }, 649 [MLX4_10GBASE_SR] = { 650 SUPPORTED_10000baseKR_Full, 651 ADVERTISED_10000baseKR_Full, 652 SPEED_10000 653 }, 654 655 [MLX4_20GBASE_KR2] = { 656 SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full, 657 ADVERTISED_20000baseMLD2_Full | ADVERTISED_20000baseKR2_Full, 658 SPEED_20000 659 }, 660 661 [MLX4_40GBASE_CR4] = { 662 SUPPORTED_40000baseCR4_Full, 663 ADVERTISED_40000baseCR4_Full, 664 SPEED_40000 665 }, 666 [MLX4_40GBASE_KR4] = { 667 SUPPORTED_40000baseKR4_Full, 668 ADVERTISED_40000baseKR4_Full, 669 SPEED_40000 670 }, 671 [MLX4_40GBASE_SR4] = { 672 SUPPORTED_40000baseSR4_Full, 673 ADVERTISED_40000baseSR4_Full, 674 SPEED_40000 675 }, 676 677 [MLX4_56GBASE_KR4] = { 678 SUPPORTED_56000baseKR4_Full, 679 ADVERTISED_56000baseKR4_Full, 680 SPEED_56000 681 }, 682 [MLX4_56GBASE_CR4] = { 683 SUPPORTED_56000baseCR4_Full, 684 ADVERTISED_56000baseCR4_Full, 685 SPEED_56000 686 }, 687 [MLX4_56GBASE_SR4] = { 688 SUPPORTED_56000baseSR4_Full, 689 ADVERTISED_56000baseSR4_Full, 690 SPEED_56000 691 }, 692 }; 693 694 static u32 ptys2ethtool_link_modes(u32 eth_proto, enum ethtool_report report) 695 { 696 int i; 697 u32 link_modes = 0; 698 699 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 700 if (eth_proto & MLX4_PROT_MASK(i)) 701 link_modes |= ptys2ethtool_map[i][report]; 702 } 703 return link_modes; 704 } 705 706 static u32 ethtool2ptys_link_modes(u32 link_modes, enum ethtool_report report) 707 { 708 int i; 709 u32 ptys_modes = 0; 710 711 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 712 if (ptys2ethtool_map[i][report] & link_modes) 713 ptys_modes |= 1 << i; 714 } 715 return ptys_modes; 716 } 717 718 /* Convert actual speed (SPEED_XXX) to ptys link modes */ 719 static u32 speed2ptys_link_modes(u32 speed) 720 { 721 int i; 722 u32 ptys_modes = 0; 723 724 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 725 if (ptys2ethtool_map[i][SPEED] == speed) 726 ptys_modes |= 1 << i; 727 } 728 return ptys_modes; 729 } 730 731 static int ethtool_get_ptys_settings(struct net_device *dev, 732 struct ethtool_cmd *cmd) 733 { 734 struct mlx4_en_priv *priv = netdev_priv(dev); 735 struct mlx4_ptys_reg ptys_reg; 736 u32 eth_proto; 737 int ret; 738 739 memset(&ptys_reg, 0, sizeof(ptys_reg)); 740 ptys_reg.local_port = priv->port; 741 ptys_reg.proto_mask = MLX4_PTYS_EN; 742 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, 743 MLX4_ACCESS_REG_QUERY, &ptys_reg); 744 if (ret) { 745 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)", 746 ret); 747 return ret; 748 } 749 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n", 750 ptys_reg.proto_mask); 751 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n", 752 be32_to_cpu(ptys_reg.eth_proto_cap)); 753 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n", 754 be32_to_cpu(ptys_reg.eth_proto_admin)); 755 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n", 756 be32_to_cpu(ptys_reg.eth_proto_oper)); 757 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n", 758 be32_to_cpu(ptys_reg.eth_proto_lp_adv)); 759 760 cmd->supported = 0; 761 cmd->advertising = 0; 762 763 cmd->supported |= ptys_get_supported_port(&ptys_reg); 764 765 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap); 766 cmd->supported |= ptys2ethtool_link_modes(eth_proto, SUPPORTED); 767 768 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin); 769 cmd->advertising |= ptys2ethtool_link_modes(eth_proto, ADVERTISED); 770 771 cmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 772 cmd->advertising |= (priv->prof->tx_pause) ? ADVERTISED_Pause : 0; 773 774 cmd->advertising |= (priv->prof->tx_pause ^ priv->prof->rx_pause) ? 775 ADVERTISED_Asym_Pause : 0; 776 777 cmd->port = ptys_get_active_port(&ptys_reg); 778 cmd->transceiver = (SUPPORTED_TP & cmd->supported) ? 779 XCVR_EXTERNAL : XCVR_INTERNAL; 780 781 if (mlx4_en_autoneg_get(dev)) { 782 cmd->supported |= SUPPORTED_Autoneg; 783 cmd->advertising |= ADVERTISED_Autoneg; 784 } 785 786 cmd->autoneg = (priv->port_state.flags & MLX4_EN_PORT_ANC) ? 787 AUTONEG_ENABLE : AUTONEG_DISABLE; 788 789 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv); 790 cmd->lp_advertising = ptys2ethtool_link_modes(eth_proto, ADVERTISED); 791 792 cmd->lp_advertising |= (priv->port_state.flags & MLX4_EN_PORT_ANC) ? 793 ADVERTISED_Autoneg : 0; 794 795 cmd->phy_address = 0; 796 cmd->mdio_support = 0; 797 cmd->maxtxpkt = 0; 798 cmd->maxrxpkt = 0; 799 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID; 800 cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 801 802 return ret; 803 } 804 805 static void ethtool_get_default_settings(struct net_device *dev, 806 struct ethtool_cmd *cmd) 807 { 808 struct mlx4_en_priv *priv = netdev_priv(dev); 809 int trans_type; 810 811 cmd->autoneg = AUTONEG_DISABLE; 812 cmd->supported = SUPPORTED_10000baseT_Full; 813 cmd->advertising = ADVERTISED_10000baseT_Full; 814 trans_type = priv->port_state.transceiver; 815 816 if (trans_type > 0 && trans_type <= 0xC) { 817 cmd->port = PORT_FIBRE; 818 cmd->transceiver = XCVR_EXTERNAL; 819 cmd->supported |= SUPPORTED_FIBRE; 820 cmd->advertising |= ADVERTISED_FIBRE; 821 } else if (trans_type == 0x80 || trans_type == 0) { 822 cmd->port = PORT_TP; 823 cmd->transceiver = XCVR_INTERNAL; 824 cmd->supported |= SUPPORTED_TP; 825 cmd->advertising |= ADVERTISED_TP; 826 } else { 827 cmd->port = -1; 828 cmd->transceiver = -1; 829 } 830 } 831 832 static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 833 { 834 struct mlx4_en_priv *priv = netdev_priv(dev); 835 int ret = -EINVAL; 836 837 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port)) 838 return -ENOMEM; 839 840 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n", 841 priv->port_state.flags & MLX4_EN_PORT_ANC, 842 priv->port_state.flags & MLX4_EN_PORT_ANE); 843 844 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) 845 ret = ethtool_get_ptys_settings(dev, cmd); 846 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */ 847 ethtool_get_default_settings(dev, cmd); 848 849 if (netif_carrier_ok(dev)) { 850 ethtool_cmd_speed_set(cmd, priv->port_state.link_speed); 851 cmd->duplex = DUPLEX_FULL; 852 } else { 853 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 854 cmd->duplex = DUPLEX_UNKNOWN; 855 } 856 return 0; 857 } 858 859 /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */ 860 static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed, 861 __be32 proto_cap) 862 { 863 __be32 proto_admin = 0; 864 865 if (!speed) { /* Speed = 0 ==> Reset Link modes */ 866 proto_admin = proto_cap; 867 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n", 868 be32_to_cpu(proto_cap)); 869 } else { 870 u32 ptys_link_modes = speed2ptys_link_modes(speed); 871 872 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap; 873 en_info(priv, "Setting Speed to %d\n", speed); 874 } 875 return proto_admin; 876 } 877 878 static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 879 { 880 struct mlx4_en_priv *priv = netdev_priv(dev); 881 struct mlx4_ptys_reg ptys_reg; 882 __be32 proto_admin; 883 int ret; 884 885 u32 ptys_adv = ethtool2ptys_link_modes(cmd->advertising, ADVERTISED); 886 int speed = ethtool_cmd_speed(cmd); 887 888 en_dbg(DRV, priv, "Set Speed=%d adv=0x%x autoneg=%d duplex=%d\n", 889 speed, cmd->advertising, cmd->autoneg, cmd->duplex); 890 891 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) || 892 (cmd->duplex == DUPLEX_HALF)) 893 return -EINVAL; 894 895 memset(&ptys_reg, 0, sizeof(ptys_reg)); 896 ptys_reg.local_port = priv->port; 897 ptys_reg.proto_mask = MLX4_PTYS_EN; 898 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, 899 MLX4_ACCESS_REG_QUERY, &ptys_reg); 900 if (ret) { 901 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n", 902 ret); 903 return 0; 904 } 905 906 proto_admin = cmd->autoneg == AUTONEG_ENABLE ? 907 cpu_to_be32(ptys_adv) : 908 speed_set_ptys_admin(priv, speed, 909 ptys_reg.eth_proto_cap); 910 911 proto_admin &= ptys_reg.eth_proto_cap; 912 if (!proto_admin) { 913 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n"); 914 return -EINVAL; /* nothing to change due to bad input */ 915 } 916 917 if (proto_admin == ptys_reg.eth_proto_admin) 918 return 0; /* Nothing to change */ 919 920 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n", 921 be32_to_cpu(proto_admin)); 922 923 ptys_reg.eth_proto_admin = proto_admin; 924 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE, 925 &ptys_reg); 926 if (ret) { 927 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)", 928 be32_to_cpu(ptys_reg.eth_proto_admin), ret); 929 return ret; 930 } 931 932 mutex_lock(&priv->mdev->state_lock); 933 if (priv->port_up) { 934 en_warn(priv, "Port link mode changed, restarting port...\n"); 935 mlx4_en_stop_port(dev, 1); 936 if (mlx4_en_start_port(dev)) 937 en_err(priv, "Failed restarting port %d\n", priv->port); 938 } 939 mutex_unlock(&priv->mdev->state_lock); 940 return 0; 941 } 942 943 static int mlx4_en_get_coalesce(struct net_device *dev, 944 struct ethtool_coalesce *coal) 945 { 946 struct mlx4_en_priv *priv = netdev_priv(dev); 947 948 coal->tx_coalesce_usecs = priv->tx_usecs; 949 coal->tx_max_coalesced_frames = priv->tx_frames; 950 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit; 951 952 coal->rx_coalesce_usecs = priv->rx_usecs; 953 coal->rx_max_coalesced_frames = priv->rx_frames; 954 955 coal->pkt_rate_low = priv->pkt_rate_low; 956 coal->rx_coalesce_usecs_low = priv->rx_usecs_low; 957 coal->pkt_rate_high = priv->pkt_rate_high; 958 coal->rx_coalesce_usecs_high = priv->rx_usecs_high; 959 coal->rate_sample_interval = priv->sample_interval; 960 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal; 961 962 return 0; 963 } 964 965 static int mlx4_en_set_coalesce(struct net_device *dev, 966 struct ethtool_coalesce *coal) 967 { 968 struct mlx4_en_priv *priv = netdev_priv(dev); 969 970 if (!coal->tx_max_coalesced_frames_irq) 971 return -EINVAL; 972 973 priv->rx_frames = (coal->rx_max_coalesced_frames == 974 MLX4_EN_AUTO_CONF) ? 975 MLX4_EN_RX_COAL_TARGET : 976 coal->rx_max_coalesced_frames; 977 priv->rx_usecs = (coal->rx_coalesce_usecs == 978 MLX4_EN_AUTO_CONF) ? 979 MLX4_EN_RX_COAL_TIME : 980 coal->rx_coalesce_usecs; 981 982 /* Setting TX coalescing parameters */ 983 if (coal->tx_coalesce_usecs != priv->tx_usecs || 984 coal->tx_max_coalesced_frames != priv->tx_frames) { 985 priv->tx_usecs = coal->tx_coalesce_usecs; 986 priv->tx_frames = coal->tx_max_coalesced_frames; 987 } 988 989 /* Set adaptive coalescing params */ 990 priv->pkt_rate_low = coal->pkt_rate_low; 991 priv->rx_usecs_low = coal->rx_coalesce_usecs_low; 992 priv->pkt_rate_high = coal->pkt_rate_high; 993 priv->rx_usecs_high = coal->rx_coalesce_usecs_high; 994 priv->sample_interval = coal->rate_sample_interval; 995 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce; 996 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq; 997 998 return mlx4_en_moderation_update(priv); 999 } 1000 1001 static int mlx4_en_set_pauseparam(struct net_device *dev, 1002 struct ethtool_pauseparam *pause) 1003 { 1004 struct mlx4_en_priv *priv = netdev_priv(dev); 1005 struct mlx4_en_dev *mdev = priv->mdev; 1006 int err; 1007 1008 if (pause->autoneg) 1009 return -EINVAL; 1010 1011 priv->prof->tx_pause = pause->tx_pause != 0; 1012 priv->prof->rx_pause = pause->rx_pause != 0; 1013 err = mlx4_SET_PORT_general(mdev->dev, priv->port, 1014 priv->rx_skb_size + ETH_FCS_LEN, 1015 priv->prof->tx_pause, 1016 priv->prof->tx_ppp, 1017 priv->prof->rx_pause, 1018 priv->prof->rx_ppp); 1019 if (err) 1020 en_err(priv, "Failed setting pause params\n"); 1021 else 1022 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap, 1023 priv->prof->rx_ppp, 1024 priv->prof->rx_pause, 1025 priv->prof->tx_ppp, 1026 priv->prof->tx_pause); 1027 1028 return err; 1029 } 1030 1031 static void mlx4_en_get_pauseparam(struct net_device *dev, 1032 struct ethtool_pauseparam *pause) 1033 { 1034 struct mlx4_en_priv *priv = netdev_priv(dev); 1035 1036 pause->tx_pause = priv->prof->tx_pause; 1037 pause->rx_pause = priv->prof->rx_pause; 1038 } 1039 1040 static int mlx4_en_set_ringparam(struct net_device *dev, 1041 struct ethtool_ringparam *param) 1042 { 1043 struct mlx4_en_priv *priv = netdev_priv(dev); 1044 struct mlx4_en_dev *mdev = priv->mdev; 1045 u32 rx_size, tx_size; 1046 int port_up = 0; 1047 int err = 0; 1048 1049 if (param->rx_jumbo_pending || param->rx_mini_pending) 1050 return -EINVAL; 1051 1052 rx_size = roundup_pow_of_two(param->rx_pending); 1053 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE); 1054 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE); 1055 tx_size = roundup_pow_of_two(param->tx_pending); 1056 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE); 1057 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE); 1058 1059 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size : 1060 priv->rx_ring[0]->size) && 1061 tx_size == priv->tx_ring[0]->size) 1062 return 0; 1063 1064 mutex_lock(&mdev->state_lock); 1065 if (priv->port_up) { 1066 port_up = 1; 1067 mlx4_en_stop_port(dev, 1); 1068 } 1069 1070 mlx4_en_free_resources(priv); 1071 1072 priv->prof->tx_ring_size = tx_size; 1073 priv->prof->rx_ring_size = rx_size; 1074 1075 err = mlx4_en_alloc_resources(priv); 1076 if (err) { 1077 en_err(priv, "Failed reallocating port resources\n"); 1078 goto out; 1079 } 1080 if (port_up) { 1081 err = mlx4_en_start_port(dev); 1082 if (err) 1083 en_err(priv, "Failed starting port\n"); 1084 } 1085 1086 err = mlx4_en_moderation_update(priv); 1087 1088 out: 1089 mutex_unlock(&mdev->state_lock); 1090 return err; 1091 } 1092 1093 static void mlx4_en_get_ringparam(struct net_device *dev, 1094 struct ethtool_ringparam *param) 1095 { 1096 struct mlx4_en_priv *priv = netdev_priv(dev); 1097 1098 memset(param, 0, sizeof(*param)); 1099 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE; 1100 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE; 1101 param->rx_pending = priv->port_up ? 1102 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size; 1103 param->tx_pending = priv->tx_ring[0]->size; 1104 } 1105 1106 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev) 1107 { 1108 struct mlx4_en_priv *priv = netdev_priv(dev); 1109 1110 return priv->rx_ring_num; 1111 } 1112 1113 static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev) 1114 { 1115 return MLX4_EN_RSS_KEY_SIZE; 1116 } 1117 1118 static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc) 1119 { 1120 struct mlx4_en_priv *priv = netdev_priv(dev); 1121 1122 /* check if requested function is supported by the device */ 1123 if (hfunc == ETH_RSS_HASH_TOP) { 1124 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) 1125 return -EINVAL; 1126 if (!(dev->features & NETIF_F_RXHASH)) 1127 en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n"); 1128 return 0; 1129 } else if (hfunc == ETH_RSS_HASH_XOR) { 1130 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR)) 1131 return -EINVAL; 1132 if (dev->features & NETIF_F_RXHASH) 1133 en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n"); 1134 return 0; 1135 } 1136 1137 return -EINVAL; 1138 } 1139 1140 static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key, 1141 u8 *hfunc) 1142 { 1143 struct mlx4_en_priv *priv = netdev_priv(dev); 1144 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1145 int rss_rings; 1146 size_t n = priv->rx_ring_num; 1147 int err = 0; 1148 1149 rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num; 1150 rss_rings = 1 << ilog2(rss_rings); 1151 1152 while (n--) { 1153 if (!ring_index) 1154 break; 1155 ring_index[n] = rss_map->qps[n % rss_rings].qpn - 1156 rss_map->base_qpn; 1157 } 1158 if (key) 1159 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE); 1160 if (hfunc) 1161 *hfunc = priv->rss_hash_fn; 1162 return err; 1163 } 1164 1165 static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index, 1166 const u8 *key, const u8 hfunc) 1167 { 1168 struct mlx4_en_priv *priv = netdev_priv(dev); 1169 struct mlx4_en_dev *mdev = priv->mdev; 1170 int port_up = 0; 1171 int err = 0; 1172 int i; 1173 int rss_rings = 0; 1174 1175 /* Calculate RSS table size and make sure flows are spread evenly 1176 * between rings 1177 */ 1178 for (i = 0; i < priv->rx_ring_num; i++) { 1179 if (!ring_index) 1180 continue; 1181 if (i > 0 && !ring_index[i] && !rss_rings) 1182 rss_rings = i; 1183 1184 if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num))) 1185 return -EINVAL; 1186 } 1187 1188 if (!rss_rings) 1189 rss_rings = priv->rx_ring_num; 1190 1191 /* RSS table size must be an order of 2 */ 1192 if (!is_power_of_2(rss_rings)) 1193 return -EINVAL; 1194 1195 if (hfunc != ETH_RSS_HASH_NO_CHANGE) { 1196 err = mlx4_en_check_rxfh_func(dev, hfunc); 1197 if (err) 1198 return err; 1199 } 1200 1201 mutex_lock(&mdev->state_lock); 1202 if (priv->port_up) { 1203 port_up = 1; 1204 mlx4_en_stop_port(dev, 1); 1205 } 1206 1207 if (ring_index) 1208 priv->prof->rss_rings = rss_rings; 1209 if (key) 1210 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE); 1211 if (hfunc != ETH_RSS_HASH_NO_CHANGE) 1212 priv->rss_hash_fn = hfunc; 1213 1214 if (port_up) { 1215 err = mlx4_en_start_port(dev); 1216 if (err) 1217 en_err(priv, "Failed starting port\n"); 1218 } 1219 1220 mutex_unlock(&mdev->state_lock); 1221 return err; 1222 } 1223 1224 #define all_zeros_or_all_ones(field) \ 1225 ((field) == 0 || (field) == (__force typeof(field))-1) 1226 1227 static int mlx4_en_validate_flow(struct net_device *dev, 1228 struct ethtool_rxnfc *cmd) 1229 { 1230 struct ethtool_usrip4_spec *l3_mask; 1231 struct ethtool_tcpip4_spec *l4_mask; 1232 struct ethhdr *eth_mask; 1233 1234 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1235 return -EINVAL; 1236 1237 if (cmd->fs.flow_type & FLOW_MAC_EXT) { 1238 /* dest mac mask must be ff:ff:ff:ff:ff:ff */ 1239 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest)) 1240 return -EINVAL; 1241 } 1242 1243 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1244 case TCP_V4_FLOW: 1245 case UDP_V4_FLOW: 1246 if (cmd->fs.m_u.tcp_ip4_spec.tos) 1247 return -EINVAL; 1248 l4_mask = &cmd->fs.m_u.tcp_ip4_spec; 1249 /* don't allow mask which isn't all 0 or 1 */ 1250 if (!all_zeros_or_all_ones(l4_mask->ip4src) || 1251 !all_zeros_or_all_ones(l4_mask->ip4dst) || 1252 !all_zeros_or_all_ones(l4_mask->psrc) || 1253 !all_zeros_or_all_ones(l4_mask->pdst)) 1254 return -EINVAL; 1255 break; 1256 case IP_USER_FLOW: 1257 l3_mask = &cmd->fs.m_u.usr_ip4_spec; 1258 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto || 1259 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 || 1260 (!l3_mask->ip4src && !l3_mask->ip4dst) || 1261 !all_zeros_or_all_ones(l3_mask->ip4src) || 1262 !all_zeros_or_all_ones(l3_mask->ip4dst)) 1263 return -EINVAL; 1264 break; 1265 case ETHER_FLOW: 1266 eth_mask = &cmd->fs.m_u.ether_spec; 1267 /* source mac mask must not be set */ 1268 if (!is_zero_ether_addr(eth_mask->h_source)) 1269 return -EINVAL; 1270 1271 /* dest mac mask must be ff:ff:ff:ff:ff:ff */ 1272 if (!is_broadcast_ether_addr(eth_mask->h_dest)) 1273 return -EINVAL; 1274 1275 if (!all_zeros_or_all_ones(eth_mask->h_proto)) 1276 return -EINVAL; 1277 break; 1278 default: 1279 return -EINVAL; 1280 } 1281 1282 if ((cmd->fs.flow_type & FLOW_EXT)) { 1283 if (cmd->fs.m_ext.vlan_etype || 1284 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == 1285 0 || 1286 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == 1287 cpu_to_be16(VLAN_VID_MASK))) 1288 return -EINVAL; 1289 1290 if (cmd->fs.m_ext.vlan_tci) { 1291 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID) 1292 return -EINVAL; 1293 1294 } 1295 } 1296 1297 return 0; 1298 } 1299 1300 static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd, 1301 struct list_head *rule_list_h, 1302 struct mlx4_spec_list *spec_l2, 1303 unsigned char *mac) 1304 { 1305 int err = 0; 1306 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16); 1307 1308 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH; 1309 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN); 1310 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN); 1311 1312 if ((cmd->fs.flow_type & FLOW_EXT) && 1313 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) { 1314 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci; 1315 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK); 1316 } 1317 1318 list_add_tail(&spec_l2->list, rule_list_h); 1319 1320 return err; 1321 } 1322 1323 static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv, 1324 struct ethtool_rxnfc *cmd, 1325 struct list_head *rule_list_h, 1326 struct mlx4_spec_list *spec_l2, 1327 __be32 ipv4_dst) 1328 { 1329 #ifdef CONFIG_INET 1330 unsigned char mac[ETH_ALEN]; 1331 1332 if (!ipv4_is_multicast(ipv4_dst)) { 1333 if (cmd->fs.flow_type & FLOW_MAC_EXT) 1334 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN); 1335 else 1336 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN); 1337 } else { 1338 ip_eth_mc_map(ipv4_dst, mac); 1339 } 1340 1341 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]); 1342 #else 1343 return -EINVAL; 1344 #endif 1345 } 1346 1347 static int add_ip_rule(struct mlx4_en_priv *priv, 1348 struct ethtool_rxnfc *cmd, 1349 struct list_head *list_h) 1350 { 1351 int err; 1352 struct mlx4_spec_list *spec_l2 = NULL; 1353 struct mlx4_spec_list *spec_l3 = NULL; 1354 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec; 1355 1356 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); 1357 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1358 if (!spec_l2 || !spec_l3) { 1359 err = -ENOMEM; 1360 goto free_spec; 1361 } 1362 1363 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2, 1364 cmd->fs.h_u. 1365 usr_ip4_spec.ip4dst); 1366 if (err) 1367 goto free_spec; 1368 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; 1369 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src; 1370 if (l3_mask->ip4src) 1371 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; 1372 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst; 1373 if (l3_mask->ip4dst) 1374 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; 1375 list_add_tail(&spec_l3->list, list_h); 1376 1377 return 0; 1378 1379 free_spec: 1380 kfree(spec_l2); 1381 kfree(spec_l3); 1382 return err; 1383 } 1384 1385 static int add_tcp_udp_rule(struct mlx4_en_priv *priv, 1386 struct ethtool_rxnfc *cmd, 1387 struct list_head *list_h, int proto) 1388 { 1389 int err; 1390 struct mlx4_spec_list *spec_l2 = NULL; 1391 struct mlx4_spec_list *spec_l3 = NULL; 1392 struct mlx4_spec_list *spec_l4 = NULL; 1393 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec; 1394 1395 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1396 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); 1397 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL); 1398 if (!spec_l2 || !spec_l3 || !spec_l4) { 1399 err = -ENOMEM; 1400 goto free_spec; 1401 } 1402 1403 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; 1404 1405 if (proto == TCP_V4_FLOW) { 1406 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, 1407 spec_l2, 1408 cmd->fs.h_u. 1409 tcp_ip4_spec.ip4dst); 1410 if (err) 1411 goto free_spec; 1412 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP; 1413 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src; 1414 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst; 1415 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc; 1416 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst; 1417 } else { 1418 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, 1419 spec_l2, 1420 cmd->fs.h_u. 1421 udp_ip4_spec.ip4dst); 1422 if (err) 1423 goto free_spec; 1424 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP; 1425 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src; 1426 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst; 1427 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc; 1428 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst; 1429 } 1430 1431 if (l4_mask->ip4src) 1432 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; 1433 if (l4_mask->ip4dst) 1434 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; 1435 1436 if (l4_mask->psrc) 1437 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK; 1438 if (l4_mask->pdst) 1439 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK; 1440 1441 list_add_tail(&spec_l3->list, list_h); 1442 list_add_tail(&spec_l4->list, list_h); 1443 1444 return 0; 1445 1446 free_spec: 1447 kfree(spec_l2); 1448 kfree(spec_l3); 1449 kfree(spec_l4); 1450 return err; 1451 } 1452 1453 static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev, 1454 struct ethtool_rxnfc *cmd, 1455 struct list_head *rule_list_h) 1456 { 1457 int err; 1458 struct ethhdr *eth_spec; 1459 struct mlx4_spec_list *spec_l2; 1460 struct mlx4_en_priv *priv = netdev_priv(dev); 1461 1462 err = mlx4_en_validate_flow(dev, cmd); 1463 if (err) 1464 return err; 1465 1466 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1467 case ETHER_FLOW: 1468 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1469 if (!spec_l2) 1470 return -ENOMEM; 1471 1472 eth_spec = &cmd->fs.h_u.ether_spec; 1473 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, 1474 ð_spec->h_dest[0]); 1475 spec_l2->eth.ether_type = eth_spec->h_proto; 1476 if (eth_spec->h_proto) 1477 spec_l2->eth.ether_type_enable = 1; 1478 break; 1479 case IP_USER_FLOW: 1480 err = add_ip_rule(priv, cmd, rule_list_h); 1481 break; 1482 case TCP_V4_FLOW: 1483 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW); 1484 break; 1485 case UDP_V4_FLOW: 1486 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW); 1487 break; 1488 } 1489 1490 return err; 1491 } 1492 1493 static int mlx4_en_flow_replace(struct net_device *dev, 1494 struct ethtool_rxnfc *cmd) 1495 { 1496 int err; 1497 struct mlx4_en_priv *priv = netdev_priv(dev); 1498 struct ethtool_flow_id *loc_rule; 1499 struct mlx4_spec_list *spec, *tmp_spec; 1500 u32 qpn; 1501 u64 reg_id; 1502 1503 struct mlx4_net_trans_rule rule = { 1504 .queue_mode = MLX4_NET_TRANS_Q_FIFO, 1505 .exclusive = 0, 1506 .allow_loopback = 1, 1507 .promisc_mode = MLX4_FS_REGULAR, 1508 }; 1509 1510 rule.port = priv->port; 1511 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location; 1512 INIT_LIST_HEAD(&rule.list); 1513 1514 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */ 1515 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC) 1516 qpn = priv->drop_qp.qpn; 1517 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) { 1518 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1); 1519 } else { 1520 if (cmd->fs.ring_cookie >= priv->rx_ring_num) { 1521 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n", 1522 cmd->fs.ring_cookie); 1523 return -EINVAL; 1524 } 1525 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn; 1526 if (!qpn) { 1527 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n", 1528 cmd->fs.ring_cookie); 1529 return -EINVAL; 1530 } 1531 } 1532 rule.qpn = qpn; 1533 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list); 1534 if (err) 1535 goto out_free_list; 1536 1537 loc_rule = &priv->ethtool_rules[cmd->fs.location]; 1538 if (loc_rule->id) { 1539 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id); 1540 if (err) { 1541 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n", 1542 cmd->fs.location, loc_rule->id); 1543 goto out_free_list; 1544 } 1545 loc_rule->id = 0; 1546 memset(&loc_rule->flow_spec, 0, 1547 sizeof(struct ethtool_rx_flow_spec)); 1548 list_del(&loc_rule->list); 1549 } 1550 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id); 1551 if (err) { 1552 en_err(priv, "Fail to attach network rule at location %d\n", 1553 cmd->fs.location); 1554 goto out_free_list; 1555 } 1556 loc_rule->id = reg_id; 1557 memcpy(&loc_rule->flow_spec, &cmd->fs, 1558 sizeof(struct ethtool_rx_flow_spec)); 1559 list_add_tail(&loc_rule->list, &priv->ethtool_list); 1560 1561 out_free_list: 1562 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) { 1563 list_del(&spec->list); 1564 kfree(spec); 1565 } 1566 return err; 1567 } 1568 1569 static int mlx4_en_flow_detach(struct net_device *dev, 1570 struct ethtool_rxnfc *cmd) 1571 { 1572 int err = 0; 1573 struct ethtool_flow_id *rule; 1574 struct mlx4_en_priv *priv = netdev_priv(dev); 1575 1576 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1577 return -EINVAL; 1578 1579 rule = &priv->ethtool_rules[cmd->fs.location]; 1580 if (!rule->id) { 1581 err = -ENOENT; 1582 goto out; 1583 } 1584 1585 err = mlx4_flow_detach(priv->mdev->dev, rule->id); 1586 if (err) { 1587 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n", 1588 cmd->fs.location, rule->id); 1589 goto out; 1590 } 1591 rule->id = 0; 1592 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec)); 1593 list_del(&rule->list); 1594 out: 1595 return err; 1596 1597 } 1598 1599 static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1600 int loc) 1601 { 1602 int err = 0; 1603 struct ethtool_flow_id *rule; 1604 struct mlx4_en_priv *priv = netdev_priv(dev); 1605 1606 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1607 return -EINVAL; 1608 1609 rule = &priv->ethtool_rules[loc]; 1610 if (rule->id) 1611 memcpy(&cmd->fs, &rule->flow_spec, 1612 sizeof(struct ethtool_rx_flow_spec)); 1613 else 1614 err = -ENOENT; 1615 1616 return err; 1617 } 1618 1619 static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv) 1620 { 1621 1622 int i, res = 0; 1623 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 1624 if (priv->ethtool_rules[i].id) 1625 res++; 1626 } 1627 return res; 1628 1629 } 1630 1631 static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1632 u32 *rule_locs) 1633 { 1634 struct mlx4_en_priv *priv = netdev_priv(dev); 1635 struct mlx4_en_dev *mdev = priv->mdev; 1636 int err = 0; 1637 int i = 0, priority = 0; 1638 1639 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT || 1640 cmd->cmd == ETHTOOL_GRXCLSRULE || 1641 cmd->cmd == ETHTOOL_GRXCLSRLALL) && 1642 (mdev->dev->caps.steering_mode != 1643 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)) 1644 return -EINVAL; 1645 1646 switch (cmd->cmd) { 1647 case ETHTOOL_GRXRINGS: 1648 cmd->data = priv->rx_ring_num; 1649 break; 1650 case ETHTOOL_GRXCLSRLCNT: 1651 cmd->rule_cnt = mlx4_en_get_num_flows(priv); 1652 break; 1653 case ETHTOOL_GRXCLSRULE: 1654 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location); 1655 break; 1656 case ETHTOOL_GRXCLSRLALL: 1657 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) { 1658 err = mlx4_en_get_flow(dev, cmd, i); 1659 if (!err) 1660 rule_locs[priority++] = i; 1661 i++; 1662 } 1663 err = 0; 1664 break; 1665 default: 1666 err = -EOPNOTSUPP; 1667 break; 1668 } 1669 1670 return err; 1671 } 1672 1673 static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1674 { 1675 int err = 0; 1676 struct mlx4_en_priv *priv = netdev_priv(dev); 1677 struct mlx4_en_dev *mdev = priv->mdev; 1678 1679 if (mdev->dev->caps.steering_mode != 1680 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up) 1681 return -EINVAL; 1682 1683 switch (cmd->cmd) { 1684 case ETHTOOL_SRXCLSRLINS: 1685 err = mlx4_en_flow_replace(dev, cmd); 1686 break; 1687 case ETHTOOL_SRXCLSRLDEL: 1688 err = mlx4_en_flow_detach(dev, cmd); 1689 break; 1690 default: 1691 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd); 1692 return -EINVAL; 1693 } 1694 1695 return err; 1696 } 1697 1698 static void mlx4_en_get_channels(struct net_device *dev, 1699 struct ethtool_channels *channel) 1700 { 1701 struct mlx4_en_priv *priv = netdev_priv(dev); 1702 1703 memset(channel, 0, sizeof(*channel)); 1704 1705 channel->max_rx = MAX_RX_RINGS; 1706 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP; 1707 1708 channel->rx_count = priv->rx_ring_num; 1709 channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP; 1710 } 1711 1712 static int mlx4_en_set_channels(struct net_device *dev, 1713 struct ethtool_channels *channel) 1714 { 1715 struct mlx4_en_priv *priv = netdev_priv(dev); 1716 struct mlx4_en_dev *mdev = priv->mdev; 1717 int port_up = 0; 1718 int err = 0; 1719 1720 if (channel->other_count || channel->combined_count || 1721 channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP || 1722 channel->rx_count > MAX_RX_RINGS || 1723 !channel->tx_count || !channel->rx_count) 1724 return -EINVAL; 1725 1726 mutex_lock(&mdev->state_lock); 1727 if (priv->port_up) { 1728 port_up = 1; 1729 mlx4_en_stop_port(dev, 1); 1730 } 1731 1732 mlx4_en_free_resources(priv); 1733 1734 priv->num_tx_rings_p_up = channel->tx_count; 1735 priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP; 1736 priv->rx_ring_num = channel->rx_count; 1737 1738 err = mlx4_en_alloc_resources(priv); 1739 if (err) { 1740 en_err(priv, "Failed reallocating port resources\n"); 1741 goto out; 1742 } 1743 1744 netif_set_real_num_tx_queues(dev, priv->tx_ring_num); 1745 netif_set_real_num_rx_queues(dev, priv->rx_ring_num); 1746 1747 if (dev->num_tc) 1748 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP); 1749 1750 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num); 1751 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num); 1752 1753 if (port_up) { 1754 err = mlx4_en_start_port(dev); 1755 if (err) 1756 en_err(priv, "Failed starting port\n"); 1757 } 1758 1759 err = mlx4_en_moderation_update(priv); 1760 1761 out: 1762 mutex_unlock(&mdev->state_lock); 1763 return err; 1764 } 1765 1766 static int mlx4_en_get_ts_info(struct net_device *dev, 1767 struct ethtool_ts_info *info) 1768 { 1769 struct mlx4_en_priv *priv = netdev_priv(dev); 1770 struct mlx4_en_dev *mdev = priv->mdev; 1771 int ret; 1772 1773 ret = ethtool_op_get_ts_info(dev, info); 1774 if (ret) 1775 return ret; 1776 1777 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 1778 info->so_timestamping |= 1779 SOF_TIMESTAMPING_TX_HARDWARE | 1780 SOF_TIMESTAMPING_RX_HARDWARE | 1781 SOF_TIMESTAMPING_RAW_HARDWARE; 1782 1783 info->tx_types = 1784 (1 << HWTSTAMP_TX_OFF) | 1785 (1 << HWTSTAMP_TX_ON); 1786 1787 info->rx_filters = 1788 (1 << HWTSTAMP_FILTER_NONE) | 1789 (1 << HWTSTAMP_FILTER_ALL); 1790 1791 if (mdev->ptp_clock) 1792 info->phc_index = ptp_clock_index(mdev->ptp_clock); 1793 } 1794 1795 return ret; 1796 } 1797 1798 static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags) 1799 { 1800 struct mlx4_en_priv *priv = netdev_priv(dev); 1801 struct mlx4_en_dev *mdev = priv->mdev; 1802 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); 1803 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); 1804 bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV); 1805 bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV); 1806 int i; 1807 int ret = 0; 1808 1809 if (bf_enabled_new != bf_enabled_old) { 1810 if (bf_enabled_new) { 1811 bool bf_supported = true; 1812 1813 for (i = 0; i < priv->tx_ring_num; i++) 1814 bf_supported &= priv->tx_ring[i]->bf_alloced; 1815 1816 if (!bf_supported) { 1817 en_err(priv, "BlueFlame is not supported\n"); 1818 return -EINVAL; 1819 } 1820 1821 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME; 1822 } else { 1823 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 1824 } 1825 1826 for (i = 0; i < priv->tx_ring_num; i++) 1827 priv->tx_ring[i]->bf_enabled = bf_enabled_new; 1828 1829 en_info(priv, "BlueFlame %s\n", 1830 bf_enabled_new ? "Enabled" : "Disabled"); 1831 } 1832 1833 if (phv_enabled_new != phv_enabled_old) { 1834 ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new); 1835 if (ret) 1836 return ret; 1837 else if (phv_enabled_new) 1838 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV; 1839 else 1840 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV; 1841 en_info(priv, "PHV bit %s\n", 1842 phv_enabled_new ? "Enabled" : "Disabled"); 1843 } 1844 return 0; 1845 } 1846 1847 static u32 mlx4_en_get_priv_flags(struct net_device *dev) 1848 { 1849 struct mlx4_en_priv *priv = netdev_priv(dev); 1850 1851 return priv->pflags; 1852 } 1853 1854 static int mlx4_en_get_tunable(struct net_device *dev, 1855 const struct ethtool_tunable *tuna, 1856 void *data) 1857 { 1858 const struct mlx4_en_priv *priv = netdev_priv(dev); 1859 int ret = 0; 1860 1861 switch (tuna->id) { 1862 case ETHTOOL_TX_COPYBREAK: 1863 *(u32 *)data = priv->prof->inline_thold; 1864 break; 1865 default: 1866 ret = -EINVAL; 1867 break; 1868 } 1869 1870 return ret; 1871 } 1872 1873 static int mlx4_en_set_tunable(struct net_device *dev, 1874 const struct ethtool_tunable *tuna, 1875 const void *data) 1876 { 1877 struct mlx4_en_priv *priv = netdev_priv(dev); 1878 int val, ret = 0; 1879 1880 switch (tuna->id) { 1881 case ETHTOOL_TX_COPYBREAK: 1882 val = *(u32 *)data; 1883 if (val < MIN_PKT_LEN || val > MAX_INLINE) 1884 ret = -EINVAL; 1885 else 1886 priv->prof->inline_thold = val; 1887 break; 1888 default: 1889 ret = -EINVAL; 1890 break; 1891 } 1892 1893 return ret; 1894 } 1895 1896 static int mlx4_en_get_module_info(struct net_device *dev, 1897 struct ethtool_modinfo *modinfo) 1898 { 1899 struct mlx4_en_priv *priv = netdev_priv(dev); 1900 struct mlx4_en_dev *mdev = priv->mdev; 1901 int ret; 1902 u8 data[4]; 1903 1904 /* Read first 2 bytes to get Module & REV ID */ 1905 ret = mlx4_get_module_info(mdev->dev, priv->port, 1906 0/*offset*/, 2/*size*/, data); 1907 if (ret < 2) 1908 return -EIO; 1909 1910 switch (data[0] /* identifier */) { 1911 case MLX4_MODULE_ID_QSFP: 1912 modinfo->type = ETH_MODULE_SFF_8436; 1913 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 1914 break; 1915 case MLX4_MODULE_ID_QSFP_PLUS: 1916 if (data[1] >= 0x3) { /* revision id */ 1917 modinfo->type = ETH_MODULE_SFF_8636; 1918 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 1919 } else { 1920 modinfo->type = ETH_MODULE_SFF_8436; 1921 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 1922 } 1923 break; 1924 case MLX4_MODULE_ID_QSFP28: 1925 modinfo->type = ETH_MODULE_SFF_8636; 1926 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 1927 break; 1928 case MLX4_MODULE_ID_SFP: 1929 modinfo->type = ETH_MODULE_SFF_8472; 1930 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1931 break; 1932 default: 1933 return -ENOSYS; 1934 } 1935 1936 return 0; 1937 } 1938 1939 static int mlx4_en_get_module_eeprom(struct net_device *dev, 1940 struct ethtool_eeprom *ee, 1941 u8 *data) 1942 { 1943 struct mlx4_en_priv *priv = netdev_priv(dev); 1944 struct mlx4_en_dev *mdev = priv->mdev; 1945 int offset = ee->offset; 1946 int i = 0, ret; 1947 1948 if (ee->len == 0) 1949 return -EINVAL; 1950 1951 memset(data, 0, ee->len); 1952 1953 while (i < ee->len) { 1954 en_dbg(DRV, priv, 1955 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n", 1956 i, offset, ee->len - i); 1957 1958 ret = mlx4_get_module_info(mdev->dev, priv->port, 1959 offset, ee->len - i, data + i); 1960 1961 if (!ret) /* Done reading */ 1962 return 0; 1963 1964 if (ret < 0) { 1965 en_err(priv, 1966 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n", 1967 i, offset, ee->len - i, ret); 1968 return 0; 1969 } 1970 1971 i += ret; 1972 offset += ret; 1973 } 1974 return 0; 1975 } 1976 1977 static int mlx4_en_set_phys_id(struct net_device *dev, 1978 enum ethtool_phys_id_state state) 1979 { 1980 int err; 1981 u16 beacon_duration; 1982 struct mlx4_en_priv *priv = netdev_priv(dev); 1983 struct mlx4_en_dev *mdev = priv->mdev; 1984 1985 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON)) 1986 return -EOPNOTSUPP; 1987 1988 switch (state) { 1989 case ETHTOOL_ID_ACTIVE: 1990 beacon_duration = PORT_BEACON_MAX_LIMIT; 1991 break; 1992 case ETHTOOL_ID_INACTIVE: 1993 beacon_duration = 0; 1994 break; 1995 default: 1996 return -EOPNOTSUPP; 1997 } 1998 1999 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration); 2000 return err; 2001 } 2002 2003 const struct ethtool_ops mlx4_en_ethtool_ops = { 2004 .get_drvinfo = mlx4_en_get_drvinfo, 2005 .get_settings = mlx4_en_get_settings, 2006 .set_settings = mlx4_en_set_settings, 2007 .get_link = ethtool_op_get_link, 2008 .get_strings = mlx4_en_get_strings, 2009 .get_sset_count = mlx4_en_get_sset_count, 2010 .get_ethtool_stats = mlx4_en_get_ethtool_stats, 2011 .self_test = mlx4_en_self_test, 2012 .set_phys_id = mlx4_en_set_phys_id, 2013 .get_wol = mlx4_en_get_wol, 2014 .set_wol = mlx4_en_set_wol, 2015 .get_msglevel = mlx4_en_get_msglevel, 2016 .set_msglevel = mlx4_en_set_msglevel, 2017 .get_coalesce = mlx4_en_get_coalesce, 2018 .set_coalesce = mlx4_en_set_coalesce, 2019 .get_pauseparam = mlx4_en_get_pauseparam, 2020 .set_pauseparam = mlx4_en_set_pauseparam, 2021 .get_ringparam = mlx4_en_get_ringparam, 2022 .set_ringparam = mlx4_en_set_ringparam, 2023 .get_rxnfc = mlx4_en_get_rxnfc, 2024 .set_rxnfc = mlx4_en_set_rxnfc, 2025 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size, 2026 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size, 2027 .get_rxfh = mlx4_en_get_rxfh, 2028 .set_rxfh = mlx4_en_set_rxfh, 2029 .get_channels = mlx4_en_get_channels, 2030 .set_channels = mlx4_en_set_channels, 2031 .get_ts_info = mlx4_en_get_ts_info, 2032 .set_priv_flags = mlx4_en_set_priv_flags, 2033 .get_priv_flags = mlx4_en_get_priv_flags, 2034 .get_tunable = mlx4_en_get_tunable, 2035 .set_tunable = mlx4_en_set_tunable, 2036 .get_module_info = mlx4_en_get_module_info, 2037 .get_module_eeprom = mlx4_en_get_module_eeprom 2038 }; 2039 2040 2041 2042 2043 2044