1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/sched.h> 36 #include <linux/slab.h> 37 #include <linux/export.h> 38 #include <linux/pci.h> 39 #include <linux/errno.h> 40 41 #include <linux/mlx4/cmd.h> 42 43 #include <asm/io.h> 44 45 #include "mlx4.h" 46 47 #define CMD_POLL_TOKEN 0xffff 48 49 enum { 50 /* command completed successfully: */ 51 CMD_STAT_OK = 0x00, 52 /* Internal error (such as a bus error) occurred while processing command: */ 53 CMD_STAT_INTERNAL_ERR = 0x01, 54 /* Operation/command not supported or opcode modifier not supported: */ 55 CMD_STAT_BAD_OP = 0x02, 56 /* Parameter not supported or parameter out of range: */ 57 CMD_STAT_BAD_PARAM = 0x03, 58 /* System not enabled or bad system state: */ 59 CMD_STAT_BAD_SYS_STATE = 0x04, 60 /* Attempt to access reserved or unallocaterd resource: */ 61 CMD_STAT_BAD_RESOURCE = 0x05, 62 /* Requested resource is currently executing a command, or is otherwise busy: */ 63 CMD_STAT_RESOURCE_BUSY = 0x06, 64 /* Required capability exceeds device limits: */ 65 CMD_STAT_EXCEED_LIM = 0x08, 66 /* Resource is not in the appropriate state or ownership: */ 67 CMD_STAT_BAD_RES_STATE = 0x09, 68 /* Index out of range: */ 69 CMD_STAT_BAD_INDEX = 0x0a, 70 /* FW image corrupted: */ 71 CMD_STAT_BAD_NVMEM = 0x0b, 72 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */ 73 CMD_STAT_ICM_ERROR = 0x0c, 74 /* Attempt to modify a QP/EE which is not in the presumed state: */ 75 CMD_STAT_BAD_QP_STATE = 0x10, 76 /* Bad segment parameters (Address/Size): */ 77 CMD_STAT_BAD_SEG_PARAM = 0x20, 78 /* Memory Region has Memory Windows bound to: */ 79 CMD_STAT_REG_BOUND = 0x21, 80 /* HCA local attached memory not present: */ 81 CMD_STAT_LAM_NOT_PRE = 0x22, 82 /* Bad management packet (silently discarded): */ 83 CMD_STAT_BAD_PKT = 0x30, 84 /* More outstanding CQEs in CQ than new CQ size: */ 85 CMD_STAT_BAD_SIZE = 0x40, 86 /* Multi Function device support required: */ 87 CMD_STAT_MULTI_FUNC_REQ = 0x50, 88 }; 89 90 enum { 91 HCR_IN_PARAM_OFFSET = 0x00, 92 HCR_IN_MODIFIER_OFFSET = 0x08, 93 HCR_OUT_PARAM_OFFSET = 0x0c, 94 HCR_TOKEN_OFFSET = 0x14, 95 HCR_STATUS_OFFSET = 0x18, 96 97 HCR_OPMOD_SHIFT = 12, 98 HCR_T_BIT = 21, 99 HCR_E_BIT = 22, 100 HCR_GO_BIT = 23 101 }; 102 103 enum { 104 GO_BIT_TIMEOUT_MSECS = 10000 105 }; 106 107 struct mlx4_cmd_context { 108 struct completion done; 109 int result; 110 int next; 111 u64 out_param; 112 u16 token; 113 }; 114 115 static int mlx4_status_to_errno(u8 status) 116 { 117 static const int trans_table[] = { 118 [CMD_STAT_INTERNAL_ERR] = -EIO, 119 [CMD_STAT_BAD_OP] = -EPERM, 120 [CMD_STAT_BAD_PARAM] = -EINVAL, 121 [CMD_STAT_BAD_SYS_STATE] = -ENXIO, 122 [CMD_STAT_BAD_RESOURCE] = -EBADF, 123 [CMD_STAT_RESOURCE_BUSY] = -EBUSY, 124 [CMD_STAT_EXCEED_LIM] = -ENOMEM, 125 [CMD_STAT_BAD_RES_STATE] = -EBADF, 126 [CMD_STAT_BAD_INDEX] = -EBADF, 127 [CMD_STAT_BAD_NVMEM] = -EFAULT, 128 [CMD_STAT_ICM_ERROR] = -ENFILE, 129 [CMD_STAT_BAD_QP_STATE] = -EINVAL, 130 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT, 131 [CMD_STAT_REG_BOUND] = -EBUSY, 132 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN, 133 [CMD_STAT_BAD_PKT] = -EINVAL, 134 [CMD_STAT_BAD_SIZE] = -ENOMEM, 135 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES, 136 }; 137 138 if (status >= ARRAY_SIZE(trans_table) || 139 (status != CMD_STAT_OK && trans_table[status] == 0)) 140 return -EIO; 141 142 return trans_table[status]; 143 } 144 145 static int cmd_pending(struct mlx4_dev *dev) 146 { 147 u32 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET); 148 149 return (status & swab32(1 << HCR_GO_BIT)) || 150 (mlx4_priv(dev)->cmd.toggle == 151 !!(status & swab32(1 << HCR_T_BIT))); 152 } 153 154 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param, 155 u32 in_modifier, u8 op_modifier, u16 op, u16 token, 156 int event) 157 { 158 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 159 u32 __iomem *hcr = cmd->hcr; 160 int ret = -EAGAIN; 161 unsigned long end; 162 163 mutex_lock(&cmd->hcr_mutex); 164 165 end = jiffies; 166 if (event) 167 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS); 168 169 while (cmd_pending(dev)) { 170 if (time_after_eq(jiffies, end)) 171 goto out; 172 cond_resched(); 173 } 174 175 /* 176 * We use writel (instead of something like memcpy_toio) 177 * because writes of less than 32 bits to the HCR don't work 178 * (and some architectures such as ia64 implement memcpy_toio 179 * in terms of writeb). 180 */ 181 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0); 182 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1); 183 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2); 184 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3); 185 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4); 186 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5); 187 188 /* __raw_writel may not order writes. */ 189 wmb(); 190 191 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | 192 (cmd->toggle << HCR_T_BIT) | 193 (event ? (1 << HCR_E_BIT) : 0) | 194 (op_modifier << HCR_OPMOD_SHIFT) | 195 op), hcr + 6); 196 197 /* 198 * Make sure that our HCR writes don't get mixed in with 199 * writes from another CPU starting a FW command. 200 */ 201 mmiowb(); 202 203 cmd->toggle = cmd->toggle ^ 1; 204 205 ret = 0; 206 207 out: 208 mutex_unlock(&cmd->hcr_mutex); 209 return ret; 210 } 211 212 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 213 int out_is_imm, u32 in_modifier, u8 op_modifier, 214 u16 op, unsigned long timeout) 215 { 216 struct mlx4_priv *priv = mlx4_priv(dev); 217 void __iomem *hcr = priv->cmd.hcr; 218 int err = 0; 219 unsigned long end; 220 221 down(&priv->cmd.poll_sem); 222 223 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0, 224 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0); 225 if (err) 226 goto out; 227 228 end = msecs_to_jiffies(timeout) + jiffies; 229 while (cmd_pending(dev) && time_before(jiffies, end)) 230 cond_resched(); 231 232 if (cmd_pending(dev)) { 233 err = -ETIMEDOUT; 234 goto out; 235 } 236 237 if (out_is_imm) 238 *out_param = 239 (u64) be32_to_cpu((__force __be32) 240 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 | 241 (u64) be32_to_cpu((__force __be32) 242 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4)); 243 244 err = mlx4_status_to_errno(be32_to_cpu((__force __be32) 245 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24); 246 247 out: 248 up(&priv->cmd.poll_sem); 249 return err; 250 } 251 252 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param) 253 { 254 struct mlx4_priv *priv = mlx4_priv(dev); 255 struct mlx4_cmd_context *context = 256 &priv->cmd.context[token & priv->cmd.token_mask]; 257 258 /* previously timed out command completing at long last */ 259 if (token != context->token) 260 return; 261 262 context->result = mlx4_status_to_errno(status); 263 context->out_param = out_param; 264 265 complete(&context->done); 266 } 267 268 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 269 int out_is_imm, u32 in_modifier, u8 op_modifier, 270 u16 op, unsigned long timeout) 271 { 272 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 273 struct mlx4_cmd_context *context; 274 int err = 0; 275 276 down(&cmd->event_sem); 277 278 spin_lock(&cmd->context_lock); 279 BUG_ON(cmd->free_head < 0); 280 context = &cmd->context[cmd->free_head]; 281 context->token += cmd->token_mask + 1; 282 cmd->free_head = context->next; 283 spin_unlock(&cmd->context_lock); 284 285 init_completion(&context->done); 286 287 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0, 288 in_modifier, op_modifier, op, context->token, 1); 289 290 if (!wait_for_completion_timeout(&context->done, msecs_to_jiffies(timeout))) { 291 err = -EBUSY; 292 goto out; 293 } 294 295 err = context->result; 296 if (err) 297 goto out; 298 299 if (out_is_imm) 300 *out_param = context->out_param; 301 302 out: 303 spin_lock(&cmd->context_lock); 304 context->next = cmd->free_head; 305 cmd->free_head = context - cmd->context; 306 spin_unlock(&cmd->context_lock); 307 308 up(&cmd->event_sem); 309 return err; 310 } 311 312 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 313 int out_is_imm, u32 in_modifier, u8 op_modifier, 314 u16 op, unsigned long timeout) 315 { 316 if (mlx4_priv(dev)->cmd.use_events) 317 return mlx4_cmd_wait(dev, in_param, out_param, out_is_imm, 318 in_modifier, op_modifier, op, timeout); 319 else 320 return mlx4_cmd_poll(dev, in_param, out_param, out_is_imm, 321 in_modifier, op_modifier, op, timeout); 322 } 323 EXPORT_SYMBOL_GPL(__mlx4_cmd); 324 325 int mlx4_cmd_init(struct mlx4_dev *dev) 326 { 327 struct mlx4_priv *priv = mlx4_priv(dev); 328 329 mutex_init(&priv->cmd.hcr_mutex); 330 sema_init(&priv->cmd.poll_sem, 1); 331 priv->cmd.use_events = 0; 332 priv->cmd.toggle = 1; 333 334 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_HCR_BASE, 335 MLX4_HCR_SIZE); 336 if (!priv->cmd.hcr) { 337 mlx4_err(dev, "Couldn't map command register."); 338 return -ENOMEM; 339 } 340 341 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev, 342 MLX4_MAILBOX_SIZE, 343 MLX4_MAILBOX_SIZE, 0); 344 if (!priv->cmd.pool) { 345 iounmap(priv->cmd.hcr); 346 return -ENOMEM; 347 } 348 349 return 0; 350 } 351 352 void mlx4_cmd_cleanup(struct mlx4_dev *dev) 353 { 354 struct mlx4_priv *priv = mlx4_priv(dev); 355 356 pci_pool_destroy(priv->cmd.pool); 357 iounmap(priv->cmd.hcr); 358 } 359 360 /* 361 * Switch to using events to issue FW commands (can only be called 362 * after event queue for command events has been initialized). 363 */ 364 int mlx4_cmd_use_events(struct mlx4_dev *dev) 365 { 366 struct mlx4_priv *priv = mlx4_priv(dev); 367 int i; 368 369 priv->cmd.context = kmalloc(priv->cmd.max_cmds * 370 sizeof (struct mlx4_cmd_context), 371 GFP_KERNEL); 372 if (!priv->cmd.context) 373 return -ENOMEM; 374 375 for (i = 0; i < priv->cmd.max_cmds; ++i) { 376 priv->cmd.context[i].token = i; 377 priv->cmd.context[i].next = i + 1; 378 } 379 380 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1; 381 priv->cmd.free_head = 0; 382 383 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds); 384 spin_lock_init(&priv->cmd.context_lock); 385 386 for (priv->cmd.token_mask = 1; 387 priv->cmd.token_mask < priv->cmd.max_cmds; 388 priv->cmd.token_mask <<= 1) 389 ; /* nothing */ 390 --priv->cmd.token_mask; 391 392 priv->cmd.use_events = 1; 393 394 down(&priv->cmd.poll_sem); 395 396 return 0; 397 } 398 399 /* 400 * Switch back to polling (used when shutting down the device) 401 */ 402 void mlx4_cmd_use_polling(struct mlx4_dev *dev) 403 { 404 struct mlx4_priv *priv = mlx4_priv(dev); 405 int i; 406 407 priv->cmd.use_events = 0; 408 409 for (i = 0; i < priv->cmd.max_cmds; ++i) 410 down(&priv->cmd.event_sem); 411 412 kfree(priv->cmd.context); 413 414 up(&priv->cmd.poll_sem); 415 } 416 417 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev) 418 { 419 struct mlx4_cmd_mailbox *mailbox; 420 421 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL); 422 if (!mailbox) 423 return ERR_PTR(-ENOMEM); 424 425 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL, 426 &mailbox->dma); 427 if (!mailbox->buf) { 428 kfree(mailbox); 429 return ERR_PTR(-ENOMEM); 430 } 431 432 return mailbox; 433 } 434 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox); 435 436 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox) 437 { 438 if (!mailbox) 439 return; 440 441 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma); 442 kfree(mailbox); 443 } 444 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox); 445