1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include <linux/bitfield.h> 21 #include <net/page_pool/types.h> 22 #include <linux/bpf_trace.h> 23 #include "mtk_ppe.h" 24 25 #define MTK_MAX_DSA_PORTS 7 26 #define MTK_DSA_PORT_MASK GENMASK(2, 0) 27 28 #define MTK_QDMA_NUM_QUEUES 16 29 #define MTK_QDMA_PAGE_SIZE 2048 30 #define MTK_MAX_RX_LENGTH 1536 31 #define MTK_MAX_RX_LENGTH_2K 2048 32 #define MTK_TX_DMA_BUF_LEN 0x3fff 33 #define MTK_TX_DMA_BUF_LEN_V2 0xffff 34 #define MTK_QDMA_RING_SIZE 2048 35 #define MTK_DMA_SIZE(x) (SZ_##x) 36 #define MTK_FQ_DMA_HEAD 32 37 #define MTK_FQ_DMA_LENGTH 2048 38 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 39 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 40 #define MTK_DMA_DUMMY_DESC 0xffffffff 41 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 42 NETIF_MSG_PROBE | \ 43 NETIF_MSG_LINK | \ 44 NETIF_MSG_TIMER | \ 45 NETIF_MSG_IFDOWN | \ 46 NETIF_MSG_IFUP | \ 47 NETIF_MSG_RX_ERR | \ 48 NETIF_MSG_TX_ERR) 49 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 50 NETIF_F_RXCSUM | \ 51 NETIF_F_HW_VLAN_CTAG_TX | \ 52 NETIF_F_SG | NETIF_F_TSO | \ 53 NETIF_F_TSO6 | \ 54 NETIF_F_IPV6_CSUM |\ 55 NETIF_F_HW_TC) 56 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 57 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 58 59 #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 60 #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 61 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 62 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 63 64 #define MTK_QRX_OFFSET 0x10 65 66 #define MTK_MAX_RX_RING_NUM 4 67 #define MTK_HW_LRO_DMA_SIZE 8 68 69 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 70 #define MTK_MAX_LRO_IP_CNT 2 71 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 72 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 73 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 74 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 75 #define MTK_HW_LRO_MAX_AGG_CNT 64 76 #define MTK_HW_LRO_BW_THRE 3000 77 #define MTK_HW_LRO_REPLACE_DELTA 1000 78 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 79 80 /* Frame Engine Global Configuration */ 81 #define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00) 82 #define MTK_FE_LINK_DOWN_P(x) BIT(((x) + 8) % 16) 83 84 /* Frame Engine Global Reset Register */ 85 #define MTK_RST_GL 0x04 86 #define RST_GL_PSE BIT(0) 87 88 /* Frame Engine Interrupt Status Register */ 89 #define MTK_INT_STATUS2 0x08 90 #define MTK_FE_INT_ENABLE 0x0c 91 #define MTK_FE_INT_FQ_EMPTY BIT(8) 92 #define MTK_FE_INT_TSO_FAIL BIT(12) 93 #define MTK_FE_INT_TSO_ILLEGAL BIT(13) 94 #define MTK_FE_INT_TSO_ALIGN BIT(14) 95 #define MTK_FE_INT_RFIFO_OV BIT(18) 96 #define MTK_FE_INT_RFIFO_UF BIT(19) 97 #define MTK_GDM1_AF BIT(28) 98 #define MTK_GDM2_AF BIT(29) 99 100 /* PDMA HW LRO Alter Flow Timer Register */ 101 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 102 103 /* Frame Engine Interrupt Grouping Register */ 104 #define MTK_FE_INT_GRP 0x20 105 106 /* CDMP Ingress Control Register */ 107 #define MTK_CDMQ_IG_CTRL 0x1400 108 #define MTK_CDMQ_STAG_EN BIT(0) 109 110 /* CDMQ Exgress Control Register */ 111 #define MTK_CDMQ_EG_CTRL 0x1404 112 113 /* CDMP Ingress Control Register */ 114 #define MTK_CDMP_IG_CTRL 0x400 115 #define MTK_CDMP_STAG_EN BIT(0) 116 117 /* CDMP Exgress Control Register */ 118 #define MTK_CDMP_EG_CTRL 0x404 119 120 /* GDM Exgress Control Register */ 121 #define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 122 0x540 : 0x500 + (_x * 0x1000); }) 123 #define MTK_GDMA_SPECIAL_TAG BIT(24) 124 #define MTK_GDMA_ICS_EN BIT(22) 125 #define MTK_GDMA_TCS_EN BIT(21) 126 #define MTK_GDMA_UCS_EN BIT(20) 127 #define MTK_GDMA_STRP_CRC BIT(16) 128 #define MTK_GDMA_TO_PDMA 0x0 129 #define MTK_GDMA_DROP_ALL 0x7777 130 131 /* GDM Egress Control Register */ 132 #define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 133 0x544 : 0x504 + (_x * 0x1000); }) 134 #define MTK_GDMA_XGDM_SEL BIT(31) 135 136 /* Unicast Filter MAC Address Register - Low */ 137 #define MTK_GDMA_MAC_ADRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 138 0x548 : 0x508 + (_x * 0x1000); }) 139 140 /* Unicast Filter MAC Address Register - High */ 141 #define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 142 0x54C : 0x50C + (_x * 0x1000); }) 143 144 /* Internal SRAM offset */ 145 #define MTK_ETH_SRAM_OFFSET 0x40000 146 147 /* FE global misc reg*/ 148 #define MTK_FE_GLO_MISC 0x124 149 150 /* PSE Free Queue Flow Control */ 151 #define PSE_FQFC_CFG1 0x100 152 #define PSE_FQFC_CFG2 0x104 153 #define PSE_DROP_CFG 0x108 154 #define PSE_PPE0_DROP 0x110 155 156 /* PSE Input Queue Reservation Register*/ 157 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 158 159 /* PSE Output Queue Threshold Register*/ 160 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 161 162 /* GDM and CDM Threshold */ 163 #define MTK_GDM2_THRES 0x1530 164 #define MTK_CDMW0_THRES 0x164c 165 #define MTK_CDMW1_THRES 0x1650 166 #define MTK_CDME0_THRES 0x1654 167 #define MTK_CDME1_THRES 0x1658 168 #define MTK_CDMM_THRES 0x165c 169 170 /* PDMA HW LRO Control Registers */ 171 #define MTK_PDMA_LRO_CTRL_DW0 0x980 172 #define MTK_LRO_EN BIT(0) 173 #define MTK_L3_CKS_UPD_EN BIT(7) 174 #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 175 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 176 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 177 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 178 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 179 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 180 181 #define MTK_PDMA_LRO_CTRL_DW1 0x984 182 #define MTK_PDMA_LRO_CTRL_DW2 0x988 183 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 184 #define MTK_ADMA_MODE BIT(15) 185 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 186 187 #define MTK_RX_DMA_LRO_EN BIT(8) 188 #define MTK_MULTI_EN BIT(10) 189 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 190 191 /* PDMA Global Configuration Register */ 192 #define MTK_PDMA_LRO_SDL 0x3000 193 #define MTK_RX_CFG_SDL_OFFSET 16 194 195 /* PDMA Reset Index Register */ 196 #define MTK_PST_DRX_IDX0 BIT(16) 197 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 198 199 /* PDMA Delay Interrupt Register */ 200 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 201 #define MTK_PDMA_DELAY_RX_EN BIT(15) 202 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 203 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 204 205 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 206 #define MTK_PDMA_DELAY_TX_EN BIT(31) 207 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 208 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 209 210 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 211 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 212 213 /* PDMA HW LRO Alter Flow Delta Register */ 214 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 215 216 /* PDMA HW LRO IP Setting Registers */ 217 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 218 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 219 #define MTK_RING_MYIP_VLD BIT(9) 220 221 /* PDMA HW LRO Ring Control Registers */ 222 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 223 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 224 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 225 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 226 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 227 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 228 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 229 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 230 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 231 #define MTK_RING_VLD BIT(8) 232 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 233 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 234 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 235 236 /* QDMA TX Queue Configuration Registers */ 237 #define MTK_QTX_OFFSET 0x10 238 #define QDMA_RES_THRES 4 239 240 /* QDMA Tx Queue Scheduler Configuration Registers */ 241 #define MTK_QTX_SCH_TX_SEL BIT(31) 242 #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30) 243 244 #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30) 245 #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28) 246 #define MTK_QTX_SCH_MIN_RATE_EN BIT(27) 247 #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20) 248 #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16) 249 #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12) 250 #define MTK_QTX_SCH_MAX_RATE_EN BIT(11) 251 #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) 252 #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) 253 254 /* QDMA TX Scheduler Rate Control Register */ 255 #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) 256 257 /* QDMA Global Configuration Register */ 258 #define MTK_RX_2B_OFFSET BIT(31) 259 #define MTK_RX_BT_32DWORDS (3 << 11) 260 #define MTK_NDP_CO_PRO BIT(10) 261 #define MTK_TX_WB_DDONE BIT(6) 262 #define MTK_TX_BT_32DWORDS (3 << 4) 263 #define MTK_RX_DMA_BUSY BIT(3) 264 #define MTK_TX_DMA_BUSY BIT(1) 265 #define MTK_RX_DMA_EN BIT(2) 266 #define MTK_TX_DMA_EN BIT(0) 267 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 268 269 /* QDMA V2 Global Configuration Register */ 270 #define MTK_CHK_DDONE_EN BIT(28) 271 #define MTK_DMAD_WR_WDONE BIT(26) 272 #define MTK_WCOMP_EN BIT(24) 273 #define MTK_RESV_BUF (0x40 << 16) 274 #define MTK_MUTLI_CNT (0x4 << 12) 275 #define MTK_LEAKY_BUCKET_EN BIT(11) 276 277 /* QDMA Flow Control Register */ 278 #define FC_THRES_DROP_MODE BIT(20) 279 #define FC_THRES_DROP_EN (7 << 16) 280 #define FC_THRES_MIN 0x4444 281 282 /* QDMA Interrupt Status Register */ 283 #define MTK_RX_DONE_DLY BIT(30) 284 #define MTK_TX_DONE_DLY BIT(28) 285 #define MTK_RX_DONE_INT3 BIT(19) 286 #define MTK_RX_DONE_INT2 BIT(18) 287 #define MTK_RX_DONE_INT1 BIT(17) 288 #define MTK_RX_DONE_INT0 BIT(16) 289 #define MTK_TX_DONE_INT3 BIT(3) 290 #define MTK_TX_DONE_INT2 BIT(2) 291 #define MTK_TX_DONE_INT1 BIT(1) 292 #define MTK_TX_DONE_INT0 BIT(0) 293 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 294 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 295 296 #define MTK_RX_DONE_INT_V2 BIT(14) 297 298 #define MTK_CDM_TXFIFO_RDY BIT(7) 299 300 /* QDMA Interrupt grouping registers */ 301 #define MTK_RLS_DONE_INT BIT(0) 302 303 /* QDMA TX NUM */ 304 #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 305 #define MTK_QDMA_GMAC2_QID 8 306 307 #define MTK_TX_DMA_BUF_SHIFT 8 308 309 /* QDMA V2 descriptor txd6 */ 310 #define TX_DMA_INS_VLAN_V2 BIT(16) 311 /* QDMA V2 descriptor txd5 */ 312 #define TX_DMA_CHKSUM_V2 (0x7 << 28) 313 #define TX_DMA_TSO_V2 BIT(31) 314 315 #define TX_DMA_SPTAG_V3 BIT(27) 316 317 /* QDMA V2 descriptor txd4 */ 318 #define TX_DMA_FPORT_SHIFT_V2 8 319 #define TX_DMA_FPORT_MASK_V2 0xf 320 #define TX_DMA_SWC_V2 BIT(30) 321 322 /* QDMA descriptor txd4 */ 323 #define TX_DMA_CHKSUM (0x7 << 29) 324 #define TX_DMA_TSO BIT(28) 325 #define TX_DMA_FPORT_SHIFT 25 326 #define TX_DMA_FPORT_MASK 0x7 327 #define TX_DMA_INS_VLAN BIT(16) 328 329 /* QDMA descriptor txd3 */ 330 #define TX_DMA_OWNER_CPU BIT(31) 331 #define TX_DMA_LS0 BIT(30) 332 #define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset) 333 #define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len) 334 #define TX_DMA_SWC BIT(14) 335 #define TX_DMA_PQID GENMASK(3, 0) 336 #define TX_DMA_ADDR64_MASK GENMASK(3, 0) 337 #if IS_ENABLED(CONFIG_64BIT) 338 # define TX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(TX_DMA_ADDR64_MASK, (x))) << 32) 339 # define TX_DMA_PREP_ADDR64(x) FIELD_PREP(TX_DMA_ADDR64_MASK, ((x) >> 32)) 340 #else 341 # define TX_DMA_GET_ADDR64(x) (0) 342 # define TX_DMA_PREP_ADDR64(x) (0) 343 #endif 344 345 /* PDMA on MT7628 */ 346 #define TX_DMA_DONE BIT(31) 347 #define TX_DMA_LS1 BIT(14) 348 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 349 350 /* QDMA descriptor rxd2 */ 351 #define RX_DMA_DONE BIT(31) 352 #define RX_DMA_LSO BIT(30) 353 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset) 354 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len) 355 #define RX_DMA_VTAG BIT(15) 356 #define RX_DMA_ADDR64_MASK GENMASK(3, 0) 357 #if IS_ENABLED(CONFIG_64BIT) 358 # define RX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(RX_DMA_ADDR64_MASK, (x))) << 32) 359 # define RX_DMA_PREP_ADDR64(x) FIELD_PREP(RX_DMA_ADDR64_MASK, ((x) >> 32)) 360 #else 361 # define RX_DMA_GET_ADDR64(x) (0) 362 # define RX_DMA_PREP_ADDR64(x) (0) 363 #endif 364 365 /* QDMA descriptor rxd3 */ 366 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 367 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 368 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 369 370 /* QDMA descriptor rxd4 */ 371 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 372 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 373 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 374 #define MTK_RXD4_ALG GENMASK(31, 22) 375 376 /* QDMA descriptor rxd4 */ 377 #define RX_DMA_L4_VALID BIT(24) 378 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 379 #define RX_DMA_SPECIAL_TAG BIT(22) 380 381 /* PDMA descriptor rxd5 */ 382 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 383 #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 384 #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 385 386 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 387 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 388 389 /* PDMA V2 descriptor rxd3 */ 390 #define RX_DMA_VTAG_V2 BIT(0) 391 #define RX_DMA_L4_VALID_V2 BIT(2) 392 393 /* PHY Polling and SMI Master Control registers */ 394 #define MTK_PPSC 0x10000 395 #define PPSC_MDC_CFG GENMASK(29, 24) 396 #define PPSC_MDC_TURBO BIT(20) 397 #define MDC_MAX_FREQ 25000000 398 #define MDC_MAX_DIVIDER 63 399 400 /* PHY Indirect Access Control registers */ 401 #define MTK_PHY_IAC 0x10004 402 #define PHY_IAC_ACCESS BIT(31) 403 #define PHY_IAC_REG_MASK GENMASK(29, 25) 404 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 405 #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 406 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 407 #define PHY_IAC_CMD_MASK GENMASK(19, 18) 408 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 409 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 410 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 411 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 412 #define PHY_IAC_START_MASK GENMASK(17, 16) 413 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 414 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 415 #define PHY_IAC_DATA_MASK GENMASK(15, 0) 416 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 417 #define PHY_IAC_TIMEOUT HZ 418 419 #define MTK_MAC_MISC 0x1000c 420 #define MTK_MAC_MISC_V3 0x10010 421 #define MTK_MUX_TO_ESW BIT(0) 422 #define MISC_MDC_TURBO BIT(4) 423 424 /* XMAC status registers */ 425 #define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) 426 #define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) 427 #define MTK_USXGMII_PCS_LINK BIT(8) 428 #define MTK_XGMAC_RX_FC BIT(5) 429 #define MTK_XGMAC_TX_FC BIT(4) 430 #define MTK_USXGMII_PCS_MODE GENMASK(3, 1) 431 #define MTK_XGMAC_LINK_STS BIT(0) 432 433 /* GSW bridge registers */ 434 #define MTK_GSW_CFG (0x10080) 435 #define GSWTX_IPG_MASK GENMASK(19, 16) 436 #define GSWTX_IPG_SHIFT 16 437 #define GSWRX_IPG_MASK GENMASK(3, 0) 438 #define GSWRX_IPG_SHIFT 0 439 #define GSW_IPG_11 11 440 441 /* Mac control registers */ 442 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 443 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 444 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 445 #define MAC_MCR_MAX_RX_1518 0x0 446 #define MAC_MCR_MAX_RX_1536 0x1 447 #define MAC_MCR_MAX_RX_1552 0x2 448 #define MAC_MCR_MAX_RX_2048 0x3 449 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 450 #define MAC_MCR_FORCE_MODE BIT(15) 451 #define MAC_MCR_TX_EN BIT(14) 452 #define MAC_MCR_RX_EN BIT(13) 453 #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12) 454 #define MAC_MCR_BACKOFF_EN BIT(9) 455 #define MAC_MCR_BACKPR_EN BIT(8) 456 #define MAC_MCR_FORCE_RX_FC BIT(5) 457 #define MAC_MCR_FORCE_TX_FC BIT(4) 458 #define MAC_MCR_SPEED_1000 BIT(3) 459 #define MAC_MCR_SPEED_100 BIT(2) 460 #define MAC_MCR_FORCE_DPX BIT(1) 461 #define MAC_MCR_FORCE_LINK BIT(0) 462 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 463 464 /* Mac status registers */ 465 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 466 #define MAC_MSR_EEE1G BIT(7) 467 #define MAC_MSR_EEE100M BIT(6) 468 #define MAC_MSR_RX_FC BIT(5) 469 #define MAC_MSR_TX_FC BIT(4) 470 #define MAC_MSR_SPEED_1000 BIT(3) 471 #define MAC_MSR_SPEED_100 BIT(2) 472 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 473 #define MAC_MSR_DPX BIT(1) 474 #define MAC_MSR_LINK BIT(0) 475 476 /* TRGMII RXC control register */ 477 #define TRGMII_RCK_CTRL 0x10300 478 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 479 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 480 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 481 #define RXC_RST BIT(31) 482 #define RXC_DQSISEL BIT(30) 483 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 484 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 485 486 #define NUM_TRGMII_CTRL 5 487 488 /* TRGMII RXC control register */ 489 #define TRGMII_TCK_CTRL 0x10340 490 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 491 #define TXC_INV BIT(30) 492 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 493 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 494 495 /* TRGMII TX Drive Strength */ 496 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 497 #define TD_DM_DRVP(x) ((x) & 0xf) 498 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 499 500 /* TRGMII Interface mode register */ 501 #define INTF_MODE 0x10390 502 #define TRGMII_INTF_DIS BIT(0) 503 #define TRGMII_MODE BIT(1) 504 #define TRGMII_CENTRAL_ALIGNED BIT(2) 505 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 506 #define INTF_MODE_RGMII_10_100 0 507 508 /* GPIO port control registers for GMAC 2*/ 509 #define GPIO_OD33_CTRL8 0x4c0 510 #define GPIO_BIAS_CTRL 0xed0 511 #define GPIO_DRV_SEL10 0xf00 512 513 /* ethernet subsystem chip id register */ 514 #define ETHSYS_CHIPID0_3 0x0 515 #define ETHSYS_CHIPID4_7 0x4 516 #define MT7623_ETH 7623 517 #define MT7622_ETH 7622 518 #define MT7621_ETH 7621 519 520 /* ethernet system control register */ 521 #define ETHSYS_SYSCFG 0x10 522 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 523 524 /* ethernet subsystem config register */ 525 #define ETHSYS_SYSCFG0 0x14 526 #define SYSCFG0_GE_MASK 0x3 527 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 528 #define SYSCFG0_SGMII_MASK GENMASK(9, 7) 529 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 530 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 531 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 532 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 533 534 535 /* ethernet subsystem clock register */ 536 #define ETHSYS_CLKCFG0 0x2c 537 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 538 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 539 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 540 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 541 542 /* ethernet reset control register */ 543 #define ETHSYS_RSTCTRL 0x34 544 #define RSTCTRL_FE BIT(6) 545 #define RSTCTRL_WDMA0 BIT(24) 546 #define RSTCTRL_WDMA1 BIT(25) 547 #define RSTCTRL_WDMA2 BIT(26) 548 #define RSTCTRL_PPE0 BIT(31) 549 #define RSTCTRL_PPE0_V2 BIT(30) 550 #define RSTCTRL_PPE1 BIT(31) 551 #define RSTCTRL_PPE0_V3 BIT(29) 552 #define RSTCTRL_PPE1_V3 BIT(30) 553 #define RSTCTRL_PPE2 BIT(31) 554 #define RSTCTRL_ETH BIT(23) 555 556 /* ethernet reset check idle register */ 557 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 558 559 /* ethernet dma channel agent map */ 560 #define ETHSYS_DMA_AG_MAP 0x408 561 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 562 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 563 #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 564 565 /* Infrasys subsystem config registers */ 566 #define INFRA_MISC2 0x70c 567 #define CO_QPHY_SEL BIT(0) 568 #define GEPHY_MAC_SEL BIT(1) 569 570 /* Top misc registers */ 571 #define USB_PHY_SWITCH_REG 0x218 572 #define QPHY_SEL_MASK GENMASK(1, 0) 573 #define SGMII_QPHY_SEL 0x2 574 575 /* MT7628/88 specific stuff */ 576 #define MT7628_PDMA_OFFSET 0x0800 577 #define MT7628_SDM_OFFSET 0x0c00 578 579 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 580 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 581 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 582 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 583 #define MT7628_PST_DTX_IDX0 BIT(0) 584 585 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 586 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 587 588 /* Counter / stat register */ 589 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 590 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 591 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 592 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 593 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 594 595 #define MTK_FE_CDM1_FSM 0x220 596 #define MTK_FE_CDM2_FSM 0x224 597 #define MTK_FE_CDM3_FSM 0x238 598 #define MTK_FE_CDM4_FSM 0x298 599 #define MTK_FE_CDM5_FSM 0x318 600 #define MTK_FE_CDM6_FSM 0x328 601 #define MTK_FE_GDM1_FSM 0x228 602 #define MTK_FE_GDM2_FSM 0x22C 603 604 #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) 605 606 struct mtk_rx_dma { 607 unsigned int rxd1; 608 unsigned int rxd2; 609 unsigned int rxd3; 610 unsigned int rxd4; 611 } __packed __aligned(4); 612 613 struct mtk_rx_dma_v2 { 614 unsigned int rxd1; 615 unsigned int rxd2; 616 unsigned int rxd3; 617 unsigned int rxd4; 618 unsigned int rxd5; 619 unsigned int rxd6; 620 unsigned int rxd7; 621 unsigned int rxd8; 622 } __packed __aligned(4); 623 624 struct mtk_tx_dma { 625 unsigned int txd1; 626 unsigned int txd2; 627 unsigned int txd3; 628 unsigned int txd4; 629 } __packed __aligned(4); 630 631 struct mtk_tx_dma_v2 { 632 unsigned int txd1; 633 unsigned int txd2; 634 unsigned int txd3; 635 unsigned int txd4; 636 unsigned int txd5; 637 unsigned int txd6; 638 unsigned int txd7; 639 unsigned int txd8; 640 } __packed __aligned(4); 641 642 struct mtk_eth; 643 struct mtk_mac; 644 645 struct mtk_xdp_stats { 646 u64 rx_xdp_redirect; 647 u64 rx_xdp_pass; 648 u64 rx_xdp_drop; 649 u64 rx_xdp_tx; 650 u64 rx_xdp_tx_errors; 651 u64 tx_xdp_xmit; 652 u64 tx_xdp_xmit_errors; 653 }; 654 655 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 656 * @stats_lock: make sure that stats operations are atomic 657 * @reg_offset: the status register offset of the SoC 658 * @syncp: the refcount 659 * 660 * All of the supported SoCs have hardware counters for traffic statistics. 661 * Whenever the status IRQ triggers we can read the latest stats from these 662 * counters and store them in this struct. 663 */ 664 struct mtk_hw_stats { 665 u64 tx_bytes; 666 u64 tx_packets; 667 u64 tx_skip; 668 u64 tx_collisions; 669 u64 rx_bytes; 670 u64 rx_packets; 671 u64 rx_overflow; 672 u64 rx_fcs_errors; 673 u64 rx_short_errors; 674 u64 rx_long_errors; 675 u64 rx_checksum_errors; 676 u64 rx_flow_control_packets; 677 678 struct mtk_xdp_stats xdp_stats; 679 680 spinlock_t stats_lock; 681 u32 reg_offset; 682 struct u64_stats_sync syncp; 683 }; 684 685 enum mtk_tx_flags { 686 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 687 * track how memory was allocated so that it can be freed properly. 688 */ 689 MTK_TX_FLAGS_SINGLE0 = 0x01, 690 MTK_TX_FLAGS_PAGE0 = 0x02, 691 }; 692 693 /* This enum allows us to identify how the clock is defined on the array of the 694 * clock in the order 695 */ 696 enum mtk_clks_map { 697 MTK_CLK_ETHIF, 698 MTK_CLK_SGMIITOP, 699 MTK_CLK_ESW, 700 MTK_CLK_GP0, 701 MTK_CLK_GP1, 702 MTK_CLK_GP2, 703 MTK_CLK_GP3, 704 MTK_CLK_XGP1, 705 MTK_CLK_XGP2, 706 MTK_CLK_XGP3, 707 MTK_CLK_CRYPTO, 708 MTK_CLK_FE, 709 MTK_CLK_TRGPLL, 710 MTK_CLK_SGMII_TX_250M, 711 MTK_CLK_SGMII_RX_250M, 712 MTK_CLK_SGMII_CDR_REF, 713 MTK_CLK_SGMII_CDR_FB, 714 MTK_CLK_SGMII2_TX_250M, 715 MTK_CLK_SGMII2_RX_250M, 716 MTK_CLK_SGMII2_CDR_REF, 717 MTK_CLK_SGMII2_CDR_FB, 718 MTK_CLK_SGMII_CK, 719 MTK_CLK_ETH2PLL, 720 MTK_CLK_WOCPU0, 721 MTK_CLK_WOCPU1, 722 MTK_CLK_NETSYS0, 723 MTK_CLK_NETSYS1, 724 MTK_CLK_ETHWARP_WOCPU2, 725 MTK_CLK_ETHWARP_WOCPU1, 726 MTK_CLK_ETHWARP_WOCPU0, 727 MTK_CLK_TOP_USXGMII_SBUS_0_SEL, 728 MTK_CLK_TOP_USXGMII_SBUS_1_SEL, 729 MTK_CLK_TOP_SGM_0_SEL, 730 MTK_CLK_TOP_SGM_1_SEL, 731 MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, 732 MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, 733 MTK_CLK_TOP_ETH_GMII_SEL, 734 MTK_CLK_TOP_ETH_REFCK_50M_SEL, 735 MTK_CLK_TOP_ETH_SYS_200M_SEL, 736 MTK_CLK_TOP_ETH_SYS_SEL, 737 MTK_CLK_TOP_ETH_XGMII_SEL, 738 MTK_CLK_TOP_ETH_MII_SEL, 739 MTK_CLK_TOP_NETSYS_SEL, 740 MTK_CLK_TOP_NETSYS_500M_SEL, 741 MTK_CLK_TOP_NETSYS_PAO_2X_SEL, 742 MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, 743 MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, 744 MTK_CLK_TOP_NETSYS_WARP_SEL, 745 MTK_CLK_MAX 746 }; 747 748 #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 749 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 750 BIT_ULL(MTK_CLK_TRGPLL)) 751 #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 752 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 753 BIT_ULL(MTK_CLK_GP2) | \ 754 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 755 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 756 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 757 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 758 BIT_ULL(MTK_CLK_SGMII_CK) | \ 759 BIT_ULL(MTK_CLK_ETH2PLL)) 760 #define MT7621_CLKS_BITMAP (0) 761 #define MT7628_CLKS_BITMAP (0) 762 #define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 763 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 764 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ 765 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 766 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 767 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 768 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 769 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 770 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 771 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 772 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 773 BIT_ULL(MTK_CLK_SGMII_CK) | \ 774 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) 775 #define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 776 BIT_ULL(MTK_CLK_GP1) | \ 777 BIT_ULL(MTK_CLK_WOCPU0) | \ 778 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 779 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 780 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 781 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 782 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 783 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 784 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 785 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 786 BIT_ULL(MTK_CLK_SGMII_CK)) 787 #define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 788 BIT_ULL(MTK_CLK_GP1) | \ 789 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ 790 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 791 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 792 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 793 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 794 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 795 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 796 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 797 BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) 798 #define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ 799 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 800 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ 801 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ 802 BIT_ULL(MTK_CLK_CRYPTO) | \ 803 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 804 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 805 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 806 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 807 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ 808 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ 809 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ 810 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ 811 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ 812 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ 813 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ 814 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ 815 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ 816 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ 817 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ 818 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ 819 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ 820 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ 821 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ 822 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ 823 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ 824 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ 825 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ 826 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ 827 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) 828 829 enum mtk_dev_state { 830 MTK_HW_INIT, 831 MTK_RESETTING 832 }; 833 834 /* PSE Port Definition */ 835 enum mtk_pse_port { 836 PSE_ADMA_PORT = 0, 837 PSE_GDM1_PORT, 838 PSE_GDM2_PORT, 839 PSE_PPE0_PORT, 840 PSE_PPE1_PORT, 841 PSE_QDMA_TX_PORT, 842 PSE_QDMA_RX_PORT, 843 PSE_DROP_PORT, 844 PSE_WDMA0_PORT, 845 PSE_WDMA1_PORT, 846 PSE_TDMA_PORT, 847 PSE_NONE_PORT, 848 PSE_PPE2_PORT, 849 PSE_WDMA2_PORT, 850 PSE_EIP197_PORT, 851 PSE_GDM3_PORT, 852 PSE_PORT_MAX 853 }; 854 855 /* GMAC Identifier */ 856 enum mtk_gmac_id { 857 MTK_GMAC1_ID = 0, 858 MTK_GMAC2_ID, 859 MTK_GMAC3_ID, 860 MTK_GMAC_ID_MAX 861 }; 862 863 enum mtk_tx_buf_type { 864 MTK_TYPE_SKB, 865 MTK_TYPE_XDP_TX, 866 MTK_TYPE_XDP_NDO, 867 }; 868 869 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 870 * by the TX descriptor s 871 * @skb: The SKB pointer of the packet being sent 872 * @dma_addr0: The base addr of the first segment 873 * @dma_len0: The length of the first segment 874 * @dma_addr1: The base addr of the second segment 875 * @dma_len1: The length of the second segment 876 */ 877 struct mtk_tx_buf { 878 enum mtk_tx_buf_type type; 879 void *data; 880 881 u16 mac_id; 882 u16 flags; 883 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 884 DEFINE_DMA_UNMAP_LEN(dma_len0); 885 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 886 DEFINE_DMA_UNMAP_LEN(dma_len1); 887 }; 888 889 /* struct mtk_tx_ring - This struct holds info describing a TX ring 890 * @dma: The descriptor ring 891 * @buf: The memory pointed at by the ring 892 * @phys: The physical addr of tx_buf 893 * @next_free: Pointer to the next free descriptor 894 * @last_free: Pointer to the last free descriptor 895 * @last_free_ptr: Hardware pointer value of the last free descriptor 896 * @thresh: The threshold of minimum amount of free descriptors 897 * @free_count: QDMA uses a linked list. Track how many free descriptors 898 * are present 899 */ 900 struct mtk_tx_ring { 901 void *dma; 902 struct mtk_tx_buf *buf; 903 dma_addr_t phys; 904 struct mtk_tx_dma *next_free; 905 struct mtk_tx_dma *last_free; 906 u32 last_free_ptr; 907 u16 thresh; 908 atomic_t free_count; 909 int dma_size; 910 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 911 dma_addr_t phys_pdma; 912 int cpu_idx; 913 }; 914 915 /* PDMA rx ring mode */ 916 enum mtk_rx_flags { 917 MTK_RX_FLAGS_NORMAL = 0, 918 MTK_RX_FLAGS_HWLRO, 919 MTK_RX_FLAGS_QDMA, 920 }; 921 922 /* struct mtk_rx_ring - This struct holds info describing a RX ring 923 * @dma: The descriptor ring 924 * @data: The memory pointed at by the ring 925 * @phys: The physical addr of rx_buf 926 * @frag_size: How big can each fragment be 927 * @buf_size: The size of each packet buffer 928 * @calc_idx: The current head of ring 929 */ 930 struct mtk_rx_ring { 931 void *dma; 932 u8 **data; 933 dma_addr_t phys; 934 u16 frag_size; 935 u16 buf_size; 936 u16 dma_size; 937 bool calc_idx_update; 938 u16 calc_idx; 939 u32 crx_idx_reg; 940 /* page_pool */ 941 struct page_pool *page_pool; 942 struct xdp_rxq_info xdp_q; 943 }; 944 945 enum mkt_eth_capabilities { 946 MTK_RGMII_BIT = 0, 947 MTK_TRGMII_BIT, 948 MTK_SGMII_BIT, 949 MTK_ESW_BIT, 950 MTK_GEPHY_BIT, 951 MTK_MUX_BIT, 952 MTK_INFRA_BIT, 953 MTK_SHARED_SGMII_BIT, 954 MTK_HWLRO_BIT, 955 MTK_SHARED_INT_BIT, 956 MTK_TRGMII_MT7621_CLK_BIT, 957 MTK_QDMA_BIT, 958 MTK_SOC_MT7628_BIT, 959 MTK_RSTCTRL_PPE1_BIT, 960 MTK_RSTCTRL_PPE2_BIT, 961 MTK_U3_COPHY_V2_BIT, 962 MTK_SRAM_BIT, 963 MTK_36BIT_DMA_BIT, 964 965 /* MUX BITS*/ 966 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 967 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 968 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 969 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 970 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 971 972 /* PATH BITS */ 973 MTK_ETH_PATH_GMAC1_RGMII_BIT, 974 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 975 MTK_ETH_PATH_GMAC1_SGMII_BIT, 976 MTK_ETH_PATH_GMAC2_RGMII_BIT, 977 MTK_ETH_PATH_GMAC2_SGMII_BIT, 978 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 979 MTK_ETH_PATH_GDM1_ESW_BIT, 980 }; 981 982 /* Supported hardware group on SoCs */ 983 #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) 984 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) 985 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) 986 #define MTK_ESW BIT_ULL(MTK_ESW_BIT) 987 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) 988 #define MTK_MUX BIT_ULL(MTK_MUX_BIT) 989 #define MTK_INFRA BIT_ULL(MTK_INFRA_BIT) 990 #define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT) 991 #define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT) 992 #define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) 993 #define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) 994 #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) 995 #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) 996 #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) 997 #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) 998 #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) 999 #define MTK_SRAM BIT_ULL(MTK_SRAM_BIT) 1000 #define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT) 1001 1002 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 1003 BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 1004 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 1005 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 1006 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 1007 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 1008 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 1009 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 1010 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 1011 BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 1012 1013 /* Supported path present on SoCs */ 1014 #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) 1015 #define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 1016 #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) 1017 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) 1018 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) 1019 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 1020 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) 1021 1022 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 1023 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 1024 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 1025 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 1026 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 1027 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 1028 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 1029 1030 /* MUXes present on SoCs */ 1031 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 1032 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 1033 1034 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 1035 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 1036 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 1037 1038 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 1039 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 1040 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 1041 1042 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 1043 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 1044 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 1045 MTK_SHARED_SGMII) 1046 1047 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 1048 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 1049 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 1050 1051 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 1052 1053 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 1054 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 1055 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 1056 1057 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 1058 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 1059 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 1060 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 1061 1062 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 1063 MTK_QDMA) 1064 1065 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 1066 1067 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 1068 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 1069 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 1070 MTK_MUX_U3_GMAC2_TO_QPHY | \ 1071 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 1072 1073 #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 1074 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1075 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ 1076 MTK_RSTCTRL_PPE1 | MTK_SRAM) 1077 1078 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 1079 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1080 MTK_RSTCTRL_PPE1 | MTK_SRAM) 1081 1082 #define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \ 1083 MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM) 1084 1085 struct mtk_tx_dma_desc_info { 1086 dma_addr_t addr; 1087 u32 size; 1088 u16 vlan_tci; 1089 u16 qid; 1090 u8 gso:1; 1091 u8 csum:1; 1092 u8 vlan:1; 1093 u8 first:1; 1094 u8 last:1; 1095 }; 1096 1097 struct mtk_reg_map { 1098 u32 tx_irq_mask; 1099 u32 tx_irq_status; 1100 struct { 1101 u32 rx_ptr; /* rx base pointer */ 1102 u32 rx_cnt_cfg; /* rx max count configuration */ 1103 u32 pcrx_ptr; /* rx cpu pointer */ 1104 u32 glo_cfg; /* global configuration */ 1105 u32 rst_idx; /* reset index */ 1106 u32 delay_irq; /* delay interrupt */ 1107 u32 irq_status; /* interrupt status */ 1108 u32 irq_mask; /* interrupt mask */ 1109 u32 adma_rx_dbg0; 1110 u32 int_grp; 1111 } pdma; 1112 struct { 1113 u32 qtx_cfg; /* tx queue configuration */ 1114 u32 qtx_sch; /* tx queue scheduler configuration */ 1115 u32 rx_ptr; /* rx base pointer */ 1116 u32 rx_cnt_cfg; /* rx max count configuration */ 1117 u32 qcrx_ptr; /* rx cpu pointer */ 1118 u32 glo_cfg; /* global configuration */ 1119 u32 rst_idx; /* reset index */ 1120 u32 delay_irq; /* delay interrupt */ 1121 u32 fc_th; /* flow control */ 1122 u32 int_grp; 1123 u32 hred; /* interrupt mask */ 1124 u32 ctx_ptr; /* tx acquire cpu pointer */ 1125 u32 dtx_ptr; /* tx acquire dma pointer */ 1126 u32 crx_ptr; /* tx release cpu pointer */ 1127 u32 drx_ptr; /* tx release dma pointer */ 1128 u32 fq_head; /* fq head pointer */ 1129 u32 fq_tail; /* fq tail pointer */ 1130 u32 fq_count; /* fq free page count */ 1131 u32 fq_blen; /* fq free page buffer length */ 1132 u32 tx_sch_rate; /* tx scheduler rate control registers */ 1133 } qdma; 1134 u32 gdm1_cnt; 1135 u32 gdma_to_ppe[3]; 1136 u32 ppe_base; 1137 u32 wdma_base[3]; 1138 u32 pse_iq_sta; 1139 u32 pse_oq_sta; 1140 }; 1141 1142 /* struct mtk_eth_data - This is the structure holding all differences 1143 * among various plaforms 1144 * @reg_map Soc register map. 1145 * @ana_rgc3: The offset for register ANA_RGC3 related to 1146 * sgmiisys syscon 1147 * @caps Flags shown the extra capability for the SoC 1148 * @hw_features Flags shown HW features 1149 * @required_clks Flags shown the bitmap for required clocks on 1150 * the target SoC 1151 * @required_pctl A bool value to show whether the SoC requires 1152 * the extra setup for those pins used by GMAC. 1153 * @hash_offset Flow table hash offset. 1154 * @version SoC version. 1155 * @foe_entry_size Foe table entry size. 1156 * @has_accounting Bool indicating support for accounting of 1157 * offloaded flows. 1158 * @desc_size Tx/Rx DMA descriptor size. 1159 * @irq_done_mask Rx irq done register mask. 1160 * @dma_l4_valid Rx DMA valid register mask. 1161 * @dma_max_len Max DMA tx/rx buffer length. 1162 * @dma_len_offset Tx/Rx DMA length field offset. 1163 */ 1164 struct mtk_soc_data { 1165 const struct mtk_reg_map *reg_map; 1166 u32 ana_rgc3; 1167 u64 caps; 1168 u64 required_clks; 1169 bool required_pctl; 1170 u8 offload_version; 1171 u8 hash_offset; 1172 u8 version; 1173 u8 ppe_num; 1174 u16 foe_entry_size; 1175 netdev_features_t hw_features; 1176 bool has_accounting; 1177 bool disable_pll_modes; 1178 struct { 1179 u32 desc_size; 1180 u32 dma_max_len; 1181 u32 dma_len_offset; 1182 u32 dma_size; 1183 u32 fq_dma_size; 1184 } tx; 1185 struct { 1186 u32 desc_size; 1187 u32 irq_done_mask; 1188 u32 dma_l4_valid; 1189 u32 dma_max_len; 1190 u32 dma_len_offset; 1191 u32 dma_size; 1192 } rx; 1193 }; 1194 1195 #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) 1196 1197 /* currently no SoC has more than 3 macs */ 1198 #define MTK_MAX_DEVS 3 1199 1200 /* struct mtk_eth - This is the main datasructure for holding the state 1201 * of the driver 1202 * @dev: The device pointer 1203 * @dev: The device pointer used for dma mapping/alloc 1204 * @base: The mapped register i/o base 1205 * @page_lock: Make sure that register operations are atomic 1206 * @tx_irq__lock: Make sure that IRQ register operations are atomic 1207 * @rx_irq__lock: Make sure that IRQ register operations are atomic 1208 * @dim_lock: Make sure that Net DIM operations are atomic 1209 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1210 * dummy for NAPI to work 1211 * @netdev: The netdev instances 1212 * @mac: Each netdev is linked to a physical MAC 1213 * @irq: The IRQ that we are using 1214 * @msg_enable: Ethtool msg level 1215 * @ethsys: The register map pointing at the range used to setup 1216 * MII modes 1217 * @infra: The register map pointing at the range used to setup 1218 * SGMII and GePHY path 1219 * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances 1220 * @pctl: The register map pointing at the range used to setup 1221 * GMAC port drive/slew values 1222 * @dma_refcnt: track how many netdevs are using the DMA engine 1223 * @tx_ring: Pointer to the memory holding info about the TX ring 1224 * @rx_ring: Pointer to the memory holding info about the RX ring 1225 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 1226 * @tx_napi: The TX NAPI struct 1227 * @rx_napi: The RX NAPI struct 1228 * @rx_events: Net DIM RX event counter 1229 * @rx_packets: Net DIM RX packet counter 1230 * @rx_bytes: Net DIM RX byte counter 1231 * @rx_dim: Net DIM RX context 1232 * @tx_events: Net DIM TX event counter 1233 * @tx_packets: Net DIM TX packet counter 1234 * @tx_bytes: Net DIM TX byte counter 1235 * @tx_dim: Net DIM TX context 1236 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1237 * @phy_scratch_ring: physical address of scratch_ring 1238 * @scratch_head: The scratch memory that scratch_ring points to. 1239 * @clks: clock array for all clocks required 1240 * @mii_bus: If there is a bus we need to create an instance for it 1241 * @pending_work: The workqueue used to reset the dma ring 1242 * @state: Initialization and runtime state of the device 1243 * @soc: Holding specific data among vaious SoCs 1244 */ 1245 1246 struct mtk_eth { 1247 struct device *dev; 1248 struct device *dma_dev; 1249 void __iomem *base; 1250 void *sram_base; 1251 spinlock_t page_lock; 1252 spinlock_t tx_irq_lock; 1253 spinlock_t rx_irq_lock; 1254 struct net_device *dummy_dev; 1255 struct net_device *netdev[MTK_MAX_DEVS]; 1256 struct mtk_mac *mac[MTK_MAX_DEVS]; 1257 int irq[3]; 1258 u32 msg_enable; 1259 unsigned long sysclk; 1260 struct regmap *ethsys; 1261 struct regmap *infra; 1262 struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; 1263 struct regmap *pctl; 1264 bool hwlro; 1265 refcount_t dma_refcnt; 1266 struct mtk_tx_ring tx_ring; 1267 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 1268 struct mtk_rx_ring rx_ring_qdma; 1269 struct napi_struct tx_napi; 1270 struct napi_struct rx_napi; 1271 void *scratch_ring; 1272 dma_addr_t phy_scratch_ring; 1273 void *scratch_head[MTK_FQ_DMA_HEAD]; 1274 struct clk *clks[MTK_CLK_MAX]; 1275 1276 struct mii_bus *mii_bus; 1277 struct work_struct pending_work; 1278 unsigned long state; 1279 1280 const struct mtk_soc_data *soc; 1281 1282 spinlock_t dim_lock; 1283 1284 u32 rx_events; 1285 u32 rx_packets; 1286 u32 rx_bytes; 1287 struct dim rx_dim; 1288 1289 u32 tx_events; 1290 u32 tx_packets; 1291 u32 tx_bytes; 1292 struct dim tx_dim; 1293 1294 int ip_align; 1295 1296 struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS]; 1297 1298 struct mtk_ppe *ppe[3]; 1299 struct rhashtable flow_table; 1300 1301 struct bpf_prog __rcu *prog; 1302 1303 struct { 1304 struct delayed_work monitor_work; 1305 u32 wdidx; 1306 u8 wdma_hang_count; 1307 u8 qdma_hang_count; 1308 u8 adma_hang_count; 1309 } reset; 1310 }; 1311 1312 /* struct mtk_mac - the structure that holds the info about the MACs of the 1313 * SoC 1314 * @id: The number of the MAC 1315 * @interface: Interface mode kept for detecting change in hw settings 1316 * @of_node: Our devicetree node 1317 * @hw: Backpointer to our main datastruture 1318 * @hw_stats: Packet statistics counter 1319 */ 1320 struct mtk_mac { 1321 int id; 1322 phy_interface_t interface; 1323 u8 ppe_idx; 1324 int speed; 1325 struct device_node *of_node; 1326 struct phylink *phylink; 1327 struct phylink_config phylink_config; 1328 struct mtk_eth *hw; 1329 struct mtk_hw_stats *hw_stats; 1330 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1331 int hwlro_ip_cnt; 1332 unsigned int syscfg0; 1333 struct notifier_block device_notifier; 1334 }; 1335 1336 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1337 extern const struct of_device_id of_mtk_match[]; 1338 1339 static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) 1340 { 1341 return eth->soc->version == 1; 1342 } 1343 1344 static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) 1345 { 1346 return eth->soc->version > 1; 1347 } 1348 1349 static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) 1350 { 1351 return eth->soc->version > 2; 1352 } 1353 1354 static inline struct mtk_foe_entry * 1355 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 1356 { 1357 const struct mtk_soc_data *soc = ppe->eth->soc; 1358 1359 return ppe->foe_table + hash * soc->foe_entry_size; 1360 } 1361 1362 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 1363 { 1364 if (mtk_is_netsys_v2_or_greater(eth)) 1365 return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 1366 1367 return MTK_FOE_IB1_BIND_TIMESTAMP; 1368 } 1369 1370 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 1371 { 1372 if (mtk_is_netsys_v2_or_greater(eth)) 1373 return MTK_FOE_IB1_BIND_PPPOE_V2; 1374 1375 return MTK_FOE_IB1_BIND_PPPOE; 1376 } 1377 1378 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 1379 { 1380 if (mtk_is_netsys_v2_or_greater(eth)) 1381 return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 1382 1383 return MTK_FOE_IB1_BIND_VLAN_TAG; 1384 } 1385 1386 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 1387 { 1388 if (mtk_is_netsys_v2_or_greater(eth)) 1389 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 1390 1391 return MTK_FOE_IB1_BIND_VLAN_LAYER; 1392 } 1393 1394 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1395 { 1396 if (mtk_is_netsys_v2_or_greater(eth)) 1397 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1398 1399 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1400 } 1401 1402 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1403 { 1404 if (mtk_is_netsys_v2_or_greater(eth)) 1405 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1406 1407 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1408 } 1409 1410 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 1411 { 1412 if (mtk_is_netsys_v2_or_greater(eth)) 1413 return MTK_FOE_IB1_PACKET_TYPE_V2; 1414 1415 return MTK_FOE_IB1_PACKET_TYPE; 1416 } 1417 1418 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 1419 { 1420 if (mtk_is_netsys_v2_or_greater(eth)) 1421 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 1422 1423 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 1424 } 1425 1426 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 1427 { 1428 if (mtk_is_netsys_v2_or_greater(eth)) 1429 return MTK_FOE_IB2_MULTICAST_V2; 1430 1431 return MTK_FOE_IB2_MULTICAST; 1432 } 1433 1434 /* read the hardware status register */ 1435 void mtk_stats_update_mac(struct mtk_mac *mac); 1436 1437 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1438 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1439 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); 1440 1441 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1442 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1443 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1444 1445 int mtk_eth_offload_init(struct mtk_eth *eth, u8 id); 1446 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1447 void *type_data); 1448 int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls, 1449 int ppe_index); 1450 void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); 1451 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1452 1453 1454 #endif /* MTK_ETH_H */ 1455