1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include "mtk_ppe.h" 21 22 #define MTK_QDMA_PAGE_SIZE 2048 23 #define MTK_MAX_RX_LENGTH 1536 24 #define MTK_MAX_RX_LENGTH_2K 2048 25 #define MTK_TX_DMA_BUF_LEN 0x3fff 26 #define MTK_DMA_SIZE 512 27 #define MTK_MAC_COUNT 2 28 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 29 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 30 #define MTK_DMA_DUMMY_DESC 0xffffffff 31 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 32 NETIF_MSG_PROBE | \ 33 NETIF_MSG_LINK | \ 34 NETIF_MSG_TIMER | \ 35 NETIF_MSG_IFDOWN | \ 36 NETIF_MSG_IFUP | \ 37 NETIF_MSG_RX_ERR | \ 38 NETIF_MSG_TX_ERR) 39 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 40 NETIF_F_RXCSUM | \ 41 NETIF_F_HW_VLAN_CTAG_TX | \ 42 NETIF_F_HW_VLAN_CTAG_RX | \ 43 NETIF_F_SG | NETIF_F_TSO | \ 44 NETIF_F_TSO6 | \ 45 NETIF_F_IPV6_CSUM |\ 46 NETIF_F_HW_TC) 47 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 48 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 49 50 #define MTK_MAX_RX_RING_NUM 4 51 #define MTK_HW_LRO_DMA_SIZE 8 52 53 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 54 #define MTK_MAX_LRO_IP_CNT 2 55 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 56 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 57 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 58 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 59 #define MTK_HW_LRO_MAX_AGG_CNT 64 60 #define MTK_HW_LRO_BW_THRE 3000 61 #define MTK_HW_LRO_REPLACE_DELTA 1000 62 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 63 64 /* Frame Engine Global Reset Register */ 65 #define MTK_RST_GL 0x04 66 #define RST_GL_PSE BIT(0) 67 68 /* Frame Engine Interrupt Status Register */ 69 #define MTK_INT_STATUS2 0x08 70 #define MTK_GDM1_AF BIT(28) 71 #define MTK_GDM2_AF BIT(29) 72 73 /* PDMA HW LRO Alter Flow Timer Register */ 74 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 75 76 /* Frame Engine Interrupt Grouping Register */ 77 #define MTK_FE_INT_GRP 0x20 78 79 /* CDMP Ingress Control Register */ 80 #define MTK_CDMQ_IG_CTRL 0x1400 81 #define MTK_CDMQ_STAG_EN BIT(0) 82 83 /* CDMP Exgress Control Register */ 84 #define MTK_CDMP_EG_CTRL 0x404 85 86 /* GDM Exgress Control Register */ 87 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 88 #define MTK_GDMA_SPECIAL_TAG BIT(24) 89 #define MTK_GDMA_ICS_EN BIT(22) 90 #define MTK_GDMA_TCS_EN BIT(21) 91 #define MTK_GDMA_UCS_EN BIT(20) 92 #define MTK_GDMA_TO_PDMA 0x0 93 #define MTK_GDMA_TO_PPE 0x4444 94 #define MTK_GDMA_DROP_ALL 0x7777 95 96 /* Unicast Filter MAC Address Register - Low */ 97 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 98 99 /* Unicast Filter MAC Address Register - High */ 100 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 101 102 /* PDMA RX Base Pointer Register */ 103 #define MTK_PRX_BASE_PTR0 0x900 104 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 105 106 /* PDMA RX Maximum Count Register */ 107 #define MTK_PRX_MAX_CNT0 0x904 108 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 109 110 /* PDMA RX CPU Pointer Register */ 111 #define MTK_PRX_CRX_IDX0 0x908 112 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 113 114 /* PDMA HW LRO Control Registers */ 115 #define MTK_PDMA_LRO_CTRL_DW0 0x980 116 #define MTK_LRO_EN BIT(0) 117 #define MTK_L3_CKS_UPD_EN BIT(7) 118 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 119 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 120 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 121 122 #define MTK_PDMA_LRO_CTRL_DW1 0x984 123 #define MTK_PDMA_LRO_CTRL_DW2 0x988 124 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 125 #define MTK_ADMA_MODE BIT(15) 126 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 127 128 /* PDMA Global Configuration Register */ 129 #define MTK_PDMA_GLO_CFG 0xa04 130 #define MTK_MULTI_EN BIT(10) 131 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 132 133 /* PDMA Reset Index Register */ 134 #define MTK_PDMA_RST_IDX 0xa08 135 #define MTK_PST_DRX_IDX0 BIT(16) 136 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 137 138 /* PDMA Delay Interrupt Register */ 139 #define MTK_PDMA_DELAY_INT 0xa0c 140 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 141 #define MTK_PDMA_DELAY_RX_EN BIT(15) 142 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 143 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 144 145 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 146 #define MTK_PDMA_DELAY_TX_EN BIT(31) 147 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 148 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 149 150 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 151 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 152 153 /* PDMA Interrupt Status Register */ 154 #define MTK_PDMA_INT_STATUS 0xa20 155 156 /* PDMA Interrupt Mask Register */ 157 #define MTK_PDMA_INT_MASK 0xa28 158 159 /* PDMA HW LRO Alter Flow Delta Register */ 160 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 161 162 /* PDMA Interrupt grouping registers */ 163 #define MTK_PDMA_INT_GRP1 0xa50 164 #define MTK_PDMA_INT_GRP2 0xa54 165 166 /* PDMA HW LRO IP Setting Registers */ 167 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 168 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 169 #define MTK_RING_MYIP_VLD BIT(9) 170 171 /* PDMA HW LRO Ring Control Registers */ 172 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 173 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 174 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 175 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 176 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 177 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 178 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 179 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 180 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 181 #define MTK_RING_VLD BIT(8) 182 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 183 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 184 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 185 186 /* QDMA TX Queue Configuration Registers */ 187 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 188 #define QDMA_RES_THRES 4 189 190 /* QDMA TX Queue Scheduler Registers */ 191 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 192 193 /* QDMA RX Base Pointer Register */ 194 #define MTK_QRX_BASE_PTR0 0x1900 195 196 /* QDMA RX Maximum Count Register */ 197 #define MTK_QRX_MAX_CNT0 0x1904 198 199 /* QDMA RX CPU Pointer Register */ 200 #define MTK_QRX_CRX_IDX0 0x1908 201 202 /* QDMA RX DMA Pointer Register */ 203 #define MTK_QRX_DRX_IDX0 0x190C 204 205 /* QDMA Global Configuration Register */ 206 #define MTK_QDMA_GLO_CFG 0x1A04 207 #define MTK_RX_2B_OFFSET BIT(31) 208 #define MTK_RX_BT_32DWORDS (3 << 11) 209 #define MTK_NDP_CO_PRO BIT(10) 210 #define MTK_TX_WB_DDONE BIT(6) 211 #define MTK_TX_BT_32DWORDS (3 << 4) 212 #define MTK_RX_DMA_BUSY BIT(3) 213 #define MTK_TX_DMA_BUSY BIT(1) 214 #define MTK_RX_DMA_EN BIT(2) 215 #define MTK_TX_DMA_EN BIT(0) 216 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 217 218 /* QDMA Reset Index Register */ 219 #define MTK_QDMA_RST_IDX 0x1A08 220 221 /* QDMA Delay Interrupt Register */ 222 #define MTK_QDMA_DELAY_INT 0x1A0C 223 224 /* QDMA Flow Control Register */ 225 #define MTK_QDMA_FC_THRES 0x1A10 226 #define FC_THRES_DROP_MODE BIT(20) 227 #define FC_THRES_DROP_EN (7 << 16) 228 #define FC_THRES_MIN 0x4444 229 230 /* QDMA Interrupt Status Register */ 231 #define MTK_QDMA_INT_STATUS 0x1A18 232 #define MTK_RX_DONE_DLY BIT(30) 233 #define MTK_TX_DONE_DLY BIT(28) 234 #define MTK_RX_DONE_INT3 BIT(19) 235 #define MTK_RX_DONE_INT2 BIT(18) 236 #define MTK_RX_DONE_INT1 BIT(17) 237 #define MTK_RX_DONE_INT0 BIT(16) 238 #define MTK_TX_DONE_INT3 BIT(3) 239 #define MTK_TX_DONE_INT2 BIT(2) 240 #define MTK_TX_DONE_INT1 BIT(1) 241 #define MTK_TX_DONE_INT0 BIT(0) 242 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 243 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 244 245 /* QDMA Interrupt grouping registers */ 246 #define MTK_QDMA_INT_GRP1 0x1a20 247 #define MTK_QDMA_INT_GRP2 0x1a24 248 #define MTK_RLS_DONE_INT BIT(0) 249 250 /* QDMA Interrupt Status Register */ 251 #define MTK_QDMA_INT_MASK 0x1A1C 252 253 /* QDMA Interrupt Mask Register */ 254 #define MTK_QDMA_HRED2 0x1A44 255 256 /* QDMA TX Forward CPU Pointer Register */ 257 #define MTK_QTX_CTX_PTR 0x1B00 258 259 /* QDMA TX Forward DMA Pointer Register */ 260 #define MTK_QTX_DTX_PTR 0x1B04 261 262 /* QDMA TX Release CPU Pointer Register */ 263 #define MTK_QTX_CRX_PTR 0x1B10 264 265 /* QDMA TX Release DMA Pointer Register */ 266 #define MTK_QTX_DRX_PTR 0x1B14 267 268 /* QDMA FQ Head Pointer Register */ 269 #define MTK_QDMA_FQ_HEAD 0x1B20 270 271 /* QDMA FQ Head Pointer Register */ 272 #define MTK_QDMA_FQ_TAIL 0x1B24 273 274 /* QDMA FQ Free Page Counter Register */ 275 #define MTK_QDMA_FQ_CNT 0x1B28 276 277 /* QDMA FQ Free Page Buffer Length Register */ 278 #define MTK_QDMA_FQ_BLEN 0x1B2C 279 280 /* GMA1 counter / statics register */ 281 #define MTK_GDM1_RX_GBCNT_L 0x2400 282 #define MTK_GDM1_RX_GBCNT_H 0x2404 283 #define MTK_GDM1_RX_GPCNT 0x2408 284 #define MTK_GDM1_RX_OERCNT 0x2410 285 #define MTK_GDM1_RX_FERCNT 0x2414 286 #define MTK_GDM1_RX_SERCNT 0x2418 287 #define MTK_GDM1_RX_LENCNT 0x241c 288 #define MTK_GDM1_RX_CERCNT 0x2420 289 #define MTK_GDM1_RX_FCCNT 0x2424 290 #define MTK_GDM1_TX_SKIPCNT 0x2428 291 #define MTK_GDM1_TX_COLCNT 0x242c 292 #define MTK_GDM1_TX_GBCNT_L 0x2430 293 #define MTK_GDM1_TX_GBCNT_H 0x2434 294 #define MTK_GDM1_TX_GPCNT 0x2438 295 #define MTK_STAT_OFFSET 0x40 296 297 #define MTK_WDMA0_BASE 0x2800 298 #define MTK_WDMA1_BASE 0x2c00 299 300 /* QDMA descriptor txd4 */ 301 #define TX_DMA_CHKSUM (0x7 << 29) 302 #define TX_DMA_TSO BIT(28) 303 #define TX_DMA_FPORT_SHIFT 25 304 #define TX_DMA_FPORT_MASK 0x7 305 #define TX_DMA_INS_VLAN BIT(16) 306 307 /* QDMA descriptor txd3 */ 308 #define TX_DMA_OWNER_CPU BIT(31) 309 #define TX_DMA_LS0 BIT(30) 310 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 311 #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) 312 #define TX_DMA_SWC BIT(14) 313 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 314 315 /* PDMA on MT7628 */ 316 #define TX_DMA_DONE BIT(31) 317 #define TX_DMA_LS1 BIT(14) 318 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 319 320 /* QDMA descriptor rxd2 */ 321 #define RX_DMA_DONE BIT(31) 322 #define RX_DMA_LSO BIT(30) 323 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 324 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 325 #define RX_DMA_VTAG BIT(15) 326 327 /* QDMA descriptor rxd3 */ 328 #define RX_DMA_VID(_x) ((_x) & 0xfff) 329 330 /* QDMA descriptor rxd4 */ 331 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 332 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 333 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 334 #define MTK_RXD4_ALG GENMASK(31, 22) 335 336 /* QDMA descriptor rxd4 */ 337 #define RX_DMA_L4_VALID BIT(24) 338 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 339 #define RX_DMA_FPORT_SHIFT 19 340 #define RX_DMA_FPORT_MASK 0x7 341 #define RX_DMA_SPECIAL_TAG BIT(22) 342 343 /* PHY Indirect Access Control registers */ 344 #define MTK_PHY_IAC 0x10004 345 #define PHY_IAC_ACCESS BIT(31) 346 #define PHY_IAC_REG_MASK GENMASK(29, 25) 347 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 348 #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 349 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 350 #define PHY_IAC_CMD_MASK GENMASK(19, 18) 351 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 352 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 353 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 354 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 355 #define PHY_IAC_START_MASK GENMASK(17, 16) 356 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 357 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 358 #define PHY_IAC_DATA_MASK GENMASK(15, 0) 359 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 360 #define PHY_IAC_TIMEOUT HZ 361 362 #define MTK_MAC_MISC 0x1000c 363 #define MTK_MUX_TO_ESW BIT(0) 364 365 /* Mac control registers */ 366 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 367 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 368 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 369 #define MAC_MCR_MAX_RX_1518 0x0 370 #define MAC_MCR_MAX_RX_1536 0x1 371 #define MAC_MCR_MAX_RX_1552 0x2 372 #define MAC_MCR_MAX_RX_2048 0x3 373 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 374 #define MAC_MCR_FORCE_MODE BIT(15) 375 #define MAC_MCR_TX_EN BIT(14) 376 #define MAC_MCR_RX_EN BIT(13) 377 #define MAC_MCR_BACKOFF_EN BIT(9) 378 #define MAC_MCR_BACKPR_EN BIT(8) 379 #define MAC_MCR_FORCE_RX_FC BIT(5) 380 #define MAC_MCR_FORCE_TX_FC BIT(4) 381 #define MAC_MCR_SPEED_1000 BIT(3) 382 #define MAC_MCR_SPEED_100 BIT(2) 383 #define MAC_MCR_FORCE_DPX BIT(1) 384 #define MAC_MCR_FORCE_LINK BIT(0) 385 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 386 387 /* Mac status registers */ 388 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 389 #define MAC_MSR_EEE1G BIT(7) 390 #define MAC_MSR_EEE100M BIT(6) 391 #define MAC_MSR_RX_FC BIT(5) 392 #define MAC_MSR_TX_FC BIT(4) 393 #define MAC_MSR_SPEED_1000 BIT(3) 394 #define MAC_MSR_SPEED_100 BIT(2) 395 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 396 #define MAC_MSR_DPX BIT(1) 397 #define MAC_MSR_LINK BIT(0) 398 399 /* TRGMII RXC control register */ 400 #define TRGMII_RCK_CTRL 0x10300 401 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 402 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 403 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 404 #define RXC_RST BIT(31) 405 #define RXC_DQSISEL BIT(30) 406 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 407 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 408 409 #define NUM_TRGMII_CTRL 5 410 411 /* TRGMII RXC control register */ 412 #define TRGMII_TCK_CTRL 0x10340 413 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 414 #define TXC_INV BIT(30) 415 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 416 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 417 418 /* TRGMII TX Drive Strength */ 419 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 420 #define TD_DM_DRVP(x) ((x) & 0xf) 421 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 422 423 /* TRGMII Interface mode register */ 424 #define INTF_MODE 0x10390 425 #define TRGMII_INTF_DIS BIT(0) 426 #define TRGMII_MODE BIT(1) 427 #define TRGMII_CENTRAL_ALIGNED BIT(2) 428 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 429 #define INTF_MODE_RGMII_10_100 0 430 431 /* GPIO port control registers for GMAC 2*/ 432 #define GPIO_OD33_CTRL8 0x4c0 433 #define GPIO_BIAS_CTRL 0xed0 434 #define GPIO_DRV_SEL10 0xf00 435 436 /* ethernet subsystem chip id register */ 437 #define ETHSYS_CHIPID0_3 0x0 438 #define ETHSYS_CHIPID4_7 0x4 439 #define MT7623_ETH 7623 440 #define MT7622_ETH 7622 441 #define MT7621_ETH 7621 442 443 /* ethernet system control register */ 444 #define ETHSYS_SYSCFG 0x10 445 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 446 447 /* ethernet subsystem config register */ 448 #define ETHSYS_SYSCFG0 0x14 449 #define SYSCFG0_GE_MASK 0x3 450 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 451 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 452 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 453 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 454 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 455 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 456 457 458 /* ethernet subsystem clock register */ 459 #define ETHSYS_CLKCFG0 0x2c 460 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 461 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 462 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 463 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 464 465 /* ethernet reset control register */ 466 #define ETHSYS_RSTCTRL 0x34 467 #define RSTCTRL_FE BIT(6) 468 #define RSTCTRL_PPE BIT(31) 469 470 /* ethernet dma channel agent map */ 471 #define ETHSYS_DMA_AG_MAP 0x408 472 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 473 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 474 #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 475 476 /* SGMII subsystem config registers */ 477 /* Register to auto-negotiation restart */ 478 #define SGMSYS_PCS_CONTROL_1 0x0 479 #define SGMII_AN_RESTART BIT(9) 480 #define SGMII_ISOLATE BIT(10) 481 #define SGMII_AN_ENABLE BIT(12) 482 #define SGMII_LINK_STATYS BIT(18) 483 #define SGMII_AN_ABILITY BIT(19) 484 #define SGMII_AN_COMPLETE BIT(21) 485 #define SGMII_PCS_FAULT BIT(23) 486 #define SGMII_AN_EXPANSION_CLR BIT(30) 487 488 /* Register to programmable link timer, the unit in 2 * 8ns */ 489 #define SGMSYS_PCS_LINK_TIMER 0x18 490 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 491 492 /* Register to control remote fault */ 493 #define SGMSYS_SGMII_MODE 0x20 494 #define SGMII_IF_MODE_BIT0 BIT(0) 495 #define SGMII_SPEED_DUPLEX_AN BIT(1) 496 #define SGMII_SPEED_10 0x0 497 #define SGMII_SPEED_100 BIT(2) 498 #define SGMII_SPEED_1000 BIT(3) 499 #define SGMII_DUPLEX_FULL BIT(4) 500 #define SGMII_IF_MODE_BIT5 BIT(5) 501 #define SGMII_REMOTE_FAULT_DIS BIT(8) 502 #define SGMII_CODE_SYNC_SET_VAL BIT(9) 503 #define SGMII_CODE_SYNC_SET_EN BIT(10) 504 #define SGMII_SEND_AN_ERROR_EN BIT(11) 505 #define SGMII_IF_MODE_MASK GENMASK(5, 1) 506 507 /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 508 #define SGMSYS_ANA_RG_CS3 0x2028 509 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 510 #define RG_PHY_SPEED_1_25G 0x0 511 #define RG_PHY_SPEED_3_125G BIT(2) 512 513 /* Register to power up QPHY */ 514 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 515 #define SGMII_PHYA_PWD BIT(4) 516 517 /* Infrasys subsystem config registers */ 518 #define INFRA_MISC2 0x70c 519 #define CO_QPHY_SEL BIT(0) 520 #define GEPHY_MAC_SEL BIT(1) 521 522 /* MT7628/88 specific stuff */ 523 #define MT7628_PDMA_OFFSET 0x0800 524 #define MT7628_SDM_OFFSET 0x0c00 525 526 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 527 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 528 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 529 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 530 #define MT7628_PST_DTX_IDX0 BIT(0) 531 532 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 533 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 534 535 /* Counter / stat register */ 536 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 537 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 538 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 539 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 540 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 541 542 struct mtk_rx_dma { 543 unsigned int rxd1; 544 unsigned int rxd2; 545 unsigned int rxd3; 546 unsigned int rxd4; 547 } __packed __aligned(4); 548 549 struct mtk_tx_dma { 550 unsigned int txd1; 551 unsigned int txd2; 552 unsigned int txd3; 553 unsigned int txd4; 554 } __packed __aligned(4); 555 556 struct mtk_eth; 557 struct mtk_mac; 558 559 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 560 * @stats_lock: make sure that stats operations are atomic 561 * @reg_offset: the status register offset of the SoC 562 * @syncp: the refcount 563 * 564 * All of the supported SoCs have hardware counters for traffic statistics. 565 * Whenever the status IRQ triggers we can read the latest stats from these 566 * counters and store them in this struct. 567 */ 568 struct mtk_hw_stats { 569 u64 tx_bytes; 570 u64 tx_packets; 571 u64 tx_skip; 572 u64 tx_collisions; 573 u64 rx_bytes; 574 u64 rx_packets; 575 u64 rx_overflow; 576 u64 rx_fcs_errors; 577 u64 rx_short_errors; 578 u64 rx_long_errors; 579 u64 rx_checksum_errors; 580 u64 rx_flow_control_packets; 581 582 spinlock_t stats_lock; 583 u32 reg_offset; 584 struct u64_stats_sync syncp; 585 }; 586 587 enum mtk_tx_flags { 588 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 589 * track how memory was allocated so that it can be freed properly. 590 */ 591 MTK_TX_FLAGS_SINGLE0 = 0x01, 592 MTK_TX_FLAGS_PAGE0 = 0x02, 593 594 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 595 * SKB out instead of looking up through hardware TX descriptor. 596 */ 597 MTK_TX_FLAGS_FPORT0 = 0x04, 598 MTK_TX_FLAGS_FPORT1 = 0x08, 599 }; 600 601 /* This enum allows us to identify how the clock is defined on the array of the 602 * clock in the order 603 */ 604 enum mtk_clks_map { 605 MTK_CLK_ETHIF, 606 MTK_CLK_SGMIITOP, 607 MTK_CLK_ESW, 608 MTK_CLK_GP0, 609 MTK_CLK_GP1, 610 MTK_CLK_GP2, 611 MTK_CLK_FE, 612 MTK_CLK_TRGPLL, 613 MTK_CLK_SGMII_TX_250M, 614 MTK_CLK_SGMII_RX_250M, 615 MTK_CLK_SGMII_CDR_REF, 616 MTK_CLK_SGMII_CDR_FB, 617 MTK_CLK_SGMII2_TX_250M, 618 MTK_CLK_SGMII2_RX_250M, 619 MTK_CLK_SGMII2_CDR_REF, 620 MTK_CLK_SGMII2_CDR_FB, 621 MTK_CLK_SGMII_CK, 622 MTK_CLK_ETH2PLL, 623 MTK_CLK_MAX 624 }; 625 626 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 627 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 628 BIT(MTK_CLK_TRGPLL)) 629 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 630 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 631 BIT(MTK_CLK_GP2) | \ 632 BIT(MTK_CLK_SGMII_TX_250M) | \ 633 BIT(MTK_CLK_SGMII_RX_250M) | \ 634 BIT(MTK_CLK_SGMII_CDR_REF) | \ 635 BIT(MTK_CLK_SGMII_CDR_FB) | \ 636 BIT(MTK_CLK_SGMII_CK) | \ 637 BIT(MTK_CLK_ETH2PLL)) 638 #define MT7621_CLKS_BITMAP (0) 639 #define MT7628_CLKS_BITMAP (0) 640 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 641 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 642 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 643 BIT(MTK_CLK_SGMII_TX_250M) | \ 644 BIT(MTK_CLK_SGMII_RX_250M) | \ 645 BIT(MTK_CLK_SGMII_CDR_REF) | \ 646 BIT(MTK_CLK_SGMII_CDR_FB) | \ 647 BIT(MTK_CLK_SGMII2_TX_250M) | \ 648 BIT(MTK_CLK_SGMII2_RX_250M) | \ 649 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 650 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 651 BIT(MTK_CLK_SGMII_CK) | \ 652 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 653 654 enum mtk_dev_state { 655 MTK_HW_INIT, 656 MTK_RESETTING 657 }; 658 659 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 660 * by the TX descriptor s 661 * @skb: The SKB pointer of the packet being sent 662 * @dma_addr0: The base addr of the first segment 663 * @dma_len0: The length of the first segment 664 * @dma_addr1: The base addr of the second segment 665 * @dma_len1: The length of the second segment 666 */ 667 struct mtk_tx_buf { 668 struct sk_buff *skb; 669 u32 flags; 670 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 671 DEFINE_DMA_UNMAP_LEN(dma_len0); 672 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 673 DEFINE_DMA_UNMAP_LEN(dma_len1); 674 }; 675 676 /* struct mtk_tx_ring - This struct holds info describing a TX ring 677 * @dma: The descriptor ring 678 * @buf: The memory pointed at by the ring 679 * @phys: The physical addr of tx_buf 680 * @next_free: Pointer to the next free descriptor 681 * @last_free: Pointer to the last free descriptor 682 * @last_free_ptr: Hardware pointer value of the last free descriptor 683 * @thresh: The threshold of minimum amount of free descriptors 684 * @free_count: QDMA uses a linked list. Track how many free descriptors 685 * are present 686 */ 687 struct mtk_tx_ring { 688 struct mtk_tx_dma *dma; 689 struct mtk_tx_buf *buf; 690 dma_addr_t phys; 691 struct mtk_tx_dma *next_free; 692 struct mtk_tx_dma *last_free; 693 u32 last_free_ptr; 694 u16 thresh; 695 atomic_t free_count; 696 int dma_size; 697 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 698 dma_addr_t phys_pdma; 699 int cpu_idx; 700 }; 701 702 /* PDMA rx ring mode */ 703 enum mtk_rx_flags { 704 MTK_RX_FLAGS_NORMAL = 0, 705 MTK_RX_FLAGS_HWLRO, 706 MTK_RX_FLAGS_QDMA, 707 }; 708 709 /* struct mtk_rx_ring - This struct holds info describing a RX ring 710 * @dma: The descriptor ring 711 * @data: The memory pointed at by the ring 712 * @phys: The physical addr of rx_buf 713 * @frag_size: How big can each fragment be 714 * @buf_size: The size of each packet buffer 715 * @calc_idx: The current head of ring 716 */ 717 struct mtk_rx_ring { 718 struct mtk_rx_dma *dma; 719 u8 **data; 720 dma_addr_t phys; 721 u16 frag_size; 722 u16 buf_size; 723 u16 dma_size; 724 bool calc_idx_update; 725 u16 calc_idx; 726 u32 crx_idx_reg; 727 }; 728 729 enum mkt_eth_capabilities { 730 MTK_RGMII_BIT = 0, 731 MTK_TRGMII_BIT, 732 MTK_SGMII_BIT, 733 MTK_ESW_BIT, 734 MTK_GEPHY_BIT, 735 MTK_MUX_BIT, 736 MTK_INFRA_BIT, 737 MTK_SHARED_SGMII_BIT, 738 MTK_HWLRO_BIT, 739 MTK_SHARED_INT_BIT, 740 MTK_TRGMII_MT7621_CLK_BIT, 741 MTK_QDMA_BIT, 742 MTK_SOC_MT7628_BIT, 743 744 /* MUX BITS*/ 745 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 746 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 747 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 748 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 749 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 750 751 /* PATH BITS */ 752 MTK_ETH_PATH_GMAC1_RGMII_BIT, 753 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 754 MTK_ETH_PATH_GMAC1_SGMII_BIT, 755 MTK_ETH_PATH_GMAC2_RGMII_BIT, 756 MTK_ETH_PATH_GMAC2_SGMII_BIT, 757 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 758 MTK_ETH_PATH_GDM1_ESW_BIT, 759 }; 760 761 /* Supported hardware group on SoCs */ 762 #define MTK_RGMII BIT(MTK_RGMII_BIT) 763 #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 764 #define MTK_SGMII BIT(MTK_SGMII_BIT) 765 #define MTK_ESW BIT(MTK_ESW_BIT) 766 #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 767 #define MTK_MUX BIT(MTK_MUX_BIT) 768 #define MTK_INFRA BIT(MTK_INFRA_BIT) 769 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 770 #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 771 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 772 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 773 #define MTK_QDMA BIT(MTK_QDMA_BIT) 774 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 775 776 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 777 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 778 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 779 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 780 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 781 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 782 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 783 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 784 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 785 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 786 787 /* Supported path present on SoCs */ 788 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 789 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 790 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 791 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 792 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 793 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 794 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 795 796 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 797 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 798 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 799 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 800 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 801 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 802 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 803 804 /* MUXes present on SoCs */ 805 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 806 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 807 808 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 809 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 810 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 811 812 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 813 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 814 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 815 816 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 817 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 818 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 819 MTK_SHARED_SGMII) 820 821 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 822 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 823 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 824 825 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 826 827 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 828 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 829 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 830 831 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 832 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 833 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 834 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 835 836 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 837 MTK_QDMA) 838 839 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 840 841 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 842 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 843 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 844 MTK_MUX_U3_GMAC2_TO_QPHY | \ 845 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 846 847 /* struct mtk_eth_data - This is the structure holding all differences 848 * among various plaforms 849 * @ana_rgc3: The offset for register ANA_RGC3 related to 850 * sgmiisys syscon 851 * @caps Flags shown the extra capability for the SoC 852 * @hw_features Flags shown HW features 853 * @required_clks Flags shown the bitmap for required clocks on 854 * the target SoC 855 * @required_pctl A bool value to show whether the SoC requires 856 * the extra setup for those pins used by GMAC. 857 */ 858 struct mtk_soc_data { 859 u32 ana_rgc3; 860 u32 caps; 861 u32 required_clks; 862 bool required_pctl; 863 u8 offload_version; 864 netdev_features_t hw_features; 865 }; 866 867 /* currently no SoC has more than 2 macs */ 868 #define MTK_MAX_DEVS 2 869 870 #define MTK_SGMII_PHYSPEED_AN BIT(31) 871 #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) 872 #define MTK_SGMII_PHYSPEED_1000 BIT(0) 873 #define MTK_SGMII_PHYSPEED_2500 BIT(1) 874 #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) 875 876 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 877 * characteristics 878 * @regmap: The register map pointing at the range used to setup 879 * SGMII modes 880 * @flags: The enum refers to which mode the sgmii wants to run on 881 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 882 */ 883 884 struct mtk_sgmii { 885 struct regmap *regmap[MTK_MAX_DEVS]; 886 u32 flags[MTK_MAX_DEVS]; 887 u32 ana_rgc3; 888 }; 889 890 /* struct mtk_eth - This is the main datasructure for holding the state 891 * of the driver 892 * @dev: The device pointer 893 * @dev: The device pointer used for dma mapping/alloc 894 * @base: The mapped register i/o base 895 * @page_lock: Make sure that register operations are atomic 896 * @tx_irq__lock: Make sure that IRQ register operations are atomic 897 * @rx_irq__lock: Make sure that IRQ register operations are atomic 898 * @dim_lock: Make sure that Net DIM operations are atomic 899 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 900 * dummy for NAPI to work 901 * @netdev: The netdev instances 902 * @mac: Each netdev is linked to a physical MAC 903 * @irq: The IRQ that we are using 904 * @msg_enable: Ethtool msg level 905 * @ethsys: The register map pointing at the range used to setup 906 * MII modes 907 * @infra: The register map pointing at the range used to setup 908 * SGMII and GePHY path 909 * @pctl: The register map pointing at the range used to setup 910 * GMAC port drive/slew values 911 * @dma_refcnt: track how many netdevs are using the DMA engine 912 * @tx_ring: Pointer to the memory holding info about the TX ring 913 * @rx_ring: Pointer to the memory holding info about the RX ring 914 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 915 * @tx_napi: The TX NAPI struct 916 * @rx_napi: The RX NAPI struct 917 * @rx_events: Net DIM RX event counter 918 * @rx_packets: Net DIM RX packet counter 919 * @rx_bytes: Net DIM RX byte counter 920 * @rx_dim: Net DIM RX context 921 * @tx_events: Net DIM TX event counter 922 * @tx_packets: Net DIM TX packet counter 923 * @tx_bytes: Net DIM TX byte counter 924 * @tx_dim: Net DIM TX context 925 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 926 * @phy_scratch_ring: physical address of scratch_ring 927 * @scratch_head: The scratch memory that scratch_ring points to. 928 * @clks: clock array for all clocks required 929 * @mii_bus: If there is a bus we need to create an instance for it 930 * @pending_work: The workqueue used to reset the dma ring 931 * @state: Initialization and runtime state of the device 932 * @soc: Holding specific data among vaious SoCs 933 */ 934 935 struct mtk_eth { 936 struct device *dev; 937 struct device *dma_dev; 938 void __iomem *base; 939 spinlock_t page_lock; 940 spinlock_t tx_irq_lock; 941 spinlock_t rx_irq_lock; 942 struct net_device dummy_dev; 943 struct net_device *netdev[MTK_MAX_DEVS]; 944 struct mtk_mac *mac[MTK_MAX_DEVS]; 945 int irq[3]; 946 u32 msg_enable; 947 unsigned long sysclk; 948 struct regmap *ethsys; 949 struct regmap *infra; 950 struct mtk_sgmii *sgmii; 951 struct regmap *pctl; 952 bool hwlro; 953 refcount_t dma_refcnt; 954 struct mtk_tx_ring tx_ring; 955 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 956 struct mtk_rx_ring rx_ring_qdma; 957 struct napi_struct tx_napi; 958 struct napi_struct rx_napi; 959 struct mtk_tx_dma *scratch_ring; 960 dma_addr_t phy_scratch_ring; 961 void *scratch_head; 962 struct clk *clks[MTK_CLK_MAX]; 963 964 struct mii_bus *mii_bus; 965 struct work_struct pending_work; 966 unsigned long state; 967 968 const struct mtk_soc_data *soc; 969 970 spinlock_t dim_lock; 971 972 u32 rx_events; 973 u32 rx_packets; 974 u32 rx_bytes; 975 struct dim rx_dim; 976 977 u32 tx_events; 978 u32 tx_packets; 979 u32 tx_bytes; 980 struct dim tx_dim; 981 982 u32 tx_int_mask_reg; 983 u32 tx_int_status_reg; 984 u32 rx_dma_l4_valid; 985 int ip_align; 986 987 struct mtk_ppe *ppe; 988 struct rhashtable flow_table; 989 }; 990 991 /* struct mtk_mac - the structure that holds the info about the MACs of the 992 * SoC 993 * @id: The number of the MAC 994 * @interface: Interface mode kept for detecting change in hw settings 995 * @of_node: Our devicetree node 996 * @hw: Backpointer to our main datastruture 997 * @hw_stats: Packet statistics counter 998 */ 999 struct mtk_mac { 1000 int id; 1001 phy_interface_t interface; 1002 unsigned int mode; 1003 int speed; 1004 struct device_node *of_node; 1005 struct phylink *phylink; 1006 struct phylink_config phylink_config; 1007 struct mtk_eth *hw; 1008 struct mtk_hw_stats *hw_stats; 1009 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1010 int hwlro_ip_cnt; 1011 }; 1012 1013 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1014 extern const struct of_device_id of_mtk_match[]; 1015 1016 /* read the hardware status register */ 1017 void mtk_stats_update_mac(struct mtk_mac *mac); 1018 1019 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1020 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1021 1022 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 1023 u32 ana_rgc3); 1024 int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); 1025 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, 1026 const struct phylink_link_state *state); 1027 void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); 1028 1029 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1030 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1031 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1032 1033 int mtk_eth_offload_init(struct mtk_eth *eth); 1034 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1035 void *type_data); 1036 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1037 1038 1039 #endif /* MTK_ETH_H */ 1040