1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include "mtk_ppe.h" 21 22 #define MTK_QDMA_PAGE_SIZE 2048 23 #define MTK_MAX_RX_LENGTH 1536 24 #define MTK_MAX_RX_LENGTH_2K 2048 25 #define MTK_TX_DMA_BUF_LEN 0x3fff 26 #define MTK_DMA_SIZE 512 27 #define MTK_NAPI_WEIGHT 64 28 #define MTK_MAC_COUNT 2 29 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 30 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 31 #define MTK_DMA_DUMMY_DESC 0xffffffff 32 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 33 NETIF_MSG_PROBE | \ 34 NETIF_MSG_LINK | \ 35 NETIF_MSG_TIMER | \ 36 NETIF_MSG_IFDOWN | \ 37 NETIF_MSG_IFUP | \ 38 NETIF_MSG_RX_ERR | \ 39 NETIF_MSG_TX_ERR) 40 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 41 NETIF_F_RXCSUM | \ 42 NETIF_F_HW_VLAN_CTAG_TX | \ 43 NETIF_F_HW_VLAN_CTAG_RX | \ 44 NETIF_F_SG | NETIF_F_TSO | \ 45 NETIF_F_TSO6 | \ 46 NETIF_F_IPV6_CSUM |\ 47 NETIF_F_HW_TC) 48 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 49 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 50 51 #define MTK_MAX_RX_RING_NUM 4 52 #define MTK_HW_LRO_DMA_SIZE 8 53 54 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 55 #define MTK_MAX_LRO_IP_CNT 2 56 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 57 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 58 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 59 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 60 #define MTK_HW_LRO_MAX_AGG_CNT 64 61 #define MTK_HW_LRO_BW_THRE 3000 62 #define MTK_HW_LRO_REPLACE_DELTA 1000 63 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 64 65 /* Frame Engine Global Reset Register */ 66 #define MTK_RST_GL 0x04 67 #define RST_GL_PSE BIT(0) 68 69 /* Frame Engine Interrupt Status Register */ 70 #define MTK_INT_STATUS2 0x08 71 #define MTK_GDM1_AF BIT(28) 72 #define MTK_GDM2_AF BIT(29) 73 74 /* PDMA HW LRO Alter Flow Timer Register */ 75 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 76 77 /* Frame Engine Interrupt Grouping Register */ 78 #define MTK_FE_INT_GRP 0x20 79 80 /* CDMP Ingress Control Register */ 81 #define MTK_CDMQ_IG_CTRL 0x1400 82 #define MTK_CDMQ_STAG_EN BIT(0) 83 84 /* CDMP Exgress Control Register */ 85 #define MTK_CDMP_EG_CTRL 0x404 86 87 /* GDM Exgress Control Register */ 88 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 89 #define MTK_GDMA_SPECIAL_TAG BIT(24) 90 #define MTK_GDMA_ICS_EN BIT(22) 91 #define MTK_GDMA_TCS_EN BIT(21) 92 #define MTK_GDMA_UCS_EN BIT(20) 93 #define MTK_GDMA_TO_PDMA 0x0 94 #define MTK_GDMA_TO_PPE 0x4444 95 #define MTK_GDMA_DROP_ALL 0x7777 96 97 /* Unicast Filter MAC Address Register - Low */ 98 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 99 100 /* Unicast Filter MAC Address Register - High */ 101 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 102 103 /* PDMA RX Base Pointer Register */ 104 #define MTK_PRX_BASE_PTR0 0x900 105 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 106 107 /* PDMA RX Maximum Count Register */ 108 #define MTK_PRX_MAX_CNT0 0x904 109 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 110 111 /* PDMA RX CPU Pointer Register */ 112 #define MTK_PRX_CRX_IDX0 0x908 113 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 114 115 /* PDMA HW LRO Control Registers */ 116 #define MTK_PDMA_LRO_CTRL_DW0 0x980 117 #define MTK_LRO_EN BIT(0) 118 #define MTK_L3_CKS_UPD_EN BIT(7) 119 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 120 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 121 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 122 123 #define MTK_PDMA_LRO_CTRL_DW1 0x984 124 #define MTK_PDMA_LRO_CTRL_DW2 0x988 125 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 126 #define MTK_ADMA_MODE BIT(15) 127 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 128 129 /* PDMA Global Configuration Register */ 130 #define MTK_PDMA_GLO_CFG 0xa04 131 #define MTK_MULTI_EN BIT(10) 132 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 133 134 /* PDMA Reset Index Register */ 135 #define MTK_PDMA_RST_IDX 0xa08 136 #define MTK_PST_DRX_IDX0 BIT(16) 137 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 138 139 /* PDMA Delay Interrupt Register */ 140 #define MTK_PDMA_DELAY_INT 0xa0c 141 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 142 #define MTK_PDMA_DELAY_RX_EN BIT(15) 143 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 144 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 145 146 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 147 #define MTK_PDMA_DELAY_TX_EN BIT(31) 148 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 149 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 150 151 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 152 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 153 154 /* PDMA Interrupt Status Register */ 155 #define MTK_PDMA_INT_STATUS 0xa20 156 157 /* PDMA Interrupt Mask Register */ 158 #define MTK_PDMA_INT_MASK 0xa28 159 160 /* PDMA HW LRO Alter Flow Delta Register */ 161 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 162 163 /* PDMA Interrupt grouping registers */ 164 #define MTK_PDMA_INT_GRP1 0xa50 165 #define MTK_PDMA_INT_GRP2 0xa54 166 167 /* PDMA HW LRO IP Setting Registers */ 168 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 169 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 170 #define MTK_RING_MYIP_VLD BIT(9) 171 172 /* PDMA HW LRO Ring Control Registers */ 173 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 174 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 175 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 176 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 177 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 178 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 179 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 180 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 181 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 182 #define MTK_RING_VLD BIT(8) 183 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 184 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 185 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 186 187 /* QDMA TX Queue Configuration Registers */ 188 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 189 #define QDMA_RES_THRES 4 190 191 /* QDMA TX Queue Scheduler Registers */ 192 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 193 194 /* QDMA RX Base Pointer Register */ 195 #define MTK_QRX_BASE_PTR0 0x1900 196 197 /* QDMA RX Maximum Count Register */ 198 #define MTK_QRX_MAX_CNT0 0x1904 199 200 /* QDMA RX CPU Pointer Register */ 201 #define MTK_QRX_CRX_IDX0 0x1908 202 203 /* QDMA RX DMA Pointer Register */ 204 #define MTK_QRX_DRX_IDX0 0x190C 205 206 /* QDMA Global Configuration Register */ 207 #define MTK_QDMA_GLO_CFG 0x1A04 208 #define MTK_RX_2B_OFFSET BIT(31) 209 #define MTK_RX_BT_32DWORDS (3 << 11) 210 #define MTK_NDP_CO_PRO BIT(10) 211 #define MTK_TX_WB_DDONE BIT(6) 212 #define MTK_TX_BT_32DWORDS (3 << 4) 213 #define MTK_RX_DMA_BUSY BIT(3) 214 #define MTK_TX_DMA_BUSY BIT(1) 215 #define MTK_RX_DMA_EN BIT(2) 216 #define MTK_TX_DMA_EN BIT(0) 217 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 218 219 /* QDMA Reset Index Register */ 220 #define MTK_QDMA_RST_IDX 0x1A08 221 222 /* QDMA Delay Interrupt Register */ 223 #define MTK_QDMA_DELAY_INT 0x1A0C 224 225 /* QDMA Flow Control Register */ 226 #define MTK_QDMA_FC_THRES 0x1A10 227 #define FC_THRES_DROP_MODE BIT(20) 228 #define FC_THRES_DROP_EN (7 << 16) 229 #define FC_THRES_MIN 0x4444 230 231 /* QDMA Interrupt Status Register */ 232 #define MTK_QDMA_INT_STATUS 0x1A18 233 #define MTK_RX_DONE_DLY BIT(30) 234 #define MTK_TX_DONE_DLY BIT(28) 235 #define MTK_RX_DONE_INT3 BIT(19) 236 #define MTK_RX_DONE_INT2 BIT(18) 237 #define MTK_RX_DONE_INT1 BIT(17) 238 #define MTK_RX_DONE_INT0 BIT(16) 239 #define MTK_TX_DONE_INT3 BIT(3) 240 #define MTK_TX_DONE_INT2 BIT(2) 241 #define MTK_TX_DONE_INT1 BIT(1) 242 #define MTK_TX_DONE_INT0 BIT(0) 243 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 244 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 245 246 /* QDMA Interrupt grouping registers */ 247 #define MTK_QDMA_INT_GRP1 0x1a20 248 #define MTK_QDMA_INT_GRP2 0x1a24 249 #define MTK_RLS_DONE_INT BIT(0) 250 251 /* QDMA Interrupt Status Register */ 252 #define MTK_QDMA_INT_MASK 0x1A1C 253 254 /* QDMA Interrupt Mask Register */ 255 #define MTK_QDMA_HRED2 0x1A44 256 257 /* QDMA TX Forward CPU Pointer Register */ 258 #define MTK_QTX_CTX_PTR 0x1B00 259 260 /* QDMA TX Forward DMA Pointer Register */ 261 #define MTK_QTX_DTX_PTR 0x1B04 262 263 /* QDMA TX Release CPU Pointer Register */ 264 #define MTK_QTX_CRX_PTR 0x1B10 265 266 /* QDMA TX Release DMA Pointer Register */ 267 #define MTK_QTX_DRX_PTR 0x1B14 268 269 /* QDMA FQ Head Pointer Register */ 270 #define MTK_QDMA_FQ_HEAD 0x1B20 271 272 /* QDMA FQ Head Pointer Register */ 273 #define MTK_QDMA_FQ_TAIL 0x1B24 274 275 /* QDMA FQ Free Page Counter Register */ 276 #define MTK_QDMA_FQ_CNT 0x1B28 277 278 /* QDMA FQ Free Page Buffer Length Register */ 279 #define MTK_QDMA_FQ_BLEN 0x1B2C 280 281 /* GMA1 counter / statics register */ 282 #define MTK_GDM1_RX_GBCNT_L 0x2400 283 #define MTK_GDM1_RX_GBCNT_H 0x2404 284 #define MTK_GDM1_RX_GPCNT 0x2408 285 #define MTK_GDM1_RX_OERCNT 0x2410 286 #define MTK_GDM1_RX_FERCNT 0x2414 287 #define MTK_GDM1_RX_SERCNT 0x2418 288 #define MTK_GDM1_RX_LENCNT 0x241c 289 #define MTK_GDM1_RX_CERCNT 0x2420 290 #define MTK_GDM1_RX_FCCNT 0x2424 291 #define MTK_GDM1_TX_SKIPCNT 0x2428 292 #define MTK_GDM1_TX_COLCNT 0x242c 293 #define MTK_GDM1_TX_GBCNT_L 0x2430 294 #define MTK_GDM1_TX_GBCNT_H 0x2434 295 #define MTK_GDM1_TX_GPCNT 0x2438 296 #define MTK_STAT_OFFSET 0x40 297 298 /* QDMA descriptor txd4 */ 299 #define TX_DMA_CHKSUM (0x7 << 29) 300 #define TX_DMA_TSO BIT(28) 301 #define TX_DMA_FPORT_SHIFT 25 302 #define TX_DMA_FPORT_MASK 0x7 303 #define TX_DMA_INS_VLAN BIT(16) 304 305 /* QDMA descriptor txd3 */ 306 #define TX_DMA_OWNER_CPU BIT(31) 307 #define TX_DMA_LS0 BIT(30) 308 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 309 #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) 310 #define TX_DMA_SWC BIT(14) 311 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 312 313 /* PDMA on MT7628 */ 314 #define TX_DMA_DONE BIT(31) 315 #define TX_DMA_LS1 BIT(14) 316 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 317 318 /* QDMA descriptor rxd2 */ 319 #define RX_DMA_DONE BIT(31) 320 #define RX_DMA_LSO BIT(30) 321 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 322 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 323 #define RX_DMA_VTAG BIT(15) 324 325 /* QDMA descriptor rxd3 */ 326 #define RX_DMA_VID(_x) ((_x) & 0xfff) 327 328 /* QDMA descriptor rxd4 */ 329 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 330 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 331 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 332 #define MTK_RXD4_ALG GENMASK(31, 22) 333 334 /* QDMA descriptor rxd4 */ 335 #define RX_DMA_L4_VALID BIT(24) 336 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 337 #define RX_DMA_FPORT_SHIFT 19 338 #define RX_DMA_FPORT_MASK 0x7 339 #define RX_DMA_SPECIAL_TAG BIT(22) 340 341 /* PHY Indirect Access Control registers */ 342 #define MTK_PHY_IAC 0x10004 343 #define PHY_IAC_ACCESS BIT(31) 344 #define PHY_IAC_READ BIT(19) 345 #define PHY_IAC_WRITE BIT(18) 346 #define PHY_IAC_START BIT(16) 347 #define PHY_IAC_ADDR_SHIFT 20 348 #define PHY_IAC_REG_SHIFT 25 349 #define PHY_IAC_TIMEOUT HZ 350 351 #define MTK_MAC_MISC 0x1000c 352 #define MTK_MUX_TO_ESW BIT(0) 353 354 /* Mac control registers */ 355 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 356 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 357 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 358 #define MAC_MCR_MAX_RX_1518 0x0 359 #define MAC_MCR_MAX_RX_1536 0x1 360 #define MAC_MCR_MAX_RX_1552 0x2 361 #define MAC_MCR_MAX_RX_2048 0x3 362 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 363 #define MAC_MCR_FORCE_MODE BIT(15) 364 #define MAC_MCR_TX_EN BIT(14) 365 #define MAC_MCR_RX_EN BIT(13) 366 #define MAC_MCR_BACKOFF_EN BIT(9) 367 #define MAC_MCR_BACKPR_EN BIT(8) 368 #define MAC_MCR_FORCE_RX_FC BIT(5) 369 #define MAC_MCR_FORCE_TX_FC BIT(4) 370 #define MAC_MCR_SPEED_1000 BIT(3) 371 #define MAC_MCR_SPEED_100 BIT(2) 372 #define MAC_MCR_FORCE_DPX BIT(1) 373 #define MAC_MCR_FORCE_LINK BIT(0) 374 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 375 376 /* Mac status registers */ 377 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 378 #define MAC_MSR_EEE1G BIT(7) 379 #define MAC_MSR_EEE100M BIT(6) 380 #define MAC_MSR_RX_FC BIT(5) 381 #define MAC_MSR_TX_FC BIT(4) 382 #define MAC_MSR_SPEED_1000 BIT(3) 383 #define MAC_MSR_SPEED_100 BIT(2) 384 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 385 #define MAC_MSR_DPX BIT(1) 386 #define MAC_MSR_LINK BIT(0) 387 388 /* TRGMII RXC control register */ 389 #define TRGMII_RCK_CTRL 0x10300 390 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 391 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 392 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 393 #define RXC_RST BIT(31) 394 #define RXC_DQSISEL BIT(30) 395 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 396 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 397 398 #define NUM_TRGMII_CTRL 5 399 400 /* TRGMII RXC control register */ 401 #define TRGMII_TCK_CTRL 0x10340 402 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 403 #define TXC_INV BIT(30) 404 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 405 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 406 407 /* TRGMII TX Drive Strength */ 408 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 409 #define TD_DM_DRVP(x) ((x) & 0xf) 410 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 411 412 /* TRGMII Interface mode register */ 413 #define INTF_MODE 0x10390 414 #define TRGMII_INTF_DIS BIT(0) 415 #define TRGMII_MODE BIT(1) 416 #define TRGMII_CENTRAL_ALIGNED BIT(2) 417 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 418 #define INTF_MODE_RGMII_10_100 0 419 420 /* GPIO port control registers for GMAC 2*/ 421 #define GPIO_OD33_CTRL8 0x4c0 422 #define GPIO_BIAS_CTRL 0xed0 423 #define GPIO_DRV_SEL10 0xf00 424 425 /* ethernet subsystem chip id register */ 426 #define ETHSYS_CHIPID0_3 0x0 427 #define ETHSYS_CHIPID4_7 0x4 428 #define MT7623_ETH 7623 429 #define MT7622_ETH 7622 430 #define MT7621_ETH 7621 431 432 /* ethernet system control register */ 433 #define ETHSYS_SYSCFG 0x10 434 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 435 436 /* ethernet subsystem config register */ 437 #define ETHSYS_SYSCFG0 0x14 438 #define SYSCFG0_GE_MASK 0x3 439 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 440 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 441 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 442 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 443 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 444 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 445 446 447 /* ethernet subsystem clock register */ 448 #define ETHSYS_CLKCFG0 0x2c 449 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 450 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 451 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 452 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 453 454 /* ethernet reset control register */ 455 #define ETHSYS_RSTCTRL 0x34 456 #define RSTCTRL_FE BIT(6) 457 #define RSTCTRL_PPE BIT(31) 458 459 /* SGMII subsystem config registers */ 460 /* Register to auto-negotiation restart */ 461 #define SGMSYS_PCS_CONTROL_1 0x0 462 #define SGMII_AN_RESTART BIT(9) 463 #define SGMII_ISOLATE BIT(10) 464 #define SGMII_AN_ENABLE BIT(12) 465 #define SGMII_LINK_STATYS BIT(18) 466 #define SGMII_AN_ABILITY BIT(19) 467 #define SGMII_AN_COMPLETE BIT(21) 468 #define SGMII_PCS_FAULT BIT(23) 469 #define SGMII_AN_EXPANSION_CLR BIT(30) 470 471 /* Register to programmable link timer, the unit in 2 * 8ns */ 472 #define SGMSYS_PCS_LINK_TIMER 0x18 473 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 474 475 /* Register to control remote fault */ 476 #define SGMSYS_SGMII_MODE 0x20 477 #define SGMII_IF_MODE_BIT0 BIT(0) 478 #define SGMII_SPEED_DUPLEX_AN BIT(1) 479 #define SGMII_SPEED_10 0x0 480 #define SGMII_SPEED_100 BIT(2) 481 #define SGMII_SPEED_1000 BIT(3) 482 #define SGMII_DUPLEX_FULL BIT(4) 483 #define SGMII_IF_MODE_BIT5 BIT(5) 484 #define SGMII_REMOTE_FAULT_DIS BIT(8) 485 #define SGMII_CODE_SYNC_SET_VAL BIT(9) 486 #define SGMII_CODE_SYNC_SET_EN BIT(10) 487 #define SGMII_SEND_AN_ERROR_EN BIT(11) 488 #define SGMII_IF_MODE_MASK GENMASK(5, 1) 489 490 /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 491 #define SGMSYS_ANA_RG_CS3 0x2028 492 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 493 #define RG_PHY_SPEED_1_25G 0x0 494 #define RG_PHY_SPEED_3_125G BIT(2) 495 496 /* Register to power up QPHY */ 497 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 498 #define SGMII_PHYA_PWD BIT(4) 499 500 /* Infrasys subsystem config registers */ 501 #define INFRA_MISC2 0x70c 502 #define CO_QPHY_SEL BIT(0) 503 #define GEPHY_MAC_SEL BIT(1) 504 505 /* MT7628/88 specific stuff */ 506 #define MT7628_PDMA_OFFSET 0x0800 507 #define MT7628_SDM_OFFSET 0x0c00 508 509 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 510 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 511 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 512 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 513 #define MT7628_PST_DTX_IDX0 BIT(0) 514 515 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 516 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 517 518 /* Counter / stat register */ 519 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 520 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 521 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 522 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 523 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 524 525 struct mtk_rx_dma { 526 unsigned int rxd1; 527 unsigned int rxd2; 528 unsigned int rxd3; 529 unsigned int rxd4; 530 } __packed __aligned(4); 531 532 struct mtk_tx_dma { 533 unsigned int txd1; 534 unsigned int txd2; 535 unsigned int txd3; 536 unsigned int txd4; 537 } __packed __aligned(4); 538 539 struct mtk_eth; 540 struct mtk_mac; 541 542 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 543 * @stats_lock: make sure that stats operations are atomic 544 * @reg_offset: the status register offset of the SoC 545 * @syncp: the refcount 546 * 547 * All of the supported SoCs have hardware counters for traffic statistics. 548 * Whenever the status IRQ triggers we can read the latest stats from these 549 * counters and store them in this struct. 550 */ 551 struct mtk_hw_stats { 552 u64 tx_bytes; 553 u64 tx_packets; 554 u64 tx_skip; 555 u64 tx_collisions; 556 u64 rx_bytes; 557 u64 rx_packets; 558 u64 rx_overflow; 559 u64 rx_fcs_errors; 560 u64 rx_short_errors; 561 u64 rx_long_errors; 562 u64 rx_checksum_errors; 563 u64 rx_flow_control_packets; 564 565 spinlock_t stats_lock; 566 u32 reg_offset; 567 struct u64_stats_sync syncp; 568 }; 569 570 enum mtk_tx_flags { 571 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 572 * track how memory was allocated so that it can be freed properly. 573 */ 574 MTK_TX_FLAGS_SINGLE0 = 0x01, 575 MTK_TX_FLAGS_PAGE0 = 0x02, 576 577 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 578 * SKB out instead of looking up through hardware TX descriptor. 579 */ 580 MTK_TX_FLAGS_FPORT0 = 0x04, 581 MTK_TX_FLAGS_FPORT1 = 0x08, 582 }; 583 584 /* This enum allows us to identify how the clock is defined on the array of the 585 * clock in the order 586 */ 587 enum mtk_clks_map { 588 MTK_CLK_ETHIF, 589 MTK_CLK_SGMIITOP, 590 MTK_CLK_ESW, 591 MTK_CLK_GP0, 592 MTK_CLK_GP1, 593 MTK_CLK_GP2, 594 MTK_CLK_FE, 595 MTK_CLK_TRGPLL, 596 MTK_CLK_SGMII_TX_250M, 597 MTK_CLK_SGMII_RX_250M, 598 MTK_CLK_SGMII_CDR_REF, 599 MTK_CLK_SGMII_CDR_FB, 600 MTK_CLK_SGMII2_TX_250M, 601 MTK_CLK_SGMII2_RX_250M, 602 MTK_CLK_SGMII2_CDR_REF, 603 MTK_CLK_SGMII2_CDR_FB, 604 MTK_CLK_SGMII_CK, 605 MTK_CLK_ETH2PLL, 606 MTK_CLK_MAX 607 }; 608 609 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 610 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 611 BIT(MTK_CLK_TRGPLL)) 612 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 613 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 614 BIT(MTK_CLK_GP2) | \ 615 BIT(MTK_CLK_SGMII_TX_250M) | \ 616 BIT(MTK_CLK_SGMII_RX_250M) | \ 617 BIT(MTK_CLK_SGMII_CDR_REF) | \ 618 BIT(MTK_CLK_SGMII_CDR_FB) | \ 619 BIT(MTK_CLK_SGMII_CK) | \ 620 BIT(MTK_CLK_ETH2PLL)) 621 #define MT7621_CLKS_BITMAP (0) 622 #define MT7628_CLKS_BITMAP (0) 623 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 624 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 625 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 626 BIT(MTK_CLK_SGMII_TX_250M) | \ 627 BIT(MTK_CLK_SGMII_RX_250M) | \ 628 BIT(MTK_CLK_SGMII_CDR_REF) | \ 629 BIT(MTK_CLK_SGMII_CDR_FB) | \ 630 BIT(MTK_CLK_SGMII2_TX_250M) | \ 631 BIT(MTK_CLK_SGMII2_RX_250M) | \ 632 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 633 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 634 BIT(MTK_CLK_SGMII_CK) | \ 635 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 636 637 enum mtk_dev_state { 638 MTK_HW_INIT, 639 MTK_RESETTING 640 }; 641 642 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 643 * by the TX descriptor s 644 * @skb: The SKB pointer of the packet being sent 645 * @dma_addr0: The base addr of the first segment 646 * @dma_len0: The length of the first segment 647 * @dma_addr1: The base addr of the second segment 648 * @dma_len1: The length of the second segment 649 */ 650 struct mtk_tx_buf { 651 struct sk_buff *skb; 652 u32 flags; 653 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 654 DEFINE_DMA_UNMAP_LEN(dma_len0); 655 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 656 DEFINE_DMA_UNMAP_LEN(dma_len1); 657 }; 658 659 /* struct mtk_tx_ring - This struct holds info describing a TX ring 660 * @dma: The descriptor ring 661 * @buf: The memory pointed at by the ring 662 * @phys: The physical addr of tx_buf 663 * @next_free: Pointer to the next free descriptor 664 * @last_free: Pointer to the last free descriptor 665 * @last_free_ptr: Hardware pointer value of the last free descriptor 666 * @thresh: The threshold of minimum amount of free descriptors 667 * @free_count: QDMA uses a linked list. Track how many free descriptors 668 * are present 669 */ 670 struct mtk_tx_ring { 671 struct mtk_tx_dma *dma; 672 struct mtk_tx_buf *buf; 673 dma_addr_t phys; 674 struct mtk_tx_dma *next_free; 675 struct mtk_tx_dma *last_free; 676 u32 last_free_ptr; 677 u16 thresh; 678 atomic_t free_count; 679 int dma_size; 680 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 681 dma_addr_t phys_pdma; 682 int cpu_idx; 683 }; 684 685 /* PDMA rx ring mode */ 686 enum mtk_rx_flags { 687 MTK_RX_FLAGS_NORMAL = 0, 688 MTK_RX_FLAGS_HWLRO, 689 MTK_RX_FLAGS_QDMA, 690 }; 691 692 /* struct mtk_rx_ring - This struct holds info describing a RX ring 693 * @dma: The descriptor ring 694 * @data: The memory pointed at by the ring 695 * @phys: The physical addr of rx_buf 696 * @frag_size: How big can each fragment be 697 * @buf_size: The size of each packet buffer 698 * @calc_idx: The current head of ring 699 */ 700 struct mtk_rx_ring { 701 struct mtk_rx_dma *dma; 702 u8 **data; 703 dma_addr_t phys; 704 u16 frag_size; 705 u16 buf_size; 706 u16 dma_size; 707 bool calc_idx_update; 708 u16 calc_idx; 709 u32 crx_idx_reg; 710 }; 711 712 enum mkt_eth_capabilities { 713 MTK_RGMII_BIT = 0, 714 MTK_TRGMII_BIT, 715 MTK_SGMII_BIT, 716 MTK_ESW_BIT, 717 MTK_GEPHY_BIT, 718 MTK_MUX_BIT, 719 MTK_INFRA_BIT, 720 MTK_SHARED_SGMII_BIT, 721 MTK_HWLRO_BIT, 722 MTK_SHARED_INT_BIT, 723 MTK_TRGMII_MT7621_CLK_BIT, 724 MTK_QDMA_BIT, 725 MTK_SOC_MT7628_BIT, 726 727 /* MUX BITS*/ 728 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 729 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 730 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 731 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 732 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 733 734 /* PATH BITS */ 735 MTK_ETH_PATH_GMAC1_RGMII_BIT, 736 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 737 MTK_ETH_PATH_GMAC1_SGMII_BIT, 738 MTK_ETH_PATH_GMAC2_RGMII_BIT, 739 MTK_ETH_PATH_GMAC2_SGMII_BIT, 740 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 741 MTK_ETH_PATH_GDM1_ESW_BIT, 742 }; 743 744 /* Supported hardware group on SoCs */ 745 #define MTK_RGMII BIT(MTK_RGMII_BIT) 746 #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 747 #define MTK_SGMII BIT(MTK_SGMII_BIT) 748 #define MTK_ESW BIT(MTK_ESW_BIT) 749 #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 750 #define MTK_MUX BIT(MTK_MUX_BIT) 751 #define MTK_INFRA BIT(MTK_INFRA_BIT) 752 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 753 #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 754 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 755 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 756 #define MTK_QDMA BIT(MTK_QDMA_BIT) 757 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 758 759 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 760 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 761 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 762 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 763 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 764 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 765 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 766 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 767 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 768 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 769 770 /* Supported path present on SoCs */ 771 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 772 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 773 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 774 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 775 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 776 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 777 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 778 779 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 780 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 781 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 782 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 783 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 784 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 785 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 786 787 /* MUXes present on SoCs */ 788 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 789 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 790 791 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 792 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 793 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 794 795 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 796 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 797 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 798 799 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 800 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 801 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 802 MTK_SHARED_SGMII) 803 804 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 805 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 806 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 807 808 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 809 810 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 811 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 812 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 813 814 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 815 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 816 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 817 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 818 819 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 820 MTK_QDMA) 821 822 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 823 824 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 825 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 826 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 827 MTK_MUX_U3_GMAC2_TO_QPHY | \ 828 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 829 830 /* struct mtk_eth_data - This is the structure holding all differences 831 * among various plaforms 832 * @ana_rgc3: The offset for register ANA_RGC3 related to 833 * sgmiisys syscon 834 * @caps Flags shown the extra capability for the SoC 835 * @hw_features Flags shown HW features 836 * @required_clks Flags shown the bitmap for required clocks on 837 * the target SoC 838 * @required_pctl A bool value to show whether the SoC requires 839 * the extra setup for those pins used by GMAC. 840 */ 841 struct mtk_soc_data { 842 u32 ana_rgc3; 843 u32 caps; 844 u32 required_clks; 845 bool required_pctl; 846 u8 offload_version; 847 netdev_features_t hw_features; 848 }; 849 850 /* currently no SoC has more than 2 macs */ 851 #define MTK_MAX_DEVS 2 852 853 #define MTK_SGMII_PHYSPEED_AN BIT(31) 854 #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) 855 #define MTK_SGMII_PHYSPEED_1000 BIT(0) 856 #define MTK_SGMII_PHYSPEED_2500 BIT(1) 857 #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) 858 859 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 860 * characteristics 861 * @regmap: The register map pointing at the range used to setup 862 * SGMII modes 863 * @flags: The enum refers to which mode the sgmii wants to run on 864 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 865 */ 866 867 struct mtk_sgmii { 868 struct regmap *regmap[MTK_MAX_DEVS]; 869 u32 flags[MTK_MAX_DEVS]; 870 u32 ana_rgc3; 871 }; 872 873 /* struct mtk_eth - This is the main datasructure for holding the state 874 * of the driver 875 * @dev: The device pointer 876 * @base: The mapped register i/o base 877 * @page_lock: Make sure that register operations are atomic 878 * @tx_irq__lock: Make sure that IRQ register operations are atomic 879 * @rx_irq__lock: Make sure that IRQ register operations are atomic 880 * @dim_lock: Make sure that Net DIM operations are atomic 881 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 882 * dummy for NAPI to work 883 * @netdev: The netdev instances 884 * @mac: Each netdev is linked to a physical MAC 885 * @irq: The IRQ that we are using 886 * @msg_enable: Ethtool msg level 887 * @ethsys: The register map pointing at the range used to setup 888 * MII modes 889 * @infra: The register map pointing at the range used to setup 890 * SGMII and GePHY path 891 * @pctl: The register map pointing at the range used to setup 892 * GMAC port drive/slew values 893 * @dma_refcnt: track how many netdevs are using the DMA engine 894 * @tx_ring: Pointer to the memory holding info about the TX ring 895 * @rx_ring: Pointer to the memory holding info about the RX ring 896 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 897 * @tx_napi: The TX NAPI struct 898 * @rx_napi: The RX NAPI struct 899 * @rx_events: Net DIM RX event counter 900 * @rx_packets: Net DIM RX packet counter 901 * @rx_bytes: Net DIM RX byte counter 902 * @rx_dim: Net DIM RX context 903 * @tx_events: Net DIM TX event counter 904 * @tx_packets: Net DIM TX packet counter 905 * @tx_bytes: Net DIM TX byte counter 906 * @tx_dim: Net DIM TX context 907 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 908 * @phy_scratch_ring: physical address of scratch_ring 909 * @scratch_head: The scratch memory that scratch_ring points to. 910 * @clks: clock array for all clocks required 911 * @mii_bus: If there is a bus we need to create an instance for it 912 * @pending_work: The workqueue used to reset the dma ring 913 * @state: Initialization and runtime state of the device 914 * @soc: Holding specific data among vaious SoCs 915 */ 916 917 struct mtk_eth { 918 struct device *dev; 919 void __iomem *base; 920 spinlock_t page_lock; 921 spinlock_t tx_irq_lock; 922 spinlock_t rx_irq_lock; 923 struct net_device dummy_dev; 924 struct net_device *netdev[MTK_MAX_DEVS]; 925 struct mtk_mac *mac[MTK_MAX_DEVS]; 926 int irq[3]; 927 u32 msg_enable; 928 unsigned long sysclk; 929 struct regmap *ethsys; 930 struct regmap *infra; 931 struct mtk_sgmii *sgmii; 932 struct regmap *pctl; 933 bool hwlro; 934 refcount_t dma_refcnt; 935 struct mtk_tx_ring tx_ring; 936 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 937 struct mtk_rx_ring rx_ring_qdma; 938 struct napi_struct tx_napi; 939 struct napi_struct rx_napi; 940 struct mtk_tx_dma *scratch_ring; 941 dma_addr_t phy_scratch_ring; 942 void *scratch_head; 943 struct clk *clks[MTK_CLK_MAX]; 944 945 struct mii_bus *mii_bus; 946 struct work_struct pending_work; 947 unsigned long state; 948 949 const struct mtk_soc_data *soc; 950 951 spinlock_t dim_lock; 952 953 u32 rx_events; 954 u32 rx_packets; 955 u32 rx_bytes; 956 struct dim rx_dim; 957 958 u32 tx_events; 959 u32 tx_packets; 960 u32 tx_bytes; 961 struct dim tx_dim; 962 963 u32 tx_int_mask_reg; 964 u32 tx_int_status_reg; 965 u32 rx_dma_l4_valid; 966 int ip_align; 967 968 struct mtk_ppe ppe; 969 struct rhashtable flow_table; 970 }; 971 972 /* struct mtk_mac - the structure that holds the info about the MACs of the 973 * SoC 974 * @id: The number of the MAC 975 * @interface: Interface mode kept for detecting change in hw settings 976 * @of_node: Our devicetree node 977 * @hw: Backpointer to our main datastruture 978 * @hw_stats: Packet statistics counter 979 */ 980 struct mtk_mac { 981 int id; 982 phy_interface_t interface; 983 unsigned int mode; 984 int speed; 985 struct device_node *of_node; 986 struct phylink *phylink; 987 struct phylink_config phylink_config; 988 struct mtk_eth *hw; 989 struct mtk_hw_stats *hw_stats; 990 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 991 int hwlro_ip_cnt; 992 }; 993 994 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 995 extern const struct of_device_id of_mtk_match[]; 996 997 /* read the hardware status register */ 998 void mtk_stats_update_mac(struct mtk_mac *mac); 999 1000 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1001 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1002 1003 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 1004 u32 ana_rgc3); 1005 int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); 1006 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, 1007 const struct phylink_link_state *state); 1008 void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); 1009 1010 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1011 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1012 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1013 1014 int mtk_eth_offload_init(struct mtk_eth *eth); 1015 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1016 void *type_data); 1017 1018 1019 #endif /* MTK_ETH_H */ 1020