1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #ifndef MTK_ETH_H 16 #define MTK_ETH_H 17 18 #include <linux/dma-mapping.h> 19 #include <linux/netdevice.h> 20 #include <linux/of_net.h> 21 #include <linux/u64_stats_sync.h> 22 #include <linux/refcount.h> 23 24 #define MTK_QDMA_PAGE_SIZE 2048 25 #define MTK_MAX_RX_LENGTH 1536 26 #define MTK_TX_DMA_BUF_LEN 0x3fff 27 #define MTK_DMA_SIZE 256 28 #define MTK_NAPI_WEIGHT 64 29 #define MTK_MAC_COUNT 2 30 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 31 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 32 #define MTK_DMA_DUMMY_DESC 0xffffffff 33 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 34 NETIF_MSG_PROBE | \ 35 NETIF_MSG_LINK | \ 36 NETIF_MSG_TIMER | \ 37 NETIF_MSG_IFDOWN | \ 38 NETIF_MSG_IFUP | \ 39 NETIF_MSG_RX_ERR | \ 40 NETIF_MSG_TX_ERR) 41 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 42 NETIF_F_RXCSUM | \ 43 NETIF_F_HW_VLAN_CTAG_TX | \ 44 NETIF_F_HW_VLAN_CTAG_RX | \ 45 NETIF_F_SG | NETIF_F_TSO | \ 46 NETIF_F_TSO6 | \ 47 NETIF_F_IPV6_CSUM) 48 #define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 49 50 #define MTK_MAX_RX_RING_NUM 4 51 #define MTK_HW_LRO_DMA_SIZE 8 52 53 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 54 #define MTK_MAX_LRO_IP_CNT 2 55 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 56 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 57 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 58 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 59 #define MTK_HW_LRO_MAX_AGG_CNT 64 60 #define MTK_HW_LRO_BW_THRE 3000 61 #define MTK_HW_LRO_REPLACE_DELTA 1000 62 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 63 64 /* Frame Engine Global Reset Register */ 65 #define MTK_RST_GL 0x04 66 #define RST_GL_PSE BIT(0) 67 68 /* Frame Engine Interrupt Status Register */ 69 #define MTK_INT_STATUS2 0x08 70 #define MTK_GDM1_AF BIT(28) 71 #define MTK_GDM2_AF BIT(29) 72 73 /* PDMA HW LRO Alter Flow Timer Register */ 74 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 75 76 /* Frame Engine Interrupt Grouping Register */ 77 #define MTK_FE_INT_GRP 0x20 78 79 /* CDMP Ingress Control Register */ 80 #define MTK_CDMQ_IG_CTRL 0x1400 81 #define MTK_CDMQ_STAG_EN BIT(0) 82 83 /* CDMP Exgress Control Register */ 84 #define MTK_CDMP_EG_CTRL 0x404 85 86 /* GDM Exgress Control Register */ 87 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 88 #define MTK_GDMA_ICS_EN BIT(22) 89 #define MTK_GDMA_TCS_EN BIT(21) 90 #define MTK_GDMA_UCS_EN BIT(20) 91 92 /* Unicast Filter MAC Address Register - Low */ 93 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 94 95 /* Unicast Filter MAC Address Register - High */ 96 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 97 98 /* PDMA RX Base Pointer Register */ 99 #define MTK_PRX_BASE_PTR0 0x900 100 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 101 102 /* PDMA RX Maximum Count Register */ 103 #define MTK_PRX_MAX_CNT0 0x904 104 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 105 106 /* PDMA RX CPU Pointer Register */ 107 #define MTK_PRX_CRX_IDX0 0x908 108 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 109 110 /* PDMA HW LRO Control Registers */ 111 #define MTK_PDMA_LRO_CTRL_DW0 0x980 112 #define MTK_LRO_EN BIT(0) 113 #define MTK_L3_CKS_UPD_EN BIT(7) 114 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 115 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 116 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 117 118 #define MTK_PDMA_LRO_CTRL_DW1 0x984 119 #define MTK_PDMA_LRO_CTRL_DW2 0x988 120 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 121 #define MTK_ADMA_MODE BIT(15) 122 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 123 124 /* PDMA Global Configuration Register */ 125 #define MTK_PDMA_GLO_CFG 0xa04 126 #define MTK_MULTI_EN BIT(10) 127 128 /* PDMA Reset Index Register */ 129 #define MTK_PDMA_RST_IDX 0xa08 130 #define MTK_PST_DRX_IDX0 BIT(16) 131 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 132 133 /* PDMA Delay Interrupt Register */ 134 #define MTK_PDMA_DELAY_INT 0xa0c 135 #define MTK_PDMA_DELAY_RX_EN BIT(15) 136 #define MTK_PDMA_DELAY_RX_PINT 4 137 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 138 #define MTK_PDMA_DELAY_RX_PTIME 4 139 #define MTK_PDMA_DELAY_RX_DELAY \ 140 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 141 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 142 143 /* PDMA Interrupt Status Register */ 144 #define MTK_PDMA_INT_STATUS 0xa20 145 146 /* PDMA Interrupt Mask Register */ 147 #define MTK_PDMA_INT_MASK 0xa28 148 149 /* PDMA HW LRO Alter Flow Delta Register */ 150 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 151 152 /* PDMA Interrupt grouping registers */ 153 #define MTK_PDMA_INT_GRP1 0xa50 154 #define MTK_PDMA_INT_GRP2 0xa54 155 156 /* PDMA HW LRO IP Setting Registers */ 157 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 158 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 159 #define MTK_RING_MYIP_VLD BIT(9) 160 161 /* PDMA HW LRO Ring Control Registers */ 162 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 163 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 164 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 165 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 166 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 167 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 168 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 169 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 170 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 171 #define MTK_RING_VLD BIT(8) 172 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 173 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 174 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 175 176 /* QDMA TX Queue Configuration Registers */ 177 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 178 #define QDMA_RES_THRES 4 179 180 /* QDMA TX Queue Scheduler Registers */ 181 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 182 183 /* QDMA RX Base Pointer Register */ 184 #define MTK_QRX_BASE_PTR0 0x1900 185 186 /* QDMA RX Maximum Count Register */ 187 #define MTK_QRX_MAX_CNT0 0x1904 188 189 /* QDMA RX CPU Pointer Register */ 190 #define MTK_QRX_CRX_IDX0 0x1908 191 192 /* QDMA RX DMA Pointer Register */ 193 #define MTK_QRX_DRX_IDX0 0x190C 194 195 /* QDMA Global Configuration Register */ 196 #define MTK_QDMA_GLO_CFG 0x1A04 197 #define MTK_RX_2B_OFFSET BIT(31) 198 #define MTK_RX_BT_32DWORDS (3 << 11) 199 #define MTK_NDP_CO_PRO BIT(10) 200 #define MTK_TX_WB_DDONE BIT(6) 201 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 202 #define MTK_RX_DMA_BUSY BIT(3) 203 #define MTK_TX_DMA_BUSY BIT(1) 204 #define MTK_RX_DMA_EN BIT(2) 205 #define MTK_TX_DMA_EN BIT(0) 206 #define MTK_DMA_BUSY_TIMEOUT HZ 207 208 /* QDMA Reset Index Register */ 209 #define MTK_QDMA_RST_IDX 0x1A08 210 211 /* QDMA Delay Interrupt Register */ 212 #define MTK_QDMA_DELAY_INT 0x1A0C 213 214 /* QDMA Flow Control Register */ 215 #define MTK_QDMA_FC_THRES 0x1A10 216 #define FC_THRES_DROP_MODE BIT(20) 217 #define FC_THRES_DROP_EN (7 << 16) 218 #define FC_THRES_MIN 0x4444 219 220 /* QDMA Interrupt Status Register */ 221 #define MTK_QMTK_INT_STATUS 0x1A18 222 #define MTK_RX_DONE_DLY BIT(30) 223 #define MTK_RX_DONE_INT3 BIT(19) 224 #define MTK_RX_DONE_INT2 BIT(18) 225 #define MTK_RX_DONE_INT1 BIT(17) 226 #define MTK_RX_DONE_INT0 BIT(16) 227 #define MTK_TX_DONE_INT3 BIT(3) 228 #define MTK_TX_DONE_INT2 BIT(2) 229 #define MTK_TX_DONE_INT1 BIT(1) 230 #define MTK_TX_DONE_INT0 BIT(0) 231 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 232 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 233 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 234 235 /* QDMA Interrupt grouping registers */ 236 #define MTK_QDMA_INT_GRP1 0x1a20 237 #define MTK_QDMA_INT_GRP2 0x1a24 238 #define MTK_RLS_DONE_INT BIT(0) 239 240 /* QDMA Interrupt Status Register */ 241 #define MTK_QDMA_INT_MASK 0x1A1C 242 243 /* QDMA Interrupt Mask Register */ 244 #define MTK_QDMA_HRED2 0x1A44 245 246 /* QDMA TX Forward CPU Pointer Register */ 247 #define MTK_QTX_CTX_PTR 0x1B00 248 249 /* QDMA TX Forward DMA Pointer Register */ 250 #define MTK_QTX_DTX_PTR 0x1B04 251 252 /* QDMA TX Release CPU Pointer Register */ 253 #define MTK_QTX_CRX_PTR 0x1B10 254 255 /* QDMA TX Release DMA Pointer Register */ 256 #define MTK_QTX_DRX_PTR 0x1B14 257 258 /* QDMA FQ Head Pointer Register */ 259 #define MTK_QDMA_FQ_HEAD 0x1B20 260 261 /* QDMA FQ Head Pointer Register */ 262 #define MTK_QDMA_FQ_TAIL 0x1B24 263 264 /* QDMA FQ Free Page Counter Register */ 265 #define MTK_QDMA_FQ_CNT 0x1B28 266 267 /* QDMA FQ Free Page Buffer Length Register */ 268 #define MTK_QDMA_FQ_BLEN 0x1B2C 269 270 /* GMA1 Received Good Byte Count Register */ 271 #define MTK_GDM1_TX_GBCNT 0x2400 272 #define MTK_STAT_OFFSET 0x40 273 274 /* QDMA descriptor txd4 */ 275 #define TX_DMA_CHKSUM (0x7 << 29) 276 #define TX_DMA_TSO BIT(28) 277 #define TX_DMA_FPORT_SHIFT 25 278 #define TX_DMA_FPORT_MASK 0x7 279 #define TX_DMA_INS_VLAN BIT(16) 280 281 /* QDMA descriptor txd3 */ 282 #define TX_DMA_OWNER_CPU BIT(31) 283 #define TX_DMA_LS0 BIT(30) 284 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 285 #define TX_DMA_SWC BIT(14) 286 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 287 288 /* QDMA descriptor rxd2 */ 289 #define RX_DMA_DONE BIT(31) 290 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 291 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 292 293 /* QDMA descriptor rxd3 */ 294 #define RX_DMA_VID(_x) ((_x) & 0xfff) 295 296 /* QDMA descriptor rxd4 */ 297 #define RX_DMA_L4_VALID BIT(24) 298 #define RX_DMA_FPORT_SHIFT 19 299 #define RX_DMA_FPORT_MASK 0x7 300 301 /* PHY Indirect Access Control registers */ 302 #define MTK_PHY_IAC 0x10004 303 #define PHY_IAC_ACCESS BIT(31) 304 #define PHY_IAC_READ BIT(19) 305 #define PHY_IAC_WRITE BIT(18) 306 #define PHY_IAC_START BIT(16) 307 #define PHY_IAC_ADDR_SHIFT 20 308 #define PHY_IAC_REG_SHIFT 25 309 #define PHY_IAC_TIMEOUT HZ 310 311 #define MTK_MAC_MISC 0x1000c 312 #define MTK_MUX_TO_ESW BIT(0) 313 314 /* Mac control registers */ 315 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 316 #define MAC_MCR_MAX_RX_1536 BIT(24) 317 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 318 #define MAC_MCR_FORCE_MODE BIT(15) 319 #define MAC_MCR_TX_EN BIT(14) 320 #define MAC_MCR_RX_EN BIT(13) 321 #define MAC_MCR_BACKOFF_EN BIT(9) 322 #define MAC_MCR_BACKPR_EN BIT(8) 323 #define MAC_MCR_FORCE_RX_FC BIT(5) 324 #define MAC_MCR_FORCE_TX_FC BIT(4) 325 #define MAC_MCR_SPEED_1000 BIT(3) 326 #define MAC_MCR_SPEED_100 BIT(2) 327 #define MAC_MCR_FORCE_DPX BIT(1) 328 #define MAC_MCR_FORCE_LINK BIT(0) 329 #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 330 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 331 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 332 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 333 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 334 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 335 336 /* TRGMII RXC control register */ 337 #define TRGMII_RCK_CTRL 0x10300 338 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 339 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 340 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 341 #define RXC_DQSISEL BIT(30) 342 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 343 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 344 345 /* TRGMII RXC control register */ 346 #define TRGMII_TCK_CTRL 0x10340 347 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 348 #define TXC_INV BIT(30) 349 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 350 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 351 352 /* TRGMII Interface mode register */ 353 #define INTF_MODE 0x10390 354 #define TRGMII_INTF_DIS BIT(0) 355 #define TRGMII_MODE BIT(1) 356 #define TRGMII_CENTRAL_ALIGNED BIT(2) 357 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 358 #define INTF_MODE_RGMII_10_100 0 359 360 /* GPIO port control registers for GMAC 2*/ 361 #define GPIO_OD33_CTRL8 0x4c0 362 #define GPIO_BIAS_CTRL 0xed0 363 #define GPIO_DRV_SEL10 0xf00 364 365 /* ethernet subsystem chip id register */ 366 #define ETHSYS_CHIPID0_3 0x0 367 #define ETHSYS_CHIPID4_7 0x4 368 #define MT7623_ETH 7623 369 #define MT7622_ETH 7622 370 #define MT7621_ETH 7621 371 372 /* ethernet subsystem config register */ 373 #define ETHSYS_SYSCFG0 0x14 374 #define SYSCFG0_GE_MASK 0x3 375 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 376 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 377 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 378 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 379 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 380 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 381 382 383 /* ethernet subsystem clock register */ 384 #define ETHSYS_CLKCFG0 0x2c 385 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 386 387 /* ethernet reset control register */ 388 #define ETHSYS_RSTCTRL 0x34 389 #define RSTCTRL_FE BIT(6) 390 #define RSTCTRL_PPE BIT(31) 391 392 /* SGMII subsystem config registers */ 393 /* Register to auto-negotiation restart */ 394 #define SGMSYS_PCS_CONTROL_1 0x0 395 #define SGMII_AN_RESTART BIT(9) 396 397 /* Register to programmable link timer, the unit in 2 * 8ns */ 398 #define SGMSYS_PCS_LINK_TIMER 0x18 399 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 400 401 /* Register to control remote fault */ 402 #define SGMSYS_SGMII_MODE 0x20 403 #define SGMII_REMOTE_FAULT_DIS BIT(8) 404 405 /* Register to power up QPHY */ 406 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 407 #define SGMII_PHYA_PWD BIT(4) 408 409 /* Infrasys subsystem config registers */ 410 #define INFRA_MISC2 0x70c 411 #define CO_QPHY_SEL BIT(0) 412 #define GEPHY_MAC_SEL BIT(1) 413 414 struct mtk_rx_dma { 415 unsigned int rxd1; 416 unsigned int rxd2; 417 unsigned int rxd3; 418 unsigned int rxd4; 419 } __packed __aligned(4); 420 421 struct mtk_tx_dma { 422 unsigned int txd1; 423 unsigned int txd2; 424 unsigned int txd3; 425 unsigned int txd4; 426 } __packed __aligned(4); 427 428 struct mtk_eth; 429 struct mtk_mac; 430 431 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 432 * @stats_lock: make sure that stats operations are atomic 433 * @reg_offset: the status register offset of the SoC 434 * @syncp: the refcount 435 * 436 * All of the supported SoCs have hardware counters for traffic statistics. 437 * Whenever the status IRQ triggers we can read the latest stats from these 438 * counters and store them in this struct. 439 */ 440 struct mtk_hw_stats { 441 u64 tx_bytes; 442 u64 tx_packets; 443 u64 tx_skip; 444 u64 tx_collisions; 445 u64 rx_bytes; 446 u64 rx_packets; 447 u64 rx_overflow; 448 u64 rx_fcs_errors; 449 u64 rx_short_errors; 450 u64 rx_long_errors; 451 u64 rx_checksum_errors; 452 u64 rx_flow_control_packets; 453 454 spinlock_t stats_lock; 455 u32 reg_offset; 456 struct u64_stats_sync syncp; 457 }; 458 459 enum mtk_tx_flags { 460 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 461 * track how memory was allocated so that it can be freed properly. 462 */ 463 MTK_TX_FLAGS_SINGLE0 = 0x01, 464 MTK_TX_FLAGS_PAGE0 = 0x02, 465 466 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 467 * SKB out instead of looking up through hardware TX descriptor. 468 */ 469 MTK_TX_FLAGS_FPORT0 = 0x04, 470 MTK_TX_FLAGS_FPORT1 = 0x08, 471 }; 472 473 /* This enum allows us to identify how the clock is defined on the array of the 474 * clock in the order 475 */ 476 enum mtk_clks_map { 477 MTK_CLK_ETHIF, 478 MTK_CLK_SGMIITOP, 479 MTK_CLK_ESW, 480 MTK_CLK_GP0, 481 MTK_CLK_GP1, 482 MTK_CLK_GP2, 483 MTK_CLK_FE, 484 MTK_CLK_TRGPLL, 485 MTK_CLK_SGMII_TX_250M, 486 MTK_CLK_SGMII_RX_250M, 487 MTK_CLK_SGMII_CDR_REF, 488 MTK_CLK_SGMII_CDR_FB, 489 MTK_CLK_SGMII2_TX_250M, 490 MTK_CLK_SGMII2_RX_250M, 491 MTK_CLK_SGMII2_CDR_REF, 492 MTK_CLK_SGMII2_CDR_FB, 493 MTK_CLK_SGMII_CK, 494 MTK_CLK_ETH2PLL, 495 MTK_CLK_MAX 496 }; 497 498 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 499 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 500 BIT(MTK_CLK_TRGPLL)) 501 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 502 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 503 BIT(MTK_CLK_GP2) | \ 504 BIT(MTK_CLK_SGMII_TX_250M) | \ 505 BIT(MTK_CLK_SGMII_RX_250M) | \ 506 BIT(MTK_CLK_SGMII_CDR_REF) | \ 507 BIT(MTK_CLK_SGMII_CDR_FB) | \ 508 BIT(MTK_CLK_SGMII_CK) | \ 509 BIT(MTK_CLK_ETH2PLL)) 510 #define MT7621_CLKS_BITMAP (0) 511 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 512 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 513 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 514 BIT(MTK_CLK_SGMII_TX_250M) | \ 515 BIT(MTK_CLK_SGMII_RX_250M) | \ 516 BIT(MTK_CLK_SGMII_CDR_REF) | \ 517 BIT(MTK_CLK_SGMII_CDR_FB) | \ 518 BIT(MTK_CLK_SGMII2_TX_250M) | \ 519 BIT(MTK_CLK_SGMII2_RX_250M) | \ 520 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 521 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 522 BIT(MTK_CLK_SGMII_CK) | \ 523 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 524 525 enum mtk_dev_state { 526 MTK_HW_INIT, 527 MTK_RESETTING 528 }; 529 530 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 531 * by the TX descriptor s 532 * @skb: The SKB pointer of the packet being sent 533 * @dma_addr0: The base addr of the first segment 534 * @dma_len0: The length of the first segment 535 * @dma_addr1: The base addr of the second segment 536 * @dma_len1: The length of the second segment 537 */ 538 struct mtk_tx_buf { 539 struct sk_buff *skb; 540 u32 flags; 541 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 542 DEFINE_DMA_UNMAP_LEN(dma_len0); 543 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 544 DEFINE_DMA_UNMAP_LEN(dma_len1); 545 }; 546 547 /* struct mtk_tx_ring - This struct holds info describing a TX ring 548 * @dma: The descriptor ring 549 * @buf: The memory pointed at by the ring 550 * @phys: The physical addr of tx_buf 551 * @next_free: Pointer to the next free descriptor 552 * @last_free: Pointer to the last free descriptor 553 * @thresh: The threshold of minimum amount of free descriptors 554 * @free_count: QDMA uses a linked list. Track how many free descriptors 555 * are present 556 */ 557 struct mtk_tx_ring { 558 struct mtk_tx_dma *dma; 559 struct mtk_tx_buf *buf; 560 dma_addr_t phys; 561 struct mtk_tx_dma *next_free; 562 struct mtk_tx_dma *last_free; 563 u16 thresh; 564 atomic_t free_count; 565 }; 566 567 /* PDMA rx ring mode */ 568 enum mtk_rx_flags { 569 MTK_RX_FLAGS_NORMAL = 0, 570 MTK_RX_FLAGS_HWLRO, 571 MTK_RX_FLAGS_QDMA, 572 }; 573 574 /* struct mtk_rx_ring - This struct holds info describing a RX ring 575 * @dma: The descriptor ring 576 * @data: The memory pointed at by the ring 577 * @phys: The physical addr of rx_buf 578 * @frag_size: How big can each fragment be 579 * @buf_size: The size of each packet buffer 580 * @calc_idx: The current head of ring 581 */ 582 struct mtk_rx_ring { 583 struct mtk_rx_dma *dma; 584 u8 **data; 585 dma_addr_t phys; 586 u16 frag_size; 587 u16 buf_size; 588 u16 dma_size; 589 bool calc_idx_update; 590 u16 calc_idx; 591 u32 crx_idx_reg; 592 }; 593 594 enum mtk_eth_mux { 595 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW, 596 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY, 597 MTK_ETH_MUX_U3_GMAC2_TO_QPHY, 598 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII, 599 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII, 600 MTK_ETH_MUX_MAX, 601 }; 602 603 enum mtk_eth_path { 604 MTK_ETH_PATH_GMAC1_RGMII, 605 MTK_ETH_PATH_GMAC1_TRGMII, 606 MTK_ETH_PATH_GMAC1_SGMII, 607 MTK_ETH_PATH_GMAC2_RGMII, 608 MTK_ETH_PATH_GMAC2_SGMII, 609 MTK_ETH_PATH_GMAC2_GEPHY, 610 MTK_ETH_PATH_GDM1_ESW, 611 MTK_ETH_PATH_MAX, 612 }; 613 614 /* Supported hardware group on SoCs */ 615 #define MTK_RGMII BIT(0) 616 #define MTK_TRGMII BIT(1) 617 #define MTK_SGMII BIT(2) 618 #define MTK_ESW BIT(3) 619 #define MTK_GEPHY BIT(4) 620 #define MTK_MUX BIT(5) 621 #define MTK_INFRA BIT(6) 622 #define MTK_SHARED_SGMII BIT(7) 623 #define MTK_HWLRO BIT(8) 624 #define MTK_SHARED_INT BIT(9) 625 626 /* Supported path present on SoCs */ 627 #define MTK_PATH_BIT(x) BIT((x) + 10) 628 629 #define MTK_GMAC1_RGMII \ 630 (MTK_PATH_BIT(MTK_ETH_PATH_GMAC1_RGMII) | MTK_RGMII) 631 632 #define MTK_GMAC1_TRGMII \ 633 (MTK_PATH_BIT(MTK_ETH_PATH_GMAC1_TRGMII) | MTK_TRGMII) 634 635 #define MTK_GMAC1_SGMII \ 636 (MTK_PATH_BIT(MTK_ETH_PATH_GMAC1_SGMII) | MTK_SGMII) 637 638 #define MTK_GMAC2_RGMII \ 639 (MTK_PATH_BIT(MTK_ETH_PATH_GMAC2_RGMII) | MTK_RGMII) 640 641 #define MTK_GMAC2_SGMII \ 642 (MTK_PATH_BIT(MTK_ETH_PATH_GMAC2_SGMII) | MTK_SGMII) 643 644 #define MTK_GMAC2_GEPHY \ 645 (MTK_PATH_BIT(MTK_ETH_PATH_GMAC2_GEPHY) | MTK_GEPHY) 646 647 #define MTK_GDM1_ESW \ 648 (MTK_PATH_BIT(MTK_ETH_PATH_GDM1_ESW) | MTK_ESW) 649 650 #define MTK_MUX_BIT(x) BIT((x) + 20) 651 652 /* MUXes present on SoCs */ 653 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 654 #define MTK_MUX_GDM1_TO_GMAC1_ESW \ 655 (MTK_MUX_BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW) | MTK_MUX) 656 657 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 658 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 659 (MTK_MUX_BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY) | MTK_MUX | MTK_INFRA) 660 661 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 662 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 663 (MTK_MUX_BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY) | MTK_MUX | MTK_INFRA) 664 665 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 666 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 667 (MTK_MUX_BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII) | MTK_MUX | \ 668 MTK_SHARED_SGMII) 669 670 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 671 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 672 (MTK_MUX_BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII) | MTK_MUX) 673 674 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 675 676 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 677 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 678 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 679 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII) 680 681 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII) 682 683 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 684 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 685 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 686 MTK_MUX_U3_GMAC2_TO_QPHY | \ 687 MTK_MUX_GMAC12_TO_GEPHY_SGMII) 688 689 /* struct mtk_eth_data - This is the structure holding all differences 690 * among various plaforms 691 * @ana_rgc3: The offset for register ANA_RGC3 related to 692 * sgmiisys syscon 693 * @caps Flags shown the extra capability for the SoC 694 * @required_clks Flags shown the bitmap for required clocks on 695 * the target SoC 696 * @required_pctl A bool value to show whether the SoC requires 697 * the extra setup for those pins used by GMAC. 698 */ 699 struct mtk_soc_data { 700 u32 ana_rgc3; 701 u32 caps; 702 u32 required_clks; 703 bool required_pctl; 704 }; 705 706 /* currently no SoC has more than 2 macs */ 707 #define MTK_MAX_DEVS 2 708 709 #define MTK_SGMII_PHYSPEED_AN BIT(31) 710 #define MTK_SGMII_PHYSPEED_MASK GENMASK(0, 2) 711 #define MTK_SGMII_PHYSPEED_1000 BIT(0) 712 #define MTK_SGMII_PHYSPEED_2500 BIT(1) 713 #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) 714 715 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 716 * characteristics 717 * @regmap: The register map pointing at the range used to setup 718 * SGMII modes 719 * @flags: The enum refers to which mode the sgmii wants to run on 720 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 721 */ 722 723 struct mtk_sgmii { 724 struct regmap *regmap[MTK_MAX_DEVS]; 725 u32 flags[MTK_MAX_DEVS]; 726 u32 ana_rgc3; 727 }; 728 729 /* struct mtk_eth - This is the main datasructure for holding the state 730 * of the driver 731 * @dev: The device pointer 732 * @base: The mapped register i/o base 733 * @page_lock: Make sure that register operations are atomic 734 * @tx_irq__lock: Make sure that IRQ register operations are atomic 735 * @rx_irq__lock: Make sure that IRQ register operations are atomic 736 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 737 * dummy for NAPI to work 738 * @netdev: The netdev instances 739 * @mac: Each netdev is linked to a physical MAC 740 * @irq: The IRQ that we are using 741 * @msg_enable: Ethtool msg level 742 * @ethsys: The register map pointing at the range used to setup 743 * MII modes 744 * @infra: The register map pointing at the range used to setup 745 * SGMII and GePHY path 746 * @pctl: The register map pointing at the range used to setup 747 * GMAC port drive/slew values 748 * @dma_refcnt: track how many netdevs are using the DMA engine 749 * @tx_ring: Pointer to the memory holding info about the TX ring 750 * @rx_ring: Pointer to the memory holding info about the RX ring 751 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 752 * @tx_napi: The TX NAPI struct 753 * @rx_napi: The RX NAPI struct 754 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 755 * @phy_scratch_ring: physical address of scratch_ring 756 * @scratch_head: The scratch memory that scratch_ring points to. 757 * @clks: clock array for all clocks required 758 * @mii_bus: If there is a bus we need to create an instance for it 759 * @pending_work: The workqueue used to reset the dma ring 760 * @state: Initialization and runtime state of the device 761 * @soc: Holding specific data among vaious SoCs 762 */ 763 764 struct mtk_eth { 765 struct device *dev; 766 void __iomem *base; 767 spinlock_t page_lock; 768 spinlock_t tx_irq_lock; 769 spinlock_t rx_irq_lock; 770 struct net_device dummy_dev; 771 struct net_device *netdev[MTK_MAX_DEVS]; 772 struct mtk_mac *mac[MTK_MAX_DEVS]; 773 int irq[3]; 774 u32 msg_enable; 775 unsigned long sysclk; 776 struct regmap *ethsys; 777 struct regmap *infra; 778 struct mtk_sgmii *sgmii; 779 struct regmap *pctl; 780 bool hwlro; 781 refcount_t dma_refcnt; 782 struct mtk_tx_ring tx_ring; 783 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 784 struct mtk_rx_ring rx_ring_qdma; 785 struct napi_struct tx_napi; 786 struct napi_struct rx_napi; 787 struct mtk_tx_dma *scratch_ring; 788 dma_addr_t phy_scratch_ring; 789 void *scratch_head; 790 struct clk *clks[MTK_CLK_MAX]; 791 792 struct mii_bus *mii_bus; 793 struct work_struct pending_work; 794 unsigned long state; 795 796 const struct mtk_soc_data *soc; 797 }; 798 799 /* struct mtk_mac - the structure that holds the info about the MACs of the 800 * SoC 801 * @id: The number of the MAC 802 * @ge_mode: Interface mode kept for setup restoring 803 * @of_node: Our devicetree node 804 * @hw: Backpointer to our main datastruture 805 * @hw_stats: Packet statistics counter 806 * @trgmii Indicate if the MAC uses TRGMII connected to internal 807 switch 808 */ 809 struct mtk_mac { 810 int id; 811 int ge_mode; 812 struct device_node *of_node; 813 struct mtk_eth *hw; 814 struct mtk_hw_stats *hw_stats; 815 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 816 int hwlro_ip_cnt; 817 bool trgmii; 818 }; 819 820 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 821 extern const struct of_device_id of_mtk_match[]; 822 823 /* read the hardware status register */ 824 void mtk_stats_update_mac(struct mtk_mac *mac); 825 826 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 827 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 828 829 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 830 u32 ana_rgc3); 831 int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); 832 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id); 833 int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode); 834 835 #endif /* MTK_ETH_H */ 836