1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/regmap.h> 14 #include <linux/clk.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/if_vlan.h> 17 #include <linux/reset.h> 18 #include <linux/tcp.h> 19 #include <linux/interrupt.h> 20 #include <linux/pinctrl/devinfo.h> 21 22 #include "mtk_eth_soc.h" 23 24 static int mtk_msg_level = -1; 25 module_param_named(msg_level, mtk_msg_level, int, 0); 26 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 27 28 #define MTK_ETHTOOL_STAT(x) { #x, \ 29 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 30 31 /* strings used by ethtool */ 32 static const struct mtk_ethtool_stats { 33 char str[ETH_GSTRING_LEN]; 34 u32 offset; 35 } mtk_ethtool_stats[] = { 36 MTK_ETHTOOL_STAT(tx_bytes), 37 MTK_ETHTOOL_STAT(tx_packets), 38 MTK_ETHTOOL_STAT(tx_skip), 39 MTK_ETHTOOL_STAT(tx_collisions), 40 MTK_ETHTOOL_STAT(rx_bytes), 41 MTK_ETHTOOL_STAT(rx_packets), 42 MTK_ETHTOOL_STAT(rx_overflow), 43 MTK_ETHTOOL_STAT(rx_fcs_errors), 44 MTK_ETHTOOL_STAT(rx_short_errors), 45 MTK_ETHTOOL_STAT(rx_long_errors), 46 MTK_ETHTOOL_STAT(rx_checksum_errors), 47 MTK_ETHTOOL_STAT(rx_flow_control_packets), 48 }; 49 50 static const char * const mtk_clks_source_name[] = { 51 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 52 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 53 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 54 "sgmii_ck", "eth2pll", 55 }; 56 57 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 58 { 59 __raw_writel(val, eth->base + reg); 60 } 61 62 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 63 { 64 return __raw_readl(eth->base + reg); 65 } 66 67 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 68 { 69 unsigned long t_start = jiffies; 70 71 while (1) { 72 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 73 return 0; 74 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 75 break; 76 usleep_range(10, 20); 77 } 78 79 dev_err(eth->dev, "mdio: MDIO timeout\n"); 80 return -1; 81 } 82 83 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 84 u32 phy_register, u32 write_data) 85 { 86 if (mtk_mdio_busy_wait(eth)) 87 return -1; 88 89 write_data &= 0xffff; 90 91 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 92 (phy_register << PHY_IAC_REG_SHIFT) | 93 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 94 MTK_PHY_IAC); 95 96 if (mtk_mdio_busy_wait(eth)) 97 return -1; 98 99 return 0; 100 } 101 102 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 103 { 104 u32 d; 105 106 if (mtk_mdio_busy_wait(eth)) 107 return 0xffff; 108 109 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 110 (phy_reg << PHY_IAC_REG_SHIFT) | 111 (phy_addr << PHY_IAC_ADDR_SHIFT), 112 MTK_PHY_IAC); 113 114 if (mtk_mdio_busy_wait(eth)) 115 return 0xffff; 116 117 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 118 119 return d; 120 } 121 122 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 123 int phy_reg, u16 val) 124 { 125 struct mtk_eth *eth = bus->priv; 126 127 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 128 } 129 130 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 131 { 132 struct mtk_eth *eth = bus->priv; 133 134 return _mtk_mdio_read(eth, phy_addr, phy_reg); 135 } 136 137 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 138 phy_interface_t interface) 139 { 140 u32 val; 141 142 /* Check DDR memory type. Currently DDR2 is not supported. */ 143 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 144 if (val & SYSCFG_DRAM_TYPE_DDR2) { 145 dev_err(eth->dev, 146 "TRGMII mode with DDR2 memory is not supported!\n"); 147 return -EOPNOTSUPP; 148 } 149 150 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 151 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 152 153 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 154 ETHSYS_TRGMII_MT7621_MASK, val); 155 156 return 0; 157 } 158 159 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 160 { 161 u32 val; 162 int ret; 163 164 val = (speed == SPEED_1000) ? 165 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 166 mtk_w32(eth, val, INTF_MODE); 167 168 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 169 ETHSYS_TRGMII_CLK_SEL362_5, 170 ETHSYS_TRGMII_CLK_SEL362_5); 171 172 val = (speed == SPEED_1000) ? 250000000 : 500000000; 173 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 174 if (ret) 175 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 176 177 val = (speed == SPEED_1000) ? 178 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 179 mtk_w32(eth, val, TRGMII_RCK_CTRL); 180 181 val = (speed == SPEED_1000) ? 182 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 183 mtk_w32(eth, val, TRGMII_TCK_CTRL); 184 } 185 186 static void mtk_phy_link_adjust(struct net_device *dev) 187 { 188 struct mtk_mac *mac = netdev_priv(dev); 189 u16 lcl_adv = 0, rmt_adv = 0; 190 u8 flowctrl; 191 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 192 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 193 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 194 MAC_MCR_BACKPR_EN; 195 196 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 197 return; 198 199 switch (dev->phydev->speed) { 200 case SPEED_1000: 201 mcr |= MAC_MCR_SPEED_1000; 202 break; 203 case SPEED_100: 204 mcr |= MAC_MCR_SPEED_100; 205 break; 206 } 207 208 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && !mac->id) { 209 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 210 if (mt7621_gmac0_rgmii_adjust(mac->hw, 211 dev->phydev->interface)) 212 return; 213 } else { 214 if (!mac->trgmii) 215 mtk_gmac0_rgmii_adjust(mac->hw, 216 dev->phydev->speed); 217 } 218 } 219 220 if (dev->phydev->link) 221 mcr |= MAC_MCR_FORCE_LINK; 222 223 if (dev->phydev->duplex) { 224 mcr |= MAC_MCR_FORCE_DPX; 225 226 if (dev->phydev->pause) 227 rmt_adv = LPA_PAUSE_CAP; 228 if (dev->phydev->asym_pause) 229 rmt_adv |= LPA_PAUSE_ASYM; 230 231 lcl_adv = linkmode_adv_to_lcl_adv_t(dev->phydev->advertising); 232 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 233 234 if (flowctrl & FLOW_CTRL_TX) 235 mcr |= MAC_MCR_FORCE_TX_FC; 236 if (flowctrl & FLOW_CTRL_RX) 237 mcr |= MAC_MCR_FORCE_RX_FC; 238 239 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 240 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 241 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 242 } 243 244 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 245 246 if (!of_phy_is_fixed_link(mac->of_node)) 247 phy_print_status(dev->phydev); 248 } 249 250 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 251 struct device_node *phy_node) 252 { 253 struct phy_device *phydev; 254 int phy_mode; 255 256 phy_mode = of_get_phy_mode(phy_node); 257 if (phy_mode < 0) { 258 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 259 return -EINVAL; 260 } 261 262 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 263 mtk_phy_link_adjust, 0, phy_mode); 264 if (!phydev) { 265 dev_err(eth->dev, "could not connect to PHY\n"); 266 return -ENODEV; 267 } 268 269 dev_info(eth->dev, 270 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 271 mac->id, phydev_name(phydev), phydev->phy_id, 272 phydev->drv->name); 273 274 return 0; 275 } 276 277 static int mtk_phy_connect(struct net_device *dev) 278 { 279 struct mtk_mac *mac = netdev_priv(dev); 280 struct mtk_eth *eth; 281 struct device_node *np; 282 u32 val; 283 int err; 284 285 eth = mac->hw; 286 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 287 if (!np && of_phy_is_fixed_link(mac->of_node)) 288 if (!of_phy_register_fixed_link(mac->of_node)) 289 np = of_node_get(mac->of_node); 290 if (!np) 291 return -ENODEV; 292 293 err = mtk_setup_hw_path(eth, mac->id, of_get_phy_mode(np)); 294 if (err) 295 goto err_phy; 296 297 mac->ge_mode = 0; 298 switch (of_get_phy_mode(np)) { 299 case PHY_INTERFACE_MODE_TRGMII: 300 mac->trgmii = true; 301 case PHY_INTERFACE_MODE_RGMII_TXID: 302 case PHY_INTERFACE_MODE_RGMII_RXID: 303 case PHY_INTERFACE_MODE_RGMII_ID: 304 case PHY_INTERFACE_MODE_RGMII: 305 case PHY_INTERFACE_MODE_SGMII: 306 break; 307 case PHY_INTERFACE_MODE_MII: 308 case PHY_INTERFACE_MODE_GMII: 309 mac->ge_mode = 1; 310 break; 311 case PHY_INTERFACE_MODE_REVMII: 312 mac->ge_mode = 2; 313 break; 314 case PHY_INTERFACE_MODE_RMII: 315 if (!mac->id) 316 goto err_phy; 317 mac->ge_mode = 3; 318 break; 319 default: 320 goto err_phy; 321 } 322 323 /* put the gmac into the right mode */ 324 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 325 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 326 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); 327 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 328 329 /* couple phydev to net_device */ 330 if (mtk_phy_connect_node(eth, mac, np)) 331 goto err_phy; 332 333 of_node_put(np); 334 335 return 0; 336 337 err_phy: 338 if (of_phy_is_fixed_link(mac->of_node)) 339 of_phy_deregister_fixed_link(mac->of_node); 340 of_node_put(np); 341 dev_err(eth->dev, "%s: invalid phy\n", __func__); 342 return -EINVAL; 343 } 344 345 static int mtk_mdio_init(struct mtk_eth *eth) 346 { 347 struct device_node *mii_np; 348 int ret; 349 350 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 351 if (!mii_np) { 352 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 353 return -ENODEV; 354 } 355 356 if (!of_device_is_available(mii_np)) { 357 ret = -ENODEV; 358 goto err_put_node; 359 } 360 361 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 362 if (!eth->mii_bus) { 363 ret = -ENOMEM; 364 goto err_put_node; 365 } 366 367 eth->mii_bus->name = "mdio"; 368 eth->mii_bus->read = mtk_mdio_read; 369 eth->mii_bus->write = mtk_mdio_write; 370 eth->mii_bus->priv = eth; 371 eth->mii_bus->parent = eth->dev; 372 373 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 374 ret = of_mdiobus_register(eth->mii_bus, mii_np); 375 376 err_put_node: 377 of_node_put(mii_np); 378 return ret; 379 } 380 381 static void mtk_mdio_cleanup(struct mtk_eth *eth) 382 { 383 if (!eth->mii_bus) 384 return; 385 386 mdiobus_unregister(eth->mii_bus); 387 } 388 389 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 390 { 391 unsigned long flags; 392 u32 val; 393 394 spin_lock_irqsave(ð->tx_irq_lock, flags); 395 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 396 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 397 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 398 } 399 400 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 401 { 402 unsigned long flags; 403 u32 val; 404 405 spin_lock_irqsave(ð->tx_irq_lock, flags); 406 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 407 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 408 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 409 } 410 411 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 412 { 413 unsigned long flags; 414 u32 val; 415 416 spin_lock_irqsave(ð->rx_irq_lock, flags); 417 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 418 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 419 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 420 } 421 422 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 423 { 424 unsigned long flags; 425 u32 val; 426 427 spin_lock_irqsave(ð->rx_irq_lock, flags); 428 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 429 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 430 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 431 } 432 433 static int mtk_set_mac_address(struct net_device *dev, void *p) 434 { 435 int ret = eth_mac_addr(dev, p); 436 struct mtk_mac *mac = netdev_priv(dev); 437 const char *macaddr = dev->dev_addr; 438 439 if (ret) 440 return ret; 441 442 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 443 return -EBUSY; 444 445 spin_lock_bh(&mac->hw->page_lock); 446 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 447 MTK_GDMA_MAC_ADRH(mac->id)); 448 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 449 (macaddr[4] << 8) | macaddr[5], 450 MTK_GDMA_MAC_ADRL(mac->id)); 451 spin_unlock_bh(&mac->hw->page_lock); 452 453 return 0; 454 } 455 456 void mtk_stats_update_mac(struct mtk_mac *mac) 457 { 458 struct mtk_hw_stats *hw_stats = mac->hw_stats; 459 unsigned int base = MTK_GDM1_TX_GBCNT; 460 u64 stats; 461 462 base += hw_stats->reg_offset; 463 464 u64_stats_update_begin(&hw_stats->syncp); 465 466 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 467 stats = mtk_r32(mac->hw, base + 0x04); 468 if (stats) 469 hw_stats->rx_bytes += (stats << 32); 470 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 471 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 472 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 473 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 474 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 475 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 476 hw_stats->rx_flow_control_packets += 477 mtk_r32(mac->hw, base + 0x24); 478 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 479 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 480 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 481 stats = mtk_r32(mac->hw, base + 0x34); 482 if (stats) 483 hw_stats->tx_bytes += (stats << 32); 484 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 485 u64_stats_update_end(&hw_stats->syncp); 486 } 487 488 static void mtk_stats_update(struct mtk_eth *eth) 489 { 490 int i; 491 492 for (i = 0; i < MTK_MAC_COUNT; i++) { 493 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 494 continue; 495 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 496 mtk_stats_update_mac(eth->mac[i]); 497 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 498 } 499 } 500 } 501 502 static void mtk_get_stats64(struct net_device *dev, 503 struct rtnl_link_stats64 *storage) 504 { 505 struct mtk_mac *mac = netdev_priv(dev); 506 struct mtk_hw_stats *hw_stats = mac->hw_stats; 507 unsigned int start; 508 509 if (netif_running(dev) && netif_device_present(dev)) { 510 if (spin_trylock_bh(&hw_stats->stats_lock)) { 511 mtk_stats_update_mac(mac); 512 spin_unlock_bh(&hw_stats->stats_lock); 513 } 514 } 515 516 do { 517 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 518 storage->rx_packets = hw_stats->rx_packets; 519 storage->tx_packets = hw_stats->tx_packets; 520 storage->rx_bytes = hw_stats->rx_bytes; 521 storage->tx_bytes = hw_stats->tx_bytes; 522 storage->collisions = hw_stats->tx_collisions; 523 storage->rx_length_errors = hw_stats->rx_short_errors + 524 hw_stats->rx_long_errors; 525 storage->rx_over_errors = hw_stats->rx_overflow; 526 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 527 storage->rx_errors = hw_stats->rx_checksum_errors; 528 storage->tx_aborted_errors = hw_stats->tx_skip; 529 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 530 531 storage->tx_errors = dev->stats.tx_errors; 532 storage->rx_dropped = dev->stats.rx_dropped; 533 storage->tx_dropped = dev->stats.tx_dropped; 534 } 535 536 static inline int mtk_max_frag_size(int mtu) 537 { 538 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 539 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 540 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 541 542 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 543 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 544 } 545 546 static inline int mtk_max_buf_size(int frag_size) 547 { 548 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 549 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 550 551 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 552 553 return buf_size; 554 } 555 556 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 557 struct mtk_rx_dma *dma_rxd) 558 { 559 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 560 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 561 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 562 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 563 } 564 565 /* the qdma core needs scratch memory to be setup */ 566 static int mtk_init_fq_dma(struct mtk_eth *eth) 567 { 568 dma_addr_t phy_ring_tail; 569 int cnt = MTK_DMA_SIZE; 570 dma_addr_t dma_addr; 571 int i; 572 573 eth->scratch_ring = dma_alloc_coherent(eth->dev, 574 cnt * sizeof(struct mtk_tx_dma), 575 ð->phy_scratch_ring, 576 GFP_ATOMIC); 577 if (unlikely(!eth->scratch_ring)) 578 return -ENOMEM; 579 580 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 581 GFP_KERNEL); 582 if (unlikely(!eth->scratch_head)) 583 return -ENOMEM; 584 585 dma_addr = dma_map_single(eth->dev, 586 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 587 DMA_FROM_DEVICE); 588 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 589 return -ENOMEM; 590 591 phy_ring_tail = eth->phy_scratch_ring + 592 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 593 594 for (i = 0; i < cnt; i++) { 595 eth->scratch_ring[i].txd1 = 596 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 597 if (i < cnt - 1) 598 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 599 ((i + 1) * sizeof(struct mtk_tx_dma))); 600 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 601 } 602 603 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 604 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 605 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 606 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 607 608 return 0; 609 } 610 611 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 612 { 613 void *ret = ring->dma; 614 615 return ret + (desc - ring->phys); 616 } 617 618 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 619 struct mtk_tx_dma *txd) 620 { 621 int idx = txd - ring->dma; 622 623 return &ring->buf[idx]; 624 } 625 626 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 627 { 628 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 629 dma_unmap_single(eth->dev, 630 dma_unmap_addr(tx_buf, dma_addr0), 631 dma_unmap_len(tx_buf, dma_len0), 632 DMA_TO_DEVICE); 633 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 634 dma_unmap_page(eth->dev, 635 dma_unmap_addr(tx_buf, dma_addr0), 636 dma_unmap_len(tx_buf, dma_len0), 637 DMA_TO_DEVICE); 638 } 639 tx_buf->flags = 0; 640 if (tx_buf->skb && 641 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 642 dev_kfree_skb_any(tx_buf->skb); 643 tx_buf->skb = NULL; 644 } 645 646 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 647 int tx_num, struct mtk_tx_ring *ring, bool gso) 648 { 649 struct mtk_mac *mac = netdev_priv(dev); 650 struct mtk_eth *eth = mac->hw; 651 struct mtk_tx_dma *itxd, *txd; 652 struct mtk_tx_buf *itx_buf, *tx_buf; 653 dma_addr_t mapped_addr; 654 unsigned int nr_frags; 655 int i, n_desc = 1; 656 u32 txd4 = 0, fport; 657 658 itxd = ring->next_free; 659 if (itxd == ring->last_free) 660 return -ENOMEM; 661 662 /* set the forward port */ 663 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 664 txd4 |= fport; 665 666 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 667 memset(itx_buf, 0, sizeof(*itx_buf)); 668 669 if (gso) 670 txd4 |= TX_DMA_TSO; 671 672 /* TX Checksum offload */ 673 if (skb->ip_summed == CHECKSUM_PARTIAL) 674 txd4 |= TX_DMA_CHKSUM; 675 676 /* VLAN header offload */ 677 if (skb_vlan_tag_present(skb)) 678 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 679 680 mapped_addr = dma_map_single(eth->dev, skb->data, 681 skb_headlen(skb), DMA_TO_DEVICE); 682 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 683 return -ENOMEM; 684 685 WRITE_ONCE(itxd->txd1, mapped_addr); 686 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 687 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 688 MTK_TX_FLAGS_FPORT1; 689 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr); 690 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb)); 691 692 /* TX SG offload */ 693 txd = itxd; 694 nr_frags = skb_shinfo(skb)->nr_frags; 695 for (i = 0; i < nr_frags; i++) { 696 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 697 unsigned int offset = 0; 698 int frag_size = skb_frag_size(frag); 699 700 while (frag_size) { 701 bool last_frag = false; 702 unsigned int frag_map_size; 703 704 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 705 if (txd == ring->last_free) 706 goto err_dma; 707 708 n_desc++; 709 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 710 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 711 frag_map_size, 712 DMA_TO_DEVICE); 713 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 714 goto err_dma; 715 716 if (i == nr_frags - 1 && 717 (frag_size - frag_map_size) == 0) 718 last_frag = true; 719 720 WRITE_ONCE(txd->txd1, mapped_addr); 721 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 722 TX_DMA_PLEN0(frag_map_size) | 723 last_frag * TX_DMA_LS0)); 724 WRITE_ONCE(txd->txd4, fport); 725 726 tx_buf = mtk_desc_to_tx_buf(ring, txd); 727 memset(tx_buf, 0, sizeof(*tx_buf)); 728 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 729 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 730 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 731 MTK_TX_FLAGS_FPORT1; 732 733 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 734 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 735 frag_size -= frag_map_size; 736 offset += frag_map_size; 737 } 738 } 739 740 /* store skb to cleanup */ 741 itx_buf->skb = skb; 742 743 WRITE_ONCE(itxd->txd4, txd4); 744 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 745 (!nr_frags * TX_DMA_LS0))); 746 747 netdev_sent_queue(dev, skb->len); 748 skb_tx_timestamp(skb); 749 750 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 751 atomic_sub(n_desc, &ring->free_count); 752 753 /* make sure that all changes to the dma ring are flushed before we 754 * continue 755 */ 756 wmb(); 757 758 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 759 !netdev_xmit_more()) 760 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 761 762 return 0; 763 764 err_dma: 765 do { 766 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 767 768 /* unmap dma */ 769 mtk_tx_unmap(eth, tx_buf); 770 771 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 772 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 773 } while (itxd != txd); 774 775 return -ENOMEM; 776 } 777 778 static inline int mtk_cal_txd_req(struct sk_buff *skb) 779 { 780 int i, nfrags; 781 struct skb_frag_struct *frag; 782 783 nfrags = 1; 784 if (skb_is_gso(skb)) { 785 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 786 frag = &skb_shinfo(skb)->frags[i]; 787 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 788 } 789 } else { 790 nfrags += skb_shinfo(skb)->nr_frags; 791 } 792 793 return nfrags; 794 } 795 796 static int mtk_queue_stopped(struct mtk_eth *eth) 797 { 798 int i; 799 800 for (i = 0; i < MTK_MAC_COUNT; i++) { 801 if (!eth->netdev[i]) 802 continue; 803 if (netif_queue_stopped(eth->netdev[i])) 804 return 1; 805 } 806 807 return 0; 808 } 809 810 static void mtk_wake_queue(struct mtk_eth *eth) 811 { 812 int i; 813 814 for (i = 0; i < MTK_MAC_COUNT; i++) { 815 if (!eth->netdev[i]) 816 continue; 817 netif_wake_queue(eth->netdev[i]); 818 } 819 } 820 821 static void mtk_stop_queue(struct mtk_eth *eth) 822 { 823 int i; 824 825 for (i = 0; i < MTK_MAC_COUNT; i++) { 826 if (!eth->netdev[i]) 827 continue; 828 netif_stop_queue(eth->netdev[i]); 829 } 830 } 831 832 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 833 { 834 struct mtk_mac *mac = netdev_priv(dev); 835 struct mtk_eth *eth = mac->hw; 836 struct mtk_tx_ring *ring = ð->tx_ring; 837 struct net_device_stats *stats = &dev->stats; 838 bool gso = false; 839 int tx_num; 840 841 /* normally we can rely on the stack not calling this more than once, 842 * however we have 2 queues running on the same ring so we need to lock 843 * the ring access 844 */ 845 spin_lock(ð->page_lock); 846 847 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 848 goto drop; 849 850 tx_num = mtk_cal_txd_req(skb); 851 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 852 mtk_stop_queue(eth); 853 netif_err(eth, tx_queued, dev, 854 "Tx Ring full when queue awake!\n"); 855 spin_unlock(ð->page_lock); 856 return NETDEV_TX_BUSY; 857 } 858 859 /* TSO: fill MSS info in tcp checksum field */ 860 if (skb_is_gso(skb)) { 861 if (skb_cow_head(skb, 0)) { 862 netif_warn(eth, tx_err, dev, 863 "GSO expand head fail.\n"); 864 goto drop; 865 } 866 867 if (skb_shinfo(skb)->gso_type & 868 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 869 gso = true; 870 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 871 } 872 } 873 874 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 875 goto drop; 876 877 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 878 mtk_stop_queue(eth); 879 880 spin_unlock(ð->page_lock); 881 882 return NETDEV_TX_OK; 883 884 drop: 885 spin_unlock(ð->page_lock); 886 stats->tx_dropped++; 887 dev_kfree_skb_any(skb); 888 return NETDEV_TX_OK; 889 } 890 891 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 892 { 893 int i; 894 struct mtk_rx_ring *ring; 895 int idx; 896 897 if (!eth->hwlro) 898 return ð->rx_ring[0]; 899 900 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 901 ring = ð->rx_ring[i]; 902 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 903 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 904 ring->calc_idx_update = true; 905 return ring; 906 } 907 } 908 909 return NULL; 910 } 911 912 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 913 { 914 struct mtk_rx_ring *ring; 915 int i; 916 917 if (!eth->hwlro) { 918 ring = ð->rx_ring[0]; 919 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 920 } else { 921 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 922 ring = ð->rx_ring[i]; 923 if (ring->calc_idx_update) { 924 ring->calc_idx_update = false; 925 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 926 } 927 } 928 } 929 } 930 931 static int mtk_poll_rx(struct napi_struct *napi, int budget, 932 struct mtk_eth *eth) 933 { 934 struct mtk_rx_ring *ring; 935 int idx; 936 struct sk_buff *skb; 937 u8 *data, *new_data; 938 struct mtk_rx_dma *rxd, trxd; 939 int done = 0; 940 941 while (done < budget) { 942 struct net_device *netdev; 943 unsigned int pktlen; 944 dma_addr_t dma_addr; 945 int mac = 0; 946 947 ring = mtk_get_rx_ring(eth); 948 if (unlikely(!ring)) 949 goto rx_done; 950 951 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 952 rxd = &ring->dma[idx]; 953 data = ring->data[idx]; 954 955 mtk_rx_get_desc(&trxd, rxd); 956 if (!(trxd.rxd2 & RX_DMA_DONE)) 957 break; 958 959 /* find out which mac the packet come from. values start at 1 */ 960 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 961 RX_DMA_FPORT_MASK; 962 mac--; 963 964 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 965 !eth->netdev[mac])) 966 goto release_desc; 967 968 netdev = eth->netdev[mac]; 969 970 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 971 goto release_desc; 972 973 /* alloc new buffer */ 974 new_data = napi_alloc_frag(ring->frag_size); 975 if (unlikely(!new_data)) { 976 netdev->stats.rx_dropped++; 977 goto release_desc; 978 } 979 dma_addr = dma_map_single(eth->dev, 980 new_data + NET_SKB_PAD, 981 ring->buf_size, 982 DMA_FROM_DEVICE); 983 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 984 skb_free_frag(new_data); 985 netdev->stats.rx_dropped++; 986 goto release_desc; 987 } 988 989 /* receive data */ 990 skb = build_skb(data, ring->frag_size); 991 if (unlikely(!skb)) { 992 skb_free_frag(new_data); 993 netdev->stats.rx_dropped++; 994 goto release_desc; 995 } 996 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 997 998 dma_unmap_single(eth->dev, trxd.rxd1, 999 ring->buf_size, DMA_FROM_DEVICE); 1000 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1001 skb->dev = netdev; 1002 skb_put(skb, pktlen); 1003 if (trxd.rxd4 & RX_DMA_L4_VALID) 1004 skb->ip_summed = CHECKSUM_UNNECESSARY; 1005 else 1006 skb_checksum_none_assert(skb); 1007 skb->protocol = eth_type_trans(skb, netdev); 1008 1009 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1010 RX_DMA_VID(trxd.rxd3)) 1011 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1012 RX_DMA_VID(trxd.rxd3)); 1013 skb_record_rx_queue(skb, 0); 1014 napi_gro_receive(napi, skb); 1015 1016 ring->data[idx] = new_data; 1017 rxd->rxd1 = (unsigned int)dma_addr; 1018 1019 release_desc: 1020 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1021 1022 ring->calc_idx = idx; 1023 1024 done++; 1025 } 1026 1027 rx_done: 1028 if (done) { 1029 /* make sure that all changes to the dma ring are flushed before 1030 * we continue 1031 */ 1032 wmb(); 1033 mtk_update_rx_cpu_idx(eth); 1034 } 1035 1036 return done; 1037 } 1038 1039 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1040 { 1041 struct mtk_tx_ring *ring = ð->tx_ring; 1042 struct mtk_tx_dma *desc; 1043 struct sk_buff *skb; 1044 struct mtk_tx_buf *tx_buf; 1045 unsigned int done[MTK_MAX_DEVS]; 1046 unsigned int bytes[MTK_MAX_DEVS]; 1047 u32 cpu, dma; 1048 int total = 0, i; 1049 1050 memset(done, 0, sizeof(done)); 1051 memset(bytes, 0, sizeof(bytes)); 1052 1053 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1054 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1055 1056 desc = mtk_qdma_phys_to_virt(ring, cpu); 1057 1058 while ((cpu != dma) && budget) { 1059 u32 next_cpu = desc->txd2; 1060 int mac = 0; 1061 1062 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1063 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1064 break; 1065 1066 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1067 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1068 mac = 1; 1069 1070 skb = tx_buf->skb; 1071 if (!skb) 1072 break; 1073 1074 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1075 bytes[mac] += skb->len; 1076 done[mac]++; 1077 budget--; 1078 } 1079 mtk_tx_unmap(eth, tx_buf); 1080 1081 ring->last_free = desc; 1082 atomic_inc(&ring->free_count); 1083 1084 cpu = next_cpu; 1085 } 1086 1087 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1088 1089 for (i = 0; i < MTK_MAC_COUNT; i++) { 1090 if (!eth->netdev[i] || !done[i]) 1091 continue; 1092 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1093 total += done[i]; 1094 } 1095 1096 if (mtk_queue_stopped(eth) && 1097 (atomic_read(&ring->free_count) > ring->thresh)) 1098 mtk_wake_queue(eth); 1099 1100 return total; 1101 } 1102 1103 static void mtk_handle_status_irq(struct mtk_eth *eth) 1104 { 1105 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1106 1107 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1108 mtk_stats_update(eth); 1109 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1110 MTK_INT_STATUS2); 1111 } 1112 } 1113 1114 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1115 { 1116 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1117 u32 status, mask; 1118 int tx_done = 0; 1119 1120 mtk_handle_status_irq(eth); 1121 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 1122 tx_done = mtk_poll_tx(eth, budget); 1123 1124 if (unlikely(netif_msg_intr(eth))) { 1125 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1126 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1127 dev_info(eth->dev, 1128 "done tx %d, intr 0x%08x/0x%x\n", 1129 tx_done, status, mask); 1130 } 1131 1132 if (tx_done == budget) 1133 return budget; 1134 1135 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1136 if (status & MTK_TX_DONE_INT) 1137 return budget; 1138 1139 napi_complete(napi); 1140 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1141 1142 return tx_done; 1143 } 1144 1145 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1146 { 1147 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1148 u32 status, mask; 1149 int rx_done = 0; 1150 int remain_budget = budget; 1151 1152 mtk_handle_status_irq(eth); 1153 1154 poll_again: 1155 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1156 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1157 1158 if (unlikely(netif_msg_intr(eth))) { 1159 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1160 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1161 dev_info(eth->dev, 1162 "done rx %d, intr 0x%08x/0x%x\n", 1163 rx_done, status, mask); 1164 } 1165 if (rx_done == remain_budget) 1166 return budget; 1167 1168 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1169 if (status & MTK_RX_DONE_INT) { 1170 remain_budget -= rx_done; 1171 goto poll_again; 1172 } 1173 napi_complete(napi); 1174 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1175 1176 return rx_done + budget - remain_budget; 1177 } 1178 1179 static int mtk_tx_alloc(struct mtk_eth *eth) 1180 { 1181 struct mtk_tx_ring *ring = ð->tx_ring; 1182 int i, sz = sizeof(*ring->dma); 1183 1184 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1185 GFP_KERNEL); 1186 if (!ring->buf) 1187 goto no_tx_mem; 1188 1189 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1190 &ring->phys, GFP_ATOMIC); 1191 if (!ring->dma) 1192 goto no_tx_mem; 1193 1194 for (i = 0; i < MTK_DMA_SIZE; i++) { 1195 int next = (i + 1) % MTK_DMA_SIZE; 1196 u32 next_ptr = ring->phys + next * sz; 1197 1198 ring->dma[i].txd2 = next_ptr; 1199 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1200 } 1201 1202 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1203 ring->next_free = &ring->dma[0]; 1204 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1205 ring->thresh = MAX_SKB_FRAGS; 1206 1207 /* make sure that all changes to the dma ring are flushed before we 1208 * continue 1209 */ 1210 wmb(); 1211 1212 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1213 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1214 mtk_w32(eth, 1215 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1216 MTK_QTX_CRX_PTR); 1217 mtk_w32(eth, 1218 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1219 MTK_QTX_DRX_PTR); 1220 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1221 1222 return 0; 1223 1224 no_tx_mem: 1225 return -ENOMEM; 1226 } 1227 1228 static void mtk_tx_clean(struct mtk_eth *eth) 1229 { 1230 struct mtk_tx_ring *ring = ð->tx_ring; 1231 int i; 1232 1233 if (ring->buf) { 1234 for (i = 0; i < MTK_DMA_SIZE; i++) 1235 mtk_tx_unmap(eth, &ring->buf[i]); 1236 kfree(ring->buf); 1237 ring->buf = NULL; 1238 } 1239 1240 if (ring->dma) { 1241 dma_free_coherent(eth->dev, 1242 MTK_DMA_SIZE * sizeof(*ring->dma), 1243 ring->dma, 1244 ring->phys); 1245 ring->dma = NULL; 1246 } 1247 } 1248 1249 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1250 { 1251 struct mtk_rx_ring *ring; 1252 int rx_data_len, rx_dma_size; 1253 int i; 1254 u32 offset = 0; 1255 1256 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1257 if (ring_no) 1258 return -EINVAL; 1259 ring = ð->rx_ring_qdma; 1260 offset = 0x1000; 1261 } else { 1262 ring = ð->rx_ring[ring_no]; 1263 } 1264 1265 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1266 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1267 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1268 } else { 1269 rx_data_len = ETH_DATA_LEN; 1270 rx_dma_size = MTK_DMA_SIZE; 1271 } 1272 1273 ring->frag_size = mtk_max_frag_size(rx_data_len); 1274 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1275 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1276 GFP_KERNEL); 1277 if (!ring->data) 1278 return -ENOMEM; 1279 1280 for (i = 0; i < rx_dma_size; i++) { 1281 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1282 if (!ring->data[i]) 1283 return -ENOMEM; 1284 } 1285 1286 ring->dma = dma_alloc_coherent(eth->dev, 1287 rx_dma_size * sizeof(*ring->dma), 1288 &ring->phys, GFP_ATOMIC); 1289 if (!ring->dma) 1290 return -ENOMEM; 1291 1292 for (i = 0; i < rx_dma_size; i++) { 1293 dma_addr_t dma_addr = dma_map_single(eth->dev, 1294 ring->data[i] + NET_SKB_PAD, 1295 ring->buf_size, 1296 DMA_FROM_DEVICE); 1297 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1298 return -ENOMEM; 1299 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1300 1301 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1302 } 1303 ring->dma_size = rx_dma_size; 1304 ring->calc_idx_update = false; 1305 ring->calc_idx = rx_dma_size - 1; 1306 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1307 /* make sure that all changes to the dma ring are flushed before we 1308 * continue 1309 */ 1310 wmb(); 1311 1312 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1313 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1314 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1315 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1316 1317 return 0; 1318 } 1319 1320 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1321 { 1322 int i; 1323 1324 if (ring->data && ring->dma) { 1325 for (i = 0; i < ring->dma_size; i++) { 1326 if (!ring->data[i]) 1327 continue; 1328 if (!ring->dma[i].rxd1) 1329 continue; 1330 dma_unmap_single(eth->dev, 1331 ring->dma[i].rxd1, 1332 ring->buf_size, 1333 DMA_FROM_DEVICE); 1334 skb_free_frag(ring->data[i]); 1335 } 1336 kfree(ring->data); 1337 ring->data = NULL; 1338 } 1339 1340 if (ring->dma) { 1341 dma_free_coherent(eth->dev, 1342 ring->dma_size * sizeof(*ring->dma), 1343 ring->dma, 1344 ring->phys); 1345 ring->dma = NULL; 1346 } 1347 } 1348 1349 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1350 { 1351 int i; 1352 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1353 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1354 1355 /* set LRO rings to auto-learn modes */ 1356 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1357 1358 /* validate LRO ring */ 1359 ring_ctrl_dw2 |= MTK_RING_VLD; 1360 1361 /* set AGE timer (unit: 20us) */ 1362 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1363 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1364 1365 /* set max AGG timer (unit: 20us) */ 1366 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1367 1368 /* set max LRO AGG count */ 1369 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1370 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1371 1372 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1373 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1374 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1375 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1376 } 1377 1378 /* IPv4 checksum update enable */ 1379 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1380 1381 /* switch priority comparison to packet count mode */ 1382 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1383 1384 /* bandwidth threshold setting */ 1385 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1386 1387 /* auto-learn score delta setting */ 1388 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1389 1390 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1391 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1392 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1393 1394 /* set HW LRO mode & the max aggregation count for rx packets */ 1395 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1396 1397 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1398 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1399 1400 /* enable HW LRO */ 1401 lro_ctrl_dw0 |= MTK_LRO_EN; 1402 1403 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1404 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1405 1406 return 0; 1407 } 1408 1409 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1410 { 1411 int i; 1412 u32 val; 1413 1414 /* relinquish lro rings, flush aggregated packets */ 1415 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1416 1417 /* wait for relinquishments done */ 1418 for (i = 0; i < 10; i++) { 1419 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1420 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1421 msleep(20); 1422 continue; 1423 } 1424 break; 1425 } 1426 1427 /* invalidate lro rings */ 1428 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1429 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1430 1431 /* disable HW LRO */ 1432 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1433 } 1434 1435 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1436 { 1437 u32 reg_val; 1438 1439 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1440 1441 /* invalidate the IP setting */ 1442 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1443 1444 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1445 1446 /* validate the IP setting */ 1447 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1448 } 1449 1450 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1451 { 1452 u32 reg_val; 1453 1454 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1455 1456 /* invalidate the IP setting */ 1457 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1458 1459 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1460 } 1461 1462 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1463 { 1464 int cnt = 0; 1465 int i; 1466 1467 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1468 if (mac->hwlro_ip[i]) 1469 cnt++; 1470 } 1471 1472 return cnt; 1473 } 1474 1475 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1476 struct ethtool_rxnfc *cmd) 1477 { 1478 struct ethtool_rx_flow_spec *fsp = 1479 (struct ethtool_rx_flow_spec *)&cmd->fs; 1480 struct mtk_mac *mac = netdev_priv(dev); 1481 struct mtk_eth *eth = mac->hw; 1482 int hwlro_idx; 1483 1484 if ((fsp->flow_type != TCP_V4_FLOW) || 1485 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1486 (fsp->location > 1)) 1487 return -EINVAL; 1488 1489 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1490 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1491 1492 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1493 1494 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1495 1496 return 0; 1497 } 1498 1499 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1500 struct ethtool_rxnfc *cmd) 1501 { 1502 struct ethtool_rx_flow_spec *fsp = 1503 (struct ethtool_rx_flow_spec *)&cmd->fs; 1504 struct mtk_mac *mac = netdev_priv(dev); 1505 struct mtk_eth *eth = mac->hw; 1506 int hwlro_idx; 1507 1508 if (fsp->location > 1) 1509 return -EINVAL; 1510 1511 mac->hwlro_ip[fsp->location] = 0; 1512 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1513 1514 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1515 1516 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1517 1518 return 0; 1519 } 1520 1521 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1522 { 1523 struct mtk_mac *mac = netdev_priv(dev); 1524 struct mtk_eth *eth = mac->hw; 1525 int i, hwlro_idx; 1526 1527 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1528 mac->hwlro_ip[i] = 0; 1529 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1530 1531 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1532 } 1533 1534 mac->hwlro_ip_cnt = 0; 1535 } 1536 1537 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1538 struct ethtool_rxnfc *cmd) 1539 { 1540 struct mtk_mac *mac = netdev_priv(dev); 1541 struct ethtool_rx_flow_spec *fsp = 1542 (struct ethtool_rx_flow_spec *)&cmd->fs; 1543 1544 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1545 fsp->flow_type = TCP_V4_FLOW; 1546 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1547 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1548 1549 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1550 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1551 fsp->h_u.tcp_ip4_spec.psrc = 0; 1552 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1553 fsp->h_u.tcp_ip4_spec.pdst = 0; 1554 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1555 fsp->h_u.tcp_ip4_spec.tos = 0; 1556 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1557 1558 return 0; 1559 } 1560 1561 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1562 struct ethtool_rxnfc *cmd, 1563 u32 *rule_locs) 1564 { 1565 struct mtk_mac *mac = netdev_priv(dev); 1566 int cnt = 0; 1567 int i; 1568 1569 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1570 if (mac->hwlro_ip[i]) { 1571 rule_locs[cnt] = i; 1572 cnt++; 1573 } 1574 } 1575 1576 cmd->rule_cnt = cnt; 1577 1578 return 0; 1579 } 1580 1581 static netdev_features_t mtk_fix_features(struct net_device *dev, 1582 netdev_features_t features) 1583 { 1584 if (!(features & NETIF_F_LRO)) { 1585 struct mtk_mac *mac = netdev_priv(dev); 1586 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1587 1588 if (ip_cnt) { 1589 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1590 1591 features |= NETIF_F_LRO; 1592 } 1593 } 1594 1595 return features; 1596 } 1597 1598 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1599 { 1600 int err = 0; 1601 1602 if (!((dev->features ^ features) & NETIF_F_LRO)) 1603 return 0; 1604 1605 if (!(features & NETIF_F_LRO)) 1606 mtk_hwlro_netdev_disable(dev); 1607 1608 return err; 1609 } 1610 1611 /* wait for DMA to finish whatever it is doing before we start using it again */ 1612 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1613 { 1614 unsigned long t_start = jiffies; 1615 1616 while (1) { 1617 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1618 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1619 return 0; 1620 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1621 break; 1622 } 1623 1624 dev_err(eth->dev, "DMA init timeout\n"); 1625 return -1; 1626 } 1627 1628 static int mtk_dma_init(struct mtk_eth *eth) 1629 { 1630 int err; 1631 u32 i; 1632 1633 if (mtk_dma_busy_wait(eth)) 1634 return -EBUSY; 1635 1636 /* QDMA needs scratch memory for internal reordering of the 1637 * descriptors 1638 */ 1639 err = mtk_init_fq_dma(eth); 1640 if (err) 1641 return err; 1642 1643 err = mtk_tx_alloc(eth); 1644 if (err) 1645 return err; 1646 1647 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 1648 if (err) 1649 return err; 1650 1651 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 1652 if (err) 1653 return err; 1654 1655 if (eth->hwlro) { 1656 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1657 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 1658 if (err) 1659 return err; 1660 } 1661 err = mtk_hwlro_rx_init(eth); 1662 if (err) 1663 return err; 1664 } 1665 1666 /* Enable random early drop and set drop threshold automatically */ 1667 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1668 MTK_QDMA_FC_THRES); 1669 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1670 1671 return 0; 1672 } 1673 1674 static void mtk_dma_free(struct mtk_eth *eth) 1675 { 1676 int i; 1677 1678 for (i = 0; i < MTK_MAC_COUNT; i++) 1679 if (eth->netdev[i]) 1680 netdev_reset_queue(eth->netdev[i]); 1681 if (eth->scratch_ring) { 1682 dma_free_coherent(eth->dev, 1683 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1684 eth->scratch_ring, 1685 eth->phy_scratch_ring); 1686 eth->scratch_ring = NULL; 1687 eth->phy_scratch_ring = 0; 1688 } 1689 mtk_tx_clean(eth); 1690 mtk_rx_clean(eth, ð->rx_ring[0]); 1691 mtk_rx_clean(eth, ð->rx_ring_qdma); 1692 1693 if (eth->hwlro) { 1694 mtk_hwlro_rx_uninit(eth); 1695 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1696 mtk_rx_clean(eth, ð->rx_ring[i]); 1697 } 1698 1699 kfree(eth->scratch_head); 1700 } 1701 1702 static void mtk_tx_timeout(struct net_device *dev) 1703 { 1704 struct mtk_mac *mac = netdev_priv(dev); 1705 struct mtk_eth *eth = mac->hw; 1706 1707 eth->netdev[mac->id]->stats.tx_errors++; 1708 netif_err(eth, tx_err, dev, 1709 "transmit timed out\n"); 1710 schedule_work(ð->pending_work); 1711 } 1712 1713 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1714 { 1715 struct mtk_eth *eth = _eth; 1716 1717 if (likely(napi_schedule_prep(ð->rx_napi))) { 1718 __napi_schedule(ð->rx_napi); 1719 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1720 } 1721 1722 return IRQ_HANDLED; 1723 } 1724 1725 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1726 { 1727 struct mtk_eth *eth = _eth; 1728 1729 if (likely(napi_schedule_prep(ð->tx_napi))) { 1730 __napi_schedule(ð->tx_napi); 1731 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1732 } 1733 1734 return IRQ_HANDLED; 1735 } 1736 1737 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 1738 { 1739 struct mtk_eth *eth = _eth; 1740 1741 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 1742 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 1743 mtk_handle_irq_rx(irq, _eth); 1744 } 1745 if (mtk_r32(eth, MTK_QDMA_INT_MASK) & MTK_TX_DONE_INT) { 1746 if (mtk_r32(eth, MTK_QMTK_INT_STATUS) & MTK_TX_DONE_INT) 1747 mtk_handle_irq_tx(irq, _eth); 1748 } 1749 1750 return IRQ_HANDLED; 1751 } 1752 1753 #ifdef CONFIG_NET_POLL_CONTROLLER 1754 static void mtk_poll_controller(struct net_device *dev) 1755 { 1756 struct mtk_mac *mac = netdev_priv(dev); 1757 struct mtk_eth *eth = mac->hw; 1758 1759 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1760 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1761 mtk_handle_irq_rx(eth->irq[2], dev); 1762 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1763 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1764 } 1765 #endif 1766 1767 static int mtk_start_dma(struct mtk_eth *eth) 1768 { 1769 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 1770 int err; 1771 1772 err = mtk_dma_init(eth); 1773 if (err) { 1774 mtk_dma_free(eth); 1775 return err; 1776 } 1777 1778 mtk_w32(eth, 1779 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 1780 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 1781 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1782 MTK_RX_BT_32DWORDS, 1783 MTK_QDMA_GLO_CFG); 1784 1785 mtk_w32(eth, 1786 MTK_RX_DMA_EN | rx_2b_offset | 1787 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 1788 MTK_PDMA_GLO_CFG); 1789 1790 return 0; 1791 } 1792 1793 static int mtk_open(struct net_device *dev) 1794 { 1795 struct mtk_mac *mac = netdev_priv(dev); 1796 struct mtk_eth *eth = mac->hw; 1797 1798 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1799 if (!refcount_read(ð->dma_refcnt)) { 1800 int err = mtk_start_dma(eth); 1801 1802 if (err) 1803 return err; 1804 1805 napi_enable(ð->tx_napi); 1806 napi_enable(ð->rx_napi); 1807 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1808 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1809 refcount_set(ð->dma_refcnt, 1); 1810 } 1811 else 1812 refcount_inc(ð->dma_refcnt); 1813 1814 phy_start(dev->phydev); 1815 netif_start_queue(dev); 1816 1817 return 0; 1818 } 1819 1820 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1821 { 1822 u32 val; 1823 int i; 1824 1825 /* stop the dma engine */ 1826 spin_lock_bh(ð->page_lock); 1827 val = mtk_r32(eth, glo_cfg); 1828 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1829 glo_cfg); 1830 spin_unlock_bh(ð->page_lock); 1831 1832 /* wait for dma stop */ 1833 for (i = 0; i < 10; i++) { 1834 val = mtk_r32(eth, glo_cfg); 1835 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1836 msleep(20); 1837 continue; 1838 } 1839 break; 1840 } 1841 } 1842 1843 static int mtk_stop(struct net_device *dev) 1844 { 1845 struct mtk_mac *mac = netdev_priv(dev); 1846 struct mtk_eth *eth = mac->hw; 1847 1848 netif_tx_disable(dev); 1849 phy_stop(dev->phydev); 1850 1851 /* only shutdown DMA if this is the last user */ 1852 if (!refcount_dec_and_test(ð->dma_refcnt)) 1853 return 0; 1854 1855 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1856 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1857 napi_disable(ð->tx_napi); 1858 napi_disable(ð->rx_napi); 1859 1860 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1861 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 1862 1863 mtk_dma_free(eth); 1864 1865 return 0; 1866 } 1867 1868 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 1869 { 1870 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1871 reset_bits, 1872 reset_bits); 1873 1874 usleep_range(1000, 1100); 1875 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1876 reset_bits, 1877 ~reset_bits); 1878 mdelay(10); 1879 } 1880 1881 static void mtk_clk_disable(struct mtk_eth *eth) 1882 { 1883 int clk; 1884 1885 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 1886 clk_disable_unprepare(eth->clks[clk]); 1887 } 1888 1889 static int mtk_clk_enable(struct mtk_eth *eth) 1890 { 1891 int clk, ret; 1892 1893 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 1894 ret = clk_prepare_enable(eth->clks[clk]); 1895 if (ret) 1896 goto err_disable_clks; 1897 } 1898 1899 return 0; 1900 1901 err_disable_clks: 1902 while (--clk >= 0) 1903 clk_disable_unprepare(eth->clks[clk]); 1904 1905 return ret; 1906 } 1907 1908 static int mtk_hw_init(struct mtk_eth *eth) 1909 { 1910 int i, val, ret; 1911 1912 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 1913 return 0; 1914 1915 pm_runtime_enable(eth->dev); 1916 pm_runtime_get_sync(eth->dev); 1917 1918 ret = mtk_clk_enable(eth); 1919 if (ret) 1920 goto err_disable_pm; 1921 1922 ethsys_reset(eth, RSTCTRL_FE); 1923 ethsys_reset(eth, RSTCTRL_PPE); 1924 1925 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 1926 for (i = 0; i < MTK_MAC_COUNT; i++) { 1927 if (!eth->mac[i]) 1928 continue; 1929 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); 1930 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); 1931 } 1932 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1933 1934 if (eth->pctl) { 1935 /* Set GE2 driving and slew rate */ 1936 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1937 1938 /* set GE2 TDSEL */ 1939 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1940 1941 /* set GE2 TUNE */ 1942 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1943 } 1944 1945 /* Set linkdown as the default for each GMAC. Its own MCR would be set 1946 * up with the more appropriate value when mtk_phy_link_adjust call is 1947 * being invoked. 1948 */ 1949 for (i = 0; i < MTK_MAC_COUNT; i++) 1950 mtk_w32(eth, 0, MTK_MAC_MCR(i)); 1951 1952 /* Indicates CDM to parse the MTK special tag from CPU 1953 * which also is working out for untag packets. 1954 */ 1955 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 1956 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 1957 1958 /* Enable RX VLan Offloading */ 1959 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1960 1961 /* enable interrupt delay for RX */ 1962 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 1963 1964 /* disable delay and normal interrupt */ 1965 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1966 mtk_tx_irq_disable(eth, ~0); 1967 mtk_rx_irq_disable(eth, ~0); 1968 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1969 mtk_w32(eth, 0, MTK_RST_GL); 1970 1971 /* FE int grouping */ 1972 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1973 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1974 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1975 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1976 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1977 1978 for (i = 0; i < 2; i++) { 1979 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1980 1981 /* setup the forward port to send frame to PDMA */ 1982 val &= ~0xffff; 1983 1984 /* Enable RX checksum */ 1985 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1986 1987 /* setup the mac dma */ 1988 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 1989 } 1990 1991 return 0; 1992 1993 err_disable_pm: 1994 pm_runtime_put_sync(eth->dev); 1995 pm_runtime_disable(eth->dev); 1996 1997 return ret; 1998 } 1999 2000 static int mtk_hw_deinit(struct mtk_eth *eth) 2001 { 2002 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2003 return 0; 2004 2005 mtk_clk_disable(eth); 2006 2007 pm_runtime_put_sync(eth->dev); 2008 pm_runtime_disable(eth->dev); 2009 2010 return 0; 2011 } 2012 2013 static int __init mtk_init(struct net_device *dev) 2014 { 2015 struct mtk_mac *mac = netdev_priv(dev); 2016 struct mtk_eth *eth = mac->hw; 2017 const char *mac_addr; 2018 2019 mac_addr = of_get_mac_address(mac->of_node); 2020 if (!IS_ERR(mac_addr)) 2021 ether_addr_copy(dev->dev_addr, mac_addr); 2022 2023 /* If the mac address is invalid, use random mac address */ 2024 if (!is_valid_ether_addr(dev->dev_addr)) { 2025 eth_hw_addr_random(dev); 2026 dev_err(eth->dev, "generated random MAC address %pM\n", 2027 dev->dev_addr); 2028 } 2029 2030 return mtk_phy_connect(dev); 2031 } 2032 2033 static void mtk_uninit(struct net_device *dev) 2034 { 2035 struct mtk_mac *mac = netdev_priv(dev); 2036 struct mtk_eth *eth = mac->hw; 2037 2038 phy_disconnect(dev->phydev); 2039 if (of_phy_is_fixed_link(mac->of_node)) 2040 of_phy_deregister_fixed_link(mac->of_node); 2041 mtk_tx_irq_disable(eth, ~0); 2042 mtk_rx_irq_disable(eth, ~0); 2043 } 2044 2045 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2046 { 2047 switch (cmd) { 2048 case SIOCGMIIPHY: 2049 case SIOCGMIIREG: 2050 case SIOCSMIIREG: 2051 return phy_mii_ioctl(dev->phydev, ifr, cmd); 2052 default: 2053 break; 2054 } 2055 2056 return -EOPNOTSUPP; 2057 } 2058 2059 static void mtk_pending_work(struct work_struct *work) 2060 { 2061 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2062 int err, i; 2063 unsigned long restart = 0; 2064 2065 rtnl_lock(); 2066 2067 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2068 2069 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2070 cpu_relax(); 2071 2072 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2073 /* stop all devices to make sure that dma is properly shut down */ 2074 for (i = 0; i < MTK_MAC_COUNT; i++) { 2075 if (!eth->netdev[i]) 2076 continue; 2077 mtk_stop(eth->netdev[i]); 2078 __set_bit(i, &restart); 2079 } 2080 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2081 2082 /* restart underlying hardware such as power, clock, pin mux 2083 * and the connected phy 2084 */ 2085 mtk_hw_deinit(eth); 2086 2087 if (eth->dev->pins) 2088 pinctrl_select_state(eth->dev->pins->p, 2089 eth->dev->pins->default_state); 2090 mtk_hw_init(eth); 2091 2092 for (i = 0; i < MTK_MAC_COUNT; i++) { 2093 if (!eth->mac[i] || 2094 of_phy_is_fixed_link(eth->mac[i]->of_node)) 2095 continue; 2096 err = phy_init_hw(eth->netdev[i]->phydev); 2097 if (err) 2098 dev_err(eth->dev, "%s: PHY init failed.\n", 2099 eth->netdev[i]->name); 2100 } 2101 2102 /* restart DMA and enable IRQs */ 2103 for (i = 0; i < MTK_MAC_COUNT; i++) { 2104 if (!test_bit(i, &restart)) 2105 continue; 2106 err = mtk_open(eth->netdev[i]); 2107 if (err) { 2108 netif_alert(eth, ifup, eth->netdev[i], 2109 "Driver up/down cycle failed, closing device.\n"); 2110 dev_close(eth->netdev[i]); 2111 } 2112 } 2113 2114 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2115 2116 clear_bit_unlock(MTK_RESETTING, ð->state); 2117 2118 rtnl_unlock(); 2119 } 2120 2121 static int mtk_free_dev(struct mtk_eth *eth) 2122 { 2123 int i; 2124 2125 for (i = 0; i < MTK_MAC_COUNT; i++) { 2126 if (!eth->netdev[i]) 2127 continue; 2128 free_netdev(eth->netdev[i]); 2129 } 2130 2131 return 0; 2132 } 2133 2134 static int mtk_unreg_dev(struct mtk_eth *eth) 2135 { 2136 int i; 2137 2138 for (i = 0; i < MTK_MAC_COUNT; i++) { 2139 if (!eth->netdev[i]) 2140 continue; 2141 unregister_netdev(eth->netdev[i]); 2142 } 2143 2144 return 0; 2145 } 2146 2147 static int mtk_cleanup(struct mtk_eth *eth) 2148 { 2149 mtk_unreg_dev(eth); 2150 mtk_free_dev(eth); 2151 cancel_work_sync(ð->pending_work); 2152 2153 return 0; 2154 } 2155 2156 static int mtk_get_link_ksettings(struct net_device *ndev, 2157 struct ethtool_link_ksettings *cmd) 2158 { 2159 struct mtk_mac *mac = netdev_priv(ndev); 2160 2161 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2162 return -EBUSY; 2163 2164 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2165 2166 return 0; 2167 } 2168 2169 static int mtk_set_link_ksettings(struct net_device *ndev, 2170 const struct ethtool_link_ksettings *cmd) 2171 { 2172 struct mtk_mac *mac = netdev_priv(ndev); 2173 2174 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2175 return -EBUSY; 2176 2177 return phy_ethtool_ksettings_set(ndev->phydev, cmd); 2178 } 2179 2180 static void mtk_get_drvinfo(struct net_device *dev, 2181 struct ethtool_drvinfo *info) 2182 { 2183 struct mtk_mac *mac = netdev_priv(dev); 2184 2185 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2186 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2187 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2188 } 2189 2190 static u32 mtk_get_msglevel(struct net_device *dev) 2191 { 2192 struct mtk_mac *mac = netdev_priv(dev); 2193 2194 return mac->hw->msg_enable; 2195 } 2196 2197 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2198 { 2199 struct mtk_mac *mac = netdev_priv(dev); 2200 2201 mac->hw->msg_enable = value; 2202 } 2203 2204 static int mtk_nway_reset(struct net_device *dev) 2205 { 2206 struct mtk_mac *mac = netdev_priv(dev); 2207 2208 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2209 return -EBUSY; 2210 2211 return genphy_restart_aneg(dev->phydev); 2212 } 2213 2214 static u32 mtk_get_link(struct net_device *dev) 2215 { 2216 struct mtk_mac *mac = netdev_priv(dev); 2217 int err; 2218 2219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2220 return -EBUSY; 2221 2222 err = genphy_update_link(dev->phydev); 2223 if (err) 2224 return ethtool_op_get_link(dev); 2225 2226 return dev->phydev->link; 2227 } 2228 2229 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2230 { 2231 int i; 2232 2233 switch (stringset) { 2234 case ETH_SS_STATS: 2235 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2236 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2237 data += ETH_GSTRING_LEN; 2238 } 2239 break; 2240 } 2241 } 2242 2243 static int mtk_get_sset_count(struct net_device *dev, int sset) 2244 { 2245 switch (sset) { 2246 case ETH_SS_STATS: 2247 return ARRAY_SIZE(mtk_ethtool_stats); 2248 default: 2249 return -EOPNOTSUPP; 2250 } 2251 } 2252 2253 static void mtk_get_ethtool_stats(struct net_device *dev, 2254 struct ethtool_stats *stats, u64 *data) 2255 { 2256 struct mtk_mac *mac = netdev_priv(dev); 2257 struct mtk_hw_stats *hwstats = mac->hw_stats; 2258 u64 *data_src, *data_dst; 2259 unsigned int start; 2260 int i; 2261 2262 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2263 return; 2264 2265 if (netif_running(dev) && netif_device_present(dev)) { 2266 if (spin_trylock_bh(&hwstats->stats_lock)) { 2267 mtk_stats_update_mac(mac); 2268 spin_unlock_bh(&hwstats->stats_lock); 2269 } 2270 } 2271 2272 data_src = (u64 *)hwstats; 2273 2274 do { 2275 data_dst = data; 2276 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2277 2278 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2279 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2280 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2281 } 2282 2283 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2284 u32 *rule_locs) 2285 { 2286 int ret = -EOPNOTSUPP; 2287 2288 switch (cmd->cmd) { 2289 case ETHTOOL_GRXRINGS: 2290 if (dev->hw_features & NETIF_F_LRO) { 2291 cmd->data = MTK_MAX_RX_RING_NUM; 2292 ret = 0; 2293 } 2294 break; 2295 case ETHTOOL_GRXCLSRLCNT: 2296 if (dev->hw_features & NETIF_F_LRO) { 2297 struct mtk_mac *mac = netdev_priv(dev); 2298 2299 cmd->rule_cnt = mac->hwlro_ip_cnt; 2300 ret = 0; 2301 } 2302 break; 2303 case ETHTOOL_GRXCLSRULE: 2304 if (dev->hw_features & NETIF_F_LRO) 2305 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2306 break; 2307 case ETHTOOL_GRXCLSRLALL: 2308 if (dev->hw_features & NETIF_F_LRO) 2309 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2310 rule_locs); 2311 break; 2312 default: 2313 break; 2314 } 2315 2316 return ret; 2317 } 2318 2319 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2320 { 2321 int ret = -EOPNOTSUPP; 2322 2323 switch (cmd->cmd) { 2324 case ETHTOOL_SRXCLSRLINS: 2325 if (dev->hw_features & NETIF_F_LRO) 2326 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2327 break; 2328 case ETHTOOL_SRXCLSRLDEL: 2329 if (dev->hw_features & NETIF_F_LRO) 2330 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2331 break; 2332 default: 2333 break; 2334 } 2335 2336 return ret; 2337 } 2338 2339 static const struct ethtool_ops mtk_ethtool_ops = { 2340 .get_link_ksettings = mtk_get_link_ksettings, 2341 .set_link_ksettings = mtk_set_link_ksettings, 2342 .get_drvinfo = mtk_get_drvinfo, 2343 .get_msglevel = mtk_get_msglevel, 2344 .set_msglevel = mtk_set_msglevel, 2345 .nway_reset = mtk_nway_reset, 2346 .get_link = mtk_get_link, 2347 .get_strings = mtk_get_strings, 2348 .get_sset_count = mtk_get_sset_count, 2349 .get_ethtool_stats = mtk_get_ethtool_stats, 2350 .get_rxnfc = mtk_get_rxnfc, 2351 .set_rxnfc = mtk_set_rxnfc, 2352 }; 2353 2354 static const struct net_device_ops mtk_netdev_ops = { 2355 .ndo_init = mtk_init, 2356 .ndo_uninit = mtk_uninit, 2357 .ndo_open = mtk_open, 2358 .ndo_stop = mtk_stop, 2359 .ndo_start_xmit = mtk_start_xmit, 2360 .ndo_set_mac_address = mtk_set_mac_address, 2361 .ndo_validate_addr = eth_validate_addr, 2362 .ndo_do_ioctl = mtk_do_ioctl, 2363 .ndo_tx_timeout = mtk_tx_timeout, 2364 .ndo_get_stats64 = mtk_get_stats64, 2365 .ndo_fix_features = mtk_fix_features, 2366 .ndo_set_features = mtk_set_features, 2367 #ifdef CONFIG_NET_POLL_CONTROLLER 2368 .ndo_poll_controller = mtk_poll_controller, 2369 #endif 2370 }; 2371 2372 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2373 { 2374 struct mtk_mac *mac; 2375 const __be32 *_id = of_get_property(np, "reg", NULL); 2376 int id, err; 2377 2378 if (!_id) { 2379 dev_err(eth->dev, "missing mac id\n"); 2380 return -EINVAL; 2381 } 2382 2383 id = be32_to_cpup(_id); 2384 if (id >= MTK_MAC_COUNT) { 2385 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2386 return -EINVAL; 2387 } 2388 2389 if (eth->netdev[id]) { 2390 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2391 return -EINVAL; 2392 } 2393 2394 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2395 if (!eth->netdev[id]) { 2396 dev_err(eth->dev, "alloc_etherdev failed\n"); 2397 return -ENOMEM; 2398 } 2399 mac = netdev_priv(eth->netdev[id]); 2400 eth->mac[id] = mac; 2401 mac->id = id; 2402 mac->hw = eth; 2403 mac->of_node = np; 2404 2405 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2406 mac->hwlro_ip_cnt = 0; 2407 2408 mac->hw_stats = devm_kzalloc(eth->dev, 2409 sizeof(*mac->hw_stats), 2410 GFP_KERNEL); 2411 if (!mac->hw_stats) { 2412 dev_err(eth->dev, "failed to allocate counter memory\n"); 2413 err = -ENOMEM; 2414 goto free_netdev; 2415 } 2416 spin_lock_init(&mac->hw_stats->stats_lock); 2417 u64_stats_init(&mac->hw_stats->syncp); 2418 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2419 2420 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2421 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2422 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2423 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2424 2425 eth->netdev[id]->hw_features = MTK_HW_FEATURES; 2426 if (eth->hwlro) 2427 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2428 2429 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 2430 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2431 eth->netdev[id]->features |= MTK_HW_FEATURES; 2432 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2433 2434 eth->netdev[id]->irq = eth->irq[0]; 2435 eth->netdev[id]->dev.of_node = np; 2436 2437 return 0; 2438 2439 free_netdev: 2440 free_netdev(eth->netdev[id]); 2441 return err; 2442 } 2443 2444 static int mtk_probe(struct platform_device *pdev) 2445 { 2446 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2447 struct device_node *mac_np; 2448 struct mtk_eth *eth; 2449 int err; 2450 int i; 2451 2452 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2453 if (!eth) 2454 return -ENOMEM; 2455 2456 eth->soc = of_device_get_match_data(&pdev->dev); 2457 2458 eth->dev = &pdev->dev; 2459 eth->base = devm_ioremap_resource(&pdev->dev, res); 2460 if (IS_ERR(eth->base)) 2461 return PTR_ERR(eth->base); 2462 2463 spin_lock_init(ð->page_lock); 2464 spin_lock_init(ð->tx_irq_lock); 2465 spin_lock_init(ð->rx_irq_lock); 2466 2467 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2468 "mediatek,ethsys"); 2469 if (IS_ERR(eth->ethsys)) { 2470 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2471 return PTR_ERR(eth->ethsys); 2472 } 2473 2474 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 2475 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2476 "mediatek,infracfg"); 2477 if (IS_ERR(eth->infra)) { 2478 dev_err(&pdev->dev, "no infracfg regmap found\n"); 2479 return PTR_ERR(eth->infra); 2480 } 2481 } 2482 2483 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2484 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 2485 GFP_KERNEL); 2486 if (!eth->sgmii) 2487 return -ENOMEM; 2488 2489 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 2490 eth->soc->ana_rgc3); 2491 2492 if (err) 2493 return err; 2494 } 2495 2496 if (eth->soc->required_pctl) { 2497 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2498 "mediatek,pctl"); 2499 if (IS_ERR(eth->pctl)) { 2500 dev_err(&pdev->dev, "no pctl regmap found\n"); 2501 return PTR_ERR(eth->pctl); 2502 } 2503 } 2504 2505 for (i = 0; i < 3; i++) { 2506 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 2507 eth->irq[i] = eth->irq[0]; 2508 else 2509 eth->irq[i] = platform_get_irq(pdev, i); 2510 if (eth->irq[i] < 0) { 2511 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2512 return -ENXIO; 2513 } 2514 } 2515 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2516 eth->clks[i] = devm_clk_get(eth->dev, 2517 mtk_clks_source_name[i]); 2518 if (IS_ERR(eth->clks[i])) { 2519 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2520 return -EPROBE_DEFER; 2521 if (eth->soc->required_clks & BIT(i)) { 2522 dev_err(&pdev->dev, "clock %s not found\n", 2523 mtk_clks_source_name[i]); 2524 return -EINVAL; 2525 } 2526 eth->clks[i] = NULL; 2527 } 2528 } 2529 2530 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2531 INIT_WORK(ð->pending_work, mtk_pending_work); 2532 2533 err = mtk_hw_init(eth); 2534 if (err) 2535 return err; 2536 2537 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 2538 2539 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2540 if (!of_device_is_compatible(mac_np, 2541 "mediatek,eth-mac")) 2542 continue; 2543 2544 if (!of_device_is_available(mac_np)) 2545 continue; 2546 2547 err = mtk_add_mac(eth, mac_np); 2548 if (err) 2549 goto err_deinit_hw; 2550 } 2551 2552 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 2553 err = devm_request_irq(eth->dev, eth->irq[0], 2554 mtk_handle_irq, 0, 2555 dev_name(eth->dev), eth); 2556 } else { 2557 err = devm_request_irq(eth->dev, eth->irq[1], 2558 mtk_handle_irq_tx, 0, 2559 dev_name(eth->dev), eth); 2560 if (err) 2561 goto err_free_dev; 2562 2563 err = devm_request_irq(eth->dev, eth->irq[2], 2564 mtk_handle_irq_rx, 0, 2565 dev_name(eth->dev), eth); 2566 } 2567 if (err) 2568 goto err_free_dev; 2569 2570 err = mtk_mdio_init(eth); 2571 if (err) 2572 goto err_free_dev; 2573 2574 for (i = 0; i < MTK_MAX_DEVS; i++) { 2575 if (!eth->netdev[i]) 2576 continue; 2577 2578 err = register_netdev(eth->netdev[i]); 2579 if (err) { 2580 dev_err(eth->dev, "error bringing up device\n"); 2581 goto err_deinit_mdio; 2582 } else 2583 netif_info(eth, probe, eth->netdev[i], 2584 "mediatek frame engine at 0x%08lx, irq %d\n", 2585 eth->netdev[i]->base_addr, eth->irq[0]); 2586 } 2587 2588 /* we run 2 devices on the same DMA ring so we need a dummy device 2589 * for NAPI to work 2590 */ 2591 init_dummy_netdev(ð->dummy_dev); 2592 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 2593 MTK_NAPI_WEIGHT); 2594 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 2595 MTK_NAPI_WEIGHT); 2596 2597 platform_set_drvdata(pdev, eth); 2598 2599 return 0; 2600 2601 err_deinit_mdio: 2602 mtk_mdio_cleanup(eth); 2603 err_free_dev: 2604 mtk_free_dev(eth); 2605 err_deinit_hw: 2606 mtk_hw_deinit(eth); 2607 2608 return err; 2609 } 2610 2611 static int mtk_remove(struct platform_device *pdev) 2612 { 2613 struct mtk_eth *eth = platform_get_drvdata(pdev); 2614 int i; 2615 2616 /* stop all devices to make sure that dma is properly shut down */ 2617 for (i = 0; i < MTK_MAC_COUNT; i++) { 2618 if (!eth->netdev[i]) 2619 continue; 2620 mtk_stop(eth->netdev[i]); 2621 } 2622 2623 mtk_hw_deinit(eth); 2624 2625 netif_napi_del(ð->tx_napi); 2626 netif_napi_del(ð->rx_napi); 2627 mtk_cleanup(eth); 2628 mtk_mdio_cleanup(eth); 2629 2630 return 0; 2631 } 2632 2633 static const struct mtk_soc_data mt2701_data = { 2634 .caps = MT7623_CAPS | MTK_HWLRO, 2635 .required_clks = MT7623_CLKS_BITMAP, 2636 .required_pctl = true, 2637 }; 2638 2639 static const struct mtk_soc_data mt7621_data = { 2640 .caps = MT7621_CAPS, 2641 .required_clks = MT7621_CLKS_BITMAP, 2642 .required_pctl = false, 2643 }; 2644 2645 static const struct mtk_soc_data mt7622_data = { 2646 .ana_rgc3 = 0x2028, 2647 .caps = MT7622_CAPS | MTK_HWLRO, 2648 .required_clks = MT7622_CLKS_BITMAP, 2649 .required_pctl = false, 2650 }; 2651 2652 static const struct mtk_soc_data mt7623_data = { 2653 .caps = MT7623_CAPS | MTK_HWLRO, 2654 .required_clks = MT7623_CLKS_BITMAP, 2655 .required_pctl = true, 2656 }; 2657 2658 static const struct mtk_soc_data mt7629_data = { 2659 .ana_rgc3 = 0x128, 2660 .caps = MT7629_CAPS | MTK_HWLRO, 2661 .required_clks = MT7629_CLKS_BITMAP, 2662 .required_pctl = false, 2663 }; 2664 2665 const struct of_device_id of_mtk_match[] = { 2666 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 2667 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 2668 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 2669 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 2670 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 2671 {}, 2672 }; 2673 MODULE_DEVICE_TABLE(of, of_mtk_match); 2674 2675 static struct platform_driver mtk_driver = { 2676 .probe = mtk_probe, 2677 .remove = mtk_remove, 2678 .driver = { 2679 .name = "mtk_soc_eth", 2680 .of_match_table = of_mtk_match, 2681 }, 2682 }; 2683 2684 module_platform_driver(mtk_driver); 2685 2686 MODULE_LICENSE("GPL"); 2687 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 2688 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 2689