1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/regmap.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/if_vlan.h> 18 #include <linux/reset.h> 19 #include <linux/tcp.h> 20 #include <linux/interrupt.h> 21 #include <linux/pinctrl/devinfo.h> 22 #include <linux/phylink.h> 23 #include <linux/pcs/pcs-mtk-lynxi.h> 24 #include <linux/jhash.h> 25 #include <linux/bitfield.h> 26 #include <net/dsa.h> 27 #include <net/dst_metadata.h> 28 29 #include "mtk_eth_soc.h" 30 #include "mtk_wed.h" 31 32 static int mtk_msg_level = -1; 33 module_param_named(msg_level, mtk_msg_level, int, 0); 34 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 35 36 #define MTK_ETHTOOL_STAT(x) { #x, \ 37 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 38 39 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 40 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 41 sizeof(u64) } 42 43 static const struct mtk_reg_map mtk_reg_map = { 44 .tx_irq_mask = 0x1a1c, 45 .tx_irq_status = 0x1a18, 46 .pdma = { 47 .rx_ptr = 0x0900, 48 .rx_cnt_cfg = 0x0904, 49 .pcrx_ptr = 0x0908, 50 .glo_cfg = 0x0a04, 51 .rst_idx = 0x0a08, 52 .delay_irq = 0x0a0c, 53 .irq_status = 0x0a20, 54 .irq_mask = 0x0a28, 55 .adma_rx_dbg0 = 0x0a38, 56 .int_grp = 0x0a50, 57 }, 58 .qdma = { 59 .qtx_cfg = 0x1800, 60 .qtx_sch = 0x1804, 61 .rx_ptr = 0x1900, 62 .rx_cnt_cfg = 0x1904, 63 .qcrx_ptr = 0x1908, 64 .glo_cfg = 0x1a04, 65 .rst_idx = 0x1a08, 66 .delay_irq = 0x1a0c, 67 .fc_th = 0x1a10, 68 .tx_sch_rate = 0x1a14, 69 .int_grp = 0x1a20, 70 .hred = 0x1a44, 71 .ctx_ptr = 0x1b00, 72 .dtx_ptr = 0x1b04, 73 .crx_ptr = 0x1b10, 74 .drx_ptr = 0x1b14, 75 .fq_head = 0x1b20, 76 .fq_tail = 0x1b24, 77 .fq_count = 0x1b28, 78 .fq_blen = 0x1b2c, 79 }, 80 .gdm1_cnt = 0x2400, 81 .gdma_to_ppe = 0x4444, 82 .ppe_base = 0x0c00, 83 .wdma_base = { 84 [0] = 0x2800, 85 [1] = 0x2c00, 86 }, 87 .pse_iq_sta = 0x0110, 88 .pse_oq_sta = 0x0118, 89 }; 90 91 static const struct mtk_reg_map mt7628_reg_map = { 92 .tx_irq_mask = 0x0a28, 93 .tx_irq_status = 0x0a20, 94 .pdma = { 95 .rx_ptr = 0x0900, 96 .rx_cnt_cfg = 0x0904, 97 .pcrx_ptr = 0x0908, 98 .glo_cfg = 0x0a04, 99 .rst_idx = 0x0a08, 100 .delay_irq = 0x0a0c, 101 .irq_status = 0x0a20, 102 .irq_mask = 0x0a28, 103 .int_grp = 0x0a50, 104 }, 105 }; 106 107 static const struct mtk_reg_map mt7986_reg_map = { 108 .tx_irq_mask = 0x461c, 109 .tx_irq_status = 0x4618, 110 .pdma = { 111 .rx_ptr = 0x6100, 112 .rx_cnt_cfg = 0x6104, 113 .pcrx_ptr = 0x6108, 114 .glo_cfg = 0x6204, 115 .rst_idx = 0x6208, 116 .delay_irq = 0x620c, 117 .irq_status = 0x6220, 118 .irq_mask = 0x6228, 119 .adma_rx_dbg0 = 0x6238, 120 .int_grp = 0x6250, 121 }, 122 .qdma = { 123 .qtx_cfg = 0x4400, 124 .qtx_sch = 0x4404, 125 .rx_ptr = 0x4500, 126 .rx_cnt_cfg = 0x4504, 127 .qcrx_ptr = 0x4508, 128 .glo_cfg = 0x4604, 129 .rst_idx = 0x4608, 130 .delay_irq = 0x460c, 131 .fc_th = 0x4610, 132 .int_grp = 0x4620, 133 .hred = 0x4644, 134 .ctx_ptr = 0x4700, 135 .dtx_ptr = 0x4704, 136 .crx_ptr = 0x4710, 137 .drx_ptr = 0x4714, 138 .fq_head = 0x4720, 139 .fq_tail = 0x4724, 140 .fq_count = 0x4728, 141 .fq_blen = 0x472c, 142 .tx_sch_rate = 0x4798, 143 }, 144 .gdm1_cnt = 0x1c00, 145 .gdma_to_ppe = 0x3333, 146 .ppe_base = 0x2000, 147 .wdma_base = { 148 [0] = 0x4800, 149 [1] = 0x4c00, 150 }, 151 .pse_iq_sta = 0x0180, 152 .pse_oq_sta = 0x01a0, 153 }; 154 155 /* strings used by ethtool */ 156 static const struct mtk_ethtool_stats { 157 char str[ETH_GSTRING_LEN]; 158 u32 offset; 159 } mtk_ethtool_stats[] = { 160 MTK_ETHTOOL_STAT(tx_bytes), 161 MTK_ETHTOOL_STAT(tx_packets), 162 MTK_ETHTOOL_STAT(tx_skip), 163 MTK_ETHTOOL_STAT(tx_collisions), 164 MTK_ETHTOOL_STAT(rx_bytes), 165 MTK_ETHTOOL_STAT(rx_packets), 166 MTK_ETHTOOL_STAT(rx_overflow), 167 MTK_ETHTOOL_STAT(rx_fcs_errors), 168 MTK_ETHTOOL_STAT(rx_short_errors), 169 MTK_ETHTOOL_STAT(rx_long_errors), 170 MTK_ETHTOOL_STAT(rx_checksum_errors), 171 MTK_ETHTOOL_STAT(rx_flow_control_packets), 172 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 173 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 174 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 175 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 176 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 177 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 178 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 179 }; 180 181 static const char * const mtk_clks_source_name[] = { 182 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 183 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 184 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 185 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" 186 }; 187 188 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 189 { 190 __raw_writel(val, eth->base + reg); 191 } 192 193 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 194 { 195 return __raw_readl(eth->base + reg); 196 } 197 198 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 199 { 200 u32 val; 201 202 val = mtk_r32(eth, reg); 203 val &= ~mask; 204 val |= set; 205 mtk_w32(eth, val, reg); 206 return reg; 207 } 208 209 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 210 { 211 unsigned long t_start = jiffies; 212 213 while (1) { 214 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 215 return 0; 216 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 217 break; 218 cond_resched(); 219 } 220 221 dev_err(eth->dev, "mdio: MDIO timeout\n"); 222 return -ETIMEDOUT; 223 } 224 225 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 226 u32 write_data) 227 { 228 int ret; 229 230 ret = mtk_mdio_busy_wait(eth); 231 if (ret < 0) 232 return ret; 233 234 mtk_w32(eth, PHY_IAC_ACCESS | 235 PHY_IAC_START_C22 | 236 PHY_IAC_CMD_WRITE | 237 PHY_IAC_REG(phy_reg) | 238 PHY_IAC_ADDR(phy_addr) | 239 PHY_IAC_DATA(write_data), 240 MTK_PHY_IAC); 241 242 ret = mtk_mdio_busy_wait(eth); 243 if (ret < 0) 244 return ret; 245 246 return 0; 247 } 248 249 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 250 u32 devad, u32 phy_reg, u32 write_data) 251 { 252 int ret; 253 254 ret = mtk_mdio_busy_wait(eth); 255 if (ret < 0) 256 return ret; 257 258 mtk_w32(eth, PHY_IAC_ACCESS | 259 PHY_IAC_START_C45 | 260 PHY_IAC_CMD_C45_ADDR | 261 PHY_IAC_REG(devad) | 262 PHY_IAC_ADDR(phy_addr) | 263 PHY_IAC_DATA(phy_reg), 264 MTK_PHY_IAC); 265 266 ret = mtk_mdio_busy_wait(eth); 267 if (ret < 0) 268 return ret; 269 270 mtk_w32(eth, PHY_IAC_ACCESS | 271 PHY_IAC_START_C45 | 272 PHY_IAC_CMD_WRITE | 273 PHY_IAC_REG(devad) | 274 PHY_IAC_ADDR(phy_addr) | 275 PHY_IAC_DATA(write_data), 276 MTK_PHY_IAC); 277 278 ret = mtk_mdio_busy_wait(eth); 279 if (ret < 0) 280 return ret; 281 282 return 0; 283 } 284 285 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 286 { 287 int ret; 288 289 ret = mtk_mdio_busy_wait(eth); 290 if (ret < 0) 291 return ret; 292 293 mtk_w32(eth, PHY_IAC_ACCESS | 294 PHY_IAC_START_C22 | 295 PHY_IAC_CMD_C22_READ | 296 PHY_IAC_REG(phy_reg) | 297 PHY_IAC_ADDR(phy_addr), 298 MTK_PHY_IAC); 299 300 ret = mtk_mdio_busy_wait(eth); 301 if (ret < 0) 302 return ret; 303 304 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 305 } 306 307 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 308 u32 devad, u32 phy_reg) 309 { 310 int ret; 311 312 ret = mtk_mdio_busy_wait(eth); 313 if (ret < 0) 314 return ret; 315 316 mtk_w32(eth, PHY_IAC_ACCESS | 317 PHY_IAC_START_C45 | 318 PHY_IAC_CMD_C45_ADDR | 319 PHY_IAC_REG(devad) | 320 PHY_IAC_ADDR(phy_addr) | 321 PHY_IAC_DATA(phy_reg), 322 MTK_PHY_IAC); 323 324 ret = mtk_mdio_busy_wait(eth); 325 if (ret < 0) 326 return ret; 327 328 mtk_w32(eth, PHY_IAC_ACCESS | 329 PHY_IAC_START_C45 | 330 PHY_IAC_CMD_C45_READ | 331 PHY_IAC_REG(devad) | 332 PHY_IAC_ADDR(phy_addr), 333 MTK_PHY_IAC); 334 335 ret = mtk_mdio_busy_wait(eth); 336 if (ret < 0) 337 return ret; 338 339 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 340 } 341 342 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 343 int phy_reg, u16 val) 344 { 345 struct mtk_eth *eth = bus->priv; 346 347 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 348 } 349 350 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 351 int devad, int phy_reg, u16 val) 352 { 353 struct mtk_eth *eth = bus->priv; 354 355 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 356 } 357 358 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 359 { 360 struct mtk_eth *eth = bus->priv; 361 362 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 363 } 364 365 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 366 int phy_reg) 367 { 368 struct mtk_eth *eth = bus->priv; 369 370 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 371 } 372 373 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 374 phy_interface_t interface) 375 { 376 u32 val; 377 378 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 379 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 380 381 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 382 ETHSYS_TRGMII_MT7621_MASK, val); 383 384 return 0; 385 } 386 387 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 388 phy_interface_t interface) 389 { 390 int ret; 391 392 if (interface == PHY_INTERFACE_MODE_TRGMII) { 393 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 394 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); 395 if (ret) 396 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 397 return; 398 } 399 400 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); 401 } 402 403 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 404 phy_interface_t interface) 405 { 406 struct mtk_mac *mac = container_of(config, struct mtk_mac, 407 phylink_config); 408 struct mtk_eth *eth = mac->hw; 409 unsigned int sid; 410 411 if (interface == PHY_INTERFACE_MODE_SGMII || 412 phy_interface_mode_is_8023z(interface)) { 413 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 414 0 : mac->id; 415 416 return eth->sgmii_pcs[sid]; 417 } 418 419 return NULL; 420 } 421 422 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 423 const struct phylink_link_state *state) 424 { 425 struct mtk_mac *mac = container_of(config, struct mtk_mac, 426 phylink_config); 427 struct mtk_eth *eth = mac->hw; 428 int val, ge_mode, err = 0; 429 u32 i; 430 431 /* MT76x8 has no hardware settings between for the MAC */ 432 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 433 mac->interface != state->interface) { 434 /* Setup soc pin functions */ 435 switch (state->interface) { 436 case PHY_INTERFACE_MODE_TRGMII: 437 case PHY_INTERFACE_MODE_RGMII_TXID: 438 case PHY_INTERFACE_MODE_RGMII_RXID: 439 case PHY_INTERFACE_MODE_RGMII_ID: 440 case PHY_INTERFACE_MODE_RGMII: 441 case PHY_INTERFACE_MODE_MII: 442 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 443 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 444 if (err) 445 goto init_err; 446 } 447 break; 448 case PHY_INTERFACE_MODE_1000BASEX: 449 case PHY_INTERFACE_MODE_2500BASEX: 450 case PHY_INTERFACE_MODE_SGMII: 451 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 452 if (err) 453 goto init_err; 454 break; 455 case PHY_INTERFACE_MODE_GMII: 456 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 457 err = mtk_gmac_gephy_path_setup(eth, mac->id); 458 if (err) 459 goto init_err; 460 } 461 break; 462 default: 463 goto err_phy; 464 } 465 466 /* Setup clock for 1st gmac */ 467 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 468 !phy_interface_mode_is_8023z(state->interface) && 469 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 470 if (MTK_HAS_CAPS(mac->hw->soc->caps, 471 MTK_TRGMII_MT7621_CLK)) { 472 if (mt7621_gmac0_rgmii_adjust(mac->hw, 473 state->interface)) 474 goto err_phy; 475 } else { 476 mtk_gmac0_rgmii_adjust(mac->hw, 477 state->interface); 478 479 /* mt7623_pad_clk_setup */ 480 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 481 mtk_w32(mac->hw, 482 TD_DM_DRVP(8) | TD_DM_DRVN(8), 483 TRGMII_TD_ODT(i)); 484 485 /* Assert/release MT7623 RXC reset */ 486 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 487 TRGMII_RCK_CTRL); 488 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 489 } 490 } 491 492 switch (state->interface) { 493 case PHY_INTERFACE_MODE_MII: 494 case PHY_INTERFACE_MODE_GMII: 495 ge_mode = 1; 496 break; 497 default: 498 ge_mode = 0; 499 break; 500 } 501 502 /* put the gmac into the right mode */ 503 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 504 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 505 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 506 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 507 508 mac->interface = state->interface; 509 } 510 511 /* SGMII */ 512 if (state->interface == PHY_INTERFACE_MODE_SGMII || 513 phy_interface_mode_is_8023z(state->interface)) { 514 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 515 * being setup done. 516 */ 517 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 518 519 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 520 SYSCFG0_SGMII_MASK, 521 ~(u32)SYSCFG0_SGMII_MASK); 522 523 /* Save the syscfg0 value for mac_finish */ 524 mac->syscfg0 = val; 525 } else if (phylink_autoneg_inband(mode)) { 526 dev_err(eth->dev, 527 "In-band mode not supported in non SGMII mode!\n"); 528 return; 529 } 530 531 return; 532 533 err_phy: 534 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 535 mac->id, phy_modes(state->interface)); 536 return; 537 538 init_err: 539 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 540 mac->id, phy_modes(state->interface), err); 541 } 542 543 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 544 phy_interface_t interface) 545 { 546 struct mtk_mac *mac = container_of(config, struct mtk_mac, 547 phylink_config); 548 struct mtk_eth *eth = mac->hw; 549 u32 mcr_cur, mcr_new; 550 551 /* Enable SGMII */ 552 if (interface == PHY_INTERFACE_MODE_SGMII || 553 phy_interface_mode_is_8023z(interface)) 554 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 555 SYSCFG0_SGMII_MASK, mac->syscfg0); 556 557 /* Setup gmac */ 558 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 559 mcr_new = mcr_cur; 560 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 561 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK | 562 MAC_MCR_RX_FIFO_CLR_DIS; 563 564 /* Only update control register when needed! */ 565 if (mcr_new != mcr_cur) 566 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 567 568 return 0; 569 } 570 571 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 572 phy_interface_t interface) 573 { 574 struct mtk_mac *mac = container_of(config, struct mtk_mac, 575 phylink_config); 576 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 577 578 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 579 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 580 } 581 582 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 583 int speed) 584 { 585 const struct mtk_soc_data *soc = eth->soc; 586 u32 ofs, val; 587 588 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 589 return; 590 591 val = MTK_QTX_SCH_MIN_RATE_EN | 592 /* minimum: 10 Mbps */ 593 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 594 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 595 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 596 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 597 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 598 599 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 600 switch (speed) { 601 case SPEED_10: 602 val |= MTK_QTX_SCH_MAX_RATE_EN | 603 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 604 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 605 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 606 break; 607 case SPEED_100: 608 val |= MTK_QTX_SCH_MAX_RATE_EN | 609 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 610 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 611 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 612 break; 613 case SPEED_1000: 614 val |= MTK_QTX_SCH_MAX_RATE_EN | 615 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 616 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 617 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 618 break; 619 default: 620 break; 621 } 622 } else { 623 switch (speed) { 624 case SPEED_10: 625 val |= MTK_QTX_SCH_MAX_RATE_EN | 626 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 627 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 628 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 629 break; 630 case SPEED_100: 631 val |= MTK_QTX_SCH_MAX_RATE_EN | 632 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 633 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 634 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 635 break; 636 case SPEED_1000: 637 val |= MTK_QTX_SCH_MAX_RATE_EN | 638 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 639 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 640 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 641 break; 642 default: 643 break; 644 } 645 } 646 647 ofs = MTK_QTX_OFFSET * idx; 648 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 649 } 650 651 static void mtk_mac_link_up(struct phylink_config *config, 652 struct phy_device *phy, 653 unsigned int mode, phy_interface_t interface, 654 int speed, int duplex, bool tx_pause, bool rx_pause) 655 { 656 struct mtk_mac *mac = container_of(config, struct mtk_mac, 657 phylink_config); 658 u32 mcr; 659 660 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 661 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 662 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 663 MAC_MCR_FORCE_RX_FC); 664 665 /* Configure speed */ 666 mac->speed = speed; 667 switch (speed) { 668 case SPEED_2500: 669 case SPEED_1000: 670 mcr |= MAC_MCR_SPEED_1000; 671 break; 672 case SPEED_100: 673 mcr |= MAC_MCR_SPEED_100; 674 break; 675 } 676 677 /* Configure duplex */ 678 if (duplex == DUPLEX_FULL) 679 mcr |= MAC_MCR_FORCE_DPX; 680 681 /* Configure pause modes - phylink will avoid these for half duplex */ 682 if (tx_pause) 683 mcr |= MAC_MCR_FORCE_TX_FC; 684 if (rx_pause) 685 mcr |= MAC_MCR_FORCE_RX_FC; 686 687 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 688 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 689 } 690 691 static const struct phylink_mac_ops mtk_phylink_ops = { 692 .mac_select_pcs = mtk_mac_select_pcs, 693 .mac_config = mtk_mac_config, 694 .mac_finish = mtk_mac_finish, 695 .mac_link_down = mtk_mac_link_down, 696 .mac_link_up = mtk_mac_link_up, 697 }; 698 699 static int mtk_mdio_init(struct mtk_eth *eth) 700 { 701 unsigned int max_clk = 2500000, divider; 702 struct device_node *mii_np; 703 int ret; 704 u32 val; 705 706 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 707 if (!mii_np) { 708 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 709 return -ENODEV; 710 } 711 712 if (!of_device_is_available(mii_np)) { 713 ret = -ENODEV; 714 goto err_put_node; 715 } 716 717 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 718 if (!eth->mii_bus) { 719 ret = -ENOMEM; 720 goto err_put_node; 721 } 722 723 eth->mii_bus->name = "mdio"; 724 eth->mii_bus->read = mtk_mdio_read_c22; 725 eth->mii_bus->write = mtk_mdio_write_c22; 726 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 727 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 728 eth->mii_bus->priv = eth; 729 eth->mii_bus->parent = eth->dev; 730 731 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 732 733 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { 734 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { 735 dev_err(eth->dev, "MDIO clock frequency out of range"); 736 ret = -EINVAL; 737 goto err_put_node; 738 } 739 max_clk = val; 740 } 741 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 742 743 /* Configure MDC Divider */ 744 val = mtk_r32(eth, MTK_PPSC); 745 val &= ~PPSC_MDC_CFG; 746 val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO; 747 mtk_w32(eth, val, MTK_PPSC); 748 749 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); 750 751 ret = of_mdiobus_register(eth->mii_bus, mii_np); 752 753 err_put_node: 754 of_node_put(mii_np); 755 return ret; 756 } 757 758 static void mtk_mdio_cleanup(struct mtk_eth *eth) 759 { 760 if (!eth->mii_bus) 761 return; 762 763 mdiobus_unregister(eth->mii_bus); 764 } 765 766 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 767 { 768 unsigned long flags; 769 u32 val; 770 771 spin_lock_irqsave(ð->tx_irq_lock, flags); 772 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 773 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 774 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 775 } 776 777 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 778 { 779 unsigned long flags; 780 u32 val; 781 782 spin_lock_irqsave(ð->tx_irq_lock, flags); 783 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 784 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 785 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 786 } 787 788 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 789 { 790 unsigned long flags; 791 u32 val; 792 793 spin_lock_irqsave(ð->rx_irq_lock, flags); 794 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 795 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 796 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 797 } 798 799 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 800 { 801 unsigned long flags; 802 u32 val; 803 804 spin_lock_irqsave(ð->rx_irq_lock, flags); 805 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 806 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 807 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 808 } 809 810 static int mtk_set_mac_address(struct net_device *dev, void *p) 811 { 812 int ret = eth_mac_addr(dev, p); 813 struct mtk_mac *mac = netdev_priv(dev); 814 struct mtk_eth *eth = mac->hw; 815 const char *macaddr = dev->dev_addr; 816 817 if (ret) 818 return ret; 819 820 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 821 return -EBUSY; 822 823 spin_lock_bh(&mac->hw->page_lock); 824 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 825 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 826 MT7628_SDM_MAC_ADRH); 827 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 828 (macaddr[4] << 8) | macaddr[5], 829 MT7628_SDM_MAC_ADRL); 830 } else { 831 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 832 MTK_GDMA_MAC_ADRH(mac->id)); 833 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 834 (macaddr[4] << 8) | macaddr[5], 835 MTK_GDMA_MAC_ADRL(mac->id)); 836 } 837 spin_unlock_bh(&mac->hw->page_lock); 838 839 return 0; 840 } 841 842 void mtk_stats_update_mac(struct mtk_mac *mac) 843 { 844 struct mtk_hw_stats *hw_stats = mac->hw_stats; 845 struct mtk_eth *eth = mac->hw; 846 847 u64_stats_update_begin(&hw_stats->syncp); 848 849 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 850 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 851 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 852 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 853 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 854 hw_stats->rx_checksum_errors += 855 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 856 } else { 857 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 858 unsigned int offs = hw_stats->reg_offset; 859 u64 stats; 860 861 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 862 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 863 if (stats) 864 hw_stats->rx_bytes += (stats << 32); 865 hw_stats->rx_packets += 866 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 867 hw_stats->rx_overflow += 868 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 869 hw_stats->rx_fcs_errors += 870 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 871 hw_stats->rx_short_errors += 872 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 873 hw_stats->rx_long_errors += 874 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 875 hw_stats->rx_checksum_errors += 876 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 877 hw_stats->rx_flow_control_packets += 878 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 879 hw_stats->tx_skip += 880 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 881 hw_stats->tx_collisions += 882 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 883 hw_stats->tx_bytes += 884 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 885 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 886 if (stats) 887 hw_stats->tx_bytes += (stats << 32); 888 hw_stats->tx_packets += 889 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 890 } 891 892 u64_stats_update_end(&hw_stats->syncp); 893 } 894 895 static void mtk_stats_update(struct mtk_eth *eth) 896 { 897 int i; 898 899 for (i = 0; i < MTK_MAC_COUNT; i++) { 900 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 901 continue; 902 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 903 mtk_stats_update_mac(eth->mac[i]); 904 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 905 } 906 } 907 } 908 909 static void mtk_get_stats64(struct net_device *dev, 910 struct rtnl_link_stats64 *storage) 911 { 912 struct mtk_mac *mac = netdev_priv(dev); 913 struct mtk_hw_stats *hw_stats = mac->hw_stats; 914 unsigned int start; 915 916 if (netif_running(dev) && netif_device_present(dev)) { 917 if (spin_trylock_bh(&hw_stats->stats_lock)) { 918 mtk_stats_update_mac(mac); 919 spin_unlock_bh(&hw_stats->stats_lock); 920 } 921 } 922 923 do { 924 start = u64_stats_fetch_begin(&hw_stats->syncp); 925 storage->rx_packets = hw_stats->rx_packets; 926 storage->tx_packets = hw_stats->tx_packets; 927 storage->rx_bytes = hw_stats->rx_bytes; 928 storage->tx_bytes = hw_stats->tx_bytes; 929 storage->collisions = hw_stats->tx_collisions; 930 storage->rx_length_errors = hw_stats->rx_short_errors + 931 hw_stats->rx_long_errors; 932 storage->rx_over_errors = hw_stats->rx_overflow; 933 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 934 storage->rx_errors = hw_stats->rx_checksum_errors; 935 storage->tx_aborted_errors = hw_stats->tx_skip; 936 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 937 938 storage->tx_errors = dev->stats.tx_errors; 939 storage->rx_dropped = dev->stats.rx_dropped; 940 storage->tx_dropped = dev->stats.tx_dropped; 941 } 942 943 static inline int mtk_max_frag_size(int mtu) 944 { 945 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 946 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 947 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 948 949 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 950 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 951 } 952 953 static inline int mtk_max_buf_size(int frag_size) 954 { 955 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 956 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 957 958 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 959 960 return buf_size; 961 } 962 963 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 964 struct mtk_rx_dma_v2 *dma_rxd) 965 { 966 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 967 if (!(rxd->rxd2 & RX_DMA_DONE)) 968 return false; 969 970 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 971 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 972 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 973 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 974 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 975 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 976 } 977 978 return true; 979 } 980 981 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 982 { 983 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 984 unsigned long data; 985 986 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 987 get_order(size)); 988 989 return (void *)data; 990 } 991 992 /* the qdma core needs scratch memory to be setup */ 993 static int mtk_init_fq_dma(struct mtk_eth *eth) 994 { 995 const struct mtk_soc_data *soc = eth->soc; 996 dma_addr_t phy_ring_tail; 997 int cnt = MTK_QDMA_RING_SIZE; 998 dma_addr_t dma_addr; 999 int i; 1000 1001 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1002 cnt * soc->txrx.txd_size, 1003 ð->phy_scratch_ring, 1004 GFP_KERNEL); 1005 if (unlikely(!eth->scratch_ring)) 1006 return -ENOMEM; 1007 1008 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1009 if (unlikely(!eth->scratch_head)) 1010 return -ENOMEM; 1011 1012 dma_addr = dma_map_single(eth->dma_dev, 1013 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 1014 DMA_FROM_DEVICE); 1015 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1016 return -ENOMEM; 1017 1018 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 1019 1020 for (i = 0; i < cnt; i++) { 1021 struct mtk_tx_dma_v2 *txd; 1022 1023 txd = eth->scratch_ring + i * soc->txrx.txd_size; 1024 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1025 if (i < cnt - 1) 1026 txd->txd2 = eth->phy_scratch_ring + 1027 (i + 1) * soc->txrx.txd_size; 1028 1029 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1030 txd->txd4 = 0; 1031 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 1032 txd->txd5 = 0; 1033 txd->txd6 = 0; 1034 txd->txd7 = 0; 1035 txd->txd8 = 0; 1036 } 1037 } 1038 1039 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1040 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1041 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1042 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1043 1044 return 0; 1045 } 1046 1047 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1048 { 1049 return ring->dma + (desc - ring->phys); 1050 } 1051 1052 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1053 void *txd, u32 txd_size) 1054 { 1055 int idx = (txd - ring->dma) / txd_size; 1056 1057 return &ring->buf[idx]; 1058 } 1059 1060 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1061 struct mtk_tx_dma *dma) 1062 { 1063 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1064 } 1065 1066 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1067 { 1068 return (dma - ring->dma) / txd_size; 1069 } 1070 1071 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1072 struct xdp_frame_bulk *bq, bool napi) 1073 { 1074 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1075 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1076 dma_unmap_single(eth->dma_dev, 1077 dma_unmap_addr(tx_buf, dma_addr0), 1078 dma_unmap_len(tx_buf, dma_len0), 1079 DMA_TO_DEVICE); 1080 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1081 dma_unmap_page(eth->dma_dev, 1082 dma_unmap_addr(tx_buf, dma_addr0), 1083 dma_unmap_len(tx_buf, dma_len0), 1084 DMA_TO_DEVICE); 1085 } 1086 } else { 1087 if (dma_unmap_len(tx_buf, dma_len0)) { 1088 dma_unmap_page(eth->dma_dev, 1089 dma_unmap_addr(tx_buf, dma_addr0), 1090 dma_unmap_len(tx_buf, dma_len0), 1091 DMA_TO_DEVICE); 1092 } 1093 1094 if (dma_unmap_len(tx_buf, dma_len1)) { 1095 dma_unmap_page(eth->dma_dev, 1096 dma_unmap_addr(tx_buf, dma_addr1), 1097 dma_unmap_len(tx_buf, dma_len1), 1098 DMA_TO_DEVICE); 1099 } 1100 } 1101 1102 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1103 if (tx_buf->type == MTK_TYPE_SKB) { 1104 struct sk_buff *skb = tx_buf->data; 1105 1106 if (napi) 1107 napi_consume_skb(skb, napi); 1108 else 1109 dev_kfree_skb_any(skb); 1110 } else { 1111 struct xdp_frame *xdpf = tx_buf->data; 1112 1113 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1114 xdp_return_frame_rx_napi(xdpf); 1115 else if (bq) 1116 xdp_return_frame_bulk(xdpf, bq); 1117 else 1118 xdp_return_frame(xdpf); 1119 } 1120 } 1121 tx_buf->flags = 0; 1122 tx_buf->data = NULL; 1123 } 1124 1125 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1126 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1127 size_t size, int idx) 1128 { 1129 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1130 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1131 dma_unmap_len_set(tx_buf, dma_len0, size); 1132 } else { 1133 if (idx & 1) { 1134 txd->txd3 = mapped_addr; 1135 txd->txd2 |= TX_DMA_PLEN1(size); 1136 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1137 dma_unmap_len_set(tx_buf, dma_len1, size); 1138 } else { 1139 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1140 txd->txd1 = mapped_addr; 1141 txd->txd2 = TX_DMA_PLEN0(size); 1142 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1143 dma_unmap_len_set(tx_buf, dma_len0, size); 1144 } 1145 } 1146 } 1147 1148 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1149 struct mtk_tx_dma_desc_info *info) 1150 { 1151 struct mtk_mac *mac = netdev_priv(dev); 1152 struct mtk_eth *eth = mac->hw; 1153 struct mtk_tx_dma *desc = txd; 1154 u32 data; 1155 1156 WRITE_ONCE(desc->txd1, info->addr); 1157 1158 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1159 FIELD_PREP(TX_DMA_PQID, info->qid); 1160 if (info->last) 1161 data |= TX_DMA_LS0; 1162 WRITE_ONCE(desc->txd3, data); 1163 1164 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1165 if (info->first) { 1166 if (info->gso) 1167 data |= TX_DMA_TSO; 1168 /* tx checksum offload */ 1169 if (info->csum) 1170 data |= TX_DMA_CHKSUM; 1171 /* vlan header offload */ 1172 if (info->vlan) 1173 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1174 } 1175 WRITE_ONCE(desc->txd4, data); 1176 } 1177 1178 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1179 struct mtk_tx_dma_desc_info *info) 1180 { 1181 struct mtk_mac *mac = netdev_priv(dev); 1182 struct mtk_tx_dma_v2 *desc = txd; 1183 struct mtk_eth *eth = mac->hw; 1184 u32 data; 1185 1186 WRITE_ONCE(desc->txd1, info->addr); 1187 1188 data = TX_DMA_PLEN0(info->size); 1189 if (info->last) 1190 data |= TX_DMA_LS0; 1191 WRITE_ONCE(desc->txd3, data); 1192 1193 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ 1194 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1195 WRITE_ONCE(desc->txd4, data); 1196 1197 data = 0; 1198 if (info->first) { 1199 if (info->gso) 1200 data |= TX_DMA_TSO_V2; 1201 /* tx checksum offload */ 1202 if (info->csum) 1203 data |= TX_DMA_CHKSUM_V2; 1204 } 1205 WRITE_ONCE(desc->txd5, data); 1206 1207 data = 0; 1208 if (info->first && info->vlan) 1209 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1210 WRITE_ONCE(desc->txd6, data); 1211 1212 WRITE_ONCE(desc->txd7, 0); 1213 WRITE_ONCE(desc->txd8, 0); 1214 } 1215 1216 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1217 struct mtk_tx_dma_desc_info *info) 1218 { 1219 struct mtk_mac *mac = netdev_priv(dev); 1220 struct mtk_eth *eth = mac->hw; 1221 1222 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1223 mtk_tx_set_dma_desc_v2(dev, txd, info); 1224 else 1225 mtk_tx_set_dma_desc_v1(dev, txd, info); 1226 } 1227 1228 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1229 int tx_num, struct mtk_tx_ring *ring, bool gso) 1230 { 1231 struct mtk_tx_dma_desc_info txd_info = { 1232 .size = skb_headlen(skb), 1233 .gso = gso, 1234 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1235 .vlan = skb_vlan_tag_present(skb), 1236 .qid = skb_get_queue_mapping(skb), 1237 .vlan_tci = skb_vlan_tag_get(skb), 1238 .first = true, 1239 .last = !skb_is_nonlinear(skb), 1240 }; 1241 struct netdev_queue *txq; 1242 struct mtk_mac *mac = netdev_priv(dev); 1243 struct mtk_eth *eth = mac->hw; 1244 const struct mtk_soc_data *soc = eth->soc; 1245 struct mtk_tx_dma *itxd, *txd; 1246 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1247 struct mtk_tx_buf *itx_buf, *tx_buf; 1248 int i, n_desc = 1; 1249 int queue = skb_get_queue_mapping(skb); 1250 int k = 0; 1251 1252 txq = netdev_get_tx_queue(dev, queue); 1253 itxd = ring->next_free; 1254 itxd_pdma = qdma_to_pdma(ring, itxd); 1255 if (itxd == ring->last_free) 1256 return -ENOMEM; 1257 1258 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1259 memset(itx_buf, 0, sizeof(*itx_buf)); 1260 1261 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1262 DMA_TO_DEVICE); 1263 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1264 return -ENOMEM; 1265 1266 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1267 1268 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1269 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1270 MTK_TX_FLAGS_FPORT1; 1271 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1272 k++); 1273 1274 /* TX SG offload */ 1275 txd = itxd; 1276 txd_pdma = qdma_to_pdma(ring, txd); 1277 1278 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1279 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1280 unsigned int offset = 0; 1281 int frag_size = skb_frag_size(frag); 1282 1283 while (frag_size) { 1284 bool new_desc = true; 1285 1286 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1287 (i & 0x1)) { 1288 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1289 txd_pdma = qdma_to_pdma(ring, txd); 1290 if (txd == ring->last_free) 1291 goto err_dma; 1292 1293 n_desc++; 1294 } else { 1295 new_desc = false; 1296 } 1297 1298 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1299 txd_info.size = min_t(unsigned int, frag_size, 1300 soc->txrx.dma_max_len); 1301 txd_info.qid = queue; 1302 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1303 !(frag_size - txd_info.size); 1304 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1305 offset, txd_info.size, 1306 DMA_TO_DEVICE); 1307 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1308 goto err_dma; 1309 1310 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1311 1312 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1313 soc->txrx.txd_size); 1314 if (new_desc) 1315 memset(tx_buf, 0, sizeof(*tx_buf)); 1316 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1317 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1318 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1319 MTK_TX_FLAGS_FPORT1; 1320 1321 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1322 txd_info.size, k++); 1323 1324 frag_size -= txd_info.size; 1325 offset += txd_info.size; 1326 } 1327 } 1328 1329 /* store skb to cleanup */ 1330 itx_buf->type = MTK_TYPE_SKB; 1331 itx_buf->data = skb; 1332 1333 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1334 if (k & 0x1) 1335 txd_pdma->txd2 |= TX_DMA_LS0; 1336 else 1337 txd_pdma->txd2 |= TX_DMA_LS1; 1338 } 1339 1340 netdev_tx_sent_queue(txq, skb->len); 1341 skb_tx_timestamp(skb); 1342 1343 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1344 atomic_sub(n_desc, &ring->free_count); 1345 1346 /* make sure that all changes to the dma ring are flushed before we 1347 * continue 1348 */ 1349 wmb(); 1350 1351 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1352 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1353 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1354 } else { 1355 int next_idx; 1356 1357 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1358 ring->dma_size); 1359 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1360 } 1361 1362 return 0; 1363 1364 err_dma: 1365 do { 1366 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1367 1368 /* unmap dma */ 1369 mtk_tx_unmap(eth, tx_buf, NULL, false); 1370 1371 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1372 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1373 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1374 1375 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1376 itxd_pdma = qdma_to_pdma(ring, itxd); 1377 } while (itxd != txd); 1378 1379 return -ENOMEM; 1380 } 1381 1382 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1383 { 1384 int i, nfrags = 1; 1385 skb_frag_t *frag; 1386 1387 if (skb_is_gso(skb)) { 1388 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1389 frag = &skb_shinfo(skb)->frags[i]; 1390 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1391 eth->soc->txrx.dma_max_len); 1392 } 1393 } else { 1394 nfrags += skb_shinfo(skb)->nr_frags; 1395 } 1396 1397 return nfrags; 1398 } 1399 1400 static int mtk_queue_stopped(struct mtk_eth *eth) 1401 { 1402 int i; 1403 1404 for (i = 0; i < MTK_MAC_COUNT; i++) { 1405 if (!eth->netdev[i]) 1406 continue; 1407 if (netif_queue_stopped(eth->netdev[i])) 1408 return 1; 1409 } 1410 1411 return 0; 1412 } 1413 1414 static void mtk_wake_queue(struct mtk_eth *eth) 1415 { 1416 int i; 1417 1418 for (i = 0; i < MTK_MAC_COUNT; i++) { 1419 if (!eth->netdev[i]) 1420 continue; 1421 netif_tx_wake_all_queues(eth->netdev[i]); 1422 } 1423 } 1424 1425 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1426 { 1427 struct mtk_mac *mac = netdev_priv(dev); 1428 struct mtk_eth *eth = mac->hw; 1429 struct mtk_tx_ring *ring = ð->tx_ring; 1430 struct net_device_stats *stats = &dev->stats; 1431 bool gso = false; 1432 int tx_num; 1433 1434 /* normally we can rely on the stack not calling this more than once, 1435 * however we have 2 queues running on the same ring so we need to lock 1436 * the ring access 1437 */ 1438 spin_lock(ð->page_lock); 1439 1440 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1441 goto drop; 1442 1443 tx_num = mtk_cal_txd_req(eth, skb); 1444 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1445 netif_tx_stop_all_queues(dev); 1446 netif_err(eth, tx_queued, dev, 1447 "Tx Ring full when queue awake!\n"); 1448 spin_unlock(ð->page_lock); 1449 return NETDEV_TX_BUSY; 1450 } 1451 1452 /* TSO: fill MSS info in tcp checksum field */ 1453 if (skb_is_gso(skb)) { 1454 if (skb_cow_head(skb, 0)) { 1455 netif_warn(eth, tx_err, dev, 1456 "GSO expand head fail.\n"); 1457 goto drop; 1458 } 1459 1460 if (skb_shinfo(skb)->gso_type & 1461 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1462 gso = true; 1463 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1464 } 1465 } 1466 1467 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1468 goto drop; 1469 1470 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1471 netif_tx_stop_all_queues(dev); 1472 1473 spin_unlock(ð->page_lock); 1474 1475 return NETDEV_TX_OK; 1476 1477 drop: 1478 spin_unlock(ð->page_lock); 1479 stats->tx_dropped++; 1480 dev_kfree_skb_any(skb); 1481 return NETDEV_TX_OK; 1482 } 1483 1484 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1485 { 1486 int i; 1487 struct mtk_rx_ring *ring; 1488 int idx; 1489 1490 if (!eth->hwlro) 1491 return ð->rx_ring[0]; 1492 1493 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1494 struct mtk_rx_dma *rxd; 1495 1496 ring = ð->rx_ring[i]; 1497 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1498 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1499 if (rxd->rxd2 & RX_DMA_DONE) { 1500 ring->calc_idx_update = true; 1501 return ring; 1502 } 1503 } 1504 1505 return NULL; 1506 } 1507 1508 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1509 { 1510 struct mtk_rx_ring *ring; 1511 int i; 1512 1513 if (!eth->hwlro) { 1514 ring = ð->rx_ring[0]; 1515 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1516 } else { 1517 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1518 ring = ð->rx_ring[i]; 1519 if (ring->calc_idx_update) { 1520 ring->calc_idx_update = false; 1521 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1522 } 1523 } 1524 } 1525 } 1526 1527 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1528 { 1529 return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2); 1530 } 1531 1532 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1533 struct xdp_rxq_info *xdp_q, 1534 int id, int size) 1535 { 1536 struct page_pool_params pp_params = { 1537 .order = 0, 1538 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1539 .pool_size = size, 1540 .nid = NUMA_NO_NODE, 1541 .dev = eth->dma_dev, 1542 .offset = MTK_PP_HEADROOM, 1543 .max_len = MTK_PP_MAX_BUF_SIZE, 1544 }; 1545 struct page_pool *pp; 1546 int err; 1547 1548 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1549 : DMA_FROM_DEVICE; 1550 pp = page_pool_create(&pp_params); 1551 if (IS_ERR(pp)) 1552 return pp; 1553 1554 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id, 1555 eth->rx_napi.napi_id, PAGE_SIZE); 1556 if (err < 0) 1557 goto err_free_pp; 1558 1559 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1560 if (err) 1561 goto err_unregister_rxq; 1562 1563 return pp; 1564 1565 err_unregister_rxq: 1566 xdp_rxq_info_unreg(xdp_q); 1567 err_free_pp: 1568 page_pool_destroy(pp); 1569 1570 return ERR_PTR(err); 1571 } 1572 1573 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1574 gfp_t gfp_mask) 1575 { 1576 struct page *page; 1577 1578 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1579 if (!page) 1580 return NULL; 1581 1582 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1583 return page_address(page); 1584 } 1585 1586 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1587 { 1588 if (ring->page_pool) 1589 page_pool_put_full_page(ring->page_pool, 1590 virt_to_head_page(data), napi); 1591 else 1592 skb_free_frag(data); 1593 } 1594 1595 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1596 struct mtk_tx_dma_desc_info *txd_info, 1597 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1598 void *data, u16 headroom, int index, bool dma_map) 1599 { 1600 struct mtk_tx_ring *ring = ð->tx_ring; 1601 struct mtk_mac *mac = netdev_priv(dev); 1602 struct mtk_tx_dma *txd_pdma; 1603 1604 if (dma_map) { /* ndo_xdp_xmit */ 1605 txd_info->addr = dma_map_single(eth->dma_dev, data, 1606 txd_info->size, DMA_TO_DEVICE); 1607 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1608 return -ENOMEM; 1609 1610 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1611 } else { 1612 struct page *page = virt_to_head_page(data); 1613 1614 txd_info->addr = page_pool_get_dma_addr(page) + 1615 sizeof(struct xdp_frame) + headroom; 1616 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1617 txd_info->size, DMA_BIDIRECTIONAL); 1618 } 1619 mtk_tx_set_dma_desc(dev, txd, txd_info); 1620 1621 tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; 1622 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1623 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1624 1625 txd_pdma = qdma_to_pdma(ring, txd); 1626 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1627 index); 1628 1629 return 0; 1630 } 1631 1632 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1633 struct net_device *dev, bool dma_map) 1634 { 1635 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1636 const struct mtk_soc_data *soc = eth->soc; 1637 struct mtk_tx_ring *ring = ð->tx_ring; 1638 struct mtk_mac *mac = netdev_priv(dev); 1639 struct mtk_tx_dma_desc_info txd_info = { 1640 .size = xdpf->len, 1641 .first = true, 1642 .last = !xdp_frame_has_frags(xdpf), 1643 .qid = mac->id, 1644 }; 1645 int err, index = 0, n_desc = 1, nr_frags; 1646 struct mtk_tx_buf *htx_buf, *tx_buf; 1647 struct mtk_tx_dma *htxd, *txd; 1648 void *data = xdpf->data; 1649 1650 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1651 return -EBUSY; 1652 1653 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1654 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1655 return -EBUSY; 1656 1657 spin_lock(ð->page_lock); 1658 1659 txd = ring->next_free; 1660 if (txd == ring->last_free) { 1661 spin_unlock(ð->page_lock); 1662 return -ENOMEM; 1663 } 1664 htxd = txd; 1665 1666 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1667 memset(tx_buf, 0, sizeof(*tx_buf)); 1668 htx_buf = tx_buf; 1669 1670 for (;;) { 1671 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1672 data, xdpf->headroom, index, dma_map); 1673 if (err < 0) 1674 goto unmap; 1675 1676 if (txd_info.last) 1677 break; 1678 1679 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1680 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1681 if (txd == ring->last_free) 1682 goto unmap; 1683 1684 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1685 soc->txrx.txd_size); 1686 memset(tx_buf, 0, sizeof(*tx_buf)); 1687 n_desc++; 1688 } 1689 1690 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1691 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1692 txd_info.last = index + 1 == nr_frags; 1693 txd_info.qid = mac->id; 1694 data = skb_frag_address(&sinfo->frags[index]); 1695 1696 index++; 1697 } 1698 /* store xdpf for cleanup */ 1699 htx_buf->data = xdpf; 1700 1701 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1702 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1703 1704 if (index & 1) 1705 txd_pdma->txd2 |= TX_DMA_LS0; 1706 else 1707 txd_pdma->txd2 |= TX_DMA_LS1; 1708 } 1709 1710 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1711 atomic_sub(n_desc, &ring->free_count); 1712 1713 /* make sure that all changes to the dma ring are flushed before we 1714 * continue 1715 */ 1716 wmb(); 1717 1718 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1719 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1720 } else { 1721 int idx; 1722 1723 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1724 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1725 MT7628_TX_CTX_IDX0); 1726 } 1727 1728 spin_unlock(ð->page_lock); 1729 1730 return 0; 1731 1732 unmap: 1733 while (htxd != txd) { 1734 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1735 mtk_tx_unmap(eth, tx_buf, NULL, false); 1736 1737 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1738 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1739 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1740 1741 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1742 } 1743 1744 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1745 } 1746 1747 spin_unlock(ð->page_lock); 1748 1749 return err; 1750 } 1751 1752 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1753 struct xdp_frame **frames, u32 flags) 1754 { 1755 struct mtk_mac *mac = netdev_priv(dev); 1756 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1757 struct mtk_eth *eth = mac->hw; 1758 int i, nxmit = 0; 1759 1760 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1761 return -EINVAL; 1762 1763 for (i = 0; i < num_frame; i++) { 1764 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1765 break; 1766 nxmit++; 1767 } 1768 1769 u64_stats_update_begin(&hw_stats->syncp); 1770 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1771 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1772 u64_stats_update_end(&hw_stats->syncp); 1773 1774 return nxmit; 1775 } 1776 1777 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1778 struct xdp_buff *xdp, struct net_device *dev) 1779 { 1780 struct mtk_mac *mac = netdev_priv(dev); 1781 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1782 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1783 struct bpf_prog *prog; 1784 u32 act = XDP_PASS; 1785 1786 rcu_read_lock(); 1787 1788 prog = rcu_dereference(eth->prog); 1789 if (!prog) 1790 goto out; 1791 1792 act = bpf_prog_run_xdp(prog, xdp); 1793 switch (act) { 1794 case XDP_PASS: 1795 count = &hw_stats->xdp_stats.rx_xdp_pass; 1796 goto update_stats; 1797 case XDP_REDIRECT: 1798 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1799 act = XDP_DROP; 1800 break; 1801 } 1802 1803 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1804 goto update_stats; 1805 case XDP_TX: { 1806 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1807 1808 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1809 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1810 act = XDP_DROP; 1811 break; 1812 } 1813 1814 count = &hw_stats->xdp_stats.rx_xdp_tx; 1815 goto update_stats; 1816 } 1817 default: 1818 bpf_warn_invalid_xdp_action(dev, prog, act); 1819 fallthrough; 1820 case XDP_ABORTED: 1821 trace_xdp_exception(dev, prog, act); 1822 fallthrough; 1823 case XDP_DROP: 1824 break; 1825 } 1826 1827 page_pool_put_full_page(ring->page_pool, 1828 virt_to_head_page(xdp->data), true); 1829 1830 update_stats: 1831 u64_stats_update_begin(&hw_stats->syncp); 1832 *count = *count + 1; 1833 u64_stats_update_end(&hw_stats->syncp); 1834 out: 1835 rcu_read_unlock(); 1836 1837 return act; 1838 } 1839 1840 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1841 struct mtk_eth *eth) 1842 { 1843 struct dim_sample dim_sample = {}; 1844 struct mtk_rx_ring *ring; 1845 bool xdp_flush = false; 1846 int idx; 1847 struct sk_buff *skb; 1848 u8 *data, *new_data; 1849 struct mtk_rx_dma_v2 *rxd, trxd; 1850 int done = 0, bytes = 0; 1851 1852 while (done < budget) { 1853 unsigned int pktlen, *rxdcsum; 1854 struct net_device *netdev; 1855 dma_addr_t dma_addr; 1856 u32 hash, reason; 1857 int mac = 0; 1858 1859 ring = mtk_get_rx_ring(eth); 1860 if (unlikely(!ring)) 1861 goto rx_done; 1862 1863 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1864 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1865 data = ring->data[idx]; 1866 1867 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 1868 break; 1869 1870 /* find out which mac the packet come from. values start at 1 */ 1871 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1872 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; 1873 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 1874 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1875 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 1876 1877 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1878 !eth->netdev[mac])) 1879 goto release_desc; 1880 1881 netdev = eth->netdev[mac]; 1882 1883 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1884 goto release_desc; 1885 1886 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1887 1888 /* alloc new buffer */ 1889 if (ring->page_pool) { 1890 struct page *page = virt_to_head_page(data); 1891 struct xdp_buff xdp; 1892 u32 ret; 1893 1894 new_data = mtk_page_pool_get_buff(ring->page_pool, 1895 &dma_addr, 1896 GFP_ATOMIC); 1897 if (unlikely(!new_data)) { 1898 netdev->stats.rx_dropped++; 1899 goto release_desc; 1900 } 1901 1902 dma_sync_single_for_cpu(eth->dma_dev, 1903 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 1904 pktlen, page_pool_get_dma_dir(ring->page_pool)); 1905 1906 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 1907 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 1908 false); 1909 xdp_buff_clear_frags_flag(&xdp); 1910 1911 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 1912 if (ret == XDP_REDIRECT) 1913 xdp_flush = true; 1914 1915 if (ret != XDP_PASS) 1916 goto skip_rx; 1917 1918 skb = build_skb(data, PAGE_SIZE); 1919 if (unlikely(!skb)) { 1920 page_pool_put_full_page(ring->page_pool, 1921 page, true); 1922 netdev->stats.rx_dropped++; 1923 goto skip_rx; 1924 } 1925 1926 skb_reserve(skb, xdp.data - xdp.data_hard_start); 1927 skb_put(skb, xdp.data_end - xdp.data); 1928 skb_mark_for_recycle(skb); 1929 } else { 1930 if (ring->frag_size <= PAGE_SIZE) 1931 new_data = napi_alloc_frag(ring->frag_size); 1932 else 1933 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 1934 1935 if (unlikely(!new_data)) { 1936 netdev->stats.rx_dropped++; 1937 goto release_desc; 1938 } 1939 1940 dma_addr = dma_map_single(eth->dma_dev, 1941 new_data + NET_SKB_PAD + eth->ip_align, 1942 ring->buf_size, DMA_FROM_DEVICE); 1943 if (unlikely(dma_mapping_error(eth->dma_dev, 1944 dma_addr))) { 1945 skb_free_frag(new_data); 1946 netdev->stats.rx_dropped++; 1947 goto release_desc; 1948 } 1949 1950 dma_unmap_single(eth->dma_dev, trxd.rxd1, 1951 ring->buf_size, DMA_FROM_DEVICE); 1952 1953 skb = build_skb(data, ring->frag_size); 1954 if (unlikely(!skb)) { 1955 netdev->stats.rx_dropped++; 1956 skb_free_frag(data); 1957 goto skip_rx; 1958 } 1959 1960 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1961 skb_put(skb, pktlen); 1962 } 1963 1964 skb->dev = netdev; 1965 bytes += skb->len; 1966 1967 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1968 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 1969 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 1970 if (hash != MTK_RXD5_FOE_ENTRY) 1971 skb_set_hash(skb, jhash_1word(hash, 0), 1972 PKT_HASH_TYPE_L4); 1973 rxdcsum = &trxd.rxd3; 1974 } else { 1975 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 1976 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 1977 if (hash != MTK_RXD4_FOE_ENTRY) 1978 skb_set_hash(skb, jhash_1word(hash, 0), 1979 PKT_HASH_TYPE_L4); 1980 rxdcsum = &trxd.rxd4; 1981 } 1982 1983 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 1984 skb->ip_summed = CHECKSUM_UNNECESSARY; 1985 else 1986 skb_checksum_none_assert(skb); 1987 skb->protocol = eth_type_trans(skb, netdev); 1988 1989 /* When using VLAN untagging in combination with DSA, the 1990 * hardware treats the MTK special tag as a VLAN and untags it. 1991 */ 1992 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && 1993 (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) { 1994 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 1995 1996 if (port < ARRAY_SIZE(eth->dsa_meta) && 1997 eth->dsa_meta[port]) 1998 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 1999 } 2000 2001 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2002 mtk_ppe_check_skb(eth->ppe[0], skb, hash); 2003 2004 skb_record_rx_queue(skb, 0); 2005 napi_gro_receive(napi, skb); 2006 2007 skip_rx: 2008 ring->data[idx] = new_data; 2009 rxd->rxd1 = (unsigned int)dma_addr; 2010 release_desc: 2011 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2012 rxd->rxd2 = RX_DMA_LSO; 2013 else 2014 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2015 2016 ring->calc_idx = idx; 2017 done++; 2018 } 2019 2020 rx_done: 2021 if (done) { 2022 /* make sure that all changes to the dma ring are flushed before 2023 * we continue 2024 */ 2025 wmb(); 2026 mtk_update_rx_cpu_idx(eth); 2027 } 2028 2029 eth->rx_packets += done; 2030 eth->rx_bytes += bytes; 2031 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2032 &dim_sample); 2033 net_dim(ð->rx_dim, dim_sample); 2034 2035 if (xdp_flush) 2036 xdp_do_flush_map(); 2037 2038 return done; 2039 } 2040 2041 struct mtk_poll_state { 2042 struct netdev_queue *txq; 2043 unsigned int total; 2044 unsigned int done; 2045 unsigned int bytes; 2046 }; 2047 2048 static void 2049 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2050 struct sk_buff *skb) 2051 { 2052 struct netdev_queue *txq; 2053 struct net_device *dev; 2054 unsigned int bytes = skb->len; 2055 2056 state->total++; 2057 eth->tx_packets++; 2058 eth->tx_bytes += bytes; 2059 2060 dev = eth->netdev[mac]; 2061 if (!dev) 2062 return; 2063 2064 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2065 if (state->txq == txq) { 2066 state->done++; 2067 state->bytes += bytes; 2068 return; 2069 } 2070 2071 if (state->txq) 2072 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2073 2074 state->txq = txq; 2075 state->done = 1; 2076 state->bytes = bytes; 2077 } 2078 2079 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2080 struct mtk_poll_state *state) 2081 { 2082 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2083 struct mtk_tx_ring *ring = ð->tx_ring; 2084 struct mtk_tx_buf *tx_buf; 2085 struct xdp_frame_bulk bq; 2086 struct mtk_tx_dma *desc; 2087 u32 cpu, dma; 2088 2089 cpu = ring->last_free_ptr; 2090 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2091 2092 desc = mtk_qdma_phys_to_virt(ring, cpu); 2093 xdp_frame_bulk_init(&bq); 2094 2095 while ((cpu != dma) && budget) { 2096 u32 next_cpu = desc->txd2; 2097 int mac = 0; 2098 2099 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2100 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2101 break; 2102 2103 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2104 eth->soc->txrx.txd_size); 2105 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 2106 mac = 1; 2107 2108 if (!tx_buf->data) 2109 break; 2110 2111 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2112 if (tx_buf->type == MTK_TYPE_SKB) 2113 mtk_poll_tx_done(eth, state, mac, tx_buf->data); 2114 2115 budget--; 2116 } 2117 mtk_tx_unmap(eth, tx_buf, &bq, true); 2118 2119 ring->last_free = desc; 2120 atomic_inc(&ring->free_count); 2121 2122 cpu = next_cpu; 2123 } 2124 xdp_flush_frame_bulk(&bq); 2125 2126 ring->last_free_ptr = cpu; 2127 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2128 2129 return budget; 2130 } 2131 2132 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2133 struct mtk_poll_state *state) 2134 { 2135 struct mtk_tx_ring *ring = ð->tx_ring; 2136 struct mtk_tx_buf *tx_buf; 2137 struct xdp_frame_bulk bq; 2138 struct mtk_tx_dma *desc; 2139 u32 cpu, dma; 2140 2141 cpu = ring->cpu_idx; 2142 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2143 xdp_frame_bulk_init(&bq); 2144 2145 while ((cpu != dma) && budget) { 2146 tx_buf = &ring->buf[cpu]; 2147 if (!tx_buf->data) 2148 break; 2149 2150 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2151 if (tx_buf->type == MTK_TYPE_SKB) 2152 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2153 budget--; 2154 } 2155 mtk_tx_unmap(eth, tx_buf, &bq, true); 2156 2157 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2158 ring->last_free = desc; 2159 atomic_inc(&ring->free_count); 2160 2161 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2162 } 2163 xdp_flush_frame_bulk(&bq); 2164 2165 ring->cpu_idx = cpu; 2166 2167 return budget; 2168 } 2169 2170 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2171 { 2172 struct mtk_tx_ring *ring = ð->tx_ring; 2173 struct dim_sample dim_sample = {}; 2174 struct mtk_poll_state state = {}; 2175 2176 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2177 budget = mtk_poll_tx_qdma(eth, budget, &state); 2178 else 2179 budget = mtk_poll_tx_pdma(eth, budget, &state); 2180 2181 if (state.txq) 2182 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2183 2184 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2185 &dim_sample); 2186 net_dim(ð->tx_dim, dim_sample); 2187 2188 if (mtk_queue_stopped(eth) && 2189 (atomic_read(&ring->free_count) > ring->thresh)) 2190 mtk_wake_queue(eth); 2191 2192 return state.total; 2193 } 2194 2195 static void mtk_handle_status_irq(struct mtk_eth *eth) 2196 { 2197 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2198 2199 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2200 mtk_stats_update(eth); 2201 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2202 MTK_INT_STATUS2); 2203 } 2204 } 2205 2206 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2207 { 2208 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2209 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2210 int tx_done = 0; 2211 2212 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2213 mtk_handle_status_irq(eth); 2214 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2215 tx_done = mtk_poll_tx(eth, budget); 2216 2217 if (unlikely(netif_msg_intr(eth))) { 2218 dev_info(eth->dev, 2219 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2220 mtk_r32(eth, reg_map->tx_irq_status), 2221 mtk_r32(eth, reg_map->tx_irq_mask)); 2222 } 2223 2224 if (tx_done == budget) 2225 return budget; 2226 2227 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2228 return budget; 2229 2230 if (napi_complete_done(napi, tx_done)) 2231 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2232 2233 return tx_done; 2234 } 2235 2236 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2237 { 2238 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2239 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2240 int rx_done_total = 0; 2241 2242 mtk_handle_status_irq(eth); 2243 2244 do { 2245 int rx_done; 2246 2247 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2248 reg_map->pdma.irq_status); 2249 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2250 rx_done_total += rx_done; 2251 2252 if (unlikely(netif_msg_intr(eth))) { 2253 dev_info(eth->dev, 2254 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2255 mtk_r32(eth, reg_map->pdma.irq_status), 2256 mtk_r32(eth, reg_map->pdma.irq_mask)); 2257 } 2258 2259 if (rx_done_total == budget) 2260 return budget; 2261 2262 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2263 eth->soc->txrx.rx_irq_done_mask); 2264 2265 if (napi_complete_done(napi, rx_done_total)) 2266 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2267 2268 return rx_done_total; 2269 } 2270 2271 static int mtk_tx_alloc(struct mtk_eth *eth) 2272 { 2273 const struct mtk_soc_data *soc = eth->soc; 2274 struct mtk_tx_ring *ring = ð->tx_ring; 2275 int i, sz = soc->txrx.txd_size; 2276 struct mtk_tx_dma_v2 *txd; 2277 int ring_size; 2278 u32 ofs, val; 2279 2280 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2281 ring_size = MTK_QDMA_RING_SIZE; 2282 else 2283 ring_size = MTK_DMA_SIZE; 2284 2285 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2286 GFP_KERNEL); 2287 if (!ring->buf) 2288 goto no_tx_mem; 2289 2290 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2291 &ring->phys, GFP_KERNEL); 2292 if (!ring->dma) 2293 goto no_tx_mem; 2294 2295 for (i = 0; i < ring_size; i++) { 2296 int next = (i + 1) % ring_size; 2297 u32 next_ptr = ring->phys + next * sz; 2298 2299 txd = ring->dma + i * sz; 2300 txd->txd2 = next_ptr; 2301 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2302 txd->txd4 = 0; 2303 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 2304 txd->txd5 = 0; 2305 txd->txd6 = 0; 2306 txd->txd7 = 0; 2307 txd->txd8 = 0; 2308 } 2309 } 2310 2311 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2312 * only as the framework. The real HW descriptors are the PDMA 2313 * descriptors in ring->dma_pdma. 2314 */ 2315 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2316 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2317 &ring->phys_pdma, GFP_KERNEL); 2318 if (!ring->dma_pdma) 2319 goto no_tx_mem; 2320 2321 for (i = 0; i < ring_size; i++) { 2322 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2323 ring->dma_pdma[i].txd4 = 0; 2324 } 2325 } 2326 2327 ring->dma_size = ring_size; 2328 atomic_set(&ring->free_count, ring_size - 2); 2329 ring->next_free = ring->dma; 2330 ring->last_free = (void *)txd; 2331 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2332 ring->thresh = MAX_SKB_FRAGS; 2333 2334 /* make sure that all changes to the dma ring are flushed before we 2335 * continue 2336 */ 2337 wmb(); 2338 2339 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2340 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2341 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2342 mtk_w32(eth, 2343 ring->phys + ((ring_size - 1) * sz), 2344 soc->reg_map->qdma.crx_ptr); 2345 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2346 2347 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2348 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2349 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2350 2351 val = MTK_QTX_SCH_MIN_RATE_EN | 2352 /* minimum: 10 Mbps */ 2353 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2354 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2355 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2356 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2357 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2358 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2359 ofs += MTK_QTX_OFFSET; 2360 } 2361 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2362 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2363 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2364 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2365 } else { 2366 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2367 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2368 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2369 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2370 } 2371 2372 return 0; 2373 2374 no_tx_mem: 2375 return -ENOMEM; 2376 } 2377 2378 static void mtk_tx_clean(struct mtk_eth *eth) 2379 { 2380 const struct mtk_soc_data *soc = eth->soc; 2381 struct mtk_tx_ring *ring = ð->tx_ring; 2382 int i; 2383 2384 if (ring->buf) { 2385 for (i = 0; i < ring->dma_size; i++) 2386 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2387 kfree(ring->buf); 2388 ring->buf = NULL; 2389 } 2390 2391 if (ring->dma) { 2392 dma_free_coherent(eth->dma_dev, 2393 ring->dma_size * soc->txrx.txd_size, 2394 ring->dma, ring->phys); 2395 ring->dma = NULL; 2396 } 2397 2398 if (ring->dma_pdma) { 2399 dma_free_coherent(eth->dma_dev, 2400 ring->dma_size * soc->txrx.txd_size, 2401 ring->dma_pdma, ring->phys_pdma); 2402 ring->dma_pdma = NULL; 2403 } 2404 } 2405 2406 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2407 { 2408 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2409 struct mtk_rx_ring *ring; 2410 int rx_data_len, rx_dma_size; 2411 int i; 2412 2413 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2414 if (ring_no) 2415 return -EINVAL; 2416 ring = ð->rx_ring_qdma; 2417 } else { 2418 ring = ð->rx_ring[ring_no]; 2419 } 2420 2421 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2422 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2423 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2424 } else { 2425 rx_data_len = ETH_DATA_LEN; 2426 rx_dma_size = MTK_DMA_SIZE; 2427 } 2428 2429 ring->frag_size = mtk_max_frag_size(rx_data_len); 2430 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2431 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2432 GFP_KERNEL); 2433 if (!ring->data) 2434 return -ENOMEM; 2435 2436 if (mtk_page_pool_enabled(eth)) { 2437 struct page_pool *pp; 2438 2439 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2440 rx_dma_size); 2441 if (IS_ERR(pp)) 2442 return PTR_ERR(pp); 2443 2444 ring->page_pool = pp; 2445 } 2446 2447 ring->dma = dma_alloc_coherent(eth->dma_dev, 2448 rx_dma_size * eth->soc->txrx.rxd_size, 2449 &ring->phys, GFP_KERNEL); 2450 if (!ring->dma) 2451 return -ENOMEM; 2452 2453 for (i = 0; i < rx_dma_size; i++) { 2454 struct mtk_rx_dma_v2 *rxd; 2455 dma_addr_t dma_addr; 2456 void *data; 2457 2458 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2459 if (ring->page_pool) { 2460 data = mtk_page_pool_get_buff(ring->page_pool, 2461 &dma_addr, GFP_KERNEL); 2462 if (!data) 2463 return -ENOMEM; 2464 } else { 2465 if (ring->frag_size <= PAGE_SIZE) 2466 data = netdev_alloc_frag(ring->frag_size); 2467 else 2468 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2469 2470 if (!data) 2471 return -ENOMEM; 2472 2473 dma_addr = dma_map_single(eth->dma_dev, 2474 data + NET_SKB_PAD + eth->ip_align, 2475 ring->buf_size, DMA_FROM_DEVICE); 2476 if (unlikely(dma_mapping_error(eth->dma_dev, 2477 dma_addr))) { 2478 skb_free_frag(data); 2479 return -ENOMEM; 2480 } 2481 } 2482 rxd->rxd1 = (unsigned int)dma_addr; 2483 ring->data[i] = data; 2484 2485 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2486 rxd->rxd2 = RX_DMA_LSO; 2487 else 2488 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2489 2490 rxd->rxd3 = 0; 2491 rxd->rxd4 = 0; 2492 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2493 rxd->rxd5 = 0; 2494 rxd->rxd6 = 0; 2495 rxd->rxd7 = 0; 2496 rxd->rxd8 = 0; 2497 } 2498 } 2499 2500 ring->dma_size = rx_dma_size; 2501 ring->calc_idx_update = false; 2502 ring->calc_idx = rx_dma_size - 1; 2503 if (rx_flag == MTK_RX_FLAGS_QDMA) 2504 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2505 ring_no * MTK_QRX_OFFSET; 2506 else 2507 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2508 ring_no * MTK_QRX_OFFSET; 2509 /* make sure that all changes to the dma ring are flushed before we 2510 * continue 2511 */ 2512 wmb(); 2513 2514 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2515 mtk_w32(eth, ring->phys, 2516 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2517 mtk_w32(eth, rx_dma_size, 2518 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2519 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2520 reg_map->qdma.rst_idx); 2521 } else { 2522 mtk_w32(eth, ring->phys, 2523 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2524 mtk_w32(eth, rx_dma_size, 2525 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2526 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2527 reg_map->pdma.rst_idx); 2528 } 2529 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2530 2531 return 0; 2532 } 2533 2534 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 2535 { 2536 int i; 2537 2538 if (ring->data && ring->dma) { 2539 for (i = 0; i < ring->dma_size; i++) { 2540 struct mtk_rx_dma *rxd; 2541 2542 if (!ring->data[i]) 2543 continue; 2544 2545 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2546 if (!rxd->rxd1) 2547 continue; 2548 2549 dma_unmap_single(eth->dma_dev, rxd->rxd1, 2550 ring->buf_size, DMA_FROM_DEVICE); 2551 mtk_rx_put_buff(ring, ring->data[i], false); 2552 } 2553 kfree(ring->data); 2554 ring->data = NULL; 2555 } 2556 2557 if (ring->dma) { 2558 dma_free_coherent(eth->dma_dev, 2559 ring->dma_size * eth->soc->txrx.rxd_size, 2560 ring->dma, ring->phys); 2561 ring->dma = NULL; 2562 } 2563 2564 if (ring->page_pool) { 2565 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2566 xdp_rxq_info_unreg(&ring->xdp_q); 2567 page_pool_destroy(ring->page_pool); 2568 ring->page_pool = NULL; 2569 } 2570 } 2571 2572 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2573 { 2574 int i; 2575 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2576 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2577 2578 /* set LRO rings to auto-learn modes */ 2579 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2580 2581 /* validate LRO ring */ 2582 ring_ctrl_dw2 |= MTK_RING_VLD; 2583 2584 /* set AGE timer (unit: 20us) */ 2585 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2586 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2587 2588 /* set max AGG timer (unit: 20us) */ 2589 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2590 2591 /* set max LRO AGG count */ 2592 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2593 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2594 2595 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2596 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2597 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2598 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2599 } 2600 2601 /* IPv4 checksum update enable */ 2602 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2603 2604 /* switch priority comparison to packet count mode */ 2605 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2606 2607 /* bandwidth threshold setting */ 2608 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2609 2610 /* auto-learn score delta setting */ 2611 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2612 2613 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2614 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2615 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2616 2617 /* set HW LRO mode & the max aggregation count for rx packets */ 2618 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2619 2620 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2621 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2622 2623 /* enable HW LRO */ 2624 lro_ctrl_dw0 |= MTK_LRO_EN; 2625 2626 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2627 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2628 2629 return 0; 2630 } 2631 2632 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2633 { 2634 int i; 2635 u32 val; 2636 2637 /* relinquish lro rings, flush aggregated packets */ 2638 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2639 2640 /* wait for relinquishments done */ 2641 for (i = 0; i < 10; i++) { 2642 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2643 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2644 msleep(20); 2645 continue; 2646 } 2647 break; 2648 } 2649 2650 /* invalidate lro rings */ 2651 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2652 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2653 2654 /* disable HW LRO */ 2655 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2656 } 2657 2658 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2659 { 2660 u32 reg_val; 2661 2662 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2663 2664 /* invalidate the IP setting */ 2665 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2666 2667 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2668 2669 /* validate the IP setting */ 2670 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2671 } 2672 2673 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2674 { 2675 u32 reg_val; 2676 2677 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2678 2679 /* invalidate the IP setting */ 2680 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2681 2682 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2683 } 2684 2685 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2686 { 2687 int cnt = 0; 2688 int i; 2689 2690 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2691 if (mac->hwlro_ip[i]) 2692 cnt++; 2693 } 2694 2695 return cnt; 2696 } 2697 2698 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2699 struct ethtool_rxnfc *cmd) 2700 { 2701 struct ethtool_rx_flow_spec *fsp = 2702 (struct ethtool_rx_flow_spec *)&cmd->fs; 2703 struct mtk_mac *mac = netdev_priv(dev); 2704 struct mtk_eth *eth = mac->hw; 2705 int hwlro_idx; 2706 2707 if ((fsp->flow_type != TCP_V4_FLOW) || 2708 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2709 (fsp->location > 1)) 2710 return -EINVAL; 2711 2712 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2713 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2714 2715 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2716 2717 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2718 2719 return 0; 2720 } 2721 2722 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2723 struct ethtool_rxnfc *cmd) 2724 { 2725 struct ethtool_rx_flow_spec *fsp = 2726 (struct ethtool_rx_flow_spec *)&cmd->fs; 2727 struct mtk_mac *mac = netdev_priv(dev); 2728 struct mtk_eth *eth = mac->hw; 2729 int hwlro_idx; 2730 2731 if (fsp->location > 1) 2732 return -EINVAL; 2733 2734 mac->hwlro_ip[fsp->location] = 0; 2735 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2736 2737 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2738 2739 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2740 2741 return 0; 2742 } 2743 2744 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2745 { 2746 struct mtk_mac *mac = netdev_priv(dev); 2747 struct mtk_eth *eth = mac->hw; 2748 int i, hwlro_idx; 2749 2750 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2751 mac->hwlro_ip[i] = 0; 2752 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2753 2754 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2755 } 2756 2757 mac->hwlro_ip_cnt = 0; 2758 } 2759 2760 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2761 struct ethtool_rxnfc *cmd) 2762 { 2763 struct mtk_mac *mac = netdev_priv(dev); 2764 struct ethtool_rx_flow_spec *fsp = 2765 (struct ethtool_rx_flow_spec *)&cmd->fs; 2766 2767 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2768 return -EINVAL; 2769 2770 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2771 fsp->flow_type = TCP_V4_FLOW; 2772 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2773 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2774 2775 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2776 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2777 fsp->h_u.tcp_ip4_spec.psrc = 0; 2778 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2779 fsp->h_u.tcp_ip4_spec.pdst = 0; 2780 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2781 fsp->h_u.tcp_ip4_spec.tos = 0; 2782 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2783 2784 return 0; 2785 } 2786 2787 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2788 struct ethtool_rxnfc *cmd, 2789 u32 *rule_locs) 2790 { 2791 struct mtk_mac *mac = netdev_priv(dev); 2792 int cnt = 0; 2793 int i; 2794 2795 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2796 if (mac->hwlro_ip[i]) { 2797 rule_locs[cnt] = i; 2798 cnt++; 2799 } 2800 } 2801 2802 cmd->rule_cnt = cnt; 2803 2804 return 0; 2805 } 2806 2807 static netdev_features_t mtk_fix_features(struct net_device *dev, 2808 netdev_features_t features) 2809 { 2810 if (!(features & NETIF_F_LRO)) { 2811 struct mtk_mac *mac = netdev_priv(dev); 2812 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2813 2814 if (ip_cnt) { 2815 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2816 2817 features |= NETIF_F_LRO; 2818 } 2819 } 2820 2821 return features; 2822 } 2823 2824 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2825 { 2826 netdev_features_t diff = dev->features ^ features; 2827 2828 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 2829 mtk_hwlro_netdev_disable(dev); 2830 2831 return 0; 2832 } 2833 2834 /* wait for DMA to finish whatever it is doing before we start using it again */ 2835 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2836 { 2837 unsigned int reg; 2838 int ret; 2839 u32 val; 2840 2841 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2842 reg = eth->soc->reg_map->qdma.glo_cfg; 2843 else 2844 reg = eth->soc->reg_map->pdma.glo_cfg; 2845 2846 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2847 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2848 5, MTK_DMA_BUSY_TIMEOUT_US); 2849 if (ret) 2850 dev_err(eth->dev, "DMA init timeout\n"); 2851 2852 return ret; 2853 } 2854 2855 static int mtk_dma_init(struct mtk_eth *eth) 2856 { 2857 int err; 2858 u32 i; 2859 2860 if (mtk_dma_busy_wait(eth)) 2861 return -EBUSY; 2862 2863 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2864 /* QDMA needs scratch memory for internal reordering of the 2865 * descriptors 2866 */ 2867 err = mtk_init_fq_dma(eth); 2868 if (err) 2869 return err; 2870 } 2871 2872 err = mtk_tx_alloc(eth); 2873 if (err) 2874 return err; 2875 2876 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2877 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2878 if (err) 2879 return err; 2880 } 2881 2882 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2883 if (err) 2884 return err; 2885 2886 if (eth->hwlro) { 2887 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2888 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2889 if (err) 2890 return err; 2891 } 2892 err = mtk_hwlro_rx_init(eth); 2893 if (err) 2894 return err; 2895 } 2896 2897 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2898 /* Enable random early drop and set drop threshold 2899 * automatically 2900 */ 2901 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2902 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 2903 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 2904 } 2905 2906 return 0; 2907 } 2908 2909 static void mtk_dma_free(struct mtk_eth *eth) 2910 { 2911 const struct mtk_soc_data *soc = eth->soc; 2912 int i; 2913 2914 for (i = 0; i < MTK_MAC_COUNT; i++) 2915 if (eth->netdev[i]) 2916 netdev_reset_queue(eth->netdev[i]); 2917 if (eth->scratch_ring) { 2918 dma_free_coherent(eth->dma_dev, 2919 MTK_QDMA_RING_SIZE * soc->txrx.txd_size, 2920 eth->scratch_ring, eth->phy_scratch_ring); 2921 eth->scratch_ring = NULL; 2922 eth->phy_scratch_ring = 0; 2923 } 2924 mtk_tx_clean(eth); 2925 mtk_rx_clean(eth, ð->rx_ring[0]); 2926 mtk_rx_clean(eth, ð->rx_ring_qdma); 2927 2928 if (eth->hwlro) { 2929 mtk_hwlro_rx_uninit(eth); 2930 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2931 mtk_rx_clean(eth, ð->rx_ring[i]); 2932 } 2933 2934 kfree(eth->scratch_head); 2935 } 2936 2937 static bool mtk_hw_reset_check(struct mtk_eth *eth) 2938 { 2939 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 2940 2941 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 2942 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 2943 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 2944 } 2945 2946 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2947 { 2948 struct mtk_mac *mac = netdev_priv(dev); 2949 struct mtk_eth *eth = mac->hw; 2950 2951 if (test_bit(MTK_RESETTING, ð->state)) 2952 return; 2953 2954 if (!mtk_hw_reset_check(eth)) 2955 return; 2956 2957 eth->netdev[mac->id]->stats.tx_errors++; 2958 netif_err(eth, tx_err, dev, "transmit timed out\n"); 2959 2960 schedule_work(ð->pending_work); 2961 } 2962 2963 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2964 { 2965 struct mtk_eth *eth = _eth; 2966 2967 eth->rx_events++; 2968 if (likely(napi_schedule_prep(ð->rx_napi))) { 2969 __napi_schedule(ð->rx_napi); 2970 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 2971 } 2972 2973 return IRQ_HANDLED; 2974 } 2975 2976 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2977 { 2978 struct mtk_eth *eth = _eth; 2979 2980 eth->tx_events++; 2981 if (likely(napi_schedule_prep(ð->tx_napi))) { 2982 __napi_schedule(ð->tx_napi); 2983 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2984 } 2985 2986 return IRQ_HANDLED; 2987 } 2988 2989 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2990 { 2991 struct mtk_eth *eth = _eth; 2992 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2993 2994 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 2995 eth->soc->txrx.rx_irq_done_mask) { 2996 if (mtk_r32(eth, reg_map->pdma.irq_status) & 2997 eth->soc->txrx.rx_irq_done_mask) 2998 mtk_handle_irq_rx(irq, _eth); 2999 } 3000 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3001 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3002 mtk_handle_irq_tx(irq, _eth); 3003 } 3004 3005 return IRQ_HANDLED; 3006 } 3007 3008 #ifdef CONFIG_NET_POLL_CONTROLLER 3009 static void mtk_poll_controller(struct net_device *dev) 3010 { 3011 struct mtk_mac *mac = netdev_priv(dev); 3012 struct mtk_eth *eth = mac->hw; 3013 3014 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3015 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3016 mtk_handle_irq_rx(eth->irq[2], dev); 3017 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3018 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 3019 } 3020 #endif 3021 3022 static int mtk_start_dma(struct mtk_eth *eth) 3023 { 3024 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3025 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3026 int err; 3027 3028 err = mtk_dma_init(eth); 3029 if (err) { 3030 mtk_dma_free(eth); 3031 return err; 3032 } 3033 3034 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3035 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3036 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3037 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3038 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3039 3040 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3041 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3042 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3043 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3044 else 3045 val |= MTK_RX_BT_32DWORDS; 3046 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3047 3048 mtk_w32(eth, 3049 MTK_RX_DMA_EN | rx_2b_offset | 3050 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3051 reg_map->pdma.glo_cfg); 3052 } else { 3053 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3054 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3055 reg_map->pdma.glo_cfg); 3056 } 3057 3058 return 0; 3059 } 3060 3061 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 3062 { 3063 int i; 3064 3065 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3066 return; 3067 3068 for (i = 0; i < MTK_MAC_COUNT; i++) { 3069 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3070 3071 /* default setup the forward port to send frame to PDMA */ 3072 val &= ~0xffff; 3073 3074 /* Enable RX checksum */ 3075 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3076 3077 val |= config; 3078 3079 if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i])) 3080 val |= MTK_GDMA_SPECIAL_TAG; 3081 3082 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 3083 } 3084 /* Reset and enable PSE */ 3085 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3086 mtk_w32(eth, 0, MTK_RST_GL); 3087 } 3088 3089 3090 static bool mtk_uses_dsa(struct net_device *dev) 3091 { 3092 #if IS_ENABLED(CONFIG_NET_DSA) 3093 return netdev_uses_dsa(dev) && 3094 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3095 #else 3096 return false; 3097 #endif 3098 } 3099 3100 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3101 { 3102 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3103 struct mtk_eth *eth = mac->hw; 3104 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3105 struct ethtool_link_ksettings s; 3106 struct net_device *ldev; 3107 struct list_head *iter; 3108 struct dsa_port *dp; 3109 3110 if (event != NETDEV_CHANGE) 3111 return NOTIFY_DONE; 3112 3113 netdev_for_each_lower_dev(dev, ldev, iter) { 3114 if (netdev_priv(ldev) == mac) 3115 goto found; 3116 } 3117 3118 return NOTIFY_DONE; 3119 3120 found: 3121 if (!dsa_slave_dev_check(dev)) 3122 return NOTIFY_DONE; 3123 3124 if (__ethtool_get_link_ksettings(dev, &s)) 3125 return NOTIFY_DONE; 3126 3127 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3128 return NOTIFY_DONE; 3129 3130 dp = dsa_port_from_netdev(dev); 3131 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3132 return NOTIFY_DONE; 3133 3134 if (mac->speed > 0 && mac->speed <= s.base.speed) 3135 s.base.speed = 0; 3136 3137 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3138 3139 return NOTIFY_DONE; 3140 } 3141 3142 static int mtk_open(struct net_device *dev) 3143 { 3144 struct mtk_mac *mac = netdev_priv(dev); 3145 struct mtk_eth *eth = mac->hw; 3146 int i, err; 3147 3148 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3149 if (err) { 3150 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3151 err); 3152 return err; 3153 } 3154 3155 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3156 if (!refcount_read(ð->dma_refcnt)) { 3157 const struct mtk_soc_data *soc = eth->soc; 3158 u32 gdm_config; 3159 int i; 3160 3161 err = mtk_start_dma(eth); 3162 if (err) { 3163 phylink_disconnect_phy(mac->phylink); 3164 return err; 3165 } 3166 3167 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3168 mtk_ppe_start(eth->ppe[i]); 3169 3170 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe 3171 : MTK_GDMA_TO_PDMA; 3172 mtk_gdm_config(eth, gdm_config); 3173 3174 napi_enable(ð->tx_napi); 3175 napi_enable(ð->rx_napi); 3176 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3177 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); 3178 refcount_set(ð->dma_refcnt, 1); 3179 } 3180 else 3181 refcount_inc(ð->dma_refcnt); 3182 3183 phylink_start(mac->phylink); 3184 netif_tx_start_all_queues(dev); 3185 3186 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3187 return 0; 3188 3189 if (mtk_uses_dsa(dev) && !eth->prog) { 3190 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3191 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3192 3193 if (md_dst) 3194 continue; 3195 3196 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3197 GFP_KERNEL); 3198 if (!md_dst) 3199 return -ENOMEM; 3200 3201 md_dst->u.port_info.port_id = i; 3202 eth->dsa_meta[i] = md_dst; 3203 } 3204 } else { 3205 /* Hardware DSA untagging and VLAN RX offloading need to be 3206 * disabled if at least one MAC does not use DSA. 3207 */ 3208 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3209 3210 val &= ~MTK_CDMP_STAG_EN; 3211 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3212 3213 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); 3214 } 3215 3216 return 0; 3217 } 3218 3219 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3220 { 3221 u32 val; 3222 int i; 3223 3224 /* stop the dma engine */ 3225 spin_lock_bh(ð->page_lock); 3226 val = mtk_r32(eth, glo_cfg); 3227 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3228 glo_cfg); 3229 spin_unlock_bh(ð->page_lock); 3230 3231 /* wait for dma stop */ 3232 for (i = 0; i < 10; i++) { 3233 val = mtk_r32(eth, glo_cfg); 3234 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3235 msleep(20); 3236 continue; 3237 } 3238 break; 3239 } 3240 } 3241 3242 static int mtk_stop(struct net_device *dev) 3243 { 3244 struct mtk_mac *mac = netdev_priv(dev); 3245 struct mtk_eth *eth = mac->hw; 3246 int i; 3247 3248 phylink_stop(mac->phylink); 3249 3250 netif_tx_disable(dev); 3251 3252 phylink_disconnect_phy(mac->phylink); 3253 3254 /* only shutdown DMA if this is the last user */ 3255 if (!refcount_dec_and_test(ð->dma_refcnt)) 3256 return 0; 3257 3258 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3259 3260 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3261 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3262 napi_disable(ð->tx_napi); 3263 napi_disable(ð->rx_napi); 3264 3265 cancel_work_sync(ð->rx_dim.work); 3266 cancel_work_sync(ð->tx_dim.work); 3267 3268 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3269 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3270 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3271 3272 mtk_dma_free(eth); 3273 3274 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3275 mtk_ppe_stop(eth->ppe[i]); 3276 3277 return 0; 3278 } 3279 3280 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3281 struct netlink_ext_ack *extack) 3282 { 3283 struct mtk_mac *mac = netdev_priv(dev); 3284 struct mtk_eth *eth = mac->hw; 3285 struct bpf_prog *old_prog; 3286 bool need_update; 3287 3288 if (eth->hwlro) { 3289 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3290 return -EOPNOTSUPP; 3291 } 3292 3293 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3294 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3295 return -EOPNOTSUPP; 3296 } 3297 3298 need_update = !!eth->prog != !!prog; 3299 if (netif_running(dev) && need_update) 3300 mtk_stop(dev); 3301 3302 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3303 if (old_prog) 3304 bpf_prog_put(old_prog); 3305 3306 if (netif_running(dev) && need_update) 3307 return mtk_open(dev); 3308 3309 return 0; 3310 } 3311 3312 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3313 { 3314 switch (xdp->command) { 3315 case XDP_SETUP_PROG: 3316 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3317 default: 3318 return -EINVAL; 3319 } 3320 } 3321 3322 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3323 { 3324 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3325 reset_bits, 3326 reset_bits); 3327 3328 usleep_range(1000, 1100); 3329 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3330 reset_bits, 3331 ~reset_bits); 3332 mdelay(10); 3333 } 3334 3335 static void mtk_clk_disable(struct mtk_eth *eth) 3336 { 3337 int clk; 3338 3339 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3340 clk_disable_unprepare(eth->clks[clk]); 3341 } 3342 3343 static int mtk_clk_enable(struct mtk_eth *eth) 3344 { 3345 int clk, ret; 3346 3347 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3348 ret = clk_prepare_enable(eth->clks[clk]); 3349 if (ret) 3350 goto err_disable_clks; 3351 } 3352 3353 return 0; 3354 3355 err_disable_clks: 3356 while (--clk >= 0) 3357 clk_disable_unprepare(eth->clks[clk]); 3358 3359 return ret; 3360 } 3361 3362 static void mtk_dim_rx(struct work_struct *work) 3363 { 3364 struct dim *dim = container_of(work, struct dim, work); 3365 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3366 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3367 struct dim_cq_moder cur_profile; 3368 u32 val, cur; 3369 3370 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3371 dim->profile_ix); 3372 spin_lock_bh(ð->dim_lock); 3373 3374 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3375 val &= MTK_PDMA_DELAY_TX_MASK; 3376 val |= MTK_PDMA_DELAY_RX_EN; 3377 3378 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3379 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3380 3381 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3382 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3383 3384 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3385 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3386 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3387 3388 spin_unlock_bh(ð->dim_lock); 3389 3390 dim->state = DIM_START_MEASURE; 3391 } 3392 3393 static void mtk_dim_tx(struct work_struct *work) 3394 { 3395 struct dim *dim = container_of(work, struct dim, work); 3396 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3397 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3398 struct dim_cq_moder cur_profile; 3399 u32 val, cur; 3400 3401 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3402 dim->profile_ix); 3403 spin_lock_bh(ð->dim_lock); 3404 3405 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3406 val &= MTK_PDMA_DELAY_RX_MASK; 3407 val |= MTK_PDMA_DELAY_TX_EN; 3408 3409 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3410 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3411 3412 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3413 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3414 3415 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3416 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3417 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3418 3419 spin_unlock_bh(ð->dim_lock); 3420 3421 dim->state = DIM_START_MEASURE; 3422 } 3423 3424 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3425 { 3426 struct mtk_eth *eth = mac->hw; 3427 u32 mcr_cur, mcr_new; 3428 3429 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3430 return; 3431 3432 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3433 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3434 3435 if (val <= 1518) 3436 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3437 else if (val <= 1536) 3438 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3439 else if (val <= 1552) 3440 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3441 else 3442 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3443 3444 if (mcr_new != mcr_cur) 3445 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3446 } 3447 3448 static void mtk_hw_reset(struct mtk_eth *eth) 3449 { 3450 u32 val; 3451 3452 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3453 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3454 val = RSTCTRL_PPE0_V2; 3455 } else { 3456 val = RSTCTRL_PPE0; 3457 } 3458 3459 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3460 val |= RSTCTRL_PPE1; 3461 3462 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3463 3464 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3465 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3466 0x3ffffff); 3467 } 3468 3469 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3470 { 3471 u32 val; 3472 3473 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3474 return val; 3475 } 3476 3477 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3478 { 3479 u32 rst_mask, val; 3480 3481 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3482 RSTCTRL_FE); 3483 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3484 val & RSTCTRL_FE, 1, 1000)) { 3485 dev_err(eth->dev, "warm reset failed\n"); 3486 mtk_hw_reset(eth); 3487 return; 3488 } 3489 3490 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3491 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3492 else 3493 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3494 3495 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3496 rst_mask |= RSTCTRL_PPE1; 3497 3498 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3499 3500 udelay(1); 3501 val = mtk_hw_reset_read(eth); 3502 if (!(val & rst_mask)) 3503 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3504 val, rst_mask); 3505 3506 rst_mask |= RSTCTRL_FE; 3507 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3508 3509 udelay(1); 3510 val = mtk_hw_reset_read(eth); 3511 if (val & rst_mask) 3512 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3513 val, rst_mask); 3514 } 3515 3516 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3517 { 3518 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3519 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3520 bool oq_hang, cdm1_busy, adma_busy; 3521 bool wtx_busy, cdm_full, oq_free; 3522 u32 wdidx, val, gdm1_fc, gdm2_fc; 3523 bool qfsm_hang, qfwd_hang; 3524 bool ret = false; 3525 3526 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3527 return false; 3528 3529 /* WDMA sanity checks */ 3530 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3531 3532 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3533 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3534 3535 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3536 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3537 3538 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3539 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3540 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3541 3542 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3543 if (++eth->reset.wdma_hang_count > 2) { 3544 eth->reset.wdma_hang_count = 0; 3545 ret = true; 3546 } 3547 goto out; 3548 } 3549 3550 /* QDMA sanity checks */ 3551 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3552 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3553 3554 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3555 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3556 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3557 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3558 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3559 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3560 3561 if (qfsm_hang && qfwd_hang && 3562 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3563 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3564 if (++eth->reset.qdma_hang_count > 2) { 3565 eth->reset.qdma_hang_count = 0; 3566 ret = true; 3567 } 3568 goto out; 3569 } 3570 3571 /* ADMA sanity checks */ 3572 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3573 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3574 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3575 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3576 3577 if (oq_hang && cdm1_busy && adma_busy) { 3578 if (++eth->reset.adma_hang_count > 2) { 3579 eth->reset.adma_hang_count = 0; 3580 ret = true; 3581 } 3582 goto out; 3583 } 3584 3585 eth->reset.wdma_hang_count = 0; 3586 eth->reset.qdma_hang_count = 0; 3587 eth->reset.adma_hang_count = 0; 3588 out: 3589 eth->reset.wdidx = wdidx; 3590 3591 return ret; 3592 } 3593 3594 static void mtk_hw_reset_monitor_work(struct work_struct *work) 3595 { 3596 struct delayed_work *del_work = to_delayed_work(work); 3597 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3598 reset.monitor_work); 3599 3600 if (test_bit(MTK_RESETTING, ð->state)) 3601 goto out; 3602 3603 /* DMA stuck checks */ 3604 if (mtk_hw_check_dma_hang(eth)) 3605 schedule_work(ð->pending_work); 3606 3607 out: 3608 schedule_delayed_work(ð->reset.monitor_work, 3609 MTK_DMA_MONITOR_TIMEOUT); 3610 } 3611 3612 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3613 { 3614 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3615 ETHSYS_DMA_AG_MAP_PPE; 3616 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3617 int i, val, ret; 3618 3619 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3620 return 0; 3621 3622 if (!reset) { 3623 pm_runtime_enable(eth->dev); 3624 pm_runtime_get_sync(eth->dev); 3625 3626 ret = mtk_clk_enable(eth); 3627 if (ret) 3628 goto err_disable_pm; 3629 } 3630 3631 if (eth->ethsys) 3632 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3633 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3634 3635 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3636 ret = device_reset(eth->dev); 3637 if (ret) { 3638 dev_err(eth->dev, "MAC reset failed!\n"); 3639 goto err_disable_pm; 3640 } 3641 3642 /* set interrupt delays based on current Net DIM sample */ 3643 mtk_dim_rx(ð->rx_dim.work); 3644 mtk_dim_tx(ð->tx_dim.work); 3645 3646 /* disable delay and normal interrupt */ 3647 mtk_tx_irq_disable(eth, ~0); 3648 mtk_rx_irq_disable(eth, ~0); 3649 3650 return 0; 3651 } 3652 3653 msleep(100); 3654 3655 if (reset) 3656 mtk_hw_warm_reset(eth); 3657 else 3658 mtk_hw_reset(eth); 3659 3660 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3661 /* Set FE to PDMAv2 if necessary */ 3662 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3663 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3664 } 3665 3666 if (eth->pctl) { 3667 /* Set GE2 driving and slew rate */ 3668 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3669 3670 /* set GE2 TDSEL */ 3671 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3672 3673 /* set GE2 TUNE */ 3674 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3675 } 3676 3677 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3678 * up with the more appropriate value when mtk_mac_config call is being 3679 * invoked. 3680 */ 3681 for (i = 0; i < MTK_MAC_COUNT; i++) { 3682 struct net_device *dev = eth->netdev[i]; 3683 3684 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3685 if (dev) { 3686 struct mtk_mac *mac = netdev_priv(dev); 3687 3688 mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN); 3689 } 3690 } 3691 3692 /* Indicates CDM to parse the MTK special tag from CPU 3693 * which also is working out for untag packets. 3694 */ 3695 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3696 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3697 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3698 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3699 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 3700 3701 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3702 } 3703 3704 /* set interrupt delays based on current Net DIM sample */ 3705 mtk_dim_rx(ð->rx_dim.work); 3706 mtk_dim_tx(ð->tx_dim.work); 3707 3708 /* disable delay and normal interrupt */ 3709 mtk_tx_irq_disable(eth, ~0); 3710 mtk_rx_irq_disable(eth, ~0); 3711 3712 /* FE int grouping */ 3713 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3714 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3715 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3716 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3717 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3718 3719 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3720 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 3721 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3722 3723 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 3724 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 3725 3726 /* PSE Free Queue Flow Control */ 3727 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3728 3729 /* PSE config input queue threshold */ 3730 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3731 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3732 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3733 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3734 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3735 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3736 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3737 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3738 3739 /* PSE config output queue threshold */ 3740 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3741 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3742 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3743 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3744 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3745 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3746 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3747 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3748 3749 /* GDM and CDM Threshold */ 3750 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 3751 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 3752 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 3753 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 3754 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 3755 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 3756 } 3757 3758 return 0; 3759 3760 err_disable_pm: 3761 if (!reset) { 3762 pm_runtime_put_sync(eth->dev); 3763 pm_runtime_disable(eth->dev); 3764 } 3765 3766 return ret; 3767 } 3768 3769 static int mtk_hw_deinit(struct mtk_eth *eth) 3770 { 3771 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 3772 return 0; 3773 3774 mtk_clk_disable(eth); 3775 3776 pm_runtime_put_sync(eth->dev); 3777 pm_runtime_disable(eth->dev); 3778 3779 return 0; 3780 } 3781 3782 static void mtk_uninit(struct net_device *dev) 3783 { 3784 struct mtk_mac *mac = netdev_priv(dev); 3785 struct mtk_eth *eth = mac->hw; 3786 3787 phylink_disconnect_phy(mac->phylink); 3788 mtk_tx_irq_disable(eth, ~0); 3789 mtk_rx_irq_disable(eth, ~0); 3790 } 3791 3792 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 3793 { 3794 int length = new_mtu + MTK_RX_ETH_HLEN; 3795 struct mtk_mac *mac = netdev_priv(dev); 3796 struct mtk_eth *eth = mac->hw; 3797 3798 if (rcu_access_pointer(eth->prog) && 3799 length > MTK_PP_MAX_BUF_SIZE) { 3800 netdev_err(dev, "Invalid MTU for XDP mode\n"); 3801 return -EINVAL; 3802 } 3803 3804 mtk_set_mcr_max_rx(mac, length); 3805 dev->mtu = new_mtu; 3806 3807 return 0; 3808 } 3809 3810 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3811 { 3812 struct mtk_mac *mac = netdev_priv(dev); 3813 3814 switch (cmd) { 3815 case SIOCGMIIPHY: 3816 case SIOCGMIIREG: 3817 case SIOCSMIIREG: 3818 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 3819 default: 3820 break; 3821 } 3822 3823 return -EOPNOTSUPP; 3824 } 3825 3826 static void mtk_prepare_for_reset(struct mtk_eth *eth) 3827 { 3828 u32 val; 3829 int i; 3830 3831 /* disabe FE P3 and P4 */ 3832 val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3; 3833 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3834 val |= MTK_FE_LINK_DOWN_P4; 3835 mtk_w32(eth, val, MTK_FE_GLO_CFG); 3836 3837 /* adjust PPE configurations to prepare for reset */ 3838 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3839 mtk_ppe_prepare_reset(eth->ppe[i]); 3840 3841 /* disable NETSYS interrupts */ 3842 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 3843 3844 /* force link down GMAC */ 3845 for (i = 0; i < 2; i++) { 3846 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 3847 mtk_w32(eth, val, MTK_MAC_MCR(i)); 3848 } 3849 } 3850 3851 static void mtk_pending_work(struct work_struct *work) 3852 { 3853 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 3854 unsigned long restart = 0; 3855 u32 val; 3856 int i; 3857 3858 rtnl_lock(); 3859 set_bit(MTK_RESETTING, ð->state); 3860 3861 mtk_prepare_for_reset(eth); 3862 mtk_wed_fe_reset(); 3863 /* Run again reset preliminary configuration in order to avoid any 3864 * possible race during FE reset since it can run releasing RTNL lock. 3865 */ 3866 mtk_prepare_for_reset(eth); 3867 3868 /* stop all devices to make sure that dma is properly shut down */ 3869 for (i = 0; i < MTK_MAC_COUNT; i++) { 3870 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 3871 continue; 3872 3873 mtk_stop(eth->netdev[i]); 3874 __set_bit(i, &restart); 3875 } 3876 3877 usleep_range(15000, 16000); 3878 3879 if (eth->dev->pins) 3880 pinctrl_select_state(eth->dev->pins->p, 3881 eth->dev->pins->default_state); 3882 mtk_hw_init(eth, true); 3883 3884 /* restart DMA and enable IRQs */ 3885 for (i = 0; i < MTK_MAC_COUNT; i++) { 3886 if (!test_bit(i, &restart)) 3887 continue; 3888 3889 if (mtk_open(eth->netdev[i])) { 3890 netif_alert(eth, ifup, eth->netdev[i], 3891 "Driver up/down cycle failed\n"); 3892 dev_close(eth->netdev[i]); 3893 } 3894 } 3895 3896 /* enabe FE P3 and P4 */ 3897 val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3; 3898 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3899 val &= ~MTK_FE_LINK_DOWN_P4; 3900 mtk_w32(eth, val, MTK_FE_GLO_CFG); 3901 3902 clear_bit(MTK_RESETTING, ð->state); 3903 3904 mtk_wed_fe_reset_complete(); 3905 3906 rtnl_unlock(); 3907 } 3908 3909 static int mtk_free_dev(struct mtk_eth *eth) 3910 { 3911 int i; 3912 3913 for (i = 0; i < MTK_MAC_COUNT; i++) { 3914 if (!eth->netdev[i]) 3915 continue; 3916 free_netdev(eth->netdev[i]); 3917 } 3918 3919 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3920 if (!eth->dsa_meta[i]) 3921 break; 3922 metadata_dst_free(eth->dsa_meta[i]); 3923 } 3924 3925 return 0; 3926 } 3927 3928 static int mtk_unreg_dev(struct mtk_eth *eth) 3929 { 3930 int i; 3931 3932 for (i = 0; i < MTK_MAC_COUNT; i++) { 3933 struct mtk_mac *mac; 3934 if (!eth->netdev[i]) 3935 continue; 3936 mac = netdev_priv(eth->netdev[i]); 3937 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3938 unregister_netdevice_notifier(&mac->device_notifier); 3939 unregister_netdev(eth->netdev[i]); 3940 } 3941 3942 return 0; 3943 } 3944 3945 static void mtk_sgmii_destroy(struct mtk_eth *eth) 3946 { 3947 int i; 3948 3949 for (i = 0; i < MTK_MAX_DEVS; i++) 3950 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); 3951 } 3952 3953 static int mtk_cleanup(struct mtk_eth *eth) 3954 { 3955 mtk_sgmii_destroy(eth); 3956 mtk_unreg_dev(eth); 3957 mtk_free_dev(eth); 3958 cancel_work_sync(ð->pending_work); 3959 cancel_delayed_work_sync(ð->reset.monitor_work); 3960 3961 return 0; 3962 } 3963 3964 static int mtk_get_link_ksettings(struct net_device *ndev, 3965 struct ethtool_link_ksettings *cmd) 3966 { 3967 struct mtk_mac *mac = netdev_priv(ndev); 3968 3969 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3970 return -EBUSY; 3971 3972 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 3973 } 3974 3975 static int mtk_set_link_ksettings(struct net_device *ndev, 3976 const struct ethtool_link_ksettings *cmd) 3977 { 3978 struct mtk_mac *mac = netdev_priv(ndev); 3979 3980 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3981 return -EBUSY; 3982 3983 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 3984 } 3985 3986 static void mtk_get_drvinfo(struct net_device *dev, 3987 struct ethtool_drvinfo *info) 3988 { 3989 struct mtk_mac *mac = netdev_priv(dev); 3990 3991 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 3992 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 3993 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 3994 } 3995 3996 static u32 mtk_get_msglevel(struct net_device *dev) 3997 { 3998 struct mtk_mac *mac = netdev_priv(dev); 3999 4000 return mac->hw->msg_enable; 4001 } 4002 4003 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4004 { 4005 struct mtk_mac *mac = netdev_priv(dev); 4006 4007 mac->hw->msg_enable = value; 4008 } 4009 4010 static int mtk_nway_reset(struct net_device *dev) 4011 { 4012 struct mtk_mac *mac = netdev_priv(dev); 4013 4014 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4015 return -EBUSY; 4016 4017 if (!mac->phylink) 4018 return -ENOTSUPP; 4019 4020 return phylink_ethtool_nway_reset(mac->phylink); 4021 } 4022 4023 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4024 { 4025 int i; 4026 4027 switch (stringset) { 4028 case ETH_SS_STATS: { 4029 struct mtk_mac *mac = netdev_priv(dev); 4030 4031 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 4032 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 4033 data += ETH_GSTRING_LEN; 4034 } 4035 if (mtk_page_pool_enabled(mac->hw)) 4036 page_pool_ethtool_stats_get_strings(data); 4037 break; 4038 } 4039 default: 4040 break; 4041 } 4042 } 4043 4044 static int mtk_get_sset_count(struct net_device *dev, int sset) 4045 { 4046 switch (sset) { 4047 case ETH_SS_STATS: { 4048 int count = ARRAY_SIZE(mtk_ethtool_stats); 4049 struct mtk_mac *mac = netdev_priv(dev); 4050 4051 if (mtk_page_pool_enabled(mac->hw)) 4052 count += page_pool_ethtool_stats_get_count(); 4053 return count; 4054 } 4055 default: 4056 return -EOPNOTSUPP; 4057 } 4058 } 4059 4060 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4061 { 4062 struct page_pool_stats stats = {}; 4063 int i; 4064 4065 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4066 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4067 4068 if (!ring->page_pool) 4069 continue; 4070 4071 page_pool_get_stats(ring->page_pool, &stats); 4072 } 4073 page_pool_ethtool_stats_get(data, &stats); 4074 } 4075 4076 static void mtk_get_ethtool_stats(struct net_device *dev, 4077 struct ethtool_stats *stats, u64 *data) 4078 { 4079 struct mtk_mac *mac = netdev_priv(dev); 4080 struct mtk_hw_stats *hwstats = mac->hw_stats; 4081 u64 *data_src, *data_dst; 4082 unsigned int start; 4083 int i; 4084 4085 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4086 return; 4087 4088 if (netif_running(dev) && netif_device_present(dev)) { 4089 if (spin_trylock_bh(&hwstats->stats_lock)) { 4090 mtk_stats_update_mac(mac); 4091 spin_unlock_bh(&hwstats->stats_lock); 4092 } 4093 } 4094 4095 data_src = (u64 *)hwstats; 4096 4097 do { 4098 data_dst = data; 4099 start = u64_stats_fetch_begin(&hwstats->syncp); 4100 4101 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4102 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4103 if (mtk_page_pool_enabled(mac->hw)) 4104 mtk_ethtool_pp_stats(mac->hw, data_dst); 4105 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4106 } 4107 4108 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4109 u32 *rule_locs) 4110 { 4111 int ret = -EOPNOTSUPP; 4112 4113 switch (cmd->cmd) { 4114 case ETHTOOL_GRXRINGS: 4115 if (dev->hw_features & NETIF_F_LRO) { 4116 cmd->data = MTK_MAX_RX_RING_NUM; 4117 ret = 0; 4118 } 4119 break; 4120 case ETHTOOL_GRXCLSRLCNT: 4121 if (dev->hw_features & NETIF_F_LRO) { 4122 struct mtk_mac *mac = netdev_priv(dev); 4123 4124 cmd->rule_cnt = mac->hwlro_ip_cnt; 4125 ret = 0; 4126 } 4127 break; 4128 case ETHTOOL_GRXCLSRULE: 4129 if (dev->hw_features & NETIF_F_LRO) 4130 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4131 break; 4132 case ETHTOOL_GRXCLSRLALL: 4133 if (dev->hw_features & NETIF_F_LRO) 4134 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4135 rule_locs); 4136 break; 4137 default: 4138 break; 4139 } 4140 4141 return ret; 4142 } 4143 4144 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4145 { 4146 int ret = -EOPNOTSUPP; 4147 4148 switch (cmd->cmd) { 4149 case ETHTOOL_SRXCLSRLINS: 4150 if (dev->hw_features & NETIF_F_LRO) 4151 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4152 break; 4153 case ETHTOOL_SRXCLSRLDEL: 4154 if (dev->hw_features & NETIF_F_LRO) 4155 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4156 break; 4157 default: 4158 break; 4159 } 4160 4161 return ret; 4162 } 4163 4164 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4165 struct net_device *sb_dev) 4166 { 4167 struct mtk_mac *mac = netdev_priv(dev); 4168 unsigned int queue = 0; 4169 4170 if (netdev_uses_dsa(dev)) 4171 queue = skb_get_queue_mapping(skb) + 3; 4172 else 4173 queue = mac->id; 4174 4175 if (queue >= dev->num_tx_queues) 4176 queue = 0; 4177 4178 return queue; 4179 } 4180 4181 static const struct ethtool_ops mtk_ethtool_ops = { 4182 .get_link_ksettings = mtk_get_link_ksettings, 4183 .set_link_ksettings = mtk_set_link_ksettings, 4184 .get_drvinfo = mtk_get_drvinfo, 4185 .get_msglevel = mtk_get_msglevel, 4186 .set_msglevel = mtk_set_msglevel, 4187 .nway_reset = mtk_nway_reset, 4188 .get_link = ethtool_op_get_link, 4189 .get_strings = mtk_get_strings, 4190 .get_sset_count = mtk_get_sset_count, 4191 .get_ethtool_stats = mtk_get_ethtool_stats, 4192 .get_rxnfc = mtk_get_rxnfc, 4193 .set_rxnfc = mtk_set_rxnfc, 4194 }; 4195 4196 static const struct net_device_ops mtk_netdev_ops = { 4197 .ndo_uninit = mtk_uninit, 4198 .ndo_open = mtk_open, 4199 .ndo_stop = mtk_stop, 4200 .ndo_start_xmit = mtk_start_xmit, 4201 .ndo_set_mac_address = mtk_set_mac_address, 4202 .ndo_validate_addr = eth_validate_addr, 4203 .ndo_eth_ioctl = mtk_do_ioctl, 4204 .ndo_change_mtu = mtk_change_mtu, 4205 .ndo_tx_timeout = mtk_tx_timeout, 4206 .ndo_get_stats64 = mtk_get_stats64, 4207 .ndo_fix_features = mtk_fix_features, 4208 .ndo_set_features = mtk_set_features, 4209 #ifdef CONFIG_NET_POLL_CONTROLLER 4210 .ndo_poll_controller = mtk_poll_controller, 4211 #endif 4212 .ndo_setup_tc = mtk_eth_setup_tc, 4213 .ndo_bpf = mtk_xdp, 4214 .ndo_xdp_xmit = mtk_xdp_xmit, 4215 .ndo_select_queue = mtk_select_queue, 4216 }; 4217 4218 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4219 { 4220 const __be32 *_id = of_get_property(np, "reg", NULL); 4221 phy_interface_t phy_mode; 4222 struct phylink *phylink; 4223 struct mtk_mac *mac; 4224 int id, err; 4225 int txqs = 1; 4226 u32 val; 4227 4228 if (!_id) { 4229 dev_err(eth->dev, "missing mac id\n"); 4230 return -EINVAL; 4231 } 4232 4233 id = be32_to_cpup(_id); 4234 if (id >= MTK_MAC_COUNT) { 4235 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4236 return -EINVAL; 4237 } 4238 4239 if (eth->netdev[id]) { 4240 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4241 return -EINVAL; 4242 } 4243 4244 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4245 txqs = MTK_QDMA_NUM_QUEUES; 4246 4247 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4248 if (!eth->netdev[id]) { 4249 dev_err(eth->dev, "alloc_etherdev failed\n"); 4250 return -ENOMEM; 4251 } 4252 mac = netdev_priv(eth->netdev[id]); 4253 eth->mac[id] = mac; 4254 mac->id = id; 4255 mac->hw = eth; 4256 mac->of_node = np; 4257 4258 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); 4259 if (err == -EPROBE_DEFER) 4260 return err; 4261 4262 if (err) { 4263 /* If the mac address is invalid, use random mac address */ 4264 eth_hw_addr_random(eth->netdev[id]); 4265 dev_err(eth->dev, "generated random MAC address %pM\n", 4266 eth->netdev[id]->dev_addr); 4267 } 4268 4269 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4270 mac->hwlro_ip_cnt = 0; 4271 4272 mac->hw_stats = devm_kzalloc(eth->dev, 4273 sizeof(*mac->hw_stats), 4274 GFP_KERNEL); 4275 if (!mac->hw_stats) { 4276 dev_err(eth->dev, "failed to allocate counter memory\n"); 4277 err = -ENOMEM; 4278 goto free_netdev; 4279 } 4280 spin_lock_init(&mac->hw_stats->stats_lock); 4281 u64_stats_init(&mac->hw_stats->syncp); 4282 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 4283 4284 /* phylink create */ 4285 err = of_get_phy_mode(np, &phy_mode); 4286 if (err) { 4287 dev_err(eth->dev, "incorrect phy-mode\n"); 4288 goto free_netdev; 4289 } 4290 4291 /* mac config is not set */ 4292 mac->interface = PHY_INTERFACE_MODE_NA; 4293 mac->speed = SPEED_UNKNOWN; 4294 4295 mac->phylink_config.dev = ð->netdev[id]->dev; 4296 mac->phylink_config.type = PHYLINK_NETDEV; 4297 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4298 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4299 4300 /* MT7623 gmac0 is now missing its speed-specific PLL configuration 4301 * in its .mac_config method (since state->speed is not valid there. 4302 * Disable support for MII, GMII and RGMII. 4303 */ 4304 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { 4305 __set_bit(PHY_INTERFACE_MODE_MII, 4306 mac->phylink_config.supported_interfaces); 4307 __set_bit(PHY_INTERFACE_MODE_GMII, 4308 mac->phylink_config.supported_interfaces); 4309 4310 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4311 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4312 } 4313 4314 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4315 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4316 mac->phylink_config.supported_interfaces); 4317 4318 /* TRGMII is not permitted on MT7621 if using DDR2 */ 4319 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 4320 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 4321 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 4322 if (val & SYSCFG_DRAM_TYPE_DDR2) 4323 __clear_bit(PHY_INTERFACE_MODE_TRGMII, 4324 mac->phylink_config.supported_interfaces); 4325 } 4326 4327 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4328 __set_bit(PHY_INTERFACE_MODE_SGMII, 4329 mac->phylink_config.supported_interfaces); 4330 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4331 mac->phylink_config.supported_interfaces); 4332 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4333 mac->phylink_config.supported_interfaces); 4334 } 4335 4336 phylink = phylink_create(&mac->phylink_config, 4337 of_fwnode_handle(mac->of_node), 4338 phy_mode, &mtk_phylink_ops); 4339 if (IS_ERR(phylink)) { 4340 err = PTR_ERR(phylink); 4341 goto free_netdev; 4342 } 4343 4344 mac->phylink = phylink; 4345 4346 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4347 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4348 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4349 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4350 4351 eth->netdev[id]->hw_features = eth->soc->hw_features; 4352 if (eth->hwlro) 4353 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4354 4355 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4356 ~NETIF_F_HW_VLAN_CTAG_TX; 4357 eth->netdev[id]->features |= eth->soc->hw_features; 4358 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4359 4360 eth->netdev[id]->irq = eth->irq[0]; 4361 eth->netdev[id]->dev.of_node = np; 4362 4363 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4364 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4365 else 4366 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4367 4368 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4369 mac->device_notifier.notifier_call = mtk_device_event; 4370 register_netdevice_notifier(&mac->device_notifier); 4371 } 4372 4373 if (mtk_page_pool_enabled(eth)) 4374 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4375 NETDEV_XDP_ACT_REDIRECT | 4376 NETDEV_XDP_ACT_NDO_XMIT | 4377 NETDEV_XDP_ACT_NDO_XMIT_SG; 4378 4379 return 0; 4380 4381 free_netdev: 4382 free_netdev(eth->netdev[id]); 4383 return err; 4384 } 4385 4386 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4387 { 4388 struct net_device *dev, *tmp; 4389 LIST_HEAD(dev_list); 4390 int i; 4391 4392 rtnl_lock(); 4393 4394 for (i = 0; i < MTK_MAC_COUNT; i++) { 4395 dev = eth->netdev[i]; 4396 4397 if (!dev || !(dev->flags & IFF_UP)) 4398 continue; 4399 4400 list_add_tail(&dev->close_list, &dev_list); 4401 } 4402 4403 dev_close_many(&dev_list, false); 4404 4405 eth->dma_dev = dma_dev; 4406 4407 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4408 list_del_init(&dev->close_list); 4409 dev_open(dev, NULL); 4410 } 4411 4412 rtnl_unlock(); 4413 } 4414 4415 static int mtk_sgmii_init(struct mtk_eth *eth) 4416 { 4417 struct device_node *np; 4418 struct regmap *regmap; 4419 u32 flags; 4420 int i; 4421 4422 for (i = 0; i < MTK_MAX_DEVS; i++) { 4423 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); 4424 if (!np) 4425 break; 4426 4427 regmap = syscon_node_to_regmap(np); 4428 flags = 0; 4429 if (of_property_read_bool(np, "mediatek,pnswap")) 4430 flags |= MTK_SGMII_FLAG_PN_SWAP; 4431 4432 of_node_put(np); 4433 4434 if (IS_ERR(regmap)) 4435 return PTR_ERR(regmap); 4436 4437 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, 4438 eth->soc->ana_rgc3, 4439 flags); 4440 } 4441 4442 return 0; 4443 } 4444 4445 static int mtk_probe(struct platform_device *pdev) 4446 { 4447 struct resource *res = NULL; 4448 struct device_node *mac_np; 4449 struct mtk_eth *eth; 4450 int err, i; 4451 4452 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4453 if (!eth) 4454 return -ENOMEM; 4455 4456 eth->soc = of_device_get_match_data(&pdev->dev); 4457 4458 eth->dev = &pdev->dev; 4459 eth->dma_dev = &pdev->dev; 4460 eth->base = devm_platform_ioremap_resource(pdev, 0); 4461 if (IS_ERR(eth->base)) 4462 return PTR_ERR(eth->base); 4463 4464 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4465 eth->ip_align = NET_IP_ALIGN; 4466 4467 spin_lock_init(ð->page_lock); 4468 spin_lock_init(ð->tx_irq_lock); 4469 spin_lock_init(ð->rx_irq_lock); 4470 spin_lock_init(ð->dim_lock); 4471 4472 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4473 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4474 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4475 4476 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4477 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4478 4479 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4480 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4481 "mediatek,ethsys"); 4482 if (IS_ERR(eth->ethsys)) { 4483 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4484 return PTR_ERR(eth->ethsys); 4485 } 4486 } 4487 4488 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4489 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4490 "mediatek,infracfg"); 4491 if (IS_ERR(eth->infra)) { 4492 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4493 return PTR_ERR(eth->infra); 4494 } 4495 } 4496 4497 if (of_dma_is_coherent(pdev->dev.of_node)) { 4498 struct regmap *cci; 4499 4500 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4501 "cci-control-port"); 4502 /* enable CPU/bus coherency */ 4503 if (!IS_ERR(cci)) 4504 regmap_write(cci, 0, 3); 4505 } 4506 4507 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4508 err = mtk_sgmii_init(eth); 4509 4510 if (err) 4511 return err; 4512 } 4513 4514 if (eth->soc->required_pctl) { 4515 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4516 "mediatek,pctl"); 4517 if (IS_ERR(eth->pctl)) { 4518 dev_err(&pdev->dev, "no pctl regmap found\n"); 4519 err = PTR_ERR(eth->pctl); 4520 goto err_destroy_sgmii; 4521 } 4522 } 4523 4524 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 4525 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4526 if (!res) { 4527 err = -EINVAL; 4528 goto err_destroy_sgmii; 4529 } 4530 } 4531 4532 if (eth->soc->offload_version) { 4533 for (i = 0;; i++) { 4534 struct device_node *np; 4535 phys_addr_t wdma_phy; 4536 u32 wdma_base; 4537 4538 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4539 break; 4540 4541 np = of_parse_phandle(pdev->dev.of_node, 4542 "mediatek,wed", i); 4543 if (!np) 4544 break; 4545 4546 wdma_base = eth->soc->reg_map->wdma_base[i]; 4547 wdma_phy = res ? res->start + wdma_base : 0; 4548 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4549 wdma_phy, i); 4550 } 4551 } 4552 4553 for (i = 0; i < 3; i++) { 4554 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4555 eth->irq[i] = eth->irq[0]; 4556 else 4557 eth->irq[i] = platform_get_irq(pdev, i); 4558 if (eth->irq[i] < 0) { 4559 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4560 err = -ENXIO; 4561 goto err_wed_exit; 4562 } 4563 } 4564 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4565 eth->clks[i] = devm_clk_get(eth->dev, 4566 mtk_clks_source_name[i]); 4567 if (IS_ERR(eth->clks[i])) { 4568 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4569 err = -EPROBE_DEFER; 4570 goto err_wed_exit; 4571 } 4572 if (eth->soc->required_clks & BIT(i)) { 4573 dev_err(&pdev->dev, "clock %s not found\n", 4574 mtk_clks_source_name[i]); 4575 err = -EINVAL; 4576 goto err_wed_exit; 4577 } 4578 eth->clks[i] = NULL; 4579 } 4580 } 4581 4582 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4583 INIT_WORK(ð->pending_work, mtk_pending_work); 4584 4585 err = mtk_hw_init(eth, false); 4586 if (err) 4587 goto err_wed_exit; 4588 4589 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4590 4591 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4592 if (!of_device_is_compatible(mac_np, 4593 "mediatek,eth-mac")) 4594 continue; 4595 4596 if (!of_device_is_available(mac_np)) 4597 continue; 4598 4599 err = mtk_add_mac(eth, mac_np); 4600 if (err) { 4601 of_node_put(mac_np); 4602 goto err_deinit_hw; 4603 } 4604 } 4605 4606 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4607 err = devm_request_irq(eth->dev, eth->irq[0], 4608 mtk_handle_irq, 0, 4609 dev_name(eth->dev), eth); 4610 } else { 4611 err = devm_request_irq(eth->dev, eth->irq[1], 4612 mtk_handle_irq_tx, 0, 4613 dev_name(eth->dev), eth); 4614 if (err) 4615 goto err_free_dev; 4616 4617 err = devm_request_irq(eth->dev, eth->irq[2], 4618 mtk_handle_irq_rx, 0, 4619 dev_name(eth->dev), eth); 4620 } 4621 if (err) 4622 goto err_free_dev; 4623 4624 /* No MT7628/88 support yet */ 4625 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4626 err = mtk_mdio_init(eth); 4627 if (err) 4628 goto err_free_dev; 4629 } 4630 4631 if (eth->soc->offload_version) { 4632 u32 num_ppe; 4633 4634 num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; 4635 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4636 for (i = 0; i < num_ppe; i++) { 4637 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; 4638 4639 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); 4640 4641 if (!eth->ppe[i]) { 4642 err = -ENOMEM; 4643 goto err_deinit_ppe; 4644 } 4645 } 4646 4647 err = mtk_eth_offload_init(eth); 4648 if (err) 4649 goto err_deinit_ppe; 4650 } 4651 4652 for (i = 0; i < MTK_MAX_DEVS; i++) { 4653 if (!eth->netdev[i]) 4654 continue; 4655 4656 err = register_netdev(eth->netdev[i]); 4657 if (err) { 4658 dev_err(eth->dev, "error bringing up device\n"); 4659 goto err_deinit_ppe; 4660 } else 4661 netif_info(eth, probe, eth->netdev[i], 4662 "mediatek frame engine at 0x%08lx, irq %d\n", 4663 eth->netdev[i]->base_addr, eth->irq[0]); 4664 } 4665 4666 /* we run 2 devices on the same DMA ring so we need a dummy device 4667 * for NAPI to work 4668 */ 4669 init_dummy_netdev(ð->dummy_dev); 4670 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); 4671 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); 4672 4673 platform_set_drvdata(pdev, eth); 4674 schedule_delayed_work(ð->reset.monitor_work, 4675 MTK_DMA_MONITOR_TIMEOUT); 4676 4677 return 0; 4678 4679 err_deinit_ppe: 4680 mtk_ppe_deinit(eth); 4681 mtk_mdio_cleanup(eth); 4682 err_free_dev: 4683 mtk_free_dev(eth); 4684 err_deinit_hw: 4685 mtk_hw_deinit(eth); 4686 err_wed_exit: 4687 mtk_wed_exit(); 4688 err_destroy_sgmii: 4689 mtk_sgmii_destroy(eth); 4690 4691 return err; 4692 } 4693 4694 static int mtk_remove(struct platform_device *pdev) 4695 { 4696 struct mtk_eth *eth = platform_get_drvdata(pdev); 4697 struct mtk_mac *mac; 4698 int i; 4699 4700 /* stop all devices to make sure that dma is properly shut down */ 4701 for (i = 0; i < MTK_MAC_COUNT; i++) { 4702 if (!eth->netdev[i]) 4703 continue; 4704 mtk_stop(eth->netdev[i]); 4705 mac = netdev_priv(eth->netdev[i]); 4706 phylink_disconnect_phy(mac->phylink); 4707 } 4708 4709 mtk_wed_exit(); 4710 mtk_hw_deinit(eth); 4711 4712 netif_napi_del(ð->tx_napi); 4713 netif_napi_del(ð->rx_napi); 4714 mtk_cleanup(eth); 4715 mtk_mdio_cleanup(eth); 4716 4717 return 0; 4718 } 4719 4720 static const struct mtk_soc_data mt2701_data = { 4721 .reg_map = &mtk_reg_map, 4722 .caps = MT7623_CAPS | MTK_HWLRO, 4723 .hw_features = MTK_HW_FEATURES, 4724 .required_clks = MT7623_CLKS_BITMAP, 4725 .required_pctl = true, 4726 .txrx = { 4727 .txd_size = sizeof(struct mtk_tx_dma), 4728 .rxd_size = sizeof(struct mtk_rx_dma), 4729 .rx_irq_done_mask = MTK_RX_DONE_INT, 4730 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4731 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4732 .dma_len_offset = 16, 4733 }, 4734 }; 4735 4736 static const struct mtk_soc_data mt7621_data = { 4737 .reg_map = &mtk_reg_map, 4738 .caps = MT7621_CAPS, 4739 .hw_features = MTK_HW_FEATURES, 4740 .required_clks = MT7621_CLKS_BITMAP, 4741 .required_pctl = false, 4742 .offload_version = 1, 4743 .hash_offset = 2, 4744 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 4745 .txrx = { 4746 .txd_size = sizeof(struct mtk_tx_dma), 4747 .rxd_size = sizeof(struct mtk_rx_dma), 4748 .rx_irq_done_mask = MTK_RX_DONE_INT, 4749 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4750 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4751 .dma_len_offset = 16, 4752 }, 4753 }; 4754 4755 static const struct mtk_soc_data mt7622_data = { 4756 .reg_map = &mtk_reg_map, 4757 .ana_rgc3 = 0x2028, 4758 .caps = MT7622_CAPS | MTK_HWLRO, 4759 .hw_features = MTK_HW_FEATURES, 4760 .required_clks = MT7622_CLKS_BITMAP, 4761 .required_pctl = false, 4762 .offload_version = 2, 4763 .hash_offset = 2, 4764 .has_accounting = true, 4765 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 4766 .txrx = { 4767 .txd_size = sizeof(struct mtk_tx_dma), 4768 .rxd_size = sizeof(struct mtk_rx_dma), 4769 .rx_irq_done_mask = MTK_RX_DONE_INT, 4770 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4771 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4772 .dma_len_offset = 16, 4773 }, 4774 }; 4775 4776 static const struct mtk_soc_data mt7623_data = { 4777 .reg_map = &mtk_reg_map, 4778 .caps = MT7623_CAPS | MTK_HWLRO, 4779 .hw_features = MTK_HW_FEATURES, 4780 .required_clks = MT7623_CLKS_BITMAP, 4781 .required_pctl = true, 4782 .offload_version = 1, 4783 .hash_offset = 2, 4784 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 4785 .disable_pll_modes = true, 4786 .txrx = { 4787 .txd_size = sizeof(struct mtk_tx_dma), 4788 .rxd_size = sizeof(struct mtk_rx_dma), 4789 .rx_irq_done_mask = MTK_RX_DONE_INT, 4790 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4791 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4792 .dma_len_offset = 16, 4793 }, 4794 }; 4795 4796 static const struct mtk_soc_data mt7629_data = { 4797 .reg_map = &mtk_reg_map, 4798 .ana_rgc3 = 0x128, 4799 .caps = MT7629_CAPS | MTK_HWLRO, 4800 .hw_features = MTK_HW_FEATURES, 4801 .required_clks = MT7629_CLKS_BITMAP, 4802 .required_pctl = false, 4803 .has_accounting = true, 4804 .txrx = { 4805 .txd_size = sizeof(struct mtk_tx_dma), 4806 .rxd_size = sizeof(struct mtk_rx_dma), 4807 .rx_irq_done_mask = MTK_RX_DONE_INT, 4808 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4809 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4810 .dma_len_offset = 16, 4811 }, 4812 }; 4813 4814 static const struct mtk_soc_data mt7981_data = { 4815 .reg_map = &mt7986_reg_map, 4816 .ana_rgc3 = 0x128, 4817 .caps = MT7981_CAPS, 4818 .hw_features = MTK_HW_FEATURES, 4819 .required_clks = MT7981_CLKS_BITMAP, 4820 .required_pctl = false, 4821 .offload_version = 2, 4822 .hash_offset = 4, 4823 .has_accounting = true, 4824 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 4825 .txrx = { 4826 .txd_size = sizeof(struct mtk_tx_dma_v2), 4827 .rxd_size = sizeof(struct mtk_rx_dma_v2), 4828 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 4829 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 4830 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 4831 .dma_len_offset = 8, 4832 }, 4833 }; 4834 4835 static const struct mtk_soc_data mt7986_data = { 4836 .reg_map = &mt7986_reg_map, 4837 .ana_rgc3 = 0x128, 4838 .caps = MT7986_CAPS, 4839 .hw_features = MTK_HW_FEATURES, 4840 .required_clks = MT7986_CLKS_BITMAP, 4841 .required_pctl = false, 4842 .offload_version = 2, 4843 .hash_offset = 4, 4844 .has_accounting = true, 4845 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 4846 .txrx = { 4847 .txd_size = sizeof(struct mtk_tx_dma_v2), 4848 .rxd_size = sizeof(struct mtk_rx_dma_v2), 4849 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 4850 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 4851 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 4852 .dma_len_offset = 8, 4853 }, 4854 }; 4855 4856 static const struct mtk_soc_data rt5350_data = { 4857 .reg_map = &mt7628_reg_map, 4858 .caps = MT7628_CAPS, 4859 .hw_features = MTK_HW_FEATURES_MT7628, 4860 .required_clks = MT7628_CLKS_BITMAP, 4861 .required_pctl = false, 4862 .txrx = { 4863 .txd_size = sizeof(struct mtk_tx_dma), 4864 .rxd_size = sizeof(struct mtk_rx_dma), 4865 .rx_irq_done_mask = MTK_RX_DONE_INT, 4866 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 4867 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4868 .dma_len_offset = 16, 4869 }, 4870 }; 4871 4872 const struct of_device_id of_mtk_match[] = { 4873 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 4874 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 4875 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 4876 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 4877 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 4878 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data}, 4879 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, 4880 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 4881 {}, 4882 }; 4883 MODULE_DEVICE_TABLE(of, of_mtk_match); 4884 4885 static struct platform_driver mtk_driver = { 4886 .probe = mtk_probe, 4887 .remove = mtk_remove, 4888 .driver = { 4889 .name = "mtk_soc_eth", 4890 .of_match_table = of_mtk_match, 4891 }, 4892 }; 4893 4894 module_platform_driver(mtk_driver); 4895 4896 MODULE_LICENSE("GPL"); 4897 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 4898 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 4899