1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/clk.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/if_vlan.h> 19 #include <linux/reset.h> 20 #include <linux/tcp.h> 21 #include <linux/interrupt.h> 22 #include <linux/pinctrl/devinfo.h> 23 #include <linux/phylink.h> 24 #include <linux/pcs/pcs-mtk-lynxi.h> 25 #include <linux/jhash.h> 26 #include <linux/bitfield.h> 27 #include <net/dsa.h> 28 #include <net/dst_metadata.h> 29 #include <net/page_pool/helpers.h> 30 31 #include "mtk_eth_soc.h" 32 #include "mtk_wed.h" 33 34 static int mtk_msg_level = -1; 35 module_param_named(msg_level, mtk_msg_level, int, 0); 36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 37 38 #define MTK_ETHTOOL_STAT(x) { #x, \ 39 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 40 41 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 42 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 43 sizeof(u64) } 44 45 static const struct mtk_reg_map mtk_reg_map = { 46 .tx_irq_mask = 0x1a1c, 47 .tx_irq_status = 0x1a18, 48 .pdma = { 49 .rx_ptr = 0x0900, 50 .rx_cnt_cfg = 0x0904, 51 .pcrx_ptr = 0x0908, 52 .glo_cfg = 0x0a04, 53 .rst_idx = 0x0a08, 54 .delay_irq = 0x0a0c, 55 .irq_status = 0x0a20, 56 .irq_mask = 0x0a28, 57 .adma_rx_dbg0 = 0x0a38, 58 .int_grp = 0x0a50, 59 }, 60 .qdma = { 61 .qtx_cfg = 0x1800, 62 .qtx_sch = 0x1804, 63 .rx_ptr = 0x1900, 64 .rx_cnt_cfg = 0x1904, 65 .qcrx_ptr = 0x1908, 66 .glo_cfg = 0x1a04, 67 .rst_idx = 0x1a08, 68 .delay_irq = 0x1a0c, 69 .fc_th = 0x1a10, 70 .tx_sch_rate = 0x1a14, 71 .int_grp = 0x1a20, 72 .hred = 0x1a44, 73 .ctx_ptr = 0x1b00, 74 .dtx_ptr = 0x1b04, 75 .crx_ptr = 0x1b10, 76 .drx_ptr = 0x1b14, 77 .fq_head = 0x1b20, 78 .fq_tail = 0x1b24, 79 .fq_count = 0x1b28, 80 .fq_blen = 0x1b2c, 81 }, 82 .gdm1_cnt = 0x2400, 83 .gdma_to_ppe = { 84 [0] = 0x4444, 85 }, 86 .ppe_base = 0x0c00, 87 .wdma_base = { 88 [0] = 0x2800, 89 [1] = 0x2c00, 90 }, 91 .pse_iq_sta = 0x0110, 92 .pse_oq_sta = 0x0118, 93 }; 94 95 static const struct mtk_reg_map mt7628_reg_map = { 96 .tx_irq_mask = 0x0a28, 97 .tx_irq_status = 0x0a20, 98 .pdma = { 99 .rx_ptr = 0x0900, 100 .rx_cnt_cfg = 0x0904, 101 .pcrx_ptr = 0x0908, 102 .glo_cfg = 0x0a04, 103 .rst_idx = 0x0a08, 104 .delay_irq = 0x0a0c, 105 .irq_status = 0x0a20, 106 .irq_mask = 0x0a28, 107 .int_grp = 0x0a50, 108 }, 109 }; 110 111 static const struct mtk_reg_map mt7986_reg_map = { 112 .tx_irq_mask = 0x461c, 113 .tx_irq_status = 0x4618, 114 .pdma = { 115 .rx_ptr = 0x4100, 116 .rx_cnt_cfg = 0x4104, 117 .pcrx_ptr = 0x4108, 118 .glo_cfg = 0x4204, 119 .rst_idx = 0x4208, 120 .delay_irq = 0x420c, 121 .irq_status = 0x4220, 122 .irq_mask = 0x4228, 123 .adma_rx_dbg0 = 0x4238, 124 .int_grp = 0x4250, 125 }, 126 .qdma = { 127 .qtx_cfg = 0x4400, 128 .qtx_sch = 0x4404, 129 .rx_ptr = 0x4500, 130 .rx_cnt_cfg = 0x4504, 131 .qcrx_ptr = 0x4508, 132 .glo_cfg = 0x4604, 133 .rst_idx = 0x4608, 134 .delay_irq = 0x460c, 135 .fc_th = 0x4610, 136 .int_grp = 0x4620, 137 .hred = 0x4644, 138 .ctx_ptr = 0x4700, 139 .dtx_ptr = 0x4704, 140 .crx_ptr = 0x4710, 141 .drx_ptr = 0x4714, 142 .fq_head = 0x4720, 143 .fq_tail = 0x4724, 144 .fq_count = 0x4728, 145 .fq_blen = 0x472c, 146 .tx_sch_rate = 0x4798, 147 }, 148 .gdm1_cnt = 0x1c00, 149 .gdma_to_ppe = { 150 [0] = 0x3333, 151 [1] = 0x4444, 152 }, 153 .ppe_base = 0x2000, 154 .wdma_base = { 155 [0] = 0x4800, 156 [1] = 0x4c00, 157 }, 158 .pse_iq_sta = 0x0180, 159 .pse_oq_sta = 0x01a0, 160 }; 161 162 static const struct mtk_reg_map mt7988_reg_map = { 163 .tx_irq_mask = 0x461c, 164 .tx_irq_status = 0x4618, 165 .pdma = { 166 .rx_ptr = 0x6900, 167 .rx_cnt_cfg = 0x6904, 168 .pcrx_ptr = 0x6908, 169 .glo_cfg = 0x6a04, 170 .rst_idx = 0x6a08, 171 .delay_irq = 0x6a0c, 172 .irq_status = 0x6a20, 173 .irq_mask = 0x6a28, 174 .adma_rx_dbg0 = 0x6a38, 175 .int_grp = 0x6a50, 176 }, 177 .qdma = { 178 .qtx_cfg = 0x4400, 179 .qtx_sch = 0x4404, 180 .rx_ptr = 0x4500, 181 .rx_cnt_cfg = 0x4504, 182 .qcrx_ptr = 0x4508, 183 .glo_cfg = 0x4604, 184 .rst_idx = 0x4608, 185 .delay_irq = 0x460c, 186 .fc_th = 0x4610, 187 .int_grp = 0x4620, 188 .hred = 0x4644, 189 .ctx_ptr = 0x4700, 190 .dtx_ptr = 0x4704, 191 .crx_ptr = 0x4710, 192 .drx_ptr = 0x4714, 193 .fq_head = 0x4720, 194 .fq_tail = 0x4724, 195 .fq_count = 0x4728, 196 .fq_blen = 0x472c, 197 .tx_sch_rate = 0x4798, 198 }, 199 .gdm1_cnt = 0x1c00, 200 .gdma_to_ppe = { 201 [0] = 0x3333, 202 [1] = 0x4444, 203 [2] = 0xcccc, 204 }, 205 .ppe_base = 0x2000, 206 .wdma_base = { 207 [0] = 0x4800, 208 [1] = 0x4c00, 209 [2] = 0x5000, 210 }, 211 .pse_iq_sta = 0x0180, 212 .pse_oq_sta = 0x01a0, 213 }; 214 215 /* strings used by ethtool */ 216 static const struct mtk_ethtool_stats { 217 char str[ETH_GSTRING_LEN]; 218 u32 offset; 219 } mtk_ethtool_stats[] = { 220 MTK_ETHTOOL_STAT(tx_bytes), 221 MTK_ETHTOOL_STAT(tx_packets), 222 MTK_ETHTOOL_STAT(tx_skip), 223 MTK_ETHTOOL_STAT(tx_collisions), 224 MTK_ETHTOOL_STAT(rx_bytes), 225 MTK_ETHTOOL_STAT(rx_packets), 226 MTK_ETHTOOL_STAT(rx_overflow), 227 MTK_ETHTOOL_STAT(rx_fcs_errors), 228 MTK_ETHTOOL_STAT(rx_short_errors), 229 MTK_ETHTOOL_STAT(rx_long_errors), 230 MTK_ETHTOOL_STAT(rx_checksum_errors), 231 MTK_ETHTOOL_STAT(rx_flow_control_packets), 232 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 233 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 234 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 235 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 236 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 237 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 238 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 239 }; 240 241 static const char * const mtk_clks_source_name[] = { 242 "ethif", 243 "sgmiitop", 244 "esw", 245 "gp0", 246 "gp1", 247 "gp2", 248 "gp3", 249 "xgp1", 250 "xgp2", 251 "xgp3", 252 "crypto", 253 "fe", 254 "trgpll", 255 "sgmii_tx250m", 256 "sgmii_rx250m", 257 "sgmii_cdr_ref", 258 "sgmii_cdr_fb", 259 "sgmii2_tx250m", 260 "sgmii2_rx250m", 261 "sgmii2_cdr_ref", 262 "sgmii2_cdr_fb", 263 "sgmii_ck", 264 "eth2pll", 265 "wocpu0", 266 "wocpu1", 267 "netsys0", 268 "netsys1", 269 "ethwarp_wocpu2", 270 "ethwarp_wocpu1", 271 "ethwarp_wocpu0", 272 "top_usxgmii0_sel", 273 "top_usxgmii1_sel", 274 "top_sgm0_sel", 275 "top_sgm1_sel", 276 "top_xfi_phy0_xtal_sel", 277 "top_xfi_phy1_xtal_sel", 278 "top_eth_gmii_sel", 279 "top_eth_refck_50m_sel", 280 "top_eth_sys_200m_sel", 281 "top_eth_sys_sel", 282 "top_eth_xgmii_sel", 283 "top_eth_mii_sel", 284 "top_netsys_sel", 285 "top_netsys_500m_sel", 286 "top_netsys_pao_2x_sel", 287 "top_netsys_sync_250m_sel", 288 "top_netsys_ppefb_250m_sel", 289 "top_netsys_warp_sel", 290 }; 291 292 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 293 { 294 __raw_writel(val, eth->base + reg); 295 } 296 297 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 298 { 299 return __raw_readl(eth->base + reg); 300 } 301 302 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) 303 { 304 u32 val; 305 306 val = mtk_r32(eth, reg); 307 val &= ~mask; 308 val |= set; 309 mtk_w32(eth, val, reg); 310 return reg; 311 } 312 313 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 314 { 315 unsigned long t_start = jiffies; 316 317 while (1) { 318 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 319 return 0; 320 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 321 break; 322 cond_resched(); 323 } 324 325 dev_err(eth->dev, "mdio: MDIO timeout\n"); 326 return -ETIMEDOUT; 327 } 328 329 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 330 u32 write_data) 331 { 332 int ret; 333 334 ret = mtk_mdio_busy_wait(eth); 335 if (ret < 0) 336 return ret; 337 338 mtk_w32(eth, PHY_IAC_ACCESS | 339 PHY_IAC_START_C22 | 340 PHY_IAC_CMD_WRITE | 341 PHY_IAC_REG(phy_reg) | 342 PHY_IAC_ADDR(phy_addr) | 343 PHY_IAC_DATA(write_data), 344 MTK_PHY_IAC); 345 346 ret = mtk_mdio_busy_wait(eth); 347 if (ret < 0) 348 return ret; 349 350 return 0; 351 } 352 353 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 354 u32 devad, u32 phy_reg, u32 write_data) 355 { 356 int ret; 357 358 ret = mtk_mdio_busy_wait(eth); 359 if (ret < 0) 360 return ret; 361 362 mtk_w32(eth, PHY_IAC_ACCESS | 363 PHY_IAC_START_C45 | 364 PHY_IAC_CMD_C45_ADDR | 365 PHY_IAC_REG(devad) | 366 PHY_IAC_ADDR(phy_addr) | 367 PHY_IAC_DATA(phy_reg), 368 MTK_PHY_IAC); 369 370 ret = mtk_mdio_busy_wait(eth); 371 if (ret < 0) 372 return ret; 373 374 mtk_w32(eth, PHY_IAC_ACCESS | 375 PHY_IAC_START_C45 | 376 PHY_IAC_CMD_WRITE | 377 PHY_IAC_REG(devad) | 378 PHY_IAC_ADDR(phy_addr) | 379 PHY_IAC_DATA(write_data), 380 MTK_PHY_IAC); 381 382 ret = mtk_mdio_busy_wait(eth); 383 if (ret < 0) 384 return ret; 385 386 return 0; 387 } 388 389 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 390 { 391 int ret; 392 393 ret = mtk_mdio_busy_wait(eth); 394 if (ret < 0) 395 return ret; 396 397 mtk_w32(eth, PHY_IAC_ACCESS | 398 PHY_IAC_START_C22 | 399 PHY_IAC_CMD_C22_READ | 400 PHY_IAC_REG(phy_reg) | 401 PHY_IAC_ADDR(phy_addr), 402 MTK_PHY_IAC); 403 404 ret = mtk_mdio_busy_wait(eth); 405 if (ret < 0) 406 return ret; 407 408 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 409 } 410 411 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 412 u32 devad, u32 phy_reg) 413 { 414 int ret; 415 416 ret = mtk_mdio_busy_wait(eth); 417 if (ret < 0) 418 return ret; 419 420 mtk_w32(eth, PHY_IAC_ACCESS | 421 PHY_IAC_START_C45 | 422 PHY_IAC_CMD_C45_ADDR | 423 PHY_IAC_REG(devad) | 424 PHY_IAC_ADDR(phy_addr) | 425 PHY_IAC_DATA(phy_reg), 426 MTK_PHY_IAC); 427 428 ret = mtk_mdio_busy_wait(eth); 429 if (ret < 0) 430 return ret; 431 432 mtk_w32(eth, PHY_IAC_ACCESS | 433 PHY_IAC_START_C45 | 434 PHY_IAC_CMD_C45_READ | 435 PHY_IAC_REG(devad) | 436 PHY_IAC_ADDR(phy_addr), 437 MTK_PHY_IAC); 438 439 ret = mtk_mdio_busy_wait(eth); 440 if (ret < 0) 441 return ret; 442 443 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 444 } 445 446 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 447 int phy_reg, u16 val) 448 { 449 struct mtk_eth *eth = bus->priv; 450 451 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 452 } 453 454 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 455 int devad, int phy_reg, u16 val) 456 { 457 struct mtk_eth *eth = bus->priv; 458 459 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 460 } 461 462 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 463 { 464 struct mtk_eth *eth = bus->priv; 465 466 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 467 } 468 469 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 470 int phy_reg) 471 { 472 struct mtk_eth *eth = bus->priv; 473 474 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 475 } 476 477 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 478 phy_interface_t interface) 479 { 480 u32 val; 481 482 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 483 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 484 485 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 486 ETHSYS_TRGMII_MT7621_MASK, val); 487 488 return 0; 489 } 490 491 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 492 phy_interface_t interface) 493 { 494 int ret; 495 496 if (interface == PHY_INTERFACE_MODE_TRGMII) { 497 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 498 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); 499 if (ret) 500 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 501 return; 502 } 503 504 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); 505 } 506 507 static void mtk_setup_bridge_switch(struct mtk_eth *eth) 508 { 509 /* Force Port1 XGMAC Link Up */ 510 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), 511 MTK_XGMAC_STS(MTK_GMAC1_ID)); 512 513 /* Adjust GSW bridge IPG to 11 */ 514 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, 515 (GSW_IPG_11 << GSWTX_IPG_SHIFT) | 516 (GSW_IPG_11 << GSWRX_IPG_SHIFT), 517 MTK_GSW_CFG); 518 } 519 520 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 521 phy_interface_t interface) 522 { 523 struct mtk_mac *mac = container_of(config, struct mtk_mac, 524 phylink_config); 525 struct mtk_eth *eth = mac->hw; 526 unsigned int sid; 527 528 if (interface == PHY_INTERFACE_MODE_SGMII || 529 phy_interface_mode_is_8023z(interface)) { 530 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 531 0 : mac->id; 532 533 return eth->sgmii_pcs[sid]; 534 } 535 536 return NULL; 537 } 538 539 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 540 const struct phylink_link_state *state) 541 { 542 struct mtk_mac *mac = container_of(config, struct mtk_mac, 543 phylink_config); 544 struct mtk_eth *eth = mac->hw; 545 int val, ge_mode, err = 0; 546 u32 i; 547 548 /* MT76x8 has no hardware settings between for the MAC */ 549 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 550 mac->interface != state->interface) { 551 /* Setup soc pin functions */ 552 switch (state->interface) { 553 case PHY_INTERFACE_MODE_TRGMII: 554 case PHY_INTERFACE_MODE_RGMII_TXID: 555 case PHY_INTERFACE_MODE_RGMII_RXID: 556 case PHY_INTERFACE_MODE_RGMII_ID: 557 case PHY_INTERFACE_MODE_RGMII: 558 case PHY_INTERFACE_MODE_MII: 559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 560 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 561 if (err) 562 goto init_err; 563 } 564 break; 565 case PHY_INTERFACE_MODE_1000BASEX: 566 case PHY_INTERFACE_MODE_2500BASEX: 567 case PHY_INTERFACE_MODE_SGMII: 568 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 569 if (err) 570 goto init_err; 571 break; 572 case PHY_INTERFACE_MODE_GMII: 573 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 574 err = mtk_gmac_gephy_path_setup(eth, mac->id); 575 if (err) 576 goto init_err; 577 } 578 break; 579 case PHY_INTERFACE_MODE_INTERNAL: 580 break; 581 default: 582 goto err_phy; 583 } 584 585 /* Setup clock for 1st gmac */ 586 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 587 !phy_interface_mode_is_8023z(state->interface) && 588 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 589 if (MTK_HAS_CAPS(mac->hw->soc->caps, 590 MTK_TRGMII_MT7621_CLK)) { 591 if (mt7621_gmac0_rgmii_adjust(mac->hw, 592 state->interface)) 593 goto err_phy; 594 } else { 595 mtk_gmac0_rgmii_adjust(mac->hw, 596 state->interface); 597 598 /* mt7623_pad_clk_setup */ 599 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 600 mtk_w32(mac->hw, 601 TD_DM_DRVP(8) | TD_DM_DRVN(8), 602 TRGMII_TD_ODT(i)); 603 604 /* Assert/release MT7623 RXC reset */ 605 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 606 TRGMII_RCK_CTRL); 607 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 608 } 609 } 610 611 switch (state->interface) { 612 case PHY_INTERFACE_MODE_MII: 613 case PHY_INTERFACE_MODE_GMII: 614 ge_mode = 1; 615 break; 616 default: 617 ge_mode = 0; 618 break; 619 } 620 621 /* put the gmac into the right mode */ 622 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 623 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 624 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 625 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 626 627 mac->interface = state->interface; 628 } 629 630 /* SGMII */ 631 if (state->interface == PHY_INTERFACE_MODE_SGMII || 632 phy_interface_mode_is_8023z(state->interface)) { 633 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 634 * being setup done. 635 */ 636 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 637 638 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 639 SYSCFG0_SGMII_MASK, 640 ~(u32)SYSCFG0_SGMII_MASK); 641 642 /* Save the syscfg0 value for mac_finish */ 643 mac->syscfg0 = val; 644 } else if (phylink_autoneg_inband(mode)) { 645 dev_err(eth->dev, 646 "In-band mode not supported in non SGMII mode!\n"); 647 return; 648 } 649 650 /* Setup gmac */ 651 if (mtk_is_netsys_v3_or_greater(eth) && 652 mac->interface == PHY_INTERFACE_MODE_INTERNAL) { 653 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); 654 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); 655 656 mtk_setup_bridge_switch(eth); 657 } 658 659 return; 660 661 err_phy: 662 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 663 mac->id, phy_modes(state->interface)); 664 return; 665 666 init_err: 667 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 668 mac->id, phy_modes(state->interface), err); 669 } 670 671 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 672 phy_interface_t interface) 673 { 674 struct mtk_mac *mac = container_of(config, struct mtk_mac, 675 phylink_config); 676 struct mtk_eth *eth = mac->hw; 677 u32 mcr_cur, mcr_new; 678 679 /* Enable SGMII */ 680 if (interface == PHY_INTERFACE_MODE_SGMII || 681 phy_interface_mode_is_8023z(interface)) 682 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 683 SYSCFG0_SGMII_MASK, mac->syscfg0); 684 685 /* Setup gmac */ 686 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 687 mcr_new = mcr_cur; 688 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 689 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS; 690 691 /* Only update control register when needed! */ 692 if (mcr_new != mcr_cur) 693 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 694 695 return 0; 696 } 697 698 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 699 phy_interface_t interface) 700 { 701 struct mtk_mac *mac = container_of(config, struct mtk_mac, 702 phylink_config); 703 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 704 705 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK); 706 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 707 } 708 709 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 710 int speed) 711 { 712 const struct mtk_soc_data *soc = eth->soc; 713 u32 ofs, val; 714 715 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 716 return; 717 718 val = MTK_QTX_SCH_MIN_RATE_EN | 719 /* minimum: 10 Mbps */ 720 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 721 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 722 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 723 if (mtk_is_netsys_v1(eth)) 724 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 725 726 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 727 switch (speed) { 728 case SPEED_10: 729 val |= MTK_QTX_SCH_MAX_RATE_EN | 730 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 731 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 732 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 733 break; 734 case SPEED_100: 735 val |= MTK_QTX_SCH_MAX_RATE_EN | 736 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 737 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 738 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 739 break; 740 case SPEED_1000: 741 val |= MTK_QTX_SCH_MAX_RATE_EN | 742 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 743 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 744 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 745 break; 746 default: 747 break; 748 } 749 } else { 750 switch (speed) { 751 case SPEED_10: 752 val |= MTK_QTX_SCH_MAX_RATE_EN | 753 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 754 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 755 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 756 break; 757 case SPEED_100: 758 val |= MTK_QTX_SCH_MAX_RATE_EN | 759 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 760 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 761 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 762 break; 763 case SPEED_1000: 764 val |= MTK_QTX_SCH_MAX_RATE_EN | 765 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 766 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 767 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 768 break; 769 default: 770 break; 771 } 772 } 773 774 ofs = MTK_QTX_OFFSET * idx; 775 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 776 } 777 778 static void mtk_mac_link_up(struct phylink_config *config, 779 struct phy_device *phy, 780 unsigned int mode, phy_interface_t interface, 781 int speed, int duplex, bool tx_pause, bool rx_pause) 782 { 783 struct mtk_mac *mac = container_of(config, struct mtk_mac, 784 phylink_config); 785 u32 mcr; 786 787 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 788 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 789 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 790 MAC_MCR_FORCE_RX_FC); 791 792 /* Configure speed */ 793 mac->speed = speed; 794 switch (speed) { 795 case SPEED_2500: 796 case SPEED_1000: 797 mcr |= MAC_MCR_SPEED_1000; 798 break; 799 case SPEED_100: 800 mcr |= MAC_MCR_SPEED_100; 801 break; 802 } 803 804 /* Configure duplex */ 805 if (duplex == DUPLEX_FULL) 806 mcr |= MAC_MCR_FORCE_DPX; 807 808 /* Configure pause modes - phylink will avoid these for half duplex */ 809 if (tx_pause) 810 mcr |= MAC_MCR_FORCE_TX_FC; 811 if (rx_pause) 812 mcr |= MAC_MCR_FORCE_RX_FC; 813 814 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK; 815 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 816 } 817 818 static void mtk_mac_disable_tx_lpi(struct phylink_config *config) 819 { 820 struct mtk_mac *mac = container_of(config, struct mtk_mac, 821 phylink_config); 822 struct mtk_eth *eth = mac->hw; 823 824 mtk_m32(eth, MAC_MCR_EEE100M | MAC_MCR_EEE1G, 0, MTK_MAC_MCR(mac->id)); 825 } 826 827 static int mtk_mac_enable_tx_lpi(struct phylink_config *config, u32 timer, 828 bool tx_clk_stop) 829 { 830 struct mtk_mac *mac = container_of(config, struct mtk_mac, 831 phylink_config); 832 struct mtk_eth *eth = mac->hw; 833 u32 val; 834 835 /* Tx idle timer in ms */ 836 timer = DIV_ROUND_UP(timer, 1000); 837 838 /* If the timer is zero, then set LPI_MODE, which allows the 839 * system to enter LPI mode immediately rather than waiting for 840 * the LPI threshold. 841 */ 842 if (!timer) 843 val = MAC_EEE_LPI_MODE; 844 else if (FIELD_FIT(MAC_EEE_LPI_TXIDLE_THD, timer)) 845 val = FIELD_PREP(MAC_EEE_LPI_TXIDLE_THD, timer); 846 else 847 val = MAC_EEE_LPI_TXIDLE_THD; 848 849 if (tx_clk_stop) 850 val |= MAC_EEE_CKG_TXIDLE; 851 852 /* PHY Wake-up time, this field does not have a reset value, so use the 853 * reset value from MT7531 (36us for 100M and 17us for 1000M). 854 */ 855 val |= FIELD_PREP(MAC_EEE_WAKEUP_TIME_1000, 17) | 856 FIELD_PREP(MAC_EEE_WAKEUP_TIME_100, 36); 857 858 mtk_w32(eth, val, MTK_MAC_EEECR(mac->id)); 859 mtk_m32(eth, 0, MAC_MCR_EEE100M | MAC_MCR_EEE1G, MTK_MAC_MCR(mac->id)); 860 861 return 0; 862 } 863 864 static const struct phylink_mac_ops mtk_phylink_ops = { 865 .mac_select_pcs = mtk_mac_select_pcs, 866 .mac_config = mtk_mac_config, 867 .mac_finish = mtk_mac_finish, 868 .mac_link_down = mtk_mac_link_down, 869 .mac_link_up = mtk_mac_link_up, 870 .mac_disable_tx_lpi = mtk_mac_disable_tx_lpi, 871 .mac_enable_tx_lpi = mtk_mac_enable_tx_lpi, 872 }; 873 874 static int mtk_mdio_init(struct mtk_eth *eth) 875 { 876 unsigned int max_clk = 2500000, divider; 877 struct device_node *mii_np; 878 int ret; 879 u32 val; 880 881 mii_np = of_get_available_child_by_name(eth->dev->of_node, "mdio-bus"); 882 if (!mii_np) { 883 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 884 return -ENODEV; 885 } 886 887 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 888 if (!eth->mii_bus) { 889 ret = -ENOMEM; 890 goto err_put_node; 891 } 892 893 eth->mii_bus->name = "mdio"; 894 eth->mii_bus->read = mtk_mdio_read_c22; 895 eth->mii_bus->write = mtk_mdio_write_c22; 896 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 897 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 898 eth->mii_bus->priv = eth; 899 eth->mii_bus->parent = eth->dev; 900 901 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 902 903 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { 904 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { 905 dev_err(eth->dev, "MDIO clock frequency out of range"); 906 ret = -EINVAL; 907 goto err_put_node; 908 } 909 max_clk = val; 910 } 911 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 912 913 /* Configure MDC Turbo Mode */ 914 if (mtk_is_netsys_v3_or_greater(eth)) 915 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); 916 917 /* Configure MDC Divider */ 918 val = FIELD_PREP(PPSC_MDC_CFG, divider); 919 if (!mtk_is_netsys_v3_or_greater(eth)) 920 val |= PPSC_MDC_TURBO; 921 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); 922 923 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); 924 925 ret = of_mdiobus_register(eth->mii_bus, mii_np); 926 927 err_put_node: 928 of_node_put(mii_np); 929 return ret; 930 } 931 932 static void mtk_mdio_cleanup(struct mtk_eth *eth) 933 { 934 if (!eth->mii_bus) 935 return; 936 937 mdiobus_unregister(eth->mii_bus); 938 } 939 940 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 941 { 942 unsigned long flags; 943 u32 val; 944 945 spin_lock_irqsave(ð->tx_irq_lock, flags); 946 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 947 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 948 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 949 } 950 951 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 952 { 953 unsigned long flags; 954 u32 val; 955 956 spin_lock_irqsave(ð->tx_irq_lock, flags); 957 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 958 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 959 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 960 } 961 962 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 963 { 964 unsigned long flags; 965 u32 val; 966 967 spin_lock_irqsave(ð->rx_irq_lock, flags); 968 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 969 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 970 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 971 } 972 973 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 974 { 975 unsigned long flags; 976 u32 val; 977 978 spin_lock_irqsave(ð->rx_irq_lock, flags); 979 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 980 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 981 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 982 } 983 984 static int mtk_set_mac_address(struct net_device *dev, void *p) 985 { 986 int ret = eth_mac_addr(dev, p); 987 struct mtk_mac *mac = netdev_priv(dev); 988 struct mtk_eth *eth = mac->hw; 989 const char *macaddr = dev->dev_addr; 990 991 if (ret) 992 return ret; 993 994 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 995 return -EBUSY; 996 997 spin_lock_bh(&mac->hw->page_lock); 998 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 999 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 1000 MT7628_SDM_MAC_ADRH); 1001 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 1002 (macaddr[4] << 8) | macaddr[5], 1003 MT7628_SDM_MAC_ADRL); 1004 } else { 1005 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 1006 MTK_GDMA_MAC_ADRH(mac->id)); 1007 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 1008 (macaddr[4] << 8) | macaddr[5], 1009 MTK_GDMA_MAC_ADRL(mac->id)); 1010 } 1011 spin_unlock_bh(&mac->hw->page_lock); 1012 1013 return 0; 1014 } 1015 1016 void mtk_stats_update_mac(struct mtk_mac *mac) 1017 { 1018 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1019 struct mtk_eth *eth = mac->hw; 1020 1021 u64_stats_update_begin(&hw_stats->syncp); 1022 1023 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 1024 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 1025 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 1026 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 1027 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 1028 hw_stats->rx_checksum_errors += 1029 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 1030 } else { 1031 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 1032 unsigned int offs = hw_stats->reg_offset; 1033 u64 stats; 1034 1035 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 1036 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 1037 if (stats) 1038 hw_stats->rx_bytes += (stats << 32); 1039 hw_stats->rx_packets += 1040 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 1041 hw_stats->rx_overflow += 1042 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 1043 hw_stats->rx_fcs_errors += 1044 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 1045 hw_stats->rx_short_errors += 1046 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 1047 hw_stats->rx_long_errors += 1048 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 1049 hw_stats->rx_checksum_errors += 1050 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 1051 hw_stats->rx_flow_control_packets += 1052 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 1053 1054 if (mtk_is_netsys_v3_or_greater(eth)) { 1055 hw_stats->tx_skip += 1056 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); 1057 hw_stats->tx_collisions += 1058 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); 1059 hw_stats->tx_bytes += 1060 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); 1061 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); 1062 if (stats) 1063 hw_stats->tx_bytes += (stats << 32); 1064 hw_stats->tx_packets += 1065 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); 1066 } else { 1067 hw_stats->tx_skip += 1068 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 1069 hw_stats->tx_collisions += 1070 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 1071 hw_stats->tx_bytes += 1072 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 1073 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 1074 if (stats) 1075 hw_stats->tx_bytes += (stats << 32); 1076 hw_stats->tx_packets += 1077 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 1078 } 1079 } 1080 1081 u64_stats_update_end(&hw_stats->syncp); 1082 } 1083 1084 static void mtk_stats_update(struct mtk_eth *eth) 1085 { 1086 int i; 1087 1088 for (i = 0; i < MTK_MAX_DEVS; i++) { 1089 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 1090 continue; 1091 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 1092 mtk_stats_update_mac(eth->mac[i]); 1093 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 1094 } 1095 } 1096 } 1097 1098 static void mtk_get_stats64(struct net_device *dev, 1099 struct rtnl_link_stats64 *storage) 1100 { 1101 struct mtk_mac *mac = netdev_priv(dev); 1102 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1103 unsigned int start; 1104 1105 if (netif_running(dev) && netif_device_present(dev)) { 1106 if (spin_trylock_bh(&hw_stats->stats_lock)) { 1107 mtk_stats_update_mac(mac); 1108 spin_unlock_bh(&hw_stats->stats_lock); 1109 } 1110 } 1111 1112 do { 1113 start = u64_stats_fetch_begin(&hw_stats->syncp); 1114 storage->rx_packets = hw_stats->rx_packets; 1115 storage->tx_packets = hw_stats->tx_packets; 1116 storage->rx_bytes = hw_stats->rx_bytes; 1117 storage->tx_bytes = hw_stats->tx_bytes; 1118 storage->collisions = hw_stats->tx_collisions; 1119 storage->rx_length_errors = hw_stats->rx_short_errors + 1120 hw_stats->rx_long_errors; 1121 storage->rx_over_errors = hw_stats->rx_overflow; 1122 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1123 storage->rx_errors = hw_stats->rx_checksum_errors; 1124 storage->tx_aborted_errors = hw_stats->tx_skip; 1125 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1126 1127 storage->tx_errors = dev->stats.tx_errors; 1128 storage->rx_dropped = dev->stats.rx_dropped; 1129 storage->tx_dropped = dev->stats.tx_dropped; 1130 } 1131 1132 static inline int mtk_max_frag_size(int mtu) 1133 { 1134 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1135 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1136 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1137 1138 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1139 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1140 } 1141 1142 static inline int mtk_max_buf_size(int frag_size) 1143 { 1144 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1145 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1146 1147 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1148 1149 return buf_size; 1150 } 1151 1152 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1153 struct mtk_rx_dma_v2 *dma_rxd) 1154 { 1155 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1156 if (!(rxd->rxd2 & RX_DMA_DONE)) 1157 return false; 1158 1159 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1160 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1161 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1162 if (mtk_is_netsys_v3_or_greater(eth)) { 1163 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1164 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1165 } 1166 1167 return true; 1168 } 1169 1170 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1171 { 1172 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1173 unsigned long data; 1174 1175 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1176 get_order(size)); 1177 1178 return (void *)data; 1179 } 1180 1181 /* the qdma core needs scratch memory to be setup */ 1182 static int mtk_init_fq_dma(struct mtk_eth *eth) 1183 { 1184 const struct mtk_soc_data *soc = eth->soc; 1185 dma_addr_t phy_ring_tail; 1186 int cnt = soc->tx.fq_dma_size; 1187 dma_addr_t dma_addr; 1188 int i, j, len; 1189 1190 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) 1191 eth->scratch_ring = eth->sram_base; 1192 else 1193 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1194 cnt * soc->tx.desc_size, 1195 ð->phy_scratch_ring, 1196 GFP_KERNEL); 1197 1198 if (unlikely(!eth->scratch_ring)) 1199 return -ENOMEM; 1200 1201 phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1); 1202 1203 for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) { 1204 len = min_t(int, cnt - j * MTK_FQ_DMA_LENGTH, MTK_FQ_DMA_LENGTH); 1205 eth->scratch_head[j] = kcalloc(len, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1206 1207 if (unlikely(!eth->scratch_head[j])) 1208 return -ENOMEM; 1209 1210 dma_addr = dma_map_single(eth->dma_dev, 1211 eth->scratch_head[j], len * MTK_QDMA_PAGE_SIZE, 1212 DMA_FROM_DEVICE); 1213 1214 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1215 return -ENOMEM; 1216 1217 for (i = 0; i < len; i++) { 1218 struct mtk_tx_dma_v2 *txd; 1219 1220 txd = eth->scratch_ring + (j * MTK_FQ_DMA_LENGTH + i) * soc->tx.desc_size; 1221 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1222 if (j * MTK_FQ_DMA_LENGTH + i < cnt) 1223 txd->txd2 = eth->phy_scratch_ring + 1224 (j * MTK_FQ_DMA_LENGTH + i + 1) * soc->tx.desc_size; 1225 1226 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1227 if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA)) 1228 txd->txd3 |= TX_DMA_PREP_ADDR64(dma_addr + i * MTK_QDMA_PAGE_SIZE); 1229 1230 txd->txd4 = 0; 1231 if (mtk_is_netsys_v2_or_greater(eth)) { 1232 txd->txd5 = 0; 1233 txd->txd6 = 0; 1234 txd->txd7 = 0; 1235 txd->txd8 = 0; 1236 } 1237 } 1238 } 1239 1240 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1241 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1242 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1243 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1244 1245 return 0; 1246 } 1247 1248 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1249 { 1250 return ring->dma + (desc - ring->phys); 1251 } 1252 1253 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1254 void *txd, u32 txd_size) 1255 { 1256 int idx = (txd - ring->dma) / txd_size; 1257 1258 return &ring->buf[idx]; 1259 } 1260 1261 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1262 struct mtk_tx_dma *dma) 1263 { 1264 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1265 } 1266 1267 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1268 { 1269 return (dma - ring->dma) / txd_size; 1270 } 1271 1272 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1273 struct xdp_frame_bulk *bq, bool napi) 1274 { 1275 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1276 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1277 dma_unmap_single(eth->dma_dev, 1278 dma_unmap_addr(tx_buf, dma_addr0), 1279 dma_unmap_len(tx_buf, dma_len0), 1280 DMA_TO_DEVICE); 1281 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1282 dma_unmap_page(eth->dma_dev, 1283 dma_unmap_addr(tx_buf, dma_addr0), 1284 dma_unmap_len(tx_buf, dma_len0), 1285 DMA_TO_DEVICE); 1286 } 1287 } else { 1288 if (dma_unmap_len(tx_buf, dma_len0)) { 1289 dma_unmap_page(eth->dma_dev, 1290 dma_unmap_addr(tx_buf, dma_addr0), 1291 dma_unmap_len(tx_buf, dma_len0), 1292 DMA_TO_DEVICE); 1293 } 1294 1295 if (dma_unmap_len(tx_buf, dma_len1)) { 1296 dma_unmap_page(eth->dma_dev, 1297 dma_unmap_addr(tx_buf, dma_addr1), 1298 dma_unmap_len(tx_buf, dma_len1), 1299 DMA_TO_DEVICE); 1300 } 1301 } 1302 1303 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1304 if (tx_buf->type == MTK_TYPE_SKB) { 1305 struct sk_buff *skb = tx_buf->data; 1306 1307 if (napi) 1308 napi_consume_skb(skb, napi); 1309 else 1310 dev_kfree_skb_any(skb); 1311 } else { 1312 struct xdp_frame *xdpf = tx_buf->data; 1313 1314 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1315 xdp_return_frame_rx_napi(xdpf); 1316 else if (bq) 1317 xdp_return_frame_bulk(xdpf, bq); 1318 else 1319 xdp_return_frame(xdpf); 1320 } 1321 } 1322 tx_buf->flags = 0; 1323 tx_buf->data = NULL; 1324 } 1325 1326 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1327 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1328 size_t size, int idx) 1329 { 1330 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1331 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1332 dma_unmap_len_set(tx_buf, dma_len0, size); 1333 } else { 1334 if (idx & 1) { 1335 txd->txd3 = mapped_addr; 1336 txd->txd2 |= TX_DMA_PLEN1(size); 1337 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1338 dma_unmap_len_set(tx_buf, dma_len1, size); 1339 } else { 1340 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1341 txd->txd1 = mapped_addr; 1342 txd->txd2 = TX_DMA_PLEN0(size); 1343 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1344 dma_unmap_len_set(tx_buf, dma_len0, size); 1345 } 1346 } 1347 } 1348 1349 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1350 struct mtk_tx_dma_desc_info *info) 1351 { 1352 struct mtk_mac *mac = netdev_priv(dev); 1353 struct mtk_eth *eth = mac->hw; 1354 struct mtk_tx_dma *desc = txd; 1355 u32 data; 1356 1357 WRITE_ONCE(desc->txd1, info->addr); 1358 1359 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1360 FIELD_PREP(TX_DMA_PQID, info->qid); 1361 if (info->last) 1362 data |= TX_DMA_LS0; 1363 WRITE_ONCE(desc->txd3, data); 1364 1365 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1366 if (info->first) { 1367 if (info->gso) 1368 data |= TX_DMA_TSO; 1369 /* tx checksum offload */ 1370 if (info->csum) 1371 data |= TX_DMA_CHKSUM; 1372 /* vlan header offload */ 1373 if (info->vlan) 1374 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1375 } 1376 WRITE_ONCE(desc->txd4, data); 1377 } 1378 1379 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1380 struct mtk_tx_dma_desc_info *info) 1381 { 1382 struct mtk_mac *mac = netdev_priv(dev); 1383 struct mtk_tx_dma_v2 *desc = txd; 1384 struct mtk_eth *eth = mac->hw; 1385 u32 data; 1386 1387 WRITE_ONCE(desc->txd1, info->addr); 1388 1389 data = TX_DMA_PLEN0(info->size); 1390 if (info->last) 1391 data |= TX_DMA_LS0; 1392 1393 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 1394 data |= TX_DMA_PREP_ADDR64(info->addr); 1395 1396 WRITE_ONCE(desc->txd3, data); 1397 1398 /* set forward port */ 1399 switch (mac->id) { 1400 case MTK_GMAC1_ID: 1401 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; 1402 break; 1403 case MTK_GMAC2_ID: 1404 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; 1405 break; 1406 case MTK_GMAC3_ID: 1407 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; 1408 break; 1409 } 1410 1411 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1412 WRITE_ONCE(desc->txd4, data); 1413 1414 data = 0; 1415 if (info->first) { 1416 if (info->gso) 1417 data |= TX_DMA_TSO_V2; 1418 /* tx checksum offload */ 1419 if (info->csum) 1420 data |= TX_DMA_CHKSUM_V2; 1421 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) 1422 data |= TX_DMA_SPTAG_V3; 1423 } 1424 WRITE_ONCE(desc->txd5, data); 1425 1426 data = 0; 1427 if (info->first && info->vlan) 1428 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1429 WRITE_ONCE(desc->txd6, data); 1430 1431 WRITE_ONCE(desc->txd7, 0); 1432 WRITE_ONCE(desc->txd8, 0); 1433 } 1434 1435 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1436 struct mtk_tx_dma_desc_info *info) 1437 { 1438 struct mtk_mac *mac = netdev_priv(dev); 1439 struct mtk_eth *eth = mac->hw; 1440 1441 if (mtk_is_netsys_v2_or_greater(eth)) 1442 mtk_tx_set_dma_desc_v2(dev, txd, info); 1443 else 1444 mtk_tx_set_dma_desc_v1(dev, txd, info); 1445 } 1446 1447 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1448 int tx_num, struct mtk_tx_ring *ring, bool gso) 1449 { 1450 struct mtk_tx_dma_desc_info txd_info = { 1451 .size = skb_headlen(skb), 1452 .gso = gso, 1453 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1454 .vlan = skb_vlan_tag_present(skb), 1455 .qid = skb_get_queue_mapping(skb), 1456 .vlan_tci = skb_vlan_tag_get(skb), 1457 .first = true, 1458 .last = !skb_is_nonlinear(skb), 1459 }; 1460 struct netdev_queue *txq; 1461 struct mtk_mac *mac = netdev_priv(dev); 1462 struct mtk_eth *eth = mac->hw; 1463 const struct mtk_soc_data *soc = eth->soc; 1464 struct mtk_tx_dma *itxd, *txd; 1465 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1466 struct mtk_tx_buf *itx_buf, *tx_buf; 1467 int i, n_desc = 1; 1468 int queue = skb_get_queue_mapping(skb); 1469 int k = 0; 1470 1471 txq = netdev_get_tx_queue(dev, queue); 1472 itxd = ring->next_free; 1473 itxd_pdma = qdma_to_pdma(ring, itxd); 1474 if (itxd == ring->last_free) 1475 return -ENOMEM; 1476 1477 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); 1478 memset(itx_buf, 0, sizeof(*itx_buf)); 1479 1480 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1481 DMA_TO_DEVICE); 1482 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1483 return -ENOMEM; 1484 1485 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1486 1487 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1488 itx_buf->mac_id = mac->id; 1489 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1490 k++); 1491 1492 /* TX SG offload */ 1493 txd = itxd; 1494 txd_pdma = qdma_to_pdma(ring, txd); 1495 1496 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1497 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1498 unsigned int offset = 0; 1499 int frag_size = skb_frag_size(frag); 1500 1501 while (frag_size) { 1502 bool new_desc = true; 1503 1504 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1505 (i & 0x1)) { 1506 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1507 txd_pdma = qdma_to_pdma(ring, txd); 1508 if (txd == ring->last_free) 1509 goto err_dma; 1510 1511 n_desc++; 1512 } else { 1513 new_desc = false; 1514 } 1515 1516 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1517 txd_info.size = min_t(unsigned int, frag_size, 1518 soc->tx.dma_max_len); 1519 txd_info.qid = queue; 1520 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1521 !(frag_size - txd_info.size); 1522 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1523 offset, txd_info.size, 1524 DMA_TO_DEVICE); 1525 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1526 goto err_dma; 1527 1528 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1529 1530 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1531 soc->tx.desc_size); 1532 if (new_desc) 1533 memset(tx_buf, 0, sizeof(*tx_buf)); 1534 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1535 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1536 tx_buf->mac_id = mac->id; 1537 1538 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1539 txd_info.size, k++); 1540 1541 frag_size -= txd_info.size; 1542 offset += txd_info.size; 1543 } 1544 } 1545 1546 /* store skb to cleanup */ 1547 itx_buf->type = MTK_TYPE_SKB; 1548 itx_buf->data = skb; 1549 1550 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1551 if (k & 0x1) 1552 txd_pdma->txd2 |= TX_DMA_LS0; 1553 else 1554 txd_pdma->txd2 |= TX_DMA_LS1; 1555 } 1556 1557 netdev_tx_sent_queue(txq, skb->len); 1558 skb_tx_timestamp(skb); 1559 1560 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1561 atomic_sub(n_desc, &ring->free_count); 1562 1563 /* make sure that all changes to the dma ring are flushed before we 1564 * continue 1565 */ 1566 wmb(); 1567 1568 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1569 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1570 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1571 } else { 1572 int next_idx; 1573 1574 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size), 1575 ring->dma_size); 1576 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1577 } 1578 1579 return 0; 1580 1581 err_dma: 1582 do { 1583 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); 1584 1585 /* unmap dma */ 1586 mtk_tx_unmap(eth, tx_buf, NULL, false); 1587 1588 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1589 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1590 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1591 1592 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1593 itxd_pdma = qdma_to_pdma(ring, itxd); 1594 } while (itxd != txd); 1595 1596 return -ENOMEM; 1597 } 1598 1599 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1600 { 1601 int i, nfrags = 1; 1602 skb_frag_t *frag; 1603 1604 if (skb_is_gso(skb)) { 1605 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1606 frag = &skb_shinfo(skb)->frags[i]; 1607 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1608 eth->soc->tx.dma_max_len); 1609 } 1610 } else { 1611 nfrags += skb_shinfo(skb)->nr_frags; 1612 } 1613 1614 return nfrags; 1615 } 1616 1617 static int mtk_queue_stopped(struct mtk_eth *eth) 1618 { 1619 int i; 1620 1621 for (i = 0; i < MTK_MAX_DEVS; i++) { 1622 if (!eth->netdev[i]) 1623 continue; 1624 if (netif_queue_stopped(eth->netdev[i])) 1625 return 1; 1626 } 1627 1628 return 0; 1629 } 1630 1631 static void mtk_wake_queue(struct mtk_eth *eth) 1632 { 1633 int i; 1634 1635 for (i = 0; i < MTK_MAX_DEVS; i++) { 1636 if (!eth->netdev[i]) 1637 continue; 1638 netif_tx_wake_all_queues(eth->netdev[i]); 1639 } 1640 } 1641 1642 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1643 { 1644 struct mtk_mac *mac = netdev_priv(dev); 1645 struct mtk_eth *eth = mac->hw; 1646 struct mtk_tx_ring *ring = ð->tx_ring; 1647 struct net_device_stats *stats = &dev->stats; 1648 bool gso = false; 1649 int tx_num; 1650 1651 /* normally we can rely on the stack not calling this more than once, 1652 * however we have 2 queues running on the same ring so we need to lock 1653 * the ring access 1654 */ 1655 spin_lock(ð->page_lock); 1656 1657 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1658 goto drop; 1659 1660 tx_num = mtk_cal_txd_req(eth, skb); 1661 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1662 netif_tx_stop_all_queues(dev); 1663 netif_err(eth, tx_queued, dev, 1664 "Tx Ring full when queue awake!\n"); 1665 spin_unlock(ð->page_lock); 1666 return NETDEV_TX_BUSY; 1667 } 1668 1669 /* TSO: fill MSS info in tcp checksum field */ 1670 if (skb_is_gso(skb)) { 1671 if (skb_cow_head(skb, 0)) { 1672 netif_warn(eth, tx_err, dev, 1673 "GSO expand head fail.\n"); 1674 goto drop; 1675 } 1676 1677 if (skb_shinfo(skb)->gso_type & 1678 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1679 gso = true; 1680 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1681 } 1682 } 1683 1684 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1685 goto drop; 1686 1687 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1688 netif_tx_stop_all_queues(dev); 1689 1690 spin_unlock(ð->page_lock); 1691 1692 return NETDEV_TX_OK; 1693 1694 drop: 1695 spin_unlock(ð->page_lock); 1696 stats->tx_dropped++; 1697 dev_kfree_skb_any(skb); 1698 return NETDEV_TX_OK; 1699 } 1700 1701 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1702 { 1703 int i; 1704 struct mtk_rx_ring *ring; 1705 int idx; 1706 1707 if (!eth->hwlro) 1708 return ð->rx_ring[0]; 1709 1710 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1711 struct mtk_rx_dma *rxd; 1712 1713 ring = ð->rx_ring[i]; 1714 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1715 rxd = ring->dma + idx * eth->soc->rx.desc_size; 1716 if (rxd->rxd2 & RX_DMA_DONE) { 1717 ring->calc_idx_update = true; 1718 return ring; 1719 } 1720 } 1721 1722 return NULL; 1723 } 1724 1725 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1726 { 1727 struct mtk_rx_ring *ring; 1728 int i; 1729 1730 if (!eth->hwlro) { 1731 ring = ð->rx_ring[0]; 1732 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1733 } else { 1734 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1735 ring = ð->rx_ring[i]; 1736 if (ring->calc_idx_update) { 1737 ring->calc_idx_update = false; 1738 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1739 } 1740 } 1741 } 1742 } 1743 1744 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1745 { 1746 return mtk_is_netsys_v2_or_greater(eth); 1747 } 1748 1749 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1750 struct xdp_rxq_info *xdp_q, 1751 int id, int size) 1752 { 1753 struct page_pool_params pp_params = { 1754 .order = 0, 1755 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1756 .pool_size = size, 1757 .nid = NUMA_NO_NODE, 1758 .dev = eth->dma_dev, 1759 .offset = MTK_PP_HEADROOM, 1760 .max_len = MTK_PP_MAX_BUF_SIZE, 1761 }; 1762 struct page_pool *pp; 1763 int err; 1764 1765 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1766 : DMA_FROM_DEVICE; 1767 pp = page_pool_create(&pp_params); 1768 if (IS_ERR(pp)) 1769 return pp; 1770 1771 err = __xdp_rxq_info_reg(xdp_q, eth->dummy_dev, id, 1772 eth->rx_napi.napi_id, PAGE_SIZE); 1773 if (err < 0) 1774 goto err_free_pp; 1775 1776 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1777 if (err) 1778 goto err_unregister_rxq; 1779 1780 return pp; 1781 1782 err_unregister_rxq: 1783 xdp_rxq_info_unreg(xdp_q); 1784 err_free_pp: 1785 page_pool_destroy(pp); 1786 1787 return ERR_PTR(err); 1788 } 1789 1790 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1791 gfp_t gfp_mask) 1792 { 1793 struct page *page; 1794 1795 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1796 if (!page) 1797 return NULL; 1798 1799 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1800 return page_address(page); 1801 } 1802 1803 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1804 { 1805 if (ring->page_pool) 1806 page_pool_put_full_page(ring->page_pool, 1807 virt_to_head_page(data), napi); 1808 else 1809 skb_free_frag(data); 1810 } 1811 1812 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1813 struct mtk_tx_dma_desc_info *txd_info, 1814 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1815 void *data, u16 headroom, int index, bool dma_map) 1816 { 1817 struct mtk_tx_ring *ring = ð->tx_ring; 1818 struct mtk_mac *mac = netdev_priv(dev); 1819 struct mtk_tx_dma *txd_pdma; 1820 1821 if (dma_map) { /* ndo_xdp_xmit */ 1822 txd_info->addr = dma_map_single(eth->dma_dev, data, 1823 txd_info->size, DMA_TO_DEVICE); 1824 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1825 return -ENOMEM; 1826 1827 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1828 } else { 1829 struct page *page = virt_to_head_page(data); 1830 1831 txd_info->addr = page_pool_get_dma_addr(page) + 1832 sizeof(struct xdp_frame) + headroom; 1833 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1834 txd_info->size, DMA_BIDIRECTIONAL); 1835 } 1836 mtk_tx_set_dma_desc(dev, txd, txd_info); 1837 1838 tx_buf->mac_id = mac->id; 1839 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1840 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1841 1842 txd_pdma = qdma_to_pdma(ring, txd); 1843 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1844 index); 1845 1846 return 0; 1847 } 1848 1849 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1850 struct net_device *dev, bool dma_map) 1851 { 1852 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1853 const struct mtk_soc_data *soc = eth->soc; 1854 struct mtk_tx_ring *ring = ð->tx_ring; 1855 struct mtk_mac *mac = netdev_priv(dev); 1856 struct mtk_tx_dma_desc_info txd_info = { 1857 .size = xdpf->len, 1858 .first = true, 1859 .last = !xdp_frame_has_frags(xdpf), 1860 .qid = mac->id, 1861 }; 1862 int err, index = 0, n_desc = 1, nr_frags; 1863 struct mtk_tx_buf *htx_buf, *tx_buf; 1864 struct mtk_tx_dma *htxd, *txd; 1865 void *data = xdpf->data; 1866 1867 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1868 return -EBUSY; 1869 1870 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1871 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1872 return -EBUSY; 1873 1874 spin_lock(ð->page_lock); 1875 1876 txd = ring->next_free; 1877 if (txd == ring->last_free) { 1878 spin_unlock(ð->page_lock); 1879 return -ENOMEM; 1880 } 1881 htxd = txd; 1882 1883 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size); 1884 memset(tx_buf, 0, sizeof(*tx_buf)); 1885 htx_buf = tx_buf; 1886 1887 for (;;) { 1888 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1889 data, xdpf->headroom, index, dma_map); 1890 if (err < 0) 1891 goto unmap; 1892 1893 if (txd_info.last) 1894 break; 1895 1896 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1897 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1898 if (txd == ring->last_free) 1899 goto unmap; 1900 1901 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1902 soc->tx.desc_size); 1903 memset(tx_buf, 0, sizeof(*tx_buf)); 1904 n_desc++; 1905 } 1906 1907 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1908 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1909 txd_info.last = index + 1 == nr_frags; 1910 txd_info.qid = mac->id; 1911 data = skb_frag_address(&sinfo->frags[index]); 1912 1913 index++; 1914 } 1915 /* store xdpf for cleanup */ 1916 htx_buf->data = xdpf; 1917 1918 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1919 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1920 1921 if (index & 1) 1922 txd_pdma->txd2 |= TX_DMA_LS0; 1923 else 1924 txd_pdma->txd2 |= TX_DMA_LS1; 1925 } 1926 1927 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1928 atomic_sub(n_desc, &ring->free_count); 1929 1930 /* make sure that all changes to the dma ring are flushed before we 1931 * continue 1932 */ 1933 wmb(); 1934 1935 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1936 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1937 } else { 1938 int idx; 1939 1940 idx = txd_to_idx(ring, txd, soc->tx.desc_size); 1941 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1942 MT7628_TX_CTX_IDX0); 1943 } 1944 1945 spin_unlock(ð->page_lock); 1946 1947 return 0; 1948 1949 unmap: 1950 while (htxd != txd) { 1951 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size); 1952 mtk_tx_unmap(eth, tx_buf, NULL, false); 1953 1954 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1955 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1956 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1957 1958 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1959 } 1960 1961 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1962 } 1963 1964 spin_unlock(ð->page_lock); 1965 1966 return err; 1967 } 1968 1969 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1970 struct xdp_frame **frames, u32 flags) 1971 { 1972 struct mtk_mac *mac = netdev_priv(dev); 1973 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1974 struct mtk_eth *eth = mac->hw; 1975 int i, nxmit = 0; 1976 1977 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1978 return -EINVAL; 1979 1980 for (i = 0; i < num_frame; i++) { 1981 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1982 break; 1983 nxmit++; 1984 } 1985 1986 u64_stats_update_begin(&hw_stats->syncp); 1987 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1988 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1989 u64_stats_update_end(&hw_stats->syncp); 1990 1991 return nxmit; 1992 } 1993 1994 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1995 struct xdp_buff *xdp, struct net_device *dev) 1996 { 1997 struct mtk_mac *mac = netdev_priv(dev); 1998 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1999 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 2000 struct bpf_prog *prog; 2001 u32 act = XDP_PASS; 2002 2003 rcu_read_lock(); 2004 2005 prog = rcu_dereference(eth->prog); 2006 if (!prog) 2007 goto out; 2008 2009 act = bpf_prog_run_xdp(prog, xdp); 2010 switch (act) { 2011 case XDP_PASS: 2012 count = &hw_stats->xdp_stats.rx_xdp_pass; 2013 goto update_stats; 2014 case XDP_REDIRECT: 2015 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 2016 act = XDP_DROP; 2017 break; 2018 } 2019 2020 count = &hw_stats->xdp_stats.rx_xdp_redirect; 2021 goto update_stats; 2022 case XDP_TX: { 2023 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2024 2025 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 2026 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 2027 act = XDP_DROP; 2028 break; 2029 } 2030 2031 count = &hw_stats->xdp_stats.rx_xdp_tx; 2032 goto update_stats; 2033 } 2034 default: 2035 bpf_warn_invalid_xdp_action(dev, prog, act); 2036 fallthrough; 2037 case XDP_ABORTED: 2038 trace_xdp_exception(dev, prog, act); 2039 fallthrough; 2040 case XDP_DROP: 2041 break; 2042 } 2043 2044 page_pool_put_full_page(ring->page_pool, 2045 virt_to_head_page(xdp->data), true); 2046 2047 update_stats: 2048 u64_stats_update_begin(&hw_stats->syncp); 2049 *count = *count + 1; 2050 u64_stats_update_end(&hw_stats->syncp); 2051 out: 2052 rcu_read_unlock(); 2053 2054 return act; 2055 } 2056 2057 static int mtk_poll_rx(struct napi_struct *napi, int budget, 2058 struct mtk_eth *eth) 2059 { 2060 struct dim_sample dim_sample = {}; 2061 struct mtk_rx_ring *ring; 2062 bool xdp_flush = false; 2063 int idx; 2064 struct sk_buff *skb; 2065 u64 addr64 = 0; 2066 u8 *data, *new_data; 2067 struct mtk_rx_dma_v2 *rxd, trxd; 2068 int done = 0, bytes = 0; 2069 dma_addr_t dma_addr = DMA_MAPPING_ERROR; 2070 int ppe_idx = 0; 2071 2072 while (done < budget) { 2073 unsigned int pktlen, *rxdcsum; 2074 struct net_device *netdev; 2075 u32 hash, reason; 2076 int mac = 0; 2077 2078 ring = mtk_get_rx_ring(eth); 2079 if (unlikely(!ring)) 2080 goto rx_done; 2081 2082 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 2083 rxd = ring->dma + idx * eth->soc->rx.desc_size; 2084 data = ring->data[idx]; 2085 2086 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 2087 break; 2088 2089 /* find out which mac the packet come from. values start at 1 */ 2090 if (mtk_is_netsys_v3_or_greater(eth)) { 2091 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); 2092 2093 switch (val) { 2094 case PSE_GDM1_PORT: 2095 case PSE_GDM2_PORT: 2096 mac = val - 1; 2097 break; 2098 case PSE_GDM3_PORT: 2099 mac = MTK_GMAC3_ID; 2100 break; 2101 default: 2102 break; 2103 } 2104 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 2105 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { 2106 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 2107 } 2108 2109 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || 2110 !eth->netdev[mac])) 2111 goto release_desc; 2112 2113 netdev = eth->netdev[mac]; 2114 ppe_idx = eth->mac[mac]->ppe_idx; 2115 2116 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 2117 goto release_desc; 2118 2119 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 2120 2121 /* alloc new buffer */ 2122 if (ring->page_pool) { 2123 struct page *page = virt_to_head_page(data); 2124 struct xdp_buff xdp; 2125 u32 ret, metasize; 2126 2127 new_data = mtk_page_pool_get_buff(ring->page_pool, 2128 &dma_addr, 2129 GFP_ATOMIC); 2130 if (unlikely(!new_data)) { 2131 netdev->stats.rx_dropped++; 2132 goto release_desc; 2133 } 2134 2135 dma_sync_single_for_cpu(eth->dma_dev, 2136 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 2137 pktlen, page_pool_get_dma_dir(ring->page_pool)); 2138 2139 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 2140 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 2141 true); 2142 xdp_buff_clear_frags_flag(&xdp); 2143 2144 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 2145 if (ret == XDP_REDIRECT) 2146 xdp_flush = true; 2147 2148 if (ret != XDP_PASS) 2149 goto skip_rx; 2150 2151 skb = build_skb(data, PAGE_SIZE); 2152 if (unlikely(!skb)) { 2153 page_pool_put_full_page(ring->page_pool, 2154 page, true); 2155 netdev->stats.rx_dropped++; 2156 goto skip_rx; 2157 } 2158 2159 skb_reserve(skb, xdp.data - xdp.data_hard_start); 2160 skb_put(skb, xdp.data_end - xdp.data); 2161 metasize = xdp.data - xdp.data_meta; 2162 if (metasize) 2163 skb_metadata_set(skb, metasize); 2164 skb_mark_for_recycle(skb); 2165 } else { 2166 if (ring->frag_size <= PAGE_SIZE) 2167 new_data = napi_alloc_frag(ring->frag_size); 2168 else 2169 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2170 2171 if (unlikely(!new_data)) { 2172 netdev->stats.rx_dropped++; 2173 goto release_desc; 2174 } 2175 2176 dma_addr = dma_map_single(eth->dma_dev, 2177 new_data + NET_SKB_PAD + eth->ip_align, 2178 ring->buf_size, DMA_FROM_DEVICE); 2179 if (unlikely(dma_mapping_error(eth->dma_dev, 2180 dma_addr))) { 2181 skb_free_frag(new_data); 2182 netdev->stats.rx_dropped++; 2183 goto release_desc; 2184 } 2185 2186 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2187 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2); 2188 2189 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), 2190 ring->buf_size, DMA_FROM_DEVICE); 2191 2192 skb = build_skb(data, ring->frag_size); 2193 if (unlikely(!skb)) { 2194 netdev->stats.rx_dropped++; 2195 skb_free_frag(data); 2196 goto skip_rx; 2197 } 2198 2199 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2200 skb_put(skb, pktlen); 2201 } 2202 2203 skb->dev = netdev; 2204 bytes += skb->len; 2205 2206 if (mtk_is_netsys_v3_or_greater(eth)) { 2207 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2208 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2209 if (hash != MTK_RXD5_FOE_ENTRY) 2210 skb_set_hash(skb, jhash_1word(hash, 0), 2211 PKT_HASH_TYPE_L4); 2212 rxdcsum = &trxd.rxd3; 2213 } else { 2214 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2215 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2216 if (hash != MTK_RXD4_FOE_ENTRY) 2217 skb_set_hash(skb, jhash_1word(hash, 0), 2218 PKT_HASH_TYPE_L4); 2219 rxdcsum = &trxd.rxd4; 2220 } 2221 2222 if (*rxdcsum & eth->soc->rx.dma_l4_valid) 2223 skb->ip_summed = CHECKSUM_UNNECESSARY; 2224 else 2225 skb_checksum_none_assert(skb); 2226 skb->protocol = eth_type_trans(skb, netdev); 2227 2228 /* When using VLAN untagging in combination with DSA, the 2229 * hardware treats the MTK special tag as a VLAN and untags it. 2230 */ 2231 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && 2232 netdev_uses_dsa(netdev)) { 2233 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 2234 2235 if (port < ARRAY_SIZE(eth->dsa_meta) && 2236 eth->dsa_meta[port]) 2237 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2238 } 2239 2240 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2241 mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash); 2242 2243 skb_record_rx_queue(skb, 0); 2244 napi_gro_receive(napi, skb); 2245 2246 skip_rx: 2247 ring->data[idx] = new_data; 2248 rxd->rxd1 = (unsigned int)dma_addr; 2249 release_desc: 2250 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2251 rxd->rxd2 = RX_DMA_LSO; 2252 else 2253 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2254 2255 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA) && 2256 likely(dma_addr != DMA_MAPPING_ERROR)) 2257 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2258 2259 ring->calc_idx = idx; 2260 done++; 2261 } 2262 2263 rx_done: 2264 if (done) { 2265 /* make sure that all changes to the dma ring are flushed before 2266 * we continue 2267 */ 2268 wmb(); 2269 mtk_update_rx_cpu_idx(eth); 2270 } 2271 2272 eth->rx_packets += done; 2273 eth->rx_bytes += bytes; 2274 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2275 &dim_sample); 2276 net_dim(ð->rx_dim, &dim_sample); 2277 2278 if (xdp_flush) 2279 xdp_do_flush(); 2280 2281 return done; 2282 } 2283 2284 struct mtk_poll_state { 2285 struct netdev_queue *txq; 2286 unsigned int total; 2287 unsigned int done; 2288 unsigned int bytes; 2289 }; 2290 2291 static void 2292 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2293 struct sk_buff *skb) 2294 { 2295 struct netdev_queue *txq; 2296 struct net_device *dev; 2297 unsigned int bytes = skb->len; 2298 2299 state->total++; 2300 eth->tx_packets++; 2301 eth->tx_bytes += bytes; 2302 2303 dev = eth->netdev[mac]; 2304 if (!dev) 2305 return; 2306 2307 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2308 if (state->txq == txq) { 2309 state->done++; 2310 state->bytes += bytes; 2311 return; 2312 } 2313 2314 if (state->txq) 2315 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2316 2317 state->txq = txq; 2318 state->done = 1; 2319 state->bytes = bytes; 2320 } 2321 2322 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2323 struct mtk_poll_state *state) 2324 { 2325 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2326 struct mtk_tx_ring *ring = ð->tx_ring; 2327 struct mtk_tx_buf *tx_buf; 2328 struct xdp_frame_bulk bq; 2329 struct mtk_tx_dma *desc; 2330 u32 cpu, dma; 2331 2332 cpu = ring->last_free_ptr; 2333 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2334 2335 desc = mtk_qdma_phys_to_virt(ring, cpu); 2336 xdp_frame_bulk_init(&bq); 2337 2338 while ((cpu != dma) && budget) { 2339 u32 next_cpu = desc->txd2; 2340 2341 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2342 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2343 break; 2344 2345 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2346 eth->soc->tx.desc_size); 2347 if (!tx_buf->data) 2348 break; 2349 2350 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2351 if (tx_buf->type == MTK_TYPE_SKB) 2352 mtk_poll_tx_done(eth, state, tx_buf->mac_id, 2353 tx_buf->data); 2354 2355 budget--; 2356 } 2357 mtk_tx_unmap(eth, tx_buf, &bq, true); 2358 2359 ring->last_free = desc; 2360 atomic_inc(&ring->free_count); 2361 2362 cpu = next_cpu; 2363 } 2364 xdp_flush_frame_bulk(&bq); 2365 2366 ring->last_free_ptr = cpu; 2367 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2368 2369 return budget; 2370 } 2371 2372 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2373 struct mtk_poll_state *state) 2374 { 2375 struct mtk_tx_ring *ring = ð->tx_ring; 2376 struct mtk_tx_buf *tx_buf; 2377 struct xdp_frame_bulk bq; 2378 struct mtk_tx_dma *desc; 2379 u32 cpu, dma; 2380 2381 cpu = ring->cpu_idx; 2382 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2383 xdp_frame_bulk_init(&bq); 2384 2385 while ((cpu != dma) && budget) { 2386 tx_buf = &ring->buf[cpu]; 2387 if (!tx_buf->data) 2388 break; 2389 2390 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2391 if (tx_buf->type == MTK_TYPE_SKB) 2392 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2393 budget--; 2394 } 2395 mtk_tx_unmap(eth, tx_buf, &bq, true); 2396 2397 desc = ring->dma + cpu * eth->soc->tx.desc_size; 2398 ring->last_free = desc; 2399 atomic_inc(&ring->free_count); 2400 2401 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2402 } 2403 xdp_flush_frame_bulk(&bq); 2404 2405 ring->cpu_idx = cpu; 2406 2407 return budget; 2408 } 2409 2410 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2411 { 2412 struct mtk_tx_ring *ring = ð->tx_ring; 2413 struct dim_sample dim_sample = {}; 2414 struct mtk_poll_state state = {}; 2415 2416 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2417 budget = mtk_poll_tx_qdma(eth, budget, &state); 2418 else 2419 budget = mtk_poll_tx_pdma(eth, budget, &state); 2420 2421 if (state.txq) 2422 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2423 2424 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2425 &dim_sample); 2426 net_dim(ð->tx_dim, &dim_sample); 2427 2428 if (mtk_queue_stopped(eth) && 2429 (atomic_read(&ring->free_count) > ring->thresh)) 2430 mtk_wake_queue(eth); 2431 2432 return state.total; 2433 } 2434 2435 static void mtk_handle_status_irq(struct mtk_eth *eth) 2436 { 2437 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2438 2439 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2440 mtk_stats_update(eth); 2441 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2442 MTK_INT_STATUS2); 2443 } 2444 } 2445 2446 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2447 { 2448 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2449 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2450 int tx_done = 0; 2451 2452 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2453 mtk_handle_status_irq(eth); 2454 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2455 tx_done = mtk_poll_tx(eth, budget); 2456 2457 if (unlikely(netif_msg_intr(eth))) { 2458 dev_info(eth->dev, 2459 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2460 mtk_r32(eth, reg_map->tx_irq_status), 2461 mtk_r32(eth, reg_map->tx_irq_mask)); 2462 } 2463 2464 if (tx_done == budget) 2465 return budget; 2466 2467 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2468 return budget; 2469 2470 if (napi_complete_done(napi, tx_done)) 2471 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2472 2473 return tx_done; 2474 } 2475 2476 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2477 { 2478 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2479 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2480 int rx_done_total = 0; 2481 2482 mtk_handle_status_irq(eth); 2483 2484 do { 2485 int rx_done; 2486 2487 mtk_w32(eth, eth->soc->rx.irq_done_mask, 2488 reg_map->pdma.irq_status); 2489 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2490 rx_done_total += rx_done; 2491 2492 if (unlikely(netif_msg_intr(eth))) { 2493 dev_info(eth->dev, 2494 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2495 mtk_r32(eth, reg_map->pdma.irq_status), 2496 mtk_r32(eth, reg_map->pdma.irq_mask)); 2497 } 2498 2499 if (rx_done_total == budget) 2500 return budget; 2501 2502 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2503 eth->soc->rx.irq_done_mask); 2504 2505 if (napi_complete_done(napi, rx_done_total)) 2506 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); 2507 2508 return rx_done_total; 2509 } 2510 2511 static int mtk_tx_alloc(struct mtk_eth *eth) 2512 { 2513 const struct mtk_soc_data *soc = eth->soc; 2514 struct mtk_tx_ring *ring = ð->tx_ring; 2515 int i, sz = soc->tx.desc_size; 2516 struct mtk_tx_dma_v2 *txd; 2517 int ring_size; 2518 u32 ofs, val; 2519 2520 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2521 ring_size = MTK_QDMA_RING_SIZE; 2522 else 2523 ring_size = soc->tx.dma_size; 2524 2525 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2526 GFP_KERNEL); 2527 if (!ring->buf) 2528 goto no_tx_mem; 2529 2530 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { 2531 ring->dma = eth->sram_base + soc->tx.fq_dma_size * sz; 2532 ring->phys = eth->phy_scratch_ring + soc->tx.fq_dma_size * (dma_addr_t)sz; 2533 } else { 2534 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2535 &ring->phys, GFP_KERNEL); 2536 } 2537 2538 if (!ring->dma) 2539 goto no_tx_mem; 2540 2541 for (i = 0; i < ring_size; i++) { 2542 int next = (i + 1) % ring_size; 2543 u32 next_ptr = ring->phys + next * sz; 2544 2545 txd = ring->dma + i * sz; 2546 txd->txd2 = next_ptr; 2547 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2548 txd->txd4 = 0; 2549 if (mtk_is_netsys_v2_or_greater(eth)) { 2550 txd->txd5 = 0; 2551 txd->txd6 = 0; 2552 txd->txd7 = 0; 2553 txd->txd8 = 0; 2554 } 2555 } 2556 2557 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2558 * only as the framework. The real HW descriptors are the PDMA 2559 * descriptors in ring->dma_pdma. 2560 */ 2561 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2562 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2563 &ring->phys_pdma, GFP_KERNEL); 2564 if (!ring->dma_pdma) 2565 goto no_tx_mem; 2566 2567 for (i = 0; i < ring_size; i++) { 2568 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2569 ring->dma_pdma[i].txd4 = 0; 2570 } 2571 } 2572 2573 ring->dma_size = ring_size; 2574 atomic_set(&ring->free_count, ring_size - 2); 2575 ring->next_free = ring->dma; 2576 ring->last_free = (void *)txd; 2577 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2578 ring->thresh = MAX_SKB_FRAGS; 2579 2580 /* make sure that all changes to the dma ring are flushed before we 2581 * continue 2582 */ 2583 wmb(); 2584 2585 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2586 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2587 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2588 mtk_w32(eth, 2589 ring->phys + ((ring_size - 1) * sz), 2590 soc->reg_map->qdma.crx_ptr); 2591 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2592 2593 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2594 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2595 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2596 2597 val = MTK_QTX_SCH_MIN_RATE_EN | 2598 /* minimum: 10 Mbps */ 2599 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2600 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2601 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2602 if (mtk_is_netsys_v1(eth)) 2603 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2604 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2605 ofs += MTK_QTX_OFFSET; 2606 } 2607 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2608 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2609 if (mtk_is_netsys_v2_or_greater(eth)) 2610 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2611 } else { 2612 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2613 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2614 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2615 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2616 } 2617 2618 return 0; 2619 2620 no_tx_mem: 2621 return -ENOMEM; 2622 } 2623 2624 static void mtk_tx_clean(struct mtk_eth *eth) 2625 { 2626 const struct mtk_soc_data *soc = eth->soc; 2627 struct mtk_tx_ring *ring = ð->tx_ring; 2628 int i; 2629 2630 if (ring->buf) { 2631 for (i = 0; i < ring->dma_size; i++) 2632 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2633 kfree(ring->buf); 2634 ring->buf = NULL; 2635 } 2636 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { 2637 dma_free_coherent(eth->dma_dev, 2638 ring->dma_size * soc->tx.desc_size, 2639 ring->dma, ring->phys); 2640 ring->dma = NULL; 2641 } 2642 2643 if (ring->dma_pdma) { 2644 dma_free_coherent(eth->dma_dev, 2645 ring->dma_size * soc->tx.desc_size, 2646 ring->dma_pdma, ring->phys_pdma); 2647 ring->dma_pdma = NULL; 2648 } 2649 } 2650 2651 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2652 { 2653 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2654 const struct mtk_soc_data *soc = eth->soc; 2655 struct mtk_rx_ring *ring; 2656 int rx_data_len, rx_dma_size, tx_ring_size; 2657 int i; 2658 2659 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2660 tx_ring_size = MTK_QDMA_RING_SIZE; 2661 else 2662 tx_ring_size = soc->tx.dma_size; 2663 2664 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2665 if (ring_no) 2666 return -EINVAL; 2667 ring = ð->rx_ring_qdma; 2668 } else { 2669 ring = ð->rx_ring[ring_no]; 2670 } 2671 2672 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2673 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2674 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2675 } else { 2676 rx_data_len = ETH_DATA_LEN; 2677 rx_dma_size = soc->rx.dma_size; 2678 } 2679 2680 ring->frag_size = mtk_max_frag_size(rx_data_len); 2681 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2682 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2683 GFP_KERNEL); 2684 if (!ring->data) 2685 return -ENOMEM; 2686 2687 if (mtk_page_pool_enabled(eth)) { 2688 struct page_pool *pp; 2689 2690 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2691 rx_dma_size); 2692 if (IS_ERR(pp)) 2693 return PTR_ERR(pp); 2694 2695 ring->page_pool = pp; 2696 } 2697 2698 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || 2699 rx_flag != MTK_RX_FLAGS_NORMAL) { 2700 ring->dma = dma_alloc_coherent(eth->dma_dev, 2701 rx_dma_size * eth->soc->rx.desc_size, 2702 &ring->phys, GFP_KERNEL); 2703 } else { 2704 struct mtk_tx_ring *tx_ring = ð->tx_ring; 2705 2706 ring->dma = tx_ring->dma + tx_ring_size * 2707 eth->soc->tx.desc_size * (ring_no + 1); 2708 ring->phys = tx_ring->phys + tx_ring_size * 2709 eth->soc->tx.desc_size * (ring_no + 1); 2710 } 2711 2712 if (!ring->dma) 2713 return -ENOMEM; 2714 2715 for (i = 0; i < rx_dma_size; i++) { 2716 struct mtk_rx_dma_v2 *rxd; 2717 dma_addr_t dma_addr; 2718 void *data; 2719 2720 rxd = ring->dma + i * eth->soc->rx.desc_size; 2721 if (ring->page_pool) { 2722 data = mtk_page_pool_get_buff(ring->page_pool, 2723 &dma_addr, GFP_KERNEL); 2724 if (!data) 2725 return -ENOMEM; 2726 } else { 2727 if (ring->frag_size <= PAGE_SIZE) 2728 data = netdev_alloc_frag(ring->frag_size); 2729 else 2730 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2731 2732 if (!data) 2733 return -ENOMEM; 2734 2735 dma_addr = dma_map_single(eth->dma_dev, 2736 data + NET_SKB_PAD + eth->ip_align, 2737 ring->buf_size, DMA_FROM_DEVICE); 2738 if (unlikely(dma_mapping_error(eth->dma_dev, 2739 dma_addr))) { 2740 skb_free_frag(data); 2741 return -ENOMEM; 2742 } 2743 } 2744 rxd->rxd1 = (unsigned int)dma_addr; 2745 ring->data[i] = data; 2746 2747 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2748 rxd->rxd2 = RX_DMA_LSO; 2749 else 2750 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2751 2752 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2753 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2754 2755 rxd->rxd3 = 0; 2756 rxd->rxd4 = 0; 2757 if (mtk_is_netsys_v3_or_greater(eth)) { 2758 rxd->rxd5 = 0; 2759 rxd->rxd6 = 0; 2760 rxd->rxd7 = 0; 2761 rxd->rxd8 = 0; 2762 } 2763 } 2764 2765 ring->dma_size = rx_dma_size; 2766 ring->calc_idx_update = false; 2767 ring->calc_idx = rx_dma_size - 1; 2768 if (rx_flag == MTK_RX_FLAGS_QDMA) 2769 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2770 ring_no * MTK_QRX_OFFSET; 2771 else 2772 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2773 ring_no * MTK_QRX_OFFSET; 2774 /* make sure that all changes to the dma ring are flushed before we 2775 * continue 2776 */ 2777 wmb(); 2778 2779 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2780 mtk_w32(eth, ring->phys, 2781 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2782 mtk_w32(eth, rx_dma_size, 2783 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2784 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2785 reg_map->qdma.rst_idx); 2786 } else { 2787 mtk_w32(eth, ring->phys, 2788 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2789 mtk_w32(eth, rx_dma_size, 2790 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2791 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2792 reg_map->pdma.rst_idx); 2793 } 2794 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2795 2796 return 0; 2797 } 2798 2799 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) 2800 { 2801 u64 addr64 = 0; 2802 int i; 2803 2804 if (ring->data && ring->dma) { 2805 for (i = 0; i < ring->dma_size; i++) { 2806 struct mtk_rx_dma *rxd; 2807 2808 if (!ring->data[i]) 2809 continue; 2810 2811 rxd = ring->dma + i * eth->soc->rx.desc_size; 2812 if (!rxd->rxd1) 2813 continue; 2814 2815 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2816 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); 2817 2818 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), 2819 ring->buf_size, DMA_FROM_DEVICE); 2820 mtk_rx_put_buff(ring, ring->data[i], false); 2821 } 2822 kfree(ring->data); 2823 ring->data = NULL; 2824 } 2825 2826 if (!in_sram && ring->dma) { 2827 dma_free_coherent(eth->dma_dev, 2828 ring->dma_size * eth->soc->rx.desc_size, 2829 ring->dma, ring->phys); 2830 ring->dma = NULL; 2831 } 2832 2833 if (ring->page_pool) { 2834 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2835 xdp_rxq_info_unreg(&ring->xdp_q); 2836 page_pool_destroy(ring->page_pool); 2837 ring->page_pool = NULL; 2838 } 2839 } 2840 2841 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2842 { 2843 int i; 2844 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2845 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2846 2847 /* set LRO rings to auto-learn modes */ 2848 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2849 2850 /* validate LRO ring */ 2851 ring_ctrl_dw2 |= MTK_RING_VLD; 2852 2853 /* set AGE timer (unit: 20us) */ 2854 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2855 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2856 2857 /* set max AGG timer (unit: 20us) */ 2858 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2859 2860 /* set max LRO AGG count */ 2861 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2862 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2863 2864 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2865 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2866 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2867 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2868 } 2869 2870 /* IPv4 checksum update enable */ 2871 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2872 2873 /* switch priority comparison to packet count mode */ 2874 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2875 2876 /* bandwidth threshold setting */ 2877 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2878 2879 /* auto-learn score delta setting */ 2880 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2881 2882 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2883 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2884 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2885 2886 /* set HW LRO mode & the max aggregation count for rx packets */ 2887 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2888 2889 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2890 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2891 2892 /* enable HW LRO */ 2893 lro_ctrl_dw0 |= MTK_LRO_EN; 2894 2895 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2896 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2897 2898 return 0; 2899 } 2900 2901 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2902 { 2903 int i; 2904 u32 val; 2905 2906 /* relinquish lro rings, flush aggregated packets */ 2907 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2908 2909 /* wait for relinquishments done */ 2910 for (i = 0; i < 10; i++) { 2911 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2912 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2913 msleep(20); 2914 continue; 2915 } 2916 break; 2917 } 2918 2919 /* invalidate lro rings */ 2920 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2921 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2922 2923 /* disable HW LRO */ 2924 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2925 } 2926 2927 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2928 { 2929 u32 reg_val; 2930 2931 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2932 2933 /* invalidate the IP setting */ 2934 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2935 2936 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2937 2938 /* validate the IP setting */ 2939 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2940 } 2941 2942 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2943 { 2944 u32 reg_val; 2945 2946 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2947 2948 /* invalidate the IP setting */ 2949 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2950 2951 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2952 } 2953 2954 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2955 { 2956 int cnt = 0; 2957 int i; 2958 2959 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2960 if (mac->hwlro_ip[i]) 2961 cnt++; 2962 } 2963 2964 return cnt; 2965 } 2966 2967 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2968 struct ethtool_rxnfc *cmd) 2969 { 2970 struct ethtool_rx_flow_spec *fsp = 2971 (struct ethtool_rx_flow_spec *)&cmd->fs; 2972 struct mtk_mac *mac = netdev_priv(dev); 2973 struct mtk_eth *eth = mac->hw; 2974 int hwlro_idx; 2975 2976 if ((fsp->flow_type != TCP_V4_FLOW) || 2977 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2978 (fsp->location > 1)) 2979 return -EINVAL; 2980 2981 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2982 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2983 2984 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2985 2986 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2987 2988 return 0; 2989 } 2990 2991 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2992 struct ethtool_rxnfc *cmd) 2993 { 2994 struct ethtool_rx_flow_spec *fsp = 2995 (struct ethtool_rx_flow_spec *)&cmd->fs; 2996 struct mtk_mac *mac = netdev_priv(dev); 2997 struct mtk_eth *eth = mac->hw; 2998 int hwlro_idx; 2999 3000 if (fsp->location > 1) 3001 return -EINVAL; 3002 3003 mac->hwlro_ip[fsp->location] = 0; 3004 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 3005 3006 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3007 3008 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 3009 3010 return 0; 3011 } 3012 3013 static void mtk_hwlro_netdev_disable(struct net_device *dev) 3014 { 3015 struct mtk_mac *mac = netdev_priv(dev); 3016 struct mtk_eth *eth = mac->hw; 3017 int i, hwlro_idx; 3018 3019 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 3020 mac->hwlro_ip[i] = 0; 3021 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 3022 3023 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 3024 } 3025 3026 mac->hwlro_ip_cnt = 0; 3027 } 3028 3029 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 3030 struct ethtool_rxnfc *cmd) 3031 { 3032 struct mtk_mac *mac = netdev_priv(dev); 3033 struct ethtool_rx_flow_spec *fsp = 3034 (struct ethtool_rx_flow_spec *)&cmd->fs; 3035 3036 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 3037 return -EINVAL; 3038 3039 /* only tcp dst ipv4 is meaningful, others are meaningless */ 3040 fsp->flow_type = TCP_V4_FLOW; 3041 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 3042 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 3043 3044 fsp->h_u.tcp_ip4_spec.ip4src = 0; 3045 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 3046 fsp->h_u.tcp_ip4_spec.psrc = 0; 3047 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 3048 fsp->h_u.tcp_ip4_spec.pdst = 0; 3049 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 3050 fsp->h_u.tcp_ip4_spec.tos = 0; 3051 fsp->m_u.tcp_ip4_spec.tos = 0xff; 3052 3053 return 0; 3054 } 3055 3056 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 3057 struct ethtool_rxnfc *cmd, 3058 u32 *rule_locs) 3059 { 3060 struct mtk_mac *mac = netdev_priv(dev); 3061 int cnt = 0; 3062 int i; 3063 3064 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 3065 if (cnt == cmd->rule_cnt) 3066 return -EMSGSIZE; 3067 3068 if (mac->hwlro_ip[i]) { 3069 rule_locs[cnt] = i; 3070 cnt++; 3071 } 3072 } 3073 3074 cmd->rule_cnt = cnt; 3075 3076 return 0; 3077 } 3078 3079 static netdev_features_t mtk_fix_features(struct net_device *dev, 3080 netdev_features_t features) 3081 { 3082 if (!(features & NETIF_F_LRO)) { 3083 struct mtk_mac *mac = netdev_priv(dev); 3084 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3085 3086 if (ip_cnt) { 3087 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 3088 3089 features |= NETIF_F_LRO; 3090 } 3091 } 3092 3093 return features; 3094 } 3095 3096 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 3097 { 3098 netdev_features_t diff = dev->features ^ features; 3099 3100 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 3101 mtk_hwlro_netdev_disable(dev); 3102 3103 return 0; 3104 } 3105 3106 /* wait for DMA to finish whatever it is doing before we start using it again */ 3107 static int mtk_dma_busy_wait(struct mtk_eth *eth) 3108 { 3109 unsigned int reg; 3110 int ret; 3111 u32 val; 3112 3113 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3114 reg = eth->soc->reg_map->qdma.glo_cfg; 3115 else 3116 reg = eth->soc->reg_map->pdma.glo_cfg; 3117 3118 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 3119 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 3120 5, MTK_DMA_BUSY_TIMEOUT_US); 3121 if (ret) 3122 dev_err(eth->dev, "DMA init timeout\n"); 3123 3124 return ret; 3125 } 3126 3127 static int mtk_dma_init(struct mtk_eth *eth) 3128 { 3129 int err; 3130 u32 i; 3131 3132 if (mtk_dma_busy_wait(eth)) 3133 return -EBUSY; 3134 3135 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3136 /* QDMA needs scratch memory for internal reordering of the 3137 * descriptors 3138 */ 3139 err = mtk_init_fq_dma(eth); 3140 if (err) 3141 return err; 3142 } 3143 3144 err = mtk_tx_alloc(eth); 3145 if (err) 3146 return err; 3147 3148 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3149 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 3150 if (err) 3151 return err; 3152 } 3153 3154 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 3155 if (err) 3156 return err; 3157 3158 if (eth->hwlro) { 3159 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 3160 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 3161 if (err) 3162 return err; 3163 } 3164 err = mtk_hwlro_rx_init(eth); 3165 if (err) 3166 return err; 3167 } 3168 3169 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3170 /* Enable random early drop and set drop threshold 3171 * automatically 3172 */ 3173 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 3174 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 3175 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 3176 } 3177 3178 return 0; 3179 } 3180 3181 static void mtk_dma_free(struct mtk_eth *eth) 3182 { 3183 const struct mtk_soc_data *soc = eth->soc; 3184 int i; 3185 3186 for (i = 0; i < MTK_MAX_DEVS; i++) 3187 if (eth->netdev[i]) 3188 netdev_reset_queue(eth->netdev[i]); 3189 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { 3190 dma_free_coherent(eth->dma_dev, 3191 MTK_QDMA_RING_SIZE * soc->tx.desc_size, 3192 eth->scratch_ring, eth->phy_scratch_ring); 3193 eth->scratch_ring = NULL; 3194 eth->phy_scratch_ring = 0; 3195 } 3196 mtk_tx_clean(eth); 3197 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); 3198 mtk_rx_clean(eth, ð->rx_ring_qdma, false); 3199 3200 if (eth->hwlro) { 3201 mtk_hwlro_rx_uninit(eth); 3202 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3203 mtk_rx_clean(eth, ð->rx_ring[i], false); 3204 } 3205 3206 for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) { 3207 kfree(eth->scratch_head[i]); 3208 eth->scratch_head[i] = NULL; 3209 } 3210 } 3211 3212 static bool mtk_hw_reset_check(struct mtk_eth *eth) 3213 { 3214 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3215 3216 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3217 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3218 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3219 } 3220 3221 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3222 { 3223 struct mtk_mac *mac = netdev_priv(dev); 3224 struct mtk_eth *eth = mac->hw; 3225 3226 if (test_bit(MTK_RESETTING, ð->state)) 3227 return; 3228 3229 if (!mtk_hw_reset_check(eth)) 3230 return; 3231 3232 eth->netdev[mac->id]->stats.tx_errors++; 3233 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3234 3235 schedule_work(ð->pending_work); 3236 } 3237 3238 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3239 { 3240 struct mtk_eth *eth = _eth; 3241 3242 eth->rx_events++; 3243 if (likely(napi_schedule_prep(ð->rx_napi))) { 3244 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3245 __napi_schedule(ð->rx_napi); 3246 } 3247 3248 return IRQ_HANDLED; 3249 } 3250 3251 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3252 { 3253 struct mtk_eth *eth = _eth; 3254 3255 eth->tx_events++; 3256 if (likely(napi_schedule_prep(ð->tx_napi))) { 3257 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3258 __napi_schedule(ð->tx_napi); 3259 } 3260 3261 return IRQ_HANDLED; 3262 } 3263 3264 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3265 { 3266 struct mtk_eth *eth = _eth; 3267 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3268 3269 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3270 eth->soc->rx.irq_done_mask) { 3271 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3272 eth->soc->rx.irq_done_mask) 3273 mtk_handle_irq_rx(irq, _eth); 3274 } 3275 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3276 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3277 mtk_handle_irq_tx(irq, _eth); 3278 } 3279 3280 return IRQ_HANDLED; 3281 } 3282 3283 #ifdef CONFIG_NET_POLL_CONTROLLER 3284 static void mtk_poll_controller(struct net_device *dev) 3285 { 3286 struct mtk_mac *mac = netdev_priv(dev); 3287 struct mtk_eth *eth = mac->hw; 3288 3289 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3290 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3291 mtk_handle_irq_rx(eth->irq[2], dev); 3292 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3293 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); 3294 } 3295 #endif 3296 3297 static int mtk_start_dma(struct mtk_eth *eth) 3298 { 3299 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3300 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3301 int err; 3302 3303 err = mtk_dma_init(eth); 3304 if (err) { 3305 mtk_dma_free(eth); 3306 return err; 3307 } 3308 3309 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3310 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3311 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3312 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3313 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3314 3315 if (mtk_is_netsys_v2_or_greater(eth)) 3316 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3317 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3318 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3319 else 3320 val |= MTK_RX_BT_32DWORDS; 3321 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3322 3323 mtk_w32(eth, 3324 MTK_RX_DMA_EN | rx_2b_offset | 3325 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3326 reg_map->pdma.glo_cfg); 3327 } else { 3328 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3329 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3330 reg_map->pdma.glo_cfg); 3331 } 3332 3333 return 0; 3334 } 3335 3336 static void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config) 3337 { 3338 u32 val; 3339 3340 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3341 return; 3342 3343 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(id)); 3344 3345 /* default setup the forward port to send frame to PDMA */ 3346 val &= ~0xffff; 3347 3348 /* Enable RX checksum */ 3349 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3350 3351 val |= config; 3352 3353 if (eth->netdev[id] && netdev_uses_dsa(eth->netdev[id])) 3354 val |= MTK_GDMA_SPECIAL_TAG; 3355 3356 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(id)); 3357 } 3358 3359 3360 static bool mtk_uses_dsa(struct net_device *dev) 3361 { 3362 #if IS_ENABLED(CONFIG_NET_DSA) 3363 return netdev_uses_dsa(dev) && 3364 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3365 #else 3366 return false; 3367 #endif 3368 } 3369 3370 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3371 { 3372 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3373 struct mtk_eth *eth = mac->hw; 3374 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3375 struct ethtool_link_ksettings s; 3376 struct net_device *ldev; 3377 struct list_head *iter; 3378 struct dsa_port *dp; 3379 3380 if (event != NETDEV_CHANGE) 3381 return NOTIFY_DONE; 3382 3383 netdev_for_each_lower_dev(dev, ldev, iter) { 3384 if (netdev_priv(ldev) == mac) 3385 goto found; 3386 } 3387 3388 return NOTIFY_DONE; 3389 3390 found: 3391 if (!dsa_user_dev_check(dev)) 3392 return NOTIFY_DONE; 3393 3394 if (__ethtool_get_link_ksettings(dev, &s)) 3395 return NOTIFY_DONE; 3396 3397 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3398 return NOTIFY_DONE; 3399 3400 dp = dsa_port_from_netdev(dev); 3401 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3402 return NOTIFY_DONE; 3403 3404 if (mac->speed > 0 && mac->speed <= s.base.speed) 3405 s.base.speed = 0; 3406 3407 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3408 3409 return NOTIFY_DONE; 3410 } 3411 3412 static int mtk_open(struct net_device *dev) 3413 { 3414 struct mtk_mac *mac = netdev_priv(dev); 3415 struct mtk_eth *eth = mac->hw; 3416 struct mtk_mac *target_mac; 3417 int i, err, ppe_num; 3418 3419 ppe_num = eth->soc->ppe_num; 3420 3421 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3422 if (err) { 3423 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3424 err); 3425 return err; 3426 } 3427 3428 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3429 if (!refcount_read(ð->dma_refcnt)) { 3430 const struct mtk_soc_data *soc = eth->soc; 3431 u32 gdm_config; 3432 int i; 3433 3434 err = mtk_start_dma(eth); 3435 if (err) { 3436 phylink_disconnect_phy(mac->phylink); 3437 return err; 3438 } 3439 3440 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3441 mtk_ppe_start(eth->ppe[i]); 3442 3443 for (i = 0; i < MTK_MAX_DEVS; i++) { 3444 if (!eth->netdev[i]) 3445 continue; 3446 3447 target_mac = netdev_priv(eth->netdev[i]); 3448 if (!soc->offload_version) { 3449 target_mac->ppe_idx = 0; 3450 gdm_config = MTK_GDMA_TO_PDMA; 3451 } else if (ppe_num >= 3 && target_mac->id == 2) { 3452 target_mac->ppe_idx = 2; 3453 gdm_config = soc->reg_map->gdma_to_ppe[2]; 3454 } else if (ppe_num >= 2 && target_mac->id == 1) { 3455 target_mac->ppe_idx = 1; 3456 gdm_config = soc->reg_map->gdma_to_ppe[1]; 3457 } else { 3458 target_mac->ppe_idx = 0; 3459 gdm_config = soc->reg_map->gdma_to_ppe[0]; 3460 } 3461 mtk_gdm_config(eth, target_mac->id, gdm_config); 3462 } 3463 /* Reset and enable PSE */ 3464 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3465 mtk_w32(eth, 0, MTK_RST_GL); 3466 3467 napi_enable(ð->tx_napi); 3468 napi_enable(ð->rx_napi); 3469 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3470 mtk_rx_irq_enable(eth, soc->rx.irq_done_mask); 3471 refcount_set(ð->dma_refcnt, 1); 3472 } else { 3473 refcount_inc(ð->dma_refcnt); 3474 } 3475 3476 phylink_start(mac->phylink); 3477 netif_tx_start_all_queues(dev); 3478 3479 if (mtk_is_netsys_v2_or_greater(eth)) 3480 return 0; 3481 3482 if (mtk_uses_dsa(dev) && !eth->prog) { 3483 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3484 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3485 3486 if (md_dst) 3487 continue; 3488 3489 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3490 GFP_KERNEL); 3491 if (!md_dst) 3492 return -ENOMEM; 3493 3494 md_dst->u.port_info.port_id = i; 3495 eth->dsa_meta[i] = md_dst; 3496 } 3497 } else { 3498 /* Hardware DSA untagging and VLAN RX offloading need to be 3499 * disabled if at least one MAC does not use DSA. 3500 */ 3501 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3502 3503 val &= ~MTK_CDMP_STAG_EN; 3504 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3505 3506 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); 3507 } 3508 3509 return 0; 3510 } 3511 3512 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3513 { 3514 u32 val; 3515 int i; 3516 3517 /* stop the dma engine */ 3518 spin_lock_bh(ð->page_lock); 3519 val = mtk_r32(eth, glo_cfg); 3520 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3521 glo_cfg); 3522 spin_unlock_bh(ð->page_lock); 3523 3524 /* wait for dma stop */ 3525 for (i = 0; i < 10; i++) { 3526 val = mtk_r32(eth, glo_cfg); 3527 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3528 msleep(20); 3529 continue; 3530 } 3531 break; 3532 } 3533 } 3534 3535 static int mtk_stop(struct net_device *dev) 3536 { 3537 struct mtk_mac *mac = netdev_priv(dev); 3538 struct mtk_eth *eth = mac->hw; 3539 int i; 3540 3541 phylink_stop(mac->phylink); 3542 3543 netif_tx_disable(dev); 3544 3545 phylink_disconnect_phy(mac->phylink); 3546 3547 /* only shutdown DMA if this is the last user */ 3548 if (!refcount_dec_and_test(ð->dma_refcnt)) 3549 return 0; 3550 3551 for (i = 0; i < MTK_MAX_DEVS; i++) 3552 mtk_gdm_config(eth, i, MTK_GDMA_DROP_ALL); 3553 3554 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3555 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3556 napi_disable(ð->tx_napi); 3557 napi_disable(ð->rx_napi); 3558 3559 cancel_work_sync(ð->rx_dim.work); 3560 cancel_work_sync(ð->tx_dim.work); 3561 3562 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3563 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3564 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3565 3566 mtk_dma_free(eth); 3567 3568 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3569 mtk_ppe_stop(eth->ppe[i]); 3570 3571 return 0; 3572 } 3573 3574 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3575 struct netlink_ext_ack *extack) 3576 { 3577 struct mtk_mac *mac = netdev_priv(dev); 3578 struct mtk_eth *eth = mac->hw; 3579 struct bpf_prog *old_prog; 3580 bool need_update; 3581 3582 if (eth->hwlro) { 3583 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3584 return -EOPNOTSUPP; 3585 } 3586 3587 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3588 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3589 return -EOPNOTSUPP; 3590 } 3591 3592 need_update = !!eth->prog != !!prog; 3593 if (netif_running(dev) && need_update) 3594 mtk_stop(dev); 3595 3596 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3597 if (old_prog) 3598 bpf_prog_put(old_prog); 3599 3600 if (netif_running(dev) && need_update) 3601 return mtk_open(dev); 3602 3603 return 0; 3604 } 3605 3606 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3607 { 3608 switch (xdp->command) { 3609 case XDP_SETUP_PROG: 3610 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3611 default: 3612 return -EINVAL; 3613 } 3614 } 3615 3616 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3617 { 3618 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3619 reset_bits, 3620 reset_bits); 3621 3622 usleep_range(1000, 1100); 3623 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3624 reset_bits, 3625 ~reset_bits); 3626 mdelay(10); 3627 } 3628 3629 static void mtk_clk_disable(struct mtk_eth *eth) 3630 { 3631 int clk; 3632 3633 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3634 clk_disable_unprepare(eth->clks[clk]); 3635 } 3636 3637 static int mtk_clk_enable(struct mtk_eth *eth) 3638 { 3639 int clk, ret; 3640 3641 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3642 ret = clk_prepare_enable(eth->clks[clk]); 3643 if (ret) 3644 goto err_disable_clks; 3645 } 3646 3647 return 0; 3648 3649 err_disable_clks: 3650 while (--clk >= 0) 3651 clk_disable_unprepare(eth->clks[clk]); 3652 3653 return ret; 3654 } 3655 3656 static void mtk_dim_rx(struct work_struct *work) 3657 { 3658 struct dim *dim = container_of(work, struct dim, work); 3659 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3660 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3661 struct dim_cq_moder cur_profile; 3662 u32 val, cur; 3663 3664 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3665 dim->profile_ix); 3666 spin_lock_bh(ð->dim_lock); 3667 3668 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3669 val &= MTK_PDMA_DELAY_TX_MASK; 3670 val |= MTK_PDMA_DELAY_RX_EN; 3671 3672 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3673 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3674 3675 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3676 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3677 3678 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3679 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3680 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3681 3682 spin_unlock_bh(ð->dim_lock); 3683 3684 dim->state = DIM_START_MEASURE; 3685 } 3686 3687 static void mtk_dim_tx(struct work_struct *work) 3688 { 3689 struct dim *dim = container_of(work, struct dim, work); 3690 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3691 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3692 struct dim_cq_moder cur_profile; 3693 u32 val, cur; 3694 3695 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3696 dim->profile_ix); 3697 spin_lock_bh(ð->dim_lock); 3698 3699 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3700 val &= MTK_PDMA_DELAY_RX_MASK; 3701 val |= MTK_PDMA_DELAY_TX_EN; 3702 3703 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3704 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3705 3706 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3707 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3708 3709 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3710 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3711 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3712 3713 spin_unlock_bh(ð->dim_lock); 3714 3715 dim->state = DIM_START_MEASURE; 3716 } 3717 3718 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3719 { 3720 struct mtk_eth *eth = mac->hw; 3721 u32 mcr_cur, mcr_new; 3722 3723 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3724 return; 3725 3726 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3727 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3728 3729 if (val <= 1518) 3730 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3731 else if (val <= 1536) 3732 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3733 else if (val <= 1552) 3734 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3735 else 3736 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3737 3738 if (mcr_new != mcr_cur) 3739 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3740 } 3741 3742 static void mtk_hw_reset(struct mtk_eth *eth) 3743 { 3744 u32 val; 3745 3746 if (mtk_is_netsys_v2_or_greater(eth)) 3747 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3748 3749 if (mtk_is_netsys_v3_or_greater(eth)) { 3750 val = RSTCTRL_PPE0_V3; 3751 3752 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3753 val |= RSTCTRL_PPE1_V3; 3754 3755 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3756 val |= RSTCTRL_PPE2; 3757 3758 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3759 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3760 val = RSTCTRL_PPE0_V2; 3761 3762 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3763 val |= RSTCTRL_PPE1; 3764 } else { 3765 val = RSTCTRL_PPE0; 3766 } 3767 3768 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3769 3770 if (mtk_is_netsys_v3_or_greater(eth)) 3771 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3772 0x6f8ff); 3773 else if (mtk_is_netsys_v2_or_greater(eth)) 3774 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3775 0x3ffffff); 3776 } 3777 3778 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3779 { 3780 u32 val; 3781 3782 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3783 return val; 3784 } 3785 3786 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3787 { 3788 u32 rst_mask, val; 3789 3790 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3791 RSTCTRL_FE); 3792 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3793 val & RSTCTRL_FE, 1, 1000)) { 3794 dev_err(eth->dev, "warm reset failed\n"); 3795 mtk_hw_reset(eth); 3796 return; 3797 } 3798 3799 if (mtk_is_netsys_v3_or_greater(eth)) { 3800 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3; 3801 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3802 rst_mask |= RSTCTRL_PPE1_V3; 3803 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3804 rst_mask |= RSTCTRL_PPE2; 3805 3806 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3807 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3808 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3809 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3810 rst_mask |= RSTCTRL_PPE1; 3811 } else { 3812 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3813 } 3814 3815 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3816 3817 udelay(1); 3818 val = mtk_hw_reset_read(eth); 3819 if (!(val & rst_mask)) 3820 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3821 val, rst_mask); 3822 3823 rst_mask |= RSTCTRL_FE; 3824 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3825 3826 udelay(1); 3827 val = mtk_hw_reset_read(eth); 3828 if (val & rst_mask) 3829 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3830 val, rst_mask); 3831 } 3832 3833 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3834 { 3835 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3836 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3837 bool oq_hang, cdm1_busy, adma_busy; 3838 bool wtx_busy, cdm_full, oq_free; 3839 u32 wdidx, val, gdm1_fc, gdm2_fc; 3840 bool qfsm_hang, qfwd_hang; 3841 bool ret = false; 3842 3843 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3844 return false; 3845 3846 /* WDMA sanity checks */ 3847 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3848 3849 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3850 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3851 3852 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3853 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3854 3855 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3856 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3857 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3858 3859 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3860 if (++eth->reset.wdma_hang_count > 2) { 3861 eth->reset.wdma_hang_count = 0; 3862 ret = true; 3863 } 3864 goto out; 3865 } 3866 3867 /* QDMA sanity checks */ 3868 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3869 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3870 3871 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3872 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3873 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3874 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3875 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3876 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3877 3878 if (qfsm_hang && qfwd_hang && 3879 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3880 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3881 if (++eth->reset.qdma_hang_count > 2) { 3882 eth->reset.qdma_hang_count = 0; 3883 ret = true; 3884 } 3885 goto out; 3886 } 3887 3888 /* ADMA sanity checks */ 3889 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3890 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3891 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3892 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3893 3894 if (oq_hang && cdm1_busy && adma_busy) { 3895 if (++eth->reset.adma_hang_count > 2) { 3896 eth->reset.adma_hang_count = 0; 3897 ret = true; 3898 } 3899 goto out; 3900 } 3901 3902 eth->reset.wdma_hang_count = 0; 3903 eth->reset.qdma_hang_count = 0; 3904 eth->reset.adma_hang_count = 0; 3905 out: 3906 eth->reset.wdidx = wdidx; 3907 3908 return ret; 3909 } 3910 3911 static void mtk_hw_reset_monitor_work(struct work_struct *work) 3912 { 3913 struct delayed_work *del_work = to_delayed_work(work); 3914 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3915 reset.monitor_work); 3916 3917 if (test_bit(MTK_RESETTING, ð->state)) 3918 goto out; 3919 3920 /* DMA stuck checks */ 3921 if (mtk_hw_check_dma_hang(eth)) 3922 schedule_work(ð->pending_work); 3923 3924 out: 3925 schedule_delayed_work(ð->reset.monitor_work, 3926 MTK_DMA_MONITOR_TIMEOUT); 3927 } 3928 3929 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3930 { 3931 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3932 ETHSYS_DMA_AG_MAP_PPE; 3933 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3934 int i, val, ret; 3935 3936 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3937 return 0; 3938 3939 if (!reset) { 3940 pm_runtime_enable(eth->dev); 3941 pm_runtime_get_sync(eth->dev); 3942 3943 ret = mtk_clk_enable(eth); 3944 if (ret) 3945 goto err_disable_pm; 3946 } 3947 3948 if (eth->ethsys) 3949 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3950 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3951 3952 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3953 ret = device_reset(eth->dev); 3954 if (ret) { 3955 dev_err(eth->dev, "MAC reset failed!\n"); 3956 goto err_disable_pm; 3957 } 3958 3959 /* set interrupt delays based on current Net DIM sample */ 3960 mtk_dim_rx(ð->rx_dim.work); 3961 mtk_dim_tx(ð->tx_dim.work); 3962 3963 /* disable delay and normal interrupt */ 3964 mtk_tx_irq_disable(eth, ~0); 3965 mtk_rx_irq_disable(eth, ~0); 3966 3967 return 0; 3968 } 3969 3970 msleep(100); 3971 3972 if (reset) 3973 mtk_hw_warm_reset(eth); 3974 else 3975 mtk_hw_reset(eth); 3976 3977 if (mtk_is_netsys_v3_or_greater(eth)) { 3978 /* Set FE to PDMAv2 if necessary */ 3979 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3980 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3981 } 3982 3983 if (eth->pctl) { 3984 /* Set GE2 driving and slew rate */ 3985 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3986 3987 /* set GE2 TDSEL */ 3988 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3989 3990 /* set GE2 TUNE */ 3991 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3992 } 3993 3994 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3995 * up with the more appropriate value when mtk_mac_config call is being 3996 * invoked. 3997 */ 3998 for (i = 0; i < MTK_MAX_DEVS; i++) { 3999 struct net_device *dev = eth->netdev[i]; 4000 4001 if (!dev) 4002 continue; 4003 4004 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 4005 mtk_set_mcr_max_rx(netdev_priv(dev), 4006 dev->mtu + MTK_RX_ETH_HLEN); 4007 } 4008 4009 /* Indicates CDM to parse the MTK special tag from CPU 4010 * which also is working out for untag packets. 4011 */ 4012 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 4013 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 4014 if (mtk_is_netsys_v1(eth)) { 4015 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 4016 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 4017 4018 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 4019 } 4020 4021 /* set interrupt delays based on current Net DIM sample */ 4022 mtk_dim_rx(ð->rx_dim.work); 4023 mtk_dim_tx(ð->tx_dim.work); 4024 4025 /* disable delay and normal interrupt */ 4026 mtk_tx_irq_disable(eth, ~0); 4027 mtk_rx_irq_disable(eth, ~0); 4028 4029 /* FE int grouping */ 4030 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 4031 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4); 4032 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 4033 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4); 4034 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 4035 4036 if (mtk_is_netsys_v3_or_greater(eth)) { 4037 /* PSE should not drop port1, port8 and port9 packets */ 4038 mtk_w32(eth, 0x00000302, PSE_DROP_CFG); 4039 4040 /* GDM and CDM Threshold */ 4041 mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); 4042 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); 4043 4044 /* Disable GDM1 RX CRC stripping */ 4045 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); 4046 4047 /* PSE GDM3 MIB counter has incorrect hw default values, 4048 * so the driver ought to read clear the values beforehand 4049 * in case ethtool retrieve wrong mib values. 4050 */ 4051 for (i = 0; i < 0x80; i += 0x4) 4052 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); 4053 } else if (!mtk_is_netsys_v1(eth)) { 4054 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 4055 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 4056 4057 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 4058 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 4059 4060 /* PSE Free Queue Flow Control */ 4061 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 4062 4063 /* PSE config input queue threshold */ 4064 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 4065 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 4066 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 4067 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 4068 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 4069 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 4070 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 4071 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 4072 4073 /* PSE config output queue threshold */ 4074 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 4075 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 4076 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 4077 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 4078 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 4079 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 4080 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 4081 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 4082 4083 /* GDM and CDM Threshold */ 4084 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 4085 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 4086 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 4087 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 4088 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 4089 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 4090 } 4091 4092 return 0; 4093 4094 err_disable_pm: 4095 if (!reset) { 4096 pm_runtime_put_sync(eth->dev); 4097 pm_runtime_disable(eth->dev); 4098 } 4099 4100 return ret; 4101 } 4102 4103 static int mtk_hw_deinit(struct mtk_eth *eth) 4104 { 4105 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 4106 return 0; 4107 4108 mtk_clk_disable(eth); 4109 4110 pm_runtime_put_sync(eth->dev); 4111 pm_runtime_disable(eth->dev); 4112 4113 return 0; 4114 } 4115 4116 static void mtk_uninit(struct net_device *dev) 4117 { 4118 struct mtk_mac *mac = netdev_priv(dev); 4119 struct mtk_eth *eth = mac->hw; 4120 4121 phylink_disconnect_phy(mac->phylink); 4122 mtk_tx_irq_disable(eth, ~0); 4123 mtk_rx_irq_disable(eth, ~0); 4124 } 4125 4126 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 4127 { 4128 int length = new_mtu + MTK_RX_ETH_HLEN; 4129 struct mtk_mac *mac = netdev_priv(dev); 4130 struct mtk_eth *eth = mac->hw; 4131 4132 if (rcu_access_pointer(eth->prog) && 4133 length > MTK_PP_MAX_BUF_SIZE) { 4134 netdev_err(dev, "Invalid MTU for XDP mode\n"); 4135 return -EINVAL; 4136 } 4137 4138 mtk_set_mcr_max_rx(mac, length); 4139 WRITE_ONCE(dev->mtu, new_mtu); 4140 4141 return 0; 4142 } 4143 4144 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4145 { 4146 struct mtk_mac *mac = netdev_priv(dev); 4147 4148 switch (cmd) { 4149 case SIOCGMIIPHY: 4150 case SIOCGMIIREG: 4151 case SIOCSMIIREG: 4152 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 4153 default: 4154 break; 4155 } 4156 4157 return -EOPNOTSUPP; 4158 } 4159 4160 static void mtk_prepare_for_reset(struct mtk_eth *eth) 4161 { 4162 u32 val; 4163 int i; 4164 4165 /* set FE PPE ports link down */ 4166 for (i = MTK_GMAC1_ID; 4167 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4168 i += 2) { 4169 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4170 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4171 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4172 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4173 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4174 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4175 } 4176 4177 /* adjust PPE configurations to prepare for reset */ 4178 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 4179 mtk_ppe_prepare_reset(eth->ppe[i]); 4180 4181 /* disable NETSYS interrupts */ 4182 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 4183 4184 /* force link down GMAC */ 4185 for (i = 0; i < 2; i++) { 4186 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 4187 mtk_w32(eth, val, MTK_MAC_MCR(i)); 4188 } 4189 } 4190 4191 static void mtk_pending_work(struct work_struct *work) 4192 { 4193 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 4194 unsigned long restart = 0; 4195 u32 val; 4196 int i; 4197 4198 rtnl_lock(); 4199 set_bit(MTK_RESETTING, ð->state); 4200 4201 mtk_prepare_for_reset(eth); 4202 mtk_wed_fe_reset(); 4203 /* Run again reset preliminary configuration in order to avoid any 4204 * possible race during FE reset since it can run releasing RTNL lock. 4205 */ 4206 mtk_prepare_for_reset(eth); 4207 4208 /* stop all devices to make sure that dma is properly shut down */ 4209 for (i = 0; i < MTK_MAX_DEVS; i++) { 4210 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 4211 continue; 4212 4213 mtk_stop(eth->netdev[i]); 4214 __set_bit(i, &restart); 4215 } 4216 4217 usleep_range(15000, 16000); 4218 4219 if (eth->dev->pins) 4220 pinctrl_select_state(eth->dev->pins->p, 4221 eth->dev->pins->default_state); 4222 mtk_hw_init(eth, true); 4223 4224 /* restart DMA and enable IRQs */ 4225 for (i = 0; i < MTK_MAX_DEVS; i++) { 4226 if (!eth->netdev[i] || !test_bit(i, &restart)) 4227 continue; 4228 4229 if (mtk_open(eth->netdev[i])) { 4230 netif_alert(eth, ifup, eth->netdev[i], 4231 "Driver up/down cycle failed\n"); 4232 dev_close(eth->netdev[i]); 4233 } 4234 } 4235 4236 /* set FE PPE ports link up */ 4237 for (i = MTK_GMAC1_ID; 4238 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4239 i += 2) { 4240 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4241 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4242 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4243 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4244 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4245 4246 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4247 } 4248 4249 clear_bit(MTK_RESETTING, ð->state); 4250 4251 mtk_wed_fe_reset_complete(); 4252 4253 rtnl_unlock(); 4254 } 4255 4256 static int mtk_free_dev(struct mtk_eth *eth) 4257 { 4258 int i; 4259 4260 for (i = 0; i < MTK_MAX_DEVS; i++) { 4261 if (!eth->netdev[i]) 4262 continue; 4263 free_netdev(eth->netdev[i]); 4264 } 4265 4266 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4267 if (!eth->dsa_meta[i]) 4268 break; 4269 metadata_dst_free(eth->dsa_meta[i]); 4270 } 4271 4272 return 0; 4273 } 4274 4275 static int mtk_unreg_dev(struct mtk_eth *eth) 4276 { 4277 int i; 4278 4279 for (i = 0; i < MTK_MAX_DEVS; i++) { 4280 struct mtk_mac *mac; 4281 if (!eth->netdev[i]) 4282 continue; 4283 mac = netdev_priv(eth->netdev[i]); 4284 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4285 unregister_netdevice_notifier(&mac->device_notifier); 4286 unregister_netdev(eth->netdev[i]); 4287 } 4288 4289 return 0; 4290 } 4291 4292 static void mtk_sgmii_destroy(struct mtk_eth *eth) 4293 { 4294 int i; 4295 4296 for (i = 0; i < MTK_MAX_DEVS; i++) 4297 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); 4298 } 4299 4300 static int mtk_cleanup(struct mtk_eth *eth) 4301 { 4302 mtk_sgmii_destroy(eth); 4303 mtk_unreg_dev(eth); 4304 mtk_free_dev(eth); 4305 cancel_work_sync(ð->pending_work); 4306 cancel_delayed_work_sync(ð->reset.monitor_work); 4307 4308 return 0; 4309 } 4310 4311 static int mtk_get_link_ksettings(struct net_device *ndev, 4312 struct ethtool_link_ksettings *cmd) 4313 { 4314 struct mtk_mac *mac = netdev_priv(ndev); 4315 4316 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4317 return -EBUSY; 4318 4319 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4320 } 4321 4322 static int mtk_set_link_ksettings(struct net_device *ndev, 4323 const struct ethtool_link_ksettings *cmd) 4324 { 4325 struct mtk_mac *mac = netdev_priv(ndev); 4326 4327 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4328 return -EBUSY; 4329 4330 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4331 } 4332 4333 static void mtk_get_drvinfo(struct net_device *dev, 4334 struct ethtool_drvinfo *info) 4335 { 4336 struct mtk_mac *mac = netdev_priv(dev); 4337 4338 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4339 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4340 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4341 } 4342 4343 static u32 mtk_get_msglevel(struct net_device *dev) 4344 { 4345 struct mtk_mac *mac = netdev_priv(dev); 4346 4347 return mac->hw->msg_enable; 4348 } 4349 4350 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4351 { 4352 struct mtk_mac *mac = netdev_priv(dev); 4353 4354 mac->hw->msg_enable = value; 4355 } 4356 4357 static int mtk_nway_reset(struct net_device *dev) 4358 { 4359 struct mtk_mac *mac = netdev_priv(dev); 4360 4361 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4362 return -EBUSY; 4363 4364 if (!mac->phylink) 4365 return -ENOTSUPP; 4366 4367 return phylink_ethtool_nway_reset(mac->phylink); 4368 } 4369 4370 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4371 { 4372 int i; 4373 4374 switch (stringset) { 4375 case ETH_SS_STATS: { 4376 struct mtk_mac *mac = netdev_priv(dev); 4377 4378 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4379 ethtool_puts(&data, mtk_ethtool_stats[i].str); 4380 if (mtk_page_pool_enabled(mac->hw)) 4381 page_pool_ethtool_stats_get_strings(data); 4382 break; 4383 } 4384 default: 4385 break; 4386 } 4387 } 4388 4389 static int mtk_get_sset_count(struct net_device *dev, int sset) 4390 { 4391 switch (sset) { 4392 case ETH_SS_STATS: { 4393 int count = ARRAY_SIZE(mtk_ethtool_stats); 4394 struct mtk_mac *mac = netdev_priv(dev); 4395 4396 if (mtk_page_pool_enabled(mac->hw)) 4397 count += page_pool_ethtool_stats_get_count(); 4398 return count; 4399 } 4400 default: 4401 return -EOPNOTSUPP; 4402 } 4403 } 4404 4405 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4406 { 4407 struct page_pool_stats stats = {}; 4408 int i; 4409 4410 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4411 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4412 4413 if (!ring->page_pool) 4414 continue; 4415 4416 page_pool_get_stats(ring->page_pool, &stats); 4417 } 4418 page_pool_ethtool_stats_get(data, &stats); 4419 } 4420 4421 static void mtk_get_ethtool_stats(struct net_device *dev, 4422 struct ethtool_stats *stats, u64 *data) 4423 { 4424 struct mtk_mac *mac = netdev_priv(dev); 4425 struct mtk_hw_stats *hwstats = mac->hw_stats; 4426 u64 *data_src, *data_dst; 4427 unsigned int start; 4428 int i; 4429 4430 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4431 return; 4432 4433 if (netif_running(dev) && netif_device_present(dev)) { 4434 if (spin_trylock_bh(&hwstats->stats_lock)) { 4435 mtk_stats_update_mac(mac); 4436 spin_unlock_bh(&hwstats->stats_lock); 4437 } 4438 } 4439 4440 data_src = (u64 *)hwstats; 4441 4442 do { 4443 data_dst = data; 4444 start = u64_stats_fetch_begin(&hwstats->syncp); 4445 4446 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4447 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4448 if (mtk_page_pool_enabled(mac->hw)) 4449 mtk_ethtool_pp_stats(mac->hw, data_dst); 4450 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4451 } 4452 4453 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4454 u32 *rule_locs) 4455 { 4456 int ret = -EOPNOTSUPP; 4457 4458 switch (cmd->cmd) { 4459 case ETHTOOL_GRXRINGS: 4460 if (dev->hw_features & NETIF_F_LRO) { 4461 cmd->data = MTK_MAX_RX_RING_NUM; 4462 ret = 0; 4463 } 4464 break; 4465 case ETHTOOL_GRXCLSRLCNT: 4466 if (dev->hw_features & NETIF_F_LRO) { 4467 struct mtk_mac *mac = netdev_priv(dev); 4468 4469 cmd->rule_cnt = mac->hwlro_ip_cnt; 4470 ret = 0; 4471 } 4472 break; 4473 case ETHTOOL_GRXCLSRULE: 4474 if (dev->hw_features & NETIF_F_LRO) 4475 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4476 break; 4477 case ETHTOOL_GRXCLSRLALL: 4478 if (dev->hw_features & NETIF_F_LRO) 4479 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4480 rule_locs); 4481 break; 4482 default: 4483 break; 4484 } 4485 4486 return ret; 4487 } 4488 4489 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4490 { 4491 int ret = -EOPNOTSUPP; 4492 4493 switch (cmd->cmd) { 4494 case ETHTOOL_SRXCLSRLINS: 4495 if (dev->hw_features & NETIF_F_LRO) 4496 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4497 break; 4498 case ETHTOOL_SRXCLSRLDEL: 4499 if (dev->hw_features & NETIF_F_LRO) 4500 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4501 break; 4502 default: 4503 break; 4504 } 4505 4506 return ret; 4507 } 4508 4509 static void mtk_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) 4510 { 4511 struct mtk_mac *mac = netdev_priv(dev); 4512 4513 phylink_ethtool_get_pauseparam(mac->phylink, pause); 4514 } 4515 4516 static int mtk_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) 4517 { 4518 struct mtk_mac *mac = netdev_priv(dev); 4519 4520 return phylink_ethtool_set_pauseparam(mac->phylink, pause); 4521 } 4522 4523 static int mtk_get_eee(struct net_device *dev, struct ethtool_keee *eee) 4524 { 4525 struct mtk_mac *mac = netdev_priv(dev); 4526 4527 return phylink_ethtool_get_eee(mac->phylink, eee); 4528 } 4529 4530 static int mtk_set_eee(struct net_device *dev, struct ethtool_keee *eee) 4531 { 4532 struct mtk_mac *mac = netdev_priv(dev); 4533 4534 return phylink_ethtool_set_eee(mac->phylink, eee); 4535 } 4536 4537 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4538 struct net_device *sb_dev) 4539 { 4540 struct mtk_mac *mac = netdev_priv(dev); 4541 unsigned int queue = 0; 4542 4543 if (netdev_uses_dsa(dev)) 4544 queue = skb_get_queue_mapping(skb) + 3; 4545 else 4546 queue = mac->id; 4547 4548 if (queue >= dev->num_tx_queues) 4549 queue = 0; 4550 4551 return queue; 4552 } 4553 4554 static const struct ethtool_ops mtk_ethtool_ops = { 4555 .get_link_ksettings = mtk_get_link_ksettings, 4556 .set_link_ksettings = mtk_set_link_ksettings, 4557 .get_drvinfo = mtk_get_drvinfo, 4558 .get_msglevel = mtk_get_msglevel, 4559 .set_msglevel = mtk_set_msglevel, 4560 .nway_reset = mtk_nway_reset, 4561 .get_link = ethtool_op_get_link, 4562 .get_strings = mtk_get_strings, 4563 .get_sset_count = mtk_get_sset_count, 4564 .get_ethtool_stats = mtk_get_ethtool_stats, 4565 .get_pauseparam = mtk_get_pauseparam, 4566 .set_pauseparam = mtk_set_pauseparam, 4567 .get_rxnfc = mtk_get_rxnfc, 4568 .set_rxnfc = mtk_set_rxnfc, 4569 .get_eee = mtk_get_eee, 4570 .set_eee = mtk_set_eee, 4571 }; 4572 4573 static const struct net_device_ops mtk_netdev_ops = { 4574 .ndo_uninit = mtk_uninit, 4575 .ndo_open = mtk_open, 4576 .ndo_stop = mtk_stop, 4577 .ndo_start_xmit = mtk_start_xmit, 4578 .ndo_set_mac_address = mtk_set_mac_address, 4579 .ndo_validate_addr = eth_validate_addr, 4580 .ndo_eth_ioctl = mtk_do_ioctl, 4581 .ndo_change_mtu = mtk_change_mtu, 4582 .ndo_tx_timeout = mtk_tx_timeout, 4583 .ndo_get_stats64 = mtk_get_stats64, 4584 .ndo_fix_features = mtk_fix_features, 4585 .ndo_set_features = mtk_set_features, 4586 #ifdef CONFIG_NET_POLL_CONTROLLER 4587 .ndo_poll_controller = mtk_poll_controller, 4588 #endif 4589 .ndo_setup_tc = mtk_eth_setup_tc, 4590 .ndo_bpf = mtk_xdp, 4591 .ndo_xdp_xmit = mtk_xdp_xmit, 4592 .ndo_select_queue = mtk_select_queue, 4593 }; 4594 4595 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4596 { 4597 const __be32 *_id = of_get_property(np, "reg", NULL); 4598 phy_interface_t phy_mode; 4599 struct phylink *phylink; 4600 struct mtk_mac *mac; 4601 int id, err; 4602 int txqs = 1; 4603 u32 val; 4604 4605 if (!_id) { 4606 dev_err(eth->dev, "missing mac id\n"); 4607 return -EINVAL; 4608 } 4609 4610 id = be32_to_cpup(_id); 4611 if (id >= MTK_MAX_DEVS) { 4612 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4613 return -EINVAL; 4614 } 4615 4616 if (eth->netdev[id]) { 4617 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4618 return -EINVAL; 4619 } 4620 4621 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4622 txqs = MTK_QDMA_NUM_QUEUES; 4623 4624 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4625 if (!eth->netdev[id]) { 4626 dev_err(eth->dev, "alloc_etherdev failed\n"); 4627 return -ENOMEM; 4628 } 4629 mac = netdev_priv(eth->netdev[id]); 4630 eth->mac[id] = mac; 4631 mac->id = id; 4632 mac->hw = eth; 4633 mac->of_node = np; 4634 4635 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); 4636 if (err == -EPROBE_DEFER) 4637 return err; 4638 4639 if (err) { 4640 /* If the mac address is invalid, use random mac address */ 4641 eth_hw_addr_random(eth->netdev[id]); 4642 dev_err(eth->dev, "generated random MAC address %pM\n", 4643 eth->netdev[id]->dev_addr); 4644 } 4645 4646 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4647 mac->hwlro_ip_cnt = 0; 4648 4649 mac->hw_stats = devm_kzalloc(eth->dev, 4650 sizeof(*mac->hw_stats), 4651 GFP_KERNEL); 4652 if (!mac->hw_stats) { 4653 dev_err(eth->dev, "failed to allocate counter memory\n"); 4654 err = -ENOMEM; 4655 goto free_netdev; 4656 } 4657 spin_lock_init(&mac->hw_stats->stats_lock); 4658 u64_stats_init(&mac->hw_stats->syncp); 4659 4660 if (mtk_is_netsys_v3_or_greater(eth)) 4661 mac->hw_stats->reg_offset = id * 0x80; 4662 else 4663 mac->hw_stats->reg_offset = id * 0x40; 4664 4665 /* phylink create */ 4666 err = of_get_phy_mode(np, &phy_mode); 4667 if (err) { 4668 dev_err(eth->dev, "incorrect phy-mode\n"); 4669 goto free_netdev; 4670 } 4671 4672 /* mac config is not set */ 4673 mac->interface = PHY_INTERFACE_MODE_NA; 4674 mac->speed = SPEED_UNKNOWN; 4675 4676 mac->phylink_config.dev = ð->netdev[id]->dev; 4677 mac->phylink_config.type = PHYLINK_NETDEV; 4678 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4679 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4680 mac->phylink_config.lpi_capabilities = MAC_100FD | MAC_1000FD | 4681 MAC_2500FD; 4682 mac->phylink_config.lpi_timer_default = 1000; 4683 4684 /* MT7623 gmac0 is now missing its speed-specific PLL configuration 4685 * in its .mac_config method (since state->speed is not valid there. 4686 * Disable support for MII, GMII and RGMII. 4687 */ 4688 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { 4689 __set_bit(PHY_INTERFACE_MODE_MII, 4690 mac->phylink_config.supported_interfaces); 4691 __set_bit(PHY_INTERFACE_MODE_GMII, 4692 mac->phylink_config.supported_interfaces); 4693 4694 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4695 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4696 } 4697 4698 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4699 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4700 mac->phylink_config.supported_interfaces); 4701 4702 /* TRGMII is not permitted on MT7621 if using DDR2 */ 4703 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 4704 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 4705 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 4706 if (val & SYSCFG_DRAM_TYPE_DDR2) 4707 __clear_bit(PHY_INTERFACE_MODE_TRGMII, 4708 mac->phylink_config.supported_interfaces); 4709 } 4710 4711 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4712 __set_bit(PHY_INTERFACE_MODE_SGMII, 4713 mac->phylink_config.supported_interfaces); 4714 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4715 mac->phylink_config.supported_interfaces); 4716 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4717 mac->phylink_config.supported_interfaces); 4718 } 4719 4720 if (mtk_is_netsys_v3_or_greater(mac->hw) && 4721 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && 4722 id == MTK_GMAC1_ID) { 4723 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 4724 MAC_SYM_PAUSE | 4725 MAC_10000FD; 4726 phy_interface_zero(mac->phylink_config.supported_interfaces); 4727 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 4728 mac->phylink_config.supported_interfaces); 4729 } 4730 4731 phylink = phylink_create(&mac->phylink_config, 4732 of_fwnode_handle(mac->of_node), 4733 phy_mode, &mtk_phylink_ops); 4734 if (IS_ERR(phylink)) { 4735 err = PTR_ERR(phylink); 4736 goto free_netdev; 4737 } 4738 4739 mac->phylink = phylink; 4740 4741 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4742 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4743 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4744 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4745 4746 eth->netdev[id]->hw_features = eth->soc->hw_features; 4747 if (eth->hwlro) 4748 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4749 4750 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4751 ~NETIF_F_HW_VLAN_CTAG_TX; 4752 eth->netdev[id]->features |= eth->soc->hw_features; 4753 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4754 4755 eth->netdev[id]->irq = eth->irq[0]; 4756 eth->netdev[id]->dev.of_node = np; 4757 4758 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4759 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4760 else 4761 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4762 4763 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4764 mac->device_notifier.notifier_call = mtk_device_event; 4765 register_netdevice_notifier(&mac->device_notifier); 4766 } 4767 4768 if (mtk_page_pool_enabled(eth)) 4769 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4770 NETDEV_XDP_ACT_REDIRECT | 4771 NETDEV_XDP_ACT_NDO_XMIT | 4772 NETDEV_XDP_ACT_NDO_XMIT_SG; 4773 4774 return 0; 4775 4776 free_netdev: 4777 free_netdev(eth->netdev[id]); 4778 return err; 4779 } 4780 4781 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4782 { 4783 struct net_device *dev, *tmp; 4784 LIST_HEAD(dev_list); 4785 int i; 4786 4787 rtnl_lock(); 4788 4789 for (i = 0; i < MTK_MAX_DEVS; i++) { 4790 dev = eth->netdev[i]; 4791 4792 if (!dev || !(dev->flags & IFF_UP)) 4793 continue; 4794 4795 list_add_tail(&dev->close_list, &dev_list); 4796 } 4797 4798 dev_close_many(&dev_list, false); 4799 4800 eth->dma_dev = dma_dev; 4801 4802 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4803 list_del_init(&dev->close_list); 4804 dev_open(dev, NULL); 4805 } 4806 4807 rtnl_unlock(); 4808 } 4809 4810 static int mtk_sgmii_init(struct mtk_eth *eth) 4811 { 4812 struct device_node *np; 4813 struct regmap *regmap; 4814 u32 flags; 4815 int i; 4816 4817 for (i = 0; i < MTK_MAX_DEVS; i++) { 4818 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); 4819 if (!np) 4820 break; 4821 4822 regmap = syscon_node_to_regmap(np); 4823 flags = 0; 4824 if (of_property_read_bool(np, "mediatek,pnswap")) 4825 flags |= MTK_SGMII_FLAG_PN_SWAP; 4826 4827 of_node_put(np); 4828 4829 if (IS_ERR(regmap)) 4830 return PTR_ERR(regmap); 4831 4832 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, 4833 eth->soc->ana_rgc3, 4834 flags); 4835 } 4836 4837 return 0; 4838 } 4839 4840 static int mtk_probe(struct platform_device *pdev) 4841 { 4842 struct resource *res = NULL, *res_sram; 4843 struct device_node *mac_np; 4844 struct mtk_eth *eth; 4845 int err, i; 4846 4847 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4848 if (!eth) 4849 return -ENOMEM; 4850 4851 eth->soc = of_device_get_match_data(&pdev->dev); 4852 4853 eth->dev = &pdev->dev; 4854 eth->dma_dev = &pdev->dev; 4855 eth->base = devm_platform_ioremap_resource(pdev, 0); 4856 if (IS_ERR(eth->base)) 4857 return PTR_ERR(eth->base); 4858 4859 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4860 eth->ip_align = NET_IP_ALIGN; 4861 4862 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4863 /* SRAM is actual memory and supports transparent access just like DRAM. 4864 * Hence we don't require __iomem being set and don't need to use accessor 4865 * functions to read from or write to SRAM. 4866 */ 4867 if (mtk_is_netsys_v3_or_greater(eth)) { 4868 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1); 4869 if (IS_ERR(eth->sram_base)) 4870 return PTR_ERR(eth->sram_base); 4871 } else { 4872 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; 4873 } 4874 } 4875 4876 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { 4877 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36)); 4878 if (!err) 4879 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 4880 4881 if (err) { 4882 dev_err(&pdev->dev, "Wrong DMA config\n"); 4883 return -EINVAL; 4884 } 4885 } 4886 4887 spin_lock_init(ð->page_lock); 4888 spin_lock_init(ð->tx_irq_lock); 4889 spin_lock_init(ð->rx_irq_lock); 4890 spin_lock_init(ð->dim_lock); 4891 4892 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4893 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4894 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4895 4896 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4897 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4898 4899 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4900 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4901 "mediatek,ethsys"); 4902 if (IS_ERR(eth->ethsys)) { 4903 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4904 return PTR_ERR(eth->ethsys); 4905 } 4906 } 4907 4908 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4909 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4910 "mediatek,infracfg"); 4911 if (IS_ERR(eth->infra)) { 4912 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4913 return PTR_ERR(eth->infra); 4914 } 4915 } 4916 4917 if (of_dma_is_coherent(pdev->dev.of_node)) { 4918 struct regmap *cci; 4919 4920 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4921 "cci-control-port"); 4922 /* enable CPU/bus coherency */ 4923 if (!IS_ERR(cci)) 4924 regmap_write(cci, 0, 3); 4925 } 4926 4927 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4928 err = mtk_sgmii_init(eth); 4929 4930 if (err) 4931 return err; 4932 } 4933 4934 if (eth->soc->required_pctl) { 4935 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4936 "mediatek,pctl"); 4937 if (IS_ERR(eth->pctl)) { 4938 dev_err(&pdev->dev, "no pctl regmap found\n"); 4939 err = PTR_ERR(eth->pctl); 4940 goto err_destroy_sgmii; 4941 } 4942 } 4943 4944 if (mtk_is_netsys_v2_or_greater(eth)) { 4945 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4946 if (!res) { 4947 err = -EINVAL; 4948 goto err_destroy_sgmii; 4949 } 4950 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4951 if (mtk_is_netsys_v3_or_greater(eth)) { 4952 res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1); 4953 if (!res_sram) { 4954 err = -EINVAL; 4955 goto err_destroy_sgmii; 4956 } 4957 eth->phy_scratch_ring = res_sram->start; 4958 } else { 4959 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; 4960 } 4961 } 4962 } 4963 4964 if (eth->soc->offload_version) { 4965 for (i = 0;; i++) { 4966 struct device_node *np; 4967 phys_addr_t wdma_phy; 4968 u32 wdma_base; 4969 4970 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4971 break; 4972 4973 np = of_parse_phandle(pdev->dev.of_node, 4974 "mediatek,wed", i); 4975 if (!np) 4976 break; 4977 4978 wdma_base = eth->soc->reg_map->wdma_base[i]; 4979 wdma_phy = res ? res->start + wdma_base : 0; 4980 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4981 wdma_phy, i); 4982 } 4983 } 4984 4985 for (i = 0; i < 3; i++) { 4986 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4987 eth->irq[i] = eth->irq[0]; 4988 else 4989 eth->irq[i] = platform_get_irq(pdev, i); 4990 if (eth->irq[i] < 0) { 4991 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4992 err = -ENXIO; 4993 goto err_wed_exit; 4994 } 4995 } 4996 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4997 eth->clks[i] = devm_clk_get(eth->dev, 4998 mtk_clks_source_name[i]); 4999 if (IS_ERR(eth->clks[i])) { 5000 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 5001 err = -EPROBE_DEFER; 5002 goto err_wed_exit; 5003 } 5004 if (eth->soc->required_clks & BIT(i)) { 5005 dev_err(&pdev->dev, "clock %s not found\n", 5006 mtk_clks_source_name[i]); 5007 err = -EINVAL; 5008 goto err_wed_exit; 5009 } 5010 eth->clks[i] = NULL; 5011 } 5012 } 5013 5014 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 5015 INIT_WORK(ð->pending_work, mtk_pending_work); 5016 5017 err = mtk_hw_init(eth, false); 5018 if (err) 5019 goto err_wed_exit; 5020 5021 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 5022 5023 for_each_child_of_node(pdev->dev.of_node, mac_np) { 5024 if (!of_device_is_compatible(mac_np, 5025 "mediatek,eth-mac")) 5026 continue; 5027 5028 if (!of_device_is_available(mac_np)) 5029 continue; 5030 5031 err = mtk_add_mac(eth, mac_np); 5032 if (err) { 5033 of_node_put(mac_np); 5034 goto err_deinit_hw; 5035 } 5036 } 5037 5038 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 5039 err = devm_request_irq(eth->dev, eth->irq[0], 5040 mtk_handle_irq, 0, 5041 dev_name(eth->dev), eth); 5042 } else { 5043 err = devm_request_irq(eth->dev, eth->irq[1], 5044 mtk_handle_irq_tx, 0, 5045 dev_name(eth->dev), eth); 5046 if (err) 5047 goto err_free_dev; 5048 5049 err = devm_request_irq(eth->dev, eth->irq[2], 5050 mtk_handle_irq_rx, 0, 5051 dev_name(eth->dev), eth); 5052 } 5053 if (err) 5054 goto err_free_dev; 5055 5056 /* No MT7628/88 support yet */ 5057 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 5058 err = mtk_mdio_init(eth); 5059 if (err) 5060 goto err_free_dev; 5061 } 5062 5063 if (eth->soc->offload_version) { 5064 u8 ppe_num = eth->soc->ppe_num; 5065 5066 ppe_num = min_t(u8, ARRAY_SIZE(eth->ppe), ppe_num); 5067 for (i = 0; i < ppe_num; i++) { 5068 u32 ppe_addr = eth->soc->reg_map->ppe_base; 5069 5070 ppe_addr += (i == 2 ? 0xc00 : i * 0x400); 5071 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); 5072 5073 if (!eth->ppe[i]) { 5074 err = -ENOMEM; 5075 goto err_deinit_ppe; 5076 } 5077 err = mtk_eth_offload_init(eth, i); 5078 5079 if (err) 5080 goto err_deinit_ppe; 5081 } 5082 } 5083 5084 for (i = 0; i < MTK_MAX_DEVS; i++) { 5085 if (!eth->netdev[i]) 5086 continue; 5087 5088 err = register_netdev(eth->netdev[i]); 5089 if (err) { 5090 dev_err(eth->dev, "error bringing up device\n"); 5091 goto err_deinit_ppe; 5092 } else 5093 netif_info(eth, probe, eth->netdev[i], 5094 "mediatek frame engine at 0x%08lx, irq %d\n", 5095 eth->netdev[i]->base_addr, eth->irq[0]); 5096 } 5097 5098 /* we run 2 devices on the same DMA ring so we need a dummy device 5099 * for NAPI to work 5100 */ 5101 eth->dummy_dev = alloc_netdev_dummy(0); 5102 if (!eth->dummy_dev) { 5103 err = -ENOMEM; 5104 dev_err(eth->dev, "failed to allocated dummy device\n"); 5105 goto err_unreg_netdev; 5106 } 5107 netif_napi_add(eth->dummy_dev, ð->tx_napi, mtk_napi_tx); 5108 netif_napi_add(eth->dummy_dev, ð->rx_napi, mtk_napi_rx); 5109 5110 platform_set_drvdata(pdev, eth); 5111 schedule_delayed_work(ð->reset.monitor_work, 5112 MTK_DMA_MONITOR_TIMEOUT); 5113 5114 return 0; 5115 5116 err_unreg_netdev: 5117 mtk_unreg_dev(eth); 5118 err_deinit_ppe: 5119 mtk_ppe_deinit(eth); 5120 mtk_mdio_cleanup(eth); 5121 err_free_dev: 5122 mtk_free_dev(eth); 5123 err_deinit_hw: 5124 mtk_hw_deinit(eth); 5125 err_wed_exit: 5126 mtk_wed_exit(); 5127 err_destroy_sgmii: 5128 mtk_sgmii_destroy(eth); 5129 5130 return err; 5131 } 5132 5133 static void mtk_remove(struct platform_device *pdev) 5134 { 5135 struct mtk_eth *eth = platform_get_drvdata(pdev); 5136 struct mtk_mac *mac; 5137 int i; 5138 5139 /* stop all devices to make sure that dma is properly shut down */ 5140 for (i = 0; i < MTK_MAX_DEVS; i++) { 5141 if (!eth->netdev[i]) 5142 continue; 5143 mtk_stop(eth->netdev[i]); 5144 mac = netdev_priv(eth->netdev[i]); 5145 phylink_disconnect_phy(mac->phylink); 5146 } 5147 5148 mtk_wed_exit(); 5149 mtk_hw_deinit(eth); 5150 5151 netif_napi_del(ð->tx_napi); 5152 netif_napi_del(ð->rx_napi); 5153 mtk_cleanup(eth); 5154 free_netdev(eth->dummy_dev); 5155 mtk_mdio_cleanup(eth); 5156 } 5157 5158 static const struct mtk_soc_data mt2701_data = { 5159 .reg_map = &mtk_reg_map, 5160 .caps = MT7623_CAPS | MTK_HWLRO, 5161 .hw_features = MTK_HW_FEATURES, 5162 .required_clks = MT7623_CLKS_BITMAP, 5163 .required_pctl = true, 5164 .version = 1, 5165 .tx = { 5166 .desc_size = sizeof(struct mtk_tx_dma), 5167 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5168 .dma_len_offset = 16, 5169 .dma_size = MTK_DMA_SIZE(2K), 5170 .fq_dma_size = MTK_DMA_SIZE(2K), 5171 }, 5172 .rx = { 5173 .desc_size = sizeof(struct mtk_rx_dma), 5174 .irq_done_mask = MTK_RX_DONE_INT, 5175 .dma_l4_valid = RX_DMA_L4_VALID, 5176 .dma_size = MTK_DMA_SIZE(2K), 5177 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5178 .dma_len_offset = 16, 5179 }, 5180 }; 5181 5182 static const struct mtk_soc_data mt7621_data = { 5183 .reg_map = &mtk_reg_map, 5184 .caps = MT7621_CAPS, 5185 .hw_features = MTK_HW_FEATURES, 5186 .required_clks = MT7621_CLKS_BITMAP, 5187 .required_pctl = false, 5188 .version = 1, 5189 .offload_version = 1, 5190 .ppe_num = 1, 5191 .hash_offset = 2, 5192 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5193 .tx = { 5194 .desc_size = sizeof(struct mtk_tx_dma), 5195 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5196 .dma_len_offset = 16, 5197 .dma_size = MTK_DMA_SIZE(2K), 5198 .fq_dma_size = MTK_DMA_SIZE(2K), 5199 }, 5200 .rx = { 5201 .desc_size = sizeof(struct mtk_rx_dma), 5202 .irq_done_mask = MTK_RX_DONE_INT, 5203 .dma_l4_valid = RX_DMA_L4_VALID, 5204 .dma_size = MTK_DMA_SIZE(2K), 5205 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5206 .dma_len_offset = 16, 5207 }, 5208 }; 5209 5210 static const struct mtk_soc_data mt7622_data = { 5211 .reg_map = &mtk_reg_map, 5212 .ana_rgc3 = 0x2028, 5213 .caps = MT7622_CAPS | MTK_HWLRO, 5214 .hw_features = MTK_HW_FEATURES, 5215 .required_clks = MT7622_CLKS_BITMAP, 5216 .required_pctl = false, 5217 .version = 1, 5218 .offload_version = 2, 5219 .ppe_num = 1, 5220 .hash_offset = 2, 5221 .has_accounting = true, 5222 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5223 .tx = { 5224 .desc_size = sizeof(struct mtk_tx_dma), 5225 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5226 .dma_len_offset = 16, 5227 .dma_size = MTK_DMA_SIZE(2K), 5228 .fq_dma_size = MTK_DMA_SIZE(2K), 5229 }, 5230 .rx = { 5231 .desc_size = sizeof(struct mtk_rx_dma), 5232 .irq_done_mask = MTK_RX_DONE_INT, 5233 .dma_l4_valid = RX_DMA_L4_VALID, 5234 .dma_size = MTK_DMA_SIZE(2K), 5235 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5236 .dma_len_offset = 16, 5237 }, 5238 }; 5239 5240 static const struct mtk_soc_data mt7623_data = { 5241 .reg_map = &mtk_reg_map, 5242 .caps = MT7623_CAPS | MTK_HWLRO, 5243 .hw_features = MTK_HW_FEATURES, 5244 .required_clks = MT7623_CLKS_BITMAP, 5245 .required_pctl = true, 5246 .version = 1, 5247 .offload_version = 1, 5248 .ppe_num = 1, 5249 .hash_offset = 2, 5250 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5251 .disable_pll_modes = true, 5252 .tx = { 5253 .desc_size = sizeof(struct mtk_tx_dma), 5254 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5255 .dma_len_offset = 16, 5256 .dma_size = MTK_DMA_SIZE(2K), 5257 .fq_dma_size = MTK_DMA_SIZE(2K), 5258 }, 5259 .rx = { 5260 .desc_size = sizeof(struct mtk_rx_dma), 5261 .irq_done_mask = MTK_RX_DONE_INT, 5262 .dma_l4_valid = RX_DMA_L4_VALID, 5263 .dma_size = MTK_DMA_SIZE(2K), 5264 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5265 .dma_len_offset = 16, 5266 }, 5267 }; 5268 5269 static const struct mtk_soc_data mt7629_data = { 5270 .reg_map = &mtk_reg_map, 5271 .ana_rgc3 = 0x128, 5272 .caps = MT7629_CAPS | MTK_HWLRO, 5273 .hw_features = MTK_HW_FEATURES, 5274 .required_clks = MT7629_CLKS_BITMAP, 5275 .required_pctl = false, 5276 .has_accounting = true, 5277 .version = 1, 5278 .tx = { 5279 .desc_size = sizeof(struct mtk_tx_dma), 5280 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5281 .dma_len_offset = 16, 5282 .dma_size = MTK_DMA_SIZE(2K), 5283 .fq_dma_size = MTK_DMA_SIZE(2K), 5284 }, 5285 .rx = { 5286 .desc_size = sizeof(struct mtk_rx_dma), 5287 .irq_done_mask = MTK_RX_DONE_INT, 5288 .dma_l4_valid = RX_DMA_L4_VALID, 5289 .dma_size = MTK_DMA_SIZE(2K), 5290 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5291 .dma_len_offset = 16, 5292 }, 5293 }; 5294 5295 static const struct mtk_soc_data mt7981_data = { 5296 .reg_map = &mt7986_reg_map, 5297 .ana_rgc3 = 0x128, 5298 .caps = MT7981_CAPS, 5299 .hw_features = MTK_HW_FEATURES, 5300 .required_clks = MT7981_CLKS_BITMAP, 5301 .required_pctl = false, 5302 .version = 2, 5303 .offload_version = 2, 5304 .ppe_num = 2, 5305 .hash_offset = 4, 5306 .has_accounting = true, 5307 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5308 .tx = { 5309 .desc_size = sizeof(struct mtk_tx_dma_v2), 5310 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5311 .dma_len_offset = 8, 5312 .dma_size = MTK_DMA_SIZE(2K), 5313 .fq_dma_size = MTK_DMA_SIZE(2K), 5314 }, 5315 .rx = { 5316 .desc_size = sizeof(struct mtk_rx_dma), 5317 .irq_done_mask = MTK_RX_DONE_INT, 5318 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5319 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5320 .dma_len_offset = 16, 5321 .dma_size = MTK_DMA_SIZE(2K), 5322 }, 5323 }; 5324 5325 static const struct mtk_soc_data mt7986_data = { 5326 .reg_map = &mt7986_reg_map, 5327 .ana_rgc3 = 0x128, 5328 .caps = MT7986_CAPS, 5329 .hw_features = MTK_HW_FEATURES, 5330 .required_clks = MT7986_CLKS_BITMAP, 5331 .required_pctl = false, 5332 .version = 2, 5333 .offload_version = 2, 5334 .ppe_num = 2, 5335 .hash_offset = 4, 5336 .has_accounting = true, 5337 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5338 .tx = { 5339 .desc_size = sizeof(struct mtk_tx_dma_v2), 5340 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5341 .dma_len_offset = 8, 5342 .dma_size = MTK_DMA_SIZE(2K), 5343 .fq_dma_size = MTK_DMA_SIZE(2K), 5344 }, 5345 .rx = { 5346 .desc_size = sizeof(struct mtk_rx_dma), 5347 .irq_done_mask = MTK_RX_DONE_INT, 5348 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5349 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5350 .dma_len_offset = 16, 5351 .dma_size = MTK_DMA_SIZE(2K), 5352 }, 5353 }; 5354 5355 static const struct mtk_soc_data mt7988_data = { 5356 .reg_map = &mt7988_reg_map, 5357 .ana_rgc3 = 0x128, 5358 .caps = MT7988_CAPS, 5359 .hw_features = MTK_HW_FEATURES, 5360 .required_clks = MT7988_CLKS_BITMAP, 5361 .required_pctl = false, 5362 .version = 3, 5363 .offload_version = 2, 5364 .ppe_num = 3, 5365 .hash_offset = 4, 5366 .has_accounting = true, 5367 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, 5368 .tx = { 5369 .desc_size = sizeof(struct mtk_tx_dma_v2), 5370 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5371 .dma_len_offset = 8, 5372 .dma_size = MTK_DMA_SIZE(2K), 5373 .fq_dma_size = MTK_DMA_SIZE(4K), 5374 }, 5375 .rx = { 5376 .desc_size = sizeof(struct mtk_rx_dma_v2), 5377 .irq_done_mask = MTK_RX_DONE_INT_V2, 5378 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5379 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5380 .dma_len_offset = 8, 5381 .dma_size = MTK_DMA_SIZE(2K), 5382 }, 5383 }; 5384 5385 static const struct mtk_soc_data rt5350_data = { 5386 .reg_map = &mt7628_reg_map, 5387 .caps = MT7628_CAPS, 5388 .hw_features = MTK_HW_FEATURES_MT7628, 5389 .required_clks = MT7628_CLKS_BITMAP, 5390 .required_pctl = false, 5391 .version = 1, 5392 .tx = { 5393 .desc_size = sizeof(struct mtk_tx_dma), 5394 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5395 .dma_len_offset = 16, 5396 .dma_size = MTK_DMA_SIZE(2K), 5397 }, 5398 .rx = { 5399 .desc_size = sizeof(struct mtk_rx_dma), 5400 .irq_done_mask = MTK_RX_DONE_INT, 5401 .dma_l4_valid = RX_DMA_L4_VALID_PDMA, 5402 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5403 .dma_len_offset = 16, 5404 .dma_size = MTK_DMA_SIZE(2K), 5405 }, 5406 }; 5407 5408 const struct of_device_id of_mtk_match[] = { 5409 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, 5410 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, 5411 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, 5412 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, 5413 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, 5414 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, 5415 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, 5416 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, 5417 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, 5418 {}, 5419 }; 5420 MODULE_DEVICE_TABLE(of, of_mtk_match); 5421 5422 static struct platform_driver mtk_driver = { 5423 .probe = mtk_probe, 5424 .remove = mtk_remove, 5425 .driver = { 5426 .name = "mtk_soc_eth", 5427 .of_match_table = of_mtk_match, 5428 }, 5429 }; 5430 5431 module_platform_driver(mtk_driver); 5432 5433 MODULE_LICENSE("GPL"); 5434 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 5435 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 5436