1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/clk.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/if_vlan.h> 19 #include <linux/reset.h> 20 #include <linux/tcp.h> 21 #include <linux/interrupt.h> 22 #include <linux/pinctrl/devinfo.h> 23 #include <linux/phylink.h> 24 #include <linux/pcs/pcs-mtk-lynxi.h> 25 #include <linux/jhash.h> 26 #include <linux/bitfield.h> 27 #include <net/dsa.h> 28 #include <net/dst_metadata.h> 29 #include <net/page_pool/helpers.h> 30 31 #include "mtk_eth_soc.h" 32 #include "mtk_wed.h" 33 34 static int mtk_msg_level = -1; 35 module_param_named(msg_level, mtk_msg_level, int, 0); 36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 37 38 #define MTK_ETHTOOL_STAT(x) { #x, \ 39 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 40 41 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 42 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 43 sizeof(u64) } 44 45 static const struct mtk_reg_map mtk_reg_map = { 46 .tx_irq_mask = 0x1a1c, 47 .tx_irq_status = 0x1a18, 48 .pdma = { 49 .rx_ptr = 0x0900, 50 .rx_cnt_cfg = 0x0904, 51 .pcrx_ptr = 0x0908, 52 .glo_cfg = 0x0a04, 53 .rst_idx = 0x0a08, 54 .delay_irq = 0x0a0c, 55 .irq_status = 0x0a20, 56 .irq_mask = 0x0a28, 57 .adma_rx_dbg0 = 0x0a38, 58 .int_grp = 0x0a50, 59 }, 60 .qdma = { 61 .qtx_cfg = 0x1800, 62 .qtx_sch = 0x1804, 63 .rx_ptr = 0x1900, 64 .rx_cnt_cfg = 0x1904, 65 .qcrx_ptr = 0x1908, 66 .glo_cfg = 0x1a04, 67 .rst_idx = 0x1a08, 68 .delay_irq = 0x1a0c, 69 .fc_th = 0x1a10, 70 .tx_sch_rate = 0x1a14, 71 .int_grp = 0x1a20, 72 .hred = 0x1a44, 73 .ctx_ptr = 0x1b00, 74 .dtx_ptr = 0x1b04, 75 .crx_ptr = 0x1b10, 76 .drx_ptr = 0x1b14, 77 .fq_head = 0x1b20, 78 .fq_tail = 0x1b24, 79 .fq_count = 0x1b28, 80 .fq_blen = 0x1b2c, 81 }, 82 .gdm1_cnt = 0x2400, 83 .gdma_to_ppe = { 84 [0] = 0x4444, 85 }, 86 .ppe_base = 0x0c00, 87 .wdma_base = { 88 [0] = 0x2800, 89 [1] = 0x2c00, 90 }, 91 .pse_iq_sta = 0x0110, 92 .pse_oq_sta = 0x0118, 93 }; 94 95 static const struct mtk_reg_map mt7628_reg_map = { 96 .tx_irq_mask = 0x0a28, 97 .tx_irq_status = 0x0a20, 98 .pdma = { 99 .rx_ptr = 0x0900, 100 .rx_cnt_cfg = 0x0904, 101 .pcrx_ptr = 0x0908, 102 .glo_cfg = 0x0a04, 103 .rst_idx = 0x0a08, 104 .delay_irq = 0x0a0c, 105 .irq_status = 0x0a20, 106 .irq_mask = 0x0a28, 107 .int_grp = 0x0a50, 108 }, 109 }; 110 111 static const struct mtk_reg_map mt7986_reg_map = { 112 .tx_irq_mask = 0x461c, 113 .tx_irq_status = 0x4618, 114 .pdma = { 115 .rx_ptr = 0x4100, 116 .rx_cnt_cfg = 0x4104, 117 .pcrx_ptr = 0x4108, 118 .glo_cfg = 0x4204, 119 .rst_idx = 0x4208, 120 .delay_irq = 0x420c, 121 .irq_status = 0x4220, 122 .irq_mask = 0x4228, 123 .adma_rx_dbg0 = 0x4238, 124 .int_grp = 0x4250, 125 }, 126 .qdma = { 127 .qtx_cfg = 0x4400, 128 .qtx_sch = 0x4404, 129 .rx_ptr = 0x4500, 130 .rx_cnt_cfg = 0x4504, 131 .qcrx_ptr = 0x4508, 132 .glo_cfg = 0x4604, 133 .rst_idx = 0x4608, 134 .delay_irq = 0x460c, 135 .fc_th = 0x4610, 136 .int_grp = 0x4620, 137 .hred = 0x4644, 138 .ctx_ptr = 0x4700, 139 .dtx_ptr = 0x4704, 140 .crx_ptr = 0x4710, 141 .drx_ptr = 0x4714, 142 .fq_head = 0x4720, 143 .fq_tail = 0x4724, 144 .fq_count = 0x4728, 145 .fq_blen = 0x472c, 146 .tx_sch_rate = 0x4798, 147 }, 148 .gdm1_cnt = 0x1c00, 149 .gdma_to_ppe = { 150 [0] = 0x3333, 151 [1] = 0x4444, 152 }, 153 .ppe_base = 0x2000, 154 .wdma_base = { 155 [0] = 0x4800, 156 [1] = 0x4c00, 157 }, 158 .pse_iq_sta = 0x0180, 159 .pse_oq_sta = 0x01a0, 160 }; 161 162 static const struct mtk_reg_map mt7988_reg_map = { 163 .tx_irq_mask = 0x461c, 164 .tx_irq_status = 0x4618, 165 .pdma = { 166 .rx_ptr = 0x6900, 167 .rx_cnt_cfg = 0x6904, 168 .pcrx_ptr = 0x6908, 169 .glo_cfg = 0x6a04, 170 .rst_idx = 0x6a08, 171 .delay_irq = 0x6a0c, 172 .irq_status = 0x6a20, 173 .irq_mask = 0x6a28, 174 .adma_rx_dbg0 = 0x6a38, 175 .int_grp = 0x6a50, 176 }, 177 .qdma = { 178 .qtx_cfg = 0x4400, 179 .qtx_sch = 0x4404, 180 .rx_ptr = 0x4500, 181 .rx_cnt_cfg = 0x4504, 182 .qcrx_ptr = 0x4508, 183 .glo_cfg = 0x4604, 184 .rst_idx = 0x4608, 185 .delay_irq = 0x460c, 186 .fc_th = 0x4610, 187 .int_grp = 0x4620, 188 .hred = 0x4644, 189 .ctx_ptr = 0x4700, 190 .dtx_ptr = 0x4704, 191 .crx_ptr = 0x4710, 192 .drx_ptr = 0x4714, 193 .fq_head = 0x4720, 194 .fq_tail = 0x4724, 195 .fq_count = 0x4728, 196 .fq_blen = 0x472c, 197 .tx_sch_rate = 0x4798, 198 }, 199 .gdm1_cnt = 0x1c00, 200 .gdma_to_ppe = { 201 [0] = 0x3333, 202 [1] = 0x4444, 203 [2] = 0xcccc, 204 }, 205 .ppe_base = 0x2000, 206 .wdma_base = { 207 [0] = 0x4800, 208 [1] = 0x4c00, 209 [2] = 0x5000, 210 }, 211 .pse_iq_sta = 0x0180, 212 .pse_oq_sta = 0x01a0, 213 }; 214 215 /* strings used by ethtool */ 216 static const struct mtk_ethtool_stats { 217 char str[ETH_GSTRING_LEN]; 218 u32 offset; 219 } mtk_ethtool_stats[] = { 220 MTK_ETHTOOL_STAT(tx_bytes), 221 MTK_ETHTOOL_STAT(tx_packets), 222 MTK_ETHTOOL_STAT(tx_skip), 223 MTK_ETHTOOL_STAT(tx_collisions), 224 MTK_ETHTOOL_STAT(rx_bytes), 225 MTK_ETHTOOL_STAT(rx_packets), 226 MTK_ETHTOOL_STAT(rx_overflow), 227 MTK_ETHTOOL_STAT(rx_fcs_errors), 228 MTK_ETHTOOL_STAT(rx_short_errors), 229 MTK_ETHTOOL_STAT(rx_long_errors), 230 MTK_ETHTOOL_STAT(rx_checksum_errors), 231 MTK_ETHTOOL_STAT(rx_flow_control_packets), 232 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 233 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 234 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 235 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 236 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 237 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 238 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 239 }; 240 241 static const char * const mtk_clks_source_name[] = { 242 "ethif", 243 "sgmiitop", 244 "esw", 245 "gp0", 246 "gp1", 247 "gp2", 248 "gp3", 249 "xgp1", 250 "xgp2", 251 "xgp3", 252 "crypto", 253 "fe", 254 "trgpll", 255 "sgmii_tx250m", 256 "sgmii_rx250m", 257 "sgmii_cdr_ref", 258 "sgmii_cdr_fb", 259 "sgmii2_tx250m", 260 "sgmii2_rx250m", 261 "sgmii2_cdr_ref", 262 "sgmii2_cdr_fb", 263 "sgmii_ck", 264 "eth2pll", 265 "wocpu0", 266 "wocpu1", 267 "netsys0", 268 "netsys1", 269 "ethwarp_wocpu2", 270 "ethwarp_wocpu1", 271 "ethwarp_wocpu0", 272 "top_usxgmii0_sel", 273 "top_usxgmii1_sel", 274 "top_sgm0_sel", 275 "top_sgm1_sel", 276 "top_xfi_phy0_xtal_sel", 277 "top_xfi_phy1_xtal_sel", 278 "top_eth_gmii_sel", 279 "top_eth_refck_50m_sel", 280 "top_eth_sys_200m_sel", 281 "top_eth_sys_sel", 282 "top_eth_xgmii_sel", 283 "top_eth_mii_sel", 284 "top_netsys_sel", 285 "top_netsys_500m_sel", 286 "top_netsys_pao_2x_sel", 287 "top_netsys_sync_250m_sel", 288 "top_netsys_ppefb_250m_sel", 289 "top_netsys_warp_sel", 290 }; 291 292 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 293 { 294 __raw_writel(val, eth->base + reg); 295 } 296 297 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 298 { 299 return __raw_readl(eth->base + reg); 300 } 301 302 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) 303 { 304 u32 val; 305 306 val = mtk_r32(eth, reg); 307 val &= ~mask; 308 val |= set; 309 mtk_w32(eth, val, reg); 310 return reg; 311 } 312 313 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 314 { 315 unsigned long t_start = jiffies; 316 317 while (1) { 318 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 319 return 0; 320 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 321 break; 322 cond_resched(); 323 } 324 325 dev_err(eth->dev, "mdio: MDIO timeout\n"); 326 return -ETIMEDOUT; 327 } 328 329 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 330 u32 write_data) 331 { 332 int ret; 333 334 ret = mtk_mdio_busy_wait(eth); 335 if (ret < 0) 336 return ret; 337 338 mtk_w32(eth, PHY_IAC_ACCESS | 339 PHY_IAC_START_C22 | 340 PHY_IAC_CMD_WRITE | 341 PHY_IAC_REG(phy_reg) | 342 PHY_IAC_ADDR(phy_addr) | 343 PHY_IAC_DATA(write_data), 344 MTK_PHY_IAC); 345 346 ret = mtk_mdio_busy_wait(eth); 347 if (ret < 0) 348 return ret; 349 350 return 0; 351 } 352 353 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 354 u32 devad, u32 phy_reg, u32 write_data) 355 { 356 int ret; 357 358 ret = mtk_mdio_busy_wait(eth); 359 if (ret < 0) 360 return ret; 361 362 mtk_w32(eth, PHY_IAC_ACCESS | 363 PHY_IAC_START_C45 | 364 PHY_IAC_CMD_C45_ADDR | 365 PHY_IAC_REG(devad) | 366 PHY_IAC_ADDR(phy_addr) | 367 PHY_IAC_DATA(phy_reg), 368 MTK_PHY_IAC); 369 370 ret = mtk_mdio_busy_wait(eth); 371 if (ret < 0) 372 return ret; 373 374 mtk_w32(eth, PHY_IAC_ACCESS | 375 PHY_IAC_START_C45 | 376 PHY_IAC_CMD_WRITE | 377 PHY_IAC_REG(devad) | 378 PHY_IAC_ADDR(phy_addr) | 379 PHY_IAC_DATA(write_data), 380 MTK_PHY_IAC); 381 382 ret = mtk_mdio_busy_wait(eth); 383 if (ret < 0) 384 return ret; 385 386 return 0; 387 } 388 389 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 390 { 391 int ret; 392 393 ret = mtk_mdio_busy_wait(eth); 394 if (ret < 0) 395 return ret; 396 397 mtk_w32(eth, PHY_IAC_ACCESS | 398 PHY_IAC_START_C22 | 399 PHY_IAC_CMD_C22_READ | 400 PHY_IAC_REG(phy_reg) | 401 PHY_IAC_ADDR(phy_addr), 402 MTK_PHY_IAC); 403 404 ret = mtk_mdio_busy_wait(eth); 405 if (ret < 0) 406 return ret; 407 408 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 409 } 410 411 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 412 u32 devad, u32 phy_reg) 413 { 414 int ret; 415 416 ret = mtk_mdio_busy_wait(eth); 417 if (ret < 0) 418 return ret; 419 420 mtk_w32(eth, PHY_IAC_ACCESS | 421 PHY_IAC_START_C45 | 422 PHY_IAC_CMD_C45_ADDR | 423 PHY_IAC_REG(devad) | 424 PHY_IAC_ADDR(phy_addr) | 425 PHY_IAC_DATA(phy_reg), 426 MTK_PHY_IAC); 427 428 ret = mtk_mdio_busy_wait(eth); 429 if (ret < 0) 430 return ret; 431 432 mtk_w32(eth, PHY_IAC_ACCESS | 433 PHY_IAC_START_C45 | 434 PHY_IAC_CMD_C45_READ | 435 PHY_IAC_REG(devad) | 436 PHY_IAC_ADDR(phy_addr), 437 MTK_PHY_IAC); 438 439 ret = mtk_mdio_busy_wait(eth); 440 if (ret < 0) 441 return ret; 442 443 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 444 } 445 446 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 447 int phy_reg, u16 val) 448 { 449 struct mtk_eth *eth = bus->priv; 450 451 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 452 } 453 454 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 455 int devad, int phy_reg, u16 val) 456 { 457 struct mtk_eth *eth = bus->priv; 458 459 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 460 } 461 462 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 463 { 464 struct mtk_eth *eth = bus->priv; 465 466 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 467 } 468 469 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 470 int phy_reg) 471 { 472 struct mtk_eth *eth = bus->priv; 473 474 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 475 } 476 477 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 478 phy_interface_t interface) 479 { 480 u32 val; 481 482 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 483 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 484 485 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 486 ETHSYS_TRGMII_MT7621_MASK, val); 487 488 return 0; 489 } 490 491 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 492 phy_interface_t interface) 493 { 494 int ret; 495 496 if (interface == PHY_INTERFACE_MODE_TRGMII) { 497 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 498 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); 499 if (ret) 500 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 501 return; 502 } 503 504 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); 505 } 506 507 static void mtk_setup_bridge_switch(struct mtk_eth *eth) 508 { 509 /* Force Port1 XGMAC Link Up */ 510 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), 511 MTK_XGMAC_STS(MTK_GMAC1_ID)); 512 513 /* Adjust GSW bridge IPG to 11 */ 514 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, 515 (GSW_IPG_11 << GSWTX_IPG_SHIFT) | 516 (GSW_IPG_11 << GSWRX_IPG_SHIFT), 517 MTK_GSW_CFG); 518 } 519 520 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 521 phy_interface_t interface) 522 { 523 struct mtk_mac *mac = container_of(config, struct mtk_mac, 524 phylink_config); 525 struct mtk_eth *eth = mac->hw; 526 unsigned int sid; 527 528 if (interface == PHY_INTERFACE_MODE_SGMII || 529 phy_interface_mode_is_8023z(interface)) { 530 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 531 0 : mac->id; 532 533 return eth->sgmii_pcs[sid]; 534 } 535 536 return NULL; 537 } 538 539 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 540 const struct phylink_link_state *state) 541 { 542 struct mtk_mac *mac = container_of(config, struct mtk_mac, 543 phylink_config); 544 struct mtk_eth *eth = mac->hw; 545 int val, ge_mode, err = 0; 546 u32 i; 547 548 /* MT76x8 has no hardware settings between for the MAC */ 549 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 550 mac->interface != state->interface) { 551 /* Setup soc pin functions */ 552 switch (state->interface) { 553 case PHY_INTERFACE_MODE_TRGMII: 554 case PHY_INTERFACE_MODE_RGMII_TXID: 555 case PHY_INTERFACE_MODE_RGMII_RXID: 556 case PHY_INTERFACE_MODE_RGMII_ID: 557 case PHY_INTERFACE_MODE_RGMII: 558 case PHY_INTERFACE_MODE_MII: 559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 560 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 561 if (err) 562 goto init_err; 563 } 564 break; 565 case PHY_INTERFACE_MODE_1000BASEX: 566 case PHY_INTERFACE_MODE_2500BASEX: 567 case PHY_INTERFACE_MODE_SGMII: 568 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 569 if (err) 570 goto init_err; 571 break; 572 case PHY_INTERFACE_MODE_GMII: 573 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 574 err = mtk_gmac_gephy_path_setup(eth, mac->id); 575 if (err) 576 goto init_err; 577 } 578 break; 579 case PHY_INTERFACE_MODE_INTERNAL: 580 break; 581 default: 582 goto err_phy; 583 } 584 585 /* Setup clock for 1st gmac */ 586 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 587 !phy_interface_mode_is_8023z(state->interface) && 588 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 589 if (MTK_HAS_CAPS(mac->hw->soc->caps, 590 MTK_TRGMII_MT7621_CLK)) { 591 if (mt7621_gmac0_rgmii_adjust(mac->hw, 592 state->interface)) 593 goto err_phy; 594 } else { 595 mtk_gmac0_rgmii_adjust(mac->hw, 596 state->interface); 597 598 /* mt7623_pad_clk_setup */ 599 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 600 mtk_w32(mac->hw, 601 TD_DM_DRVP(8) | TD_DM_DRVN(8), 602 TRGMII_TD_ODT(i)); 603 604 /* Assert/release MT7623 RXC reset */ 605 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 606 TRGMII_RCK_CTRL); 607 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 608 } 609 } 610 611 switch (state->interface) { 612 case PHY_INTERFACE_MODE_MII: 613 case PHY_INTERFACE_MODE_GMII: 614 ge_mode = 1; 615 break; 616 default: 617 ge_mode = 0; 618 break; 619 } 620 621 /* put the gmac into the right mode */ 622 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 623 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 624 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 625 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 626 627 mac->interface = state->interface; 628 } 629 630 /* SGMII */ 631 if (state->interface == PHY_INTERFACE_MODE_SGMII || 632 phy_interface_mode_is_8023z(state->interface)) { 633 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 634 * being setup done. 635 */ 636 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 637 638 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 639 SYSCFG0_SGMII_MASK, 640 ~(u32)SYSCFG0_SGMII_MASK); 641 642 /* Save the syscfg0 value for mac_finish */ 643 mac->syscfg0 = val; 644 } else if (phylink_autoneg_inband(mode)) { 645 dev_err(eth->dev, 646 "In-band mode not supported in non SGMII mode!\n"); 647 return; 648 } 649 650 /* Setup gmac */ 651 if (mtk_is_netsys_v3_or_greater(eth) && 652 mac->interface == PHY_INTERFACE_MODE_INTERNAL) { 653 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); 654 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); 655 656 mtk_setup_bridge_switch(eth); 657 } 658 659 return; 660 661 err_phy: 662 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 663 mac->id, phy_modes(state->interface)); 664 return; 665 666 init_err: 667 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 668 mac->id, phy_modes(state->interface), err); 669 } 670 671 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 672 phy_interface_t interface) 673 { 674 struct mtk_mac *mac = container_of(config, struct mtk_mac, 675 phylink_config); 676 struct mtk_eth *eth = mac->hw; 677 u32 mcr_cur, mcr_new; 678 679 /* Enable SGMII */ 680 if (interface == PHY_INTERFACE_MODE_SGMII || 681 phy_interface_mode_is_8023z(interface)) 682 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 683 SYSCFG0_SGMII_MASK, mac->syscfg0); 684 685 /* Setup gmac */ 686 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 687 mcr_new = mcr_cur; 688 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 689 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS; 690 691 /* Only update control register when needed! */ 692 if (mcr_new != mcr_cur) 693 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 694 695 return 0; 696 } 697 698 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 699 phy_interface_t interface) 700 { 701 struct mtk_mac *mac = container_of(config, struct mtk_mac, 702 phylink_config); 703 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 704 705 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK); 706 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 707 } 708 709 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 710 int speed) 711 { 712 const struct mtk_soc_data *soc = eth->soc; 713 u32 ofs, val; 714 715 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 716 return; 717 718 val = MTK_QTX_SCH_MIN_RATE_EN | 719 /* minimum: 10 Mbps */ 720 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 721 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 722 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 723 if (mtk_is_netsys_v1(eth)) 724 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 725 726 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 727 switch (speed) { 728 case SPEED_10: 729 val |= MTK_QTX_SCH_MAX_RATE_EN | 730 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 731 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 732 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 733 break; 734 case SPEED_100: 735 val |= MTK_QTX_SCH_MAX_RATE_EN | 736 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 737 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3) | 738 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 739 break; 740 case SPEED_1000: 741 val |= MTK_QTX_SCH_MAX_RATE_EN | 742 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 743 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 744 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 745 break; 746 default: 747 break; 748 } 749 } else { 750 switch (speed) { 751 case SPEED_10: 752 val |= MTK_QTX_SCH_MAX_RATE_EN | 753 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 754 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 755 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 756 break; 757 case SPEED_100: 758 val |= MTK_QTX_SCH_MAX_RATE_EN | 759 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 760 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 761 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 762 break; 763 case SPEED_1000: 764 val |= MTK_QTX_SCH_MAX_RATE_EN | 765 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 766 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 6) | 767 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 768 break; 769 default: 770 break; 771 } 772 } 773 774 ofs = MTK_QTX_OFFSET * idx; 775 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 776 } 777 778 static void mtk_mac_link_up(struct phylink_config *config, 779 struct phy_device *phy, 780 unsigned int mode, phy_interface_t interface, 781 int speed, int duplex, bool tx_pause, bool rx_pause) 782 { 783 struct mtk_mac *mac = container_of(config, struct mtk_mac, 784 phylink_config); 785 u32 mcr; 786 787 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 788 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 789 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 790 MAC_MCR_FORCE_RX_FC); 791 792 /* Configure speed */ 793 mac->speed = speed; 794 switch (speed) { 795 case SPEED_2500: 796 case SPEED_1000: 797 mcr |= MAC_MCR_SPEED_1000; 798 break; 799 case SPEED_100: 800 mcr |= MAC_MCR_SPEED_100; 801 break; 802 } 803 804 /* Configure duplex */ 805 if (duplex == DUPLEX_FULL) 806 mcr |= MAC_MCR_FORCE_DPX; 807 808 /* Configure pause modes - phylink will avoid these for half duplex */ 809 if (tx_pause) 810 mcr |= MAC_MCR_FORCE_TX_FC; 811 if (rx_pause) 812 mcr |= MAC_MCR_FORCE_RX_FC; 813 814 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK; 815 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 816 } 817 818 static void mtk_mac_disable_tx_lpi(struct phylink_config *config) 819 { 820 struct mtk_mac *mac = container_of(config, struct mtk_mac, 821 phylink_config); 822 struct mtk_eth *eth = mac->hw; 823 824 mtk_m32(eth, MAC_MCR_EEE100M | MAC_MCR_EEE1G, 0, MTK_MAC_MCR(mac->id)); 825 } 826 827 static int mtk_mac_enable_tx_lpi(struct phylink_config *config, u32 timer, 828 bool tx_clk_stop) 829 { 830 struct mtk_mac *mac = container_of(config, struct mtk_mac, 831 phylink_config); 832 struct mtk_eth *eth = mac->hw; 833 u32 val; 834 835 /* Tx idle timer in ms */ 836 timer = DIV_ROUND_UP(timer, 1000); 837 838 /* If the timer is zero, then set LPI_MODE, which allows the 839 * system to enter LPI mode immediately rather than waiting for 840 * the LPI threshold. 841 */ 842 if (!timer) 843 val = MAC_EEE_LPI_MODE; 844 else if (FIELD_FIT(MAC_EEE_LPI_TXIDLE_THD, timer)) 845 val = FIELD_PREP(MAC_EEE_LPI_TXIDLE_THD, timer); 846 else 847 val = MAC_EEE_LPI_TXIDLE_THD; 848 849 if (tx_clk_stop) 850 val |= MAC_EEE_CKG_TXIDLE; 851 852 /* PHY Wake-up time, this field does not have a reset value, so use the 853 * reset value from MT7531 (36us for 100M and 17us for 1000M). 854 */ 855 val |= FIELD_PREP(MAC_EEE_WAKEUP_TIME_1000, 17) | 856 FIELD_PREP(MAC_EEE_WAKEUP_TIME_100, 36); 857 858 mtk_w32(eth, val, MTK_MAC_EEECR(mac->id)); 859 mtk_m32(eth, 0, MAC_MCR_EEE100M | MAC_MCR_EEE1G, MTK_MAC_MCR(mac->id)); 860 861 return 0; 862 } 863 864 static const struct phylink_mac_ops mtk_phylink_ops = { 865 .mac_select_pcs = mtk_mac_select_pcs, 866 .mac_config = mtk_mac_config, 867 .mac_finish = mtk_mac_finish, 868 .mac_link_down = mtk_mac_link_down, 869 .mac_link_up = mtk_mac_link_up, 870 .mac_disable_tx_lpi = mtk_mac_disable_tx_lpi, 871 .mac_enable_tx_lpi = mtk_mac_enable_tx_lpi, 872 }; 873 874 static void mtk_mdio_config(struct mtk_eth *eth) 875 { 876 u32 val; 877 878 /* Configure MDC Divider */ 879 val = FIELD_PREP(PPSC_MDC_CFG, eth->mdc_divider); 880 881 /* Configure MDC Turbo Mode */ 882 if (mtk_is_netsys_v3_or_greater(eth)) 883 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); 884 else 885 val |= PPSC_MDC_TURBO; 886 887 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); 888 } 889 890 static int mtk_mdio_init(struct mtk_eth *eth) 891 { 892 unsigned int max_clk = 2500000; 893 struct device_node *mii_np; 894 int ret; 895 u32 val; 896 897 mii_np = of_get_available_child_by_name(eth->dev->of_node, "mdio-bus"); 898 if (!mii_np) { 899 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 900 return -ENODEV; 901 } 902 903 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 904 if (!eth->mii_bus) { 905 ret = -ENOMEM; 906 goto err_put_node; 907 } 908 909 eth->mii_bus->name = "mdio"; 910 eth->mii_bus->read = mtk_mdio_read_c22; 911 eth->mii_bus->write = mtk_mdio_write_c22; 912 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 913 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 914 eth->mii_bus->priv = eth; 915 eth->mii_bus->parent = eth->dev; 916 917 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 918 919 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { 920 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { 921 dev_err(eth->dev, "MDIO clock frequency out of range"); 922 ret = -EINVAL; 923 goto err_put_node; 924 } 925 max_clk = val; 926 } 927 eth->mdc_divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 928 mtk_mdio_config(eth); 929 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / eth->mdc_divider); 930 ret = of_mdiobus_register(eth->mii_bus, mii_np); 931 932 err_put_node: 933 of_node_put(mii_np); 934 return ret; 935 } 936 937 static void mtk_mdio_cleanup(struct mtk_eth *eth) 938 { 939 if (!eth->mii_bus) 940 return; 941 942 mdiobus_unregister(eth->mii_bus); 943 } 944 945 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 946 { 947 unsigned long flags; 948 u32 val; 949 950 spin_lock_irqsave(ð->tx_irq_lock, flags); 951 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 952 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 953 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 954 } 955 956 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 957 { 958 unsigned long flags; 959 u32 val; 960 961 spin_lock_irqsave(ð->tx_irq_lock, flags); 962 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 963 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 964 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 965 } 966 967 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 968 { 969 unsigned long flags; 970 u32 val; 971 972 spin_lock_irqsave(ð->rx_irq_lock, flags); 973 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 974 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 975 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 976 } 977 978 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 979 { 980 unsigned long flags; 981 u32 val; 982 983 spin_lock_irqsave(ð->rx_irq_lock, flags); 984 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 985 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 986 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 987 } 988 989 static int mtk_set_mac_address(struct net_device *dev, void *p) 990 { 991 int ret = eth_mac_addr(dev, p); 992 struct mtk_mac *mac = netdev_priv(dev); 993 struct mtk_eth *eth = mac->hw; 994 const char *macaddr = dev->dev_addr; 995 996 if (ret) 997 return ret; 998 999 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 1000 return -EBUSY; 1001 1002 spin_lock_bh(&mac->hw->page_lock); 1003 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 1004 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 1005 MT7628_SDM_MAC_ADRH); 1006 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 1007 (macaddr[4] << 8) | macaddr[5], 1008 MT7628_SDM_MAC_ADRL); 1009 } else { 1010 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 1011 MTK_GDMA_MAC_ADRH(mac->id)); 1012 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 1013 (macaddr[4] << 8) | macaddr[5], 1014 MTK_GDMA_MAC_ADRL(mac->id)); 1015 } 1016 spin_unlock_bh(&mac->hw->page_lock); 1017 1018 return 0; 1019 } 1020 1021 void mtk_stats_update_mac(struct mtk_mac *mac) 1022 { 1023 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1024 struct mtk_eth *eth = mac->hw; 1025 1026 u64_stats_update_begin(&hw_stats->syncp); 1027 1028 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 1029 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 1030 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 1031 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 1032 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 1033 hw_stats->rx_checksum_errors += 1034 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 1035 } else { 1036 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 1037 unsigned int offs = hw_stats->reg_offset; 1038 u64 stats; 1039 1040 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 1041 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 1042 if (stats) 1043 hw_stats->rx_bytes += (stats << 32); 1044 hw_stats->rx_packets += 1045 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 1046 hw_stats->rx_overflow += 1047 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 1048 hw_stats->rx_fcs_errors += 1049 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 1050 hw_stats->rx_short_errors += 1051 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 1052 hw_stats->rx_long_errors += 1053 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 1054 hw_stats->rx_checksum_errors += 1055 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 1056 hw_stats->rx_flow_control_packets += 1057 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 1058 1059 if (mtk_is_netsys_v3_or_greater(eth)) { 1060 hw_stats->tx_skip += 1061 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); 1062 hw_stats->tx_collisions += 1063 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); 1064 hw_stats->tx_bytes += 1065 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); 1066 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); 1067 if (stats) 1068 hw_stats->tx_bytes += (stats << 32); 1069 hw_stats->tx_packets += 1070 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); 1071 } else { 1072 hw_stats->tx_skip += 1073 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 1074 hw_stats->tx_collisions += 1075 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 1076 hw_stats->tx_bytes += 1077 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 1078 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 1079 if (stats) 1080 hw_stats->tx_bytes += (stats << 32); 1081 hw_stats->tx_packets += 1082 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 1083 } 1084 } 1085 1086 u64_stats_update_end(&hw_stats->syncp); 1087 } 1088 1089 static void mtk_stats_update(struct mtk_eth *eth) 1090 { 1091 int i; 1092 1093 for (i = 0; i < MTK_MAX_DEVS; i++) { 1094 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 1095 continue; 1096 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 1097 mtk_stats_update_mac(eth->mac[i]); 1098 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 1099 } 1100 } 1101 } 1102 1103 static void mtk_get_stats64(struct net_device *dev, 1104 struct rtnl_link_stats64 *storage) 1105 { 1106 struct mtk_mac *mac = netdev_priv(dev); 1107 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1108 unsigned int start; 1109 1110 if (netif_running(dev) && netif_device_present(dev)) { 1111 if (spin_trylock_bh(&hw_stats->stats_lock)) { 1112 mtk_stats_update_mac(mac); 1113 spin_unlock_bh(&hw_stats->stats_lock); 1114 } 1115 } 1116 1117 do { 1118 start = u64_stats_fetch_begin(&hw_stats->syncp); 1119 storage->rx_packets = hw_stats->rx_packets; 1120 storage->tx_packets = hw_stats->tx_packets; 1121 storage->rx_bytes = hw_stats->rx_bytes; 1122 storage->tx_bytes = hw_stats->tx_bytes; 1123 storage->collisions = hw_stats->tx_collisions; 1124 storage->rx_length_errors = hw_stats->rx_short_errors + 1125 hw_stats->rx_long_errors; 1126 storage->rx_over_errors = hw_stats->rx_overflow; 1127 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1128 storage->rx_errors = hw_stats->rx_checksum_errors; 1129 storage->tx_aborted_errors = hw_stats->tx_skip; 1130 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1131 1132 storage->tx_errors = dev->stats.tx_errors; 1133 storage->rx_dropped = dev->stats.rx_dropped; 1134 storage->tx_dropped = dev->stats.tx_dropped; 1135 } 1136 1137 static inline int mtk_max_frag_size(int mtu) 1138 { 1139 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1140 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1141 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1142 1143 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1144 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1145 } 1146 1147 static inline int mtk_max_buf_size(int frag_size) 1148 { 1149 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1150 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1151 1152 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1153 1154 return buf_size; 1155 } 1156 1157 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1158 struct mtk_rx_dma_v2 *dma_rxd) 1159 { 1160 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1161 if (!(rxd->rxd2 & RX_DMA_DONE)) 1162 return false; 1163 1164 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1165 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1166 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1167 if (mtk_is_netsys_v3_or_greater(eth)) { 1168 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1169 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1170 } 1171 1172 return true; 1173 } 1174 1175 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1176 { 1177 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1178 unsigned long data; 1179 1180 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1181 get_order(size)); 1182 1183 return (void *)data; 1184 } 1185 1186 /* the qdma core needs scratch memory to be setup */ 1187 static int mtk_init_fq_dma(struct mtk_eth *eth) 1188 { 1189 const struct mtk_soc_data *soc = eth->soc; 1190 dma_addr_t phy_ring_tail; 1191 int cnt = soc->tx.fq_dma_size; 1192 dma_addr_t dma_addr; 1193 int i, j, len; 1194 1195 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) 1196 eth->scratch_ring = eth->sram_base; 1197 else 1198 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1199 cnt * soc->tx.desc_size, 1200 ð->phy_scratch_ring, 1201 GFP_KERNEL); 1202 1203 if (unlikely(!eth->scratch_ring)) 1204 return -ENOMEM; 1205 1206 phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1); 1207 1208 for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) { 1209 len = min_t(int, cnt - j * MTK_FQ_DMA_LENGTH, MTK_FQ_DMA_LENGTH); 1210 eth->scratch_head[j] = kcalloc(len, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1211 1212 if (unlikely(!eth->scratch_head[j])) 1213 return -ENOMEM; 1214 1215 dma_addr = dma_map_single(eth->dma_dev, 1216 eth->scratch_head[j], len * MTK_QDMA_PAGE_SIZE, 1217 DMA_FROM_DEVICE); 1218 1219 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1220 return -ENOMEM; 1221 1222 for (i = 0; i < len; i++) { 1223 struct mtk_tx_dma_v2 *txd; 1224 1225 txd = eth->scratch_ring + (j * MTK_FQ_DMA_LENGTH + i) * soc->tx.desc_size; 1226 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1227 if (j * MTK_FQ_DMA_LENGTH + i < cnt) 1228 txd->txd2 = eth->phy_scratch_ring + 1229 (j * MTK_FQ_DMA_LENGTH + i + 1) * soc->tx.desc_size; 1230 1231 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1232 if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA)) 1233 txd->txd3 |= TX_DMA_PREP_ADDR64(dma_addr + i * MTK_QDMA_PAGE_SIZE); 1234 1235 txd->txd4 = 0; 1236 if (mtk_is_netsys_v2_or_greater(eth)) { 1237 txd->txd5 = 0; 1238 txd->txd6 = 0; 1239 txd->txd7 = 0; 1240 txd->txd8 = 0; 1241 } 1242 } 1243 } 1244 1245 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1246 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1247 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1248 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1249 1250 return 0; 1251 } 1252 1253 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1254 { 1255 return ring->dma + (desc - ring->phys); 1256 } 1257 1258 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1259 void *txd, u32 txd_size) 1260 { 1261 int idx = (txd - ring->dma) / txd_size; 1262 1263 return &ring->buf[idx]; 1264 } 1265 1266 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1267 struct mtk_tx_dma *dma) 1268 { 1269 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1270 } 1271 1272 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1273 { 1274 return (dma - ring->dma) / txd_size; 1275 } 1276 1277 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1278 struct xdp_frame_bulk *bq, bool napi) 1279 { 1280 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1281 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1282 dma_unmap_single(eth->dma_dev, 1283 dma_unmap_addr(tx_buf, dma_addr0), 1284 dma_unmap_len(tx_buf, dma_len0), 1285 DMA_TO_DEVICE); 1286 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1287 dma_unmap_page(eth->dma_dev, 1288 dma_unmap_addr(tx_buf, dma_addr0), 1289 dma_unmap_len(tx_buf, dma_len0), 1290 DMA_TO_DEVICE); 1291 } 1292 } else { 1293 if (dma_unmap_len(tx_buf, dma_len0)) { 1294 dma_unmap_page(eth->dma_dev, 1295 dma_unmap_addr(tx_buf, dma_addr0), 1296 dma_unmap_len(tx_buf, dma_len0), 1297 DMA_TO_DEVICE); 1298 } 1299 1300 if (dma_unmap_len(tx_buf, dma_len1)) { 1301 dma_unmap_page(eth->dma_dev, 1302 dma_unmap_addr(tx_buf, dma_addr1), 1303 dma_unmap_len(tx_buf, dma_len1), 1304 DMA_TO_DEVICE); 1305 } 1306 } 1307 1308 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1309 if (tx_buf->type == MTK_TYPE_SKB) { 1310 struct sk_buff *skb = tx_buf->data; 1311 1312 if (napi) 1313 napi_consume_skb(skb, napi); 1314 else 1315 dev_kfree_skb_any(skb); 1316 } else { 1317 struct xdp_frame *xdpf = tx_buf->data; 1318 1319 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1320 xdp_return_frame_rx_napi(xdpf); 1321 else if (bq) 1322 xdp_return_frame_bulk(xdpf, bq); 1323 else 1324 xdp_return_frame(xdpf); 1325 } 1326 } 1327 tx_buf->flags = 0; 1328 tx_buf->data = NULL; 1329 } 1330 1331 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1332 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1333 size_t size, int idx) 1334 { 1335 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1336 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1337 dma_unmap_len_set(tx_buf, dma_len0, size); 1338 } else { 1339 if (idx & 1) { 1340 txd->txd3 = mapped_addr; 1341 txd->txd2 |= TX_DMA_PLEN1(size); 1342 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1343 dma_unmap_len_set(tx_buf, dma_len1, size); 1344 } else { 1345 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1346 txd->txd1 = mapped_addr; 1347 txd->txd2 = TX_DMA_PLEN0(size); 1348 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1349 dma_unmap_len_set(tx_buf, dma_len0, size); 1350 } 1351 } 1352 } 1353 1354 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1355 struct mtk_tx_dma_desc_info *info) 1356 { 1357 struct mtk_mac *mac = netdev_priv(dev); 1358 struct mtk_eth *eth = mac->hw; 1359 struct mtk_tx_dma *desc = txd; 1360 u32 data; 1361 1362 WRITE_ONCE(desc->txd1, info->addr); 1363 1364 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1365 FIELD_PREP(TX_DMA_PQID, info->qid); 1366 if (info->last) 1367 data |= TX_DMA_LS0; 1368 WRITE_ONCE(desc->txd3, data); 1369 1370 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1371 if (info->first) { 1372 if (info->gso) 1373 data |= TX_DMA_TSO; 1374 /* tx checksum offload */ 1375 if (info->csum) 1376 data |= TX_DMA_CHKSUM; 1377 /* vlan header offload */ 1378 if (info->vlan) 1379 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1380 } 1381 WRITE_ONCE(desc->txd4, data); 1382 } 1383 1384 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1385 struct mtk_tx_dma_desc_info *info) 1386 { 1387 struct mtk_mac *mac = netdev_priv(dev); 1388 struct mtk_tx_dma_v2 *desc = txd; 1389 struct mtk_eth *eth = mac->hw; 1390 u32 data; 1391 1392 WRITE_ONCE(desc->txd1, info->addr); 1393 1394 data = TX_DMA_PLEN0(info->size); 1395 if (info->last) 1396 data |= TX_DMA_LS0; 1397 1398 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 1399 data |= TX_DMA_PREP_ADDR64(info->addr); 1400 1401 WRITE_ONCE(desc->txd3, data); 1402 1403 /* set forward port */ 1404 switch (mac->id) { 1405 case MTK_GMAC1_ID: 1406 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; 1407 break; 1408 case MTK_GMAC2_ID: 1409 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; 1410 break; 1411 case MTK_GMAC3_ID: 1412 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; 1413 break; 1414 } 1415 1416 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1417 WRITE_ONCE(desc->txd4, data); 1418 1419 data = 0; 1420 if (info->first) { 1421 if (info->gso) 1422 data |= TX_DMA_TSO_V2; 1423 /* tx checksum offload */ 1424 if (info->csum) 1425 data |= TX_DMA_CHKSUM_V2; 1426 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) 1427 data |= TX_DMA_SPTAG_V3; 1428 } 1429 WRITE_ONCE(desc->txd5, data); 1430 1431 data = 0; 1432 if (info->first && info->vlan) 1433 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1434 WRITE_ONCE(desc->txd6, data); 1435 1436 WRITE_ONCE(desc->txd7, 0); 1437 WRITE_ONCE(desc->txd8, 0); 1438 } 1439 1440 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1441 struct mtk_tx_dma_desc_info *info) 1442 { 1443 struct mtk_mac *mac = netdev_priv(dev); 1444 struct mtk_eth *eth = mac->hw; 1445 1446 if (mtk_is_netsys_v2_or_greater(eth)) 1447 mtk_tx_set_dma_desc_v2(dev, txd, info); 1448 else 1449 mtk_tx_set_dma_desc_v1(dev, txd, info); 1450 } 1451 1452 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1453 int tx_num, struct mtk_tx_ring *ring, bool gso) 1454 { 1455 struct mtk_tx_dma_desc_info txd_info = { 1456 .size = skb_headlen(skb), 1457 .gso = gso, 1458 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1459 .vlan = skb_vlan_tag_present(skb), 1460 .qid = skb_get_queue_mapping(skb), 1461 .vlan_tci = skb_vlan_tag_get(skb), 1462 .first = true, 1463 .last = !skb_is_nonlinear(skb), 1464 }; 1465 struct netdev_queue *txq; 1466 struct mtk_mac *mac = netdev_priv(dev); 1467 struct mtk_eth *eth = mac->hw; 1468 const struct mtk_soc_data *soc = eth->soc; 1469 struct mtk_tx_dma *itxd, *txd; 1470 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1471 struct mtk_tx_buf *itx_buf, *tx_buf; 1472 int i, n_desc = 1; 1473 int queue = skb_get_queue_mapping(skb); 1474 int k = 0; 1475 1476 txq = netdev_get_tx_queue(dev, queue); 1477 itxd = ring->next_free; 1478 itxd_pdma = qdma_to_pdma(ring, itxd); 1479 if (itxd == ring->last_free) 1480 return -ENOMEM; 1481 1482 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); 1483 memset(itx_buf, 0, sizeof(*itx_buf)); 1484 1485 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1486 DMA_TO_DEVICE); 1487 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1488 return -ENOMEM; 1489 1490 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1491 1492 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1493 itx_buf->mac_id = mac->id; 1494 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1495 k++); 1496 1497 /* TX SG offload */ 1498 txd = itxd; 1499 txd_pdma = qdma_to_pdma(ring, txd); 1500 1501 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1502 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1503 unsigned int offset = 0; 1504 int frag_size = skb_frag_size(frag); 1505 1506 while (frag_size) { 1507 bool new_desc = true; 1508 1509 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1510 (i & 0x1)) { 1511 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1512 txd_pdma = qdma_to_pdma(ring, txd); 1513 if (txd == ring->last_free) 1514 goto err_dma; 1515 1516 n_desc++; 1517 } else { 1518 new_desc = false; 1519 } 1520 1521 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1522 txd_info.size = min_t(unsigned int, frag_size, 1523 soc->tx.dma_max_len); 1524 txd_info.qid = queue; 1525 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1526 !(frag_size - txd_info.size); 1527 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1528 offset, txd_info.size, 1529 DMA_TO_DEVICE); 1530 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1531 goto err_dma; 1532 1533 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1534 1535 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1536 soc->tx.desc_size); 1537 if (new_desc) 1538 memset(tx_buf, 0, sizeof(*tx_buf)); 1539 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1540 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1541 tx_buf->mac_id = mac->id; 1542 1543 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1544 txd_info.size, k++); 1545 1546 frag_size -= txd_info.size; 1547 offset += txd_info.size; 1548 } 1549 } 1550 1551 /* store skb to cleanup */ 1552 itx_buf->type = MTK_TYPE_SKB; 1553 itx_buf->data = skb; 1554 1555 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1556 if (k & 0x1) 1557 txd_pdma->txd2 |= TX_DMA_LS0; 1558 else 1559 txd_pdma->txd2 |= TX_DMA_LS1; 1560 } 1561 1562 netdev_tx_sent_queue(txq, skb->len); 1563 skb_tx_timestamp(skb); 1564 1565 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1566 atomic_sub(n_desc, &ring->free_count); 1567 1568 /* make sure that all changes to the dma ring are flushed before we 1569 * continue 1570 */ 1571 wmb(); 1572 1573 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1574 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1575 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1576 } else { 1577 int next_idx; 1578 1579 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size), 1580 ring->dma_size); 1581 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1582 } 1583 1584 return 0; 1585 1586 err_dma: 1587 do { 1588 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); 1589 1590 /* unmap dma */ 1591 mtk_tx_unmap(eth, tx_buf, NULL, false); 1592 1593 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1594 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1595 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1596 1597 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1598 itxd_pdma = qdma_to_pdma(ring, itxd); 1599 } while (itxd != txd); 1600 1601 return -ENOMEM; 1602 } 1603 1604 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1605 { 1606 int i, nfrags = 1; 1607 skb_frag_t *frag; 1608 1609 if (skb_is_gso(skb)) { 1610 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1611 frag = &skb_shinfo(skb)->frags[i]; 1612 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1613 eth->soc->tx.dma_max_len); 1614 } 1615 } else { 1616 nfrags += skb_shinfo(skb)->nr_frags; 1617 } 1618 1619 return nfrags; 1620 } 1621 1622 static int mtk_queue_stopped(struct mtk_eth *eth) 1623 { 1624 int i; 1625 1626 for (i = 0; i < MTK_MAX_DEVS; i++) { 1627 if (!eth->netdev[i]) 1628 continue; 1629 if (netif_queue_stopped(eth->netdev[i])) 1630 return 1; 1631 } 1632 1633 return 0; 1634 } 1635 1636 static void mtk_wake_queue(struct mtk_eth *eth) 1637 { 1638 int i; 1639 1640 for (i = 0; i < MTK_MAX_DEVS; i++) { 1641 if (!eth->netdev[i]) 1642 continue; 1643 netif_tx_wake_all_queues(eth->netdev[i]); 1644 } 1645 } 1646 1647 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1648 { 1649 struct mtk_mac *mac = netdev_priv(dev); 1650 struct mtk_eth *eth = mac->hw; 1651 struct mtk_tx_ring *ring = ð->tx_ring; 1652 struct net_device_stats *stats = &dev->stats; 1653 bool gso = false; 1654 int tx_num; 1655 1656 /* normally we can rely on the stack not calling this more than once, 1657 * however we have 2 queues running on the same ring so we need to lock 1658 * the ring access 1659 */ 1660 spin_lock(ð->page_lock); 1661 1662 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1663 goto drop; 1664 1665 tx_num = mtk_cal_txd_req(eth, skb); 1666 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1667 netif_tx_stop_all_queues(dev); 1668 netif_err(eth, tx_queued, dev, 1669 "Tx Ring full when queue awake!\n"); 1670 spin_unlock(ð->page_lock); 1671 return NETDEV_TX_BUSY; 1672 } 1673 1674 /* TSO: fill MSS info in tcp checksum field */ 1675 if (skb_is_gso(skb)) { 1676 if (skb_cow_head(skb, 0)) { 1677 netif_warn(eth, tx_err, dev, 1678 "GSO expand head fail.\n"); 1679 goto drop; 1680 } 1681 1682 if (skb_shinfo(skb)->gso_type & 1683 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1684 gso = true; 1685 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1686 } 1687 } 1688 1689 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1690 goto drop; 1691 1692 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1693 netif_tx_stop_all_queues(dev); 1694 1695 spin_unlock(ð->page_lock); 1696 1697 return NETDEV_TX_OK; 1698 1699 drop: 1700 spin_unlock(ð->page_lock); 1701 stats->tx_dropped++; 1702 dev_kfree_skb_any(skb); 1703 return NETDEV_TX_OK; 1704 } 1705 1706 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1707 { 1708 int i; 1709 struct mtk_rx_ring *ring; 1710 int idx; 1711 1712 if (!eth->hwlro) 1713 return ð->rx_ring[0]; 1714 1715 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1716 struct mtk_rx_dma *rxd; 1717 1718 ring = ð->rx_ring[i]; 1719 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1720 rxd = ring->dma + idx * eth->soc->rx.desc_size; 1721 if (rxd->rxd2 & RX_DMA_DONE) { 1722 ring->calc_idx_update = true; 1723 return ring; 1724 } 1725 } 1726 1727 return NULL; 1728 } 1729 1730 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1731 { 1732 struct mtk_rx_ring *ring; 1733 int i; 1734 1735 if (!eth->hwlro) { 1736 ring = ð->rx_ring[0]; 1737 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1738 } else { 1739 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1740 ring = ð->rx_ring[i]; 1741 if (ring->calc_idx_update) { 1742 ring->calc_idx_update = false; 1743 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1744 } 1745 } 1746 } 1747 } 1748 1749 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1750 { 1751 return mtk_is_netsys_v2_or_greater(eth); 1752 } 1753 1754 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1755 struct xdp_rxq_info *xdp_q, 1756 int id, int size) 1757 { 1758 struct page_pool_params pp_params = { 1759 .order = 0, 1760 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1761 .pool_size = size, 1762 .nid = NUMA_NO_NODE, 1763 .dev = eth->dma_dev, 1764 .offset = MTK_PP_HEADROOM, 1765 .max_len = MTK_PP_MAX_BUF_SIZE, 1766 }; 1767 struct page_pool *pp; 1768 int err; 1769 1770 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1771 : DMA_FROM_DEVICE; 1772 pp = page_pool_create(&pp_params); 1773 if (IS_ERR(pp)) 1774 return pp; 1775 1776 err = __xdp_rxq_info_reg(xdp_q, eth->dummy_dev, id, 1777 eth->rx_napi.napi_id, PAGE_SIZE); 1778 if (err < 0) 1779 goto err_free_pp; 1780 1781 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1782 if (err) 1783 goto err_unregister_rxq; 1784 1785 return pp; 1786 1787 err_unregister_rxq: 1788 xdp_rxq_info_unreg(xdp_q); 1789 err_free_pp: 1790 page_pool_destroy(pp); 1791 1792 return ERR_PTR(err); 1793 } 1794 1795 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1796 gfp_t gfp_mask) 1797 { 1798 struct page *page; 1799 1800 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1801 if (!page) 1802 return NULL; 1803 1804 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1805 return page_address(page); 1806 } 1807 1808 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1809 { 1810 if (ring->page_pool) 1811 page_pool_put_full_page(ring->page_pool, 1812 virt_to_head_page(data), napi); 1813 else 1814 skb_free_frag(data); 1815 } 1816 1817 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1818 struct mtk_tx_dma_desc_info *txd_info, 1819 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1820 void *data, u16 headroom, int index, bool dma_map) 1821 { 1822 struct mtk_tx_ring *ring = ð->tx_ring; 1823 struct mtk_mac *mac = netdev_priv(dev); 1824 struct mtk_tx_dma *txd_pdma; 1825 1826 if (dma_map) { /* ndo_xdp_xmit */ 1827 txd_info->addr = dma_map_single(eth->dma_dev, data, 1828 txd_info->size, DMA_TO_DEVICE); 1829 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1830 return -ENOMEM; 1831 1832 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1833 } else { 1834 struct page *page = virt_to_head_page(data); 1835 1836 txd_info->addr = page_pool_get_dma_addr(page) + 1837 sizeof(struct xdp_frame) + headroom; 1838 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1839 txd_info->size, DMA_BIDIRECTIONAL); 1840 } 1841 mtk_tx_set_dma_desc(dev, txd, txd_info); 1842 1843 tx_buf->mac_id = mac->id; 1844 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1845 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1846 1847 txd_pdma = qdma_to_pdma(ring, txd); 1848 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1849 index); 1850 1851 return 0; 1852 } 1853 1854 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1855 struct net_device *dev, bool dma_map) 1856 { 1857 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1858 const struct mtk_soc_data *soc = eth->soc; 1859 struct mtk_tx_ring *ring = ð->tx_ring; 1860 struct mtk_mac *mac = netdev_priv(dev); 1861 struct mtk_tx_dma_desc_info txd_info = { 1862 .size = xdpf->len, 1863 .first = true, 1864 .last = !xdp_frame_has_frags(xdpf), 1865 .qid = mac->id, 1866 }; 1867 int err, index = 0, n_desc = 1, nr_frags; 1868 struct mtk_tx_buf *htx_buf, *tx_buf; 1869 struct mtk_tx_dma *htxd, *txd; 1870 void *data = xdpf->data; 1871 1872 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1873 return -EBUSY; 1874 1875 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1876 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1877 return -EBUSY; 1878 1879 spin_lock(ð->page_lock); 1880 1881 txd = ring->next_free; 1882 if (txd == ring->last_free) { 1883 spin_unlock(ð->page_lock); 1884 return -ENOMEM; 1885 } 1886 htxd = txd; 1887 1888 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size); 1889 memset(tx_buf, 0, sizeof(*tx_buf)); 1890 htx_buf = tx_buf; 1891 1892 for (;;) { 1893 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1894 data, xdpf->headroom, index, dma_map); 1895 if (err < 0) 1896 goto unmap; 1897 1898 if (txd_info.last) 1899 break; 1900 1901 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1902 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1903 if (txd == ring->last_free) 1904 goto unmap; 1905 1906 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1907 soc->tx.desc_size); 1908 memset(tx_buf, 0, sizeof(*tx_buf)); 1909 n_desc++; 1910 } 1911 1912 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1913 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1914 txd_info.last = index + 1 == nr_frags; 1915 txd_info.qid = mac->id; 1916 data = skb_frag_address(&sinfo->frags[index]); 1917 1918 index++; 1919 } 1920 /* store xdpf for cleanup */ 1921 htx_buf->data = xdpf; 1922 1923 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1924 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1925 1926 if (index & 1) 1927 txd_pdma->txd2 |= TX_DMA_LS0; 1928 else 1929 txd_pdma->txd2 |= TX_DMA_LS1; 1930 } 1931 1932 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1933 atomic_sub(n_desc, &ring->free_count); 1934 1935 /* make sure that all changes to the dma ring are flushed before we 1936 * continue 1937 */ 1938 wmb(); 1939 1940 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1941 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1942 } else { 1943 int idx; 1944 1945 idx = txd_to_idx(ring, txd, soc->tx.desc_size); 1946 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1947 MT7628_TX_CTX_IDX0); 1948 } 1949 1950 spin_unlock(ð->page_lock); 1951 1952 return 0; 1953 1954 unmap: 1955 while (htxd != txd) { 1956 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size); 1957 mtk_tx_unmap(eth, tx_buf, NULL, false); 1958 1959 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1960 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1961 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1962 1963 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1964 } 1965 1966 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1967 } 1968 1969 spin_unlock(ð->page_lock); 1970 1971 return err; 1972 } 1973 1974 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1975 struct xdp_frame **frames, u32 flags) 1976 { 1977 struct mtk_mac *mac = netdev_priv(dev); 1978 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1979 struct mtk_eth *eth = mac->hw; 1980 int i, nxmit = 0; 1981 1982 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1983 return -EINVAL; 1984 1985 for (i = 0; i < num_frame; i++) { 1986 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1987 break; 1988 nxmit++; 1989 } 1990 1991 u64_stats_update_begin(&hw_stats->syncp); 1992 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1993 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1994 u64_stats_update_end(&hw_stats->syncp); 1995 1996 return nxmit; 1997 } 1998 1999 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 2000 struct xdp_buff *xdp, struct net_device *dev) 2001 { 2002 struct mtk_mac *mac = netdev_priv(dev); 2003 struct mtk_hw_stats *hw_stats = mac->hw_stats; 2004 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 2005 struct bpf_prog *prog; 2006 u32 act = XDP_PASS; 2007 2008 rcu_read_lock(); 2009 2010 prog = rcu_dereference(eth->prog); 2011 if (!prog) 2012 goto out; 2013 2014 act = bpf_prog_run_xdp(prog, xdp); 2015 switch (act) { 2016 case XDP_PASS: 2017 count = &hw_stats->xdp_stats.rx_xdp_pass; 2018 goto update_stats; 2019 case XDP_REDIRECT: 2020 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 2021 act = XDP_DROP; 2022 break; 2023 } 2024 2025 count = &hw_stats->xdp_stats.rx_xdp_redirect; 2026 goto update_stats; 2027 case XDP_TX: { 2028 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2029 2030 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 2031 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 2032 act = XDP_DROP; 2033 break; 2034 } 2035 2036 count = &hw_stats->xdp_stats.rx_xdp_tx; 2037 goto update_stats; 2038 } 2039 default: 2040 bpf_warn_invalid_xdp_action(dev, prog, act); 2041 fallthrough; 2042 case XDP_ABORTED: 2043 trace_xdp_exception(dev, prog, act); 2044 fallthrough; 2045 case XDP_DROP: 2046 break; 2047 } 2048 2049 page_pool_put_full_page(ring->page_pool, 2050 virt_to_head_page(xdp->data), true); 2051 2052 update_stats: 2053 u64_stats_update_begin(&hw_stats->syncp); 2054 *count = *count + 1; 2055 u64_stats_update_end(&hw_stats->syncp); 2056 out: 2057 rcu_read_unlock(); 2058 2059 return act; 2060 } 2061 2062 static int mtk_poll_rx(struct napi_struct *napi, int budget, 2063 struct mtk_eth *eth) 2064 { 2065 struct dim_sample dim_sample = {}; 2066 struct mtk_rx_ring *ring; 2067 bool xdp_flush = false; 2068 int idx; 2069 struct sk_buff *skb; 2070 u64 addr64 = 0; 2071 u8 *data, *new_data; 2072 struct mtk_rx_dma_v2 *rxd, trxd; 2073 int done = 0, bytes = 0; 2074 dma_addr_t dma_addr = DMA_MAPPING_ERROR; 2075 int ppe_idx = 0; 2076 2077 while (done < budget) { 2078 unsigned int pktlen, *rxdcsum; 2079 struct net_device *netdev; 2080 u32 hash, reason; 2081 int mac = 0; 2082 2083 ring = mtk_get_rx_ring(eth); 2084 if (unlikely(!ring)) 2085 goto rx_done; 2086 2087 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 2088 rxd = ring->dma + idx * eth->soc->rx.desc_size; 2089 data = ring->data[idx]; 2090 2091 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 2092 break; 2093 2094 /* find out which mac the packet come from. values start at 1 */ 2095 if (mtk_is_netsys_v3_or_greater(eth)) { 2096 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); 2097 2098 switch (val) { 2099 case PSE_GDM1_PORT: 2100 case PSE_GDM2_PORT: 2101 mac = val - 1; 2102 break; 2103 case PSE_GDM3_PORT: 2104 mac = MTK_GMAC3_ID; 2105 break; 2106 default: 2107 break; 2108 } 2109 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 2110 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { 2111 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 2112 } 2113 2114 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || 2115 !eth->netdev[mac])) 2116 goto release_desc; 2117 2118 netdev = eth->netdev[mac]; 2119 ppe_idx = eth->mac[mac]->ppe_idx; 2120 2121 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 2122 goto release_desc; 2123 2124 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 2125 2126 /* alloc new buffer */ 2127 if (ring->page_pool) { 2128 struct page *page = virt_to_head_page(data); 2129 struct xdp_buff xdp; 2130 u32 ret, metasize; 2131 2132 new_data = mtk_page_pool_get_buff(ring->page_pool, 2133 &dma_addr, 2134 GFP_ATOMIC); 2135 if (unlikely(!new_data)) { 2136 netdev->stats.rx_dropped++; 2137 goto release_desc; 2138 } 2139 2140 dma_sync_single_for_cpu(eth->dma_dev, 2141 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 2142 pktlen, page_pool_get_dma_dir(ring->page_pool)); 2143 2144 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 2145 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 2146 true); 2147 xdp_buff_clear_frags_flag(&xdp); 2148 2149 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 2150 if (ret == XDP_REDIRECT) 2151 xdp_flush = true; 2152 2153 if (ret != XDP_PASS) 2154 goto skip_rx; 2155 2156 skb = build_skb(data, PAGE_SIZE); 2157 if (unlikely(!skb)) { 2158 page_pool_put_full_page(ring->page_pool, 2159 page, true); 2160 netdev->stats.rx_dropped++; 2161 goto skip_rx; 2162 } 2163 2164 skb_reserve(skb, xdp.data - xdp.data_hard_start); 2165 skb_put(skb, xdp.data_end - xdp.data); 2166 metasize = xdp.data - xdp.data_meta; 2167 if (metasize) 2168 skb_metadata_set(skb, metasize); 2169 skb_mark_for_recycle(skb); 2170 } else { 2171 if (ring->frag_size <= PAGE_SIZE) 2172 new_data = napi_alloc_frag(ring->frag_size); 2173 else 2174 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2175 2176 if (unlikely(!new_data)) { 2177 netdev->stats.rx_dropped++; 2178 goto release_desc; 2179 } 2180 2181 dma_addr = dma_map_single(eth->dma_dev, 2182 new_data + NET_SKB_PAD + eth->ip_align, 2183 ring->buf_size, DMA_FROM_DEVICE); 2184 if (unlikely(dma_mapping_error(eth->dma_dev, 2185 dma_addr))) { 2186 skb_free_frag(new_data); 2187 netdev->stats.rx_dropped++; 2188 goto release_desc; 2189 } 2190 2191 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2192 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2); 2193 2194 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), 2195 ring->buf_size, DMA_FROM_DEVICE); 2196 2197 skb = build_skb(data, ring->frag_size); 2198 if (unlikely(!skb)) { 2199 netdev->stats.rx_dropped++; 2200 skb_free_frag(data); 2201 goto skip_rx; 2202 } 2203 2204 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2205 skb_put(skb, pktlen); 2206 } 2207 2208 skb->dev = netdev; 2209 bytes += skb->len; 2210 2211 if (mtk_is_netsys_v3_or_greater(eth)) { 2212 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2213 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2214 if (hash != MTK_RXD5_FOE_ENTRY) 2215 skb_set_hash(skb, jhash_1word(hash, 0), 2216 PKT_HASH_TYPE_L4); 2217 rxdcsum = &trxd.rxd3; 2218 } else { 2219 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2220 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2221 if (hash != MTK_RXD4_FOE_ENTRY) 2222 skb_set_hash(skb, jhash_1word(hash, 0), 2223 PKT_HASH_TYPE_L4); 2224 rxdcsum = &trxd.rxd4; 2225 } 2226 2227 if (*rxdcsum & eth->soc->rx.dma_l4_valid) 2228 skb->ip_summed = CHECKSUM_UNNECESSARY; 2229 else 2230 skb_checksum_none_assert(skb); 2231 skb->protocol = eth_type_trans(skb, netdev); 2232 2233 /* When using VLAN untagging in combination with DSA, the 2234 * hardware treats the MTK special tag as a VLAN and untags it. 2235 */ 2236 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && 2237 netdev_uses_dsa(netdev)) { 2238 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 2239 2240 if (port < ARRAY_SIZE(eth->dsa_meta) && 2241 eth->dsa_meta[port]) 2242 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2243 } 2244 2245 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2246 mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash); 2247 2248 skb_record_rx_queue(skb, 0); 2249 napi_gro_receive(napi, skb); 2250 2251 skip_rx: 2252 ring->data[idx] = new_data; 2253 rxd->rxd1 = (unsigned int)dma_addr; 2254 release_desc: 2255 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2256 rxd->rxd2 = RX_DMA_LSO; 2257 else 2258 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2259 2260 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA) && 2261 likely(dma_addr != DMA_MAPPING_ERROR)) 2262 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2263 2264 ring->calc_idx = idx; 2265 done++; 2266 } 2267 2268 rx_done: 2269 if (done) { 2270 /* make sure that all changes to the dma ring are flushed before 2271 * we continue 2272 */ 2273 wmb(); 2274 mtk_update_rx_cpu_idx(eth); 2275 } 2276 2277 eth->rx_packets += done; 2278 eth->rx_bytes += bytes; 2279 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2280 &dim_sample); 2281 net_dim(ð->rx_dim, &dim_sample); 2282 2283 if (xdp_flush) 2284 xdp_do_flush(); 2285 2286 return done; 2287 } 2288 2289 struct mtk_poll_state { 2290 struct netdev_queue *txq; 2291 unsigned int total; 2292 unsigned int done; 2293 unsigned int bytes; 2294 }; 2295 2296 static void 2297 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2298 struct sk_buff *skb) 2299 { 2300 struct netdev_queue *txq; 2301 struct net_device *dev; 2302 unsigned int bytes = skb->len; 2303 2304 state->total++; 2305 eth->tx_packets++; 2306 eth->tx_bytes += bytes; 2307 2308 dev = eth->netdev[mac]; 2309 if (!dev) 2310 return; 2311 2312 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2313 if (state->txq == txq) { 2314 state->done++; 2315 state->bytes += bytes; 2316 return; 2317 } 2318 2319 if (state->txq) 2320 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2321 2322 state->txq = txq; 2323 state->done = 1; 2324 state->bytes = bytes; 2325 } 2326 2327 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2328 struct mtk_poll_state *state) 2329 { 2330 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2331 struct mtk_tx_ring *ring = ð->tx_ring; 2332 struct mtk_tx_buf *tx_buf; 2333 struct xdp_frame_bulk bq; 2334 struct mtk_tx_dma *desc; 2335 u32 cpu, dma; 2336 2337 cpu = ring->last_free_ptr; 2338 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2339 2340 desc = mtk_qdma_phys_to_virt(ring, cpu); 2341 xdp_frame_bulk_init(&bq); 2342 2343 while ((cpu != dma) && budget) { 2344 u32 next_cpu = desc->txd2; 2345 2346 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2347 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2348 break; 2349 2350 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2351 eth->soc->tx.desc_size); 2352 if (!tx_buf->data) 2353 break; 2354 2355 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2356 if (tx_buf->type == MTK_TYPE_SKB) 2357 mtk_poll_tx_done(eth, state, tx_buf->mac_id, 2358 tx_buf->data); 2359 2360 budget--; 2361 } 2362 mtk_tx_unmap(eth, tx_buf, &bq, true); 2363 2364 ring->last_free = desc; 2365 atomic_inc(&ring->free_count); 2366 2367 cpu = next_cpu; 2368 } 2369 xdp_flush_frame_bulk(&bq); 2370 2371 ring->last_free_ptr = cpu; 2372 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2373 2374 return budget; 2375 } 2376 2377 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2378 struct mtk_poll_state *state) 2379 { 2380 struct mtk_tx_ring *ring = ð->tx_ring; 2381 struct mtk_tx_buf *tx_buf; 2382 struct xdp_frame_bulk bq; 2383 struct mtk_tx_dma *desc; 2384 u32 cpu, dma; 2385 2386 cpu = ring->cpu_idx; 2387 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2388 xdp_frame_bulk_init(&bq); 2389 2390 while ((cpu != dma) && budget) { 2391 tx_buf = &ring->buf[cpu]; 2392 if (!tx_buf->data) 2393 break; 2394 2395 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2396 if (tx_buf->type == MTK_TYPE_SKB) 2397 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2398 budget--; 2399 } 2400 mtk_tx_unmap(eth, tx_buf, &bq, true); 2401 2402 desc = ring->dma + cpu * eth->soc->tx.desc_size; 2403 ring->last_free = desc; 2404 atomic_inc(&ring->free_count); 2405 2406 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2407 } 2408 xdp_flush_frame_bulk(&bq); 2409 2410 ring->cpu_idx = cpu; 2411 2412 return budget; 2413 } 2414 2415 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2416 { 2417 struct mtk_tx_ring *ring = ð->tx_ring; 2418 struct dim_sample dim_sample = {}; 2419 struct mtk_poll_state state = {}; 2420 2421 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2422 budget = mtk_poll_tx_qdma(eth, budget, &state); 2423 else 2424 budget = mtk_poll_tx_pdma(eth, budget, &state); 2425 2426 if (state.txq) 2427 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2428 2429 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2430 &dim_sample); 2431 net_dim(ð->tx_dim, &dim_sample); 2432 2433 if (mtk_queue_stopped(eth) && 2434 (atomic_read(&ring->free_count) > ring->thresh)) 2435 mtk_wake_queue(eth); 2436 2437 return state.total; 2438 } 2439 2440 static void mtk_handle_status_irq(struct mtk_eth *eth) 2441 { 2442 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2443 2444 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2445 mtk_stats_update(eth); 2446 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2447 MTK_INT_STATUS2); 2448 } 2449 } 2450 2451 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2452 { 2453 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2454 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2455 int tx_done = 0; 2456 2457 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2458 mtk_handle_status_irq(eth); 2459 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2460 tx_done = mtk_poll_tx(eth, budget); 2461 2462 if (unlikely(netif_msg_intr(eth))) { 2463 dev_info(eth->dev, 2464 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2465 mtk_r32(eth, reg_map->tx_irq_status), 2466 mtk_r32(eth, reg_map->tx_irq_mask)); 2467 } 2468 2469 if (tx_done == budget) 2470 return budget; 2471 2472 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2473 return budget; 2474 2475 if (napi_complete_done(napi, tx_done)) 2476 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2477 2478 return tx_done; 2479 } 2480 2481 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2482 { 2483 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2484 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2485 int rx_done_total = 0; 2486 2487 mtk_handle_status_irq(eth); 2488 2489 do { 2490 int rx_done; 2491 2492 mtk_w32(eth, eth->soc->rx.irq_done_mask, 2493 reg_map->pdma.irq_status); 2494 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2495 rx_done_total += rx_done; 2496 2497 if (unlikely(netif_msg_intr(eth))) { 2498 dev_info(eth->dev, 2499 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2500 mtk_r32(eth, reg_map->pdma.irq_status), 2501 mtk_r32(eth, reg_map->pdma.irq_mask)); 2502 } 2503 2504 if (rx_done_total == budget) 2505 return budget; 2506 2507 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2508 eth->soc->rx.irq_done_mask); 2509 2510 if (napi_complete_done(napi, rx_done_total)) 2511 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); 2512 2513 return rx_done_total; 2514 } 2515 2516 static int mtk_tx_alloc(struct mtk_eth *eth) 2517 { 2518 const struct mtk_soc_data *soc = eth->soc; 2519 struct mtk_tx_ring *ring = ð->tx_ring; 2520 int i, sz = soc->tx.desc_size; 2521 struct mtk_tx_dma_v2 *txd; 2522 int ring_size; 2523 u32 ofs, val; 2524 2525 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2526 ring_size = MTK_QDMA_RING_SIZE; 2527 else 2528 ring_size = soc->tx.dma_size; 2529 2530 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2531 GFP_KERNEL); 2532 if (!ring->buf) 2533 goto no_tx_mem; 2534 2535 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { 2536 ring->dma = eth->sram_base + soc->tx.fq_dma_size * sz; 2537 ring->phys = eth->phy_scratch_ring + soc->tx.fq_dma_size * (dma_addr_t)sz; 2538 } else { 2539 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2540 &ring->phys, GFP_KERNEL); 2541 } 2542 2543 if (!ring->dma) 2544 goto no_tx_mem; 2545 2546 for (i = 0; i < ring_size; i++) { 2547 int next = (i + 1) % ring_size; 2548 u32 next_ptr = ring->phys + next * sz; 2549 2550 txd = ring->dma + i * sz; 2551 txd->txd2 = next_ptr; 2552 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2553 txd->txd4 = 0; 2554 if (mtk_is_netsys_v2_or_greater(eth)) { 2555 txd->txd5 = 0; 2556 txd->txd6 = 0; 2557 txd->txd7 = 0; 2558 txd->txd8 = 0; 2559 } 2560 } 2561 2562 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2563 * only as the framework. The real HW descriptors are the PDMA 2564 * descriptors in ring->dma_pdma. 2565 */ 2566 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2567 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2568 &ring->phys_pdma, GFP_KERNEL); 2569 if (!ring->dma_pdma) 2570 goto no_tx_mem; 2571 2572 for (i = 0; i < ring_size; i++) { 2573 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2574 ring->dma_pdma[i].txd4 = 0; 2575 } 2576 } 2577 2578 ring->dma_size = ring_size; 2579 atomic_set(&ring->free_count, ring_size - 2); 2580 ring->next_free = ring->dma; 2581 ring->last_free = (void *)txd; 2582 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2583 ring->thresh = MAX_SKB_FRAGS; 2584 2585 /* make sure that all changes to the dma ring are flushed before we 2586 * continue 2587 */ 2588 wmb(); 2589 2590 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2591 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2592 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2593 mtk_w32(eth, 2594 ring->phys + ((ring_size - 1) * sz), 2595 soc->reg_map->qdma.crx_ptr); 2596 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2597 2598 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2599 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2600 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2601 2602 val = MTK_QTX_SCH_MIN_RATE_EN | 2603 /* minimum: 10 Mbps */ 2604 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2605 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2606 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2607 if (mtk_is_netsys_v1(eth)) 2608 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2609 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2610 ofs += MTK_QTX_OFFSET; 2611 } 2612 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2613 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2614 if (mtk_is_netsys_v2_or_greater(eth)) 2615 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2616 } else { 2617 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2618 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2619 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2620 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2621 } 2622 2623 return 0; 2624 2625 no_tx_mem: 2626 return -ENOMEM; 2627 } 2628 2629 static void mtk_tx_clean(struct mtk_eth *eth) 2630 { 2631 const struct mtk_soc_data *soc = eth->soc; 2632 struct mtk_tx_ring *ring = ð->tx_ring; 2633 int i; 2634 2635 if (ring->buf) { 2636 for (i = 0; i < ring->dma_size; i++) 2637 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2638 kfree(ring->buf); 2639 ring->buf = NULL; 2640 } 2641 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { 2642 dma_free_coherent(eth->dma_dev, 2643 ring->dma_size * soc->tx.desc_size, 2644 ring->dma, ring->phys); 2645 ring->dma = NULL; 2646 } 2647 2648 if (ring->dma_pdma) { 2649 dma_free_coherent(eth->dma_dev, 2650 ring->dma_size * soc->tx.desc_size, 2651 ring->dma_pdma, ring->phys_pdma); 2652 ring->dma_pdma = NULL; 2653 } 2654 } 2655 2656 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2657 { 2658 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2659 const struct mtk_soc_data *soc = eth->soc; 2660 struct mtk_rx_ring *ring; 2661 int rx_data_len, rx_dma_size, tx_ring_size; 2662 int i; 2663 2664 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2665 tx_ring_size = MTK_QDMA_RING_SIZE; 2666 else 2667 tx_ring_size = soc->tx.dma_size; 2668 2669 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2670 if (ring_no) 2671 return -EINVAL; 2672 ring = ð->rx_ring_qdma; 2673 } else { 2674 ring = ð->rx_ring[ring_no]; 2675 } 2676 2677 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2678 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2679 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2680 } else { 2681 rx_data_len = ETH_DATA_LEN; 2682 rx_dma_size = soc->rx.dma_size; 2683 } 2684 2685 ring->frag_size = mtk_max_frag_size(rx_data_len); 2686 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2687 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2688 GFP_KERNEL); 2689 if (!ring->data) 2690 return -ENOMEM; 2691 2692 if (mtk_page_pool_enabled(eth)) { 2693 struct page_pool *pp; 2694 2695 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2696 rx_dma_size); 2697 if (IS_ERR(pp)) 2698 return PTR_ERR(pp); 2699 2700 ring->page_pool = pp; 2701 } 2702 2703 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || 2704 rx_flag != MTK_RX_FLAGS_NORMAL) { 2705 ring->dma = dma_alloc_coherent(eth->dma_dev, 2706 rx_dma_size * eth->soc->rx.desc_size, 2707 &ring->phys, GFP_KERNEL); 2708 } else { 2709 struct mtk_tx_ring *tx_ring = ð->tx_ring; 2710 2711 ring->dma = tx_ring->dma + tx_ring_size * 2712 eth->soc->tx.desc_size * (ring_no + 1); 2713 ring->phys = tx_ring->phys + tx_ring_size * 2714 eth->soc->tx.desc_size * (ring_no + 1); 2715 } 2716 2717 if (!ring->dma) 2718 return -ENOMEM; 2719 2720 for (i = 0; i < rx_dma_size; i++) { 2721 struct mtk_rx_dma_v2 *rxd; 2722 dma_addr_t dma_addr; 2723 void *data; 2724 2725 rxd = ring->dma + i * eth->soc->rx.desc_size; 2726 if (ring->page_pool) { 2727 data = mtk_page_pool_get_buff(ring->page_pool, 2728 &dma_addr, GFP_KERNEL); 2729 if (!data) 2730 return -ENOMEM; 2731 } else { 2732 if (ring->frag_size <= PAGE_SIZE) 2733 data = netdev_alloc_frag(ring->frag_size); 2734 else 2735 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2736 2737 if (!data) 2738 return -ENOMEM; 2739 2740 dma_addr = dma_map_single(eth->dma_dev, 2741 data + NET_SKB_PAD + eth->ip_align, 2742 ring->buf_size, DMA_FROM_DEVICE); 2743 if (unlikely(dma_mapping_error(eth->dma_dev, 2744 dma_addr))) { 2745 skb_free_frag(data); 2746 return -ENOMEM; 2747 } 2748 } 2749 rxd->rxd1 = (unsigned int)dma_addr; 2750 ring->data[i] = data; 2751 2752 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2753 rxd->rxd2 = RX_DMA_LSO; 2754 else 2755 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2756 2757 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2758 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2759 2760 rxd->rxd3 = 0; 2761 rxd->rxd4 = 0; 2762 if (mtk_is_netsys_v3_or_greater(eth)) { 2763 rxd->rxd5 = 0; 2764 rxd->rxd6 = 0; 2765 rxd->rxd7 = 0; 2766 rxd->rxd8 = 0; 2767 } 2768 } 2769 2770 ring->dma_size = rx_dma_size; 2771 ring->calc_idx_update = false; 2772 ring->calc_idx = rx_dma_size - 1; 2773 if (rx_flag == MTK_RX_FLAGS_QDMA) 2774 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2775 ring_no * MTK_QRX_OFFSET; 2776 else 2777 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2778 ring_no * MTK_QRX_OFFSET; 2779 /* make sure that all changes to the dma ring are flushed before we 2780 * continue 2781 */ 2782 wmb(); 2783 2784 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2785 mtk_w32(eth, ring->phys, 2786 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2787 mtk_w32(eth, rx_dma_size, 2788 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2789 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2790 reg_map->qdma.rst_idx); 2791 } else { 2792 mtk_w32(eth, ring->phys, 2793 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2794 mtk_w32(eth, rx_dma_size, 2795 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2796 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2797 reg_map->pdma.rst_idx); 2798 } 2799 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2800 2801 return 0; 2802 } 2803 2804 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) 2805 { 2806 u64 addr64 = 0; 2807 int i; 2808 2809 if (ring->data && ring->dma) { 2810 for (i = 0; i < ring->dma_size; i++) { 2811 struct mtk_rx_dma *rxd; 2812 2813 if (!ring->data[i]) 2814 continue; 2815 2816 rxd = ring->dma + i * eth->soc->rx.desc_size; 2817 if (!rxd->rxd1) 2818 continue; 2819 2820 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2821 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); 2822 2823 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), 2824 ring->buf_size, DMA_FROM_DEVICE); 2825 mtk_rx_put_buff(ring, ring->data[i], false); 2826 } 2827 kfree(ring->data); 2828 ring->data = NULL; 2829 } 2830 2831 if (!in_sram && ring->dma) { 2832 dma_free_coherent(eth->dma_dev, 2833 ring->dma_size * eth->soc->rx.desc_size, 2834 ring->dma, ring->phys); 2835 ring->dma = NULL; 2836 } 2837 2838 if (ring->page_pool) { 2839 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2840 xdp_rxq_info_unreg(&ring->xdp_q); 2841 page_pool_destroy(ring->page_pool); 2842 ring->page_pool = NULL; 2843 } 2844 } 2845 2846 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2847 { 2848 int i; 2849 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2850 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2851 2852 /* set LRO rings to auto-learn modes */ 2853 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2854 2855 /* validate LRO ring */ 2856 ring_ctrl_dw2 |= MTK_RING_VLD; 2857 2858 /* set AGE timer (unit: 20us) */ 2859 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2860 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2861 2862 /* set max AGG timer (unit: 20us) */ 2863 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2864 2865 /* set max LRO AGG count */ 2866 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2867 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2868 2869 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2870 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2871 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2872 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2873 } 2874 2875 /* IPv4 checksum update enable */ 2876 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2877 2878 /* switch priority comparison to packet count mode */ 2879 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2880 2881 /* bandwidth threshold setting */ 2882 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2883 2884 /* auto-learn score delta setting */ 2885 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2886 2887 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2888 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2889 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2890 2891 /* set HW LRO mode & the max aggregation count for rx packets */ 2892 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2893 2894 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2895 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2896 2897 /* enable HW LRO */ 2898 lro_ctrl_dw0 |= MTK_LRO_EN; 2899 2900 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2901 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2902 2903 return 0; 2904 } 2905 2906 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2907 { 2908 int i; 2909 u32 val; 2910 2911 /* relinquish lro rings, flush aggregated packets */ 2912 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2913 2914 /* wait for relinquishments done */ 2915 for (i = 0; i < 10; i++) { 2916 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2917 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2918 msleep(20); 2919 continue; 2920 } 2921 break; 2922 } 2923 2924 /* invalidate lro rings */ 2925 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2926 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2927 2928 /* disable HW LRO */ 2929 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2930 } 2931 2932 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2933 { 2934 u32 reg_val; 2935 2936 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2937 2938 /* invalidate the IP setting */ 2939 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2940 2941 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2942 2943 /* validate the IP setting */ 2944 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2945 } 2946 2947 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2948 { 2949 u32 reg_val; 2950 2951 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2952 2953 /* invalidate the IP setting */ 2954 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2955 2956 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2957 } 2958 2959 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2960 { 2961 int cnt = 0; 2962 int i; 2963 2964 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2965 if (mac->hwlro_ip[i]) 2966 cnt++; 2967 } 2968 2969 return cnt; 2970 } 2971 2972 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2973 struct ethtool_rxnfc *cmd) 2974 { 2975 struct ethtool_rx_flow_spec *fsp = 2976 (struct ethtool_rx_flow_spec *)&cmd->fs; 2977 struct mtk_mac *mac = netdev_priv(dev); 2978 struct mtk_eth *eth = mac->hw; 2979 int hwlro_idx; 2980 2981 if ((fsp->flow_type != TCP_V4_FLOW) || 2982 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2983 (fsp->location > 1)) 2984 return -EINVAL; 2985 2986 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2987 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2988 2989 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2990 2991 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2992 2993 return 0; 2994 } 2995 2996 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2997 struct ethtool_rxnfc *cmd) 2998 { 2999 struct ethtool_rx_flow_spec *fsp = 3000 (struct ethtool_rx_flow_spec *)&cmd->fs; 3001 struct mtk_mac *mac = netdev_priv(dev); 3002 struct mtk_eth *eth = mac->hw; 3003 int hwlro_idx; 3004 3005 if (fsp->location > 1) 3006 return -EINVAL; 3007 3008 mac->hwlro_ip[fsp->location] = 0; 3009 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 3010 3011 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3012 3013 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 3014 3015 return 0; 3016 } 3017 3018 static void mtk_hwlro_netdev_disable(struct net_device *dev) 3019 { 3020 struct mtk_mac *mac = netdev_priv(dev); 3021 struct mtk_eth *eth = mac->hw; 3022 int i, hwlro_idx; 3023 3024 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 3025 mac->hwlro_ip[i] = 0; 3026 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 3027 3028 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 3029 } 3030 3031 mac->hwlro_ip_cnt = 0; 3032 } 3033 3034 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 3035 struct ethtool_rxnfc *cmd) 3036 { 3037 struct mtk_mac *mac = netdev_priv(dev); 3038 struct ethtool_rx_flow_spec *fsp = 3039 (struct ethtool_rx_flow_spec *)&cmd->fs; 3040 3041 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 3042 return -EINVAL; 3043 3044 /* only tcp dst ipv4 is meaningful, others are meaningless */ 3045 fsp->flow_type = TCP_V4_FLOW; 3046 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 3047 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 3048 3049 fsp->h_u.tcp_ip4_spec.ip4src = 0; 3050 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 3051 fsp->h_u.tcp_ip4_spec.psrc = 0; 3052 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 3053 fsp->h_u.tcp_ip4_spec.pdst = 0; 3054 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 3055 fsp->h_u.tcp_ip4_spec.tos = 0; 3056 fsp->m_u.tcp_ip4_spec.tos = 0xff; 3057 3058 return 0; 3059 } 3060 3061 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 3062 struct ethtool_rxnfc *cmd, 3063 u32 *rule_locs) 3064 { 3065 struct mtk_mac *mac = netdev_priv(dev); 3066 int cnt = 0; 3067 int i; 3068 3069 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 3070 if (cnt == cmd->rule_cnt) 3071 return -EMSGSIZE; 3072 3073 if (mac->hwlro_ip[i]) { 3074 rule_locs[cnt] = i; 3075 cnt++; 3076 } 3077 } 3078 3079 cmd->rule_cnt = cnt; 3080 3081 return 0; 3082 } 3083 3084 static netdev_features_t mtk_fix_features(struct net_device *dev, 3085 netdev_features_t features) 3086 { 3087 if (!(features & NETIF_F_LRO)) { 3088 struct mtk_mac *mac = netdev_priv(dev); 3089 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3090 3091 if (ip_cnt) { 3092 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 3093 3094 features |= NETIF_F_LRO; 3095 } 3096 } 3097 3098 return features; 3099 } 3100 3101 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 3102 { 3103 netdev_features_t diff = dev->features ^ features; 3104 3105 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 3106 mtk_hwlro_netdev_disable(dev); 3107 3108 return 0; 3109 } 3110 3111 /* wait for DMA to finish whatever it is doing before we start using it again */ 3112 static int mtk_dma_busy_wait(struct mtk_eth *eth) 3113 { 3114 unsigned int reg; 3115 int ret; 3116 u32 val; 3117 3118 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3119 reg = eth->soc->reg_map->qdma.glo_cfg; 3120 else 3121 reg = eth->soc->reg_map->pdma.glo_cfg; 3122 3123 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 3124 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 3125 5, MTK_DMA_BUSY_TIMEOUT_US); 3126 if (ret) 3127 dev_err(eth->dev, "DMA init timeout\n"); 3128 3129 return ret; 3130 } 3131 3132 static int mtk_dma_init(struct mtk_eth *eth) 3133 { 3134 int err; 3135 u32 i; 3136 3137 if (mtk_dma_busy_wait(eth)) 3138 return -EBUSY; 3139 3140 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3141 /* QDMA needs scratch memory for internal reordering of the 3142 * descriptors 3143 */ 3144 err = mtk_init_fq_dma(eth); 3145 if (err) 3146 return err; 3147 } 3148 3149 err = mtk_tx_alloc(eth); 3150 if (err) 3151 return err; 3152 3153 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3154 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 3155 if (err) 3156 return err; 3157 } 3158 3159 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 3160 if (err) 3161 return err; 3162 3163 if (eth->hwlro) { 3164 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 3165 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 3166 if (err) 3167 return err; 3168 } 3169 err = mtk_hwlro_rx_init(eth); 3170 if (err) 3171 return err; 3172 } 3173 3174 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3175 /* Enable random early drop and set drop threshold 3176 * automatically 3177 */ 3178 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 3179 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 3180 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 3181 } 3182 3183 return 0; 3184 } 3185 3186 static void mtk_dma_free(struct mtk_eth *eth) 3187 { 3188 const struct mtk_soc_data *soc = eth->soc; 3189 int i; 3190 3191 for (i = 0; i < MTK_MAX_DEVS; i++) 3192 if (eth->netdev[i]) 3193 netdev_reset_queue(eth->netdev[i]); 3194 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { 3195 dma_free_coherent(eth->dma_dev, 3196 MTK_QDMA_RING_SIZE * soc->tx.desc_size, 3197 eth->scratch_ring, eth->phy_scratch_ring); 3198 eth->scratch_ring = NULL; 3199 eth->phy_scratch_ring = 0; 3200 } 3201 mtk_tx_clean(eth); 3202 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); 3203 mtk_rx_clean(eth, ð->rx_ring_qdma, false); 3204 3205 if (eth->hwlro) { 3206 mtk_hwlro_rx_uninit(eth); 3207 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3208 mtk_rx_clean(eth, ð->rx_ring[i], false); 3209 } 3210 3211 for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) { 3212 kfree(eth->scratch_head[i]); 3213 eth->scratch_head[i] = NULL; 3214 } 3215 } 3216 3217 static bool mtk_hw_reset_check(struct mtk_eth *eth) 3218 { 3219 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3220 3221 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3222 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3223 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3224 } 3225 3226 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3227 { 3228 struct mtk_mac *mac = netdev_priv(dev); 3229 struct mtk_eth *eth = mac->hw; 3230 3231 if (test_bit(MTK_RESETTING, ð->state)) 3232 return; 3233 3234 if (!mtk_hw_reset_check(eth)) 3235 return; 3236 3237 eth->netdev[mac->id]->stats.tx_errors++; 3238 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3239 3240 schedule_work(ð->pending_work); 3241 } 3242 3243 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3244 { 3245 struct mtk_eth *eth = _eth; 3246 3247 eth->rx_events++; 3248 if (likely(napi_schedule_prep(ð->rx_napi))) { 3249 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3250 __napi_schedule(ð->rx_napi); 3251 } 3252 3253 return IRQ_HANDLED; 3254 } 3255 3256 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3257 { 3258 struct mtk_eth *eth = _eth; 3259 3260 eth->tx_events++; 3261 if (likely(napi_schedule_prep(ð->tx_napi))) { 3262 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3263 __napi_schedule(ð->tx_napi); 3264 } 3265 3266 return IRQ_HANDLED; 3267 } 3268 3269 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3270 { 3271 struct mtk_eth *eth = _eth; 3272 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3273 3274 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3275 eth->soc->rx.irq_done_mask) { 3276 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3277 eth->soc->rx.irq_done_mask) 3278 mtk_handle_irq_rx(irq, _eth); 3279 } 3280 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3281 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3282 mtk_handle_irq_tx(irq, _eth); 3283 } 3284 3285 return IRQ_HANDLED; 3286 } 3287 3288 #ifdef CONFIG_NET_POLL_CONTROLLER 3289 static void mtk_poll_controller(struct net_device *dev) 3290 { 3291 struct mtk_mac *mac = netdev_priv(dev); 3292 struct mtk_eth *eth = mac->hw; 3293 3294 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3295 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3296 mtk_handle_irq_rx(eth->irq[2], dev); 3297 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3298 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); 3299 } 3300 #endif 3301 3302 static int mtk_start_dma(struct mtk_eth *eth) 3303 { 3304 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3305 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3306 int err; 3307 3308 err = mtk_dma_init(eth); 3309 if (err) { 3310 mtk_dma_free(eth); 3311 return err; 3312 } 3313 3314 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3315 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3316 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3317 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3318 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3319 3320 if (mtk_is_netsys_v2_or_greater(eth)) 3321 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3322 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3323 MTK_CHK_DDONE_EN; 3324 else 3325 val |= MTK_RX_BT_32DWORDS; 3326 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3327 3328 mtk_w32(eth, 3329 MTK_RX_DMA_EN | rx_2b_offset | 3330 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3331 reg_map->pdma.glo_cfg); 3332 } else { 3333 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3334 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3335 reg_map->pdma.glo_cfg); 3336 } 3337 3338 return 0; 3339 } 3340 3341 static void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config) 3342 { 3343 u32 val; 3344 3345 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3346 return; 3347 3348 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(id)); 3349 3350 /* default setup the forward port to send frame to PDMA */ 3351 val &= ~0xffff; 3352 3353 /* Enable RX checksum */ 3354 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3355 3356 val |= config; 3357 3358 if (eth->netdev[id] && netdev_uses_dsa(eth->netdev[id])) 3359 val |= MTK_GDMA_SPECIAL_TAG; 3360 3361 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(id)); 3362 } 3363 3364 3365 static bool mtk_uses_dsa(struct net_device *dev) 3366 { 3367 #if IS_ENABLED(CONFIG_NET_DSA) 3368 return netdev_uses_dsa(dev) && 3369 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3370 #else 3371 return false; 3372 #endif 3373 } 3374 3375 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3376 { 3377 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3378 struct mtk_eth *eth = mac->hw; 3379 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3380 struct ethtool_link_ksettings s; 3381 struct net_device *ldev; 3382 struct list_head *iter; 3383 struct dsa_port *dp; 3384 3385 if (event != NETDEV_CHANGE) 3386 return NOTIFY_DONE; 3387 3388 netdev_for_each_lower_dev(dev, ldev, iter) { 3389 if (netdev_priv(ldev) == mac) 3390 goto found; 3391 } 3392 3393 return NOTIFY_DONE; 3394 3395 found: 3396 if (!dsa_user_dev_check(dev)) 3397 return NOTIFY_DONE; 3398 3399 if (__ethtool_get_link_ksettings(dev, &s)) 3400 return NOTIFY_DONE; 3401 3402 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3403 return NOTIFY_DONE; 3404 3405 dp = dsa_port_from_netdev(dev); 3406 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3407 return NOTIFY_DONE; 3408 3409 if (mac->speed > 0 && mac->speed <= s.base.speed) 3410 s.base.speed = 0; 3411 3412 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3413 3414 return NOTIFY_DONE; 3415 } 3416 3417 static int mtk_open(struct net_device *dev) 3418 { 3419 struct mtk_mac *mac = netdev_priv(dev); 3420 struct mtk_eth *eth = mac->hw; 3421 struct mtk_mac *target_mac; 3422 int i, err, ppe_num; 3423 3424 ppe_num = eth->soc->ppe_num; 3425 3426 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3427 if (err) { 3428 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3429 err); 3430 return err; 3431 } 3432 3433 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3434 if (!refcount_read(ð->dma_refcnt)) { 3435 const struct mtk_soc_data *soc = eth->soc; 3436 u32 gdm_config; 3437 int i; 3438 3439 err = mtk_start_dma(eth); 3440 if (err) { 3441 phylink_disconnect_phy(mac->phylink); 3442 return err; 3443 } 3444 3445 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3446 mtk_ppe_start(eth->ppe[i]); 3447 3448 for (i = 0; i < MTK_MAX_DEVS; i++) { 3449 if (!eth->netdev[i]) 3450 continue; 3451 3452 target_mac = netdev_priv(eth->netdev[i]); 3453 if (!soc->offload_version) { 3454 target_mac->ppe_idx = 0; 3455 gdm_config = MTK_GDMA_TO_PDMA; 3456 } else if (ppe_num >= 3 && target_mac->id == 2) { 3457 target_mac->ppe_idx = 2; 3458 gdm_config = soc->reg_map->gdma_to_ppe[2]; 3459 } else if (ppe_num >= 2 && target_mac->id == 1) { 3460 target_mac->ppe_idx = 1; 3461 gdm_config = soc->reg_map->gdma_to_ppe[1]; 3462 } else { 3463 target_mac->ppe_idx = 0; 3464 gdm_config = soc->reg_map->gdma_to_ppe[0]; 3465 } 3466 mtk_gdm_config(eth, target_mac->id, gdm_config); 3467 } 3468 /* Reset and enable PSE */ 3469 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3470 mtk_w32(eth, 0, MTK_RST_GL); 3471 3472 napi_enable(ð->tx_napi); 3473 napi_enable(ð->rx_napi); 3474 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3475 mtk_rx_irq_enable(eth, soc->rx.irq_done_mask); 3476 refcount_set(ð->dma_refcnt, 1); 3477 } else { 3478 refcount_inc(ð->dma_refcnt); 3479 } 3480 3481 phylink_start(mac->phylink); 3482 netif_tx_start_all_queues(dev); 3483 3484 if (mtk_is_netsys_v2_or_greater(eth)) 3485 return 0; 3486 3487 if (mtk_uses_dsa(dev) && !eth->prog) { 3488 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3489 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3490 3491 if (md_dst) 3492 continue; 3493 3494 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3495 GFP_KERNEL); 3496 if (!md_dst) 3497 return -ENOMEM; 3498 3499 md_dst->u.port_info.port_id = i; 3500 eth->dsa_meta[i] = md_dst; 3501 } 3502 } else { 3503 /* Hardware DSA untagging and VLAN RX offloading need to be 3504 * disabled if at least one MAC does not use DSA. 3505 */ 3506 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3507 3508 val &= ~MTK_CDMP_STAG_EN; 3509 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3510 3511 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); 3512 } 3513 3514 return 0; 3515 } 3516 3517 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3518 { 3519 u32 val; 3520 int i; 3521 3522 /* stop the dma engine */ 3523 spin_lock_bh(ð->page_lock); 3524 val = mtk_r32(eth, glo_cfg); 3525 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3526 glo_cfg); 3527 spin_unlock_bh(ð->page_lock); 3528 3529 /* wait for dma stop */ 3530 for (i = 0; i < 10; i++) { 3531 val = mtk_r32(eth, glo_cfg); 3532 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3533 msleep(20); 3534 continue; 3535 } 3536 break; 3537 } 3538 } 3539 3540 static int mtk_stop(struct net_device *dev) 3541 { 3542 struct mtk_mac *mac = netdev_priv(dev); 3543 struct mtk_eth *eth = mac->hw; 3544 int i; 3545 3546 phylink_stop(mac->phylink); 3547 3548 netif_tx_disable(dev); 3549 3550 phylink_disconnect_phy(mac->phylink); 3551 3552 /* only shutdown DMA if this is the last user */ 3553 if (!refcount_dec_and_test(ð->dma_refcnt)) 3554 return 0; 3555 3556 for (i = 0; i < MTK_MAX_DEVS; i++) 3557 mtk_gdm_config(eth, i, MTK_GDMA_DROP_ALL); 3558 3559 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3560 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3561 napi_disable(ð->tx_napi); 3562 napi_disable(ð->rx_napi); 3563 3564 cancel_work_sync(ð->rx_dim.work); 3565 cancel_work_sync(ð->tx_dim.work); 3566 3567 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3568 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3569 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3570 3571 mtk_dma_free(eth); 3572 3573 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3574 mtk_ppe_stop(eth->ppe[i]); 3575 3576 return 0; 3577 } 3578 3579 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3580 struct netlink_ext_ack *extack) 3581 { 3582 struct mtk_mac *mac = netdev_priv(dev); 3583 struct mtk_eth *eth = mac->hw; 3584 struct bpf_prog *old_prog; 3585 bool need_update; 3586 3587 if (eth->hwlro) { 3588 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3589 return -EOPNOTSUPP; 3590 } 3591 3592 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3593 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3594 return -EOPNOTSUPP; 3595 } 3596 3597 need_update = !!eth->prog != !!prog; 3598 if (netif_running(dev) && need_update) 3599 mtk_stop(dev); 3600 3601 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3602 if (old_prog) 3603 bpf_prog_put(old_prog); 3604 3605 if (netif_running(dev) && need_update) 3606 return mtk_open(dev); 3607 3608 return 0; 3609 } 3610 3611 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3612 { 3613 switch (xdp->command) { 3614 case XDP_SETUP_PROG: 3615 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3616 default: 3617 return -EINVAL; 3618 } 3619 } 3620 3621 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3622 { 3623 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3624 reset_bits, 3625 reset_bits); 3626 3627 usleep_range(1000, 1100); 3628 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3629 reset_bits, 3630 ~reset_bits); 3631 mdelay(10); 3632 } 3633 3634 static void mtk_clk_disable(struct mtk_eth *eth) 3635 { 3636 int clk; 3637 3638 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3639 clk_disable_unprepare(eth->clks[clk]); 3640 } 3641 3642 static int mtk_clk_enable(struct mtk_eth *eth) 3643 { 3644 int clk, ret; 3645 3646 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3647 ret = clk_prepare_enable(eth->clks[clk]); 3648 if (ret) 3649 goto err_disable_clks; 3650 } 3651 3652 return 0; 3653 3654 err_disable_clks: 3655 while (--clk >= 0) 3656 clk_disable_unprepare(eth->clks[clk]); 3657 3658 return ret; 3659 } 3660 3661 static void mtk_dim_rx(struct work_struct *work) 3662 { 3663 struct dim *dim = container_of(work, struct dim, work); 3664 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3665 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3666 struct dim_cq_moder cur_profile; 3667 u32 val, cur; 3668 3669 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3670 dim->profile_ix); 3671 spin_lock_bh(ð->dim_lock); 3672 3673 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3674 val &= MTK_PDMA_DELAY_TX_MASK; 3675 val |= MTK_PDMA_DELAY_RX_EN; 3676 3677 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3678 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3679 3680 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3681 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3682 3683 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3684 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3685 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3686 3687 spin_unlock_bh(ð->dim_lock); 3688 3689 dim->state = DIM_START_MEASURE; 3690 } 3691 3692 static void mtk_dim_tx(struct work_struct *work) 3693 { 3694 struct dim *dim = container_of(work, struct dim, work); 3695 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3696 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3697 struct dim_cq_moder cur_profile; 3698 u32 val, cur; 3699 3700 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3701 dim->profile_ix); 3702 spin_lock_bh(ð->dim_lock); 3703 3704 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3705 val &= MTK_PDMA_DELAY_RX_MASK; 3706 val |= MTK_PDMA_DELAY_TX_EN; 3707 3708 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3709 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3710 3711 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3712 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3713 3714 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3715 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3716 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3717 3718 spin_unlock_bh(ð->dim_lock); 3719 3720 dim->state = DIM_START_MEASURE; 3721 } 3722 3723 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3724 { 3725 struct mtk_eth *eth = mac->hw; 3726 u32 mcr_cur, mcr_new; 3727 3728 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3729 return; 3730 3731 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3732 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3733 3734 if (val <= 1518) 3735 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3736 else if (val <= 1536) 3737 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3738 else if (val <= 1552) 3739 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3740 else 3741 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3742 3743 if (mcr_new != mcr_cur) 3744 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3745 } 3746 3747 static void mtk_hw_reset(struct mtk_eth *eth) 3748 { 3749 u32 val; 3750 3751 if (mtk_is_netsys_v2_or_greater(eth)) 3752 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3753 3754 if (mtk_is_netsys_v3_or_greater(eth)) { 3755 val = RSTCTRL_PPE0_V3; 3756 3757 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3758 val |= RSTCTRL_PPE1_V3; 3759 3760 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3761 val |= RSTCTRL_PPE2; 3762 3763 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3764 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3765 val = RSTCTRL_PPE0_V2; 3766 3767 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3768 val |= RSTCTRL_PPE1; 3769 } else { 3770 val = RSTCTRL_PPE0; 3771 } 3772 3773 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3774 3775 if (mtk_is_netsys_v3_or_greater(eth)) 3776 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3777 0x6f8ff); 3778 else if (mtk_is_netsys_v2_or_greater(eth)) 3779 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3780 0x3ffffff); 3781 } 3782 3783 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3784 { 3785 u32 val; 3786 3787 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3788 return val; 3789 } 3790 3791 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3792 { 3793 u32 rst_mask, val; 3794 3795 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3796 RSTCTRL_FE); 3797 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3798 val & RSTCTRL_FE, 1, 1000)) { 3799 dev_err(eth->dev, "warm reset failed\n"); 3800 mtk_hw_reset(eth); 3801 return; 3802 } 3803 3804 if (mtk_is_netsys_v3_or_greater(eth)) { 3805 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3; 3806 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3807 rst_mask |= RSTCTRL_PPE1_V3; 3808 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3809 rst_mask |= RSTCTRL_PPE2; 3810 3811 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3812 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3813 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3814 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3815 rst_mask |= RSTCTRL_PPE1; 3816 } else { 3817 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3818 } 3819 3820 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3821 3822 udelay(1); 3823 val = mtk_hw_reset_read(eth); 3824 if (!(val & rst_mask)) 3825 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3826 val, rst_mask); 3827 3828 rst_mask |= RSTCTRL_FE; 3829 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3830 3831 udelay(1); 3832 val = mtk_hw_reset_read(eth); 3833 if (val & rst_mask) 3834 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3835 val, rst_mask); 3836 } 3837 3838 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3839 { 3840 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3841 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3842 bool oq_hang, cdm1_busy, adma_busy; 3843 bool wtx_busy, cdm_full, oq_free; 3844 u32 wdidx, val, gdm1_fc, gdm2_fc; 3845 bool qfsm_hang, qfwd_hang; 3846 bool ret = false; 3847 3848 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3849 return false; 3850 3851 /* WDMA sanity checks */ 3852 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3853 3854 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3855 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3856 3857 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3858 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3859 3860 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3861 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3862 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3863 3864 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3865 if (++eth->reset.wdma_hang_count > 2) { 3866 eth->reset.wdma_hang_count = 0; 3867 ret = true; 3868 } 3869 goto out; 3870 } 3871 3872 /* QDMA sanity checks */ 3873 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3874 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3875 3876 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3877 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3878 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3879 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3880 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3881 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3882 3883 if (qfsm_hang && qfwd_hang && 3884 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3885 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3886 if (++eth->reset.qdma_hang_count > 2) { 3887 eth->reset.qdma_hang_count = 0; 3888 ret = true; 3889 } 3890 goto out; 3891 } 3892 3893 /* ADMA sanity checks */ 3894 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3895 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3896 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3897 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3898 3899 if (oq_hang && cdm1_busy && adma_busy) { 3900 if (++eth->reset.adma_hang_count > 2) { 3901 eth->reset.adma_hang_count = 0; 3902 ret = true; 3903 } 3904 goto out; 3905 } 3906 3907 eth->reset.wdma_hang_count = 0; 3908 eth->reset.qdma_hang_count = 0; 3909 eth->reset.adma_hang_count = 0; 3910 out: 3911 eth->reset.wdidx = wdidx; 3912 3913 return ret; 3914 } 3915 3916 static void mtk_hw_reset_monitor_work(struct work_struct *work) 3917 { 3918 struct delayed_work *del_work = to_delayed_work(work); 3919 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3920 reset.monitor_work); 3921 3922 if (test_bit(MTK_RESETTING, ð->state)) 3923 goto out; 3924 3925 /* DMA stuck checks */ 3926 if (mtk_hw_check_dma_hang(eth)) 3927 schedule_work(ð->pending_work); 3928 3929 out: 3930 schedule_delayed_work(ð->reset.monitor_work, 3931 MTK_DMA_MONITOR_TIMEOUT); 3932 } 3933 3934 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3935 { 3936 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3937 ETHSYS_DMA_AG_MAP_PPE; 3938 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3939 int i, val, ret; 3940 3941 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3942 return 0; 3943 3944 if (!reset) { 3945 pm_runtime_enable(eth->dev); 3946 pm_runtime_get_sync(eth->dev); 3947 3948 ret = mtk_clk_enable(eth); 3949 if (ret) 3950 goto err_disable_pm; 3951 } 3952 3953 if (eth->ethsys) 3954 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3955 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3956 3957 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3958 ret = device_reset(eth->dev); 3959 if (ret) { 3960 dev_err(eth->dev, "MAC reset failed!\n"); 3961 goto err_disable_pm; 3962 } 3963 3964 /* set interrupt delays based on current Net DIM sample */ 3965 mtk_dim_rx(ð->rx_dim.work); 3966 mtk_dim_tx(ð->tx_dim.work); 3967 3968 /* disable delay and normal interrupt */ 3969 mtk_tx_irq_disable(eth, ~0); 3970 mtk_rx_irq_disable(eth, ~0); 3971 3972 return 0; 3973 } 3974 3975 msleep(100); 3976 3977 if (reset) 3978 mtk_hw_warm_reset(eth); 3979 else 3980 mtk_hw_reset(eth); 3981 3982 /* No MT7628/88 support yet */ 3983 if (reset && !MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3984 mtk_mdio_config(eth); 3985 3986 if (mtk_is_netsys_v3_or_greater(eth)) { 3987 /* Set FE to PDMAv2 if necessary */ 3988 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3989 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3990 } 3991 3992 if (eth->pctl) { 3993 /* Set GE2 driving and slew rate */ 3994 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3995 3996 /* set GE2 TDSEL */ 3997 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3998 3999 /* set GE2 TUNE */ 4000 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 4001 } 4002 4003 /* Set linkdown as the default for each GMAC. Its own MCR would be set 4004 * up with the more appropriate value when mtk_mac_config call is being 4005 * invoked. 4006 */ 4007 for (i = 0; i < MTK_MAX_DEVS; i++) { 4008 struct net_device *dev = eth->netdev[i]; 4009 4010 if (!dev) 4011 continue; 4012 4013 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 4014 mtk_set_mcr_max_rx(netdev_priv(dev), 4015 dev->mtu + MTK_RX_ETH_HLEN); 4016 } 4017 4018 /* Indicates CDM to parse the MTK special tag from CPU 4019 * which also is working out for untag packets. 4020 */ 4021 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 4022 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 4023 if (mtk_is_netsys_v1(eth)) { 4024 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 4025 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 4026 4027 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 4028 } 4029 4030 /* set interrupt delays based on current Net DIM sample */ 4031 mtk_dim_rx(ð->rx_dim.work); 4032 mtk_dim_tx(ð->tx_dim.work); 4033 4034 /* disable delay and normal interrupt */ 4035 mtk_tx_irq_disable(eth, ~0); 4036 mtk_rx_irq_disable(eth, ~0); 4037 4038 /* FE int grouping */ 4039 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 4040 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4); 4041 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 4042 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4); 4043 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 4044 4045 if (mtk_is_netsys_v3_or_greater(eth)) { 4046 /* PSE should not drop port1, port8 and port9 packets */ 4047 mtk_w32(eth, 0x00000302, PSE_DROP_CFG); 4048 4049 /* GDM and CDM Threshold */ 4050 mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); 4051 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); 4052 4053 /* Disable GDM1 RX CRC stripping */ 4054 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); 4055 4056 /* PSE GDM3 MIB counter has incorrect hw default values, 4057 * so the driver ought to read clear the values beforehand 4058 * in case ethtool retrieve wrong mib values. 4059 */ 4060 for (i = 0; i < 0x80; i += 0x4) 4061 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); 4062 } else if (!mtk_is_netsys_v1(eth)) { 4063 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 4064 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 4065 4066 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 4067 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 4068 4069 /* PSE Free Queue Flow Control */ 4070 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 4071 4072 /* PSE config input queue threshold */ 4073 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 4074 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 4075 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 4076 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 4077 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 4078 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 4079 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 4080 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 4081 4082 /* PSE config output queue threshold */ 4083 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 4084 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 4085 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 4086 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 4087 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 4088 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 4089 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 4090 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 4091 4092 /* GDM and CDM Threshold */ 4093 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 4094 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 4095 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 4096 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 4097 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 4098 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 4099 } 4100 4101 return 0; 4102 4103 err_disable_pm: 4104 if (!reset) { 4105 pm_runtime_put_sync(eth->dev); 4106 pm_runtime_disable(eth->dev); 4107 } 4108 4109 return ret; 4110 } 4111 4112 static int mtk_hw_deinit(struct mtk_eth *eth) 4113 { 4114 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 4115 return 0; 4116 4117 mtk_clk_disable(eth); 4118 4119 pm_runtime_put_sync(eth->dev); 4120 pm_runtime_disable(eth->dev); 4121 4122 return 0; 4123 } 4124 4125 static void mtk_uninit(struct net_device *dev) 4126 { 4127 struct mtk_mac *mac = netdev_priv(dev); 4128 struct mtk_eth *eth = mac->hw; 4129 4130 phylink_disconnect_phy(mac->phylink); 4131 mtk_tx_irq_disable(eth, ~0); 4132 mtk_rx_irq_disable(eth, ~0); 4133 } 4134 4135 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 4136 { 4137 int length = new_mtu + MTK_RX_ETH_HLEN; 4138 struct mtk_mac *mac = netdev_priv(dev); 4139 struct mtk_eth *eth = mac->hw; 4140 4141 if (rcu_access_pointer(eth->prog) && 4142 length > MTK_PP_MAX_BUF_SIZE) { 4143 netdev_err(dev, "Invalid MTU for XDP mode\n"); 4144 return -EINVAL; 4145 } 4146 4147 mtk_set_mcr_max_rx(mac, length); 4148 WRITE_ONCE(dev->mtu, new_mtu); 4149 4150 return 0; 4151 } 4152 4153 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4154 { 4155 struct mtk_mac *mac = netdev_priv(dev); 4156 4157 switch (cmd) { 4158 case SIOCGMIIPHY: 4159 case SIOCGMIIREG: 4160 case SIOCSMIIREG: 4161 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 4162 default: 4163 break; 4164 } 4165 4166 return -EOPNOTSUPP; 4167 } 4168 4169 static void mtk_prepare_for_reset(struct mtk_eth *eth) 4170 { 4171 u32 val; 4172 int i; 4173 4174 /* set FE PPE ports link down */ 4175 for (i = MTK_GMAC1_ID; 4176 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4177 i += 2) { 4178 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4179 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4180 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4181 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4182 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4183 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4184 } 4185 4186 /* adjust PPE configurations to prepare for reset */ 4187 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 4188 mtk_ppe_prepare_reset(eth->ppe[i]); 4189 4190 /* disable NETSYS interrupts */ 4191 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 4192 4193 /* force link down GMAC */ 4194 for (i = 0; i < 2; i++) { 4195 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 4196 mtk_w32(eth, val, MTK_MAC_MCR(i)); 4197 } 4198 } 4199 4200 static void mtk_pending_work(struct work_struct *work) 4201 { 4202 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 4203 unsigned long restart = 0; 4204 u32 val; 4205 int i; 4206 4207 rtnl_lock(); 4208 set_bit(MTK_RESETTING, ð->state); 4209 4210 mtk_prepare_for_reset(eth); 4211 mtk_wed_fe_reset(); 4212 /* Run again reset preliminary configuration in order to avoid any 4213 * possible race during FE reset since it can run releasing RTNL lock. 4214 */ 4215 mtk_prepare_for_reset(eth); 4216 4217 /* stop all devices to make sure that dma is properly shut down */ 4218 for (i = 0; i < MTK_MAX_DEVS; i++) { 4219 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 4220 continue; 4221 4222 mtk_stop(eth->netdev[i]); 4223 __set_bit(i, &restart); 4224 } 4225 4226 usleep_range(15000, 16000); 4227 4228 if (eth->dev->pins) 4229 pinctrl_select_state(eth->dev->pins->p, 4230 eth->dev->pins->default_state); 4231 mtk_hw_init(eth, true); 4232 4233 /* restart DMA and enable IRQs */ 4234 for (i = 0; i < MTK_MAX_DEVS; i++) { 4235 if (!eth->netdev[i] || !test_bit(i, &restart)) 4236 continue; 4237 4238 if (mtk_open(eth->netdev[i])) { 4239 netif_alert(eth, ifup, eth->netdev[i], 4240 "Driver up/down cycle failed\n"); 4241 dev_close(eth->netdev[i]); 4242 } 4243 } 4244 4245 /* set FE PPE ports link up */ 4246 for (i = MTK_GMAC1_ID; 4247 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4248 i += 2) { 4249 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4250 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4251 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4252 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4253 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4254 4255 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4256 } 4257 4258 clear_bit(MTK_RESETTING, ð->state); 4259 4260 mtk_wed_fe_reset_complete(); 4261 4262 rtnl_unlock(); 4263 } 4264 4265 static int mtk_free_dev(struct mtk_eth *eth) 4266 { 4267 int i; 4268 4269 for (i = 0; i < MTK_MAX_DEVS; i++) { 4270 if (!eth->netdev[i]) 4271 continue; 4272 free_netdev(eth->netdev[i]); 4273 } 4274 4275 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4276 if (!eth->dsa_meta[i]) 4277 break; 4278 metadata_dst_free(eth->dsa_meta[i]); 4279 } 4280 4281 return 0; 4282 } 4283 4284 static int mtk_unreg_dev(struct mtk_eth *eth) 4285 { 4286 int i; 4287 4288 for (i = 0; i < MTK_MAX_DEVS; i++) { 4289 struct mtk_mac *mac; 4290 if (!eth->netdev[i]) 4291 continue; 4292 mac = netdev_priv(eth->netdev[i]); 4293 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4294 unregister_netdevice_notifier(&mac->device_notifier); 4295 unregister_netdev(eth->netdev[i]); 4296 } 4297 4298 return 0; 4299 } 4300 4301 static void mtk_sgmii_destroy(struct mtk_eth *eth) 4302 { 4303 int i; 4304 4305 for (i = 0; i < MTK_MAX_DEVS; i++) 4306 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); 4307 } 4308 4309 static int mtk_cleanup(struct mtk_eth *eth) 4310 { 4311 mtk_sgmii_destroy(eth); 4312 mtk_unreg_dev(eth); 4313 mtk_free_dev(eth); 4314 cancel_work_sync(ð->pending_work); 4315 cancel_delayed_work_sync(ð->reset.monitor_work); 4316 4317 return 0; 4318 } 4319 4320 static int mtk_get_link_ksettings(struct net_device *ndev, 4321 struct ethtool_link_ksettings *cmd) 4322 { 4323 struct mtk_mac *mac = netdev_priv(ndev); 4324 4325 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4326 return -EBUSY; 4327 4328 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4329 } 4330 4331 static int mtk_set_link_ksettings(struct net_device *ndev, 4332 const struct ethtool_link_ksettings *cmd) 4333 { 4334 struct mtk_mac *mac = netdev_priv(ndev); 4335 4336 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4337 return -EBUSY; 4338 4339 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4340 } 4341 4342 static void mtk_get_drvinfo(struct net_device *dev, 4343 struct ethtool_drvinfo *info) 4344 { 4345 struct mtk_mac *mac = netdev_priv(dev); 4346 4347 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4348 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4349 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4350 } 4351 4352 static u32 mtk_get_msglevel(struct net_device *dev) 4353 { 4354 struct mtk_mac *mac = netdev_priv(dev); 4355 4356 return mac->hw->msg_enable; 4357 } 4358 4359 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4360 { 4361 struct mtk_mac *mac = netdev_priv(dev); 4362 4363 mac->hw->msg_enable = value; 4364 } 4365 4366 static int mtk_nway_reset(struct net_device *dev) 4367 { 4368 struct mtk_mac *mac = netdev_priv(dev); 4369 4370 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4371 return -EBUSY; 4372 4373 if (!mac->phylink) 4374 return -ENOTSUPP; 4375 4376 return phylink_ethtool_nway_reset(mac->phylink); 4377 } 4378 4379 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4380 { 4381 int i; 4382 4383 switch (stringset) { 4384 case ETH_SS_STATS: { 4385 struct mtk_mac *mac = netdev_priv(dev); 4386 4387 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4388 ethtool_puts(&data, mtk_ethtool_stats[i].str); 4389 if (mtk_page_pool_enabled(mac->hw)) 4390 page_pool_ethtool_stats_get_strings(data); 4391 break; 4392 } 4393 default: 4394 break; 4395 } 4396 } 4397 4398 static int mtk_get_sset_count(struct net_device *dev, int sset) 4399 { 4400 switch (sset) { 4401 case ETH_SS_STATS: { 4402 int count = ARRAY_SIZE(mtk_ethtool_stats); 4403 struct mtk_mac *mac = netdev_priv(dev); 4404 4405 if (mtk_page_pool_enabled(mac->hw)) 4406 count += page_pool_ethtool_stats_get_count(); 4407 return count; 4408 } 4409 default: 4410 return -EOPNOTSUPP; 4411 } 4412 } 4413 4414 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4415 { 4416 struct page_pool_stats stats = {}; 4417 int i; 4418 4419 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4420 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4421 4422 if (!ring->page_pool) 4423 continue; 4424 4425 page_pool_get_stats(ring->page_pool, &stats); 4426 } 4427 page_pool_ethtool_stats_get(data, &stats); 4428 } 4429 4430 static void mtk_get_ethtool_stats(struct net_device *dev, 4431 struct ethtool_stats *stats, u64 *data) 4432 { 4433 struct mtk_mac *mac = netdev_priv(dev); 4434 struct mtk_hw_stats *hwstats = mac->hw_stats; 4435 u64 *data_src, *data_dst; 4436 unsigned int start; 4437 int i; 4438 4439 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4440 return; 4441 4442 if (netif_running(dev) && netif_device_present(dev)) { 4443 if (spin_trylock_bh(&hwstats->stats_lock)) { 4444 mtk_stats_update_mac(mac); 4445 spin_unlock_bh(&hwstats->stats_lock); 4446 } 4447 } 4448 4449 data_src = (u64 *)hwstats; 4450 4451 do { 4452 data_dst = data; 4453 start = u64_stats_fetch_begin(&hwstats->syncp); 4454 4455 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4456 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4457 if (mtk_page_pool_enabled(mac->hw)) 4458 mtk_ethtool_pp_stats(mac->hw, data_dst); 4459 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4460 } 4461 4462 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4463 u32 *rule_locs) 4464 { 4465 int ret = -EOPNOTSUPP; 4466 4467 switch (cmd->cmd) { 4468 case ETHTOOL_GRXRINGS: 4469 if (dev->hw_features & NETIF_F_LRO) { 4470 cmd->data = MTK_MAX_RX_RING_NUM; 4471 ret = 0; 4472 } 4473 break; 4474 case ETHTOOL_GRXCLSRLCNT: 4475 if (dev->hw_features & NETIF_F_LRO) { 4476 struct mtk_mac *mac = netdev_priv(dev); 4477 4478 cmd->rule_cnt = mac->hwlro_ip_cnt; 4479 ret = 0; 4480 } 4481 break; 4482 case ETHTOOL_GRXCLSRULE: 4483 if (dev->hw_features & NETIF_F_LRO) 4484 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4485 break; 4486 case ETHTOOL_GRXCLSRLALL: 4487 if (dev->hw_features & NETIF_F_LRO) 4488 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4489 rule_locs); 4490 break; 4491 default: 4492 break; 4493 } 4494 4495 return ret; 4496 } 4497 4498 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4499 { 4500 int ret = -EOPNOTSUPP; 4501 4502 switch (cmd->cmd) { 4503 case ETHTOOL_SRXCLSRLINS: 4504 if (dev->hw_features & NETIF_F_LRO) 4505 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4506 break; 4507 case ETHTOOL_SRXCLSRLDEL: 4508 if (dev->hw_features & NETIF_F_LRO) 4509 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4510 break; 4511 default: 4512 break; 4513 } 4514 4515 return ret; 4516 } 4517 4518 static void mtk_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) 4519 { 4520 struct mtk_mac *mac = netdev_priv(dev); 4521 4522 phylink_ethtool_get_pauseparam(mac->phylink, pause); 4523 } 4524 4525 static int mtk_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) 4526 { 4527 struct mtk_mac *mac = netdev_priv(dev); 4528 4529 return phylink_ethtool_set_pauseparam(mac->phylink, pause); 4530 } 4531 4532 static int mtk_get_eee(struct net_device *dev, struct ethtool_keee *eee) 4533 { 4534 struct mtk_mac *mac = netdev_priv(dev); 4535 4536 return phylink_ethtool_get_eee(mac->phylink, eee); 4537 } 4538 4539 static int mtk_set_eee(struct net_device *dev, struct ethtool_keee *eee) 4540 { 4541 struct mtk_mac *mac = netdev_priv(dev); 4542 4543 return phylink_ethtool_set_eee(mac->phylink, eee); 4544 } 4545 4546 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4547 struct net_device *sb_dev) 4548 { 4549 struct mtk_mac *mac = netdev_priv(dev); 4550 unsigned int queue = 0; 4551 4552 if (netdev_uses_dsa(dev)) 4553 queue = skb_get_queue_mapping(skb) + 3; 4554 else 4555 queue = mac->id; 4556 4557 if (queue >= dev->num_tx_queues) 4558 queue = 0; 4559 4560 return queue; 4561 } 4562 4563 static const struct ethtool_ops mtk_ethtool_ops = { 4564 .get_link_ksettings = mtk_get_link_ksettings, 4565 .set_link_ksettings = mtk_set_link_ksettings, 4566 .get_drvinfo = mtk_get_drvinfo, 4567 .get_msglevel = mtk_get_msglevel, 4568 .set_msglevel = mtk_set_msglevel, 4569 .nway_reset = mtk_nway_reset, 4570 .get_link = ethtool_op_get_link, 4571 .get_strings = mtk_get_strings, 4572 .get_sset_count = mtk_get_sset_count, 4573 .get_ethtool_stats = mtk_get_ethtool_stats, 4574 .get_pauseparam = mtk_get_pauseparam, 4575 .set_pauseparam = mtk_set_pauseparam, 4576 .get_rxnfc = mtk_get_rxnfc, 4577 .set_rxnfc = mtk_set_rxnfc, 4578 .get_eee = mtk_get_eee, 4579 .set_eee = mtk_set_eee, 4580 }; 4581 4582 static const struct net_device_ops mtk_netdev_ops = { 4583 .ndo_uninit = mtk_uninit, 4584 .ndo_open = mtk_open, 4585 .ndo_stop = mtk_stop, 4586 .ndo_start_xmit = mtk_start_xmit, 4587 .ndo_set_mac_address = mtk_set_mac_address, 4588 .ndo_validate_addr = eth_validate_addr, 4589 .ndo_eth_ioctl = mtk_do_ioctl, 4590 .ndo_change_mtu = mtk_change_mtu, 4591 .ndo_tx_timeout = mtk_tx_timeout, 4592 .ndo_get_stats64 = mtk_get_stats64, 4593 .ndo_fix_features = mtk_fix_features, 4594 .ndo_set_features = mtk_set_features, 4595 #ifdef CONFIG_NET_POLL_CONTROLLER 4596 .ndo_poll_controller = mtk_poll_controller, 4597 #endif 4598 .ndo_setup_tc = mtk_eth_setup_tc, 4599 .ndo_bpf = mtk_xdp, 4600 .ndo_xdp_xmit = mtk_xdp_xmit, 4601 .ndo_select_queue = mtk_select_queue, 4602 }; 4603 4604 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4605 { 4606 const __be32 *_id = of_get_property(np, "reg", NULL); 4607 phy_interface_t phy_mode; 4608 struct phylink *phylink; 4609 struct mtk_mac *mac; 4610 int id, err; 4611 int txqs = 1; 4612 u32 val; 4613 4614 if (!_id) { 4615 dev_err(eth->dev, "missing mac id\n"); 4616 return -EINVAL; 4617 } 4618 4619 id = be32_to_cpup(_id); 4620 if (id >= MTK_MAX_DEVS) { 4621 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4622 return -EINVAL; 4623 } 4624 4625 if (eth->netdev[id]) { 4626 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4627 return -EINVAL; 4628 } 4629 4630 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4631 txqs = MTK_QDMA_NUM_QUEUES; 4632 4633 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4634 if (!eth->netdev[id]) { 4635 dev_err(eth->dev, "alloc_etherdev failed\n"); 4636 return -ENOMEM; 4637 } 4638 mac = netdev_priv(eth->netdev[id]); 4639 eth->mac[id] = mac; 4640 mac->id = id; 4641 mac->hw = eth; 4642 mac->of_node = np; 4643 4644 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); 4645 if (err == -EPROBE_DEFER) 4646 return err; 4647 4648 if (err) { 4649 /* If the mac address is invalid, use random mac address */ 4650 eth_hw_addr_random(eth->netdev[id]); 4651 dev_err(eth->dev, "generated random MAC address %pM\n", 4652 eth->netdev[id]->dev_addr); 4653 } 4654 4655 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4656 mac->hwlro_ip_cnt = 0; 4657 4658 mac->hw_stats = devm_kzalloc(eth->dev, 4659 sizeof(*mac->hw_stats), 4660 GFP_KERNEL); 4661 if (!mac->hw_stats) { 4662 dev_err(eth->dev, "failed to allocate counter memory\n"); 4663 err = -ENOMEM; 4664 goto free_netdev; 4665 } 4666 spin_lock_init(&mac->hw_stats->stats_lock); 4667 u64_stats_init(&mac->hw_stats->syncp); 4668 4669 if (mtk_is_netsys_v3_or_greater(eth)) 4670 mac->hw_stats->reg_offset = id * 0x80; 4671 else 4672 mac->hw_stats->reg_offset = id * 0x40; 4673 4674 /* phylink create */ 4675 err = of_get_phy_mode(np, &phy_mode); 4676 if (err) { 4677 dev_err(eth->dev, "incorrect phy-mode\n"); 4678 goto free_netdev; 4679 } 4680 4681 /* mac config is not set */ 4682 mac->interface = PHY_INTERFACE_MODE_NA; 4683 mac->speed = SPEED_UNKNOWN; 4684 4685 mac->phylink_config.dev = ð->netdev[id]->dev; 4686 mac->phylink_config.type = PHYLINK_NETDEV; 4687 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4688 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4689 mac->phylink_config.lpi_capabilities = MAC_100FD | MAC_1000FD | 4690 MAC_2500FD; 4691 mac->phylink_config.lpi_timer_default = 1000; 4692 4693 /* MT7623 gmac0 is now missing its speed-specific PLL configuration 4694 * in its .mac_config method (since state->speed is not valid there. 4695 * Disable support for MII, GMII and RGMII. 4696 */ 4697 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { 4698 __set_bit(PHY_INTERFACE_MODE_MII, 4699 mac->phylink_config.supported_interfaces); 4700 __set_bit(PHY_INTERFACE_MODE_GMII, 4701 mac->phylink_config.supported_interfaces); 4702 4703 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4704 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4705 } 4706 4707 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4708 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4709 mac->phylink_config.supported_interfaces); 4710 4711 /* TRGMII is not permitted on MT7621 if using DDR2 */ 4712 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 4713 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 4714 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 4715 if (val & SYSCFG_DRAM_TYPE_DDR2) 4716 __clear_bit(PHY_INTERFACE_MODE_TRGMII, 4717 mac->phylink_config.supported_interfaces); 4718 } 4719 4720 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4721 __set_bit(PHY_INTERFACE_MODE_SGMII, 4722 mac->phylink_config.supported_interfaces); 4723 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4724 mac->phylink_config.supported_interfaces); 4725 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4726 mac->phylink_config.supported_interfaces); 4727 } 4728 4729 if (mtk_is_netsys_v3_or_greater(mac->hw) && 4730 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && 4731 id == MTK_GMAC1_ID) { 4732 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 4733 MAC_SYM_PAUSE | 4734 MAC_10000FD; 4735 phy_interface_zero(mac->phylink_config.supported_interfaces); 4736 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 4737 mac->phylink_config.supported_interfaces); 4738 } 4739 4740 phylink = phylink_create(&mac->phylink_config, 4741 of_fwnode_handle(mac->of_node), 4742 phy_mode, &mtk_phylink_ops); 4743 if (IS_ERR(phylink)) { 4744 err = PTR_ERR(phylink); 4745 goto free_netdev; 4746 } 4747 4748 mac->phylink = phylink; 4749 4750 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4751 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4752 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4753 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4754 4755 eth->netdev[id]->hw_features = eth->soc->hw_features; 4756 if (eth->hwlro) 4757 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4758 4759 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4760 ~NETIF_F_HW_VLAN_CTAG_TX; 4761 eth->netdev[id]->features |= eth->soc->hw_features; 4762 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4763 4764 eth->netdev[id]->irq = eth->irq[0]; 4765 eth->netdev[id]->dev.of_node = np; 4766 4767 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4768 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4769 else 4770 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4771 4772 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4773 mac->device_notifier.notifier_call = mtk_device_event; 4774 register_netdevice_notifier(&mac->device_notifier); 4775 } 4776 4777 if (mtk_page_pool_enabled(eth)) 4778 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4779 NETDEV_XDP_ACT_REDIRECT | 4780 NETDEV_XDP_ACT_NDO_XMIT | 4781 NETDEV_XDP_ACT_NDO_XMIT_SG; 4782 4783 return 0; 4784 4785 free_netdev: 4786 free_netdev(eth->netdev[id]); 4787 return err; 4788 } 4789 4790 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4791 { 4792 struct net_device *dev, *tmp; 4793 LIST_HEAD(dev_list); 4794 int i; 4795 4796 rtnl_lock(); 4797 4798 for (i = 0; i < MTK_MAX_DEVS; i++) { 4799 dev = eth->netdev[i]; 4800 4801 if (!dev || !(dev->flags & IFF_UP)) 4802 continue; 4803 4804 list_add_tail(&dev->close_list, &dev_list); 4805 } 4806 4807 dev_close_many(&dev_list, false); 4808 4809 eth->dma_dev = dma_dev; 4810 4811 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4812 list_del_init(&dev->close_list); 4813 dev_open(dev, NULL); 4814 } 4815 4816 rtnl_unlock(); 4817 } 4818 4819 static int mtk_sgmii_init(struct mtk_eth *eth) 4820 { 4821 struct device_node *np; 4822 struct regmap *regmap; 4823 u32 flags; 4824 int i; 4825 4826 for (i = 0; i < MTK_MAX_DEVS; i++) { 4827 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); 4828 if (!np) 4829 break; 4830 4831 regmap = syscon_node_to_regmap(np); 4832 flags = 0; 4833 if (of_property_read_bool(np, "mediatek,pnswap")) 4834 flags |= MTK_SGMII_FLAG_PN_SWAP; 4835 4836 of_node_put(np); 4837 4838 if (IS_ERR(regmap)) 4839 return PTR_ERR(regmap); 4840 4841 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, 4842 eth->soc->ana_rgc3, 4843 flags); 4844 } 4845 4846 return 0; 4847 } 4848 4849 static int mtk_probe(struct platform_device *pdev) 4850 { 4851 struct resource *res = NULL, *res_sram; 4852 struct device_node *mac_np; 4853 struct mtk_eth *eth; 4854 int err, i; 4855 4856 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4857 if (!eth) 4858 return -ENOMEM; 4859 4860 eth->soc = of_device_get_match_data(&pdev->dev); 4861 4862 eth->dev = &pdev->dev; 4863 eth->dma_dev = &pdev->dev; 4864 eth->base = devm_platform_ioremap_resource(pdev, 0); 4865 if (IS_ERR(eth->base)) 4866 return PTR_ERR(eth->base); 4867 4868 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4869 eth->ip_align = NET_IP_ALIGN; 4870 4871 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4872 /* SRAM is actual memory and supports transparent access just like DRAM. 4873 * Hence we don't require __iomem being set and don't need to use accessor 4874 * functions to read from or write to SRAM. 4875 */ 4876 if (mtk_is_netsys_v3_or_greater(eth)) { 4877 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1); 4878 if (IS_ERR(eth->sram_base)) 4879 return PTR_ERR(eth->sram_base); 4880 } else { 4881 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; 4882 } 4883 } 4884 4885 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { 4886 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36)); 4887 if (!err) 4888 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 4889 4890 if (err) { 4891 dev_err(&pdev->dev, "Wrong DMA config\n"); 4892 return -EINVAL; 4893 } 4894 } 4895 4896 spin_lock_init(ð->page_lock); 4897 spin_lock_init(ð->tx_irq_lock); 4898 spin_lock_init(ð->rx_irq_lock); 4899 spin_lock_init(ð->dim_lock); 4900 4901 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4902 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4903 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4904 4905 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4906 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4907 4908 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4909 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4910 "mediatek,ethsys"); 4911 if (IS_ERR(eth->ethsys)) { 4912 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4913 return PTR_ERR(eth->ethsys); 4914 } 4915 } 4916 4917 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4918 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4919 "mediatek,infracfg"); 4920 if (IS_ERR(eth->infra)) { 4921 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4922 return PTR_ERR(eth->infra); 4923 } 4924 } 4925 4926 if (of_dma_is_coherent(pdev->dev.of_node)) { 4927 struct regmap *cci; 4928 4929 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4930 "cci-control-port"); 4931 /* enable CPU/bus coherency */ 4932 if (!IS_ERR(cci)) 4933 regmap_write(cci, 0, 3); 4934 } 4935 4936 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4937 err = mtk_sgmii_init(eth); 4938 4939 if (err) 4940 return err; 4941 } 4942 4943 if (eth->soc->required_pctl) { 4944 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4945 "mediatek,pctl"); 4946 if (IS_ERR(eth->pctl)) { 4947 dev_err(&pdev->dev, "no pctl regmap found\n"); 4948 err = PTR_ERR(eth->pctl); 4949 goto err_destroy_sgmii; 4950 } 4951 } 4952 4953 if (mtk_is_netsys_v2_or_greater(eth)) { 4954 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4955 if (!res) { 4956 err = -EINVAL; 4957 goto err_destroy_sgmii; 4958 } 4959 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4960 if (mtk_is_netsys_v3_or_greater(eth)) { 4961 res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1); 4962 if (!res_sram) { 4963 err = -EINVAL; 4964 goto err_destroy_sgmii; 4965 } 4966 eth->phy_scratch_ring = res_sram->start; 4967 } else { 4968 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; 4969 } 4970 } 4971 } 4972 4973 if (eth->soc->offload_version) { 4974 for (i = 0;; i++) { 4975 struct device_node *np; 4976 phys_addr_t wdma_phy; 4977 u32 wdma_base; 4978 4979 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4980 break; 4981 4982 np = of_parse_phandle(pdev->dev.of_node, 4983 "mediatek,wed", i); 4984 if (!np) 4985 break; 4986 4987 wdma_base = eth->soc->reg_map->wdma_base[i]; 4988 wdma_phy = res ? res->start + wdma_base : 0; 4989 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4990 wdma_phy, i); 4991 } 4992 } 4993 4994 for (i = 0; i < 3; i++) { 4995 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4996 eth->irq[i] = eth->irq[0]; 4997 else 4998 eth->irq[i] = platform_get_irq(pdev, i); 4999 if (eth->irq[i] < 0) { 5000 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 5001 err = -ENXIO; 5002 goto err_wed_exit; 5003 } 5004 } 5005 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 5006 eth->clks[i] = devm_clk_get(eth->dev, 5007 mtk_clks_source_name[i]); 5008 if (IS_ERR(eth->clks[i])) { 5009 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 5010 err = -EPROBE_DEFER; 5011 goto err_wed_exit; 5012 } 5013 if (eth->soc->required_clks & BIT(i)) { 5014 dev_err(&pdev->dev, "clock %s not found\n", 5015 mtk_clks_source_name[i]); 5016 err = -EINVAL; 5017 goto err_wed_exit; 5018 } 5019 eth->clks[i] = NULL; 5020 } 5021 } 5022 5023 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 5024 INIT_WORK(ð->pending_work, mtk_pending_work); 5025 5026 err = mtk_hw_init(eth, false); 5027 if (err) 5028 goto err_wed_exit; 5029 5030 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 5031 5032 for_each_child_of_node(pdev->dev.of_node, mac_np) { 5033 if (!of_device_is_compatible(mac_np, 5034 "mediatek,eth-mac")) 5035 continue; 5036 5037 if (!of_device_is_available(mac_np)) 5038 continue; 5039 5040 err = mtk_add_mac(eth, mac_np); 5041 if (err) { 5042 of_node_put(mac_np); 5043 goto err_deinit_hw; 5044 } 5045 } 5046 5047 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 5048 err = devm_request_irq(eth->dev, eth->irq[0], 5049 mtk_handle_irq, 0, 5050 dev_name(eth->dev), eth); 5051 } else { 5052 err = devm_request_irq(eth->dev, eth->irq[1], 5053 mtk_handle_irq_tx, 0, 5054 dev_name(eth->dev), eth); 5055 if (err) 5056 goto err_free_dev; 5057 5058 err = devm_request_irq(eth->dev, eth->irq[2], 5059 mtk_handle_irq_rx, 0, 5060 dev_name(eth->dev), eth); 5061 } 5062 if (err) 5063 goto err_free_dev; 5064 5065 /* No MT7628/88 support yet */ 5066 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 5067 err = mtk_mdio_init(eth); 5068 if (err) 5069 goto err_free_dev; 5070 } 5071 5072 if (eth->soc->offload_version) { 5073 u8 ppe_num = eth->soc->ppe_num; 5074 5075 ppe_num = min_t(u8, ARRAY_SIZE(eth->ppe), ppe_num); 5076 for (i = 0; i < ppe_num; i++) { 5077 u32 ppe_addr = eth->soc->reg_map->ppe_base; 5078 5079 ppe_addr += (i == 2 ? 0xc00 : i * 0x400); 5080 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); 5081 5082 if (!eth->ppe[i]) { 5083 err = -ENOMEM; 5084 goto err_deinit_ppe; 5085 } 5086 err = mtk_eth_offload_init(eth, i); 5087 5088 if (err) 5089 goto err_deinit_ppe; 5090 } 5091 } 5092 5093 for (i = 0; i < MTK_MAX_DEVS; i++) { 5094 if (!eth->netdev[i]) 5095 continue; 5096 5097 err = register_netdev(eth->netdev[i]); 5098 if (err) { 5099 dev_err(eth->dev, "error bringing up device\n"); 5100 goto err_deinit_ppe; 5101 } else 5102 netif_info(eth, probe, eth->netdev[i], 5103 "mediatek frame engine at 0x%08lx, irq %d\n", 5104 eth->netdev[i]->base_addr, eth->irq[0]); 5105 } 5106 5107 /* we run 2 devices on the same DMA ring so we need a dummy device 5108 * for NAPI to work 5109 */ 5110 eth->dummy_dev = alloc_netdev_dummy(0); 5111 if (!eth->dummy_dev) { 5112 err = -ENOMEM; 5113 dev_err(eth->dev, "failed to allocated dummy device\n"); 5114 goto err_unreg_netdev; 5115 } 5116 netif_napi_add(eth->dummy_dev, ð->tx_napi, mtk_napi_tx); 5117 netif_napi_add(eth->dummy_dev, ð->rx_napi, mtk_napi_rx); 5118 5119 platform_set_drvdata(pdev, eth); 5120 schedule_delayed_work(ð->reset.monitor_work, 5121 MTK_DMA_MONITOR_TIMEOUT); 5122 5123 return 0; 5124 5125 err_unreg_netdev: 5126 mtk_unreg_dev(eth); 5127 err_deinit_ppe: 5128 mtk_ppe_deinit(eth); 5129 mtk_mdio_cleanup(eth); 5130 err_free_dev: 5131 mtk_free_dev(eth); 5132 err_deinit_hw: 5133 mtk_hw_deinit(eth); 5134 err_wed_exit: 5135 mtk_wed_exit(); 5136 err_destroy_sgmii: 5137 mtk_sgmii_destroy(eth); 5138 5139 return err; 5140 } 5141 5142 static void mtk_remove(struct platform_device *pdev) 5143 { 5144 struct mtk_eth *eth = platform_get_drvdata(pdev); 5145 struct mtk_mac *mac; 5146 int i; 5147 5148 /* stop all devices to make sure that dma is properly shut down */ 5149 for (i = 0; i < MTK_MAX_DEVS; i++) { 5150 if (!eth->netdev[i]) 5151 continue; 5152 mtk_stop(eth->netdev[i]); 5153 mac = netdev_priv(eth->netdev[i]); 5154 phylink_disconnect_phy(mac->phylink); 5155 } 5156 5157 mtk_wed_exit(); 5158 mtk_hw_deinit(eth); 5159 5160 netif_napi_del(ð->tx_napi); 5161 netif_napi_del(ð->rx_napi); 5162 mtk_cleanup(eth); 5163 free_netdev(eth->dummy_dev); 5164 mtk_mdio_cleanup(eth); 5165 } 5166 5167 static const struct mtk_soc_data mt2701_data = { 5168 .reg_map = &mtk_reg_map, 5169 .caps = MT7623_CAPS | MTK_HWLRO, 5170 .hw_features = MTK_HW_FEATURES, 5171 .required_clks = MT7623_CLKS_BITMAP, 5172 .required_pctl = true, 5173 .version = 1, 5174 .tx = { 5175 .desc_size = sizeof(struct mtk_tx_dma), 5176 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5177 .dma_len_offset = 16, 5178 .dma_size = MTK_DMA_SIZE(2K), 5179 .fq_dma_size = MTK_DMA_SIZE(2K), 5180 }, 5181 .rx = { 5182 .desc_size = sizeof(struct mtk_rx_dma), 5183 .irq_done_mask = MTK_RX_DONE_INT, 5184 .dma_l4_valid = RX_DMA_L4_VALID, 5185 .dma_size = MTK_DMA_SIZE(2K), 5186 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5187 .dma_len_offset = 16, 5188 }, 5189 }; 5190 5191 static const struct mtk_soc_data mt7621_data = { 5192 .reg_map = &mtk_reg_map, 5193 .caps = MT7621_CAPS, 5194 .hw_features = MTK_HW_FEATURES, 5195 .required_clks = MT7621_CLKS_BITMAP, 5196 .required_pctl = false, 5197 .version = 1, 5198 .offload_version = 1, 5199 .ppe_num = 1, 5200 .hash_offset = 2, 5201 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5202 .tx = { 5203 .desc_size = sizeof(struct mtk_tx_dma), 5204 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5205 .dma_len_offset = 16, 5206 .dma_size = MTK_DMA_SIZE(2K), 5207 .fq_dma_size = MTK_DMA_SIZE(2K), 5208 }, 5209 .rx = { 5210 .desc_size = sizeof(struct mtk_rx_dma), 5211 .irq_done_mask = MTK_RX_DONE_INT, 5212 .dma_l4_valid = RX_DMA_L4_VALID, 5213 .dma_size = MTK_DMA_SIZE(2K), 5214 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5215 .dma_len_offset = 16, 5216 }, 5217 }; 5218 5219 static const struct mtk_soc_data mt7622_data = { 5220 .reg_map = &mtk_reg_map, 5221 .ana_rgc3 = 0x2028, 5222 .caps = MT7622_CAPS | MTK_HWLRO, 5223 .hw_features = MTK_HW_FEATURES, 5224 .required_clks = MT7622_CLKS_BITMAP, 5225 .required_pctl = false, 5226 .version = 1, 5227 .offload_version = 2, 5228 .ppe_num = 1, 5229 .hash_offset = 2, 5230 .has_accounting = true, 5231 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5232 .tx = { 5233 .desc_size = sizeof(struct mtk_tx_dma), 5234 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5235 .dma_len_offset = 16, 5236 .dma_size = MTK_DMA_SIZE(2K), 5237 .fq_dma_size = MTK_DMA_SIZE(2K), 5238 }, 5239 .rx = { 5240 .desc_size = sizeof(struct mtk_rx_dma), 5241 .irq_done_mask = MTK_RX_DONE_INT, 5242 .dma_l4_valid = RX_DMA_L4_VALID, 5243 .dma_size = MTK_DMA_SIZE(2K), 5244 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5245 .dma_len_offset = 16, 5246 }, 5247 }; 5248 5249 static const struct mtk_soc_data mt7623_data = { 5250 .reg_map = &mtk_reg_map, 5251 .caps = MT7623_CAPS | MTK_HWLRO, 5252 .hw_features = MTK_HW_FEATURES, 5253 .required_clks = MT7623_CLKS_BITMAP, 5254 .required_pctl = true, 5255 .version = 1, 5256 .offload_version = 1, 5257 .ppe_num = 1, 5258 .hash_offset = 2, 5259 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5260 .disable_pll_modes = true, 5261 .tx = { 5262 .desc_size = sizeof(struct mtk_tx_dma), 5263 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5264 .dma_len_offset = 16, 5265 .dma_size = MTK_DMA_SIZE(2K), 5266 .fq_dma_size = MTK_DMA_SIZE(2K), 5267 }, 5268 .rx = { 5269 .desc_size = sizeof(struct mtk_rx_dma), 5270 .irq_done_mask = MTK_RX_DONE_INT, 5271 .dma_l4_valid = RX_DMA_L4_VALID, 5272 .dma_size = MTK_DMA_SIZE(2K), 5273 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5274 .dma_len_offset = 16, 5275 }, 5276 }; 5277 5278 static const struct mtk_soc_data mt7629_data = { 5279 .reg_map = &mtk_reg_map, 5280 .ana_rgc3 = 0x128, 5281 .caps = MT7629_CAPS | MTK_HWLRO, 5282 .hw_features = MTK_HW_FEATURES, 5283 .required_clks = MT7629_CLKS_BITMAP, 5284 .required_pctl = false, 5285 .has_accounting = true, 5286 .version = 1, 5287 .tx = { 5288 .desc_size = sizeof(struct mtk_tx_dma), 5289 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5290 .dma_len_offset = 16, 5291 .dma_size = MTK_DMA_SIZE(2K), 5292 .fq_dma_size = MTK_DMA_SIZE(2K), 5293 }, 5294 .rx = { 5295 .desc_size = sizeof(struct mtk_rx_dma), 5296 .irq_done_mask = MTK_RX_DONE_INT, 5297 .dma_l4_valid = RX_DMA_L4_VALID, 5298 .dma_size = MTK_DMA_SIZE(2K), 5299 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5300 .dma_len_offset = 16, 5301 }, 5302 }; 5303 5304 static const struct mtk_soc_data mt7981_data = { 5305 .reg_map = &mt7986_reg_map, 5306 .ana_rgc3 = 0x128, 5307 .caps = MT7981_CAPS, 5308 .hw_features = MTK_HW_FEATURES, 5309 .required_clks = MT7981_CLKS_BITMAP, 5310 .required_pctl = false, 5311 .version = 2, 5312 .offload_version = 2, 5313 .ppe_num = 2, 5314 .hash_offset = 4, 5315 .has_accounting = true, 5316 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5317 .tx = { 5318 .desc_size = sizeof(struct mtk_tx_dma_v2), 5319 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5320 .dma_len_offset = 8, 5321 .dma_size = MTK_DMA_SIZE(2K), 5322 .fq_dma_size = MTK_DMA_SIZE(2K), 5323 }, 5324 .rx = { 5325 .desc_size = sizeof(struct mtk_rx_dma), 5326 .irq_done_mask = MTK_RX_DONE_INT, 5327 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5328 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5329 .dma_len_offset = 16, 5330 .dma_size = MTK_DMA_SIZE(2K), 5331 }, 5332 }; 5333 5334 static const struct mtk_soc_data mt7986_data = { 5335 .reg_map = &mt7986_reg_map, 5336 .ana_rgc3 = 0x128, 5337 .caps = MT7986_CAPS, 5338 .hw_features = MTK_HW_FEATURES, 5339 .required_clks = MT7986_CLKS_BITMAP, 5340 .required_pctl = false, 5341 .version = 2, 5342 .offload_version = 2, 5343 .ppe_num = 2, 5344 .hash_offset = 4, 5345 .has_accounting = true, 5346 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5347 .tx = { 5348 .desc_size = sizeof(struct mtk_tx_dma_v2), 5349 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5350 .dma_len_offset = 8, 5351 .dma_size = MTK_DMA_SIZE(2K), 5352 .fq_dma_size = MTK_DMA_SIZE(2K), 5353 }, 5354 .rx = { 5355 .desc_size = sizeof(struct mtk_rx_dma), 5356 .irq_done_mask = MTK_RX_DONE_INT, 5357 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5358 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5359 .dma_len_offset = 16, 5360 .dma_size = MTK_DMA_SIZE(2K), 5361 }, 5362 }; 5363 5364 static const struct mtk_soc_data mt7988_data = { 5365 .reg_map = &mt7988_reg_map, 5366 .ana_rgc3 = 0x128, 5367 .caps = MT7988_CAPS, 5368 .hw_features = MTK_HW_FEATURES, 5369 .required_clks = MT7988_CLKS_BITMAP, 5370 .required_pctl = false, 5371 .version = 3, 5372 .offload_version = 2, 5373 .ppe_num = 3, 5374 .hash_offset = 4, 5375 .has_accounting = true, 5376 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, 5377 .tx = { 5378 .desc_size = sizeof(struct mtk_tx_dma_v2), 5379 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5380 .dma_len_offset = 8, 5381 .dma_size = MTK_DMA_SIZE(2K), 5382 .fq_dma_size = MTK_DMA_SIZE(4K), 5383 }, 5384 .rx = { 5385 .desc_size = sizeof(struct mtk_rx_dma_v2), 5386 .irq_done_mask = MTK_RX_DONE_INT_V2, 5387 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5388 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5389 .dma_len_offset = 8, 5390 .dma_size = MTK_DMA_SIZE(2K), 5391 }, 5392 }; 5393 5394 static const struct mtk_soc_data rt5350_data = { 5395 .reg_map = &mt7628_reg_map, 5396 .caps = MT7628_CAPS, 5397 .hw_features = MTK_HW_FEATURES_MT7628, 5398 .required_clks = MT7628_CLKS_BITMAP, 5399 .required_pctl = false, 5400 .version = 1, 5401 .tx = { 5402 .desc_size = sizeof(struct mtk_tx_dma), 5403 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5404 .dma_len_offset = 16, 5405 .dma_size = MTK_DMA_SIZE(2K), 5406 }, 5407 .rx = { 5408 .desc_size = sizeof(struct mtk_rx_dma), 5409 .irq_done_mask = MTK_RX_DONE_INT, 5410 .dma_l4_valid = RX_DMA_L4_VALID_PDMA, 5411 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5412 .dma_len_offset = 16, 5413 .dma_size = MTK_DMA_SIZE(2K), 5414 }, 5415 }; 5416 5417 const struct of_device_id of_mtk_match[] = { 5418 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, 5419 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, 5420 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, 5421 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, 5422 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, 5423 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, 5424 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, 5425 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, 5426 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, 5427 {}, 5428 }; 5429 MODULE_DEVICE_TABLE(of, of_mtk_match); 5430 5431 static struct platform_driver mtk_driver = { 5432 .probe = mtk_probe, 5433 .remove = mtk_remove, 5434 .driver = { 5435 .name = "mtk_soc_eth", 5436 .of_match_table = of_mtk_match, 5437 }, 5438 }; 5439 5440 module_platform_driver(mtk_driver); 5441 5442 MODULE_LICENSE("GPL"); 5443 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 5444 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 5445