1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/clk.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/if_vlan.h> 19 #include <linux/reset.h> 20 #include <linux/tcp.h> 21 #include <linux/interrupt.h> 22 #include <linux/pinctrl/devinfo.h> 23 #include <linux/phylink.h> 24 #include <linux/pcs/pcs-mtk-lynxi.h> 25 #include <linux/jhash.h> 26 #include <linux/bitfield.h> 27 #include <net/dsa.h> 28 #include <net/dst_metadata.h> 29 #include <net/page_pool/helpers.h> 30 31 #include "mtk_eth_soc.h" 32 #include "mtk_wed.h" 33 34 static int mtk_msg_level = -1; 35 module_param_named(msg_level, mtk_msg_level, int, 0); 36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 37 38 #define MTK_ETHTOOL_STAT(x) { #x, \ 39 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 40 41 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 42 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 43 sizeof(u64) } 44 45 static const struct mtk_reg_map mtk_reg_map = { 46 .tx_irq_mask = 0x1a1c, 47 .tx_irq_status = 0x1a18, 48 .pdma = { 49 .rx_ptr = 0x0900, 50 .rx_cnt_cfg = 0x0904, 51 .pcrx_ptr = 0x0908, 52 .glo_cfg = 0x0a04, 53 .rst_idx = 0x0a08, 54 .delay_irq = 0x0a0c, 55 .irq_status = 0x0a20, 56 .irq_mask = 0x0a28, 57 .adma_rx_dbg0 = 0x0a38, 58 .int_grp = 0x0a50, 59 }, 60 .qdma = { 61 .qtx_cfg = 0x1800, 62 .qtx_sch = 0x1804, 63 .rx_ptr = 0x1900, 64 .rx_cnt_cfg = 0x1904, 65 .qcrx_ptr = 0x1908, 66 .glo_cfg = 0x1a04, 67 .rst_idx = 0x1a08, 68 .delay_irq = 0x1a0c, 69 .fc_th = 0x1a10, 70 .tx_sch_rate = 0x1a14, 71 .int_grp = 0x1a20, 72 .hred = 0x1a44, 73 .ctx_ptr = 0x1b00, 74 .dtx_ptr = 0x1b04, 75 .crx_ptr = 0x1b10, 76 .drx_ptr = 0x1b14, 77 .fq_head = 0x1b20, 78 .fq_tail = 0x1b24, 79 .fq_count = 0x1b28, 80 .fq_blen = 0x1b2c, 81 }, 82 .gdm1_cnt = 0x2400, 83 .gdma_to_ppe = 0x4444, 84 .ppe_base = 0x0c00, 85 .wdma_base = { 86 [0] = 0x2800, 87 [1] = 0x2c00, 88 }, 89 .pse_iq_sta = 0x0110, 90 .pse_oq_sta = 0x0118, 91 }; 92 93 static const struct mtk_reg_map mt7628_reg_map = { 94 .tx_irq_mask = 0x0a28, 95 .tx_irq_status = 0x0a20, 96 .pdma = { 97 .rx_ptr = 0x0900, 98 .rx_cnt_cfg = 0x0904, 99 .pcrx_ptr = 0x0908, 100 .glo_cfg = 0x0a04, 101 .rst_idx = 0x0a08, 102 .delay_irq = 0x0a0c, 103 .irq_status = 0x0a20, 104 .irq_mask = 0x0a28, 105 .int_grp = 0x0a50, 106 }, 107 }; 108 109 static const struct mtk_reg_map mt7986_reg_map = { 110 .tx_irq_mask = 0x461c, 111 .tx_irq_status = 0x4618, 112 .pdma = { 113 .rx_ptr = 0x6100, 114 .rx_cnt_cfg = 0x6104, 115 .pcrx_ptr = 0x6108, 116 .glo_cfg = 0x6204, 117 .rst_idx = 0x6208, 118 .delay_irq = 0x620c, 119 .irq_status = 0x6220, 120 .irq_mask = 0x6228, 121 .adma_rx_dbg0 = 0x6238, 122 .int_grp = 0x6250, 123 }, 124 .qdma = { 125 .qtx_cfg = 0x4400, 126 .qtx_sch = 0x4404, 127 .rx_ptr = 0x4500, 128 .rx_cnt_cfg = 0x4504, 129 .qcrx_ptr = 0x4508, 130 .glo_cfg = 0x4604, 131 .rst_idx = 0x4608, 132 .delay_irq = 0x460c, 133 .fc_th = 0x4610, 134 .int_grp = 0x4620, 135 .hred = 0x4644, 136 .ctx_ptr = 0x4700, 137 .dtx_ptr = 0x4704, 138 .crx_ptr = 0x4710, 139 .drx_ptr = 0x4714, 140 .fq_head = 0x4720, 141 .fq_tail = 0x4724, 142 .fq_count = 0x4728, 143 .fq_blen = 0x472c, 144 .tx_sch_rate = 0x4798, 145 }, 146 .gdm1_cnt = 0x1c00, 147 .gdma_to_ppe = 0x3333, 148 .ppe_base = 0x2000, 149 .wdma_base = { 150 [0] = 0x4800, 151 [1] = 0x4c00, 152 }, 153 .pse_iq_sta = 0x0180, 154 .pse_oq_sta = 0x01a0, 155 }; 156 157 static const struct mtk_reg_map mt7988_reg_map = { 158 .tx_irq_mask = 0x461c, 159 .tx_irq_status = 0x4618, 160 .pdma = { 161 .rx_ptr = 0x6900, 162 .rx_cnt_cfg = 0x6904, 163 .pcrx_ptr = 0x6908, 164 .glo_cfg = 0x6a04, 165 .rst_idx = 0x6a08, 166 .delay_irq = 0x6a0c, 167 .irq_status = 0x6a20, 168 .irq_mask = 0x6a28, 169 .adma_rx_dbg0 = 0x6a38, 170 .int_grp = 0x6a50, 171 }, 172 .qdma = { 173 .qtx_cfg = 0x4400, 174 .qtx_sch = 0x4404, 175 .rx_ptr = 0x4500, 176 .rx_cnt_cfg = 0x4504, 177 .qcrx_ptr = 0x4508, 178 .glo_cfg = 0x4604, 179 .rst_idx = 0x4608, 180 .delay_irq = 0x460c, 181 .fc_th = 0x4610, 182 .int_grp = 0x4620, 183 .hred = 0x4644, 184 .ctx_ptr = 0x4700, 185 .dtx_ptr = 0x4704, 186 .crx_ptr = 0x4710, 187 .drx_ptr = 0x4714, 188 .fq_head = 0x4720, 189 .fq_tail = 0x4724, 190 .fq_count = 0x4728, 191 .fq_blen = 0x472c, 192 .tx_sch_rate = 0x4798, 193 }, 194 .gdm1_cnt = 0x1c00, 195 .gdma_to_ppe = 0x3333, 196 .ppe_base = 0x2000, 197 .wdma_base = { 198 [0] = 0x4800, 199 [1] = 0x4c00, 200 [2] = 0x5000, 201 }, 202 .pse_iq_sta = 0x0180, 203 .pse_oq_sta = 0x01a0, 204 }; 205 206 /* strings used by ethtool */ 207 static const struct mtk_ethtool_stats { 208 char str[ETH_GSTRING_LEN]; 209 u32 offset; 210 } mtk_ethtool_stats[] = { 211 MTK_ETHTOOL_STAT(tx_bytes), 212 MTK_ETHTOOL_STAT(tx_packets), 213 MTK_ETHTOOL_STAT(tx_skip), 214 MTK_ETHTOOL_STAT(tx_collisions), 215 MTK_ETHTOOL_STAT(rx_bytes), 216 MTK_ETHTOOL_STAT(rx_packets), 217 MTK_ETHTOOL_STAT(rx_overflow), 218 MTK_ETHTOOL_STAT(rx_fcs_errors), 219 MTK_ETHTOOL_STAT(rx_short_errors), 220 MTK_ETHTOOL_STAT(rx_long_errors), 221 MTK_ETHTOOL_STAT(rx_checksum_errors), 222 MTK_ETHTOOL_STAT(rx_flow_control_packets), 223 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 224 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 225 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 226 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 227 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 228 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 229 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 230 }; 231 232 static const char * const mtk_clks_source_name[] = { 233 "ethif", 234 "sgmiitop", 235 "esw", 236 "gp0", 237 "gp1", 238 "gp2", 239 "gp3", 240 "xgp1", 241 "xgp2", 242 "xgp3", 243 "crypto", 244 "fe", 245 "trgpll", 246 "sgmii_tx250m", 247 "sgmii_rx250m", 248 "sgmii_cdr_ref", 249 "sgmii_cdr_fb", 250 "sgmii2_tx250m", 251 "sgmii2_rx250m", 252 "sgmii2_cdr_ref", 253 "sgmii2_cdr_fb", 254 "sgmii_ck", 255 "eth2pll", 256 "wocpu0", 257 "wocpu1", 258 "netsys0", 259 "netsys1", 260 "ethwarp_wocpu2", 261 "ethwarp_wocpu1", 262 "ethwarp_wocpu0", 263 "top_usxgmii0_sel", 264 "top_usxgmii1_sel", 265 "top_sgm0_sel", 266 "top_sgm1_sel", 267 "top_xfi_phy0_xtal_sel", 268 "top_xfi_phy1_xtal_sel", 269 "top_eth_gmii_sel", 270 "top_eth_refck_50m_sel", 271 "top_eth_sys_200m_sel", 272 "top_eth_sys_sel", 273 "top_eth_xgmii_sel", 274 "top_eth_mii_sel", 275 "top_netsys_sel", 276 "top_netsys_500m_sel", 277 "top_netsys_pao_2x_sel", 278 "top_netsys_sync_250m_sel", 279 "top_netsys_ppefb_250m_sel", 280 "top_netsys_warp_sel", 281 }; 282 283 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 284 { 285 __raw_writel(val, eth->base + reg); 286 } 287 288 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 289 { 290 return __raw_readl(eth->base + reg); 291 } 292 293 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) 294 { 295 u32 val; 296 297 val = mtk_r32(eth, reg); 298 val &= ~mask; 299 val |= set; 300 mtk_w32(eth, val, reg); 301 return reg; 302 } 303 304 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 305 { 306 unsigned long t_start = jiffies; 307 308 while (1) { 309 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 310 return 0; 311 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 312 break; 313 cond_resched(); 314 } 315 316 dev_err(eth->dev, "mdio: MDIO timeout\n"); 317 return -ETIMEDOUT; 318 } 319 320 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 321 u32 write_data) 322 { 323 int ret; 324 325 ret = mtk_mdio_busy_wait(eth); 326 if (ret < 0) 327 return ret; 328 329 mtk_w32(eth, PHY_IAC_ACCESS | 330 PHY_IAC_START_C22 | 331 PHY_IAC_CMD_WRITE | 332 PHY_IAC_REG(phy_reg) | 333 PHY_IAC_ADDR(phy_addr) | 334 PHY_IAC_DATA(write_data), 335 MTK_PHY_IAC); 336 337 ret = mtk_mdio_busy_wait(eth); 338 if (ret < 0) 339 return ret; 340 341 return 0; 342 } 343 344 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 345 u32 devad, u32 phy_reg, u32 write_data) 346 { 347 int ret; 348 349 ret = mtk_mdio_busy_wait(eth); 350 if (ret < 0) 351 return ret; 352 353 mtk_w32(eth, PHY_IAC_ACCESS | 354 PHY_IAC_START_C45 | 355 PHY_IAC_CMD_C45_ADDR | 356 PHY_IAC_REG(devad) | 357 PHY_IAC_ADDR(phy_addr) | 358 PHY_IAC_DATA(phy_reg), 359 MTK_PHY_IAC); 360 361 ret = mtk_mdio_busy_wait(eth); 362 if (ret < 0) 363 return ret; 364 365 mtk_w32(eth, PHY_IAC_ACCESS | 366 PHY_IAC_START_C45 | 367 PHY_IAC_CMD_WRITE | 368 PHY_IAC_REG(devad) | 369 PHY_IAC_ADDR(phy_addr) | 370 PHY_IAC_DATA(write_data), 371 MTK_PHY_IAC); 372 373 ret = mtk_mdio_busy_wait(eth); 374 if (ret < 0) 375 return ret; 376 377 return 0; 378 } 379 380 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 381 { 382 int ret; 383 384 ret = mtk_mdio_busy_wait(eth); 385 if (ret < 0) 386 return ret; 387 388 mtk_w32(eth, PHY_IAC_ACCESS | 389 PHY_IAC_START_C22 | 390 PHY_IAC_CMD_C22_READ | 391 PHY_IAC_REG(phy_reg) | 392 PHY_IAC_ADDR(phy_addr), 393 MTK_PHY_IAC); 394 395 ret = mtk_mdio_busy_wait(eth); 396 if (ret < 0) 397 return ret; 398 399 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 400 } 401 402 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 403 u32 devad, u32 phy_reg) 404 { 405 int ret; 406 407 ret = mtk_mdio_busy_wait(eth); 408 if (ret < 0) 409 return ret; 410 411 mtk_w32(eth, PHY_IAC_ACCESS | 412 PHY_IAC_START_C45 | 413 PHY_IAC_CMD_C45_ADDR | 414 PHY_IAC_REG(devad) | 415 PHY_IAC_ADDR(phy_addr) | 416 PHY_IAC_DATA(phy_reg), 417 MTK_PHY_IAC); 418 419 ret = mtk_mdio_busy_wait(eth); 420 if (ret < 0) 421 return ret; 422 423 mtk_w32(eth, PHY_IAC_ACCESS | 424 PHY_IAC_START_C45 | 425 PHY_IAC_CMD_C45_READ | 426 PHY_IAC_REG(devad) | 427 PHY_IAC_ADDR(phy_addr), 428 MTK_PHY_IAC); 429 430 ret = mtk_mdio_busy_wait(eth); 431 if (ret < 0) 432 return ret; 433 434 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 435 } 436 437 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 438 int phy_reg, u16 val) 439 { 440 struct mtk_eth *eth = bus->priv; 441 442 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 443 } 444 445 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 446 int devad, int phy_reg, u16 val) 447 { 448 struct mtk_eth *eth = bus->priv; 449 450 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 451 } 452 453 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 454 { 455 struct mtk_eth *eth = bus->priv; 456 457 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 458 } 459 460 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 461 int phy_reg) 462 { 463 struct mtk_eth *eth = bus->priv; 464 465 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 466 } 467 468 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 469 phy_interface_t interface) 470 { 471 u32 val; 472 473 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 474 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 475 476 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 477 ETHSYS_TRGMII_MT7621_MASK, val); 478 479 return 0; 480 } 481 482 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 483 phy_interface_t interface) 484 { 485 int ret; 486 487 if (interface == PHY_INTERFACE_MODE_TRGMII) { 488 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 489 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); 490 if (ret) 491 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 492 return; 493 } 494 495 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); 496 } 497 498 static void mtk_setup_bridge_switch(struct mtk_eth *eth) 499 { 500 /* Force Port1 XGMAC Link Up */ 501 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), 502 MTK_XGMAC_STS(MTK_GMAC1_ID)); 503 504 /* Adjust GSW bridge IPG to 11 */ 505 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, 506 (GSW_IPG_11 << GSWTX_IPG_SHIFT) | 507 (GSW_IPG_11 << GSWRX_IPG_SHIFT), 508 MTK_GSW_CFG); 509 } 510 511 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 512 phy_interface_t interface) 513 { 514 struct mtk_mac *mac = container_of(config, struct mtk_mac, 515 phylink_config); 516 struct mtk_eth *eth = mac->hw; 517 unsigned int sid; 518 519 if (interface == PHY_INTERFACE_MODE_SGMII || 520 phy_interface_mode_is_8023z(interface)) { 521 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 522 0 : mac->id; 523 524 return eth->sgmii_pcs[sid]; 525 } 526 527 return NULL; 528 } 529 530 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 531 const struct phylink_link_state *state) 532 { 533 struct mtk_mac *mac = container_of(config, struct mtk_mac, 534 phylink_config); 535 struct mtk_eth *eth = mac->hw; 536 int val, ge_mode, err = 0; 537 u32 i; 538 539 /* MT76x8 has no hardware settings between for the MAC */ 540 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 541 mac->interface != state->interface) { 542 /* Setup soc pin functions */ 543 switch (state->interface) { 544 case PHY_INTERFACE_MODE_TRGMII: 545 case PHY_INTERFACE_MODE_RGMII_TXID: 546 case PHY_INTERFACE_MODE_RGMII_RXID: 547 case PHY_INTERFACE_MODE_RGMII_ID: 548 case PHY_INTERFACE_MODE_RGMII: 549 case PHY_INTERFACE_MODE_MII: 550 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 551 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 552 if (err) 553 goto init_err; 554 } 555 break; 556 case PHY_INTERFACE_MODE_1000BASEX: 557 case PHY_INTERFACE_MODE_2500BASEX: 558 case PHY_INTERFACE_MODE_SGMII: 559 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 560 if (err) 561 goto init_err; 562 break; 563 case PHY_INTERFACE_MODE_GMII: 564 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 565 err = mtk_gmac_gephy_path_setup(eth, mac->id); 566 if (err) 567 goto init_err; 568 } 569 break; 570 case PHY_INTERFACE_MODE_INTERNAL: 571 break; 572 default: 573 goto err_phy; 574 } 575 576 /* Setup clock for 1st gmac */ 577 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 578 !phy_interface_mode_is_8023z(state->interface) && 579 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 580 if (MTK_HAS_CAPS(mac->hw->soc->caps, 581 MTK_TRGMII_MT7621_CLK)) { 582 if (mt7621_gmac0_rgmii_adjust(mac->hw, 583 state->interface)) 584 goto err_phy; 585 } else { 586 mtk_gmac0_rgmii_adjust(mac->hw, 587 state->interface); 588 589 /* mt7623_pad_clk_setup */ 590 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 591 mtk_w32(mac->hw, 592 TD_DM_DRVP(8) | TD_DM_DRVN(8), 593 TRGMII_TD_ODT(i)); 594 595 /* Assert/release MT7623 RXC reset */ 596 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 597 TRGMII_RCK_CTRL); 598 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 599 } 600 } 601 602 switch (state->interface) { 603 case PHY_INTERFACE_MODE_MII: 604 case PHY_INTERFACE_MODE_GMII: 605 ge_mode = 1; 606 break; 607 default: 608 ge_mode = 0; 609 break; 610 } 611 612 /* put the gmac into the right mode */ 613 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 614 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 615 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 616 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 617 618 mac->interface = state->interface; 619 } 620 621 /* SGMII */ 622 if (state->interface == PHY_INTERFACE_MODE_SGMII || 623 phy_interface_mode_is_8023z(state->interface)) { 624 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 625 * being setup done. 626 */ 627 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 628 629 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 630 SYSCFG0_SGMII_MASK, 631 ~(u32)SYSCFG0_SGMII_MASK); 632 633 /* Save the syscfg0 value for mac_finish */ 634 mac->syscfg0 = val; 635 } else if (phylink_autoneg_inband(mode)) { 636 dev_err(eth->dev, 637 "In-band mode not supported in non SGMII mode!\n"); 638 return; 639 } 640 641 /* Setup gmac */ 642 if (mtk_is_netsys_v3_or_greater(eth) && 643 mac->interface == PHY_INTERFACE_MODE_INTERNAL) { 644 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); 645 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); 646 647 mtk_setup_bridge_switch(eth); 648 } 649 650 return; 651 652 err_phy: 653 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 654 mac->id, phy_modes(state->interface)); 655 return; 656 657 init_err: 658 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 659 mac->id, phy_modes(state->interface), err); 660 } 661 662 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 663 phy_interface_t interface) 664 { 665 struct mtk_mac *mac = container_of(config, struct mtk_mac, 666 phylink_config); 667 struct mtk_eth *eth = mac->hw; 668 u32 mcr_cur, mcr_new; 669 670 /* Enable SGMII */ 671 if (interface == PHY_INTERFACE_MODE_SGMII || 672 phy_interface_mode_is_8023z(interface)) 673 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 674 SYSCFG0_SGMII_MASK, mac->syscfg0); 675 676 /* Setup gmac */ 677 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 678 mcr_new = mcr_cur; 679 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 680 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK | 681 MAC_MCR_RX_FIFO_CLR_DIS; 682 683 /* Only update control register when needed! */ 684 if (mcr_new != mcr_cur) 685 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 686 687 return 0; 688 } 689 690 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 691 phy_interface_t interface) 692 { 693 struct mtk_mac *mac = container_of(config, struct mtk_mac, 694 phylink_config); 695 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 696 697 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 698 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 699 } 700 701 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 702 int speed) 703 { 704 const struct mtk_soc_data *soc = eth->soc; 705 u32 ofs, val; 706 707 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 708 return; 709 710 val = MTK_QTX_SCH_MIN_RATE_EN | 711 /* minimum: 10 Mbps */ 712 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 713 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 714 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 715 if (mtk_is_netsys_v1(eth)) 716 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 717 718 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 719 switch (speed) { 720 case SPEED_10: 721 val |= MTK_QTX_SCH_MAX_RATE_EN | 722 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 723 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 724 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 725 break; 726 case SPEED_100: 727 val |= MTK_QTX_SCH_MAX_RATE_EN | 728 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 729 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 730 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 731 break; 732 case SPEED_1000: 733 val |= MTK_QTX_SCH_MAX_RATE_EN | 734 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 735 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 736 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 737 break; 738 default: 739 break; 740 } 741 } else { 742 switch (speed) { 743 case SPEED_10: 744 val |= MTK_QTX_SCH_MAX_RATE_EN | 745 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 746 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 747 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 748 break; 749 case SPEED_100: 750 val |= MTK_QTX_SCH_MAX_RATE_EN | 751 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 752 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 753 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 754 break; 755 case SPEED_1000: 756 val |= MTK_QTX_SCH_MAX_RATE_EN | 757 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 758 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 759 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 760 break; 761 default: 762 break; 763 } 764 } 765 766 ofs = MTK_QTX_OFFSET * idx; 767 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 768 } 769 770 static void mtk_mac_link_up(struct phylink_config *config, 771 struct phy_device *phy, 772 unsigned int mode, phy_interface_t interface, 773 int speed, int duplex, bool tx_pause, bool rx_pause) 774 { 775 struct mtk_mac *mac = container_of(config, struct mtk_mac, 776 phylink_config); 777 u32 mcr; 778 779 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 780 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 781 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 782 MAC_MCR_FORCE_RX_FC); 783 784 /* Configure speed */ 785 mac->speed = speed; 786 switch (speed) { 787 case SPEED_2500: 788 case SPEED_1000: 789 mcr |= MAC_MCR_SPEED_1000; 790 break; 791 case SPEED_100: 792 mcr |= MAC_MCR_SPEED_100; 793 break; 794 } 795 796 /* Configure duplex */ 797 if (duplex == DUPLEX_FULL) 798 mcr |= MAC_MCR_FORCE_DPX; 799 800 /* Configure pause modes - phylink will avoid these for half duplex */ 801 if (tx_pause) 802 mcr |= MAC_MCR_FORCE_TX_FC; 803 if (rx_pause) 804 mcr |= MAC_MCR_FORCE_RX_FC; 805 806 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 807 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 808 } 809 810 static const struct phylink_mac_ops mtk_phylink_ops = { 811 .mac_select_pcs = mtk_mac_select_pcs, 812 .mac_config = mtk_mac_config, 813 .mac_finish = mtk_mac_finish, 814 .mac_link_down = mtk_mac_link_down, 815 .mac_link_up = mtk_mac_link_up, 816 }; 817 818 static int mtk_mdio_init(struct mtk_eth *eth) 819 { 820 unsigned int max_clk = 2500000, divider; 821 struct device_node *mii_np; 822 int ret; 823 u32 val; 824 825 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 826 if (!mii_np) { 827 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 828 return -ENODEV; 829 } 830 831 if (!of_device_is_available(mii_np)) { 832 ret = -ENODEV; 833 goto err_put_node; 834 } 835 836 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 837 if (!eth->mii_bus) { 838 ret = -ENOMEM; 839 goto err_put_node; 840 } 841 842 eth->mii_bus->name = "mdio"; 843 eth->mii_bus->read = mtk_mdio_read_c22; 844 eth->mii_bus->write = mtk_mdio_write_c22; 845 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 846 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 847 eth->mii_bus->priv = eth; 848 eth->mii_bus->parent = eth->dev; 849 850 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 851 852 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { 853 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { 854 dev_err(eth->dev, "MDIO clock frequency out of range"); 855 ret = -EINVAL; 856 goto err_put_node; 857 } 858 max_clk = val; 859 } 860 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 861 862 /* Configure MDC Turbo Mode */ 863 if (mtk_is_netsys_v3_or_greater(eth)) 864 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); 865 866 /* Configure MDC Divider */ 867 val = FIELD_PREP(PPSC_MDC_CFG, divider); 868 if (!mtk_is_netsys_v3_or_greater(eth)) 869 val |= PPSC_MDC_TURBO; 870 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); 871 872 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); 873 874 ret = of_mdiobus_register(eth->mii_bus, mii_np); 875 876 err_put_node: 877 of_node_put(mii_np); 878 return ret; 879 } 880 881 static void mtk_mdio_cleanup(struct mtk_eth *eth) 882 { 883 if (!eth->mii_bus) 884 return; 885 886 mdiobus_unregister(eth->mii_bus); 887 } 888 889 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 890 { 891 unsigned long flags; 892 u32 val; 893 894 spin_lock_irqsave(ð->tx_irq_lock, flags); 895 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 896 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 897 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 898 } 899 900 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 901 { 902 unsigned long flags; 903 u32 val; 904 905 spin_lock_irqsave(ð->tx_irq_lock, flags); 906 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 907 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 908 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 909 } 910 911 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 912 { 913 unsigned long flags; 914 u32 val; 915 916 spin_lock_irqsave(ð->rx_irq_lock, flags); 917 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 918 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 919 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 920 } 921 922 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 923 { 924 unsigned long flags; 925 u32 val; 926 927 spin_lock_irqsave(ð->rx_irq_lock, flags); 928 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 929 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 930 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 931 } 932 933 static int mtk_set_mac_address(struct net_device *dev, void *p) 934 { 935 int ret = eth_mac_addr(dev, p); 936 struct mtk_mac *mac = netdev_priv(dev); 937 struct mtk_eth *eth = mac->hw; 938 const char *macaddr = dev->dev_addr; 939 940 if (ret) 941 return ret; 942 943 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 944 return -EBUSY; 945 946 spin_lock_bh(&mac->hw->page_lock); 947 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 948 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 949 MT7628_SDM_MAC_ADRH); 950 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 951 (macaddr[4] << 8) | macaddr[5], 952 MT7628_SDM_MAC_ADRL); 953 } else { 954 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 955 MTK_GDMA_MAC_ADRH(mac->id)); 956 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 957 (macaddr[4] << 8) | macaddr[5], 958 MTK_GDMA_MAC_ADRL(mac->id)); 959 } 960 spin_unlock_bh(&mac->hw->page_lock); 961 962 return 0; 963 } 964 965 void mtk_stats_update_mac(struct mtk_mac *mac) 966 { 967 struct mtk_hw_stats *hw_stats = mac->hw_stats; 968 struct mtk_eth *eth = mac->hw; 969 970 u64_stats_update_begin(&hw_stats->syncp); 971 972 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 973 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 974 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 975 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 976 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 977 hw_stats->rx_checksum_errors += 978 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 979 } else { 980 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 981 unsigned int offs = hw_stats->reg_offset; 982 u64 stats; 983 984 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 985 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 986 if (stats) 987 hw_stats->rx_bytes += (stats << 32); 988 hw_stats->rx_packets += 989 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 990 hw_stats->rx_overflow += 991 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 992 hw_stats->rx_fcs_errors += 993 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 994 hw_stats->rx_short_errors += 995 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 996 hw_stats->rx_long_errors += 997 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 998 hw_stats->rx_checksum_errors += 999 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 1000 hw_stats->rx_flow_control_packets += 1001 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 1002 1003 if (mtk_is_netsys_v3_or_greater(eth)) { 1004 hw_stats->tx_skip += 1005 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); 1006 hw_stats->tx_collisions += 1007 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); 1008 hw_stats->tx_bytes += 1009 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); 1010 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); 1011 if (stats) 1012 hw_stats->tx_bytes += (stats << 32); 1013 hw_stats->tx_packets += 1014 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); 1015 } else { 1016 hw_stats->tx_skip += 1017 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 1018 hw_stats->tx_collisions += 1019 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 1020 hw_stats->tx_bytes += 1021 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 1022 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 1023 if (stats) 1024 hw_stats->tx_bytes += (stats << 32); 1025 hw_stats->tx_packets += 1026 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 1027 } 1028 } 1029 1030 u64_stats_update_end(&hw_stats->syncp); 1031 } 1032 1033 static void mtk_stats_update(struct mtk_eth *eth) 1034 { 1035 int i; 1036 1037 for (i = 0; i < MTK_MAX_DEVS; i++) { 1038 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 1039 continue; 1040 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 1041 mtk_stats_update_mac(eth->mac[i]); 1042 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 1043 } 1044 } 1045 } 1046 1047 static void mtk_get_stats64(struct net_device *dev, 1048 struct rtnl_link_stats64 *storage) 1049 { 1050 struct mtk_mac *mac = netdev_priv(dev); 1051 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1052 unsigned int start; 1053 1054 if (netif_running(dev) && netif_device_present(dev)) { 1055 if (spin_trylock_bh(&hw_stats->stats_lock)) { 1056 mtk_stats_update_mac(mac); 1057 spin_unlock_bh(&hw_stats->stats_lock); 1058 } 1059 } 1060 1061 do { 1062 start = u64_stats_fetch_begin(&hw_stats->syncp); 1063 storage->rx_packets = hw_stats->rx_packets; 1064 storage->tx_packets = hw_stats->tx_packets; 1065 storage->rx_bytes = hw_stats->rx_bytes; 1066 storage->tx_bytes = hw_stats->tx_bytes; 1067 storage->collisions = hw_stats->tx_collisions; 1068 storage->rx_length_errors = hw_stats->rx_short_errors + 1069 hw_stats->rx_long_errors; 1070 storage->rx_over_errors = hw_stats->rx_overflow; 1071 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1072 storage->rx_errors = hw_stats->rx_checksum_errors; 1073 storage->tx_aborted_errors = hw_stats->tx_skip; 1074 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1075 1076 storage->tx_errors = dev->stats.tx_errors; 1077 storage->rx_dropped = dev->stats.rx_dropped; 1078 storage->tx_dropped = dev->stats.tx_dropped; 1079 } 1080 1081 static inline int mtk_max_frag_size(int mtu) 1082 { 1083 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1084 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1085 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1086 1087 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1088 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1089 } 1090 1091 static inline int mtk_max_buf_size(int frag_size) 1092 { 1093 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1094 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1095 1096 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1097 1098 return buf_size; 1099 } 1100 1101 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1102 struct mtk_rx_dma_v2 *dma_rxd) 1103 { 1104 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1105 if (!(rxd->rxd2 & RX_DMA_DONE)) 1106 return false; 1107 1108 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1109 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1110 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1111 if (mtk_is_netsys_v2_or_greater(eth)) { 1112 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1113 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1114 } 1115 1116 return true; 1117 } 1118 1119 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1120 { 1121 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1122 unsigned long data; 1123 1124 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1125 get_order(size)); 1126 1127 return (void *)data; 1128 } 1129 1130 /* the qdma core needs scratch memory to be setup */ 1131 static int mtk_init_fq_dma(struct mtk_eth *eth) 1132 { 1133 const struct mtk_soc_data *soc = eth->soc; 1134 dma_addr_t phy_ring_tail; 1135 int cnt = MTK_QDMA_RING_SIZE; 1136 dma_addr_t dma_addr; 1137 int i; 1138 1139 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) 1140 eth->scratch_ring = eth->sram_base; 1141 else 1142 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1143 cnt * soc->txrx.txd_size, 1144 ð->phy_scratch_ring, 1145 GFP_KERNEL); 1146 if (unlikely(!eth->scratch_ring)) 1147 return -ENOMEM; 1148 1149 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1150 if (unlikely(!eth->scratch_head)) 1151 return -ENOMEM; 1152 1153 dma_addr = dma_map_single(eth->dma_dev, 1154 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 1155 DMA_FROM_DEVICE); 1156 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1157 return -ENOMEM; 1158 1159 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 1160 1161 for (i = 0; i < cnt; i++) { 1162 struct mtk_tx_dma_v2 *txd; 1163 1164 txd = eth->scratch_ring + i * soc->txrx.txd_size; 1165 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1166 if (i < cnt - 1) 1167 txd->txd2 = eth->phy_scratch_ring + 1168 (i + 1) * soc->txrx.txd_size; 1169 1170 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1171 txd->txd4 = 0; 1172 if (mtk_is_netsys_v2_or_greater(eth)) { 1173 txd->txd5 = 0; 1174 txd->txd6 = 0; 1175 txd->txd7 = 0; 1176 txd->txd8 = 0; 1177 } 1178 } 1179 1180 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1181 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1182 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1183 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1184 1185 return 0; 1186 } 1187 1188 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1189 { 1190 return ring->dma + (desc - ring->phys); 1191 } 1192 1193 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1194 void *txd, u32 txd_size) 1195 { 1196 int idx = (txd - ring->dma) / txd_size; 1197 1198 return &ring->buf[idx]; 1199 } 1200 1201 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1202 struct mtk_tx_dma *dma) 1203 { 1204 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1205 } 1206 1207 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1208 { 1209 return (dma - ring->dma) / txd_size; 1210 } 1211 1212 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1213 struct xdp_frame_bulk *bq, bool napi) 1214 { 1215 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1216 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1217 dma_unmap_single(eth->dma_dev, 1218 dma_unmap_addr(tx_buf, dma_addr0), 1219 dma_unmap_len(tx_buf, dma_len0), 1220 DMA_TO_DEVICE); 1221 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1222 dma_unmap_page(eth->dma_dev, 1223 dma_unmap_addr(tx_buf, dma_addr0), 1224 dma_unmap_len(tx_buf, dma_len0), 1225 DMA_TO_DEVICE); 1226 } 1227 } else { 1228 if (dma_unmap_len(tx_buf, dma_len0)) { 1229 dma_unmap_page(eth->dma_dev, 1230 dma_unmap_addr(tx_buf, dma_addr0), 1231 dma_unmap_len(tx_buf, dma_len0), 1232 DMA_TO_DEVICE); 1233 } 1234 1235 if (dma_unmap_len(tx_buf, dma_len1)) { 1236 dma_unmap_page(eth->dma_dev, 1237 dma_unmap_addr(tx_buf, dma_addr1), 1238 dma_unmap_len(tx_buf, dma_len1), 1239 DMA_TO_DEVICE); 1240 } 1241 } 1242 1243 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1244 if (tx_buf->type == MTK_TYPE_SKB) { 1245 struct sk_buff *skb = tx_buf->data; 1246 1247 if (napi) 1248 napi_consume_skb(skb, napi); 1249 else 1250 dev_kfree_skb_any(skb); 1251 } else { 1252 struct xdp_frame *xdpf = tx_buf->data; 1253 1254 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1255 xdp_return_frame_rx_napi(xdpf); 1256 else if (bq) 1257 xdp_return_frame_bulk(xdpf, bq); 1258 else 1259 xdp_return_frame(xdpf); 1260 } 1261 } 1262 tx_buf->flags = 0; 1263 tx_buf->data = NULL; 1264 } 1265 1266 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1267 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1268 size_t size, int idx) 1269 { 1270 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1271 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1272 dma_unmap_len_set(tx_buf, dma_len0, size); 1273 } else { 1274 if (idx & 1) { 1275 txd->txd3 = mapped_addr; 1276 txd->txd2 |= TX_DMA_PLEN1(size); 1277 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1278 dma_unmap_len_set(tx_buf, dma_len1, size); 1279 } else { 1280 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1281 txd->txd1 = mapped_addr; 1282 txd->txd2 = TX_DMA_PLEN0(size); 1283 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1284 dma_unmap_len_set(tx_buf, dma_len0, size); 1285 } 1286 } 1287 } 1288 1289 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1290 struct mtk_tx_dma_desc_info *info) 1291 { 1292 struct mtk_mac *mac = netdev_priv(dev); 1293 struct mtk_eth *eth = mac->hw; 1294 struct mtk_tx_dma *desc = txd; 1295 u32 data; 1296 1297 WRITE_ONCE(desc->txd1, info->addr); 1298 1299 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1300 FIELD_PREP(TX_DMA_PQID, info->qid); 1301 if (info->last) 1302 data |= TX_DMA_LS0; 1303 WRITE_ONCE(desc->txd3, data); 1304 1305 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1306 if (info->first) { 1307 if (info->gso) 1308 data |= TX_DMA_TSO; 1309 /* tx checksum offload */ 1310 if (info->csum) 1311 data |= TX_DMA_CHKSUM; 1312 /* vlan header offload */ 1313 if (info->vlan) 1314 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1315 } 1316 WRITE_ONCE(desc->txd4, data); 1317 } 1318 1319 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1320 struct mtk_tx_dma_desc_info *info) 1321 { 1322 struct mtk_mac *mac = netdev_priv(dev); 1323 struct mtk_tx_dma_v2 *desc = txd; 1324 struct mtk_eth *eth = mac->hw; 1325 u32 data; 1326 1327 WRITE_ONCE(desc->txd1, info->addr); 1328 1329 data = TX_DMA_PLEN0(info->size); 1330 if (info->last) 1331 data |= TX_DMA_LS0; 1332 1333 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 1334 data |= TX_DMA_PREP_ADDR64(info->addr); 1335 1336 WRITE_ONCE(desc->txd3, data); 1337 1338 /* set forward port */ 1339 switch (mac->id) { 1340 case MTK_GMAC1_ID: 1341 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; 1342 break; 1343 case MTK_GMAC2_ID: 1344 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; 1345 break; 1346 case MTK_GMAC3_ID: 1347 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; 1348 break; 1349 } 1350 1351 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1352 WRITE_ONCE(desc->txd4, data); 1353 1354 data = 0; 1355 if (info->first) { 1356 if (info->gso) 1357 data |= TX_DMA_TSO_V2; 1358 /* tx checksum offload */ 1359 if (info->csum) 1360 data |= TX_DMA_CHKSUM_V2; 1361 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) 1362 data |= TX_DMA_SPTAG_V3; 1363 } 1364 WRITE_ONCE(desc->txd5, data); 1365 1366 data = 0; 1367 if (info->first && info->vlan) 1368 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1369 WRITE_ONCE(desc->txd6, data); 1370 1371 WRITE_ONCE(desc->txd7, 0); 1372 WRITE_ONCE(desc->txd8, 0); 1373 } 1374 1375 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1376 struct mtk_tx_dma_desc_info *info) 1377 { 1378 struct mtk_mac *mac = netdev_priv(dev); 1379 struct mtk_eth *eth = mac->hw; 1380 1381 if (mtk_is_netsys_v2_or_greater(eth)) 1382 mtk_tx_set_dma_desc_v2(dev, txd, info); 1383 else 1384 mtk_tx_set_dma_desc_v1(dev, txd, info); 1385 } 1386 1387 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1388 int tx_num, struct mtk_tx_ring *ring, bool gso) 1389 { 1390 struct mtk_tx_dma_desc_info txd_info = { 1391 .size = skb_headlen(skb), 1392 .gso = gso, 1393 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1394 .vlan = skb_vlan_tag_present(skb), 1395 .qid = skb_get_queue_mapping(skb), 1396 .vlan_tci = skb_vlan_tag_get(skb), 1397 .first = true, 1398 .last = !skb_is_nonlinear(skb), 1399 }; 1400 struct netdev_queue *txq; 1401 struct mtk_mac *mac = netdev_priv(dev); 1402 struct mtk_eth *eth = mac->hw; 1403 const struct mtk_soc_data *soc = eth->soc; 1404 struct mtk_tx_dma *itxd, *txd; 1405 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1406 struct mtk_tx_buf *itx_buf, *tx_buf; 1407 int i, n_desc = 1; 1408 int queue = skb_get_queue_mapping(skb); 1409 int k = 0; 1410 1411 txq = netdev_get_tx_queue(dev, queue); 1412 itxd = ring->next_free; 1413 itxd_pdma = qdma_to_pdma(ring, itxd); 1414 if (itxd == ring->last_free) 1415 return -ENOMEM; 1416 1417 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1418 memset(itx_buf, 0, sizeof(*itx_buf)); 1419 1420 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1421 DMA_TO_DEVICE); 1422 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1423 return -ENOMEM; 1424 1425 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1426 1427 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1428 itx_buf->mac_id = mac->id; 1429 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1430 k++); 1431 1432 /* TX SG offload */ 1433 txd = itxd; 1434 txd_pdma = qdma_to_pdma(ring, txd); 1435 1436 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1437 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1438 unsigned int offset = 0; 1439 int frag_size = skb_frag_size(frag); 1440 1441 while (frag_size) { 1442 bool new_desc = true; 1443 1444 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1445 (i & 0x1)) { 1446 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1447 txd_pdma = qdma_to_pdma(ring, txd); 1448 if (txd == ring->last_free) 1449 goto err_dma; 1450 1451 n_desc++; 1452 } else { 1453 new_desc = false; 1454 } 1455 1456 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1457 txd_info.size = min_t(unsigned int, frag_size, 1458 soc->txrx.dma_max_len); 1459 txd_info.qid = queue; 1460 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1461 !(frag_size - txd_info.size); 1462 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1463 offset, txd_info.size, 1464 DMA_TO_DEVICE); 1465 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1466 goto err_dma; 1467 1468 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1469 1470 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1471 soc->txrx.txd_size); 1472 if (new_desc) 1473 memset(tx_buf, 0, sizeof(*tx_buf)); 1474 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1475 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1476 tx_buf->mac_id = mac->id; 1477 1478 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1479 txd_info.size, k++); 1480 1481 frag_size -= txd_info.size; 1482 offset += txd_info.size; 1483 } 1484 } 1485 1486 /* store skb to cleanup */ 1487 itx_buf->type = MTK_TYPE_SKB; 1488 itx_buf->data = skb; 1489 1490 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1491 if (k & 0x1) 1492 txd_pdma->txd2 |= TX_DMA_LS0; 1493 else 1494 txd_pdma->txd2 |= TX_DMA_LS1; 1495 } 1496 1497 netdev_tx_sent_queue(txq, skb->len); 1498 skb_tx_timestamp(skb); 1499 1500 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1501 atomic_sub(n_desc, &ring->free_count); 1502 1503 /* make sure that all changes to the dma ring are flushed before we 1504 * continue 1505 */ 1506 wmb(); 1507 1508 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1509 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1510 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1511 } else { 1512 int next_idx; 1513 1514 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1515 ring->dma_size); 1516 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1517 } 1518 1519 return 0; 1520 1521 err_dma: 1522 do { 1523 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1524 1525 /* unmap dma */ 1526 mtk_tx_unmap(eth, tx_buf, NULL, false); 1527 1528 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1529 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1530 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1531 1532 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1533 itxd_pdma = qdma_to_pdma(ring, itxd); 1534 } while (itxd != txd); 1535 1536 return -ENOMEM; 1537 } 1538 1539 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1540 { 1541 int i, nfrags = 1; 1542 skb_frag_t *frag; 1543 1544 if (skb_is_gso(skb)) { 1545 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1546 frag = &skb_shinfo(skb)->frags[i]; 1547 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1548 eth->soc->txrx.dma_max_len); 1549 } 1550 } else { 1551 nfrags += skb_shinfo(skb)->nr_frags; 1552 } 1553 1554 return nfrags; 1555 } 1556 1557 static int mtk_queue_stopped(struct mtk_eth *eth) 1558 { 1559 int i; 1560 1561 for (i = 0; i < MTK_MAX_DEVS; i++) { 1562 if (!eth->netdev[i]) 1563 continue; 1564 if (netif_queue_stopped(eth->netdev[i])) 1565 return 1; 1566 } 1567 1568 return 0; 1569 } 1570 1571 static void mtk_wake_queue(struct mtk_eth *eth) 1572 { 1573 int i; 1574 1575 for (i = 0; i < MTK_MAX_DEVS; i++) { 1576 if (!eth->netdev[i]) 1577 continue; 1578 netif_tx_wake_all_queues(eth->netdev[i]); 1579 } 1580 } 1581 1582 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1583 { 1584 struct mtk_mac *mac = netdev_priv(dev); 1585 struct mtk_eth *eth = mac->hw; 1586 struct mtk_tx_ring *ring = ð->tx_ring; 1587 struct net_device_stats *stats = &dev->stats; 1588 bool gso = false; 1589 int tx_num; 1590 1591 /* normally we can rely on the stack not calling this more than once, 1592 * however we have 2 queues running on the same ring so we need to lock 1593 * the ring access 1594 */ 1595 spin_lock(ð->page_lock); 1596 1597 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1598 goto drop; 1599 1600 tx_num = mtk_cal_txd_req(eth, skb); 1601 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1602 netif_tx_stop_all_queues(dev); 1603 netif_err(eth, tx_queued, dev, 1604 "Tx Ring full when queue awake!\n"); 1605 spin_unlock(ð->page_lock); 1606 return NETDEV_TX_BUSY; 1607 } 1608 1609 /* TSO: fill MSS info in tcp checksum field */ 1610 if (skb_is_gso(skb)) { 1611 if (skb_cow_head(skb, 0)) { 1612 netif_warn(eth, tx_err, dev, 1613 "GSO expand head fail.\n"); 1614 goto drop; 1615 } 1616 1617 if (skb_shinfo(skb)->gso_type & 1618 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1619 gso = true; 1620 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1621 } 1622 } 1623 1624 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1625 goto drop; 1626 1627 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1628 netif_tx_stop_all_queues(dev); 1629 1630 spin_unlock(ð->page_lock); 1631 1632 return NETDEV_TX_OK; 1633 1634 drop: 1635 spin_unlock(ð->page_lock); 1636 stats->tx_dropped++; 1637 dev_kfree_skb_any(skb); 1638 return NETDEV_TX_OK; 1639 } 1640 1641 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1642 { 1643 int i; 1644 struct mtk_rx_ring *ring; 1645 int idx; 1646 1647 if (!eth->hwlro) 1648 return ð->rx_ring[0]; 1649 1650 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1651 struct mtk_rx_dma *rxd; 1652 1653 ring = ð->rx_ring[i]; 1654 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1655 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1656 if (rxd->rxd2 & RX_DMA_DONE) { 1657 ring->calc_idx_update = true; 1658 return ring; 1659 } 1660 } 1661 1662 return NULL; 1663 } 1664 1665 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1666 { 1667 struct mtk_rx_ring *ring; 1668 int i; 1669 1670 if (!eth->hwlro) { 1671 ring = ð->rx_ring[0]; 1672 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1673 } else { 1674 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1675 ring = ð->rx_ring[i]; 1676 if (ring->calc_idx_update) { 1677 ring->calc_idx_update = false; 1678 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1679 } 1680 } 1681 } 1682 } 1683 1684 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1685 { 1686 return mtk_is_netsys_v2_or_greater(eth); 1687 } 1688 1689 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1690 struct xdp_rxq_info *xdp_q, 1691 int id, int size) 1692 { 1693 struct page_pool_params pp_params = { 1694 .order = 0, 1695 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1696 .pool_size = size, 1697 .nid = NUMA_NO_NODE, 1698 .dev = eth->dma_dev, 1699 .offset = MTK_PP_HEADROOM, 1700 .max_len = MTK_PP_MAX_BUF_SIZE, 1701 }; 1702 struct page_pool *pp; 1703 int err; 1704 1705 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1706 : DMA_FROM_DEVICE; 1707 pp = page_pool_create(&pp_params); 1708 if (IS_ERR(pp)) 1709 return pp; 1710 1711 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id, 1712 eth->rx_napi.napi_id, PAGE_SIZE); 1713 if (err < 0) 1714 goto err_free_pp; 1715 1716 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1717 if (err) 1718 goto err_unregister_rxq; 1719 1720 return pp; 1721 1722 err_unregister_rxq: 1723 xdp_rxq_info_unreg(xdp_q); 1724 err_free_pp: 1725 page_pool_destroy(pp); 1726 1727 return ERR_PTR(err); 1728 } 1729 1730 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1731 gfp_t gfp_mask) 1732 { 1733 struct page *page; 1734 1735 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1736 if (!page) 1737 return NULL; 1738 1739 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1740 return page_address(page); 1741 } 1742 1743 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1744 { 1745 if (ring->page_pool) 1746 page_pool_put_full_page(ring->page_pool, 1747 virt_to_head_page(data), napi); 1748 else 1749 skb_free_frag(data); 1750 } 1751 1752 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1753 struct mtk_tx_dma_desc_info *txd_info, 1754 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1755 void *data, u16 headroom, int index, bool dma_map) 1756 { 1757 struct mtk_tx_ring *ring = ð->tx_ring; 1758 struct mtk_mac *mac = netdev_priv(dev); 1759 struct mtk_tx_dma *txd_pdma; 1760 1761 if (dma_map) { /* ndo_xdp_xmit */ 1762 txd_info->addr = dma_map_single(eth->dma_dev, data, 1763 txd_info->size, DMA_TO_DEVICE); 1764 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1765 return -ENOMEM; 1766 1767 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1768 } else { 1769 struct page *page = virt_to_head_page(data); 1770 1771 txd_info->addr = page_pool_get_dma_addr(page) + 1772 sizeof(struct xdp_frame) + headroom; 1773 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1774 txd_info->size, DMA_BIDIRECTIONAL); 1775 } 1776 mtk_tx_set_dma_desc(dev, txd, txd_info); 1777 1778 tx_buf->mac_id = mac->id; 1779 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1780 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1781 1782 txd_pdma = qdma_to_pdma(ring, txd); 1783 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1784 index); 1785 1786 return 0; 1787 } 1788 1789 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1790 struct net_device *dev, bool dma_map) 1791 { 1792 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1793 const struct mtk_soc_data *soc = eth->soc; 1794 struct mtk_tx_ring *ring = ð->tx_ring; 1795 struct mtk_mac *mac = netdev_priv(dev); 1796 struct mtk_tx_dma_desc_info txd_info = { 1797 .size = xdpf->len, 1798 .first = true, 1799 .last = !xdp_frame_has_frags(xdpf), 1800 .qid = mac->id, 1801 }; 1802 int err, index = 0, n_desc = 1, nr_frags; 1803 struct mtk_tx_buf *htx_buf, *tx_buf; 1804 struct mtk_tx_dma *htxd, *txd; 1805 void *data = xdpf->data; 1806 1807 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1808 return -EBUSY; 1809 1810 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1811 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1812 return -EBUSY; 1813 1814 spin_lock(ð->page_lock); 1815 1816 txd = ring->next_free; 1817 if (txd == ring->last_free) { 1818 spin_unlock(ð->page_lock); 1819 return -ENOMEM; 1820 } 1821 htxd = txd; 1822 1823 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1824 memset(tx_buf, 0, sizeof(*tx_buf)); 1825 htx_buf = tx_buf; 1826 1827 for (;;) { 1828 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1829 data, xdpf->headroom, index, dma_map); 1830 if (err < 0) 1831 goto unmap; 1832 1833 if (txd_info.last) 1834 break; 1835 1836 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1837 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1838 if (txd == ring->last_free) 1839 goto unmap; 1840 1841 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1842 soc->txrx.txd_size); 1843 memset(tx_buf, 0, sizeof(*tx_buf)); 1844 n_desc++; 1845 } 1846 1847 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1848 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1849 txd_info.last = index + 1 == nr_frags; 1850 txd_info.qid = mac->id; 1851 data = skb_frag_address(&sinfo->frags[index]); 1852 1853 index++; 1854 } 1855 /* store xdpf for cleanup */ 1856 htx_buf->data = xdpf; 1857 1858 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1859 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1860 1861 if (index & 1) 1862 txd_pdma->txd2 |= TX_DMA_LS0; 1863 else 1864 txd_pdma->txd2 |= TX_DMA_LS1; 1865 } 1866 1867 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1868 atomic_sub(n_desc, &ring->free_count); 1869 1870 /* make sure that all changes to the dma ring are flushed before we 1871 * continue 1872 */ 1873 wmb(); 1874 1875 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1876 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1877 } else { 1878 int idx; 1879 1880 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1881 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1882 MT7628_TX_CTX_IDX0); 1883 } 1884 1885 spin_unlock(ð->page_lock); 1886 1887 return 0; 1888 1889 unmap: 1890 while (htxd != txd) { 1891 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1892 mtk_tx_unmap(eth, tx_buf, NULL, false); 1893 1894 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1895 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1896 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1897 1898 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1899 } 1900 1901 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1902 } 1903 1904 spin_unlock(ð->page_lock); 1905 1906 return err; 1907 } 1908 1909 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1910 struct xdp_frame **frames, u32 flags) 1911 { 1912 struct mtk_mac *mac = netdev_priv(dev); 1913 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1914 struct mtk_eth *eth = mac->hw; 1915 int i, nxmit = 0; 1916 1917 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1918 return -EINVAL; 1919 1920 for (i = 0; i < num_frame; i++) { 1921 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1922 break; 1923 nxmit++; 1924 } 1925 1926 u64_stats_update_begin(&hw_stats->syncp); 1927 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1928 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1929 u64_stats_update_end(&hw_stats->syncp); 1930 1931 return nxmit; 1932 } 1933 1934 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1935 struct xdp_buff *xdp, struct net_device *dev) 1936 { 1937 struct mtk_mac *mac = netdev_priv(dev); 1938 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1939 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1940 struct bpf_prog *prog; 1941 u32 act = XDP_PASS; 1942 1943 rcu_read_lock(); 1944 1945 prog = rcu_dereference(eth->prog); 1946 if (!prog) 1947 goto out; 1948 1949 act = bpf_prog_run_xdp(prog, xdp); 1950 switch (act) { 1951 case XDP_PASS: 1952 count = &hw_stats->xdp_stats.rx_xdp_pass; 1953 goto update_stats; 1954 case XDP_REDIRECT: 1955 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1956 act = XDP_DROP; 1957 break; 1958 } 1959 1960 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1961 goto update_stats; 1962 case XDP_TX: { 1963 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1964 1965 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1966 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1967 act = XDP_DROP; 1968 break; 1969 } 1970 1971 count = &hw_stats->xdp_stats.rx_xdp_tx; 1972 goto update_stats; 1973 } 1974 default: 1975 bpf_warn_invalid_xdp_action(dev, prog, act); 1976 fallthrough; 1977 case XDP_ABORTED: 1978 trace_xdp_exception(dev, prog, act); 1979 fallthrough; 1980 case XDP_DROP: 1981 break; 1982 } 1983 1984 page_pool_put_full_page(ring->page_pool, 1985 virt_to_head_page(xdp->data), true); 1986 1987 update_stats: 1988 u64_stats_update_begin(&hw_stats->syncp); 1989 *count = *count + 1; 1990 u64_stats_update_end(&hw_stats->syncp); 1991 out: 1992 rcu_read_unlock(); 1993 1994 return act; 1995 } 1996 1997 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1998 struct mtk_eth *eth) 1999 { 2000 struct dim_sample dim_sample = {}; 2001 struct mtk_rx_ring *ring; 2002 bool xdp_flush = false; 2003 int idx; 2004 struct sk_buff *skb; 2005 u64 addr64 = 0; 2006 u8 *data, *new_data; 2007 struct mtk_rx_dma_v2 *rxd, trxd; 2008 int done = 0, bytes = 0; 2009 dma_addr_t dma_addr = DMA_MAPPING_ERROR; 2010 2011 while (done < budget) { 2012 unsigned int pktlen, *rxdcsum; 2013 struct net_device *netdev; 2014 u32 hash, reason; 2015 int mac = 0; 2016 2017 ring = mtk_get_rx_ring(eth); 2018 if (unlikely(!ring)) 2019 goto rx_done; 2020 2021 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 2022 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 2023 data = ring->data[idx]; 2024 2025 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 2026 break; 2027 2028 /* find out which mac the packet come from. values start at 1 */ 2029 if (mtk_is_netsys_v2_or_greater(eth)) { 2030 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); 2031 2032 switch (val) { 2033 case PSE_GDM1_PORT: 2034 case PSE_GDM2_PORT: 2035 mac = val - 1; 2036 break; 2037 case PSE_GDM3_PORT: 2038 mac = MTK_GMAC3_ID; 2039 break; 2040 default: 2041 break; 2042 } 2043 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 2044 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { 2045 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 2046 } 2047 2048 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || 2049 !eth->netdev[mac])) 2050 goto release_desc; 2051 2052 netdev = eth->netdev[mac]; 2053 2054 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 2055 goto release_desc; 2056 2057 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 2058 2059 /* alloc new buffer */ 2060 if (ring->page_pool) { 2061 struct page *page = virt_to_head_page(data); 2062 struct xdp_buff xdp; 2063 u32 ret; 2064 2065 new_data = mtk_page_pool_get_buff(ring->page_pool, 2066 &dma_addr, 2067 GFP_ATOMIC); 2068 if (unlikely(!new_data)) { 2069 netdev->stats.rx_dropped++; 2070 goto release_desc; 2071 } 2072 2073 dma_sync_single_for_cpu(eth->dma_dev, 2074 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 2075 pktlen, page_pool_get_dma_dir(ring->page_pool)); 2076 2077 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 2078 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 2079 false); 2080 xdp_buff_clear_frags_flag(&xdp); 2081 2082 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 2083 if (ret == XDP_REDIRECT) 2084 xdp_flush = true; 2085 2086 if (ret != XDP_PASS) 2087 goto skip_rx; 2088 2089 skb = build_skb(data, PAGE_SIZE); 2090 if (unlikely(!skb)) { 2091 page_pool_put_full_page(ring->page_pool, 2092 page, true); 2093 netdev->stats.rx_dropped++; 2094 goto skip_rx; 2095 } 2096 2097 skb_reserve(skb, xdp.data - xdp.data_hard_start); 2098 skb_put(skb, xdp.data_end - xdp.data); 2099 skb_mark_for_recycle(skb); 2100 } else { 2101 if (ring->frag_size <= PAGE_SIZE) 2102 new_data = napi_alloc_frag(ring->frag_size); 2103 else 2104 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2105 2106 if (unlikely(!new_data)) { 2107 netdev->stats.rx_dropped++; 2108 goto release_desc; 2109 } 2110 2111 dma_addr = dma_map_single(eth->dma_dev, 2112 new_data + NET_SKB_PAD + eth->ip_align, 2113 ring->buf_size, DMA_FROM_DEVICE); 2114 if (unlikely(dma_mapping_error(eth->dma_dev, 2115 dma_addr))) { 2116 skb_free_frag(new_data); 2117 netdev->stats.rx_dropped++; 2118 goto release_desc; 2119 } 2120 2121 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2122 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2); 2123 2124 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), 2125 ring->buf_size, DMA_FROM_DEVICE); 2126 2127 skb = build_skb(data, ring->frag_size); 2128 if (unlikely(!skb)) { 2129 netdev->stats.rx_dropped++; 2130 skb_free_frag(data); 2131 goto skip_rx; 2132 } 2133 2134 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2135 skb_put(skb, pktlen); 2136 } 2137 2138 skb->dev = netdev; 2139 bytes += skb->len; 2140 2141 if (mtk_is_netsys_v2_or_greater(eth)) { 2142 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2143 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2144 if (hash != MTK_RXD5_FOE_ENTRY) 2145 skb_set_hash(skb, jhash_1word(hash, 0), 2146 PKT_HASH_TYPE_L4); 2147 rxdcsum = &trxd.rxd3; 2148 } else { 2149 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2150 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2151 if (hash != MTK_RXD4_FOE_ENTRY) 2152 skb_set_hash(skb, jhash_1word(hash, 0), 2153 PKT_HASH_TYPE_L4); 2154 rxdcsum = &trxd.rxd4; 2155 } 2156 2157 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 2158 skb->ip_summed = CHECKSUM_UNNECESSARY; 2159 else 2160 skb_checksum_none_assert(skb); 2161 skb->protocol = eth_type_trans(skb, netdev); 2162 2163 /* When using VLAN untagging in combination with DSA, the 2164 * hardware treats the MTK special tag as a VLAN and untags it. 2165 */ 2166 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && 2167 netdev_uses_dsa(netdev)) { 2168 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 2169 2170 if (port < ARRAY_SIZE(eth->dsa_meta) && 2171 eth->dsa_meta[port]) 2172 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2173 } 2174 2175 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2176 mtk_ppe_check_skb(eth->ppe[0], skb, hash); 2177 2178 skb_record_rx_queue(skb, 0); 2179 napi_gro_receive(napi, skb); 2180 2181 skip_rx: 2182 ring->data[idx] = new_data; 2183 rxd->rxd1 = (unsigned int)dma_addr; 2184 release_desc: 2185 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2186 rxd->rxd2 = RX_DMA_LSO; 2187 else 2188 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2189 2190 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA) && 2191 likely(dma_addr != DMA_MAPPING_ERROR)) 2192 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2193 2194 ring->calc_idx = idx; 2195 done++; 2196 } 2197 2198 rx_done: 2199 if (done) { 2200 /* make sure that all changes to the dma ring are flushed before 2201 * we continue 2202 */ 2203 wmb(); 2204 mtk_update_rx_cpu_idx(eth); 2205 } 2206 2207 eth->rx_packets += done; 2208 eth->rx_bytes += bytes; 2209 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2210 &dim_sample); 2211 net_dim(ð->rx_dim, dim_sample); 2212 2213 if (xdp_flush) 2214 xdp_do_flush(); 2215 2216 return done; 2217 } 2218 2219 struct mtk_poll_state { 2220 struct netdev_queue *txq; 2221 unsigned int total; 2222 unsigned int done; 2223 unsigned int bytes; 2224 }; 2225 2226 static void 2227 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2228 struct sk_buff *skb) 2229 { 2230 struct netdev_queue *txq; 2231 struct net_device *dev; 2232 unsigned int bytes = skb->len; 2233 2234 state->total++; 2235 eth->tx_packets++; 2236 eth->tx_bytes += bytes; 2237 2238 dev = eth->netdev[mac]; 2239 if (!dev) 2240 return; 2241 2242 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2243 if (state->txq == txq) { 2244 state->done++; 2245 state->bytes += bytes; 2246 return; 2247 } 2248 2249 if (state->txq) 2250 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2251 2252 state->txq = txq; 2253 state->done = 1; 2254 state->bytes = bytes; 2255 } 2256 2257 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2258 struct mtk_poll_state *state) 2259 { 2260 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2261 struct mtk_tx_ring *ring = ð->tx_ring; 2262 struct mtk_tx_buf *tx_buf; 2263 struct xdp_frame_bulk bq; 2264 struct mtk_tx_dma *desc; 2265 u32 cpu, dma; 2266 2267 cpu = ring->last_free_ptr; 2268 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2269 2270 desc = mtk_qdma_phys_to_virt(ring, cpu); 2271 xdp_frame_bulk_init(&bq); 2272 2273 while ((cpu != dma) && budget) { 2274 u32 next_cpu = desc->txd2; 2275 2276 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2277 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2278 break; 2279 2280 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2281 eth->soc->txrx.txd_size); 2282 if (!tx_buf->data) 2283 break; 2284 2285 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2286 if (tx_buf->type == MTK_TYPE_SKB) 2287 mtk_poll_tx_done(eth, state, tx_buf->mac_id, 2288 tx_buf->data); 2289 2290 budget--; 2291 } 2292 mtk_tx_unmap(eth, tx_buf, &bq, true); 2293 2294 ring->last_free = desc; 2295 atomic_inc(&ring->free_count); 2296 2297 cpu = next_cpu; 2298 } 2299 xdp_flush_frame_bulk(&bq); 2300 2301 ring->last_free_ptr = cpu; 2302 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2303 2304 return budget; 2305 } 2306 2307 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2308 struct mtk_poll_state *state) 2309 { 2310 struct mtk_tx_ring *ring = ð->tx_ring; 2311 struct mtk_tx_buf *tx_buf; 2312 struct xdp_frame_bulk bq; 2313 struct mtk_tx_dma *desc; 2314 u32 cpu, dma; 2315 2316 cpu = ring->cpu_idx; 2317 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2318 xdp_frame_bulk_init(&bq); 2319 2320 while ((cpu != dma) && budget) { 2321 tx_buf = &ring->buf[cpu]; 2322 if (!tx_buf->data) 2323 break; 2324 2325 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2326 if (tx_buf->type == MTK_TYPE_SKB) 2327 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2328 budget--; 2329 } 2330 mtk_tx_unmap(eth, tx_buf, &bq, true); 2331 2332 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2333 ring->last_free = desc; 2334 atomic_inc(&ring->free_count); 2335 2336 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2337 } 2338 xdp_flush_frame_bulk(&bq); 2339 2340 ring->cpu_idx = cpu; 2341 2342 return budget; 2343 } 2344 2345 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2346 { 2347 struct mtk_tx_ring *ring = ð->tx_ring; 2348 struct dim_sample dim_sample = {}; 2349 struct mtk_poll_state state = {}; 2350 2351 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2352 budget = mtk_poll_tx_qdma(eth, budget, &state); 2353 else 2354 budget = mtk_poll_tx_pdma(eth, budget, &state); 2355 2356 if (state.txq) 2357 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2358 2359 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2360 &dim_sample); 2361 net_dim(ð->tx_dim, dim_sample); 2362 2363 if (mtk_queue_stopped(eth) && 2364 (atomic_read(&ring->free_count) > ring->thresh)) 2365 mtk_wake_queue(eth); 2366 2367 return state.total; 2368 } 2369 2370 static void mtk_handle_status_irq(struct mtk_eth *eth) 2371 { 2372 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2373 2374 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2375 mtk_stats_update(eth); 2376 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2377 MTK_INT_STATUS2); 2378 } 2379 } 2380 2381 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2382 { 2383 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2384 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2385 int tx_done = 0; 2386 2387 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2388 mtk_handle_status_irq(eth); 2389 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2390 tx_done = mtk_poll_tx(eth, budget); 2391 2392 if (unlikely(netif_msg_intr(eth))) { 2393 dev_info(eth->dev, 2394 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2395 mtk_r32(eth, reg_map->tx_irq_status), 2396 mtk_r32(eth, reg_map->tx_irq_mask)); 2397 } 2398 2399 if (tx_done == budget) 2400 return budget; 2401 2402 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2403 return budget; 2404 2405 if (napi_complete_done(napi, tx_done)) 2406 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2407 2408 return tx_done; 2409 } 2410 2411 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2412 { 2413 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2414 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2415 int rx_done_total = 0; 2416 2417 mtk_handle_status_irq(eth); 2418 2419 do { 2420 int rx_done; 2421 2422 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2423 reg_map->pdma.irq_status); 2424 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2425 rx_done_total += rx_done; 2426 2427 if (unlikely(netif_msg_intr(eth))) { 2428 dev_info(eth->dev, 2429 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2430 mtk_r32(eth, reg_map->pdma.irq_status), 2431 mtk_r32(eth, reg_map->pdma.irq_mask)); 2432 } 2433 2434 if (rx_done_total == budget) 2435 return budget; 2436 2437 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2438 eth->soc->txrx.rx_irq_done_mask); 2439 2440 if (napi_complete_done(napi, rx_done_total)) 2441 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2442 2443 return rx_done_total; 2444 } 2445 2446 static int mtk_tx_alloc(struct mtk_eth *eth) 2447 { 2448 const struct mtk_soc_data *soc = eth->soc; 2449 struct mtk_tx_ring *ring = ð->tx_ring; 2450 int i, sz = soc->txrx.txd_size; 2451 struct mtk_tx_dma_v2 *txd; 2452 int ring_size; 2453 u32 ofs, val; 2454 2455 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2456 ring_size = MTK_QDMA_RING_SIZE; 2457 else 2458 ring_size = MTK_DMA_SIZE; 2459 2460 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2461 GFP_KERNEL); 2462 if (!ring->buf) 2463 goto no_tx_mem; 2464 2465 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { 2466 ring->dma = eth->sram_base + ring_size * sz; 2467 ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz; 2468 } else { 2469 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2470 &ring->phys, GFP_KERNEL); 2471 } 2472 2473 if (!ring->dma) 2474 goto no_tx_mem; 2475 2476 for (i = 0; i < ring_size; i++) { 2477 int next = (i + 1) % ring_size; 2478 u32 next_ptr = ring->phys + next * sz; 2479 2480 txd = ring->dma + i * sz; 2481 txd->txd2 = next_ptr; 2482 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2483 txd->txd4 = 0; 2484 if (mtk_is_netsys_v2_or_greater(eth)) { 2485 txd->txd5 = 0; 2486 txd->txd6 = 0; 2487 txd->txd7 = 0; 2488 txd->txd8 = 0; 2489 } 2490 } 2491 2492 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2493 * only as the framework. The real HW descriptors are the PDMA 2494 * descriptors in ring->dma_pdma. 2495 */ 2496 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2497 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2498 &ring->phys_pdma, GFP_KERNEL); 2499 if (!ring->dma_pdma) 2500 goto no_tx_mem; 2501 2502 for (i = 0; i < ring_size; i++) { 2503 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2504 ring->dma_pdma[i].txd4 = 0; 2505 } 2506 } 2507 2508 ring->dma_size = ring_size; 2509 atomic_set(&ring->free_count, ring_size - 2); 2510 ring->next_free = ring->dma; 2511 ring->last_free = (void *)txd; 2512 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2513 ring->thresh = MAX_SKB_FRAGS; 2514 2515 /* make sure that all changes to the dma ring are flushed before we 2516 * continue 2517 */ 2518 wmb(); 2519 2520 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2521 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2522 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2523 mtk_w32(eth, 2524 ring->phys + ((ring_size - 1) * sz), 2525 soc->reg_map->qdma.crx_ptr); 2526 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2527 2528 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2529 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2530 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2531 2532 val = MTK_QTX_SCH_MIN_RATE_EN | 2533 /* minimum: 10 Mbps */ 2534 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2535 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2536 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2537 if (mtk_is_netsys_v1(eth)) 2538 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2539 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2540 ofs += MTK_QTX_OFFSET; 2541 } 2542 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2543 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2544 if (mtk_is_netsys_v2_or_greater(eth)) 2545 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2546 } else { 2547 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2548 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2549 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2550 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2551 } 2552 2553 return 0; 2554 2555 no_tx_mem: 2556 return -ENOMEM; 2557 } 2558 2559 static void mtk_tx_clean(struct mtk_eth *eth) 2560 { 2561 const struct mtk_soc_data *soc = eth->soc; 2562 struct mtk_tx_ring *ring = ð->tx_ring; 2563 int i; 2564 2565 if (ring->buf) { 2566 for (i = 0; i < ring->dma_size; i++) 2567 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2568 kfree(ring->buf); 2569 ring->buf = NULL; 2570 } 2571 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { 2572 dma_free_coherent(eth->dma_dev, 2573 ring->dma_size * soc->txrx.txd_size, 2574 ring->dma, ring->phys); 2575 ring->dma = NULL; 2576 } 2577 2578 if (ring->dma_pdma) { 2579 dma_free_coherent(eth->dma_dev, 2580 ring->dma_size * soc->txrx.txd_size, 2581 ring->dma_pdma, ring->phys_pdma); 2582 ring->dma_pdma = NULL; 2583 } 2584 } 2585 2586 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2587 { 2588 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2589 struct mtk_rx_ring *ring; 2590 int rx_data_len, rx_dma_size, tx_ring_size; 2591 int i; 2592 2593 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2594 tx_ring_size = MTK_QDMA_RING_SIZE; 2595 else 2596 tx_ring_size = MTK_DMA_SIZE; 2597 2598 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2599 if (ring_no) 2600 return -EINVAL; 2601 ring = ð->rx_ring_qdma; 2602 } else { 2603 ring = ð->rx_ring[ring_no]; 2604 } 2605 2606 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2607 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2608 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2609 } else { 2610 rx_data_len = ETH_DATA_LEN; 2611 rx_dma_size = MTK_DMA_SIZE; 2612 } 2613 2614 ring->frag_size = mtk_max_frag_size(rx_data_len); 2615 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2616 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2617 GFP_KERNEL); 2618 if (!ring->data) 2619 return -ENOMEM; 2620 2621 if (mtk_page_pool_enabled(eth)) { 2622 struct page_pool *pp; 2623 2624 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2625 rx_dma_size); 2626 if (IS_ERR(pp)) 2627 return PTR_ERR(pp); 2628 2629 ring->page_pool = pp; 2630 } 2631 2632 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || 2633 rx_flag != MTK_RX_FLAGS_NORMAL) { 2634 ring->dma = dma_alloc_coherent(eth->dma_dev, 2635 rx_dma_size * eth->soc->txrx.rxd_size, 2636 &ring->phys, GFP_KERNEL); 2637 } else { 2638 struct mtk_tx_ring *tx_ring = ð->tx_ring; 2639 2640 ring->dma = tx_ring->dma + tx_ring_size * 2641 eth->soc->txrx.txd_size * (ring_no + 1); 2642 ring->phys = tx_ring->phys + tx_ring_size * 2643 eth->soc->txrx.txd_size * (ring_no + 1); 2644 } 2645 2646 if (!ring->dma) 2647 return -ENOMEM; 2648 2649 for (i = 0; i < rx_dma_size; i++) { 2650 struct mtk_rx_dma_v2 *rxd; 2651 dma_addr_t dma_addr; 2652 void *data; 2653 2654 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2655 if (ring->page_pool) { 2656 data = mtk_page_pool_get_buff(ring->page_pool, 2657 &dma_addr, GFP_KERNEL); 2658 if (!data) 2659 return -ENOMEM; 2660 } else { 2661 if (ring->frag_size <= PAGE_SIZE) 2662 data = netdev_alloc_frag(ring->frag_size); 2663 else 2664 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2665 2666 if (!data) 2667 return -ENOMEM; 2668 2669 dma_addr = dma_map_single(eth->dma_dev, 2670 data + NET_SKB_PAD + eth->ip_align, 2671 ring->buf_size, DMA_FROM_DEVICE); 2672 if (unlikely(dma_mapping_error(eth->dma_dev, 2673 dma_addr))) { 2674 skb_free_frag(data); 2675 return -ENOMEM; 2676 } 2677 } 2678 rxd->rxd1 = (unsigned int)dma_addr; 2679 ring->data[i] = data; 2680 2681 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2682 rxd->rxd2 = RX_DMA_LSO; 2683 else 2684 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2685 2686 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2687 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2688 2689 rxd->rxd3 = 0; 2690 rxd->rxd4 = 0; 2691 if (mtk_is_netsys_v2_or_greater(eth)) { 2692 rxd->rxd5 = 0; 2693 rxd->rxd6 = 0; 2694 rxd->rxd7 = 0; 2695 rxd->rxd8 = 0; 2696 } 2697 } 2698 2699 ring->dma_size = rx_dma_size; 2700 ring->calc_idx_update = false; 2701 ring->calc_idx = rx_dma_size - 1; 2702 if (rx_flag == MTK_RX_FLAGS_QDMA) 2703 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2704 ring_no * MTK_QRX_OFFSET; 2705 else 2706 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2707 ring_no * MTK_QRX_OFFSET; 2708 /* make sure that all changes to the dma ring are flushed before we 2709 * continue 2710 */ 2711 wmb(); 2712 2713 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2714 mtk_w32(eth, ring->phys, 2715 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2716 mtk_w32(eth, rx_dma_size, 2717 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2718 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2719 reg_map->qdma.rst_idx); 2720 } else { 2721 mtk_w32(eth, ring->phys, 2722 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2723 mtk_w32(eth, rx_dma_size, 2724 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2725 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2726 reg_map->pdma.rst_idx); 2727 } 2728 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2729 2730 return 0; 2731 } 2732 2733 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) 2734 { 2735 u64 addr64 = 0; 2736 int i; 2737 2738 if (ring->data && ring->dma) { 2739 for (i = 0; i < ring->dma_size; i++) { 2740 struct mtk_rx_dma *rxd; 2741 2742 if (!ring->data[i]) 2743 continue; 2744 2745 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2746 if (!rxd->rxd1) 2747 continue; 2748 2749 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2750 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); 2751 2752 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), 2753 ring->buf_size, DMA_FROM_DEVICE); 2754 mtk_rx_put_buff(ring, ring->data[i], false); 2755 } 2756 kfree(ring->data); 2757 ring->data = NULL; 2758 } 2759 2760 if (!in_sram && ring->dma) { 2761 dma_free_coherent(eth->dma_dev, 2762 ring->dma_size * eth->soc->txrx.rxd_size, 2763 ring->dma, ring->phys); 2764 ring->dma = NULL; 2765 } 2766 2767 if (ring->page_pool) { 2768 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2769 xdp_rxq_info_unreg(&ring->xdp_q); 2770 page_pool_destroy(ring->page_pool); 2771 ring->page_pool = NULL; 2772 } 2773 } 2774 2775 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2776 { 2777 int i; 2778 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2779 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2780 2781 /* set LRO rings to auto-learn modes */ 2782 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2783 2784 /* validate LRO ring */ 2785 ring_ctrl_dw2 |= MTK_RING_VLD; 2786 2787 /* set AGE timer (unit: 20us) */ 2788 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2789 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2790 2791 /* set max AGG timer (unit: 20us) */ 2792 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2793 2794 /* set max LRO AGG count */ 2795 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2796 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2797 2798 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2799 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2800 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2801 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2802 } 2803 2804 /* IPv4 checksum update enable */ 2805 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2806 2807 /* switch priority comparison to packet count mode */ 2808 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2809 2810 /* bandwidth threshold setting */ 2811 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2812 2813 /* auto-learn score delta setting */ 2814 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2815 2816 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2817 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2818 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2819 2820 /* set HW LRO mode & the max aggregation count for rx packets */ 2821 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2822 2823 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2824 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2825 2826 /* enable HW LRO */ 2827 lro_ctrl_dw0 |= MTK_LRO_EN; 2828 2829 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2830 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2831 2832 return 0; 2833 } 2834 2835 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2836 { 2837 int i; 2838 u32 val; 2839 2840 /* relinquish lro rings, flush aggregated packets */ 2841 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2842 2843 /* wait for relinquishments done */ 2844 for (i = 0; i < 10; i++) { 2845 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2846 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2847 msleep(20); 2848 continue; 2849 } 2850 break; 2851 } 2852 2853 /* invalidate lro rings */ 2854 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2855 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2856 2857 /* disable HW LRO */ 2858 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2859 } 2860 2861 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2862 { 2863 u32 reg_val; 2864 2865 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2866 2867 /* invalidate the IP setting */ 2868 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2869 2870 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2871 2872 /* validate the IP setting */ 2873 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2874 } 2875 2876 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2877 { 2878 u32 reg_val; 2879 2880 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2881 2882 /* invalidate the IP setting */ 2883 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2884 2885 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2886 } 2887 2888 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2889 { 2890 int cnt = 0; 2891 int i; 2892 2893 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2894 if (mac->hwlro_ip[i]) 2895 cnt++; 2896 } 2897 2898 return cnt; 2899 } 2900 2901 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2902 struct ethtool_rxnfc *cmd) 2903 { 2904 struct ethtool_rx_flow_spec *fsp = 2905 (struct ethtool_rx_flow_spec *)&cmd->fs; 2906 struct mtk_mac *mac = netdev_priv(dev); 2907 struct mtk_eth *eth = mac->hw; 2908 int hwlro_idx; 2909 2910 if ((fsp->flow_type != TCP_V4_FLOW) || 2911 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2912 (fsp->location > 1)) 2913 return -EINVAL; 2914 2915 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2916 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2917 2918 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2919 2920 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2921 2922 return 0; 2923 } 2924 2925 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2926 struct ethtool_rxnfc *cmd) 2927 { 2928 struct ethtool_rx_flow_spec *fsp = 2929 (struct ethtool_rx_flow_spec *)&cmd->fs; 2930 struct mtk_mac *mac = netdev_priv(dev); 2931 struct mtk_eth *eth = mac->hw; 2932 int hwlro_idx; 2933 2934 if (fsp->location > 1) 2935 return -EINVAL; 2936 2937 mac->hwlro_ip[fsp->location] = 0; 2938 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2939 2940 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2941 2942 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2943 2944 return 0; 2945 } 2946 2947 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2948 { 2949 struct mtk_mac *mac = netdev_priv(dev); 2950 struct mtk_eth *eth = mac->hw; 2951 int i, hwlro_idx; 2952 2953 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2954 mac->hwlro_ip[i] = 0; 2955 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2956 2957 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2958 } 2959 2960 mac->hwlro_ip_cnt = 0; 2961 } 2962 2963 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2964 struct ethtool_rxnfc *cmd) 2965 { 2966 struct mtk_mac *mac = netdev_priv(dev); 2967 struct ethtool_rx_flow_spec *fsp = 2968 (struct ethtool_rx_flow_spec *)&cmd->fs; 2969 2970 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2971 return -EINVAL; 2972 2973 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2974 fsp->flow_type = TCP_V4_FLOW; 2975 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2976 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2977 2978 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2979 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2980 fsp->h_u.tcp_ip4_spec.psrc = 0; 2981 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2982 fsp->h_u.tcp_ip4_spec.pdst = 0; 2983 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2984 fsp->h_u.tcp_ip4_spec.tos = 0; 2985 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2986 2987 return 0; 2988 } 2989 2990 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2991 struct ethtool_rxnfc *cmd, 2992 u32 *rule_locs) 2993 { 2994 struct mtk_mac *mac = netdev_priv(dev); 2995 int cnt = 0; 2996 int i; 2997 2998 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2999 if (cnt == cmd->rule_cnt) 3000 return -EMSGSIZE; 3001 3002 if (mac->hwlro_ip[i]) { 3003 rule_locs[cnt] = i; 3004 cnt++; 3005 } 3006 } 3007 3008 cmd->rule_cnt = cnt; 3009 3010 return 0; 3011 } 3012 3013 static netdev_features_t mtk_fix_features(struct net_device *dev, 3014 netdev_features_t features) 3015 { 3016 if (!(features & NETIF_F_LRO)) { 3017 struct mtk_mac *mac = netdev_priv(dev); 3018 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3019 3020 if (ip_cnt) { 3021 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 3022 3023 features |= NETIF_F_LRO; 3024 } 3025 } 3026 3027 return features; 3028 } 3029 3030 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 3031 { 3032 netdev_features_t diff = dev->features ^ features; 3033 3034 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 3035 mtk_hwlro_netdev_disable(dev); 3036 3037 return 0; 3038 } 3039 3040 /* wait for DMA to finish whatever it is doing before we start using it again */ 3041 static int mtk_dma_busy_wait(struct mtk_eth *eth) 3042 { 3043 unsigned int reg; 3044 int ret; 3045 u32 val; 3046 3047 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3048 reg = eth->soc->reg_map->qdma.glo_cfg; 3049 else 3050 reg = eth->soc->reg_map->pdma.glo_cfg; 3051 3052 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 3053 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 3054 5, MTK_DMA_BUSY_TIMEOUT_US); 3055 if (ret) 3056 dev_err(eth->dev, "DMA init timeout\n"); 3057 3058 return ret; 3059 } 3060 3061 static int mtk_dma_init(struct mtk_eth *eth) 3062 { 3063 int err; 3064 u32 i; 3065 3066 if (mtk_dma_busy_wait(eth)) 3067 return -EBUSY; 3068 3069 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3070 /* QDMA needs scratch memory for internal reordering of the 3071 * descriptors 3072 */ 3073 err = mtk_init_fq_dma(eth); 3074 if (err) 3075 return err; 3076 } 3077 3078 err = mtk_tx_alloc(eth); 3079 if (err) 3080 return err; 3081 3082 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3083 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 3084 if (err) 3085 return err; 3086 } 3087 3088 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 3089 if (err) 3090 return err; 3091 3092 if (eth->hwlro) { 3093 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 3094 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 3095 if (err) 3096 return err; 3097 } 3098 err = mtk_hwlro_rx_init(eth); 3099 if (err) 3100 return err; 3101 } 3102 3103 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3104 /* Enable random early drop and set drop threshold 3105 * automatically 3106 */ 3107 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 3108 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 3109 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 3110 } 3111 3112 return 0; 3113 } 3114 3115 static void mtk_dma_free(struct mtk_eth *eth) 3116 { 3117 const struct mtk_soc_data *soc = eth->soc; 3118 int i; 3119 3120 for (i = 0; i < MTK_MAX_DEVS; i++) 3121 if (eth->netdev[i]) 3122 netdev_reset_queue(eth->netdev[i]); 3123 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { 3124 dma_free_coherent(eth->dma_dev, 3125 MTK_QDMA_RING_SIZE * soc->txrx.txd_size, 3126 eth->scratch_ring, eth->phy_scratch_ring); 3127 eth->scratch_ring = NULL; 3128 eth->phy_scratch_ring = 0; 3129 } 3130 mtk_tx_clean(eth); 3131 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); 3132 mtk_rx_clean(eth, ð->rx_ring_qdma, false); 3133 3134 if (eth->hwlro) { 3135 mtk_hwlro_rx_uninit(eth); 3136 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3137 mtk_rx_clean(eth, ð->rx_ring[i], false); 3138 } 3139 3140 kfree(eth->scratch_head); 3141 } 3142 3143 static bool mtk_hw_reset_check(struct mtk_eth *eth) 3144 { 3145 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3146 3147 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3148 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3149 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3150 } 3151 3152 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3153 { 3154 struct mtk_mac *mac = netdev_priv(dev); 3155 struct mtk_eth *eth = mac->hw; 3156 3157 if (test_bit(MTK_RESETTING, ð->state)) 3158 return; 3159 3160 if (!mtk_hw_reset_check(eth)) 3161 return; 3162 3163 eth->netdev[mac->id]->stats.tx_errors++; 3164 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3165 3166 schedule_work(ð->pending_work); 3167 } 3168 3169 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3170 { 3171 struct mtk_eth *eth = _eth; 3172 3173 eth->rx_events++; 3174 if (likely(napi_schedule_prep(ð->rx_napi))) { 3175 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3176 __napi_schedule(ð->rx_napi); 3177 } 3178 3179 return IRQ_HANDLED; 3180 } 3181 3182 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3183 { 3184 struct mtk_eth *eth = _eth; 3185 3186 eth->tx_events++; 3187 if (likely(napi_schedule_prep(ð->tx_napi))) { 3188 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3189 __napi_schedule(ð->tx_napi); 3190 } 3191 3192 return IRQ_HANDLED; 3193 } 3194 3195 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3196 { 3197 struct mtk_eth *eth = _eth; 3198 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3199 3200 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3201 eth->soc->txrx.rx_irq_done_mask) { 3202 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3203 eth->soc->txrx.rx_irq_done_mask) 3204 mtk_handle_irq_rx(irq, _eth); 3205 } 3206 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3207 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3208 mtk_handle_irq_tx(irq, _eth); 3209 } 3210 3211 return IRQ_HANDLED; 3212 } 3213 3214 #ifdef CONFIG_NET_POLL_CONTROLLER 3215 static void mtk_poll_controller(struct net_device *dev) 3216 { 3217 struct mtk_mac *mac = netdev_priv(dev); 3218 struct mtk_eth *eth = mac->hw; 3219 3220 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3221 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3222 mtk_handle_irq_rx(eth->irq[2], dev); 3223 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3224 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 3225 } 3226 #endif 3227 3228 static int mtk_start_dma(struct mtk_eth *eth) 3229 { 3230 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3231 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3232 int err; 3233 3234 err = mtk_dma_init(eth); 3235 if (err) { 3236 mtk_dma_free(eth); 3237 return err; 3238 } 3239 3240 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3241 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3242 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3243 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3244 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3245 3246 if (mtk_is_netsys_v2_or_greater(eth)) 3247 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3248 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3249 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3250 else 3251 val |= MTK_RX_BT_32DWORDS; 3252 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3253 3254 mtk_w32(eth, 3255 MTK_RX_DMA_EN | rx_2b_offset | 3256 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3257 reg_map->pdma.glo_cfg); 3258 } else { 3259 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3260 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3261 reg_map->pdma.glo_cfg); 3262 } 3263 3264 return 0; 3265 } 3266 3267 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 3268 { 3269 int i; 3270 3271 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3272 return; 3273 3274 for (i = 0; i < MTK_MAX_DEVS; i++) { 3275 u32 val; 3276 3277 if (!eth->netdev[i]) 3278 continue; 3279 3280 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3281 3282 /* default setup the forward port to send frame to PDMA */ 3283 val &= ~0xffff; 3284 3285 /* Enable RX checksum */ 3286 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3287 3288 val |= config; 3289 3290 if (netdev_uses_dsa(eth->netdev[i])) 3291 val |= MTK_GDMA_SPECIAL_TAG; 3292 3293 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 3294 } 3295 /* Reset and enable PSE */ 3296 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3297 mtk_w32(eth, 0, MTK_RST_GL); 3298 } 3299 3300 3301 static bool mtk_uses_dsa(struct net_device *dev) 3302 { 3303 #if IS_ENABLED(CONFIG_NET_DSA) 3304 return netdev_uses_dsa(dev) && 3305 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3306 #else 3307 return false; 3308 #endif 3309 } 3310 3311 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3312 { 3313 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3314 struct mtk_eth *eth = mac->hw; 3315 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3316 struct ethtool_link_ksettings s; 3317 struct net_device *ldev; 3318 struct list_head *iter; 3319 struct dsa_port *dp; 3320 3321 if (event != NETDEV_CHANGE) 3322 return NOTIFY_DONE; 3323 3324 netdev_for_each_lower_dev(dev, ldev, iter) { 3325 if (netdev_priv(ldev) == mac) 3326 goto found; 3327 } 3328 3329 return NOTIFY_DONE; 3330 3331 found: 3332 if (!dsa_user_dev_check(dev)) 3333 return NOTIFY_DONE; 3334 3335 if (__ethtool_get_link_ksettings(dev, &s)) 3336 return NOTIFY_DONE; 3337 3338 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3339 return NOTIFY_DONE; 3340 3341 dp = dsa_port_from_netdev(dev); 3342 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3343 return NOTIFY_DONE; 3344 3345 if (mac->speed > 0 && mac->speed <= s.base.speed) 3346 s.base.speed = 0; 3347 3348 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3349 3350 return NOTIFY_DONE; 3351 } 3352 3353 static int mtk_open(struct net_device *dev) 3354 { 3355 struct mtk_mac *mac = netdev_priv(dev); 3356 struct mtk_eth *eth = mac->hw; 3357 int i, err; 3358 3359 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3360 if (err) { 3361 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3362 err); 3363 return err; 3364 } 3365 3366 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3367 if (!refcount_read(ð->dma_refcnt)) { 3368 const struct mtk_soc_data *soc = eth->soc; 3369 u32 gdm_config; 3370 int i; 3371 3372 err = mtk_start_dma(eth); 3373 if (err) { 3374 phylink_disconnect_phy(mac->phylink); 3375 return err; 3376 } 3377 3378 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3379 mtk_ppe_start(eth->ppe[i]); 3380 3381 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe 3382 : MTK_GDMA_TO_PDMA; 3383 mtk_gdm_config(eth, gdm_config); 3384 3385 napi_enable(ð->tx_napi); 3386 napi_enable(ð->rx_napi); 3387 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3388 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); 3389 refcount_set(ð->dma_refcnt, 1); 3390 } 3391 else 3392 refcount_inc(ð->dma_refcnt); 3393 3394 phylink_start(mac->phylink); 3395 netif_tx_start_all_queues(dev); 3396 3397 if (mtk_is_netsys_v2_or_greater(eth)) 3398 return 0; 3399 3400 if (mtk_uses_dsa(dev) && !eth->prog) { 3401 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3402 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3403 3404 if (md_dst) 3405 continue; 3406 3407 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3408 GFP_KERNEL); 3409 if (!md_dst) 3410 return -ENOMEM; 3411 3412 md_dst->u.port_info.port_id = i; 3413 eth->dsa_meta[i] = md_dst; 3414 } 3415 } else { 3416 /* Hardware DSA untagging and VLAN RX offloading need to be 3417 * disabled if at least one MAC does not use DSA. 3418 */ 3419 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3420 3421 val &= ~MTK_CDMP_STAG_EN; 3422 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3423 3424 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); 3425 } 3426 3427 return 0; 3428 } 3429 3430 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3431 { 3432 u32 val; 3433 int i; 3434 3435 /* stop the dma engine */ 3436 spin_lock_bh(ð->page_lock); 3437 val = mtk_r32(eth, glo_cfg); 3438 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3439 glo_cfg); 3440 spin_unlock_bh(ð->page_lock); 3441 3442 /* wait for dma stop */ 3443 for (i = 0; i < 10; i++) { 3444 val = mtk_r32(eth, glo_cfg); 3445 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3446 msleep(20); 3447 continue; 3448 } 3449 break; 3450 } 3451 } 3452 3453 static int mtk_stop(struct net_device *dev) 3454 { 3455 struct mtk_mac *mac = netdev_priv(dev); 3456 struct mtk_eth *eth = mac->hw; 3457 int i; 3458 3459 phylink_stop(mac->phylink); 3460 3461 netif_tx_disable(dev); 3462 3463 phylink_disconnect_phy(mac->phylink); 3464 3465 /* only shutdown DMA if this is the last user */ 3466 if (!refcount_dec_and_test(ð->dma_refcnt)) 3467 return 0; 3468 3469 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3470 3471 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3472 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3473 napi_disable(ð->tx_napi); 3474 napi_disable(ð->rx_napi); 3475 3476 cancel_work_sync(ð->rx_dim.work); 3477 cancel_work_sync(ð->tx_dim.work); 3478 3479 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3480 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3481 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3482 3483 mtk_dma_free(eth); 3484 3485 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3486 mtk_ppe_stop(eth->ppe[i]); 3487 3488 return 0; 3489 } 3490 3491 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3492 struct netlink_ext_ack *extack) 3493 { 3494 struct mtk_mac *mac = netdev_priv(dev); 3495 struct mtk_eth *eth = mac->hw; 3496 struct bpf_prog *old_prog; 3497 bool need_update; 3498 3499 if (eth->hwlro) { 3500 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3501 return -EOPNOTSUPP; 3502 } 3503 3504 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3505 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3506 return -EOPNOTSUPP; 3507 } 3508 3509 need_update = !!eth->prog != !!prog; 3510 if (netif_running(dev) && need_update) 3511 mtk_stop(dev); 3512 3513 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3514 if (old_prog) 3515 bpf_prog_put(old_prog); 3516 3517 if (netif_running(dev) && need_update) 3518 return mtk_open(dev); 3519 3520 return 0; 3521 } 3522 3523 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3524 { 3525 switch (xdp->command) { 3526 case XDP_SETUP_PROG: 3527 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3528 default: 3529 return -EINVAL; 3530 } 3531 } 3532 3533 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3534 { 3535 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3536 reset_bits, 3537 reset_bits); 3538 3539 usleep_range(1000, 1100); 3540 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3541 reset_bits, 3542 ~reset_bits); 3543 mdelay(10); 3544 } 3545 3546 static void mtk_clk_disable(struct mtk_eth *eth) 3547 { 3548 int clk; 3549 3550 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3551 clk_disable_unprepare(eth->clks[clk]); 3552 } 3553 3554 static int mtk_clk_enable(struct mtk_eth *eth) 3555 { 3556 int clk, ret; 3557 3558 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3559 ret = clk_prepare_enable(eth->clks[clk]); 3560 if (ret) 3561 goto err_disable_clks; 3562 } 3563 3564 return 0; 3565 3566 err_disable_clks: 3567 while (--clk >= 0) 3568 clk_disable_unprepare(eth->clks[clk]); 3569 3570 return ret; 3571 } 3572 3573 static void mtk_dim_rx(struct work_struct *work) 3574 { 3575 struct dim *dim = container_of(work, struct dim, work); 3576 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3577 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3578 struct dim_cq_moder cur_profile; 3579 u32 val, cur; 3580 3581 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3582 dim->profile_ix); 3583 spin_lock_bh(ð->dim_lock); 3584 3585 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3586 val &= MTK_PDMA_DELAY_TX_MASK; 3587 val |= MTK_PDMA_DELAY_RX_EN; 3588 3589 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3590 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3591 3592 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3593 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3594 3595 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3596 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3597 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3598 3599 spin_unlock_bh(ð->dim_lock); 3600 3601 dim->state = DIM_START_MEASURE; 3602 } 3603 3604 static void mtk_dim_tx(struct work_struct *work) 3605 { 3606 struct dim *dim = container_of(work, struct dim, work); 3607 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3608 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3609 struct dim_cq_moder cur_profile; 3610 u32 val, cur; 3611 3612 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3613 dim->profile_ix); 3614 spin_lock_bh(ð->dim_lock); 3615 3616 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3617 val &= MTK_PDMA_DELAY_RX_MASK; 3618 val |= MTK_PDMA_DELAY_TX_EN; 3619 3620 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3621 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3622 3623 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3624 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3625 3626 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3627 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3628 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3629 3630 spin_unlock_bh(ð->dim_lock); 3631 3632 dim->state = DIM_START_MEASURE; 3633 } 3634 3635 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3636 { 3637 struct mtk_eth *eth = mac->hw; 3638 u32 mcr_cur, mcr_new; 3639 3640 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3641 return; 3642 3643 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3644 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3645 3646 if (val <= 1518) 3647 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3648 else if (val <= 1536) 3649 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3650 else if (val <= 1552) 3651 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3652 else 3653 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3654 3655 if (mcr_new != mcr_cur) 3656 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3657 } 3658 3659 static void mtk_hw_reset(struct mtk_eth *eth) 3660 { 3661 u32 val; 3662 3663 if (mtk_is_netsys_v2_or_greater(eth)) 3664 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3665 3666 if (mtk_is_netsys_v3_or_greater(eth)) { 3667 val = RSTCTRL_PPE0_V3; 3668 3669 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3670 val |= RSTCTRL_PPE1_V3; 3671 3672 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3673 val |= RSTCTRL_PPE2; 3674 3675 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3676 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3677 val = RSTCTRL_PPE0_V2; 3678 3679 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3680 val |= RSTCTRL_PPE1; 3681 } else { 3682 val = RSTCTRL_PPE0; 3683 } 3684 3685 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3686 3687 if (mtk_is_netsys_v3_or_greater(eth)) 3688 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3689 0x6f8ff); 3690 else if (mtk_is_netsys_v2_or_greater(eth)) 3691 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3692 0x3ffffff); 3693 } 3694 3695 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3696 { 3697 u32 val; 3698 3699 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3700 return val; 3701 } 3702 3703 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3704 { 3705 u32 rst_mask, val; 3706 3707 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3708 RSTCTRL_FE); 3709 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3710 val & RSTCTRL_FE, 1, 1000)) { 3711 dev_err(eth->dev, "warm reset failed\n"); 3712 mtk_hw_reset(eth); 3713 return; 3714 } 3715 3716 if (mtk_is_netsys_v3_or_greater(eth)) { 3717 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3; 3718 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3719 rst_mask |= RSTCTRL_PPE1_V3; 3720 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3721 rst_mask |= RSTCTRL_PPE2; 3722 3723 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3724 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3725 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3726 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3727 rst_mask |= RSTCTRL_PPE1; 3728 } else { 3729 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3730 } 3731 3732 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3733 3734 udelay(1); 3735 val = mtk_hw_reset_read(eth); 3736 if (!(val & rst_mask)) 3737 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3738 val, rst_mask); 3739 3740 rst_mask |= RSTCTRL_FE; 3741 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3742 3743 udelay(1); 3744 val = mtk_hw_reset_read(eth); 3745 if (val & rst_mask) 3746 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3747 val, rst_mask); 3748 } 3749 3750 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3751 { 3752 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3753 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3754 bool oq_hang, cdm1_busy, adma_busy; 3755 bool wtx_busy, cdm_full, oq_free; 3756 u32 wdidx, val, gdm1_fc, gdm2_fc; 3757 bool qfsm_hang, qfwd_hang; 3758 bool ret = false; 3759 3760 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3761 return false; 3762 3763 /* WDMA sanity checks */ 3764 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3765 3766 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3767 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3768 3769 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3770 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3771 3772 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3773 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3774 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3775 3776 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3777 if (++eth->reset.wdma_hang_count > 2) { 3778 eth->reset.wdma_hang_count = 0; 3779 ret = true; 3780 } 3781 goto out; 3782 } 3783 3784 /* QDMA sanity checks */ 3785 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3786 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3787 3788 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3789 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3790 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3791 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3792 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3793 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3794 3795 if (qfsm_hang && qfwd_hang && 3796 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3797 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3798 if (++eth->reset.qdma_hang_count > 2) { 3799 eth->reset.qdma_hang_count = 0; 3800 ret = true; 3801 } 3802 goto out; 3803 } 3804 3805 /* ADMA sanity checks */ 3806 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3807 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3808 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3809 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3810 3811 if (oq_hang && cdm1_busy && adma_busy) { 3812 if (++eth->reset.adma_hang_count > 2) { 3813 eth->reset.adma_hang_count = 0; 3814 ret = true; 3815 } 3816 goto out; 3817 } 3818 3819 eth->reset.wdma_hang_count = 0; 3820 eth->reset.qdma_hang_count = 0; 3821 eth->reset.adma_hang_count = 0; 3822 out: 3823 eth->reset.wdidx = wdidx; 3824 3825 return ret; 3826 } 3827 3828 static void mtk_hw_reset_monitor_work(struct work_struct *work) 3829 { 3830 struct delayed_work *del_work = to_delayed_work(work); 3831 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3832 reset.monitor_work); 3833 3834 if (test_bit(MTK_RESETTING, ð->state)) 3835 goto out; 3836 3837 /* DMA stuck checks */ 3838 if (mtk_hw_check_dma_hang(eth)) 3839 schedule_work(ð->pending_work); 3840 3841 out: 3842 schedule_delayed_work(ð->reset.monitor_work, 3843 MTK_DMA_MONITOR_TIMEOUT); 3844 } 3845 3846 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3847 { 3848 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3849 ETHSYS_DMA_AG_MAP_PPE; 3850 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3851 int i, val, ret; 3852 3853 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3854 return 0; 3855 3856 if (!reset) { 3857 pm_runtime_enable(eth->dev); 3858 pm_runtime_get_sync(eth->dev); 3859 3860 ret = mtk_clk_enable(eth); 3861 if (ret) 3862 goto err_disable_pm; 3863 } 3864 3865 if (eth->ethsys) 3866 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3867 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3868 3869 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3870 ret = device_reset(eth->dev); 3871 if (ret) { 3872 dev_err(eth->dev, "MAC reset failed!\n"); 3873 goto err_disable_pm; 3874 } 3875 3876 /* set interrupt delays based on current Net DIM sample */ 3877 mtk_dim_rx(ð->rx_dim.work); 3878 mtk_dim_tx(ð->tx_dim.work); 3879 3880 /* disable delay and normal interrupt */ 3881 mtk_tx_irq_disable(eth, ~0); 3882 mtk_rx_irq_disable(eth, ~0); 3883 3884 return 0; 3885 } 3886 3887 msleep(100); 3888 3889 if (reset) 3890 mtk_hw_warm_reset(eth); 3891 else 3892 mtk_hw_reset(eth); 3893 3894 if (mtk_is_netsys_v2_or_greater(eth)) { 3895 /* Set FE to PDMAv2 if necessary */ 3896 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3897 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3898 } 3899 3900 if (eth->pctl) { 3901 /* Set GE2 driving and slew rate */ 3902 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3903 3904 /* set GE2 TDSEL */ 3905 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3906 3907 /* set GE2 TUNE */ 3908 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3909 } 3910 3911 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3912 * up with the more appropriate value when mtk_mac_config call is being 3913 * invoked. 3914 */ 3915 for (i = 0; i < MTK_MAX_DEVS; i++) { 3916 struct net_device *dev = eth->netdev[i]; 3917 3918 if (!dev) 3919 continue; 3920 3921 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3922 mtk_set_mcr_max_rx(netdev_priv(dev), 3923 dev->mtu + MTK_RX_ETH_HLEN); 3924 } 3925 3926 /* Indicates CDM to parse the MTK special tag from CPU 3927 * which also is working out for untag packets. 3928 */ 3929 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3930 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3931 if (mtk_is_netsys_v1(eth)) { 3932 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3933 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 3934 3935 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3936 } 3937 3938 /* set interrupt delays based on current Net DIM sample */ 3939 mtk_dim_rx(ð->rx_dim.work); 3940 mtk_dim_tx(ð->tx_dim.work); 3941 3942 /* disable delay and normal interrupt */ 3943 mtk_tx_irq_disable(eth, ~0); 3944 mtk_rx_irq_disable(eth, ~0); 3945 3946 /* FE int grouping */ 3947 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3948 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3949 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3950 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3951 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3952 3953 if (mtk_is_netsys_v3_or_greater(eth)) { 3954 /* PSE should not drop port1, port8 and port9 packets */ 3955 mtk_w32(eth, 0x00000302, PSE_DROP_CFG); 3956 3957 /* GDM and CDM Threshold */ 3958 mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); 3959 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); 3960 3961 /* Disable GDM1 RX CRC stripping */ 3962 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); 3963 3964 /* PSE GDM3 MIB counter has incorrect hw default values, 3965 * so the driver ought to read clear the values beforehand 3966 * in case ethtool retrieve wrong mib values. 3967 */ 3968 for (i = 0; i < 0x80; i += 0x4) 3969 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); 3970 } else if (!mtk_is_netsys_v1(eth)) { 3971 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 3972 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3973 3974 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 3975 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 3976 3977 /* PSE Free Queue Flow Control */ 3978 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3979 3980 /* PSE config input queue threshold */ 3981 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3982 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3983 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3984 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3985 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3986 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3987 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3988 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3989 3990 /* PSE config output queue threshold */ 3991 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3992 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3993 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3994 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3995 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3996 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3997 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3998 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3999 4000 /* GDM and CDM Threshold */ 4001 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 4002 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 4003 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 4004 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 4005 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 4006 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 4007 } 4008 4009 return 0; 4010 4011 err_disable_pm: 4012 if (!reset) { 4013 pm_runtime_put_sync(eth->dev); 4014 pm_runtime_disable(eth->dev); 4015 } 4016 4017 return ret; 4018 } 4019 4020 static int mtk_hw_deinit(struct mtk_eth *eth) 4021 { 4022 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 4023 return 0; 4024 4025 mtk_clk_disable(eth); 4026 4027 pm_runtime_put_sync(eth->dev); 4028 pm_runtime_disable(eth->dev); 4029 4030 return 0; 4031 } 4032 4033 static void mtk_uninit(struct net_device *dev) 4034 { 4035 struct mtk_mac *mac = netdev_priv(dev); 4036 struct mtk_eth *eth = mac->hw; 4037 4038 phylink_disconnect_phy(mac->phylink); 4039 mtk_tx_irq_disable(eth, ~0); 4040 mtk_rx_irq_disable(eth, ~0); 4041 } 4042 4043 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 4044 { 4045 int length = new_mtu + MTK_RX_ETH_HLEN; 4046 struct mtk_mac *mac = netdev_priv(dev); 4047 struct mtk_eth *eth = mac->hw; 4048 4049 if (rcu_access_pointer(eth->prog) && 4050 length > MTK_PP_MAX_BUF_SIZE) { 4051 netdev_err(dev, "Invalid MTU for XDP mode\n"); 4052 return -EINVAL; 4053 } 4054 4055 mtk_set_mcr_max_rx(mac, length); 4056 dev->mtu = new_mtu; 4057 4058 return 0; 4059 } 4060 4061 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4062 { 4063 struct mtk_mac *mac = netdev_priv(dev); 4064 4065 switch (cmd) { 4066 case SIOCGMIIPHY: 4067 case SIOCGMIIREG: 4068 case SIOCSMIIREG: 4069 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 4070 default: 4071 break; 4072 } 4073 4074 return -EOPNOTSUPP; 4075 } 4076 4077 static void mtk_prepare_for_reset(struct mtk_eth *eth) 4078 { 4079 u32 val; 4080 int i; 4081 4082 /* set FE PPE ports link down */ 4083 for (i = MTK_GMAC1_ID; 4084 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4085 i += 2) { 4086 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4087 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4088 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4089 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4090 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4091 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4092 } 4093 4094 /* adjust PPE configurations to prepare for reset */ 4095 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 4096 mtk_ppe_prepare_reset(eth->ppe[i]); 4097 4098 /* disable NETSYS interrupts */ 4099 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 4100 4101 /* force link down GMAC */ 4102 for (i = 0; i < 2; i++) { 4103 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 4104 mtk_w32(eth, val, MTK_MAC_MCR(i)); 4105 } 4106 } 4107 4108 static void mtk_pending_work(struct work_struct *work) 4109 { 4110 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 4111 unsigned long restart = 0; 4112 u32 val; 4113 int i; 4114 4115 rtnl_lock(); 4116 set_bit(MTK_RESETTING, ð->state); 4117 4118 mtk_prepare_for_reset(eth); 4119 mtk_wed_fe_reset(); 4120 /* Run again reset preliminary configuration in order to avoid any 4121 * possible race during FE reset since it can run releasing RTNL lock. 4122 */ 4123 mtk_prepare_for_reset(eth); 4124 4125 /* stop all devices to make sure that dma is properly shut down */ 4126 for (i = 0; i < MTK_MAX_DEVS; i++) { 4127 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 4128 continue; 4129 4130 mtk_stop(eth->netdev[i]); 4131 __set_bit(i, &restart); 4132 } 4133 4134 usleep_range(15000, 16000); 4135 4136 if (eth->dev->pins) 4137 pinctrl_select_state(eth->dev->pins->p, 4138 eth->dev->pins->default_state); 4139 mtk_hw_init(eth, true); 4140 4141 /* restart DMA and enable IRQs */ 4142 for (i = 0; i < MTK_MAX_DEVS; i++) { 4143 if (!eth->netdev[i] || !test_bit(i, &restart)) 4144 continue; 4145 4146 if (mtk_open(eth->netdev[i])) { 4147 netif_alert(eth, ifup, eth->netdev[i], 4148 "Driver up/down cycle failed\n"); 4149 dev_close(eth->netdev[i]); 4150 } 4151 } 4152 4153 /* set FE PPE ports link up */ 4154 for (i = MTK_GMAC1_ID; 4155 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4156 i += 2) { 4157 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4158 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4159 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4160 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4161 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4162 4163 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4164 } 4165 4166 clear_bit(MTK_RESETTING, ð->state); 4167 4168 mtk_wed_fe_reset_complete(); 4169 4170 rtnl_unlock(); 4171 } 4172 4173 static int mtk_free_dev(struct mtk_eth *eth) 4174 { 4175 int i; 4176 4177 for (i = 0; i < MTK_MAX_DEVS; i++) { 4178 if (!eth->netdev[i]) 4179 continue; 4180 free_netdev(eth->netdev[i]); 4181 } 4182 4183 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4184 if (!eth->dsa_meta[i]) 4185 break; 4186 metadata_dst_free(eth->dsa_meta[i]); 4187 } 4188 4189 return 0; 4190 } 4191 4192 static int mtk_unreg_dev(struct mtk_eth *eth) 4193 { 4194 int i; 4195 4196 for (i = 0; i < MTK_MAX_DEVS; i++) { 4197 struct mtk_mac *mac; 4198 if (!eth->netdev[i]) 4199 continue; 4200 mac = netdev_priv(eth->netdev[i]); 4201 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4202 unregister_netdevice_notifier(&mac->device_notifier); 4203 unregister_netdev(eth->netdev[i]); 4204 } 4205 4206 return 0; 4207 } 4208 4209 static void mtk_sgmii_destroy(struct mtk_eth *eth) 4210 { 4211 int i; 4212 4213 for (i = 0; i < MTK_MAX_DEVS; i++) 4214 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); 4215 } 4216 4217 static int mtk_cleanup(struct mtk_eth *eth) 4218 { 4219 mtk_sgmii_destroy(eth); 4220 mtk_unreg_dev(eth); 4221 mtk_free_dev(eth); 4222 cancel_work_sync(ð->pending_work); 4223 cancel_delayed_work_sync(ð->reset.monitor_work); 4224 4225 return 0; 4226 } 4227 4228 static int mtk_get_link_ksettings(struct net_device *ndev, 4229 struct ethtool_link_ksettings *cmd) 4230 { 4231 struct mtk_mac *mac = netdev_priv(ndev); 4232 4233 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4234 return -EBUSY; 4235 4236 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4237 } 4238 4239 static int mtk_set_link_ksettings(struct net_device *ndev, 4240 const struct ethtool_link_ksettings *cmd) 4241 { 4242 struct mtk_mac *mac = netdev_priv(ndev); 4243 4244 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4245 return -EBUSY; 4246 4247 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4248 } 4249 4250 static void mtk_get_drvinfo(struct net_device *dev, 4251 struct ethtool_drvinfo *info) 4252 { 4253 struct mtk_mac *mac = netdev_priv(dev); 4254 4255 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4256 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4257 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4258 } 4259 4260 static u32 mtk_get_msglevel(struct net_device *dev) 4261 { 4262 struct mtk_mac *mac = netdev_priv(dev); 4263 4264 return mac->hw->msg_enable; 4265 } 4266 4267 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4268 { 4269 struct mtk_mac *mac = netdev_priv(dev); 4270 4271 mac->hw->msg_enable = value; 4272 } 4273 4274 static int mtk_nway_reset(struct net_device *dev) 4275 { 4276 struct mtk_mac *mac = netdev_priv(dev); 4277 4278 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4279 return -EBUSY; 4280 4281 if (!mac->phylink) 4282 return -ENOTSUPP; 4283 4284 return phylink_ethtool_nway_reset(mac->phylink); 4285 } 4286 4287 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4288 { 4289 int i; 4290 4291 switch (stringset) { 4292 case ETH_SS_STATS: { 4293 struct mtk_mac *mac = netdev_priv(dev); 4294 4295 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 4296 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 4297 data += ETH_GSTRING_LEN; 4298 } 4299 if (mtk_page_pool_enabled(mac->hw)) 4300 page_pool_ethtool_stats_get_strings(data); 4301 break; 4302 } 4303 default: 4304 break; 4305 } 4306 } 4307 4308 static int mtk_get_sset_count(struct net_device *dev, int sset) 4309 { 4310 switch (sset) { 4311 case ETH_SS_STATS: { 4312 int count = ARRAY_SIZE(mtk_ethtool_stats); 4313 struct mtk_mac *mac = netdev_priv(dev); 4314 4315 if (mtk_page_pool_enabled(mac->hw)) 4316 count += page_pool_ethtool_stats_get_count(); 4317 return count; 4318 } 4319 default: 4320 return -EOPNOTSUPP; 4321 } 4322 } 4323 4324 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4325 { 4326 struct page_pool_stats stats = {}; 4327 int i; 4328 4329 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4330 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4331 4332 if (!ring->page_pool) 4333 continue; 4334 4335 page_pool_get_stats(ring->page_pool, &stats); 4336 } 4337 page_pool_ethtool_stats_get(data, &stats); 4338 } 4339 4340 static void mtk_get_ethtool_stats(struct net_device *dev, 4341 struct ethtool_stats *stats, u64 *data) 4342 { 4343 struct mtk_mac *mac = netdev_priv(dev); 4344 struct mtk_hw_stats *hwstats = mac->hw_stats; 4345 u64 *data_src, *data_dst; 4346 unsigned int start; 4347 int i; 4348 4349 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4350 return; 4351 4352 if (netif_running(dev) && netif_device_present(dev)) { 4353 if (spin_trylock_bh(&hwstats->stats_lock)) { 4354 mtk_stats_update_mac(mac); 4355 spin_unlock_bh(&hwstats->stats_lock); 4356 } 4357 } 4358 4359 data_src = (u64 *)hwstats; 4360 4361 do { 4362 data_dst = data; 4363 start = u64_stats_fetch_begin(&hwstats->syncp); 4364 4365 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4366 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4367 if (mtk_page_pool_enabled(mac->hw)) 4368 mtk_ethtool_pp_stats(mac->hw, data_dst); 4369 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4370 } 4371 4372 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4373 u32 *rule_locs) 4374 { 4375 int ret = -EOPNOTSUPP; 4376 4377 switch (cmd->cmd) { 4378 case ETHTOOL_GRXRINGS: 4379 if (dev->hw_features & NETIF_F_LRO) { 4380 cmd->data = MTK_MAX_RX_RING_NUM; 4381 ret = 0; 4382 } 4383 break; 4384 case ETHTOOL_GRXCLSRLCNT: 4385 if (dev->hw_features & NETIF_F_LRO) { 4386 struct mtk_mac *mac = netdev_priv(dev); 4387 4388 cmd->rule_cnt = mac->hwlro_ip_cnt; 4389 ret = 0; 4390 } 4391 break; 4392 case ETHTOOL_GRXCLSRULE: 4393 if (dev->hw_features & NETIF_F_LRO) 4394 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4395 break; 4396 case ETHTOOL_GRXCLSRLALL: 4397 if (dev->hw_features & NETIF_F_LRO) 4398 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4399 rule_locs); 4400 break; 4401 default: 4402 break; 4403 } 4404 4405 return ret; 4406 } 4407 4408 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4409 { 4410 int ret = -EOPNOTSUPP; 4411 4412 switch (cmd->cmd) { 4413 case ETHTOOL_SRXCLSRLINS: 4414 if (dev->hw_features & NETIF_F_LRO) 4415 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4416 break; 4417 case ETHTOOL_SRXCLSRLDEL: 4418 if (dev->hw_features & NETIF_F_LRO) 4419 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4420 break; 4421 default: 4422 break; 4423 } 4424 4425 return ret; 4426 } 4427 4428 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4429 struct net_device *sb_dev) 4430 { 4431 struct mtk_mac *mac = netdev_priv(dev); 4432 unsigned int queue = 0; 4433 4434 if (netdev_uses_dsa(dev)) 4435 queue = skb_get_queue_mapping(skb) + 3; 4436 else 4437 queue = mac->id; 4438 4439 if (queue >= dev->num_tx_queues) 4440 queue = 0; 4441 4442 return queue; 4443 } 4444 4445 static const struct ethtool_ops mtk_ethtool_ops = { 4446 .get_link_ksettings = mtk_get_link_ksettings, 4447 .set_link_ksettings = mtk_set_link_ksettings, 4448 .get_drvinfo = mtk_get_drvinfo, 4449 .get_msglevel = mtk_get_msglevel, 4450 .set_msglevel = mtk_set_msglevel, 4451 .nway_reset = mtk_nway_reset, 4452 .get_link = ethtool_op_get_link, 4453 .get_strings = mtk_get_strings, 4454 .get_sset_count = mtk_get_sset_count, 4455 .get_ethtool_stats = mtk_get_ethtool_stats, 4456 .get_rxnfc = mtk_get_rxnfc, 4457 .set_rxnfc = mtk_set_rxnfc, 4458 }; 4459 4460 static const struct net_device_ops mtk_netdev_ops = { 4461 .ndo_uninit = mtk_uninit, 4462 .ndo_open = mtk_open, 4463 .ndo_stop = mtk_stop, 4464 .ndo_start_xmit = mtk_start_xmit, 4465 .ndo_set_mac_address = mtk_set_mac_address, 4466 .ndo_validate_addr = eth_validate_addr, 4467 .ndo_eth_ioctl = mtk_do_ioctl, 4468 .ndo_change_mtu = mtk_change_mtu, 4469 .ndo_tx_timeout = mtk_tx_timeout, 4470 .ndo_get_stats64 = mtk_get_stats64, 4471 .ndo_fix_features = mtk_fix_features, 4472 .ndo_set_features = mtk_set_features, 4473 #ifdef CONFIG_NET_POLL_CONTROLLER 4474 .ndo_poll_controller = mtk_poll_controller, 4475 #endif 4476 .ndo_setup_tc = mtk_eth_setup_tc, 4477 .ndo_bpf = mtk_xdp, 4478 .ndo_xdp_xmit = mtk_xdp_xmit, 4479 .ndo_select_queue = mtk_select_queue, 4480 }; 4481 4482 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4483 { 4484 const __be32 *_id = of_get_property(np, "reg", NULL); 4485 phy_interface_t phy_mode; 4486 struct phylink *phylink; 4487 struct mtk_mac *mac; 4488 int id, err; 4489 int txqs = 1; 4490 u32 val; 4491 4492 if (!_id) { 4493 dev_err(eth->dev, "missing mac id\n"); 4494 return -EINVAL; 4495 } 4496 4497 id = be32_to_cpup(_id); 4498 if (id >= MTK_MAX_DEVS) { 4499 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4500 return -EINVAL; 4501 } 4502 4503 if (eth->netdev[id]) { 4504 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4505 return -EINVAL; 4506 } 4507 4508 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4509 txqs = MTK_QDMA_NUM_QUEUES; 4510 4511 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4512 if (!eth->netdev[id]) { 4513 dev_err(eth->dev, "alloc_etherdev failed\n"); 4514 return -ENOMEM; 4515 } 4516 mac = netdev_priv(eth->netdev[id]); 4517 eth->mac[id] = mac; 4518 mac->id = id; 4519 mac->hw = eth; 4520 mac->of_node = np; 4521 4522 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); 4523 if (err == -EPROBE_DEFER) 4524 return err; 4525 4526 if (err) { 4527 /* If the mac address is invalid, use random mac address */ 4528 eth_hw_addr_random(eth->netdev[id]); 4529 dev_err(eth->dev, "generated random MAC address %pM\n", 4530 eth->netdev[id]->dev_addr); 4531 } 4532 4533 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4534 mac->hwlro_ip_cnt = 0; 4535 4536 mac->hw_stats = devm_kzalloc(eth->dev, 4537 sizeof(*mac->hw_stats), 4538 GFP_KERNEL); 4539 if (!mac->hw_stats) { 4540 dev_err(eth->dev, "failed to allocate counter memory\n"); 4541 err = -ENOMEM; 4542 goto free_netdev; 4543 } 4544 spin_lock_init(&mac->hw_stats->stats_lock); 4545 u64_stats_init(&mac->hw_stats->syncp); 4546 4547 if (mtk_is_netsys_v3_or_greater(eth)) 4548 mac->hw_stats->reg_offset = id * 0x80; 4549 else 4550 mac->hw_stats->reg_offset = id * 0x40; 4551 4552 /* phylink create */ 4553 err = of_get_phy_mode(np, &phy_mode); 4554 if (err) { 4555 dev_err(eth->dev, "incorrect phy-mode\n"); 4556 goto free_netdev; 4557 } 4558 4559 /* mac config is not set */ 4560 mac->interface = PHY_INTERFACE_MODE_NA; 4561 mac->speed = SPEED_UNKNOWN; 4562 4563 mac->phylink_config.dev = ð->netdev[id]->dev; 4564 mac->phylink_config.type = PHYLINK_NETDEV; 4565 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4566 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4567 4568 /* MT7623 gmac0 is now missing its speed-specific PLL configuration 4569 * in its .mac_config method (since state->speed is not valid there. 4570 * Disable support for MII, GMII and RGMII. 4571 */ 4572 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { 4573 __set_bit(PHY_INTERFACE_MODE_MII, 4574 mac->phylink_config.supported_interfaces); 4575 __set_bit(PHY_INTERFACE_MODE_GMII, 4576 mac->phylink_config.supported_interfaces); 4577 4578 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4579 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4580 } 4581 4582 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4583 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4584 mac->phylink_config.supported_interfaces); 4585 4586 /* TRGMII is not permitted on MT7621 if using DDR2 */ 4587 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 4588 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 4589 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 4590 if (val & SYSCFG_DRAM_TYPE_DDR2) 4591 __clear_bit(PHY_INTERFACE_MODE_TRGMII, 4592 mac->phylink_config.supported_interfaces); 4593 } 4594 4595 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4596 __set_bit(PHY_INTERFACE_MODE_SGMII, 4597 mac->phylink_config.supported_interfaces); 4598 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4599 mac->phylink_config.supported_interfaces); 4600 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4601 mac->phylink_config.supported_interfaces); 4602 } 4603 4604 if (mtk_is_netsys_v3_or_greater(mac->hw) && 4605 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && 4606 id == MTK_GMAC1_ID) { 4607 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 4608 MAC_SYM_PAUSE | 4609 MAC_10000FD; 4610 phy_interface_zero(mac->phylink_config.supported_interfaces); 4611 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 4612 mac->phylink_config.supported_interfaces); 4613 } 4614 4615 phylink = phylink_create(&mac->phylink_config, 4616 of_fwnode_handle(mac->of_node), 4617 phy_mode, &mtk_phylink_ops); 4618 if (IS_ERR(phylink)) { 4619 err = PTR_ERR(phylink); 4620 goto free_netdev; 4621 } 4622 4623 mac->phylink = phylink; 4624 4625 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4626 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4627 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4628 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4629 4630 eth->netdev[id]->hw_features = eth->soc->hw_features; 4631 if (eth->hwlro) 4632 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4633 4634 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4635 ~NETIF_F_HW_VLAN_CTAG_TX; 4636 eth->netdev[id]->features |= eth->soc->hw_features; 4637 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4638 4639 eth->netdev[id]->irq = eth->irq[0]; 4640 eth->netdev[id]->dev.of_node = np; 4641 4642 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4643 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4644 else 4645 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4646 4647 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4648 mac->device_notifier.notifier_call = mtk_device_event; 4649 register_netdevice_notifier(&mac->device_notifier); 4650 } 4651 4652 if (mtk_page_pool_enabled(eth)) 4653 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4654 NETDEV_XDP_ACT_REDIRECT | 4655 NETDEV_XDP_ACT_NDO_XMIT | 4656 NETDEV_XDP_ACT_NDO_XMIT_SG; 4657 4658 return 0; 4659 4660 free_netdev: 4661 free_netdev(eth->netdev[id]); 4662 return err; 4663 } 4664 4665 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4666 { 4667 struct net_device *dev, *tmp; 4668 LIST_HEAD(dev_list); 4669 int i; 4670 4671 rtnl_lock(); 4672 4673 for (i = 0; i < MTK_MAX_DEVS; i++) { 4674 dev = eth->netdev[i]; 4675 4676 if (!dev || !(dev->flags & IFF_UP)) 4677 continue; 4678 4679 list_add_tail(&dev->close_list, &dev_list); 4680 } 4681 4682 dev_close_many(&dev_list, false); 4683 4684 eth->dma_dev = dma_dev; 4685 4686 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4687 list_del_init(&dev->close_list); 4688 dev_open(dev, NULL); 4689 } 4690 4691 rtnl_unlock(); 4692 } 4693 4694 static int mtk_sgmii_init(struct mtk_eth *eth) 4695 { 4696 struct device_node *np; 4697 struct regmap *regmap; 4698 u32 flags; 4699 int i; 4700 4701 for (i = 0; i < MTK_MAX_DEVS; i++) { 4702 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); 4703 if (!np) 4704 break; 4705 4706 regmap = syscon_node_to_regmap(np); 4707 flags = 0; 4708 if (of_property_read_bool(np, "mediatek,pnswap")) 4709 flags |= MTK_SGMII_FLAG_PN_SWAP; 4710 4711 of_node_put(np); 4712 4713 if (IS_ERR(regmap)) 4714 return PTR_ERR(regmap); 4715 4716 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, 4717 eth->soc->ana_rgc3, 4718 flags); 4719 } 4720 4721 return 0; 4722 } 4723 4724 static int mtk_probe(struct platform_device *pdev) 4725 { 4726 struct resource *res = NULL, *res_sram; 4727 struct device_node *mac_np; 4728 struct mtk_eth *eth; 4729 int err, i; 4730 4731 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4732 if (!eth) 4733 return -ENOMEM; 4734 4735 eth->soc = of_device_get_match_data(&pdev->dev); 4736 4737 eth->dev = &pdev->dev; 4738 eth->dma_dev = &pdev->dev; 4739 eth->base = devm_platform_ioremap_resource(pdev, 0); 4740 if (IS_ERR(eth->base)) 4741 return PTR_ERR(eth->base); 4742 4743 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4744 eth->ip_align = NET_IP_ALIGN; 4745 4746 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4747 /* SRAM is actual memory and supports transparent access just like DRAM. 4748 * Hence we don't require __iomem being set and don't need to use accessor 4749 * functions to read from or write to SRAM. 4750 */ 4751 if (mtk_is_netsys_v3_or_greater(eth)) { 4752 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1); 4753 if (IS_ERR(eth->sram_base)) 4754 return PTR_ERR(eth->sram_base); 4755 } else { 4756 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; 4757 } 4758 } 4759 4760 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { 4761 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); 4762 if (err) { 4763 dev_err(&pdev->dev, "Wrong DMA config\n"); 4764 return -EINVAL; 4765 } 4766 } 4767 4768 spin_lock_init(ð->page_lock); 4769 spin_lock_init(ð->tx_irq_lock); 4770 spin_lock_init(ð->rx_irq_lock); 4771 spin_lock_init(ð->dim_lock); 4772 4773 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4774 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4775 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4776 4777 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4778 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4779 4780 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4781 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4782 "mediatek,ethsys"); 4783 if (IS_ERR(eth->ethsys)) { 4784 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4785 return PTR_ERR(eth->ethsys); 4786 } 4787 } 4788 4789 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4790 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4791 "mediatek,infracfg"); 4792 if (IS_ERR(eth->infra)) { 4793 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4794 return PTR_ERR(eth->infra); 4795 } 4796 } 4797 4798 if (of_dma_is_coherent(pdev->dev.of_node)) { 4799 struct regmap *cci; 4800 4801 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4802 "cci-control-port"); 4803 /* enable CPU/bus coherency */ 4804 if (!IS_ERR(cci)) 4805 regmap_write(cci, 0, 3); 4806 } 4807 4808 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4809 err = mtk_sgmii_init(eth); 4810 4811 if (err) 4812 return err; 4813 } 4814 4815 if (eth->soc->required_pctl) { 4816 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4817 "mediatek,pctl"); 4818 if (IS_ERR(eth->pctl)) { 4819 dev_err(&pdev->dev, "no pctl regmap found\n"); 4820 err = PTR_ERR(eth->pctl); 4821 goto err_destroy_sgmii; 4822 } 4823 } 4824 4825 if (mtk_is_netsys_v2_or_greater(eth)) { 4826 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4827 if (!res) { 4828 err = -EINVAL; 4829 goto err_destroy_sgmii; 4830 } 4831 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4832 if (mtk_is_netsys_v3_or_greater(eth)) { 4833 res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1); 4834 if (!res_sram) { 4835 err = -EINVAL; 4836 goto err_destroy_sgmii; 4837 } 4838 eth->phy_scratch_ring = res_sram->start; 4839 } else { 4840 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; 4841 } 4842 } 4843 } 4844 4845 if (eth->soc->offload_version) { 4846 for (i = 0;; i++) { 4847 struct device_node *np; 4848 phys_addr_t wdma_phy; 4849 u32 wdma_base; 4850 4851 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4852 break; 4853 4854 np = of_parse_phandle(pdev->dev.of_node, 4855 "mediatek,wed", i); 4856 if (!np) 4857 break; 4858 4859 wdma_base = eth->soc->reg_map->wdma_base[i]; 4860 wdma_phy = res ? res->start + wdma_base : 0; 4861 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4862 wdma_phy, i); 4863 } 4864 } 4865 4866 for (i = 0; i < 3; i++) { 4867 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4868 eth->irq[i] = eth->irq[0]; 4869 else 4870 eth->irq[i] = platform_get_irq(pdev, i); 4871 if (eth->irq[i] < 0) { 4872 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4873 err = -ENXIO; 4874 goto err_wed_exit; 4875 } 4876 } 4877 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4878 eth->clks[i] = devm_clk_get(eth->dev, 4879 mtk_clks_source_name[i]); 4880 if (IS_ERR(eth->clks[i])) { 4881 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4882 err = -EPROBE_DEFER; 4883 goto err_wed_exit; 4884 } 4885 if (eth->soc->required_clks & BIT(i)) { 4886 dev_err(&pdev->dev, "clock %s not found\n", 4887 mtk_clks_source_name[i]); 4888 err = -EINVAL; 4889 goto err_wed_exit; 4890 } 4891 eth->clks[i] = NULL; 4892 } 4893 } 4894 4895 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4896 INIT_WORK(ð->pending_work, mtk_pending_work); 4897 4898 err = mtk_hw_init(eth, false); 4899 if (err) 4900 goto err_wed_exit; 4901 4902 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4903 4904 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4905 if (!of_device_is_compatible(mac_np, 4906 "mediatek,eth-mac")) 4907 continue; 4908 4909 if (!of_device_is_available(mac_np)) 4910 continue; 4911 4912 err = mtk_add_mac(eth, mac_np); 4913 if (err) { 4914 of_node_put(mac_np); 4915 goto err_deinit_hw; 4916 } 4917 } 4918 4919 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4920 err = devm_request_irq(eth->dev, eth->irq[0], 4921 mtk_handle_irq, 0, 4922 dev_name(eth->dev), eth); 4923 } else { 4924 err = devm_request_irq(eth->dev, eth->irq[1], 4925 mtk_handle_irq_tx, 0, 4926 dev_name(eth->dev), eth); 4927 if (err) 4928 goto err_free_dev; 4929 4930 err = devm_request_irq(eth->dev, eth->irq[2], 4931 mtk_handle_irq_rx, 0, 4932 dev_name(eth->dev), eth); 4933 } 4934 if (err) 4935 goto err_free_dev; 4936 4937 /* No MT7628/88 support yet */ 4938 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4939 err = mtk_mdio_init(eth); 4940 if (err) 4941 goto err_free_dev; 4942 } 4943 4944 if (eth->soc->offload_version) { 4945 u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1; 4946 4947 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4948 for (i = 0; i < num_ppe; i++) { 4949 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; 4950 4951 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); 4952 4953 if (!eth->ppe[i]) { 4954 err = -ENOMEM; 4955 goto err_deinit_ppe; 4956 } 4957 } 4958 4959 err = mtk_eth_offload_init(eth); 4960 if (err) 4961 goto err_deinit_ppe; 4962 } 4963 4964 for (i = 0; i < MTK_MAX_DEVS; i++) { 4965 if (!eth->netdev[i]) 4966 continue; 4967 4968 err = register_netdev(eth->netdev[i]); 4969 if (err) { 4970 dev_err(eth->dev, "error bringing up device\n"); 4971 goto err_deinit_ppe; 4972 } else 4973 netif_info(eth, probe, eth->netdev[i], 4974 "mediatek frame engine at 0x%08lx, irq %d\n", 4975 eth->netdev[i]->base_addr, eth->irq[0]); 4976 } 4977 4978 /* we run 2 devices on the same DMA ring so we need a dummy device 4979 * for NAPI to work 4980 */ 4981 init_dummy_netdev(ð->dummy_dev); 4982 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); 4983 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); 4984 4985 platform_set_drvdata(pdev, eth); 4986 schedule_delayed_work(ð->reset.monitor_work, 4987 MTK_DMA_MONITOR_TIMEOUT); 4988 4989 return 0; 4990 4991 err_deinit_ppe: 4992 mtk_ppe_deinit(eth); 4993 mtk_mdio_cleanup(eth); 4994 err_free_dev: 4995 mtk_free_dev(eth); 4996 err_deinit_hw: 4997 mtk_hw_deinit(eth); 4998 err_wed_exit: 4999 mtk_wed_exit(); 5000 err_destroy_sgmii: 5001 mtk_sgmii_destroy(eth); 5002 5003 return err; 5004 } 5005 5006 static void mtk_remove(struct platform_device *pdev) 5007 { 5008 struct mtk_eth *eth = platform_get_drvdata(pdev); 5009 struct mtk_mac *mac; 5010 int i; 5011 5012 /* stop all devices to make sure that dma is properly shut down */ 5013 for (i = 0; i < MTK_MAX_DEVS; i++) { 5014 if (!eth->netdev[i]) 5015 continue; 5016 mtk_stop(eth->netdev[i]); 5017 mac = netdev_priv(eth->netdev[i]); 5018 phylink_disconnect_phy(mac->phylink); 5019 } 5020 5021 mtk_wed_exit(); 5022 mtk_hw_deinit(eth); 5023 5024 netif_napi_del(ð->tx_napi); 5025 netif_napi_del(ð->rx_napi); 5026 mtk_cleanup(eth); 5027 mtk_mdio_cleanup(eth); 5028 } 5029 5030 static const struct mtk_soc_data mt2701_data = { 5031 .reg_map = &mtk_reg_map, 5032 .caps = MT7623_CAPS | MTK_HWLRO, 5033 .hw_features = MTK_HW_FEATURES, 5034 .required_clks = MT7623_CLKS_BITMAP, 5035 .required_pctl = true, 5036 .version = 1, 5037 .txrx = { 5038 .txd_size = sizeof(struct mtk_tx_dma), 5039 .rxd_size = sizeof(struct mtk_rx_dma), 5040 .rx_irq_done_mask = MTK_RX_DONE_INT, 5041 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5042 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5043 .dma_len_offset = 16, 5044 }, 5045 }; 5046 5047 static const struct mtk_soc_data mt7621_data = { 5048 .reg_map = &mtk_reg_map, 5049 .caps = MT7621_CAPS, 5050 .hw_features = MTK_HW_FEATURES, 5051 .required_clks = MT7621_CLKS_BITMAP, 5052 .required_pctl = false, 5053 .version = 1, 5054 .offload_version = 1, 5055 .hash_offset = 2, 5056 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5057 .txrx = { 5058 .txd_size = sizeof(struct mtk_tx_dma), 5059 .rxd_size = sizeof(struct mtk_rx_dma), 5060 .rx_irq_done_mask = MTK_RX_DONE_INT, 5061 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5062 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5063 .dma_len_offset = 16, 5064 }, 5065 }; 5066 5067 static const struct mtk_soc_data mt7622_data = { 5068 .reg_map = &mtk_reg_map, 5069 .ana_rgc3 = 0x2028, 5070 .caps = MT7622_CAPS | MTK_HWLRO, 5071 .hw_features = MTK_HW_FEATURES, 5072 .required_clks = MT7622_CLKS_BITMAP, 5073 .required_pctl = false, 5074 .version = 1, 5075 .offload_version = 2, 5076 .hash_offset = 2, 5077 .has_accounting = true, 5078 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5079 .txrx = { 5080 .txd_size = sizeof(struct mtk_tx_dma), 5081 .rxd_size = sizeof(struct mtk_rx_dma), 5082 .rx_irq_done_mask = MTK_RX_DONE_INT, 5083 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5084 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5085 .dma_len_offset = 16, 5086 }, 5087 }; 5088 5089 static const struct mtk_soc_data mt7623_data = { 5090 .reg_map = &mtk_reg_map, 5091 .caps = MT7623_CAPS | MTK_HWLRO, 5092 .hw_features = MTK_HW_FEATURES, 5093 .required_clks = MT7623_CLKS_BITMAP, 5094 .required_pctl = true, 5095 .version = 1, 5096 .offload_version = 1, 5097 .hash_offset = 2, 5098 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5099 .disable_pll_modes = true, 5100 .txrx = { 5101 .txd_size = sizeof(struct mtk_tx_dma), 5102 .rxd_size = sizeof(struct mtk_rx_dma), 5103 .rx_irq_done_mask = MTK_RX_DONE_INT, 5104 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5105 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5106 .dma_len_offset = 16, 5107 }, 5108 }; 5109 5110 static const struct mtk_soc_data mt7629_data = { 5111 .reg_map = &mtk_reg_map, 5112 .ana_rgc3 = 0x128, 5113 .caps = MT7629_CAPS | MTK_HWLRO, 5114 .hw_features = MTK_HW_FEATURES, 5115 .required_clks = MT7629_CLKS_BITMAP, 5116 .required_pctl = false, 5117 .has_accounting = true, 5118 .version = 1, 5119 .txrx = { 5120 .txd_size = sizeof(struct mtk_tx_dma), 5121 .rxd_size = sizeof(struct mtk_rx_dma), 5122 .rx_irq_done_mask = MTK_RX_DONE_INT, 5123 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5124 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5125 .dma_len_offset = 16, 5126 }, 5127 }; 5128 5129 static const struct mtk_soc_data mt7981_data = { 5130 .reg_map = &mt7986_reg_map, 5131 .ana_rgc3 = 0x128, 5132 .caps = MT7981_CAPS, 5133 .hw_features = MTK_HW_FEATURES, 5134 .required_clks = MT7981_CLKS_BITMAP, 5135 .required_pctl = false, 5136 .version = 2, 5137 .offload_version = 2, 5138 .hash_offset = 4, 5139 .has_accounting = true, 5140 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5141 .txrx = { 5142 .txd_size = sizeof(struct mtk_tx_dma_v2), 5143 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5144 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5145 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5146 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5147 .dma_len_offset = 8, 5148 }, 5149 }; 5150 5151 static const struct mtk_soc_data mt7986_data = { 5152 .reg_map = &mt7986_reg_map, 5153 .ana_rgc3 = 0x128, 5154 .caps = MT7986_CAPS, 5155 .hw_features = MTK_HW_FEATURES, 5156 .required_clks = MT7986_CLKS_BITMAP, 5157 .required_pctl = false, 5158 .version = 2, 5159 .offload_version = 2, 5160 .hash_offset = 4, 5161 .has_accounting = true, 5162 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5163 .txrx = { 5164 .txd_size = sizeof(struct mtk_tx_dma_v2), 5165 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5166 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5167 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5168 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5169 .dma_len_offset = 8, 5170 }, 5171 }; 5172 5173 static const struct mtk_soc_data mt7988_data = { 5174 .reg_map = &mt7988_reg_map, 5175 .ana_rgc3 = 0x128, 5176 .caps = MT7988_CAPS, 5177 .hw_features = MTK_HW_FEATURES, 5178 .required_clks = MT7988_CLKS_BITMAP, 5179 .required_pctl = false, 5180 .version = 3, 5181 .offload_version = 2, 5182 .hash_offset = 4, 5183 .has_accounting = true, 5184 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, 5185 .txrx = { 5186 .txd_size = sizeof(struct mtk_tx_dma_v2), 5187 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5188 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5189 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5190 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5191 .dma_len_offset = 8, 5192 }, 5193 }; 5194 5195 static const struct mtk_soc_data rt5350_data = { 5196 .reg_map = &mt7628_reg_map, 5197 .caps = MT7628_CAPS, 5198 .hw_features = MTK_HW_FEATURES_MT7628, 5199 .required_clks = MT7628_CLKS_BITMAP, 5200 .required_pctl = false, 5201 .version = 1, 5202 .txrx = { 5203 .txd_size = sizeof(struct mtk_tx_dma), 5204 .rxd_size = sizeof(struct mtk_rx_dma), 5205 .rx_irq_done_mask = MTK_RX_DONE_INT, 5206 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 5207 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5208 .dma_len_offset = 16, 5209 }, 5210 }; 5211 5212 const struct of_device_id of_mtk_match[] = { 5213 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, 5214 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, 5215 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, 5216 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, 5217 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, 5218 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, 5219 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, 5220 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, 5221 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, 5222 {}, 5223 }; 5224 MODULE_DEVICE_TABLE(of, of_mtk_match); 5225 5226 static struct platform_driver mtk_driver = { 5227 .probe = mtk_probe, 5228 .remove_new = mtk_remove, 5229 .driver = { 5230 .name = "mtk_soc_eth", 5231 .of_match_table = of_mtk_match, 5232 }, 5233 }; 5234 5235 module_platform_driver(mtk_driver); 5236 5237 MODULE_LICENSE("GPL"); 5238 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 5239 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 5240