1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #include <linux/of_device.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/regmap.h> 20 #include <linux/clk.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/if_vlan.h> 23 #include <linux/reset.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/pinctrl/devinfo.h> 27 28 #include "mtk_eth_soc.h" 29 30 static int mtk_msg_level = -1; 31 module_param_named(msg_level, mtk_msg_level, int, 0); 32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 33 34 #define MTK_ETHTOOL_STAT(x) { #x, \ 35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 36 37 /* strings used by ethtool */ 38 static const struct mtk_ethtool_stats { 39 char str[ETH_GSTRING_LEN]; 40 u32 offset; 41 } mtk_ethtool_stats[] = { 42 MTK_ETHTOOL_STAT(tx_bytes), 43 MTK_ETHTOOL_STAT(tx_packets), 44 MTK_ETHTOOL_STAT(tx_skip), 45 MTK_ETHTOOL_STAT(tx_collisions), 46 MTK_ETHTOOL_STAT(rx_bytes), 47 MTK_ETHTOOL_STAT(rx_packets), 48 MTK_ETHTOOL_STAT(rx_overflow), 49 MTK_ETHTOOL_STAT(rx_fcs_errors), 50 MTK_ETHTOOL_STAT(rx_short_errors), 51 MTK_ETHTOOL_STAT(rx_long_errors), 52 MTK_ETHTOOL_STAT(rx_checksum_errors), 53 MTK_ETHTOOL_STAT(rx_flow_control_packets), 54 }; 55 56 static const char * const mtk_clks_source_name[] = { 57 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m", 58 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" 59 }; 60 61 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 62 { 63 __raw_writel(val, eth->base + reg); 64 } 65 66 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 67 { 68 return __raw_readl(eth->base + reg); 69 } 70 71 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 72 { 73 unsigned long t_start = jiffies; 74 75 while (1) { 76 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 77 return 0; 78 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 79 break; 80 usleep_range(10, 20); 81 } 82 83 dev_err(eth->dev, "mdio: MDIO timeout\n"); 84 return -1; 85 } 86 87 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 88 u32 phy_register, u32 write_data) 89 { 90 if (mtk_mdio_busy_wait(eth)) 91 return -1; 92 93 write_data &= 0xffff; 94 95 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 96 (phy_register << PHY_IAC_REG_SHIFT) | 97 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 98 MTK_PHY_IAC); 99 100 if (mtk_mdio_busy_wait(eth)) 101 return -1; 102 103 return 0; 104 } 105 106 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 107 { 108 u32 d; 109 110 if (mtk_mdio_busy_wait(eth)) 111 return 0xffff; 112 113 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 114 (phy_reg << PHY_IAC_REG_SHIFT) | 115 (phy_addr << PHY_IAC_ADDR_SHIFT), 116 MTK_PHY_IAC); 117 118 if (mtk_mdio_busy_wait(eth)) 119 return 0xffff; 120 121 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 122 123 return d; 124 } 125 126 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 127 int phy_reg, u16 val) 128 { 129 struct mtk_eth *eth = bus->priv; 130 131 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 132 } 133 134 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 135 { 136 struct mtk_eth *eth = bus->priv; 137 138 return _mtk_mdio_read(eth, phy_addr, phy_reg); 139 } 140 141 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 142 { 143 u32 val; 144 int ret; 145 146 val = (speed == SPEED_1000) ? 147 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 148 mtk_w32(eth, val, INTF_MODE); 149 150 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 151 ETHSYS_TRGMII_CLK_SEL362_5, 152 ETHSYS_TRGMII_CLK_SEL362_5); 153 154 val = (speed == SPEED_1000) ? 250000000 : 500000000; 155 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 156 if (ret) 157 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 158 159 val = (speed == SPEED_1000) ? 160 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 161 mtk_w32(eth, val, TRGMII_RCK_CTRL); 162 163 val = (speed == SPEED_1000) ? 164 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 165 mtk_w32(eth, val, TRGMII_TCK_CTRL); 166 } 167 168 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id) 169 { 170 u32 val; 171 172 /* Setup the link timer and QPHY power up inside SGMIISYS */ 173 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER, 174 SGMII_LINK_TIMER_DEFAULT); 175 176 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val); 177 val |= SGMII_REMOTE_FAULT_DIS; 178 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val); 179 180 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val); 181 val |= SGMII_AN_RESTART; 182 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val); 183 184 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val); 185 val &= ~SGMII_PHYA_PWD; 186 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val); 187 188 /* Determine MUX for which GMAC uses the SGMII interface */ 189 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) { 190 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 191 val &= ~SYSCFG0_SGMII_MASK; 192 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2; 193 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 194 195 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n", 196 mac_id); 197 } 198 199 /* Setup the GMAC1 going through SGMII path when SoC also support 200 * ESW on GMAC1 201 */ 202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) && 203 !mac_id) { 204 mtk_w32(eth, 0, MTK_MAC_MISC); 205 dev_info(eth->dev, "setup gmac1 going through sgmii"); 206 } 207 } 208 209 static void mtk_phy_link_adjust(struct net_device *dev) 210 { 211 struct mtk_mac *mac = netdev_priv(dev); 212 u16 lcl_adv = 0, rmt_adv = 0; 213 u8 flowctrl; 214 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 215 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 216 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 217 MAC_MCR_BACKPR_EN; 218 219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 220 return; 221 222 switch (dev->phydev->speed) { 223 case SPEED_1000: 224 mcr |= MAC_MCR_SPEED_1000; 225 break; 226 case SPEED_100: 227 mcr |= MAC_MCR_SPEED_100; 228 break; 229 } 230 231 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 232 !mac->id && !mac->trgmii) 233 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); 234 235 if (dev->phydev->link) 236 mcr |= MAC_MCR_FORCE_LINK; 237 238 if (dev->phydev->duplex) { 239 mcr |= MAC_MCR_FORCE_DPX; 240 241 if (dev->phydev->pause) 242 rmt_adv = LPA_PAUSE_CAP; 243 if (dev->phydev->asym_pause) 244 rmt_adv |= LPA_PAUSE_ASYM; 245 246 lcl_adv = linkmode_adv_to_lcl_adv_t(dev->phydev->advertising); 247 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 248 249 if (flowctrl & FLOW_CTRL_TX) 250 mcr |= MAC_MCR_FORCE_TX_FC; 251 if (flowctrl & FLOW_CTRL_RX) 252 mcr |= MAC_MCR_FORCE_RX_FC; 253 254 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 255 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 256 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 257 } 258 259 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 260 261 if (!of_phy_is_fixed_link(mac->of_node)) 262 phy_print_status(dev->phydev); 263 } 264 265 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 266 struct device_node *phy_node) 267 { 268 struct phy_device *phydev; 269 int phy_mode; 270 271 phy_mode = of_get_phy_mode(phy_node); 272 if (phy_mode < 0) { 273 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 274 return -EINVAL; 275 } 276 277 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 278 mtk_phy_link_adjust, 0, phy_mode); 279 if (!phydev) { 280 dev_err(eth->dev, "could not connect to PHY\n"); 281 return -ENODEV; 282 } 283 284 dev_info(eth->dev, 285 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 286 mac->id, phydev_name(phydev), phydev->phy_id, 287 phydev->drv->name); 288 289 return 0; 290 } 291 292 static int mtk_phy_connect(struct net_device *dev) 293 { 294 struct mtk_mac *mac = netdev_priv(dev); 295 struct mtk_eth *eth; 296 struct device_node *np; 297 u32 val; 298 299 eth = mac->hw; 300 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 301 if (!np && of_phy_is_fixed_link(mac->of_node)) 302 if (!of_phy_register_fixed_link(mac->of_node)) 303 np = of_node_get(mac->of_node); 304 if (!np) 305 return -ENODEV; 306 307 mac->ge_mode = 0; 308 switch (of_get_phy_mode(np)) { 309 case PHY_INTERFACE_MODE_TRGMII: 310 mac->trgmii = true; 311 case PHY_INTERFACE_MODE_RGMII_TXID: 312 case PHY_INTERFACE_MODE_RGMII_RXID: 313 case PHY_INTERFACE_MODE_RGMII_ID: 314 case PHY_INTERFACE_MODE_RGMII: 315 break; 316 case PHY_INTERFACE_MODE_SGMII: 317 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) 318 mtk_gmac_sgmii_hw_setup(eth, mac->id); 319 break; 320 case PHY_INTERFACE_MODE_MII: 321 mac->ge_mode = 1; 322 break; 323 case PHY_INTERFACE_MODE_REVMII: 324 mac->ge_mode = 2; 325 break; 326 case PHY_INTERFACE_MODE_RMII: 327 if (!mac->id) 328 goto err_phy; 329 mac->ge_mode = 3; 330 break; 331 default: 332 goto err_phy; 333 } 334 335 /* put the gmac into the right mode */ 336 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 337 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 338 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); 339 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 340 341 /* couple phydev to net_device */ 342 if (mtk_phy_connect_node(eth, mac, np)) 343 goto err_phy; 344 345 of_node_put(np); 346 347 return 0; 348 349 err_phy: 350 if (of_phy_is_fixed_link(mac->of_node)) 351 of_phy_deregister_fixed_link(mac->of_node); 352 of_node_put(np); 353 dev_err(eth->dev, "%s: invalid phy\n", __func__); 354 return -EINVAL; 355 } 356 357 static int mtk_mdio_init(struct mtk_eth *eth) 358 { 359 struct device_node *mii_np; 360 int ret; 361 362 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 363 if (!mii_np) { 364 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 365 return -ENODEV; 366 } 367 368 if (!of_device_is_available(mii_np)) { 369 ret = -ENODEV; 370 goto err_put_node; 371 } 372 373 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 374 if (!eth->mii_bus) { 375 ret = -ENOMEM; 376 goto err_put_node; 377 } 378 379 eth->mii_bus->name = "mdio"; 380 eth->mii_bus->read = mtk_mdio_read; 381 eth->mii_bus->write = mtk_mdio_write; 382 eth->mii_bus->priv = eth; 383 eth->mii_bus->parent = eth->dev; 384 385 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 386 ret = of_mdiobus_register(eth->mii_bus, mii_np); 387 388 err_put_node: 389 of_node_put(mii_np); 390 return ret; 391 } 392 393 static void mtk_mdio_cleanup(struct mtk_eth *eth) 394 { 395 if (!eth->mii_bus) 396 return; 397 398 mdiobus_unregister(eth->mii_bus); 399 } 400 401 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 402 { 403 unsigned long flags; 404 u32 val; 405 406 spin_lock_irqsave(ð->tx_irq_lock, flags); 407 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 408 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 409 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 410 } 411 412 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 413 { 414 unsigned long flags; 415 u32 val; 416 417 spin_lock_irqsave(ð->tx_irq_lock, flags); 418 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 419 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 420 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 421 } 422 423 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 424 { 425 unsigned long flags; 426 u32 val; 427 428 spin_lock_irqsave(ð->rx_irq_lock, flags); 429 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 430 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 431 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 432 } 433 434 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 435 { 436 unsigned long flags; 437 u32 val; 438 439 spin_lock_irqsave(ð->rx_irq_lock, flags); 440 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 441 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 442 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 443 } 444 445 static int mtk_set_mac_address(struct net_device *dev, void *p) 446 { 447 int ret = eth_mac_addr(dev, p); 448 struct mtk_mac *mac = netdev_priv(dev); 449 const char *macaddr = dev->dev_addr; 450 451 if (ret) 452 return ret; 453 454 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 455 return -EBUSY; 456 457 spin_lock_bh(&mac->hw->page_lock); 458 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 459 MTK_GDMA_MAC_ADRH(mac->id)); 460 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 461 (macaddr[4] << 8) | macaddr[5], 462 MTK_GDMA_MAC_ADRL(mac->id)); 463 spin_unlock_bh(&mac->hw->page_lock); 464 465 return 0; 466 } 467 468 void mtk_stats_update_mac(struct mtk_mac *mac) 469 { 470 struct mtk_hw_stats *hw_stats = mac->hw_stats; 471 unsigned int base = MTK_GDM1_TX_GBCNT; 472 u64 stats; 473 474 base += hw_stats->reg_offset; 475 476 u64_stats_update_begin(&hw_stats->syncp); 477 478 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 479 stats = mtk_r32(mac->hw, base + 0x04); 480 if (stats) 481 hw_stats->rx_bytes += (stats << 32); 482 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 483 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 484 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 485 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 486 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 487 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 488 hw_stats->rx_flow_control_packets += 489 mtk_r32(mac->hw, base + 0x24); 490 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 491 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 492 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 493 stats = mtk_r32(mac->hw, base + 0x34); 494 if (stats) 495 hw_stats->tx_bytes += (stats << 32); 496 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 497 u64_stats_update_end(&hw_stats->syncp); 498 } 499 500 static void mtk_stats_update(struct mtk_eth *eth) 501 { 502 int i; 503 504 for (i = 0; i < MTK_MAC_COUNT; i++) { 505 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 506 continue; 507 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 508 mtk_stats_update_mac(eth->mac[i]); 509 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 510 } 511 } 512 } 513 514 static void mtk_get_stats64(struct net_device *dev, 515 struct rtnl_link_stats64 *storage) 516 { 517 struct mtk_mac *mac = netdev_priv(dev); 518 struct mtk_hw_stats *hw_stats = mac->hw_stats; 519 unsigned int start; 520 521 if (netif_running(dev) && netif_device_present(dev)) { 522 if (spin_trylock_bh(&hw_stats->stats_lock)) { 523 mtk_stats_update_mac(mac); 524 spin_unlock_bh(&hw_stats->stats_lock); 525 } 526 } 527 528 do { 529 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 530 storage->rx_packets = hw_stats->rx_packets; 531 storage->tx_packets = hw_stats->tx_packets; 532 storage->rx_bytes = hw_stats->rx_bytes; 533 storage->tx_bytes = hw_stats->tx_bytes; 534 storage->collisions = hw_stats->tx_collisions; 535 storage->rx_length_errors = hw_stats->rx_short_errors + 536 hw_stats->rx_long_errors; 537 storage->rx_over_errors = hw_stats->rx_overflow; 538 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 539 storage->rx_errors = hw_stats->rx_checksum_errors; 540 storage->tx_aborted_errors = hw_stats->tx_skip; 541 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 542 543 storage->tx_errors = dev->stats.tx_errors; 544 storage->rx_dropped = dev->stats.rx_dropped; 545 storage->tx_dropped = dev->stats.tx_dropped; 546 } 547 548 static inline int mtk_max_frag_size(int mtu) 549 { 550 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 551 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 552 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 553 554 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 555 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 556 } 557 558 static inline int mtk_max_buf_size(int frag_size) 559 { 560 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 561 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 562 563 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 564 565 return buf_size; 566 } 567 568 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 569 struct mtk_rx_dma *dma_rxd) 570 { 571 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 572 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 573 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 574 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 575 } 576 577 /* the qdma core needs scratch memory to be setup */ 578 static int mtk_init_fq_dma(struct mtk_eth *eth) 579 { 580 dma_addr_t phy_ring_tail; 581 int cnt = MTK_DMA_SIZE; 582 dma_addr_t dma_addr; 583 int i; 584 585 eth->scratch_ring = dma_alloc_coherent(eth->dev, 586 cnt * sizeof(struct mtk_tx_dma), 587 ð->phy_scratch_ring, 588 GFP_ATOMIC); 589 if (unlikely(!eth->scratch_ring)) 590 return -ENOMEM; 591 592 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 593 GFP_KERNEL); 594 if (unlikely(!eth->scratch_head)) 595 return -ENOMEM; 596 597 dma_addr = dma_map_single(eth->dev, 598 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 599 DMA_FROM_DEVICE); 600 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 601 return -ENOMEM; 602 603 phy_ring_tail = eth->phy_scratch_ring + 604 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 605 606 for (i = 0; i < cnt; i++) { 607 eth->scratch_ring[i].txd1 = 608 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 609 if (i < cnt - 1) 610 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 611 ((i + 1) * sizeof(struct mtk_tx_dma))); 612 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 613 } 614 615 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 616 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 617 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 618 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 619 620 return 0; 621 } 622 623 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 624 { 625 void *ret = ring->dma; 626 627 return ret + (desc - ring->phys); 628 } 629 630 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 631 struct mtk_tx_dma *txd) 632 { 633 int idx = txd - ring->dma; 634 635 return &ring->buf[idx]; 636 } 637 638 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 639 { 640 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 641 dma_unmap_single(eth->dev, 642 dma_unmap_addr(tx_buf, dma_addr0), 643 dma_unmap_len(tx_buf, dma_len0), 644 DMA_TO_DEVICE); 645 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 646 dma_unmap_page(eth->dev, 647 dma_unmap_addr(tx_buf, dma_addr0), 648 dma_unmap_len(tx_buf, dma_len0), 649 DMA_TO_DEVICE); 650 } 651 tx_buf->flags = 0; 652 if (tx_buf->skb && 653 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 654 dev_kfree_skb_any(tx_buf->skb); 655 tx_buf->skb = NULL; 656 } 657 658 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 659 int tx_num, struct mtk_tx_ring *ring, bool gso) 660 { 661 struct mtk_mac *mac = netdev_priv(dev); 662 struct mtk_eth *eth = mac->hw; 663 struct mtk_tx_dma *itxd, *txd; 664 struct mtk_tx_buf *itx_buf, *tx_buf; 665 dma_addr_t mapped_addr; 666 unsigned int nr_frags; 667 int i, n_desc = 1; 668 u32 txd4 = 0, fport; 669 670 itxd = ring->next_free; 671 if (itxd == ring->last_free) 672 return -ENOMEM; 673 674 /* set the forward port */ 675 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 676 txd4 |= fport; 677 678 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 679 memset(itx_buf, 0, sizeof(*itx_buf)); 680 681 if (gso) 682 txd4 |= TX_DMA_TSO; 683 684 /* TX Checksum offload */ 685 if (skb->ip_summed == CHECKSUM_PARTIAL) 686 txd4 |= TX_DMA_CHKSUM; 687 688 /* VLAN header offload */ 689 if (skb_vlan_tag_present(skb)) 690 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 691 692 mapped_addr = dma_map_single(eth->dev, skb->data, 693 skb_headlen(skb), DMA_TO_DEVICE); 694 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 695 return -ENOMEM; 696 697 WRITE_ONCE(itxd->txd1, mapped_addr); 698 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 699 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 700 MTK_TX_FLAGS_FPORT1; 701 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr); 702 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb)); 703 704 /* TX SG offload */ 705 txd = itxd; 706 nr_frags = skb_shinfo(skb)->nr_frags; 707 for (i = 0; i < nr_frags; i++) { 708 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 709 unsigned int offset = 0; 710 int frag_size = skb_frag_size(frag); 711 712 while (frag_size) { 713 bool last_frag = false; 714 unsigned int frag_map_size; 715 716 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 717 if (txd == ring->last_free) 718 goto err_dma; 719 720 n_desc++; 721 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 722 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 723 frag_map_size, 724 DMA_TO_DEVICE); 725 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 726 goto err_dma; 727 728 if (i == nr_frags - 1 && 729 (frag_size - frag_map_size) == 0) 730 last_frag = true; 731 732 WRITE_ONCE(txd->txd1, mapped_addr); 733 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 734 TX_DMA_PLEN0(frag_map_size) | 735 last_frag * TX_DMA_LS0)); 736 WRITE_ONCE(txd->txd4, fport); 737 738 tx_buf = mtk_desc_to_tx_buf(ring, txd); 739 memset(tx_buf, 0, sizeof(*tx_buf)); 740 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 741 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 742 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 743 MTK_TX_FLAGS_FPORT1; 744 745 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 746 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 747 frag_size -= frag_map_size; 748 offset += frag_map_size; 749 } 750 } 751 752 /* store skb to cleanup */ 753 itx_buf->skb = skb; 754 755 WRITE_ONCE(itxd->txd4, txd4); 756 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 757 (!nr_frags * TX_DMA_LS0))); 758 759 netdev_sent_queue(dev, skb->len); 760 skb_tx_timestamp(skb); 761 762 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 763 atomic_sub(n_desc, &ring->free_count); 764 765 /* make sure that all changes to the dma ring are flushed before we 766 * continue 767 */ 768 wmb(); 769 770 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 771 !netdev_xmit_more()) 772 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 773 774 return 0; 775 776 err_dma: 777 do { 778 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 779 780 /* unmap dma */ 781 mtk_tx_unmap(eth, tx_buf); 782 783 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 784 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 785 } while (itxd != txd); 786 787 return -ENOMEM; 788 } 789 790 static inline int mtk_cal_txd_req(struct sk_buff *skb) 791 { 792 int i, nfrags; 793 struct skb_frag_struct *frag; 794 795 nfrags = 1; 796 if (skb_is_gso(skb)) { 797 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 798 frag = &skb_shinfo(skb)->frags[i]; 799 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 800 } 801 } else { 802 nfrags += skb_shinfo(skb)->nr_frags; 803 } 804 805 return nfrags; 806 } 807 808 static int mtk_queue_stopped(struct mtk_eth *eth) 809 { 810 int i; 811 812 for (i = 0; i < MTK_MAC_COUNT; i++) { 813 if (!eth->netdev[i]) 814 continue; 815 if (netif_queue_stopped(eth->netdev[i])) 816 return 1; 817 } 818 819 return 0; 820 } 821 822 static void mtk_wake_queue(struct mtk_eth *eth) 823 { 824 int i; 825 826 for (i = 0; i < MTK_MAC_COUNT; i++) { 827 if (!eth->netdev[i]) 828 continue; 829 netif_wake_queue(eth->netdev[i]); 830 } 831 } 832 833 static void mtk_stop_queue(struct mtk_eth *eth) 834 { 835 int i; 836 837 for (i = 0; i < MTK_MAC_COUNT; i++) { 838 if (!eth->netdev[i]) 839 continue; 840 netif_stop_queue(eth->netdev[i]); 841 } 842 } 843 844 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 845 { 846 struct mtk_mac *mac = netdev_priv(dev); 847 struct mtk_eth *eth = mac->hw; 848 struct mtk_tx_ring *ring = ð->tx_ring; 849 struct net_device_stats *stats = &dev->stats; 850 bool gso = false; 851 int tx_num; 852 853 /* normally we can rely on the stack not calling this more than once, 854 * however we have 2 queues running on the same ring so we need to lock 855 * the ring access 856 */ 857 spin_lock(ð->page_lock); 858 859 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 860 goto drop; 861 862 tx_num = mtk_cal_txd_req(skb); 863 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 864 mtk_stop_queue(eth); 865 netif_err(eth, tx_queued, dev, 866 "Tx Ring full when queue awake!\n"); 867 spin_unlock(ð->page_lock); 868 return NETDEV_TX_BUSY; 869 } 870 871 /* TSO: fill MSS info in tcp checksum field */ 872 if (skb_is_gso(skb)) { 873 if (skb_cow_head(skb, 0)) { 874 netif_warn(eth, tx_err, dev, 875 "GSO expand head fail.\n"); 876 goto drop; 877 } 878 879 if (skb_shinfo(skb)->gso_type & 880 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 881 gso = true; 882 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 883 } 884 } 885 886 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 887 goto drop; 888 889 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 890 mtk_stop_queue(eth); 891 892 spin_unlock(ð->page_lock); 893 894 return NETDEV_TX_OK; 895 896 drop: 897 spin_unlock(ð->page_lock); 898 stats->tx_dropped++; 899 dev_kfree_skb_any(skb); 900 return NETDEV_TX_OK; 901 } 902 903 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 904 { 905 int i; 906 struct mtk_rx_ring *ring; 907 int idx; 908 909 if (!eth->hwlro) 910 return ð->rx_ring[0]; 911 912 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 913 ring = ð->rx_ring[i]; 914 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 915 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 916 ring->calc_idx_update = true; 917 return ring; 918 } 919 } 920 921 return NULL; 922 } 923 924 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 925 { 926 struct mtk_rx_ring *ring; 927 int i; 928 929 if (!eth->hwlro) { 930 ring = ð->rx_ring[0]; 931 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 932 } else { 933 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 934 ring = ð->rx_ring[i]; 935 if (ring->calc_idx_update) { 936 ring->calc_idx_update = false; 937 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 938 } 939 } 940 } 941 } 942 943 static int mtk_poll_rx(struct napi_struct *napi, int budget, 944 struct mtk_eth *eth) 945 { 946 struct mtk_rx_ring *ring; 947 int idx; 948 struct sk_buff *skb; 949 u8 *data, *new_data; 950 struct mtk_rx_dma *rxd, trxd; 951 int done = 0; 952 953 while (done < budget) { 954 struct net_device *netdev; 955 unsigned int pktlen; 956 dma_addr_t dma_addr; 957 int mac = 0; 958 959 ring = mtk_get_rx_ring(eth); 960 if (unlikely(!ring)) 961 goto rx_done; 962 963 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 964 rxd = &ring->dma[idx]; 965 data = ring->data[idx]; 966 967 mtk_rx_get_desc(&trxd, rxd); 968 if (!(trxd.rxd2 & RX_DMA_DONE)) 969 break; 970 971 /* find out which mac the packet come from. values start at 1 */ 972 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 973 RX_DMA_FPORT_MASK; 974 mac--; 975 976 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 977 !eth->netdev[mac])) 978 goto release_desc; 979 980 netdev = eth->netdev[mac]; 981 982 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 983 goto release_desc; 984 985 /* alloc new buffer */ 986 new_data = napi_alloc_frag(ring->frag_size); 987 if (unlikely(!new_data)) { 988 netdev->stats.rx_dropped++; 989 goto release_desc; 990 } 991 dma_addr = dma_map_single(eth->dev, 992 new_data + NET_SKB_PAD, 993 ring->buf_size, 994 DMA_FROM_DEVICE); 995 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 996 skb_free_frag(new_data); 997 netdev->stats.rx_dropped++; 998 goto release_desc; 999 } 1000 1001 /* receive data */ 1002 skb = build_skb(data, ring->frag_size); 1003 if (unlikely(!skb)) { 1004 skb_free_frag(new_data); 1005 netdev->stats.rx_dropped++; 1006 goto release_desc; 1007 } 1008 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1009 1010 dma_unmap_single(eth->dev, trxd.rxd1, 1011 ring->buf_size, DMA_FROM_DEVICE); 1012 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1013 skb->dev = netdev; 1014 skb_put(skb, pktlen); 1015 if (trxd.rxd4 & RX_DMA_L4_VALID) 1016 skb->ip_summed = CHECKSUM_UNNECESSARY; 1017 else 1018 skb_checksum_none_assert(skb); 1019 skb->protocol = eth_type_trans(skb, netdev); 1020 1021 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1022 RX_DMA_VID(trxd.rxd3)) 1023 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1024 RX_DMA_VID(trxd.rxd3)); 1025 skb_record_rx_queue(skb, 0); 1026 napi_gro_receive(napi, skb); 1027 1028 ring->data[idx] = new_data; 1029 rxd->rxd1 = (unsigned int)dma_addr; 1030 1031 release_desc: 1032 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1033 1034 ring->calc_idx = idx; 1035 1036 done++; 1037 } 1038 1039 rx_done: 1040 if (done) { 1041 /* make sure that all changes to the dma ring are flushed before 1042 * we continue 1043 */ 1044 wmb(); 1045 mtk_update_rx_cpu_idx(eth); 1046 } 1047 1048 return done; 1049 } 1050 1051 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1052 { 1053 struct mtk_tx_ring *ring = ð->tx_ring; 1054 struct mtk_tx_dma *desc; 1055 struct sk_buff *skb; 1056 struct mtk_tx_buf *tx_buf; 1057 unsigned int done[MTK_MAX_DEVS]; 1058 unsigned int bytes[MTK_MAX_DEVS]; 1059 u32 cpu, dma; 1060 int total = 0, i; 1061 1062 memset(done, 0, sizeof(done)); 1063 memset(bytes, 0, sizeof(bytes)); 1064 1065 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1066 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1067 1068 desc = mtk_qdma_phys_to_virt(ring, cpu); 1069 1070 while ((cpu != dma) && budget) { 1071 u32 next_cpu = desc->txd2; 1072 int mac = 0; 1073 1074 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1075 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1076 break; 1077 1078 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1079 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1080 mac = 1; 1081 1082 skb = tx_buf->skb; 1083 if (!skb) 1084 break; 1085 1086 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1087 bytes[mac] += skb->len; 1088 done[mac]++; 1089 budget--; 1090 } 1091 mtk_tx_unmap(eth, tx_buf); 1092 1093 ring->last_free = desc; 1094 atomic_inc(&ring->free_count); 1095 1096 cpu = next_cpu; 1097 } 1098 1099 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1100 1101 for (i = 0; i < MTK_MAC_COUNT; i++) { 1102 if (!eth->netdev[i] || !done[i]) 1103 continue; 1104 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1105 total += done[i]; 1106 } 1107 1108 if (mtk_queue_stopped(eth) && 1109 (atomic_read(&ring->free_count) > ring->thresh)) 1110 mtk_wake_queue(eth); 1111 1112 return total; 1113 } 1114 1115 static void mtk_handle_status_irq(struct mtk_eth *eth) 1116 { 1117 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1118 1119 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1120 mtk_stats_update(eth); 1121 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1122 MTK_INT_STATUS2); 1123 } 1124 } 1125 1126 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1127 { 1128 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1129 u32 status, mask; 1130 int tx_done = 0; 1131 1132 mtk_handle_status_irq(eth); 1133 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 1134 tx_done = mtk_poll_tx(eth, budget); 1135 1136 if (unlikely(netif_msg_intr(eth))) { 1137 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1138 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1139 dev_info(eth->dev, 1140 "done tx %d, intr 0x%08x/0x%x\n", 1141 tx_done, status, mask); 1142 } 1143 1144 if (tx_done == budget) 1145 return budget; 1146 1147 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1148 if (status & MTK_TX_DONE_INT) 1149 return budget; 1150 1151 napi_complete(napi); 1152 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1153 1154 return tx_done; 1155 } 1156 1157 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1158 { 1159 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1160 u32 status, mask; 1161 int rx_done = 0; 1162 int remain_budget = budget; 1163 1164 mtk_handle_status_irq(eth); 1165 1166 poll_again: 1167 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1168 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1169 1170 if (unlikely(netif_msg_intr(eth))) { 1171 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1172 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1173 dev_info(eth->dev, 1174 "done rx %d, intr 0x%08x/0x%x\n", 1175 rx_done, status, mask); 1176 } 1177 if (rx_done == remain_budget) 1178 return budget; 1179 1180 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1181 if (status & MTK_RX_DONE_INT) { 1182 remain_budget -= rx_done; 1183 goto poll_again; 1184 } 1185 napi_complete(napi); 1186 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1187 1188 return rx_done + budget - remain_budget; 1189 } 1190 1191 static int mtk_tx_alloc(struct mtk_eth *eth) 1192 { 1193 struct mtk_tx_ring *ring = ð->tx_ring; 1194 int i, sz = sizeof(*ring->dma); 1195 1196 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1197 GFP_KERNEL); 1198 if (!ring->buf) 1199 goto no_tx_mem; 1200 1201 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1202 &ring->phys, GFP_ATOMIC); 1203 if (!ring->dma) 1204 goto no_tx_mem; 1205 1206 for (i = 0; i < MTK_DMA_SIZE; i++) { 1207 int next = (i + 1) % MTK_DMA_SIZE; 1208 u32 next_ptr = ring->phys + next * sz; 1209 1210 ring->dma[i].txd2 = next_ptr; 1211 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1212 } 1213 1214 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1215 ring->next_free = &ring->dma[0]; 1216 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1217 ring->thresh = MAX_SKB_FRAGS; 1218 1219 /* make sure that all changes to the dma ring are flushed before we 1220 * continue 1221 */ 1222 wmb(); 1223 1224 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1225 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1226 mtk_w32(eth, 1227 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1228 MTK_QTX_CRX_PTR); 1229 mtk_w32(eth, 1230 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1231 MTK_QTX_DRX_PTR); 1232 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1233 1234 return 0; 1235 1236 no_tx_mem: 1237 return -ENOMEM; 1238 } 1239 1240 static void mtk_tx_clean(struct mtk_eth *eth) 1241 { 1242 struct mtk_tx_ring *ring = ð->tx_ring; 1243 int i; 1244 1245 if (ring->buf) { 1246 for (i = 0; i < MTK_DMA_SIZE; i++) 1247 mtk_tx_unmap(eth, &ring->buf[i]); 1248 kfree(ring->buf); 1249 ring->buf = NULL; 1250 } 1251 1252 if (ring->dma) { 1253 dma_free_coherent(eth->dev, 1254 MTK_DMA_SIZE * sizeof(*ring->dma), 1255 ring->dma, 1256 ring->phys); 1257 ring->dma = NULL; 1258 } 1259 } 1260 1261 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1262 { 1263 struct mtk_rx_ring *ring; 1264 int rx_data_len, rx_dma_size; 1265 int i; 1266 u32 offset = 0; 1267 1268 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1269 if (ring_no) 1270 return -EINVAL; 1271 ring = ð->rx_ring_qdma; 1272 offset = 0x1000; 1273 } else { 1274 ring = ð->rx_ring[ring_no]; 1275 } 1276 1277 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1278 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1279 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1280 } else { 1281 rx_data_len = ETH_DATA_LEN; 1282 rx_dma_size = MTK_DMA_SIZE; 1283 } 1284 1285 ring->frag_size = mtk_max_frag_size(rx_data_len); 1286 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1287 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1288 GFP_KERNEL); 1289 if (!ring->data) 1290 return -ENOMEM; 1291 1292 for (i = 0; i < rx_dma_size; i++) { 1293 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1294 if (!ring->data[i]) 1295 return -ENOMEM; 1296 } 1297 1298 ring->dma = dma_alloc_coherent(eth->dev, 1299 rx_dma_size * sizeof(*ring->dma), 1300 &ring->phys, GFP_ATOMIC); 1301 if (!ring->dma) 1302 return -ENOMEM; 1303 1304 for (i = 0; i < rx_dma_size; i++) { 1305 dma_addr_t dma_addr = dma_map_single(eth->dev, 1306 ring->data[i] + NET_SKB_PAD, 1307 ring->buf_size, 1308 DMA_FROM_DEVICE); 1309 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1310 return -ENOMEM; 1311 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1312 1313 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1314 } 1315 ring->dma_size = rx_dma_size; 1316 ring->calc_idx_update = false; 1317 ring->calc_idx = rx_dma_size - 1; 1318 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1319 /* make sure that all changes to the dma ring are flushed before we 1320 * continue 1321 */ 1322 wmb(); 1323 1324 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1325 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1326 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1327 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1328 1329 return 0; 1330 } 1331 1332 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1333 { 1334 int i; 1335 1336 if (ring->data && ring->dma) { 1337 for (i = 0; i < ring->dma_size; i++) { 1338 if (!ring->data[i]) 1339 continue; 1340 if (!ring->dma[i].rxd1) 1341 continue; 1342 dma_unmap_single(eth->dev, 1343 ring->dma[i].rxd1, 1344 ring->buf_size, 1345 DMA_FROM_DEVICE); 1346 skb_free_frag(ring->data[i]); 1347 } 1348 kfree(ring->data); 1349 ring->data = NULL; 1350 } 1351 1352 if (ring->dma) { 1353 dma_free_coherent(eth->dev, 1354 ring->dma_size * sizeof(*ring->dma), 1355 ring->dma, 1356 ring->phys); 1357 ring->dma = NULL; 1358 } 1359 } 1360 1361 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1362 { 1363 int i; 1364 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1365 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1366 1367 /* set LRO rings to auto-learn modes */ 1368 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1369 1370 /* validate LRO ring */ 1371 ring_ctrl_dw2 |= MTK_RING_VLD; 1372 1373 /* set AGE timer (unit: 20us) */ 1374 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1375 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1376 1377 /* set max AGG timer (unit: 20us) */ 1378 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1379 1380 /* set max LRO AGG count */ 1381 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1382 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1383 1384 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1385 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1386 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1387 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1388 } 1389 1390 /* IPv4 checksum update enable */ 1391 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1392 1393 /* switch priority comparison to packet count mode */ 1394 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1395 1396 /* bandwidth threshold setting */ 1397 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1398 1399 /* auto-learn score delta setting */ 1400 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1401 1402 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1403 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1404 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1405 1406 /* set HW LRO mode & the max aggregation count for rx packets */ 1407 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1408 1409 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1410 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1411 1412 /* enable HW LRO */ 1413 lro_ctrl_dw0 |= MTK_LRO_EN; 1414 1415 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1416 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1417 1418 return 0; 1419 } 1420 1421 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1422 { 1423 int i; 1424 u32 val; 1425 1426 /* relinquish lro rings, flush aggregated packets */ 1427 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1428 1429 /* wait for relinquishments done */ 1430 for (i = 0; i < 10; i++) { 1431 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1432 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1433 msleep(20); 1434 continue; 1435 } 1436 break; 1437 } 1438 1439 /* invalidate lro rings */ 1440 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1441 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1442 1443 /* disable HW LRO */ 1444 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1445 } 1446 1447 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1448 { 1449 u32 reg_val; 1450 1451 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1452 1453 /* invalidate the IP setting */ 1454 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1455 1456 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1457 1458 /* validate the IP setting */ 1459 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1460 } 1461 1462 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1463 { 1464 u32 reg_val; 1465 1466 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1467 1468 /* invalidate the IP setting */ 1469 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1470 1471 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1472 } 1473 1474 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1475 { 1476 int cnt = 0; 1477 int i; 1478 1479 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1480 if (mac->hwlro_ip[i]) 1481 cnt++; 1482 } 1483 1484 return cnt; 1485 } 1486 1487 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1488 struct ethtool_rxnfc *cmd) 1489 { 1490 struct ethtool_rx_flow_spec *fsp = 1491 (struct ethtool_rx_flow_spec *)&cmd->fs; 1492 struct mtk_mac *mac = netdev_priv(dev); 1493 struct mtk_eth *eth = mac->hw; 1494 int hwlro_idx; 1495 1496 if ((fsp->flow_type != TCP_V4_FLOW) || 1497 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1498 (fsp->location > 1)) 1499 return -EINVAL; 1500 1501 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1502 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1503 1504 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1505 1506 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1507 1508 return 0; 1509 } 1510 1511 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1512 struct ethtool_rxnfc *cmd) 1513 { 1514 struct ethtool_rx_flow_spec *fsp = 1515 (struct ethtool_rx_flow_spec *)&cmd->fs; 1516 struct mtk_mac *mac = netdev_priv(dev); 1517 struct mtk_eth *eth = mac->hw; 1518 int hwlro_idx; 1519 1520 if (fsp->location > 1) 1521 return -EINVAL; 1522 1523 mac->hwlro_ip[fsp->location] = 0; 1524 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1525 1526 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1527 1528 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1529 1530 return 0; 1531 } 1532 1533 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1534 { 1535 struct mtk_mac *mac = netdev_priv(dev); 1536 struct mtk_eth *eth = mac->hw; 1537 int i, hwlro_idx; 1538 1539 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1540 mac->hwlro_ip[i] = 0; 1541 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1542 1543 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1544 } 1545 1546 mac->hwlro_ip_cnt = 0; 1547 } 1548 1549 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1550 struct ethtool_rxnfc *cmd) 1551 { 1552 struct mtk_mac *mac = netdev_priv(dev); 1553 struct ethtool_rx_flow_spec *fsp = 1554 (struct ethtool_rx_flow_spec *)&cmd->fs; 1555 1556 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1557 fsp->flow_type = TCP_V4_FLOW; 1558 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1559 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1560 1561 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1562 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1563 fsp->h_u.tcp_ip4_spec.psrc = 0; 1564 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1565 fsp->h_u.tcp_ip4_spec.pdst = 0; 1566 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1567 fsp->h_u.tcp_ip4_spec.tos = 0; 1568 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1569 1570 return 0; 1571 } 1572 1573 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1574 struct ethtool_rxnfc *cmd, 1575 u32 *rule_locs) 1576 { 1577 struct mtk_mac *mac = netdev_priv(dev); 1578 int cnt = 0; 1579 int i; 1580 1581 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1582 if (mac->hwlro_ip[i]) { 1583 rule_locs[cnt] = i; 1584 cnt++; 1585 } 1586 } 1587 1588 cmd->rule_cnt = cnt; 1589 1590 return 0; 1591 } 1592 1593 static netdev_features_t mtk_fix_features(struct net_device *dev, 1594 netdev_features_t features) 1595 { 1596 if (!(features & NETIF_F_LRO)) { 1597 struct mtk_mac *mac = netdev_priv(dev); 1598 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1599 1600 if (ip_cnt) { 1601 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1602 1603 features |= NETIF_F_LRO; 1604 } 1605 } 1606 1607 return features; 1608 } 1609 1610 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1611 { 1612 int err = 0; 1613 1614 if (!((dev->features ^ features) & NETIF_F_LRO)) 1615 return 0; 1616 1617 if (!(features & NETIF_F_LRO)) 1618 mtk_hwlro_netdev_disable(dev); 1619 1620 return err; 1621 } 1622 1623 /* wait for DMA to finish whatever it is doing before we start using it again */ 1624 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1625 { 1626 unsigned long t_start = jiffies; 1627 1628 while (1) { 1629 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1630 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1631 return 0; 1632 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1633 break; 1634 } 1635 1636 dev_err(eth->dev, "DMA init timeout\n"); 1637 return -1; 1638 } 1639 1640 static int mtk_dma_init(struct mtk_eth *eth) 1641 { 1642 int err; 1643 u32 i; 1644 1645 if (mtk_dma_busy_wait(eth)) 1646 return -EBUSY; 1647 1648 /* QDMA needs scratch memory for internal reordering of the 1649 * descriptors 1650 */ 1651 err = mtk_init_fq_dma(eth); 1652 if (err) 1653 return err; 1654 1655 err = mtk_tx_alloc(eth); 1656 if (err) 1657 return err; 1658 1659 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 1660 if (err) 1661 return err; 1662 1663 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 1664 if (err) 1665 return err; 1666 1667 if (eth->hwlro) { 1668 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1669 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 1670 if (err) 1671 return err; 1672 } 1673 err = mtk_hwlro_rx_init(eth); 1674 if (err) 1675 return err; 1676 } 1677 1678 /* Enable random early drop and set drop threshold automatically */ 1679 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1680 MTK_QDMA_FC_THRES); 1681 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1682 1683 return 0; 1684 } 1685 1686 static void mtk_dma_free(struct mtk_eth *eth) 1687 { 1688 int i; 1689 1690 for (i = 0; i < MTK_MAC_COUNT; i++) 1691 if (eth->netdev[i]) 1692 netdev_reset_queue(eth->netdev[i]); 1693 if (eth->scratch_ring) { 1694 dma_free_coherent(eth->dev, 1695 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1696 eth->scratch_ring, 1697 eth->phy_scratch_ring); 1698 eth->scratch_ring = NULL; 1699 eth->phy_scratch_ring = 0; 1700 } 1701 mtk_tx_clean(eth); 1702 mtk_rx_clean(eth, ð->rx_ring[0]); 1703 mtk_rx_clean(eth, ð->rx_ring_qdma); 1704 1705 if (eth->hwlro) { 1706 mtk_hwlro_rx_uninit(eth); 1707 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1708 mtk_rx_clean(eth, ð->rx_ring[i]); 1709 } 1710 1711 kfree(eth->scratch_head); 1712 } 1713 1714 static void mtk_tx_timeout(struct net_device *dev) 1715 { 1716 struct mtk_mac *mac = netdev_priv(dev); 1717 struct mtk_eth *eth = mac->hw; 1718 1719 eth->netdev[mac->id]->stats.tx_errors++; 1720 netif_err(eth, tx_err, dev, 1721 "transmit timed out\n"); 1722 schedule_work(ð->pending_work); 1723 } 1724 1725 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1726 { 1727 struct mtk_eth *eth = _eth; 1728 1729 if (likely(napi_schedule_prep(ð->rx_napi))) { 1730 __napi_schedule(ð->rx_napi); 1731 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1732 } 1733 1734 return IRQ_HANDLED; 1735 } 1736 1737 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1738 { 1739 struct mtk_eth *eth = _eth; 1740 1741 if (likely(napi_schedule_prep(ð->tx_napi))) { 1742 __napi_schedule(ð->tx_napi); 1743 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1744 } 1745 1746 return IRQ_HANDLED; 1747 } 1748 1749 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 1750 { 1751 struct mtk_eth *eth = _eth; 1752 1753 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 1754 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 1755 mtk_handle_irq_rx(irq, _eth); 1756 } 1757 if (mtk_r32(eth, MTK_QDMA_INT_MASK) & MTK_TX_DONE_INT) { 1758 if (mtk_r32(eth, MTK_QMTK_INT_STATUS) & MTK_TX_DONE_INT) 1759 mtk_handle_irq_tx(irq, _eth); 1760 } 1761 1762 return IRQ_HANDLED; 1763 } 1764 1765 #ifdef CONFIG_NET_POLL_CONTROLLER 1766 static void mtk_poll_controller(struct net_device *dev) 1767 { 1768 struct mtk_mac *mac = netdev_priv(dev); 1769 struct mtk_eth *eth = mac->hw; 1770 1771 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1772 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1773 mtk_handle_irq_rx(eth->irq[2], dev); 1774 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1775 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1776 } 1777 #endif 1778 1779 static int mtk_start_dma(struct mtk_eth *eth) 1780 { 1781 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 1782 int err; 1783 1784 err = mtk_dma_init(eth); 1785 if (err) { 1786 mtk_dma_free(eth); 1787 return err; 1788 } 1789 1790 mtk_w32(eth, 1791 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 1792 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 1793 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1794 MTK_RX_BT_32DWORDS, 1795 MTK_QDMA_GLO_CFG); 1796 1797 mtk_w32(eth, 1798 MTK_RX_DMA_EN | rx_2b_offset | 1799 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 1800 MTK_PDMA_GLO_CFG); 1801 1802 return 0; 1803 } 1804 1805 static int mtk_open(struct net_device *dev) 1806 { 1807 struct mtk_mac *mac = netdev_priv(dev); 1808 struct mtk_eth *eth = mac->hw; 1809 1810 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1811 if (!refcount_read(ð->dma_refcnt)) { 1812 int err = mtk_start_dma(eth); 1813 1814 if (err) 1815 return err; 1816 1817 napi_enable(ð->tx_napi); 1818 napi_enable(ð->rx_napi); 1819 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1820 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1821 refcount_set(ð->dma_refcnt, 1); 1822 } 1823 else 1824 refcount_inc(ð->dma_refcnt); 1825 1826 phy_start(dev->phydev); 1827 netif_start_queue(dev); 1828 1829 return 0; 1830 } 1831 1832 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1833 { 1834 u32 val; 1835 int i; 1836 1837 /* stop the dma engine */ 1838 spin_lock_bh(ð->page_lock); 1839 val = mtk_r32(eth, glo_cfg); 1840 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1841 glo_cfg); 1842 spin_unlock_bh(ð->page_lock); 1843 1844 /* wait for dma stop */ 1845 for (i = 0; i < 10; i++) { 1846 val = mtk_r32(eth, glo_cfg); 1847 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1848 msleep(20); 1849 continue; 1850 } 1851 break; 1852 } 1853 } 1854 1855 static int mtk_stop(struct net_device *dev) 1856 { 1857 struct mtk_mac *mac = netdev_priv(dev); 1858 struct mtk_eth *eth = mac->hw; 1859 1860 netif_tx_disable(dev); 1861 phy_stop(dev->phydev); 1862 1863 /* only shutdown DMA if this is the last user */ 1864 if (!refcount_dec_and_test(ð->dma_refcnt)) 1865 return 0; 1866 1867 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1868 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1869 napi_disable(ð->tx_napi); 1870 napi_disable(ð->rx_napi); 1871 1872 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1873 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 1874 1875 mtk_dma_free(eth); 1876 1877 return 0; 1878 } 1879 1880 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 1881 { 1882 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1883 reset_bits, 1884 reset_bits); 1885 1886 usleep_range(1000, 1100); 1887 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1888 reset_bits, 1889 ~reset_bits); 1890 mdelay(10); 1891 } 1892 1893 static void mtk_clk_disable(struct mtk_eth *eth) 1894 { 1895 int clk; 1896 1897 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 1898 clk_disable_unprepare(eth->clks[clk]); 1899 } 1900 1901 static int mtk_clk_enable(struct mtk_eth *eth) 1902 { 1903 int clk, ret; 1904 1905 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 1906 ret = clk_prepare_enable(eth->clks[clk]); 1907 if (ret) 1908 goto err_disable_clks; 1909 } 1910 1911 return 0; 1912 1913 err_disable_clks: 1914 while (--clk >= 0) 1915 clk_disable_unprepare(eth->clks[clk]); 1916 1917 return ret; 1918 } 1919 1920 static int mtk_hw_init(struct mtk_eth *eth) 1921 { 1922 int i, val, ret; 1923 1924 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 1925 return 0; 1926 1927 pm_runtime_enable(eth->dev); 1928 pm_runtime_get_sync(eth->dev); 1929 1930 ret = mtk_clk_enable(eth); 1931 if (ret) 1932 goto err_disable_pm; 1933 1934 ethsys_reset(eth, RSTCTRL_FE); 1935 ethsys_reset(eth, RSTCTRL_PPE); 1936 1937 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 1938 for (i = 0; i < MTK_MAC_COUNT; i++) { 1939 if (!eth->mac[i]) 1940 continue; 1941 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); 1942 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); 1943 } 1944 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1945 1946 if (eth->pctl) { 1947 /* Set GE2 driving and slew rate */ 1948 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1949 1950 /* set GE2 TDSEL */ 1951 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1952 1953 /* set GE2 TUNE */ 1954 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1955 } 1956 1957 /* Set linkdown as the default for each GMAC. Its own MCR would be set 1958 * up with the more appropriate value when mtk_phy_link_adjust call is 1959 * being invoked. 1960 */ 1961 for (i = 0; i < MTK_MAC_COUNT; i++) 1962 mtk_w32(eth, 0, MTK_MAC_MCR(i)); 1963 1964 /* Indicates CDM to parse the MTK special tag from CPU 1965 * which also is working out for untag packets. 1966 */ 1967 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 1968 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 1969 1970 /* Enable RX VLan Offloading */ 1971 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1972 1973 /* enable interrupt delay for RX */ 1974 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 1975 1976 /* disable delay and normal interrupt */ 1977 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1978 mtk_tx_irq_disable(eth, ~0); 1979 mtk_rx_irq_disable(eth, ~0); 1980 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1981 mtk_w32(eth, 0, MTK_RST_GL); 1982 1983 /* FE int grouping */ 1984 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1985 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1986 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1987 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1988 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1989 1990 for (i = 0; i < 2; i++) { 1991 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1992 1993 /* setup the forward port to send frame to PDMA */ 1994 val &= ~0xffff; 1995 1996 /* Enable RX checksum */ 1997 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1998 1999 /* setup the mac dma */ 2000 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2001 } 2002 2003 return 0; 2004 2005 err_disable_pm: 2006 pm_runtime_put_sync(eth->dev); 2007 pm_runtime_disable(eth->dev); 2008 2009 return ret; 2010 } 2011 2012 static int mtk_hw_deinit(struct mtk_eth *eth) 2013 { 2014 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2015 return 0; 2016 2017 mtk_clk_disable(eth); 2018 2019 pm_runtime_put_sync(eth->dev); 2020 pm_runtime_disable(eth->dev); 2021 2022 return 0; 2023 } 2024 2025 static int __init mtk_init(struct net_device *dev) 2026 { 2027 struct mtk_mac *mac = netdev_priv(dev); 2028 struct mtk_eth *eth = mac->hw; 2029 const char *mac_addr; 2030 2031 mac_addr = of_get_mac_address(mac->of_node); 2032 if (!IS_ERR(mac_addr)) 2033 ether_addr_copy(dev->dev_addr, mac_addr); 2034 2035 /* If the mac address is invalid, use random mac address */ 2036 if (!is_valid_ether_addr(dev->dev_addr)) { 2037 eth_hw_addr_random(dev); 2038 dev_err(eth->dev, "generated random MAC address %pM\n", 2039 dev->dev_addr); 2040 } 2041 2042 return mtk_phy_connect(dev); 2043 } 2044 2045 static void mtk_uninit(struct net_device *dev) 2046 { 2047 struct mtk_mac *mac = netdev_priv(dev); 2048 struct mtk_eth *eth = mac->hw; 2049 2050 phy_disconnect(dev->phydev); 2051 if (of_phy_is_fixed_link(mac->of_node)) 2052 of_phy_deregister_fixed_link(mac->of_node); 2053 mtk_tx_irq_disable(eth, ~0); 2054 mtk_rx_irq_disable(eth, ~0); 2055 } 2056 2057 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2058 { 2059 switch (cmd) { 2060 case SIOCGMIIPHY: 2061 case SIOCGMIIREG: 2062 case SIOCSMIIREG: 2063 return phy_mii_ioctl(dev->phydev, ifr, cmd); 2064 default: 2065 break; 2066 } 2067 2068 return -EOPNOTSUPP; 2069 } 2070 2071 static void mtk_pending_work(struct work_struct *work) 2072 { 2073 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2074 int err, i; 2075 unsigned long restart = 0; 2076 2077 rtnl_lock(); 2078 2079 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2080 2081 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2082 cpu_relax(); 2083 2084 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2085 /* stop all devices to make sure that dma is properly shut down */ 2086 for (i = 0; i < MTK_MAC_COUNT; i++) { 2087 if (!eth->netdev[i]) 2088 continue; 2089 mtk_stop(eth->netdev[i]); 2090 __set_bit(i, &restart); 2091 } 2092 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2093 2094 /* restart underlying hardware such as power, clock, pin mux 2095 * and the connected phy 2096 */ 2097 mtk_hw_deinit(eth); 2098 2099 if (eth->dev->pins) 2100 pinctrl_select_state(eth->dev->pins->p, 2101 eth->dev->pins->default_state); 2102 mtk_hw_init(eth); 2103 2104 for (i = 0; i < MTK_MAC_COUNT; i++) { 2105 if (!eth->mac[i] || 2106 of_phy_is_fixed_link(eth->mac[i]->of_node)) 2107 continue; 2108 err = phy_init_hw(eth->netdev[i]->phydev); 2109 if (err) 2110 dev_err(eth->dev, "%s: PHY init failed.\n", 2111 eth->netdev[i]->name); 2112 } 2113 2114 /* restart DMA and enable IRQs */ 2115 for (i = 0; i < MTK_MAC_COUNT; i++) { 2116 if (!test_bit(i, &restart)) 2117 continue; 2118 err = mtk_open(eth->netdev[i]); 2119 if (err) { 2120 netif_alert(eth, ifup, eth->netdev[i], 2121 "Driver up/down cycle failed, closing device.\n"); 2122 dev_close(eth->netdev[i]); 2123 } 2124 } 2125 2126 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2127 2128 clear_bit_unlock(MTK_RESETTING, ð->state); 2129 2130 rtnl_unlock(); 2131 } 2132 2133 static int mtk_free_dev(struct mtk_eth *eth) 2134 { 2135 int i; 2136 2137 for (i = 0; i < MTK_MAC_COUNT; i++) { 2138 if (!eth->netdev[i]) 2139 continue; 2140 free_netdev(eth->netdev[i]); 2141 } 2142 2143 return 0; 2144 } 2145 2146 static int mtk_unreg_dev(struct mtk_eth *eth) 2147 { 2148 int i; 2149 2150 for (i = 0; i < MTK_MAC_COUNT; i++) { 2151 if (!eth->netdev[i]) 2152 continue; 2153 unregister_netdev(eth->netdev[i]); 2154 } 2155 2156 return 0; 2157 } 2158 2159 static int mtk_cleanup(struct mtk_eth *eth) 2160 { 2161 mtk_unreg_dev(eth); 2162 mtk_free_dev(eth); 2163 cancel_work_sync(ð->pending_work); 2164 2165 return 0; 2166 } 2167 2168 static int mtk_get_link_ksettings(struct net_device *ndev, 2169 struct ethtool_link_ksettings *cmd) 2170 { 2171 struct mtk_mac *mac = netdev_priv(ndev); 2172 2173 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2174 return -EBUSY; 2175 2176 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2177 2178 return 0; 2179 } 2180 2181 static int mtk_set_link_ksettings(struct net_device *ndev, 2182 const struct ethtool_link_ksettings *cmd) 2183 { 2184 struct mtk_mac *mac = netdev_priv(ndev); 2185 2186 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2187 return -EBUSY; 2188 2189 return phy_ethtool_ksettings_set(ndev->phydev, cmd); 2190 } 2191 2192 static void mtk_get_drvinfo(struct net_device *dev, 2193 struct ethtool_drvinfo *info) 2194 { 2195 struct mtk_mac *mac = netdev_priv(dev); 2196 2197 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2198 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2199 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2200 } 2201 2202 static u32 mtk_get_msglevel(struct net_device *dev) 2203 { 2204 struct mtk_mac *mac = netdev_priv(dev); 2205 2206 return mac->hw->msg_enable; 2207 } 2208 2209 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2210 { 2211 struct mtk_mac *mac = netdev_priv(dev); 2212 2213 mac->hw->msg_enable = value; 2214 } 2215 2216 static int mtk_nway_reset(struct net_device *dev) 2217 { 2218 struct mtk_mac *mac = netdev_priv(dev); 2219 2220 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2221 return -EBUSY; 2222 2223 return genphy_restart_aneg(dev->phydev); 2224 } 2225 2226 static u32 mtk_get_link(struct net_device *dev) 2227 { 2228 struct mtk_mac *mac = netdev_priv(dev); 2229 int err; 2230 2231 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2232 return -EBUSY; 2233 2234 err = genphy_update_link(dev->phydev); 2235 if (err) 2236 return ethtool_op_get_link(dev); 2237 2238 return dev->phydev->link; 2239 } 2240 2241 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2242 { 2243 int i; 2244 2245 switch (stringset) { 2246 case ETH_SS_STATS: 2247 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2248 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2249 data += ETH_GSTRING_LEN; 2250 } 2251 break; 2252 } 2253 } 2254 2255 static int mtk_get_sset_count(struct net_device *dev, int sset) 2256 { 2257 switch (sset) { 2258 case ETH_SS_STATS: 2259 return ARRAY_SIZE(mtk_ethtool_stats); 2260 default: 2261 return -EOPNOTSUPP; 2262 } 2263 } 2264 2265 static void mtk_get_ethtool_stats(struct net_device *dev, 2266 struct ethtool_stats *stats, u64 *data) 2267 { 2268 struct mtk_mac *mac = netdev_priv(dev); 2269 struct mtk_hw_stats *hwstats = mac->hw_stats; 2270 u64 *data_src, *data_dst; 2271 unsigned int start; 2272 int i; 2273 2274 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2275 return; 2276 2277 if (netif_running(dev) && netif_device_present(dev)) { 2278 if (spin_trylock_bh(&hwstats->stats_lock)) { 2279 mtk_stats_update_mac(mac); 2280 spin_unlock_bh(&hwstats->stats_lock); 2281 } 2282 } 2283 2284 data_src = (u64 *)hwstats; 2285 2286 do { 2287 data_dst = data; 2288 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2289 2290 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2291 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2292 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2293 } 2294 2295 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2296 u32 *rule_locs) 2297 { 2298 int ret = -EOPNOTSUPP; 2299 2300 switch (cmd->cmd) { 2301 case ETHTOOL_GRXRINGS: 2302 if (dev->hw_features & NETIF_F_LRO) { 2303 cmd->data = MTK_MAX_RX_RING_NUM; 2304 ret = 0; 2305 } 2306 break; 2307 case ETHTOOL_GRXCLSRLCNT: 2308 if (dev->hw_features & NETIF_F_LRO) { 2309 struct mtk_mac *mac = netdev_priv(dev); 2310 2311 cmd->rule_cnt = mac->hwlro_ip_cnt; 2312 ret = 0; 2313 } 2314 break; 2315 case ETHTOOL_GRXCLSRULE: 2316 if (dev->hw_features & NETIF_F_LRO) 2317 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2318 break; 2319 case ETHTOOL_GRXCLSRLALL: 2320 if (dev->hw_features & NETIF_F_LRO) 2321 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2322 rule_locs); 2323 break; 2324 default: 2325 break; 2326 } 2327 2328 return ret; 2329 } 2330 2331 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2332 { 2333 int ret = -EOPNOTSUPP; 2334 2335 switch (cmd->cmd) { 2336 case ETHTOOL_SRXCLSRLINS: 2337 if (dev->hw_features & NETIF_F_LRO) 2338 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2339 break; 2340 case ETHTOOL_SRXCLSRLDEL: 2341 if (dev->hw_features & NETIF_F_LRO) 2342 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2343 break; 2344 default: 2345 break; 2346 } 2347 2348 return ret; 2349 } 2350 2351 static const struct ethtool_ops mtk_ethtool_ops = { 2352 .get_link_ksettings = mtk_get_link_ksettings, 2353 .set_link_ksettings = mtk_set_link_ksettings, 2354 .get_drvinfo = mtk_get_drvinfo, 2355 .get_msglevel = mtk_get_msglevel, 2356 .set_msglevel = mtk_set_msglevel, 2357 .nway_reset = mtk_nway_reset, 2358 .get_link = mtk_get_link, 2359 .get_strings = mtk_get_strings, 2360 .get_sset_count = mtk_get_sset_count, 2361 .get_ethtool_stats = mtk_get_ethtool_stats, 2362 .get_rxnfc = mtk_get_rxnfc, 2363 .set_rxnfc = mtk_set_rxnfc, 2364 }; 2365 2366 static const struct net_device_ops mtk_netdev_ops = { 2367 .ndo_init = mtk_init, 2368 .ndo_uninit = mtk_uninit, 2369 .ndo_open = mtk_open, 2370 .ndo_stop = mtk_stop, 2371 .ndo_start_xmit = mtk_start_xmit, 2372 .ndo_set_mac_address = mtk_set_mac_address, 2373 .ndo_validate_addr = eth_validate_addr, 2374 .ndo_do_ioctl = mtk_do_ioctl, 2375 .ndo_tx_timeout = mtk_tx_timeout, 2376 .ndo_get_stats64 = mtk_get_stats64, 2377 .ndo_fix_features = mtk_fix_features, 2378 .ndo_set_features = mtk_set_features, 2379 #ifdef CONFIG_NET_POLL_CONTROLLER 2380 .ndo_poll_controller = mtk_poll_controller, 2381 #endif 2382 }; 2383 2384 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2385 { 2386 struct mtk_mac *mac; 2387 const __be32 *_id = of_get_property(np, "reg", NULL); 2388 int id, err; 2389 2390 if (!_id) { 2391 dev_err(eth->dev, "missing mac id\n"); 2392 return -EINVAL; 2393 } 2394 2395 id = be32_to_cpup(_id); 2396 if (id >= MTK_MAC_COUNT) { 2397 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2398 return -EINVAL; 2399 } 2400 2401 if (eth->netdev[id]) { 2402 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2403 return -EINVAL; 2404 } 2405 2406 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2407 if (!eth->netdev[id]) { 2408 dev_err(eth->dev, "alloc_etherdev failed\n"); 2409 return -ENOMEM; 2410 } 2411 mac = netdev_priv(eth->netdev[id]); 2412 eth->mac[id] = mac; 2413 mac->id = id; 2414 mac->hw = eth; 2415 mac->of_node = np; 2416 2417 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2418 mac->hwlro_ip_cnt = 0; 2419 2420 mac->hw_stats = devm_kzalloc(eth->dev, 2421 sizeof(*mac->hw_stats), 2422 GFP_KERNEL); 2423 if (!mac->hw_stats) { 2424 dev_err(eth->dev, "failed to allocate counter memory\n"); 2425 err = -ENOMEM; 2426 goto free_netdev; 2427 } 2428 spin_lock_init(&mac->hw_stats->stats_lock); 2429 u64_stats_init(&mac->hw_stats->syncp); 2430 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2431 2432 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2433 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2434 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2435 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2436 2437 eth->netdev[id]->hw_features = MTK_HW_FEATURES; 2438 if (eth->hwlro) 2439 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2440 2441 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 2442 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2443 eth->netdev[id]->features |= MTK_HW_FEATURES; 2444 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2445 2446 eth->netdev[id]->irq = eth->irq[0]; 2447 eth->netdev[id]->dev.of_node = np; 2448 2449 return 0; 2450 2451 free_netdev: 2452 free_netdev(eth->netdev[id]); 2453 return err; 2454 } 2455 2456 static int mtk_probe(struct platform_device *pdev) 2457 { 2458 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2459 struct device_node *mac_np; 2460 struct mtk_eth *eth; 2461 int err; 2462 int i; 2463 2464 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2465 if (!eth) 2466 return -ENOMEM; 2467 2468 eth->soc = of_device_get_match_data(&pdev->dev); 2469 2470 eth->dev = &pdev->dev; 2471 eth->base = devm_ioremap_resource(&pdev->dev, res); 2472 if (IS_ERR(eth->base)) 2473 return PTR_ERR(eth->base); 2474 2475 spin_lock_init(ð->page_lock); 2476 spin_lock_init(ð->tx_irq_lock); 2477 spin_lock_init(ð->rx_irq_lock); 2478 2479 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2480 "mediatek,ethsys"); 2481 if (IS_ERR(eth->ethsys)) { 2482 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2483 return PTR_ERR(eth->ethsys); 2484 } 2485 2486 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2487 eth->sgmiisys = 2488 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2489 "mediatek,sgmiisys"); 2490 if (IS_ERR(eth->sgmiisys)) { 2491 dev_err(&pdev->dev, "no sgmiisys regmap found\n"); 2492 return PTR_ERR(eth->sgmiisys); 2493 } 2494 } 2495 2496 if (eth->soc->required_pctl) { 2497 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2498 "mediatek,pctl"); 2499 if (IS_ERR(eth->pctl)) { 2500 dev_err(&pdev->dev, "no pctl regmap found\n"); 2501 return PTR_ERR(eth->pctl); 2502 } 2503 } 2504 2505 for (i = 0; i < 3; i++) { 2506 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 2507 eth->irq[i] = eth->irq[0]; 2508 else 2509 eth->irq[i] = platform_get_irq(pdev, i); 2510 if (eth->irq[i] < 0) { 2511 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2512 return -ENXIO; 2513 } 2514 } 2515 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2516 eth->clks[i] = devm_clk_get(eth->dev, 2517 mtk_clks_source_name[i]); 2518 if (IS_ERR(eth->clks[i])) { 2519 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2520 return -EPROBE_DEFER; 2521 if (eth->soc->required_clks & BIT(i)) { 2522 dev_err(&pdev->dev, "clock %s not found\n", 2523 mtk_clks_source_name[i]); 2524 return -EINVAL; 2525 } 2526 eth->clks[i] = NULL; 2527 } 2528 } 2529 2530 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2531 INIT_WORK(ð->pending_work, mtk_pending_work); 2532 2533 err = mtk_hw_init(eth); 2534 if (err) 2535 return err; 2536 2537 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 2538 2539 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2540 if (!of_device_is_compatible(mac_np, 2541 "mediatek,eth-mac")) 2542 continue; 2543 2544 if (!of_device_is_available(mac_np)) 2545 continue; 2546 2547 err = mtk_add_mac(eth, mac_np); 2548 if (err) 2549 goto err_deinit_hw; 2550 } 2551 2552 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 2553 err = devm_request_irq(eth->dev, eth->irq[0], 2554 mtk_handle_irq, 0, 2555 dev_name(eth->dev), eth); 2556 } else { 2557 err = devm_request_irq(eth->dev, eth->irq[1], 2558 mtk_handle_irq_tx, 0, 2559 dev_name(eth->dev), eth); 2560 if (err) 2561 goto err_free_dev; 2562 2563 err = devm_request_irq(eth->dev, eth->irq[2], 2564 mtk_handle_irq_rx, 0, 2565 dev_name(eth->dev), eth); 2566 } 2567 if (err) 2568 goto err_free_dev; 2569 2570 err = mtk_mdio_init(eth); 2571 if (err) 2572 goto err_free_dev; 2573 2574 for (i = 0; i < MTK_MAX_DEVS; i++) { 2575 if (!eth->netdev[i]) 2576 continue; 2577 2578 err = register_netdev(eth->netdev[i]); 2579 if (err) { 2580 dev_err(eth->dev, "error bringing up device\n"); 2581 goto err_deinit_mdio; 2582 } else 2583 netif_info(eth, probe, eth->netdev[i], 2584 "mediatek frame engine at 0x%08lx, irq %d\n", 2585 eth->netdev[i]->base_addr, eth->irq[0]); 2586 } 2587 2588 /* we run 2 devices on the same DMA ring so we need a dummy device 2589 * for NAPI to work 2590 */ 2591 init_dummy_netdev(ð->dummy_dev); 2592 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 2593 MTK_NAPI_WEIGHT); 2594 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 2595 MTK_NAPI_WEIGHT); 2596 2597 platform_set_drvdata(pdev, eth); 2598 2599 return 0; 2600 2601 err_deinit_mdio: 2602 mtk_mdio_cleanup(eth); 2603 err_free_dev: 2604 mtk_free_dev(eth); 2605 err_deinit_hw: 2606 mtk_hw_deinit(eth); 2607 2608 return err; 2609 } 2610 2611 static int mtk_remove(struct platform_device *pdev) 2612 { 2613 struct mtk_eth *eth = platform_get_drvdata(pdev); 2614 int i; 2615 2616 /* stop all devices to make sure that dma is properly shut down */ 2617 for (i = 0; i < MTK_MAC_COUNT; i++) { 2618 if (!eth->netdev[i]) 2619 continue; 2620 mtk_stop(eth->netdev[i]); 2621 } 2622 2623 mtk_hw_deinit(eth); 2624 2625 netif_napi_del(ð->tx_napi); 2626 netif_napi_del(ð->rx_napi); 2627 mtk_cleanup(eth); 2628 mtk_mdio_cleanup(eth); 2629 2630 return 0; 2631 } 2632 2633 static const struct mtk_soc_data mt2701_data = { 2634 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO, 2635 .required_clks = MT7623_CLKS_BITMAP, 2636 .required_pctl = true, 2637 }; 2638 2639 static const struct mtk_soc_data mt7621_data = { 2640 .caps = MTK_SHARED_INT, 2641 .required_clks = MT7621_CLKS_BITMAP, 2642 .required_pctl = false, 2643 }; 2644 2645 static const struct mtk_soc_data mt7622_data = { 2646 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO, 2647 .required_clks = MT7622_CLKS_BITMAP, 2648 .required_pctl = false, 2649 }; 2650 2651 static const struct mtk_soc_data mt7623_data = { 2652 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO, 2653 .required_clks = MT7623_CLKS_BITMAP, 2654 .required_pctl = true, 2655 }; 2656 2657 const struct of_device_id of_mtk_match[] = { 2658 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 2659 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 2660 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 2661 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 2662 {}, 2663 }; 2664 MODULE_DEVICE_TABLE(of, of_mtk_match); 2665 2666 static struct platform_driver mtk_driver = { 2667 .probe = mtk_probe, 2668 .remove = mtk_remove, 2669 .driver = { 2670 .name = "mtk_soc_eth", 2671 .of_match_table = of_mtk_match, 2672 }, 2673 }; 2674 2675 module_platform_driver(mtk_driver); 2676 2677 MODULE_LICENSE("GPL"); 2678 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 2679 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 2680