1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/clk.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/if_vlan.h> 19 #include <linux/reset.h> 20 #include <linux/tcp.h> 21 #include <linux/interrupt.h> 22 #include <linux/pinctrl/devinfo.h> 23 #include <linux/phylink.h> 24 #include <linux/pcs/pcs-mtk-lynxi.h> 25 #include <linux/jhash.h> 26 #include <linux/bitfield.h> 27 #include <net/dsa.h> 28 #include <net/dst_metadata.h> 29 #include <net/page_pool/helpers.h> 30 31 #include "mtk_eth_soc.h" 32 #include "mtk_wed.h" 33 34 static int mtk_msg_level = -1; 35 module_param_named(msg_level, mtk_msg_level, int, 0); 36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 37 38 #define MTK_ETHTOOL_STAT(x) { #x, \ 39 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 40 41 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 42 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 43 sizeof(u64) } 44 45 static const struct mtk_reg_map mtk_reg_map = { 46 .tx_irq_mask = 0x1a1c, 47 .tx_irq_status = 0x1a18, 48 .pdma = { 49 .rx_ptr = 0x0900, 50 .rx_cnt_cfg = 0x0904, 51 .pcrx_ptr = 0x0908, 52 .glo_cfg = 0x0a04, 53 .rst_idx = 0x0a08, 54 .delay_irq = 0x0a0c, 55 .irq_status = 0x0a20, 56 .irq_mask = 0x0a28, 57 .adma_rx_dbg0 = 0x0a38, 58 .int_grp = 0x0a50, 59 }, 60 .qdma = { 61 .qtx_cfg = 0x1800, 62 .qtx_sch = 0x1804, 63 .rx_ptr = 0x1900, 64 .rx_cnt_cfg = 0x1904, 65 .qcrx_ptr = 0x1908, 66 .glo_cfg = 0x1a04, 67 .rst_idx = 0x1a08, 68 .delay_irq = 0x1a0c, 69 .fc_th = 0x1a10, 70 .tx_sch_rate = 0x1a14, 71 .int_grp = 0x1a20, 72 .hred = 0x1a44, 73 .ctx_ptr = 0x1b00, 74 .dtx_ptr = 0x1b04, 75 .crx_ptr = 0x1b10, 76 .drx_ptr = 0x1b14, 77 .fq_head = 0x1b20, 78 .fq_tail = 0x1b24, 79 .fq_count = 0x1b28, 80 .fq_blen = 0x1b2c, 81 }, 82 .gdm1_cnt = 0x2400, 83 .gdma_to_ppe = { 84 [0] = 0x4444, 85 }, 86 .ppe_base = 0x0c00, 87 .wdma_base = { 88 [0] = 0x2800, 89 [1] = 0x2c00, 90 }, 91 .pse_iq_sta = 0x0110, 92 .pse_oq_sta = 0x0118, 93 }; 94 95 static const struct mtk_reg_map mt7628_reg_map = { 96 .tx_irq_mask = 0x0a28, 97 .tx_irq_status = 0x0a20, 98 .pdma = { 99 .rx_ptr = 0x0900, 100 .rx_cnt_cfg = 0x0904, 101 .pcrx_ptr = 0x0908, 102 .glo_cfg = 0x0a04, 103 .rst_idx = 0x0a08, 104 .delay_irq = 0x0a0c, 105 .irq_status = 0x0a20, 106 .irq_mask = 0x0a28, 107 .int_grp = 0x0a50, 108 }, 109 }; 110 111 static const struct mtk_reg_map mt7986_reg_map = { 112 .tx_irq_mask = 0x461c, 113 .tx_irq_status = 0x4618, 114 .pdma = { 115 .rx_ptr = 0x4100, 116 .rx_cnt_cfg = 0x4104, 117 .pcrx_ptr = 0x4108, 118 .glo_cfg = 0x4204, 119 .rst_idx = 0x4208, 120 .delay_irq = 0x420c, 121 .irq_status = 0x4220, 122 .irq_mask = 0x4228, 123 .adma_rx_dbg0 = 0x4238, 124 .int_grp = 0x4250, 125 }, 126 .qdma = { 127 .qtx_cfg = 0x4400, 128 .qtx_sch = 0x4404, 129 .rx_ptr = 0x4500, 130 .rx_cnt_cfg = 0x4504, 131 .qcrx_ptr = 0x4508, 132 .glo_cfg = 0x4604, 133 .rst_idx = 0x4608, 134 .delay_irq = 0x460c, 135 .fc_th = 0x4610, 136 .int_grp = 0x4620, 137 .hred = 0x4644, 138 .ctx_ptr = 0x4700, 139 .dtx_ptr = 0x4704, 140 .crx_ptr = 0x4710, 141 .drx_ptr = 0x4714, 142 .fq_head = 0x4720, 143 .fq_tail = 0x4724, 144 .fq_count = 0x4728, 145 .fq_blen = 0x472c, 146 .tx_sch_rate = 0x4798, 147 }, 148 .gdm1_cnt = 0x1c00, 149 .gdma_to_ppe = { 150 [0] = 0x3333, 151 [1] = 0x4444, 152 }, 153 .ppe_base = 0x2000, 154 .wdma_base = { 155 [0] = 0x4800, 156 [1] = 0x4c00, 157 }, 158 .pse_iq_sta = 0x0180, 159 .pse_oq_sta = 0x01a0, 160 }; 161 162 static const struct mtk_reg_map mt7988_reg_map = { 163 .tx_irq_mask = 0x461c, 164 .tx_irq_status = 0x4618, 165 .pdma = { 166 .rx_ptr = 0x6900, 167 .rx_cnt_cfg = 0x6904, 168 .pcrx_ptr = 0x6908, 169 .glo_cfg = 0x6a04, 170 .rst_idx = 0x6a08, 171 .delay_irq = 0x6a0c, 172 .irq_status = 0x6a20, 173 .irq_mask = 0x6a28, 174 .adma_rx_dbg0 = 0x6a38, 175 .int_grp = 0x6a50, 176 }, 177 .qdma = { 178 .qtx_cfg = 0x4400, 179 .qtx_sch = 0x4404, 180 .rx_ptr = 0x4500, 181 .rx_cnt_cfg = 0x4504, 182 .qcrx_ptr = 0x4508, 183 .glo_cfg = 0x4604, 184 .rst_idx = 0x4608, 185 .delay_irq = 0x460c, 186 .fc_th = 0x4610, 187 .int_grp = 0x4620, 188 .hred = 0x4644, 189 .ctx_ptr = 0x4700, 190 .dtx_ptr = 0x4704, 191 .crx_ptr = 0x4710, 192 .drx_ptr = 0x4714, 193 .fq_head = 0x4720, 194 .fq_tail = 0x4724, 195 .fq_count = 0x4728, 196 .fq_blen = 0x472c, 197 .tx_sch_rate = 0x4798, 198 }, 199 .gdm1_cnt = 0x1c00, 200 .gdma_to_ppe = { 201 [0] = 0x3333, 202 [1] = 0x4444, 203 [2] = 0xcccc, 204 }, 205 .ppe_base = 0x2000, 206 .wdma_base = { 207 [0] = 0x4800, 208 [1] = 0x4c00, 209 [2] = 0x5000, 210 }, 211 .pse_iq_sta = 0x0180, 212 .pse_oq_sta = 0x01a0, 213 }; 214 215 /* strings used by ethtool */ 216 static const struct mtk_ethtool_stats { 217 char str[ETH_GSTRING_LEN]; 218 u32 offset; 219 } mtk_ethtool_stats[] = { 220 MTK_ETHTOOL_STAT(tx_bytes), 221 MTK_ETHTOOL_STAT(tx_packets), 222 MTK_ETHTOOL_STAT(tx_skip), 223 MTK_ETHTOOL_STAT(tx_collisions), 224 MTK_ETHTOOL_STAT(rx_bytes), 225 MTK_ETHTOOL_STAT(rx_packets), 226 MTK_ETHTOOL_STAT(rx_overflow), 227 MTK_ETHTOOL_STAT(rx_fcs_errors), 228 MTK_ETHTOOL_STAT(rx_short_errors), 229 MTK_ETHTOOL_STAT(rx_long_errors), 230 MTK_ETHTOOL_STAT(rx_checksum_errors), 231 MTK_ETHTOOL_STAT(rx_flow_control_packets), 232 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 233 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 234 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 235 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 236 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 237 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 238 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 239 }; 240 241 static const char * const mtk_clks_source_name[] = { 242 "ethif", 243 "sgmiitop", 244 "esw", 245 "gp0", 246 "gp1", 247 "gp2", 248 "gp3", 249 "xgp1", 250 "xgp2", 251 "xgp3", 252 "crypto", 253 "fe", 254 "trgpll", 255 "sgmii_tx250m", 256 "sgmii_rx250m", 257 "sgmii_cdr_ref", 258 "sgmii_cdr_fb", 259 "sgmii2_tx250m", 260 "sgmii2_rx250m", 261 "sgmii2_cdr_ref", 262 "sgmii2_cdr_fb", 263 "sgmii_ck", 264 "eth2pll", 265 "wocpu0", 266 "wocpu1", 267 "netsys0", 268 "netsys1", 269 "ethwarp_wocpu2", 270 "ethwarp_wocpu1", 271 "ethwarp_wocpu0", 272 "top_usxgmii0_sel", 273 "top_usxgmii1_sel", 274 "top_sgm0_sel", 275 "top_sgm1_sel", 276 "top_xfi_phy0_xtal_sel", 277 "top_xfi_phy1_xtal_sel", 278 "top_eth_gmii_sel", 279 "top_eth_refck_50m_sel", 280 "top_eth_sys_200m_sel", 281 "top_eth_sys_sel", 282 "top_eth_xgmii_sel", 283 "top_eth_mii_sel", 284 "top_netsys_sel", 285 "top_netsys_500m_sel", 286 "top_netsys_pao_2x_sel", 287 "top_netsys_sync_250m_sel", 288 "top_netsys_ppefb_250m_sel", 289 "top_netsys_warp_sel", 290 }; 291 292 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 293 { 294 __raw_writel(val, eth->base + reg); 295 } 296 297 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 298 { 299 return __raw_readl(eth->base + reg); 300 } 301 302 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) 303 { 304 u32 val; 305 306 val = mtk_r32(eth, reg); 307 val &= ~mask; 308 val |= set; 309 mtk_w32(eth, val, reg); 310 return reg; 311 } 312 313 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 314 { 315 unsigned long t_start = jiffies; 316 317 while (1) { 318 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 319 return 0; 320 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 321 break; 322 cond_resched(); 323 } 324 325 dev_err(eth->dev, "mdio: MDIO timeout\n"); 326 return -ETIMEDOUT; 327 } 328 329 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 330 u32 write_data) 331 { 332 int ret; 333 334 ret = mtk_mdio_busy_wait(eth); 335 if (ret < 0) 336 return ret; 337 338 mtk_w32(eth, PHY_IAC_ACCESS | 339 PHY_IAC_START_C22 | 340 PHY_IAC_CMD_WRITE | 341 PHY_IAC_REG(phy_reg) | 342 PHY_IAC_ADDR(phy_addr) | 343 PHY_IAC_DATA(write_data), 344 MTK_PHY_IAC); 345 346 ret = mtk_mdio_busy_wait(eth); 347 if (ret < 0) 348 return ret; 349 350 return 0; 351 } 352 353 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 354 u32 devad, u32 phy_reg, u32 write_data) 355 { 356 int ret; 357 358 ret = mtk_mdio_busy_wait(eth); 359 if (ret < 0) 360 return ret; 361 362 mtk_w32(eth, PHY_IAC_ACCESS | 363 PHY_IAC_START_C45 | 364 PHY_IAC_CMD_C45_ADDR | 365 PHY_IAC_REG(devad) | 366 PHY_IAC_ADDR(phy_addr) | 367 PHY_IAC_DATA(phy_reg), 368 MTK_PHY_IAC); 369 370 ret = mtk_mdio_busy_wait(eth); 371 if (ret < 0) 372 return ret; 373 374 mtk_w32(eth, PHY_IAC_ACCESS | 375 PHY_IAC_START_C45 | 376 PHY_IAC_CMD_WRITE | 377 PHY_IAC_REG(devad) | 378 PHY_IAC_ADDR(phy_addr) | 379 PHY_IAC_DATA(write_data), 380 MTK_PHY_IAC); 381 382 ret = mtk_mdio_busy_wait(eth); 383 if (ret < 0) 384 return ret; 385 386 return 0; 387 } 388 389 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 390 { 391 int ret; 392 393 ret = mtk_mdio_busy_wait(eth); 394 if (ret < 0) 395 return ret; 396 397 mtk_w32(eth, PHY_IAC_ACCESS | 398 PHY_IAC_START_C22 | 399 PHY_IAC_CMD_C22_READ | 400 PHY_IAC_REG(phy_reg) | 401 PHY_IAC_ADDR(phy_addr), 402 MTK_PHY_IAC); 403 404 ret = mtk_mdio_busy_wait(eth); 405 if (ret < 0) 406 return ret; 407 408 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 409 } 410 411 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 412 u32 devad, u32 phy_reg) 413 { 414 int ret; 415 416 ret = mtk_mdio_busy_wait(eth); 417 if (ret < 0) 418 return ret; 419 420 mtk_w32(eth, PHY_IAC_ACCESS | 421 PHY_IAC_START_C45 | 422 PHY_IAC_CMD_C45_ADDR | 423 PHY_IAC_REG(devad) | 424 PHY_IAC_ADDR(phy_addr) | 425 PHY_IAC_DATA(phy_reg), 426 MTK_PHY_IAC); 427 428 ret = mtk_mdio_busy_wait(eth); 429 if (ret < 0) 430 return ret; 431 432 mtk_w32(eth, PHY_IAC_ACCESS | 433 PHY_IAC_START_C45 | 434 PHY_IAC_CMD_C45_READ | 435 PHY_IAC_REG(devad) | 436 PHY_IAC_ADDR(phy_addr), 437 MTK_PHY_IAC); 438 439 ret = mtk_mdio_busy_wait(eth); 440 if (ret < 0) 441 return ret; 442 443 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 444 } 445 446 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 447 int phy_reg, u16 val) 448 { 449 struct mtk_eth *eth = bus->priv; 450 451 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 452 } 453 454 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 455 int devad, int phy_reg, u16 val) 456 { 457 struct mtk_eth *eth = bus->priv; 458 459 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 460 } 461 462 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 463 { 464 struct mtk_eth *eth = bus->priv; 465 466 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 467 } 468 469 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 470 int phy_reg) 471 { 472 struct mtk_eth *eth = bus->priv; 473 474 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 475 } 476 477 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 478 phy_interface_t interface) 479 { 480 u32 val; 481 482 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 483 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 484 485 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 486 ETHSYS_TRGMII_MT7621_MASK, val); 487 488 return 0; 489 } 490 491 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 492 phy_interface_t interface) 493 { 494 int ret; 495 496 if (interface == PHY_INTERFACE_MODE_TRGMII) { 497 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 498 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); 499 if (ret) 500 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 501 return; 502 } 503 504 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); 505 } 506 507 static void mtk_setup_bridge_switch(struct mtk_eth *eth) 508 { 509 /* Force Port1 XGMAC Link Up */ 510 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), 511 MTK_XGMAC_STS(MTK_GMAC1_ID)); 512 513 /* Adjust GSW bridge IPG to 11 */ 514 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, 515 (GSW_IPG_11 << GSWTX_IPG_SHIFT) | 516 (GSW_IPG_11 << GSWRX_IPG_SHIFT), 517 MTK_GSW_CFG); 518 } 519 520 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 521 phy_interface_t interface) 522 { 523 struct mtk_mac *mac = container_of(config, struct mtk_mac, 524 phylink_config); 525 struct mtk_eth *eth = mac->hw; 526 unsigned int sid; 527 528 if (interface == PHY_INTERFACE_MODE_SGMII || 529 phy_interface_mode_is_8023z(interface)) { 530 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 531 0 : mac->id; 532 533 return eth->sgmii_pcs[sid]; 534 } 535 536 return NULL; 537 } 538 539 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 540 const struct phylink_link_state *state) 541 { 542 struct mtk_mac *mac = container_of(config, struct mtk_mac, 543 phylink_config); 544 struct mtk_eth *eth = mac->hw; 545 int val, ge_mode, err = 0; 546 u32 i; 547 548 /* MT76x8 has no hardware settings between for the MAC */ 549 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 550 mac->interface != state->interface) { 551 /* Setup soc pin functions */ 552 switch (state->interface) { 553 case PHY_INTERFACE_MODE_TRGMII: 554 case PHY_INTERFACE_MODE_RGMII_TXID: 555 case PHY_INTERFACE_MODE_RGMII_RXID: 556 case PHY_INTERFACE_MODE_RGMII_ID: 557 case PHY_INTERFACE_MODE_RGMII: 558 case PHY_INTERFACE_MODE_MII: 559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 560 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 561 if (err) 562 goto init_err; 563 } 564 break; 565 case PHY_INTERFACE_MODE_1000BASEX: 566 case PHY_INTERFACE_MODE_2500BASEX: 567 case PHY_INTERFACE_MODE_SGMII: 568 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 569 if (err) 570 goto init_err; 571 break; 572 case PHY_INTERFACE_MODE_GMII: 573 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 574 err = mtk_gmac_gephy_path_setup(eth, mac->id); 575 if (err) 576 goto init_err; 577 } 578 break; 579 case PHY_INTERFACE_MODE_INTERNAL: 580 break; 581 default: 582 goto err_phy; 583 } 584 585 /* Setup clock for 1st gmac */ 586 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 587 !phy_interface_mode_is_8023z(state->interface) && 588 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 589 if (MTK_HAS_CAPS(mac->hw->soc->caps, 590 MTK_TRGMII_MT7621_CLK)) { 591 if (mt7621_gmac0_rgmii_adjust(mac->hw, 592 state->interface)) 593 goto err_phy; 594 } else { 595 mtk_gmac0_rgmii_adjust(mac->hw, 596 state->interface); 597 598 /* mt7623_pad_clk_setup */ 599 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 600 mtk_w32(mac->hw, 601 TD_DM_DRVP(8) | TD_DM_DRVN(8), 602 TRGMII_TD_ODT(i)); 603 604 /* Assert/release MT7623 RXC reset */ 605 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 606 TRGMII_RCK_CTRL); 607 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 608 } 609 } 610 611 switch (state->interface) { 612 case PHY_INTERFACE_MODE_MII: 613 case PHY_INTERFACE_MODE_GMII: 614 ge_mode = 1; 615 break; 616 default: 617 ge_mode = 0; 618 break; 619 } 620 621 /* put the gmac into the right mode */ 622 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 623 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 624 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 625 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 626 627 mac->interface = state->interface; 628 } 629 630 /* SGMII */ 631 if (state->interface == PHY_INTERFACE_MODE_SGMII || 632 phy_interface_mode_is_8023z(state->interface)) { 633 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 634 * being setup done. 635 */ 636 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 637 638 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 639 SYSCFG0_SGMII_MASK, 640 ~(u32)SYSCFG0_SGMII_MASK); 641 642 /* Save the syscfg0 value for mac_finish */ 643 mac->syscfg0 = val; 644 } else if (phylink_autoneg_inband(mode)) { 645 dev_err(eth->dev, 646 "In-band mode not supported in non SGMII mode!\n"); 647 return; 648 } 649 650 /* Setup gmac */ 651 if (mtk_is_netsys_v3_or_greater(eth) && 652 mac->interface == PHY_INTERFACE_MODE_INTERNAL) { 653 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); 654 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); 655 656 mtk_setup_bridge_switch(eth); 657 } 658 659 return; 660 661 err_phy: 662 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 663 mac->id, phy_modes(state->interface)); 664 return; 665 666 init_err: 667 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 668 mac->id, phy_modes(state->interface), err); 669 } 670 671 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 672 phy_interface_t interface) 673 { 674 struct mtk_mac *mac = container_of(config, struct mtk_mac, 675 phylink_config); 676 struct mtk_eth *eth = mac->hw; 677 u32 mcr_cur, mcr_new; 678 679 /* Enable SGMII */ 680 if (interface == PHY_INTERFACE_MODE_SGMII || 681 phy_interface_mode_is_8023z(interface)) 682 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 683 SYSCFG0_SGMII_MASK, mac->syscfg0); 684 685 /* Setup gmac */ 686 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 687 mcr_new = mcr_cur; 688 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 689 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS; 690 691 /* Only update control register when needed! */ 692 if (mcr_new != mcr_cur) 693 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 694 695 return 0; 696 } 697 698 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 699 phy_interface_t interface) 700 { 701 struct mtk_mac *mac = container_of(config, struct mtk_mac, 702 phylink_config); 703 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 704 705 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK); 706 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 707 } 708 709 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 710 int speed) 711 { 712 const struct mtk_soc_data *soc = eth->soc; 713 u32 ofs, val; 714 715 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 716 return; 717 718 val = MTK_QTX_SCH_MIN_RATE_EN | 719 /* minimum: 10 Mbps */ 720 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 721 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 722 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 723 if (mtk_is_netsys_v1(eth)) 724 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 725 726 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 727 switch (speed) { 728 case SPEED_10: 729 val |= MTK_QTX_SCH_MAX_RATE_EN | 730 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 731 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 732 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 733 break; 734 case SPEED_100: 735 val |= MTK_QTX_SCH_MAX_RATE_EN | 736 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 737 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 738 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 739 break; 740 case SPEED_1000: 741 val |= MTK_QTX_SCH_MAX_RATE_EN | 742 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 743 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 744 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 745 break; 746 default: 747 break; 748 } 749 } else { 750 switch (speed) { 751 case SPEED_10: 752 val |= MTK_QTX_SCH_MAX_RATE_EN | 753 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 754 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 755 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 756 break; 757 case SPEED_100: 758 val |= MTK_QTX_SCH_MAX_RATE_EN | 759 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 760 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 761 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 762 break; 763 case SPEED_1000: 764 val |= MTK_QTX_SCH_MAX_RATE_EN | 765 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 766 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 767 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 768 break; 769 default: 770 break; 771 } 772 } 773 774 ofs = MTK_QTX_OFFSET * idx; 775 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 776 } 777 778 static void mtk_mac_link_up(struct phylink_config *config, 779 struct phy_device *phy, 780 unsigned int mode, phy_interface_t interface, 781 int speed, int duplex, bool tx_pause, bool rx_pause) 782 { 783 struct mtk_mac *mac = container_of(config, struct mtk_mac, 784 phylink_config); 785 u32 mcr; 786 787 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 788 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 789 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 790 MAC_MCR_FORCE_RX_FC); 791 792 /* Configure speed */ 793 mac->speed = speed; 794 switch (speed) { 795 case SPEED_2500: 796 case SPEED_1000: 797 mcr |= MAC_MCR_SPEED_1000; 798 break; 799 case SPEED_100: 800 mcr |= MAC_MCR_SPEED_100; 801 break; 802 } 803 804 /* Configure duplex */ 805 if (duplex == DUPLEX_FULL) 806 mcr |= MAC_MCR_FORCE_DPX; 807 808 /* Configure pause modes - phylink will avoid these for half duplex */ 809 if (tx_pause) 810 mcr |= MAC_MCR_FORCE_TX_FC; 811 if (rx_pause) 812 mcr |= MAC_MCR_FORCE_RX_FC; 813 814 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK; 815 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 816 } 817 818 static void mtk_mac_disable_tx_lpi(struct phylink_config *config) 819 { 820 struct mtk_mac *mac = container_of(config, struct mtk_mac, 821 phylink_config); 822 struct mtk_eth *eth = mac->hw; 823 824 mtk_m32(eth, MAC_MCR_EEE100M | MAC_MCR_EEE1G, 0, MTK_MAC_MCR(mac->id)); 825 } 826 827 static int mtk_mac_enable_tx_lpi(struct phylink_config *config, u32 timer, 828 bool tx_clk_stop) 829 { 830 struct mtk_mac *mac = container_of(config, struct mtk_mac, 831 phylink_config); 832 struct mtk_eth *eth = mac->hw; 833 u32 val; 834 835 /* Tx idle timer in ms */ 836 timer = DIV_ROUND_UP(timer, 1000); 837 838 /* If the timer is zero, then set LPI_MODE, which allows the 839 * system to enter LPI mode immediately rather than waiting for 840 * the LPI threshold. 841 */ 842 if (!timer) 843 val = MAC_EEE_LPI_MODE; 844 else if (FIELD_FIT(MAC_EEE_LPI_TXIDLE_THD, timer)) 845 val = FIELD_PREP(MAC_EEE_LPI_TXIDLE_THD, timer); 846 else 847 val = MAC_EEE_LPI_TXIDLE_THD; 848 849 if (tx_clk_stop) 850 val |= MAC_EEE_CKG_TXIDLE; 851 852 /* PHY Wake-up time, this field does not have a reset value, so use the 853 * reset value from MT7531 (36us for 100M and 17us for 1000M). 854 */ 855 val |= FIELD_PREP(MAC_EEE_WAKEUP_TIME_1000, 17) | 856 FIELD_PREP(MAC_EEE_WAKEUP_TIME_100, 36); 857 858 mtk_w32(eth, val, MTK_MAC_EEECR(mac->id)); 859 mtk_m32(eth, 0, MAC_MCR_EEE100M | MAC_MCR_EEE1G, MTK_MAC_MCR(mac->id)); 860 861 return 0; 862 } 863 864 static const struct phylink_mac_ops mtk_phylink_ops = { 865 .mac_select_pcs = mtk_mac_select_pcs, 866 .mac_config = mtk_mac_config, 867 .mac_finish = mtk_mac_finish, 868 .mac_link_down = mtk_mac_link_down, 869 .mac_link_up = mtk_mac_link_up, 870 .mac_disable_tx_lpi = mtk_mac_disable_tx_lpi, 871 .mac_enable_tx_lpi = mtk_mac_enable_tx_lpi, 872 }; 873 874 static int mtk_mdio_init(struct mtk_eth *eth) 875 { 876 unsigned int max_clk = 2500000, divider; 877 struct device_node *mii_np; 878 int ret; 879 u32 val; 880 881 mii_np = of_get_available_child_by_name(eth->dev->of_node, "mdio-bus"); 882 if (!mii_np) { 883 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 884 return -ENODEV; 885 } 886 887 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 888 if (!eth->mii_bus) { 889 ret = -ENOMEM; 890 goto err_put_node; 891 } 892 893 eth->mii_bus->name = "mdio"; 894 eth->mii_bus->read = mtk_mdio_read_c22; 895 eth->mii_bus->write = mtk_mdio_write_c22; 896 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 897 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 898 eth->mii_bus->priv = eth; 899 eth->mii_bus->parent = eth->dev; 900 901 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 902 903 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { 904 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { 905 dev_err(eth->dev, "MDIO clock frequency out of range"); 906 ret = -EINVAL; 907 goto err_put_node; 908 } 909 max_clk = val; 910 } 911 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 912 913 /* Configure MDC Turbo Mode */ 914 if (mtk_is_netsys_v3_or_greater(eth)) 915 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); 916 917 /* Configure MDC Divider */ 918 val = FIELD_PREP(PPSC_MDC_CFG, divider); 919 if (!mtk_is_netsys_v3_or_greater(eth)) 920 val |= PPSC_MDC_TURBO; 921 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); 922 923 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); 924 925 ret = of_mdiobus_register(eth->mii_bus, mii_np); 926 927 err_put_node: 928 of_node_put(mii_np); 929 return ret; 930 } 931 932 static void mtk_mdio_cleanup(struct mtk_eth *eth) 933 { 934 if (!eth->mii_bus) 935 return; 936 937 mdiobus_unregister(eth->mii_bus); 938 } 939 940 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 941 { 942 unsigned long flags; 943 u32 val; 944 945 spin_lock_irqsave(ð->tx_irq_lock, flags); 946 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 947 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 948 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 949 } 950 951 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 952 { 953 unsigned long flags; 954 u32 val; 955 956 spin_lock_irqsave(ð->tx_irq_lock, flags); 957 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 958 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 959 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 960 } 961 962 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 963 { 964 unsigned long flags; 965 u32 val; 966 967 spin_lock_irqsave(ð->rx_irq_lock, flags); 968 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 969 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 970 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 971 } 972 973 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 974 { 975 unsigned long flags; 976 u32 val; 977 978 spin_lock_irqsave(ð->rx_irq_lock, flags); 979 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 980 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 981 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 982 } 983 984 static int mtk_set_mac_address(struct net_device *dev, void *p) 985 { 986 int ret = eth_mac_addr(dev, p); 987 struct mtk_mac *mac = netdev_priv(dev); 988 struct mtk_eth *eth = mac->hw; 989 const char *macaddr = dev->dev_addr; 990 991 if (ret) 992 return ret; 993 994 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 995 return -EBUSY; 996 997 spin_lock_bh(&mac->hw->page_lock); 998 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 999 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 1000 MT7628_SDM_MAC_ADRH); 1001 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 1002 (macaddr[4] << 8) | macaddr[5], 1003 MT7628_SDM_MAC_ADRL); 1004 } else { 1005 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 1006 MTK_GDMA_MAC_ADRH(mac->id)); 1007 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 1008 (macaddr[4] << 8) | macaddr[5], 1009 MTK_GDMA_MAC_ADRL(mac->id)); 1010 } 1011 spin_unlock_bh(&mac->hw->page_lock); 1012 1013 return 0; 1014 } 1015 1016 void mtk_stats_update_mac(struct mtk_mac *mac) 1017 { 1018 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1019 struct mtk_eth *eth = mac->hw; 1020 1021 u64_stats_update_begin(&hw_stats->syncp); 1022 1023 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 1024 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 1025 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 1026 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 1027 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 1028 hw_stats->rx_checksum_errors += 1029 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 1030 } else { 1031 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 1032 unsigned int offs = hw_stats->reg_offset; 1033 u64 stats; 1034 1035 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 1036 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 1037 if (stats) 1038 hw_stats->rx_bytes += (stats << 32); 1039 hw_stats->rx_packets += 1040 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 1041 hw_stats->rx_overflow += 1042 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 1043 hw_stats->rx_fcs_errors += 1044 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 1045 hw_stats->rx_short_errors += 1046 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 1047 hw_stats->rx_long_errors += 1048 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 1049 hw_stats->rx_checksum_errors += 1050 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 1051 hw_stats->rx_flow_control_packets += 1052 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 1053 1054 if (mtk_is_netsys_v3_or_greater(eth)) { 1055 hw_stats->tx_skip += 1056 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); 1057 hw_stats->tx_collisions += 1058 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); 1059 hw_stats->tx_bytes += 1060 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); 1061 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); 1062 if (stats) 1063 hw_stats->tx_bytes += (stats << 32); 1064 hw_stats->tx_packets += 1065 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); 1066 } else { 1067 hw_stats->tx_skip += 1068 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 1069 hw_stats->tx_collisions += 1070 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 1071 hw_stats->tx_bytes += 1072 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 1073 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 1074 if (stats) 1075 hw_stats->tx_bytes += (stats << 32); 1076 hw_stats->tx_packets += 1077 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 1078 } 1079 } 1080 1081 u64_stats_update_end(&hw_stats->syncp); 1082 } 1083 1084 static void mtk_stats_update(struct mtk_eth *eth) 1085 { 1086 int i; 1087 1088 for (i = 0; i < MTK_MAX_DEVS; i++) { 1089 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 1090 continue; 1091 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 1092 mtk_stats_update_mac(eth->mac[i]); 1093 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 1094 } 1095 } 1096 } 1097 1098 static void mtk_get_stats64(struct net_device *dev, 1099 struct rtnl_link_stats64 *storage) 1100 { 1101 struct mtk_mac *mac = netdev_priv(dev); 1102 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1103 unsigned int start; 1104 1105 if (netif_running(dev) && netif_device_present(dev)) { 1106 if (spin_trylock_bh(&hw_stats->stats_lock)) { 1107 mtk_stats_update_mac(mac); 1108 spin_unlock_bh(&hw_stats->stats_lock); 1109 } 1110 } 1111 1112 do { 1113 start = u64_stats_fetch_begin(&hw_stats->syncp); 1114 storage->rx_packets = hw_stats->rx_packets; 1115 storage->tx_packets = hw_stats->tx_packets; 1116 storage->rx_bytes = hw_stats->rx_bytes; 1117 storage->tx_bytes = hw_stats->tx_bytes; 1118 storage->collisions = hw_stats->tx_collisions; 1119 storage->rx_length_errors = hw_stats->rx_short_errors + 1120 hw_stats->rx_long_errors; 1121 storage->rx_over_errors = hw_stats->rx_overflow; 1122 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1123 storage->rx_errors = hw_stats->rx_checksum_errors; 1124 storage->tx_aborted_errors = hw_stats->tx_skip; 1125 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1126 1127 storage->tx_errors = dev->stats.tx_errors; 1128 storage->rx_dropped = dev->stats.rx_dropped; 1129 storage->tx_dropped = dev->stats.tx_dropped; 1130 } 1131 1132 static inline int mtk_max_frag_size(int mtu) 1133 { 1134 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1135 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1136 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1137 1138 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1139 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1140 } 1141 1142 static inline int mtk_max_buf_size(int frag_size) 1143 { 1144 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1145 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1146 1147 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1148 1149 return buf_size; 1150 } 1151 1152 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1153 struct mtk_rx_dma_v2 *dma_rxd) 1154 { 1155 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1156 if (!(rxd->rxd2 & RX_DMA_DONE)) 1157 return false; 1158 1159 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1160 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1161 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1162 if (mtk_is_netsys_v3_or_greater(eth)) { 1163 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1164 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1165 } 1166 1167 return true; 1168 } 1169 1170 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1171 { 1172 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1173 unsigned long data; 1174 1175 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1176 get_order(size)); 1177 1178 return (void *)data; 1179 } 1180 1181 /* the qdma core needs scratch memory to be setup */ 1182 static int mtk_init_fq_dma(struct mtk_eth *eth) 1183 { 1184 const struct mtk_soc_data *soc = eth->soc; 1185 dma_addr_t phy_ring_tail; 1186 int cnt = soc->tx.fq_dma_size; 1187 dma_addr_t dma_addr; 1188 int i, j, len; 1189 1190 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) 1191 eth->scratch_ring = eth->sram_base; 1192 else 1193 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1194 cnt * soc->tx.desc_size, 1195 ð->phy_scratch_ring, 1196 GFP_KERNEL); 1197 1198 if (unlikely(!eth->scratch_ring)) 1199 return -ENOMEM; 1200 1201 phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1); 1202 1203 for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) { 1204 len = min_t(int, cnt - j * MTK_FQ_DMA_LENGTH, MTK_FQ_DMA_LENGTH); 1205 eth->scratch_head[j] = kcalloc(len, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1206 1207 if (unlikely(!eth->scratch_head[j])) 1208 return -ENOMEM; 1209 1210 dma_addr = dma_map_single(eth->dma_dev, 1211 eth->scratch_head[j], len * MTK_QDMA_PAGE_SIZE, 1212 DMA_FROM_DEVICE); 1213 1214 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1215 return -ENOMEM; 1216 1217 for (i = 0; i < len; i++) { 1218 struct mtk_tx_dma_v2 *txd; 1219 1220 txd = eth->scratch_ring + (j * MTK_FQ_DMA_LENGTH + i) * soc->tx.desc_size; 1221 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1222 if (j * MTK_FQ_DMA_LENGTH + i < cnt) 1223 txd->txd2 = eth->phy_scratch_ring + 1224 (j * MTK_FQ_DMA_LENGTH + i + 1) * soc->tx.desc_size; 1225 1226 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1227 if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA)) 1228 txd->txd3 |= TX_DMA_PREP_ADDR64(dma_addr + i * MTK_QDMA_PAGE_SIZE); 1229 1230 txd->txd4 = 0; 1231 if (mtk_is_netsys_v2_or_greater(eth)) { 1232 txd->txd5 = 0; 1233 txd->txd6 = 0; 1234 txd->txd7 = 0; 1235 txd->txd8 = 0; 1236 } 1237 } 1238 } 1239 1240 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1241 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1242 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1243 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1244 1245 return 0; 1246 } 1247 1248 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1249 { 1250 return ring->dma + (desc - ring->phys); 1251 } 1252 1253 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1254 void *txd, u32 txd_size) 1255 { 1256 int idx = (txd - ring->dma) / txd_size; 1257 1258 return &ring->buf[idx]; 1259 } 1260 1261 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1262 struct mtk_tx_dma *dma) 1263 { 1264 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1265 } 1266 1267 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1268 { 1269 return (dma - ring->dma) / txd_size; 1270 } 1271 1272 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1273 struct xdp_frame_bulk *bq, bool napi) 1274 { 1275 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1276 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1277 dma_unmap_single(eth->dma_dev, 1278 dma_unmap_addr(tx_buf, dma_addr0), 1279 dma_unmap_len(tx_buf, dma_len0), 1280 DMA_TO_DEVICE); 1281 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1282 dma_unmap_page(eth->dma_dev, 1283 dma_unmap_addr(tx_buf, dma_addr0), 1284 dma_unmap_len(tx_buf, dma_len0), 1285 DMA_TO_DEVICE); 1286 } 1287 } else { 1288 if (dma_unmap_len(tx_buf, dma_len0)) { 1289 dma_unmap_page(eth->dma_dev, 1290 dma_unmap_addr(tx_buf, dma_addr0), 1291 dma_unmap_len(tx_buf, dma_len0), 1292 DMA_TO_DEVICE); 1293 } 1294 1295 if (dma_unmap_len(tx_buf, dma_len1)) { 1296 dma_unmap_page(eth->dma_dev, 1297 dma_unmap_addr(tx_buf, dma_addr1), 1298 dma_unmap_len(tx_buf, dma_len1), 1299 DMA_TO_DEVICE); 1300 } 1301 } 1302 1303 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1304 if (tx_buf->type == MTK_TYPE_SKB) { 1305 struct sk_buff *skb = tx_buf->data; 1306 1307 if (napi) 1308 napi_consume_skb(skb, napi); 1309 else 1310 dev_kfree_skb_any(skb); 1311 } else { 1312 struct xdp_frame *xdpf = tx_buf->data; 1313 1314 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1315 xdp_return_frame_rx_napi(xdpf); 1316 else if (bq) 1317 xdp_return_frame_bulk(xdpf, bq); 1318 else 1319 xdp_return_frame(xdpf); 1320 } 1321 } 1322 tx_buf->flags = 0; 1323 tx_buf->data = NULL; 1324 } 1325 1326 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1327 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1328 size_t size, int idx) 1329 { 1330 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1331 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1332 dma_unmap_len_set(tx_buf, dma_len0, size); 1333 } else { 1334 if (idx & 1) { 1335 txd->txd3 = mapped_addr; 1336 txd->txd2 |= TX_DMA_PLEN1(size); 1337 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1338 dma_unmap_len_set(tx_buf, dma_len1, size); 1339 } else { 1340 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1341 txd->txd1 = mapped_addr; 1342 txd->txd2 = TX_DMA_PLEN0(size); 1343 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1344 dma_unmap_len_set(tx_buf, dma_len0, size); 1345 } 1346 } 1347 } 1348 1349 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1350 struct mtk_tx_dma_desc_info *info) 1351 { 1352 struct mtk_mac *mac = netdev_priv(dev); 1353 struct mtk_eth *eth = mac->hw; 1354 struct mtk_tx_dma *desc = txd; 1355 u32 data; 1356 1357 WRITE_ONCE(desc->txd1, info->addr); 1358 1359 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1360 FIELD_PREP(TX_DMA_PQID, info->qid); 1361 if (info->last) 1362 data |= TX_DMA_LS0; 1363 WRITE_ONCE(desc->txd3, data); 1364 1365 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1366 if (info->first) { 1367 if (info->gso) 1368 data |= TX_DMA_TSO; 1369 /* tx checksum offload */ 1370 if (info->csum) 1371 data |= TX_DMA_CHKSUM; 1372 /* vlan header offload */ 1373 if (info->vlan) 1374 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1375 } 1376 WRITE_ONCE(desc->txd4, data); 1377 } 1378 1379 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1380 struct mtk_tx_dma_desc_info *info) 1381 { 1382 struct mtk_mac *mac = netdev_priv(dev); 1383 struct mtk_tx_dma_v2 *desc = txd; 1384 struct mtk_eth *eth = mac->hw; 1385 u32 data; 1386 1387 WRITE_ONCE(desc->txd1, info->addr); 1388 1389 data = TX_DMA_PLEN0(info->size); 1390 if (info->last) 1391 data |= TX_DMA_LS0; 1392 1393 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 1394 data |= TX_DMA_PREP_ADDR64(info->addr); 1395 1396 WRITE_ONCE(desc->txd3, data); 1397 1398 /* set forward port */ 1399 switch (mac->id) { 1400 case MTK_GMAC1_ID: 1401 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; 1402 break; 1403 case MTK_GMAC2_ID: 1404 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; 1405 break; 1406 case MTK_GMAC3_ID: 1407 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; 1408 break; 1409 } 1410 1411 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1412 WRITE_ONCE(desc->txd4, data); 1413 1414 data = 0; 1415 if (info->first) { 1416 if (info->gso) 1417 data |= TX_DMA_TSO_V2; 1418 /* tx checksum offload */ 1419 if (info->csum) 1420 data |= TX_DMA_CHKSUM_V2; 1421 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) 1422 data |= TX_DMA_SPTAG_V3; 1423 } 1424 WRITE_ONCE(desc->txd5, data); 1425 1426 data = 0; 1427 if (info->first && info->vlan) 1428 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1429 WRITE_ONCE(desc->txd6, data); 1430 1431 WRITE_ONCE(desc->txd7, 0); 1432 WRITE_ONCE(desc->txd8, 0); 1433 } 1434 1435 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1436 struct mtk_tx_dma_desc_info *info) 1437 { 1438 struct mtk_mac *mac = netdev_priv(dev); 1439 struct mtk_eth *eth = mac->hw; 1440 1441 if (mtk_is_netsys_v2_or_greater(eth)) 1442 mtk_tx_set_dma_desc_v2(dev, txd, info); 1443 else 1444 mtk_tx_set_dma_desc_v1(dev, txd, info); 1445 } 1446 1447 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1448 int tx_num, struct mtk_tx_ring *ring, bool gso) 1449 { 1450 struct mtk_tx_dma_desc_info txd_info = { 1451 .size = skb_headlen(skb), 1452 .gso = gso, 1453 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1454 .vlan = skb_vlan_tag_present(skb), 1455 .qid = skb_get_queue_mapping(skb), 1456 .vlan_tci = skb_vlan_tag_get(skb), 1457 .first = true, 1458 .last = !skb_is_nonlinear(skb), 1459 }; 1460 struct netdev_queue *txq; 1461 struct mtk_mac *mac = netdev_priv(dev); 1462 struct mtk_eth *eth = mac->hw; 1463 const struct mtk_soc_data *soc = eth->soc; 1464 struct mtk_tx_dma *itxd, *txd; 1465 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1466 struct mtk_tx_buf *itx_buf, *tx_buf; 1467 int i, n_desc = 1; 1468 int queue = skb_get_queue_mapping(skb); 1469 int k = 0; 1470 1471 txq = netdev_get_tx_queue(dev, queue); 1472 itxd = ring->next_free; 1473 itxd_pdma = qdma_to_pdma(ring, itxd); 1474 if (itxd == ring->last_free) 1475 return -ENOMEM; 1476 1477 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); 1478 memset(itx_buf, 0, sizeof(*itx_buf)); 1479 1480 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1481 DMA_TO_DEVICE); 1482 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1483 return -ENOMEM; 1484 1485 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1486 1487 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1488 itx_buf->mac_id = mac->id; 1489 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1490 k++); 1491 1492 /* TX SG offload */ 1493 txd = itxd; 1494 txd_pdma = qdma_to_pdma(ring, txd); 1495 1496 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1497 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1498 unsigned int offset = 0; 1499 int frag_size = skb_frag_size(frag); 1500 1501 while (frag_size) { 1502 bool new_desc = true; 1503 1504 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1505 (i & 0x1)) { 1506 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1507 txd_pdma = qdma_to_pdma(ring, txd); 1508 if (txd == ring->last_free) 1509 goto err_dma; 1510 1511 n_desc++; 1512 } else { 1513 new_desc = false; 1514 } 1515 1516 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1517 txd_info.size = min_t(unsigned int, frag_size, 1518 soc->tx.dma_max_len); 1519 txd_info.qid = queue; 1520 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1521 !(frag_size - txd_info.size); 1522 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1523 offset, txd_info.size, 1524 DMA_TO_DEVICE); 1525 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1526 goto err_dma; 1527 1528 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1529 1530 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1531 soc->tx.desc_size); 1532 if (new_desc) 1533 memset(tx_buf, 0, sizeof(*tx_buf)); 1534 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1535 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1536 tx_buf->mac_id = mac->id; 1537 1538 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1539 txd_info.size, k++); 1540 1541 frag_size -= txd_info.size; 1542 offset += txd_info.size; 1543 } 1544 } 1545 1546 /* store skb to cleanup */ 1547 itx_buf->type = MTK_TYPE_SKB; 1548 itx_buf->data = skb; 1549 1550 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1551 if (k & 0x1) 1552 txd_pdma->txd2 |= TX_DMA_LS0; 1553 else 1554 txd_pdma->txd2 |= TX_DMA_LS1; 1555 } 1556 1557 netdev_tx_sent_queue(txq, skb->len); 1558 skb_tx_timestamp(skb); 1559 1560 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1561 atomic_sub(n_desc, &ring->free_count); 1562 1563 /* make sure that all changes to the dma ring are flushed before we 1564 * continue 1565 */ 1566 wmb(); 1567 1568 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1569 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1570 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1571 } else { 1572 int next_idx; 1573 1574 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size), 1575 ring->dma_size); 1576 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1577 } 1578 1579 return 0; 1580 1581 err_dma: 1582 do { 1583 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); 1584 1585 /* unmap dma */ 1586 mtk_tx_unmap(eth, tx_buf, NULL, false); 1587 1588 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1589 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1590 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1591 1592 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1593 itxd_pdma = qdma_to_pdma(ring, itxd); 1594 } while (itxd != txd); 1595 1596 return -ENOMEM; 1597 } 1598 1599 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1600 { 1601 int i, nfrags = 1; 1602 skb_frag_t *frag; 1603 1604 if (skb_is_gso(skb)) { 1605 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1606 frag = &skb_shinfo(skb)->frags[i]; 1607 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1608 eth->soc->tx.dma_max_len); 1609 } 1610 } else { 1611 nfrags += skb_shinfo(skb)->nr_frags; 1612 } 1613 1614 return nfrags; 1615 } 1616 1617 static int mtk_queue_stopped(struct mtk_eth *eth) 1618 { 1619 int i; 1620 1621 for (i = 0; i < MTK_MAX_DEVS; i++) { 1622 if (!eth->netdev[i]) 1623 continue; 1624 if (netif_queue_stopped(eth->netdev[i])) 1625 return 1; 1626 } 1627 1628 return 0; 1629 } 1630 1631 static void mtk_wake_queue(struct mtk_eth *eth) 1632 { 1633 int i; 1634 1635 for (i = 0; i < MTK_MAX_DEVS; i++) { 1636 if (!eth->netdev[i]) 1637 continue; 1638 netif_tx_wake_all_queues(eth->netdev[i]); 1639 } 1640 } 1641 1642 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1643 { 1644 struct mtk_mac *mac = netdev_priv(dev); 1645 struct mtk_eth *eth = mac->hw; 1646 struct mtk_tx_ring *ring = ð->tx_ring; 1647 struct net_device_stats *stats = &dev->stats; 1648 bool gso = false; 1649 int tx_num; 1650 1651 /* normally we can rely on the stack not calling this more than once, 1652 * however we have 2 queues running on the same ring so we need to lock 1653 * the ring access 1654 */ 1655 spin_lock(ð->page_lock); 1656 1657 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1658 goto drop; 1659 1660 tx_num = mtk_cal_txd_req(eth, skb); 1661 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1662 netif_tx_stop_all_queues(dev); 1663 netif_err(eth, tx_queued, dev, 1664 "Tx Ring full when queue awake!\n"); 1665 spin_unlock(ð->page_lock); 1666 return NETDEV_TX_BUSY; 1667 } 1668 1669 /* TSO: fill MSS info in tcp checksum field */ 1670 if (skb_is_gso(skb)) { 1671 if (skb_cow_head(skb, 0)) { 1672 netif_warn(eth, tx_err, dev, 1673 "GSO expand head fail.\n"); 1674 goto drop; 1675 } 1676 1677 if (skb_shinfo(skb)->gso_type & 1678 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1679 gso = true; 1680 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1681 } 1682 } 1683 1684 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1685 goto drop; 1686 1687 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1688 netif_tx_stop_all_queues(dev); 1689 1690 spin_unlock(ð->page_lock); 1691 1692 return NETDEV_TX_OK; 1693 1694 drop: 1695 spin_unlock(ð->page_lock); 1696 stats->tx_dropped++; 1697 dev_kfree_skb_any(skb); 1698 return NETDEV_TX_OK; 1699 } 1700 1701 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1702 { 1703 int i; 1704 struct mtk_rx_ring *ring; 1705 int idx; 1706 1707 if (!eth->hwlro) 1708 return ð->rx_ring[0]; 1709 1710 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1711 struct mtk_rx_dma *rxd; 1712 1713 ring = ð->rx_ring[i]; 1714 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1715 rxd = ring->dma + idx * eth->soc->rx.desc_size; 1716 if (rxd->rxd2 & RX_DMA_DONE) { 1717 ring->calc_idx_update = true; 1718 return ring; 1719 } 1720 } 1721 1722 return NULL; 1723 } 1724 1725 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1726 { 1727 struct mtk_rx_ring *ring; 1728 int i; 1729 1730 if (!eth->hwlro) { 1731 ring = ð->rx_ring[0]; 1732 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1733 } else { 1734 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1735 ring = ð->rx_ring[i]; 1736 if (ring->calc_idx_update) { 1737 ring->calc_idx_update = false; 1738 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1739 } 1740 } 1741 } 1742 } 1743 1744 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1745 { 1746 return mtk_is_netsys_v2_or_greater(eth); 1747 } 1748 1749 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1750 struct xdp_rxq_info *xdp_q, 1751 int id, int size) 1752 { 1753 struct page_pool_params pp_params = { 1754 .order = 0, 1755 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1756 .pool_size = size, 1757 .nid = NUMA_NO_NODE, 1758 .dev = eth->dma_dev, 1759 .offset = MTK_PP_HEADROOM, 1760 .max_len = MTK_PP_MAX_BUF_SIZE, 1761 }; 1762 struct page_pool *pp; 1763 int err; 1764 1765 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1766 : DMA_FROM_DEVICE; 1767 pp = page_pool_create(&pp_params); 1768 if (IS_ERR(pp)) 1769 return pp; 1770 1771 err = __xdp_rxq_info_reg(xdp_q, eth->dummy_dev, id, 1772 eth->rx_napi.napi_id, PAGE_SIZE); 1773 if (err < 0) 1774 goto err_free_pp; 1775 1776 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1777 if (err) 1778 goto err_unregister_rxq; 1779 1780 return pp; 1781 1782 err_unregister_rxq: 1783 xdp_rxq_info_unreg(xdp_q); 1784 err_free_pp: 1785 page_pool_destroy(pp); 1786 1787 return ERR_PTR(err); 1788 } 1789 1790 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1791 gfp_t gfp_mask) 1792 { 1793 struct page *page; 1794 1795 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1796 if (!page) 1797 return NULL; 1798 1799 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1800 return page_address(page); 1801 } 1802 1803 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1804 { 1805 if (ring->page_pool) 1806 page_pool_put_full_page(ring->page_pool, 1807 virt_to_head_page(data), napi); 1808 else 1809 skb_free_frag(data); 1810 } 1811 1812 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1813 struct mtk_tx_dma_desc_info *txd_info, 1814 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1815 void *data, u16 headroom, int index, bool dma_map) 1816 { 1817 struct mtk_tx_ring *ring = ð->tx_ring; 1818 struct mtk_mac *mac = netdev_priv(dev); 1819 struct mtk_tx_dma *txd_pdma; 1820 1821 if (dma_map) { /* ndo_xdp_xmit */ 1822 txd_info->addr = dma_map_single(eth->dma_dev, data, 1823 txd_info->size, DMA_TO_DEVICE); 1824 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1825 return -ENOMEM; 1826 1827 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1828 } else { 1829 struct page *page = virt_to_head_page(data); 1830 1831 txd_info->addr = page_pool_get_dma_addr(page) + 1832 sizeof(struct xdp_frame) + headroom; 1833 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1834 txd_info->size, DMA_BIDIRECTIONAL); 1835 } 1836 mtk_tx_set_dma_desc(dev, txd, txd_info); 1837 1838 tx_buf->mac_id = mac->id; 1839 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1840 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1841 1842 txd_pdma = qdma_to_pdma(ring, txd); 1843 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1844 index); 1845 1846 return 0; 1847 } 1848 1849 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1850 struct net_device *dev, bool dma_map) 1851 { 1852 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1853 const struct mtk_soc_data *soc = eth->soc; 1854 struct mtk_tx_ring *ring = ð->tx_ring; 1855 struct mtk_mac *mac = netdev_priv(dev); 1856 struct mtk_tx_dma_desc_info txd_info = { 1857 .size = xdpf->len, 1858 .first = true, 1859 .last = !xdp_frame_has_frags(xdpf), 1860 .qid = mac->id, 1861 }; 1862 int err, index = 0, n_desc = 1, nr_frags; 1863 struct mtk_tx_buf *htx_buf, *tx_buf; 1864 struct mtk_tx_dma *htxd, *txd; 1865 void *data = xdpf->data; 1866 1867 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1868 return -EBUSY; 1869 1870 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1871 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1872 return -EBUSY; 1873 1874 spin_lock(ð->page_lock); 1875 1876 txd = ring->next_free; 1877 if (txd == ring->last_free) { 1878 spin_unlock(ð->page_lock); 1879 return -ENOMEM; 1880 } 1881 htxd = txd; 1882 1883 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size); 1884 memset(tx_buf, 0, sizeof(*tx_buf)); 1885 htx_buf = tx_buf; 1886 1887 for (;;) { 1888 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1889 data, xdpf->headroom, index, dma_map); 1890 if (err < 0) 1891 goto unmap; 1892 1893 if (txd_info.last) 1894 break; 1895 1896 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1897 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1898 if (txd == ring->last_free) 1899 goto unmap; 1900 1901 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1902 soc->tx.desc_size); 1903 memset(tx_buf, 0, sizeof(*tx_buf)); 1904 n_desc++; 1905 } 1906 1907 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1908 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1909 txd_info.last = index + 1 == nr_frags; 1910 txd_info.qid = mac->id; 1911 data = skb_frag_address(&sinfo->frags[index]); 1912 1913 index++; 1914 } 1915 /* store xdpf for cleanup */ 1916 htx_buf->data = xdpf; 1917 1918 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1919 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1920 1921 if (index & 1) 1922 txd_pdma->txd2 |= TX_DMA_LS0; 1923 else 1924 txd_pdma->txd2 |= TX_DMA_LS1; 1925 } 1926 1927 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1928 atomic_sub(n_desc, &ring->free_count); 1929 1930 /* make sure that all changes to the dma ring are flushed before we 1931 * continue 1932 */ 1933 wmb(); 1934 1935 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1936 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1937 } else { 1938 int idx; 1939 1940 idx = txd_to_idx(ring, txd, soc->tx.desc_size); 1941 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1942 MT7628_TX_CTX_IDX0); 1943 } 1944 1945 spin_unlock(ð->page_lock); 1946 1947 return 0; 1948 1949 unmap: 1950 while (htxd != txd) { 1951 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size); 1952 mtk_tx_unmap(eth, tx_buf, NULL, false); 1953 1954 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1955 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1956 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1957 1958 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1959 } 1960 1961 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1962 } 1963 1964 spin_unlock(ð->page_lock); 1965 1966 return err; 1967 } 1968 1969 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1970 struct xdp_frame **frames, u32 flags) 1971 { 1972 struct mtk_mac *mac = netdev_priv(dev); 1973 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1974 struct mtk_eth *eth = mac->hw; 1975 int i, nxmit = 0; 1976 1977 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1978 return -EINVAL; 1979 1980 for (i = 0; i < num_frame; i++) { 1981 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1982 break; 1983 nxmit++; 1984 } 1985 1986 u64_stats_update_begin(&hw_stats->syncp); 1987 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1988 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1989 u64_stats_update_end(&hw_stats->syncp); 1990 1991 return nxmit; 1992 } 1993 1994 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1995 struct xdp_buff *xdp, struct net_device *dev) 1996 { 1997 struct mtk_mac *mac = netdev_priv(dev); 1998 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1999 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 2000 struct bpf_prog *prog; 2001 u32 act = XDP_PASS; 2002 2003 rcu_read_lock(); 2004 2005 prog = rcu_dereference(eth->prog); 2006 if (!prog) 2007 goto out; 2008 2009 act = bpf_prog_run_xdp(prog, xdp); 2010 switch (act) { 2011 case XDP_PASS: 2012 count = &hw_stats->xdp_stats.rx_xdp_pass; 2013 goto update_stats; 2014 case XDP_REDIRECT: 2015 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 2016 act = XDP_DROP; 2017 break; 2018 } 2019 2020 count = &hw_stats->xdp_stats.rx_xdp_redirect; 2021 goto update_stats; 2022 case XDP_TX: { 2023 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2024 2025 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 2026 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 2027 act = XDP_DROP; 2028 break; 2029 } 2030 2031 count = &hw_stats->xdp_stats.rx_xdp_tx; 2032 goto update_stats; 2033 } 2034 default: 2035 bpf_warn_invalid_xdp_action(dev, prog, act); 2036 fallthrough; 2037 case XDP_ABORTED: 2038 trace_xdp_exception(dev, prog, act); 2039 fallthrough; 2040 case XDP_DROP: 2041 break; 2042 } 2043 2044 page_pool_put_full_page(ring->page_pool, 2045 virt_to_head_page(xdp->data), true); 2046 2047 update_stats: 2048 u64_stats_update_begin(&hw_stats->syncp); 2049 *count = *count + 1; 2050 u64_stats_update_end(&hw_stats->syncp); 2051 out: 2052 rcu_read_unlock(); 2053 2054 return act; 2055 } 2056 2057 static int mtk_poll_rx(struct napi_struct *napi, int budget, 2058 struct mtk_eth *eth) 2059 { 2060 struct dim_sample dim_sample = {}; 2061 struct mtk_rx_ring *ring; 2062 bool xdp_flush = false; 2063 int idx; 2064 struct sk_buff *skb; 2065 u64 addr64 = 0; 2066 u8 *data, *new_data; 2067 struct mtk_rx_dma_v2 *rxd, trxd; 2068 int done = 0, bytes = 0; 2069 dma_addr_t dma_addr = DMA_MAPPING_ERROR; 2070 int ppe_idx = 0; 2071 2072 while (done < budget) { 2073 unsigned int pktlen, *rxdcsum; 2074 struct net_device *netdev; 2075 u32 hash, reason; 2076 int mac = 0; 2077 2078 ring = mtk_get_rx_ring(eth); 2079 if (unlikely(!ring)) 2080 goto rx_done; 2081 2082 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 2083 rxd = ring->dma + idx * eth->soc->rx.desc_size; 2084 data = ring->data[idx]; 2085 2086 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 2087 break; 2088 2089 /* find out which mac the packet come from. values start at 1 */ 2090 if (mtk_is_netsys_v3_or_greater(eth)) { 2091 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); 2092 2093 switch (val) { 2094 case PSE_GDM1_PORT: 2095 case PSE_GDM2_PORT: 2096 mac = val - 1; 2097 break; 2098 case PSE_GDM3_PORT: 2099 mac = MTK_GMAC3_ID; 2100 break; 2101 default: 2102 break; 2103 } 2104 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 2105 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { 2106 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 2107 } 2108 2109 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || 2110 !eth->netdev[mac])) 2111 goto release_desc; 2112 2113 netdev = eth->netdev[mac]; 2114 ppe_idx = eth->mac[mac]->ppe_idx; 2115 2116 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 2117 goto release_desc; 2118 2119 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 2120 2121 /* alloc new buffer */ 2122 if (ring->page_pool) { 2123 struct page *page = virt_to_head_page(data); 2124 struct xdp_buff xdp; 2125 u32 ret; 2126 2127 new_data = mtk_page_pool_get_buff(ring->page_pool, 2128 &dma_addr, 2129 GFP_ATOMIC); 2130 if (unlikely(!new_data)) { 2131 netdev->stats.rx_dropped++; 2132 goto release_desc; 2133 } 2134 2135 dma_sync_single_for_cpu(eth->dma_dev, 2136 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 2137 pktlen, page_pool_get_dma_dir(ring->page_pool)); 2138 2139 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 2140 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 2141 false); 2142 xdp_buff_clear_frags_flag(&xdp); 2143 2144 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 2145 if (ret == XDP_REDIRECT) 2146 xdp_flush = true; 2147 2148 if (ret != XDP_PASS) 2149 goto skip_rx; 2150 2151 skb = build_skb(data, PAGE_SIZE); 2152 if (unlikely(!skb)) { 2153 page_pool_put_full_page(ring->page_pool, 2154 page, true); 2155 netdev->stats.rx_dropped++; 2156 goto skip_rx; 2157 } 2158 2159 skb_reserve(skb, xdp.data - xdp.data_hard_start); 2160 skb_put(skb, xdp.data_end - xdp.data); 2161 skb_mark_for_recycle(skb); 2162 } else { 2163 if (ring->frag_size <= PAGE_SIZE) 2164 new_data = napi_alloc_frag(ring->frag_size); 2165 else 2166 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2167 2168 if (unlikely(!new_data)) { 2169 netdev->stats.rx_dropped++; 2170 goto release_desc; 2171 } 2172 2173 dma_addr = dma_map_single(eth->dma_dev, 2174 new_data + NET_SKB_PAD + eth->ip_align, 2175 ring->buf_size, DMA_FROM_DEVICE); 2176 if (unlikely(dma_mapping_error(eth->dma_dev, 2177 dma_addr))) { 2178 skb_free_frag(new_data); 2179 netdev->stats.rx_dropped++; 2180 goto release_desc; 2181 } 2182 2183 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2184 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2); 2185 2186 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), 2187 ring->buf_size, DMA_FROM_DEVICE); 2188 2189 skb = build_skb(data, ring->frag_size); 2190 if (unlikely(!skb)) { 2191 netdev->stats.rx_dropped++; 2192 skb_free_frag(data); 2193 goto skip_rx; 2194 } 2195 2196 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2197 skb_put(skb, pktlen); 2198 } 2199 2200 skb->dev = netdev; 2201 bytes += skb->len; 2202 2203 if (mtk_is_netsys_v3_or_greater(eth)) { 2204 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2205 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2206 if (hash != MTK_RXD5_FOE_ENTRY) 2207 skb_set_hash(skb, jhash_1word(hash, 0), 2208 PKT_HASH_TYPE_L4); 2209 rxdcsum = &trxd.rxd3; 2210 } else { 2211 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2212 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2213 if (hash != MTK_RXD4_FOE_ENTRY) 2214 skb_set_hash(skb, jhash_1word(hash, 0), 2215 PKT_HASH_TYPE_L4); 2216 rxdcsum = &trxd.rxd4; 2217 } 2218 2219 if (*rxdcsum & eth->soc->rx.dma_l4_valid) 2220 skb->ip_summed = CHECKSUM_UNNECESSARY; 2221 else 2222 skb_checksum_none_assert(skb); 2223 skb->protocol = eth_type_trans(skb, netdev); 2224 2225 /* When using VLAN untagging in combination with DSA, the 2226 * hardware treats the MTK special tag as a VLAN and untags it. 2227 */ 2228 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && 2229 netdev_uses_dsa(netdev)) { 2230 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 2231 2232 if (port < ARRAY_SIZE(eth->dsa_meta) && 2233 eth->dsa_meta[port]) 2234 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2235 } 2236 2237 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2238 mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash); 2239 2240 skb_record_rx_queue(skb, 0); 2241 napi_gro_receive(napi, skb); 2242 2243 skip_rx: 2244 ring->data[idx] = new_data; 2245 rxd->rxd1 = (unsigned int)dma_addr; 2246 release_desc: 2247 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2248 rxd->rxd2 = RX_DMA_LSO; 2249 else 2250 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2251 2252 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA) && 2253 likely(dma_addr != DMA_MAPPING_ERROR)) 2254 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2255 2256 ring->calc_idx = idx; 2257 done++; 2258 } 2259 2260 rx_done: 2261 if (done) { 2262 /* make sure that all changes to the dma ring are flushed before 2263 * we continue 2264 */ 2265 wmb(); 2266 mtk_update_rx_cpu_idx(eth); 2267 } 2268 2269 eth->rx_packets += done; 2270 eth->rx_bytes += bytes; 2271 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2272 &dim_sample); 2273 net_dim(ð->rx_dim, &dim_sample); 2274 2275 if (xdp_flush) 2276 xdp_do_flush(); 2277 2278 return done; 2279 } 2280 2281 struct mtk_poll_state { 2282 struct netdev_queue *txq; 2283 unsigned int total; 2284 unsigned int done; 2285 unsigned int bytes; 2286 }; 2287 2288 static void 2289 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2290 struct sk_buff *skb) 2291 { 2292 struct netdev_queue *txq; 2293 struct net_device *dev; 2294 unsigned int bytes = skb->len; 2295 2296 state->total++; 2297 eth->tx_packets++; 2298 eth->tx_bytes += bytes; 2299 2300 dev = eth->netdev[mac]; 2301 if (!dev) 2302 return; 2303 2304 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2305 if (state->txq == txq) { 2306 state->done++; 2307 state->bytes += bytes; 2308 return; 2309 } 2310 2311 if (state->txq) 2312 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2313 2314 state->txq = txq; 2315 state->done = 1; 2316 state->bytes = bytes; 2317 } 2318 2319 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2320 struct mtk_poll_state *state) 2321 { 2322 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2323 struct mtk_tx_ring *ring = ð->tx_ring; 2324 struct mtk_tx_buf *tx_buf; 2325 struct xdp_frame_bulk bq; 2326 struct mtk_tx_dma *desc; 2327 u32 cpu, dma; 2328 2329 cpu = ring->last_free_ptr; 2330 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2331 2332 desc = mtk_qdma_phys_to_virt(ring, cpu); 2333 xdp_frame_bulk_init(&bq); 2334 2335 while ((cpu != dma) && budget) { 2336 u32 next_cpu = desc->txd2; 2337 2338 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2339 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2340 break; 2341 2342 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2343 eth->soc->tx.desc_size); 2344 if (!tx_buf->data) 2345 break; 2346 2347 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2348 if (tx_buf->type == MTK_TYPE_SKB) 2349 mtk_poll_tx_done(eth, state, tx_buf->mac_id, 2350 tx_buf->data); 2351 2352 budget--; 2353 } 2354 mtk_tx_unmap(eth, tx_buf, &bq, true); 2355 2356 ring->last_free = desc; 2357 atomic_inc(&ring->free_count); 2358 2359 cpu = next_cpu; 2360 } 2361 xdp_flush_frame_bulk(&bq); 2362 2363 ring->last_free_ptr = cpu; 2364 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2365 2366 return budget; 2367 } 2368 2369 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2370 struct mtk_poll_state *state) 2371 { 2372 struct mtk_tx_ring *ring = ð->tx_ring; 2373 struct mtk_tx_buf *tx_buf; 2374 struct xdp_frame_bulk bq; 2375 struct mtk_tx_dma *desc; 2376 u32 cpu, dma; 2377 2378 cpu = ring->cpu_idx; 2379 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2380 xdp_frame_bulk_init(&bq); 2381 2382 while ((cpu != dma) && budget) { 2383 tx_buf = &ring->buf[cpu]; 2384 if (!tx_buf->data) 2385 break; 2386 2387 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2388 if (tx_buf->type == MTK_TYPE_SKB) 2389 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2390 budget--; 2391 } 2392 mtk_tx_unmap(eth, tx_buf, &bq, true); 2393 2394 desc = ring->dma + cpu * eth->soc->tx.desc_size; 2395 ring->last_free = desc; 2396 atomic_inc(&ring->free_count); 2397 2398 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2399 } 2400 xdp_flush_frame_bulk(&bq); 2401 2402 ring->cpu_idx = cpu; 2403 2404 return budget; 2405 } 2406 2407 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2408 { 2409 struct mtk_tx_ring *ring = ð->tx_ring; 2410 struct dim_sample dim_sample = {}; 2411 struct mtk_poll_state state = {}; 2412 2413 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2414 budget = mtk_poll_tx_qdma(eth, budget, &state); 2415 else 2416 budget = mtk_poll_tx_pdma(eth, budget, &state); 2417 2418 if (state.txq) 2419 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2420 2421 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2422 &dim_sample); 2423 net_dim(ð->tx_dim, &dim_sample); 2424 2425 if (mtk_queue_stopped(eth) && 2426 (atomic_read(&ring->free_count) > ring->thresh)) 2427 mtk_wake_queue(eth); 2428 2429 return state.total; 2430 } 2431 2432 static void mtk_handle_status_irq(struct mtk_eth *eth) 2433 { 2434 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2435 2436 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2437 mtk_stats_update(eth); 2438 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2439 MTK_INT_STATUS2); 2440 } 2441 } 2442 2443 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2444 { 2445 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2446 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2447 int tx_done = 0; 2448 2449 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2450 mtk_handle_status_irq(eth); 2451 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2452 tx_done = mtk_poll_tx(eth, budget); 2453 2454 if (unlikely(netif_msg_intr(eth))) { 2455 dev_info(eth->dev, 2456 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2457 mtk_r32(eth, reg_map->tx_irq_status), 2458 mtk_r32(eth, reg_map->tx_irq_mask)); 2459 } 2460 2461 if (tx_done == budget) 2462 return budget; 2463 2464 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2465 return budget; 2466 2467 if (napi_complete_done(napi, tx_done)) 2468 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2469 2470 return tx_done; 2471 } 2472 2473 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2474 { 2475 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2476 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2477 int rx_done_total = 0; 2478 2479 mtk_handle_status_irq(eth); 2480 2481 do { 2482 int rx_done; 2483 2484 mtk_w32(eth, eth->soc->rx.irq_done_mask, 2485 reg_map->pdma.irq_status); 2486 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2487 rx_done_total += rx_done; 2488 2489 if (unlikely(netif_msg_intr(eth))) { 2490 dev_info(eth->dev, 2491 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2492 mtk_r32(eth, reg_map->pdma.irq_status), 2493 mtk_r32(eth, reg_map->pdma.irq_mask)); 2494 } 2495 2496 if (rx_done_total == budget) 2497 return budget; 2498 2499 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2500 eth->soc->rx.irq_done_mask); 2501 2502 if (napi_complete_done(napi, rx_done_total)) 2503 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); 2504 2505 return rx_done_total; 2506 } 2507 2508 static int mtk_tx_alloc(struct mtk_eth *eth) 2509 { 2510 const struct mtk_soc_data *soc = eth->soc; 2511 struct mtk_tx_ring *ring = ð->tx_ring; 2512 int i, sz = soc->tx.desc_size; 2513 struct mtk_tx_dma_v2 *txd; 2514 int ring_size; 2515 u32 ofs, val; 2516 2517 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2518 ring_size = MTK_QDMA_RING_SIZE; 2519 else 2520 ring_size = soc->tx.dma_size; 2521 2522 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2523 GFP_KERNEL); 2524 if (!ring->buf) 2525 goto no_tx_mem; 2526 2527 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { 2528 ring->dma = eth->sram_base + soc->tx.fq_dma_size * sz; 2529 ring->phys = eth->phy_scratch_ring + soc->tx.fq_dma_size * (dma_addr_t)sz; 2530 } else { 2531 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2532 &ring->phys, GFP_KERNEL); 2533 } 2534 2535 if (!ring->dma) 2536 goto no_tx_mem; 2537 2538 for (i = 0; i < ring_size; i++) { 2539 int next = (i + 1) % ring_size; 2540 u32 next_ptr = ring->phys + next * sz; 2541 2542 txd = ring->dma + i * sz; 2543 txd->txd2 = next_ptr; 2544 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2545 txd->txd4 = 0; 2546 if (mtk_is_netsys_v2_or_greater(eth)) { 2547 txd->txd5 = 0; 2548 txd->txd6 = 0; 2549 txd->txd7 = 0; 2550 txd->txd8 = 0; 2551 } 2552 } 2553 2554 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2555 * only as the framework. The real HW descriptors are the PDMA 2556 * descriptors in ring->dma_pdma. 2557 */ 2558 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2559 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2560 &ring->phys_pdma, GFP_KERNEL); 2561 if (!ring->dma_pdma) 2562 goto no_tx_mem; 2563 2564 for (i = 0; i < ring_size; i++) { 2565 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2566 ring->dma_pdma[i].txd4 = 0; 2567 } 2568 } 2569 2570 ring->dma_size = ring_size; 2571 atomic_set(&ring->free_count, ring_size - 2); 2572 ring->next_free = ring->dma; 2573 ring->last_free = (void *)txd; 2574 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2575 ring->thresh = MAX_SKB_FRAGS; 2576 2577 /* make sure that all changes to the dma ring are flushed before we 2578 * continue 2579 */ 2580 wmb(); 2581 2582 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2583 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2584 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2585 mtk_w32(eth, 2586 ring->phys + ((ring_size - 1) * sz), 2587 soc->reg_map->qdma.crx_ptr); 2588 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2589 2590 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2591 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2592 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2593 2594 val = MTK_QTX_SCH_MIN_RATE_EN | 2595 /* minimum: 10 Mbps */ 2596 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2597 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2598 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2599 if (mtk_is_netsys_v1(eth)) 2600 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2601 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2602 ofs += MTK_QTX_OFFSET; 2603 } 2604 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2605 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2606 if (mtk_is_netsys_v2_or_greater(eth)) 2607 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2608 } else { 2609 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2610 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2611 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2612 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2613 } 2614 2615 return 0; 2616 2617 no_tx_mem: 2618 return -ENOMEM; 2619 } 2620 2621 static void mtk_tx_clean(struct mtk_eth *eth) 2622 { 2623 const struct mtk_soc_data *soc = eth->soc; 2624 struct mtk_tx_ring *ring = ð->tx_ring; 2625 int i; 2626 2627 if (ring->buf) { 2628 for (i = 0; i < ring->dma_size; i++) 2629 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2630 kfree(ring->buf); 2631 ring->buf = NULL; 2632 } 2633 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { 2634 dma_free_coherent(eth->dma_dev, 2635 ring->dma_size * soc->tx.desc_size, 2636 ring->dma, ring->phys); 2637 ring->dma = NULL; 2638 } 2639 2640 if (ring->dma_pdma) { 2641 dma_free_coherent(eth->dma_dev, 2642 ring->dma_size * soc->tx.desc_size, 2643 ring->dma_pdma, ring->phys_pdma); 2644 ring->dma_pdma = NULL; 2645 } 2646 } 2647 2648 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2649 { 2650 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2651 const struct mtk_soc_data *soc = eth->soc; 2652 struct mtk_rx_ring *ring; 2653 int rx_data_len, rx_dma_size, tx_ring_size; 2654 int i; 2655 2656 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2657 tx_ring_size = MTK_QDMA_RING_SIZE; 2658 else 2659 tx_ring_size = soc->tx.dma_size; 2660 2661 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2662 if (ring_no) 2663 return -EINVAL; 2664 ring = ð->rx_ring_qdma; 2665 } else { 2666 ring = ð->rx_ring[ring_no]; 2667 } 2668 2669 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2670 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2671 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2672 } else { 2673 rx_data_len = ETH_DATA_LEN; 2674 rx_dma_size = soc->rx.dma_size; 2675 } 2676 2677 ring->frag_size = mtk_max_frag_size(rx_data_len); 2678 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2679 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2680 GFP_KERNEL); 2681 if (!ring->data) 2682 return -ENOMEM; 2683 2684 if (mtk_page_pool_enabled(eth)) { 2685 struct page_pool *pp; 2686 2687 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2688 rx_dma_size); 2689 if (IS_ERR(pp)) 2690 return PTR_ERR(pp); 2691 2692 ring->page_pool = pp; 2693 } 2694 2695 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || 2696 rx_flag != MTK_RX_FLAGS_NORMAL) { 2697 ring->dma = dma_alloc_coherent(eth->dma_dev, 2698 rx_dma_size * eth->soc->rx.desc_size, 2699 &ring->phys, GFP_KERNEL); 2700 } else { 2701 struct mtk_tx_ring *tx_ring = ð->tx_ring; 2702 2703 ring->dma = tx_ring->dma + tx_ring_size * 2704 eth->soc->tx.desc_size * (ring_no + 1); 2705 ring->phys = tx_ring->phys + tx_ring_size * 2706 eth->soc->tx.desc_size * (ring_no + 1); 2707 } 2708 2709 if (!ring->dma) 2710 return -ENOMEM; 2711 2712 for (i = 0; i < rx_dma_size; i++) { 2713 struct mtk_rx_dma_v2 *rxd; 2714 dma_addr_t dma_addr; 2715 void *data; 2716 2717 rxd = ring->dma + i * eth->soc->rx.desc_size; 2718 if (ring->page_pool) { 2719 data = mtk_page_pool_get_buff(ring->page_pool, 2720 &dma_addr, GFP_KERNEL); 2721 if (!data) 2722 return -ENOMEM; 2723 } else { 2724 if (ring->frag_size <= PAGE_SIZE) 2725 data = netdev_alloc_frag(ring->frag_size); 2726 else 2727 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2728 2729 if (!data) 2730 return -ENOMEM; 2731 2732 dma_addr = dma_map_single(eth->dma_dev, 2733 data + NET_SKB_PAD + eth->ip_align, 2734 ring->buf_size, DMA_FROM_DEVICE); 2735 if (unlikely(dma_mapping_error(eth->dma_dev, 2736 dma_addr))) { 2737 skb_free_frag(data); 2738 return -ENOMEM; 2739 } 2740 } 2741 rxd->rxd1 = (unsigned int)dma_addr; 2742 ring->data[i] = data; 2743 2744 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2745 rxd->rxd2 = RX_DMA_LSO; 2746 else 2747 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2748 2749 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2750 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2751 2752 rxd->rxd3 = 0; 2753 rxd->rxd4 = 0; 2754 if (mtk_is_netsys_v3_or_greater(eth)) { 2755 rxd->rxd5 = 0; 2756 rxd->rxd6 = 0; 2757 rxd->rxd7 = 0; 2758 rxd->rxd8 = 0; 2759 } 2760 } 2761 2762 ring->dma_size = rx_dma_size; 2763 ring->calc_idx_update = false; 2764 ring->calc_idx = rx_dma_size - 1; 2765 if (rx_flag == MTK_RX_FLAGS_QDMA) 2766 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2767 ring_no * MTK_QRX_OFFSET; 2768 else 2769 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2770 ring_no * MTK_QRX_OFFSET; 2771 /* make sure that all changes to the dma ring are flushed before we 2772 * continue 2773 */ 2774 wmb(); 2775 2776 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2777 mtk_w32(eth, ring->phys, 2778 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2779 mtk_w32(eth, rx_dma_size, 2780 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2781 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2782 reg_map->qdma.rst_idx); 2783 } else { 2784 mtk_w32(eth, ring->phys, 2785 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2786 mtk_w32(eth, rx_dma_size, 2787 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2788 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2789 reg_map->pdma.rst_idx); 2790 } 2791 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2792 2793 return 0; 2794 } 2795 2796 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) 2797 { 2798 u64 addr64 = 0; 2799 int i; 2800 2801 if (ring->data && ring->dma) { 2802 for (i = 0; i < ring->dma_size; i++) { 2803 struct mtk_rx_dma *rxd; 2804 2805 if (!ring->data[i]) 2806 continue; 2807 2808 rxd = ring->dma + i * eth->soc->rx.desc_size; 2809 if (!rxd->rxd1) 2810 continue; 2811 2812 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2813 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); 2814 2815 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), 2816 ring->buf_size, DMA_FROM_DEVICE); 2817 mtk_rx_put_buff(ring, ring->data[i], false); 2818 } 2819 kfree(ring->data); 2820 ring->data = NULL; 2821 } 2822 2823 if (!in_sram && ring->dma) { 2824 dma_free_coherent(eth->dma_dev, 2825 ring->dma_size * eth->soc->rx.desc_size, 2826 ring->dma, ring->phys); 2827 ring->dma = NULL; 2828 } 2829 2830 if (ring->page_pool) { 2831 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2832 xdp_rxq_info_unreg(&ring->xdp_q); 2833 page_pool_destroy(ring->page_pool); 2834 ring->page_pool = NULL; 2835 } 2836 } 2837 2838 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2839 { 2840 int i; 2841 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2842 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2843 2844 /* set LRO rings to auto-learn modes */ 2845 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2846 2847 /* validate LRO ring */ 2848 ring_ctrl_dw2 |= MTK_RING_VLD; 2849 2850 /* set AGE timer (unit: 20us) */ 2851 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2852 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2853 2854 /* set max AGG timer (unit: 20us) */ 2855 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2856 2857 /* set max LRO AGG count */ 2858 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2859 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2860 2861 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2862 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2863 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2864 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2865 } 2866 2867 /* IPv4 checksum update enable */ 2868 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2869 2870 /* switch priority comparison to packet count mode */ 2871 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2872 2873 /* bandwidth threshold setting */ 2874 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2875 2876 /* auto-learn score delta setting */ 2877 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2878 2879 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2880 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2881 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2882 2883 /* set HW LRO mode & the max aggregation count for rx packets */ 2884 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2885 2886 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2887 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2888 2889 /* enable HW LRO */ 2890 lro_ctrl_dw0 |= MTK_LRO_EN; 2891 2892 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2893 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2894 2895 return 0; 2896 } 2897 2898 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2899 { 2900 int i; 2901 u32 val; 2902 2903 /* relinquish lro rings, flush aggregated packets */ 2904 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2905 2906 /* wait for relinquishments done */ 2907 for (i = 0; i < 10; i++) { 2908 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2909 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2910 msleep(20); 2911 continue; 2912 } 2913 break; 2914 } 2915 2916 /* invalidate lro rings */ 2917 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2918 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2919 2920 /* disable HW LRO */ 2921 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2922 } 2923 2924 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2925 { 2926 u32 reg_val; 2927 2928 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2929 2930 /* invalidate the IP setting */ 2931 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2932 2933 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2934 2935 /* validate the IP setting */ 2936 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2937 } 2938 2939 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2940 { 2941 u32 reg_val; 2942 2943 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2944 2945 /* invalidate the IP setting */ 2946 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2947 2948 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2949 } 2950 2951 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2952 { 2953 int cnt = 0; 2954 int i; 2955 2956 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2957 if (mac->hwlro_ip[i]) 2958 cnt++; 2959 } 2960 2961 return cnt; 2962 } 2963 2964 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2965 struct ethtool_rxnfc *cmd) 2966 { 2967 struct ethtool_rx_flow_spec *fsp = 2968 (struct ethtool_rx_flow_spec *)&cmd->fs; 2969 struct mtk_mac *mac = netdev_priv(dev); 2970 struct mtk_eth *eth = mac->hw; 2971 int hwlro_idx; 2972 2973 if ((fsp->flow_type != TCP_V4_FLOW) || 2974 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2975 (fsp->location > 1)) 2976 return -EINVAL; 2977 2978 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2979 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2980 2981 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2982 2983 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2984 2985 return 0; 2986 } 2987 2988 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2989 struct ethtool_rxnfc *cmd) 2990 { 2991 struct ethtool_rx_flow_spec *fsp = 2992 (struct ethtool_rx_flow_spec *)&cmd->fs; 2993 struct mtk_mac *mac = netdev_priv(dev); 2994 struct mtk_eth *eth = mac->hw; 2995 int hwlro_idx; 2996 2997 if (fsp->location > 1) 2998 return -EINVAL; 2999 3000 mac->hwlro_ip[fsp->location] = 0; 3001 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 3002 3003 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3004 3005 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 3006 3007 return 0; 3008 } 3009 3010 static void mtk_hwlro_netdev_disable(struct net_device *dev) 3011 { 3012 struct mtk_mac *mac = netdev_priv(dev); 3013 struct mtk_eth *eth = mac->hw; 3014 int i, hwlro_idx; 3015 3016 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 3017 mac->hwlro_ip[i] = 0; 3018 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 3019 3020 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 3021 } 3022 3023 mac->hwlro_ip_cnt = 0; 3024 } 3025 3026 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 3027 struct ethtool_rxnfc *cmd) 3028 { 3029 struct mtk_mac *mac = netdev_priv(dev); 3030 struct ethtool_rx_flow_spec *fsp = 3031 (struct ethtool_rx_flow_spec *)&cmd->fs; 3032 3033 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 3034 return -EINVAL; 3035 3036 /* only tcp dst ipv4 is meaningful, others are meaningless */ 3037 fsp->flow_type = TCP_V4_FLOW; 3038 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 3039 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 3040 3041 fsp->h_u.tcp_ip4_spec.ip4src = 0; 3042 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 3043 fsp->h_u.tcp_ip4_spec.psrc = 0; 3044 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 3045 fsp->h_u.tcp_ip4_spec.pdst = 0; 3046 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 3047 fsp->h_u.tcp_ip4_spec.tos = 0; 3048 fsp->m_u.tcp_ip4_spec.tos = 0xff; 3049 3050 return 0; 3051 } 3052 3053 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 3054 struct ethtool_rxnfc *cmd, 3055 u32 *rule_locs) 3056 { 3057 struct mtk_mac *mac = netdev_priv(dev); 3058 int cnt = 0; 3059 int i; 3060 3061 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 3062 if (cnt == cmd->rule_cnt) 3063 return -EMSGSIZE; 3064 3065 if (mac->hwlro_ip[i]) { 3066 rule_locs[cnt] = i; 3067 cnt++; 3068 } 3069 } 3070 3071 cmd->rule_cnt = cnt; 3072 3073 return 0; 3074 } 3075 3076 static netdev_features_t mtk_fix_features(struct net_device *dev, 3077 netdev_features_t features) 3078 { 3079 if (!(features & NETIF_F_LRO)) { 3080 struct mtk_mac *mac = netdev_priv(dev); 3081 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3082 3083 if (ip_cnt) { 3084 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 3085 3086 features |= NETIF_F_LRO; 3087 } 3088 } 3089 3090 return features; 3091 } 3092 3093 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 3094 { 3095 netdev_features_t diff = dev->features ^ features; 3096 3097 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 3098 mtk_hwlro_netdev_disable(dev); 3099 3100 return 0; 3101 } 3102 3103 /* wait for DMA to finish whatever it is doing before we start using it again */ 3104 static int mtk_dma_busy_wait(struct mtk_eth *eth) 3105 { 3106 unsigned int reg; 3107 int ret; 3108 u32 val; 3109 3110 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3111 reg = eth->soc->reg_map->qdma.glo_cfg; 3112 else 3113 reg = eth->soc->reg_map->pdma.glo_cfg; 3114 3115 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 3116 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 3117 5, MTK_DMA_BUSY_TIMEOUT_US); 3118 if (ret) 3119 dev_err(eth->dev, "DMA init timeout\n"); 3120 3121 return ret; 3122 } 3123 3124 static int mtk_dma_init(struct mtk_eth *eth) 3125 { 3126 int err; 3127 u32 i; 3128 3129 if (mtk_dma_busy_wait(eth)) 3130 return -EBUSY; 3131 3132 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3133 /* QDMA needs scratch memory for internal reordering of the 3134 * descriptors 3135 */ 3136 err = mtk_init_fq_dma(eth); 3137 if (err) 3138 return err; 3139 } 3140 3141 err = mtk_tx_alloc(eth); 3142 if (err) 3143 return err; 3144 3145 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3146 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 3147 if (err) 3148 return err; 3149 } 3150 3151 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 3152 if (err) 3153 return err; 3154 3155 if (eth->hwlro) { 3156 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 3157 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 3158 if (err) 3159 return err; 3160 } 3161 err = mtk_hwlro_rx_init(eth); 3162 if (err) 3163 return err; 3164 } 3165 3166 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3167 /* Enable random early drop and set drop threshold 3168 * automatically 3169 */ 3170 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 3171 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 3172 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 3173 } 3174 3175 return 0; 3176 } 3177 3178 static void mtk_dma_free(struct mtk_eth *eth) 3179 { 3180 const struct mtk_soc_data *soc = eth->soc; 3181 int i; 3182 3183 for (i = 0; i < MTK_MAX_DEVS; i++) 3184 if (eth->netdev[i]) 3185 netdev_reset_queue(eth->netdev[i]); 3186 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { 3187 dma_free_coherent(eth->dma_dev, 3188 MTK_QDMA_RING_SIZE * soc->tx.desc_size, 3189 eth->scratch_ring, eth->phy_scratch_ring); 3190 eth->scratch_ring = NULL; 3191 eth->phy_scratch_ring = 0; 3192 } 3193 mtk_tx_clean(eth); 3194 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); 3195 mtk_rx_clean(eth, ð->rx_ring_qdma, false); 3196 3197 if (eth->hwlro) { 3198 mtk_hwlro_rx_uninit(eth); 3199 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3200 mtk_rx_clean(eth, ð->rx_ring[i], false); 3201 } 3202 3203 for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) { 3204 kfree(eth->scratch_head[i]); 3205 eth->scratch_head[i] = NULL; 3206 } 3207 } 3208 3209 static bool mtk_hw_reset_check(struct mtk_eth *eth) 3210 { 3211 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3212 3213 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3214 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3215 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3216 } 3217 3218 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3219 { 3220 struct mtk_mac *mac = netdev_priv(dev); 3221 struct mtk_eth *eth = mac->hw; 3222 3223 if (test_bit(MTK_RESETTING, ð->state)) 3224 return; 3225 3226 if (!mtk_hw_reset_check(eth)) 3227 return; 3228 3229 eth->netdev[mac->id]->stats.tx_errors++; 3230 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3231 3232 schedule_work(ð->pending_work); 3233 } 3234 3235 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3236 { 3237 struct mtk_eth *eth = _eth; 3238 3239 eth->rx_events++; 3240 if (likely(napi_schedule_prep(ð->rx_napi))) { 3241 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3242 __napi_schedule(ð->rx_napi); 3243 } 3244 3245 return IRQ_HANDLED; 3246 } 3247 3248 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3249 { 3250 struct mtk_eth *eth = _eth; 3251 3252 eth->tx_events++; 3253 if (likely(napi_schedule_prep(ð->tx_napi))) { 3254 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3255 __napi_schedule(ð->tx_napi); 3256 } 3257 3258 return IRQ_HANDLED; 3259 } 3260 3261 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3262 { 3263 struct mtk_eth *eth = _eth; 3264 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3265 3266 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3267 eth->soc->rx.irq_done_mask) { 3268 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3269 eth->soc->rx.irq_done_mask) 3270 mtk_handle_irq_rx(irq, _eth); 3271 } 3272 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3273 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3274 mtk_handle_irq_tx(irq, _eth); 3275 } 3276 3277 return IRQ_HANDLED; 3278 } 3279 3280 #ifdef CONFIG_NET_POLL_CONTROLLER 3281 static void mtk_poll_controller(struct net_device *dev) 3282 { 3283 struct mtk_mac *mac = netdev_priv(dev); 3284 struct mtk_eth *eth = mac->hw; 3285 3286 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3287 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3288 mtk_handle_irq_rx(eth->irq[2], dev); 3289 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3290 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); 3291 } 3292 #endif 3293 3294 static int mtk_start_dma(struct mtk_eth *eth) 3295 { 3296 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3297 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3298 int err; 3299 3300 err = mtk_dma_init(eth); 3301 if (err) { 3302 mtk_dma_free(eth); 3303 return err; 3304 } 3305 3306 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3307 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3308 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3309 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3310 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3311 3312 if (mtk_is_netsys_v2_or_greater(eth)) 3313 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3314 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3315 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3316 else 3317 val |= MTK_RX_BT_32DWORDS; 3318 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3319 3320 mtk_w32(eth, 3321 MTK_RX_DMA_EN | rx_2b_offset | 3322 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3323 reg_map->pdma.glo_cfg); 3324 } else { 3325 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3326 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3327 reg_map->pdma.glo_cfg); 3328 } 3329 3330 return 0; 3331 } 3332 3333 static void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config) 3334 { 3335 u32 val; 3336 3337 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3338 return; 3339 3340 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(id)); 3341 3342 /* default setup the forward port to send frame to PDMA */ 3343 val &= ~0xffff; 3344 3345 /* Enable RX checksum */ 3346 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3347 3348 val |= config; 3349 3350 if (eth->netdev[id] && netdev_uses_dsa(eth->netdev[id])) 3351 val |= MTK_GDMA_SPECIAL_TAG; 3352 3353 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(id)); 3354 } 3355 3356 3357 static bool mtk_uses_dsa(struct net_device *dev) 3358 { 3359 #if IS_ENABLED(CONFIG_NET_DSA) 3360 return netdev_uses_dsa(dev) && 3361 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3362 #else 3363 return false; 3364 #endif 3365 } 3366 3367 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3368 { 3369 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3370 struct mtk_eth *eth = mac->hw; 3371 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3372 struct ethtool_link_ksettings s; 3373 struct net_device *ldev; 3374 struct list_head *iter; 3375 struct dsa_port *dp; 3376 3377 if (event != NETDEV_CHANGE) 3378 return NOTIFY_DONE; 3379 3380 netdev_for_each_lower_dev(dev, ldev, iter) { 3381 if (netdev_priv(ldev) == mac) 3382 goto found; 3383 } 3384 3385 return NOTIFY_DONE; 3386 3387 found: 3388 if (!dsa_user_dev_check(dev)) 3389 return NOTIFY_DONE; 3390 3391 if (__ethtool_get_link_ksettings(dev, &s)) 3392 return NOTIFY_DONE; 3393 3394 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3395 return NOTIFY_DONE; 3396 3397 dp = dsa_port_from_netdev(dev); 3398 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3399 return NOTIFY_DONE; 3400 3401 if (mac->speed > 0 && mac->speed <= s.base.speed) 3402 s.base.speed = 0; 3403 3404 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3405 3406 return NOTIFY_DONE; 3407 } 3408 3409 static int mtk_open(struct net_device *dev) 3410 { 3411 struct mtk_mac *mac = netdev_priv(dev); 3412 struct mtk_eth *eth = mac->hw; 3413 struct mtk_mac *target_mac; 3414 int i, err, ppe_num; 3415 3416 ppe_num = eth->soc->ppe_num; 3417 3418 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3419 if (err) { 3420 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3421 err); 3422 return err; 3423 } 3424 3425 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3426 if (!refcount_read(ð->dma_refcnt)) { 3427 const struct mtk_soc_data *soc = eth->soc; 3428 u32 gdm_config; 3429 int i; 3430 3431 err = mtk_start_dma(eth); 3432 if (err) { 3433 phylink_disconnect_phy(mac->phylink); 3434 return err; 3435 } 3436 3437 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3438 mtk_ppe_start(eth->ppe[i]); 3439 3440 for (i = 0; i < MTK_MAX_DEVS; i++) { 3441 if (!eth->netdev[i]) 3442 continue; 3443 3444 target_mac = netdev_priv(eth->netdev[i]); 3445 if (!soc->offload_version) { 3446 target_mac->ppe_idx = 0; 3447 gdm_config = MTK_GDMA_TO_PDMA; 3448 } else if (ppe_num >= 3 && target_mac->id == 2) { 3449 target_mac->ppe_idx = 2; 3450 gdm_config = soc->reg_map->gdma_to_ppe[2]; 3451 } else if (ppe_num >= 2 && target_mac->id == 1) { 3452 target_mac->ppe_idx = 1; 3453 gdm_config = soc->reg_map->gdma_to_ppe[1]; 3454 } else { 3455 target_mac->ppe_idx = 0; 3456 gdm_config = soc->reg_map->gdma_to_ppe[0]; 3457 } 3458 mtk_gdm_config(eth, target_mac->id, gdm_config); 3459 } 3460 /* Reset and enable PSE */ 3461 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3462 mtk_w32(eth, 0, MTK_RST_GL); 3463 3464 napi_enable(ð->tx_napi); 3465 napi_enable(ð->rx_napi); 3466 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3467 mtk_rx_irq_enable(eth, soc->rx.irq_done_mask); 3468 refcount_set(ð->dma_refcnt, 1); 3469 } else { 3470 refcount_inc(ð->dma_refcnt); 3471 } 3472 3473 phylink_start(mac->phylink); 3474 netif_tx_start_all_queues(dev); 3475 3476 if (mtk_is_netsys_v2_or_greater(eth)) 3477 return 0; 3478 3479 if (mtk_uses_dsa(dev) && !eth->prog) { 3480 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3481 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3482 3483 if (md_dst) 3484 continue; 3485 3486 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3487 GFP_KERNEL); 3488 if (!md_dst) 3489 return -ENOMEM; 3490 3491 md_dst->u.port_info.port_id = i; 3492 eth->dsa_meta[i] = md_dst; 3493 } 3494 } else { 3495 /* Hardware DSA untagging and VLAN RX offloading need to be 3496 * disabled if at least one MAC does not use DSA. 3497 */ 3498 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3499 3500 val &= ~MTK_CDMP_STAG_EN; 3501 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3502 3503 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); 3504 } 3505 3506 return 0; 3507 } 3508 3509 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3510 { 3511 u32 val; 3512 int i; 3513 3514 /* stop the dma engine */ 3515 spin_lock_bh(ð->page_lock); 3516 val = mtk_r32(eth, glo_cfg); 3517 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3518 glo_cfg); 3519 spin_unlock_bh(ð->page_lock); 3520 3521 /* wait for dma stop */ 3522 for (i = 0; i < 10; i++) { 3523 val = mtk_r32(eth, glo_cfg); 3524 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3525 msleep(20); 3526 continue; 3527 } 3528 break; 3529 } 3530 } 3531 3532 static int mtk_stop(struct net_device *dev) 3533 { 3534 struct mtk_mac *mac = netdev_priv(dev); 3535 struct mtk_eth *eth = mac->hw; 3536 int i; 3537 3538 phylink_stop(mac->phylink); 3539 3540 netif_tx_disable(dev); 3541 3542 phylink_disconnect_phy(mac->phylink); 3543 3544 /* only shutdown DMA if this is the last user */ 3545 if (!refcount_dec_and_test(ð->dma_refcnt)) 3546 return 0; 3547 3548 for (i = 0; i < MTK_MAX_DEVS; i++) 3549 mtk_gdm_config(eth, i, MTK_GDMA_DROP_ALL); 3550 3551 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3552 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); 3553 napi_disable(ð->tx_napi); 3554 napi_disable(ð->rx_napi); 3555 3556 cancel_work_sync(ð->rx_dim.work); 3557 cancel_work_sync(ð->tx_dim.work); 3558 3559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3560 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3561 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3562 3563 mtk_dma_free(eth); 3564 3565 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3566 mtk_ppe_stop(eth->ppe[i]); 3567 3568 return 0; 3569 } 3570 3571 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3572 struct netlink_ext_ack *extack) 3573 { 3574 struct mtk_mac *mac = netdev_priv(dev); 3575 struct mtk_eth *eth = mac->hw; 3576 struct bpf_prog *old_prog; 3577 bool need_update; 3578 3579 if (eth->hwlro) { 3580 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3581 return -EOPNOTSUPP; 3582 } 3583 3584 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3585 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3586 return -EOPNOTSUPP; 3587 } 3588 3589 need_update = !!eth->prog != !!prog; 3590 if (netif_running(dev) && need_update) 3591 mtk_stop(dev); 3592 3593 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3594 if (old_prog) 3595 bpf_prog_put(old_prog); 3596 3597 if (netif_running(dev) && need_update) 3598 return mtk_open(dev); 3599 3600 return 0; 3601 } 3602 3603 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3604 { 3605 switch (xdp->command) { 3606 case XDP_SETUP_PROG: 3607 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3608 default: 3609 return -EINVAL; 3610 } 3611 } 3612 3613 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3614 { 3615 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3616 reset_bits, 3617 reset_bits); 3618 3619 usleep_range(1000, 1100); 3620 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3621 reset_bits, 3622 ~reset_bits); 3623 mdelay(10); 3624 } 3625 3626 static void mtk_clk_disable(struct mtk_eth *eth) 3627 { 3628 int clk; 3629 3630 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3631 clk_disable_unprepare(eth->clks[clk]); 3632 } 3633 3634 static int mtk_clk_enable(struct mtk_eth *eth) 3635 { 3636 int clk, ret; 3637 3638 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3639 ret = clk_prepare_enable(eth->clks[clk]); 3640 if (ret) 3641 goto err_disable_clks; 3642 } 3643 3644 return 0; 3645 3646 err_disable_clks: 3647 while (--clk >= 0) 3648 clk_disable_unprepare(eth->clks[clk]); 3649 3650 return ret; 3651 } 3652 3653 static void mtk_dim_rx(struct work_struct *work) 3654 { 3655 struct dim *dim = container_of(work, struct dim, work); 3656 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3657 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3658 struct dim_cq_moder cur_profile; 3659 u32 val, cur; 3660 3661 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3662 dim->profile_ix); 3663 spin_lock_bh(ð->dim_lock); 3664 3665 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3666 val &= MTK_PDMA_DELAY_TX_MASK; 3667 val |= MTK_PDMA_DELAY_RX_EN; 3668 3669 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3670 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3671 3672 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3673 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3674 3675 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3676 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3677 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3678 3679 spin_unlock_bh(ð->dim_lock); 3680 3681 dim->state = DIM_START_MEASURE; 3682 } 3683 3684 static void mtk_dim_tx(struct work_struct *work) 3685 { 3686 struct dim *dim = container_of(work, struct dim, work); 3687 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3688 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3689 struct dim_cq_moder cur_profile; 3690 u32 val, cur; 3691 3692 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3693 dim->profile_ix); 3694 spin_lock_bh(ð->dim_lock); 3695 3696 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3697 val &= MTK_PDMA_DELAY_RX_MASK; 3698 val |= MTK_PDMA_DELAY_TX_EN; 3699 3700 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3701 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3702 3703 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3704 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3705 3706 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3707 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3708 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3709 3710 spin_unlock_bh(ð->dim_lock); 3711 3712 dim->state = DIM_START_MEASURE; 3713 } 3714 3715 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3716 { 3717 struct mtk_eth *eth = mac->hw; 3718 u32 mcr_cur, mcr_new; 3719 3720 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3721 return; 3722 3723 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3724 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3725 3726 if (val <= 1518) 3727 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3728 else if (val <= 1536) 3729 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3730 else if (val <= 1552) 3731 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3732 else 3733 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3734 3735 if (mcr_new != mcr_cur) 3736 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3737 } 3738 3739 static void mtk_hw_reset(struct mtk_eth *eth) 3740 { 3741 u32 val; 3742 3743 if (mtk_is_netsys_v2_or_greater(eth)) 3744 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3745 3746 if (mtk_is_netsys_v3_or_greater(eth)) { 3747 val = RSTCTRL_PPE0_V3; 3748 3749 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3750 val |= RSTCTRL_PPE1_V3; 3751 3752 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3753 val |= RSTCTRL_PPE2; 3754 3755 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3756 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3757 val = RSTCTRL_PPE0_V2; 3758 3759 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3760 val |= RSTCTRL_PPE1; 3761 } else { 3762 val = RSTCTRL_PPE0; 3763 } 3764 3765 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3766 3767 if (mtk_is_netsys_v3_or_greater(eth)) 3768 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3769 0x6f8ff); 3770 else if (mtk_is_netsys_v2_or_greater(eth)) 3771 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3772 0x3ffffff); 3773 } 3774 3775 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3776 { 3777 u32 val; 3778 3779 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3780 return val; 3781 } 3782 3783 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3784 { 3785 u32 rst_mask, val; 3786 3787 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3788 RSTCTRL_FE); 3789 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3790 val & RSTCTRL_FE, 1, 1000)) { 3791 dev_err(eth->dev, "warm reset failed\n"); 3792 mtk_hw_reset(eth); 3793 return; 3794 } 3795 3796 if (mtk_is_netsys_v3_or_greater(eth)) { 3797 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3; 3798 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3799 rst_mask |= RSTCTRL_PPE1_V3; 3800 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3801 rst_mask |= RSTCTRL_PPE2; 3802 3803 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3804 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3805 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3806 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3807 rst_mask |= RSTCTRL_PPE1; 3808 } else { 3809 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3810 } 3811 3812 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3813 3814 udelay(1); 3815 val = mtk_hw_reset_read(eth); 3816 if (!(val & rst_mask)) 3817 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3818 val, rst_mask); 3819 3820 rst_mask |= RSTCTRL_FE; 3821 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3822 3823 udelay(1); 3824 val = mtk_hw_reset_read(eth); 3825 if (val & rst_mask) 3826 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3827 val, rst_mask); 3828 } 3829 3830 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3831 { 3832 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3833 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3834 bool oq_hang, cdm1_busy, adma_busy; 3835 bool wtx_busy, cdm_full, oq_free; 3836 u32 wdidx, val, gdm1_fc, gdm2_fc; 3837 bool qfsm_hang, qfwd_hang; 3838 bool ret = false; 3839 3840 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3841 return false; 3842 3843 /* WDMA sanity checks */ 3844 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3845 3846 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3847 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3848 3849 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3850 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3851 3852 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3853 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3854 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3855 3856 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3857 if (++eth->reset.wdma_hang_count > 2) { 3858 eth->reset.wdma_hang_count = 0; 3859 ret = true; 3860 } 3861 goto out; 3862 } 3863 3864 /* QDMA sanity checks */ 3865 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3866 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3867 3868 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3869 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3870 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3871 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3872 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3873 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3874 3875 if (qfsm_hang && qfwd_hang && 3876 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3877 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3878 if (++eth->reset.qdma_hang_count > 2) { 3879 eth->reset.qdma_hang_count = 0; 3880 ret = true; 3881 } 3882 goto out; 3883 } 3884 3885 /* ADMA sanity checks */ 3886 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3887 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3888 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3889 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3890 3891 if (oq_hang && cdm1_busy && adma_busy) { 3892 if (++eth->reset.adma_hang_count > 2) { 3893 eth->reset.adma_hang_count = 0; 3894 ret = true; 3895 } 3896 goto out; 3897 } 3898 3899 eth->reset.wdma_hang_count = 0; 3900 eth->reset.qdma_hang_count = 0; 3901 eth->reset.adma_hang_count = 0; 3902 out: 3903 eth->reset.wdidx = wdidx; 3904 3905 return ret; 3906 } 3907 3908 static void mtk_hw_reset_monitor_work(struct work_struct *work) 3909 { 3910 struct delayed_work *del_work = to_delayed_work(work); 3911 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3912 reset.monitor_work); 3913 3914 if (test_bit(MTK_RESETTING, ð->state)) 3915 goto out; 3916 3917 /* DMA stuck checks */ 3918 if (mtk_hw_check_dma_hang(eth)) 3919 schedule_work(ð->pending_work); 3920 3921 out: 3922 schedule_delayed_work(ð->reset.monitor_work, 3923 MTK_DMA_MONITOR_TIMEOUT); 3924 } 3925 3926 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3927 { 3928 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3929 ETHSYS_DMA_AG_MAP_PPE; 3930 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3931 int i, val, ret; 3932 3933 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3934 return 0; 3935 3936 if (!reset) { 3937 pm_runtime_enable(eth->dev); 3938 pm_runtime_get_sync(eth->dev); 3939 3940 ret = mtk_clk_enable(eth); 3941 if (ret) 3942 goto err_disable_pm; 3943 } 3944 3945 if (eth->ethsys) 3946 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3947 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3948 3949 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3950 ret = device_reset(eth->dev); 3951 if (ret) { 3952 dev_err(eth->dev, "MAC reset failed!\n"); 3953 goto err_disable_pm; 3954 } 3955 3956 /* set interrupt delays based on current Net DIM sample */ 3957 mtk_dim_rx(ð->rx_dim.work); 3958 mtk_dim_tx(ð->tx_dim.work); 3959 3960 /* disable delay and normal interrupt */ 3961 mtk_tx_irq_disable(eth, ~0); 3962 mtk_rx_irq_disable(eth, ~0); 3963 3964 return 0; 3965 } 3966 3967 msleep(100); 3968 3969 if (reset) 3970 mtk_hw_warm_reset(eth); 3971 else 3972 mtk_hw_reset(eth); 3973 3974 if (mtk_is_netsys_v3_or_greater(eth)) { 3975 /* Set FE to PDMAv2 if necessary */ 3976 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3977 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3978 } 3979 3980 if (eth->pctl) { 3981 /* Set GE2 driving and slew rate */ 3982 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3983 3984 /* set GE2 TDSEL */ 3985 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3986 3987 /* set GE2 TUNE */ 3988 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3989 } 3990 3991 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3992 * up with the more appropriate value when mtk_mac_config call is being 3993 * invoked. 3994 */ 3995 for (i = 0; i < MTK_MAX_DEVS; i++) { 3996 struct net_device *dev = eth->netdev[i]; 3997 3998 if (!dev) 3999 continue; 4000 4001 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 4002 mtk_set_mcr_max_rx(netdev_priv(dev), 4003 dev->mtu + MTK_RX_ETH_HLEN); 4004 } 4005 4006 /* Indicates CDM to parse the MTK special tag from CPU 4007 * which also is working out for untag packets. 4008 */ 4009 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 4010 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 4011 if (mtk_is_netsys_v1(eth)) { 4012 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 4013 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 4014 4015 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 4016 } 4017 4018 /* set interrupt delays based on current Net DIM sample */ 4019 mtk_dim_rx(ð->rx_dim.work); 4020 mtk_dim_tx(ð->tx_dim.work); 4021 4022 /* disable delay and normal interrupt */ 4023 mtk_tx_irq_disable(eth, ~0); 4024 mtk_rx_irq_disable(eth, ~0); 4025 4026 /* FE int grouping */ 4027 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 4028 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4); 4029 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 4030 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4); 4031 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 4032 4033 if (mtk_is_netsys_v3_or_greater(eth)) { 4034 /* PSE should not drop port1, port8 and port9 packets */ 4035 mtk_w32(eth, 0x00000302, PSE_DROP_CFG); 4036 4037 /* GDM and CDM Threshold */ 4038 mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); 4039 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); 4040 4041 /* Disable GDM1 RX CRC stripping */ 4042 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); 4043 4044 /* PSE GDM3 MIB counter has incorrect hw default values, 4045 * so the driver ought to read clear the values beforehand 4046 * in case ethtool retrieve wrong mib values. 4047 */ 4048 for (i = 0; i < 0x80; i += 0x4) 4049 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); 4050 } else if (!mtk_is_netsys_v1(eth)) { 4051 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 4052 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 4053 4054 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 4055 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 4056 4057 /* PSE Free Queue Flow Control */ 4058 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 4059 4060 /* PSE config input queue threshold */ 4061 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 4062 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 4063 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 4064 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 4065 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 4066 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 4067 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 4068 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 4069 4070 /* PSE config output queue threshold */ 4071 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 4072 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 4073 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 4074 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 4075 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 4076 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 4077 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 4078 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 4079 4080 /* GDM and CDM Threshold */ 4081 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 4082 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 4083 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 4084 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 4085 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 4086 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 4087 } 4088 4089 return 0; 4090 4091 err_disable_pm: 4092 if (!reset) { 4093 pm_runtime_put_sync(eth->dev); 4094 pm_runtime_disable(eth->dev); 4095 } 4096 4097 return ret; 4098 } 4099 4100 static int mtk_hw_deinit(struct mtk_eth *eth) 4101 { 4102 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 4103 return 0; 4104 4105 mtk_clk_disable(eth); 4106 4107 pm_runtime_put_sync(eth->dev); 4108 pm_runtime_disable(eth->dev); 4109 4110 return 0; 4111 } 4112 4113 static void mtk_uninit(struct net_device *dev) 4114 { 4115 struct mtk_mac *mac = netdev_priv(dev); 4116 struct mtk_eth *eth = mac->hw; 4117 4118 phylink_disconnect_phy(mac->phylink); 4119 mtk_tx_irq_disable(eth, ~0); 4120 mtk_rx_irq_disable(eth, ~0); 4121 } 4122 4123 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 4124 { 4125 int length = new_mtu + MTK_RX_ETH_HLEN; 4126 struct mtk_mac *mac = netdev_priv(dev); 4127 struct mtk_eth *eth = mac->hw; 4128 4129 if (rcu_access_pointer(eth->prog) && 4130 length > MTK_PP_MAX_BUF_SIZE) { 4131 netdev_err(dev, "Invalid MTU for XDP mode\n"); 4132 return -EINVAL; 4133 } 4134 4135 mtk_set_mcr_max_rx(mac, length); 4136 WRITE_ONCE(dev->mtu, new_mtu); 4137 4138 return 0; 4139 } 4140 4141 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4142 { 4143 struct mtk_mac *mac = netdev_priv(dev); 4144 4145 switch (cmd) { 4146 case SIOCGMIIPHY: 4147 case SIOCGMIIREG: 4148 case SIOCSMIIREG: 4149 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 4150 default: 4151 break; 4152 } 4153 4154 return -EOPNOTSUPP; 4155 } 4156 4157 static void mtk_prepare_for_reset(struct mtk_eth *eth) 4158 { 4159 u32 val; 4160 int i; 4161 4162 /* set FE PPE ports link down */ 4163 for (i = MTK_GMAC1_ID; 4164 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4165 i += 2) { 4166 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4167 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4168 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4169 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4170 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4171 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4172 } 4173 4174 /* adjust PPE configurations to prepare for reset */ 4175 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 4176 mtk_ppe_prepare_reset(eth->ppe[i]); 4177 4178 /* disable NETSYS interrupts */ 4179 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 4180 4181 /* force link down GMAC */ 4182 for (i = 0; i < 2; i++) { 4183 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 4184 mtk_w32(eth, val, MTK_MAC_MCR(i)); 4185 } 4186 } 4187 4188 static void mtk_pending_work(struct work_struct *work) 4189 { 4190 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 4191 unsigned long restart = 0; 4192 u32 val; 4193 int i; 4194 4195 rtnl_lock(); 4196 set_bit(MTK_RESETTING, ð->state); 4197 4198 mtk_prepare_for_reset(eth); 4199 mtk_wed_fe_reset(); 4200 /* Run again reset preliminary configuration in order to avoid any 4201 * possible race during FE reset since it can run releasing RTNL lock. 4202 */ 4203 mtk_prepare_for_reset(eth); 4204 4205 /* stop all devices to make sure that dma is properly shut down */ 4206 for (i = 0; i < MTK_MAX_DEVS; i++) { 4207 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 4208 continue; 4209 4210 mtk_stop(eth->netdev[i]); 4211 __set_bit(i, &restart); 4212 } 4213 4214 usleep_range(15000, 16000); 4215 4216 if (eth->dev->pins) 4217 pinctrl_select_state(eth->dev->pins->p, 4218 eth->dev->pins->default_state); 4219 mtk_hw_init(eth, true); 4220 4221 /* restart DMA and enable IRQs */ 4222 for (i = 0; i < MTK_MAX_DEVS; i++) { 4223 if (!eth->netdev[i] || !test_bit(i, &restart)) 4224 continue; 4225 4226 if (mtk_open(eth->netdev[i])) { 4227 netif_alert(eth, ifup, eth->netdev[i], 4228 "Driver up/down cycle failed\n"); 4229 dev_close(eth->netdev[i]); 4230 } 4231 } 4232 4233 /* set FE PPE ports link up */ 4234 for (i = MTK_GMAC1_ID; 4235 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4236 i += 2) { 4237 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4238 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4239 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4240 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4241 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4242 4243 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4244 } 4245 4246 clear_bit(MTK_RESETTING, ð->state); 4247 4248 mtk_wed_fe_reset_complete(); 4249 4250 rtnl_unlock(); 4251 } 4252 4253 static int mtk_free_dev(struct mtk_eth *eth) 4254 { 4255 int i; 4256 4257 for (i = 0; i < MTK_MAX_DEVS; i++) { 4258 if (!eth->netdev[i]) 4259 continue; 4260 free_netdev(eth->netdev[i]); 4261 } 4262 4263 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4264 if (!eth->dsa_meta[i]) 4265 break; 4266 metadata_dst_free(eth->dsa_meta[i]); 4267 } 4268 4269 return 0; 4270 } 4271 4272 static int mtk_unreg_dev(struct mtk_eth *eth) 4273 { 4274 int i; 4275 4276 for (i = 0; i < MTK_MAX_DEVS; i++) { 4277 struct mtk_mac *mac; 4278 if (!eth->netdev[i]) 4279 continue; 4280 mac = netdev_priv(eth->netdev[i]); 4281 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4282 unregister_netdevice_notifier(&mac->device_notifier); 4283 unregister_netdev(eth->netdev[i]); 4284 } 4285 4286 return 0; 4287 } 4288 4289 static void mtk_sgmii_destroy(struct mtk_eth *eth) 4290 { 4291 int i; 4292 4293 for (i = 0; i < MTK_MAX_DEVS; i++) 4294 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); 4295 } 4296 4297 static int mtk_cleanup(struct mtk_eth *eth) 4298 { 4299 mtk_sgmii_destroy(eth); 4300 mtk_unreg_dev(eth); 4301 mtk_free_dev(eth); 4302 cancel_work_sync(ð->pending_work); 4303 cancel_delayed_work_sync(ð->reset.monitor_work); 4304 4305 return 0; 4306 } 4307 4308 static int mtk_get_link_ksettings(struct net_device *ndev, 4309 struct ethtool_link_ksettings *cmd) 4310 { 4311 struct mtk_mac *mac = netdev_priv(ndev); 4312 4313 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4314 return -EBUSY; 4315 4316 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4317 } 4318 4319 static int mtk_set_link_ksettings(struct net_device *ndev, 4320 const struct ethtool_link_ksettings *cmd) 4321 { 4322 struct mtk_mac *mac = netdev_priv(ndev); 4323 4324 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4325 return -EBUSY; 4326 4327 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4328 } 4329 4330 static void mtk_get_drvinfo(struct net_device *dev, 4331 struct ethtool_drvinfo *info) 4332 { 4333 struct mtk_mac *mac = netdev_priv(dev); 4334 4335 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4336 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4337 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4338 } 4339 4340 static u32 mtk_get_msglevel(struct net_device *dev) 4341 { 4342 struct mtk_mac *mac = netdev_priv(dev); 4343 4344 return mac->hw->msg_enable; 4345 } 4346 4347 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4348 { 4349 struct mtk_mac *mac = netdev_priv(dev); 4350 4351 mac->hw->msg_enable = value; 4352 } 4353 4354 static int mtk_nway_reset(struct net_device *dev) 4355 { 4356 struct mtk_mac *mac = netdev_priv(dev); 4357 4358 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4359 return -EBUSY; 4360 4361 if (!mac->phylink) 4362 return -ENOTSUPP; 4363 4364 return phylink_ethtool_nway_reset(mac->phylink); 4365 } 4366 4367 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4368 { 4369 int i; 4370 4371 switch (stringset) { 4372 case ETH_SS_STATS: { 4373 struct mtk_mac *mac = netdev_priv(dev); 4374 4375 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4376 ethtool_puts(&data, mtk_ethtool_stats[i].str); 4377 if (mtk_page_pool_enabled(mac->hw)) 4378 page_pool_ethtool_stats_get_strings(data); 4379 break; 4380 } 4381 default: 4382 break; 4383 } 4384 } 4385 4386 static int mtk_get_sset_count(struct net_device *dev, int sset) 4387 { 4388 switch (sset) { 4389 case ETH_SS_STATS: { 4390 int count = ARRAY_SIZE(mtk_ethtool_stats); 4391 struct mtk_mac *mac = netdev_priv(dev); 4392 4393 if (mtk_page_pool_enabled(mac->hw)) 4394 count += page_pool_ethtool_stats_get_count(); 4395 return count; 4396 } 4397 default: 4398 return -EOPNOTSUPP; 4399 } 4400 } 4401 4402 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4403 { 4404 struct page_pool_stats stats = {}; 4405 int i; 4406 4407 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4408 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4409 4410 if (!ring->page_pool) 4411 continue; 4412 4413 page_pool_get_stats(ring->page_pool, &stats); 4414 } 4415 page_pool_ethtool_stats_get(data, &stats); 4416 } 4417 4418 static void mtk_get_ethtool_stats(struct net_device *dev, 4419 struct ethtool_stats *stats, u64 *data) 4420 { 4421 struct mtk_mac *mac = netdev_priv(dev); 4422 struct mtk_hw_stats *hwstats = mac->hw_stats; 4423 u64 *data_src, *data_dst; 4424 unsigned int start; 4425 int i; 4426 4427 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4428 return; 4429 4430 if (netif_running(dev) && netif_device_present(dev)) { 4431 if (spin_trylock_bh(&hwstats->stats_lock)) { 4432 mtk_stats_update_mac(mac); 4433 spin_unlock_bh(&hwstats->stats_lock); 4434 } 4435 } 4436 4437 data_src = (u64 *)hwstats; 4438 4439 do { 4440 data_dst = data; 4441 start = u64_stats_fetch_begin(&hwstats->syncp); 4442 4443 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4444 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4445 if (mtk_page_pool_enabled(mac->hw)) 4446 mtk_ethtool_pp_stats(mac->hw, data_dst); 4447 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4448 } 4449 4450 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4451 u32 *rule_locs) 4452 { 4453 int ret = -EOPNOTSUPP; 4454 4455 switch (cmd->cmd) { 4456 case ETHTOOL_GRXRINGS: 4457 if (dev->hw_features & NETIF_F_LRO) { 4458 cmd->data = MTK_MAX_RX_RING_NUM; 4459 ret = 0; 4460 } 4461 break; 4462 case ETHTOOL_GRXCLSRLCNT: 4463 if (dev->hw_features & NETIF_F_LRO) { 4464 struct mtk_mac *mac = netdev_priv(dev); 4465 4466 cmd->rule_cnt = mac->hwlro_ip_cnt; 4467 ret = 0; 4468 } 4469 break; 4470 case ETHTOOL_GRXCLSRULE: 4471 if (dev->hw_features & NETIF_F_LRO) 4472 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4473 break; 4474 case ETHTOOL_GRXCLSRLALL: 4475 if (dev->hw_features & NETIF_F_LRO) 4476 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4477 rule_locs); 4478 break; 4479 default: 4480 break; 4481 } 4482 4483 return ret; 4484 } 4485 4486 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4487 { 4488 int ret = -EOPNOTSUPP; 4489 4490 switch (cmd->cmd) { 4491 case ETHTOOL_SRXCLSRLINS: 4492 if (dev->hw_features & NETIF_F_LRO) 4493 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4494 break; 4495 case ETHTOOL_SRXCLSRLDEL: 4496 if (dev->hw_features & NETIF_F_LRO) 4497 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4498 break; 4499 default: 4500 break; 4501 } 4502 4503 return ret; 4504 } 4505 4506 static void mtk_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) 4507 { 4508 struct mtk_mac *mac = netdev_priv(dev); 4509 4510 phylink_ethtool_get_pauseparam(mac->phylink, pause); 4511 } 4512 4513 static int mtk_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) 4514 { 4515 struct mtk_mac *mac = netdev_priv(dev); 4516 4517 return phylink_ethtool_set_pauseparam(mac->phylink, pause); 4518 } 4519 4520 static int mtk_get_eee(struct net_device *dev, struct ethtool_keee *eee) 4521 { 4522 struct mtk_mac *mac = netdev_priv(dev); 4523 4524 return phylink_ethtool_get_eee(mac->phylink, eee); 4525 } 4526 4527 static int mtk_set_eee(struct net_device *dev, struct ethtool_keee *eee) 4528 { 4529 struct mtk_mac *mac = netdev_priv(dev); 4530 4531 return phylink_ethtool_set_eee(mac->phylink, eee); 4532 } 4533 4534 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4535 struct net_device *sb_dev) 4536 { 4537 struct mtk_mac *mac = netdev_priv(dev); 4538 unsigned int queue = 0; 4539 4540 if (netdev_uses_dsa(dev)) 4541 queue = skb_get_queue_mapping(skb) + 3; 4542 else 4543 queue = mac->id; 4544 4545 if (queue >= dev->num_tx_queues) 4546 queue = 0; 4547 4548 return queue; 4549 } 4550 4551 static const struct ethtool_ops mtk_ethtool_ops = { 4552 .get_link_ksettings = mtk_get_link_ksettings, 4553 .set_link_ksettings = mtk_set_link_ksettings, 4554 .get_drvinfo = mtk_get_drvinfo, 4555 .get_msglevel = mtk_get_msglevel, 4556 .set_msglevel = mtk_set_msglevel, 4557 .nway_reset = mtk_nway_reset, 4558 .get_link = ethtool_op_get_link, 4559 .get_strings = mtk_get_strings, 4560 .get_sset_count = mtk_get_sset_count, 4561 .get_ethtool_stats = mtk_get_ethtool_stats, 4562 .get_pauseparam = mtk_get_pauseparam, 4563 .set_pauseparam = mtk_set_pauseparam, 4564 .get_rxnfc = mtk_get_rxnfc, 4565 .set_rxnfc = mtk_set_rxnfc, 4566 .get_eee = mtk_get_eee, 4567 .set_eee = mtk_set_eee, 4568 }; 4569 4570 static const struct net_device_ops mtk_netdev_ops = { 4571 .ndo_uninit = mtk_uninit, 4572 .ndo_open = mtk_open, 4573 .ndo_stop = mtk_stop, 4574 .ndo_start_xmit = mtk_start_xmit, 4575 .ndo_set_mac_address = mtk_set_mac_address, 4576 .ndo_validate_addr = eth_validate_addr, 4577 .ndo_eth_ioctl = mtk_do_ioctl, 4578 .ndo_change_mtu = mtk_change_mtu, 4579 .ndo_tx_timeout = mtk_tx_timeout, 4580 .ndo_get_stats64 = mtk_get_stats64, 4581 .ndo_fix_features = mtk_fix_features, 4582 .ndo_set_features = mtk_set_features, 4583 #ifdef CONFIG_NET_POLL_CONTROLLER 4584 .ndo_poll_controller = mtk_poll_controller, 4585 #endif 4586 .ndo_setup_tc = mtk_eth_setup_tc, 4587 .ndo_bpf = mtk_xdp, 4588 .ndo_xdp_xmit = mtk_xdp_xmit, 4589 .ndo_select_queue = mtk_select_queue, 4590 }; 4591 4592 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4593 { 4594 const __be32 *_id = of_get_property(np, "reg", NULL); 4595 phy_interface_t phy_mode; 4596 struct phylink *phylink; 4597 struct mtk_mac *mac; 4598 int id, err; 4599 int txqs = 1; 4600 u32 val; 4601 4602 if (!_id) { 4603 dev_err(eth->dev, "missing mac id\n"); 4604 return -EINVAL; 4605 } 4606 4607 id = be32_to_cpup(_id); 4608 if (id >= MTK_MAX_DEVS) { 4609 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4610 return -EINVAL; 4611 } 4612 4613 if (eth->netdev[id]) { 4614 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4615 return -EINVAL; 4616 } 4617 4618 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4619 txqs = MTK_QDMA_NUM_QUEUES; 4620 4621 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4622 if (!eth->netdev[id]) { 4623 dev_err(eth->dev, "alloc_etherdev failed\n"); 4624 return -ENOMEM; 4625 } 4626 mac = netdev_priv(eth->netdev[id]); 4627 eth->mac[id] = mac; 4628 mac->id = id; 4629 mac->hw = eth; 4630 mac->of_node = np; 4631 4632 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); 4633 if (err == -EPROBE_DEFER) 4634 return err; 4635 4636 if (err) { 4637 /* If the mac address is invalid, use random mac address */ 4638 eth_hw_addr_random(eth->netdev[id]); 4639 dev_err(eth->dev, "generated random MAC address %pM\n", 4640 eth->netdev[id]->dev_addr); 4641 } 4642 4643 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4644 mac->hwlro_ip_cnt = 0; 4645 4646 mac->hw_stats = devm_kzalloc(eth->dev, 4647 sizeof(*mac->hw_stats), 4648 GFP_KERNEL); 4649 if (!mac->hw_stats) { 4650 dev_err(eth->dev, "failed to allocate counter memory\n"); 4651 err = -ENOMEM; 4652 goto free_netdev; 4653 } 4654 spin_lock_init(&mac->hw_stats->stats_lock); 4655 u64_stats_init(&mac->hw_stats->syncp); 4656 4657 if (mtk_is_netsys_v3_or_greater(eth)) 4658 mac->hw_stats->reg_offset = id * 0x80; 4659 else 4660 mac->hw_stats->reg_offset = id * 0x40; 4661 4662 /* phylink create */ 4663 err = of_get_phy_mode(np, &phy_mode); 4664 if (err) { 4665 dev_err(eth->dev, "incorrect phy-mode\n"); 4666 goto free_netdev; 4667 } 4668 4669 /* mac config is not set */ 4670 mac->interface = PHY_INTERFACE_MODE_NA; 4671 mac->speed = SPEED_UNKNOWN; 4672 4673 mac->phylink_config.dev = ð->netdev[id]->dev; 4674 mac->phylink_config.type = PHYLINK_NETDEV; 4675 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4676 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4677 mac->phylink_config.lpi_capabilities = MAC_100FD | MAC_1000FD | 4678 MAC_2500FD; 4679 mac->phylink_config.lpi_timer_default = 1000; 4680 4681 /* MT7623 gmac0 is now missing its speed-specific PLL configuration 4682 * in its .mac_config method (since state->speed is not valid there. 4683 * Disable support for MII, GMII and RGMII. 4684 */ 4685 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { 4686 __set_bit(PHY_INTERFACE_MODE_MII, 4687 mac->phylink_config.supported_interfaces); 4688 __set_bit(PHY_INTERFACE_MODE_GMII, 4689 mac->phylink_config.supported_interfaces); 4690 4691 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4692 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4693 } 4694 4695 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4696 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4697 mac->phylink_config.supported_interfaces); 4698 4699 /* TRGMII is not permitted on MT7621 if using DDR2 */ 4700 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 4701 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 4702 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 4703 if (val & SYSCFG_DRAM_TYPE_DDR2) 4704 __clear_bit(PHY_INTERFACE_MODE_TRGMII, 4705 mac->phylink_config.supported_interfaces); 4706 } 4707 4708 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4709 __set_bit(PHY_INTERFACE_MODE_SGMII, 4710 mac->phylink_config.supported_interfaces); 4711 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4712 mac->phylink_config.supported_interfaces); 4713 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4714 mac->phylink_config.supported_interfaces); 4715 } 4716 4717 if (mtk_is_netsys_v3_or_greater(mac->hw) && 4718 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && 4719 id == MTK_GMAC1_ID) { 4720 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 4721 MAC_SYM_PAUSE | 4722 MAC_10000FD; 4723 phy_interface_zero(mac->phylink_config.supported_interfaces); 4724 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 4725 mac->phylink_config.supported_interfaces); 4726 } 4727 4728 phylink = phylink_create(&mac->phylink_config, 4729 of_fwnode_handle(mac->of_node), 4730 phy_mode, &mtk_phylink_ops); 4731 if (IS_ERR(phylink)) { 4732 err = PTR_ERR(phylink); 4733 goto free_netdev; 4734 } 4735 4736 mac->phylink = phylink; 4737 4738 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4739 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4740 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4741 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4742 4743 eth->netdev[id]->hw_features = eth->soc->hw_features; 4744 if (eth->hwlro) 4745 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4746 4747 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4748 ~NETIF_F_HW_VLAN_CTAG_TX; 4749 eth->netdev[id]->features |= eth->soc->hw_features; 4750 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4751 4752 eth->netdev[id]->irq = eth->irq[0]; 4753 eth->netdev[id]->dev.of_node = np; 4754 4755 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4756 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4757 else 4758 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4759 4760 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4761 mac->device_notifier.notifier_call = mtk_device_event; 4762 register_netdevice_notifier(&mac->device_notifier); 4763 } 4764 4765 if (mtk_page_pool_enabled(eth)) 4766 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4767 NETDEV_XDP_ACT_REDIRECT | 4768 NETDEV_XDP_ACT_NDO_XMIT | 4769 NETDEV_XDP_ACT_NDO_XMIT_SG; 4770 4771 return 0; 4772 4773 free_netdev: 4774 free_netdev(eth->netdev[id]); 4775 return err; 4776 } 4777 4778 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4779 { 4780 struct net_device *dev, *tmp; 4781 LIST_HEAD(dev_list); 4782 int i; 4783 4784 rtnl_lock(); 4785 4786 for (i = 0; i < MTK_MAX_DEVS; i++) { 4787 dev = eth->netdev[i]; 4788 4789 if (!dev || !(dev->flags & IFF_UP)) 4790 continue; 4791 4792 list_add_tail(&dev->close_list, &dev_list); 4793 } 4794 4795 dev_close_many(&dev_list, false); 4796 4797 eth->dma_dev = dma_dev; 4798 4799 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4800 list_del_init(&dev->close_list); 4801 dev_open(dev, NULL); 4802 } 4803 4804 rtnl_unlock(); 4805 } 4806 4807 static int mtk_sgmii_init(struct mtk_eth *eth) 4808 { 4809 struct device_node *np; 4810 struct regmap *regmap; 4811 u32 flags; 4812 int i; 4813 4814 for (i = 0; i < MTK_MAX_DEVS; i++) { 4815 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); 4816 if (!np) 4817 break; 4818 4819 regmap = syscon_node_to_regmap(np); 4820 flags = 0; 4821 if (of_property_read_bool(np, "mediatek,pnswap")) 4822 flags |= MTK_SGMII_FLAG_PN_SWAP; 4823 4824 of_node_put(np); 4825 4826 if (IS_ERR(regmap)) 4827 return PTR_ERR(regmap); 4828 4829 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, 4830 eth->soc->ana_rgc3, 4831 flags); 4832 } 4833 4834 return 0; 4835 } 4836 4837 static int mtk_probe(struct platform_device *pdev) 4838 { 4839 struct resource *res = NULL, *res_sram; 4840 struct device_node *mac_np; 4841 struct mtk_eth *eth; 4842 int err, i; 4843 4844 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4845 if (!eth) 4846 return -ENOMEM; 4847 4848 eth->soc = of_device_get_match_data(&pdev->dev); 4849 4850 eth->dev = &pdev->dev; 4851 eth->dma_dev = &pdev->dev; 4852 eth->base = devm_platform_ioremap_resource(pdev, 0); 4853 if (IS_ERR(eth->base)) 4854 return PTR_ERR(eth->base); 4855 4856 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4857 eth->ip_align = NET_IP_ALIGN; 4858 4859 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4860 /* SRAM is actual memory and supports transparent access just like DRAM. 4861 * Hence we don't require __iomem being set and don't need to use accessor 4862 * functions to read from or write to SRAM. 4863 */ 4864 if (mtk_is_netsys_v3_or_greater(eth)) { 4865 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1); 4866 if (IS_ERR(eth->sram_base)) 4867 return PTR_ERR(eth->sram_base); 4868 } else { 4869 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; 4870 } 4871 } 4872 4873 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { 4874 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36)); 4875 if (!err) 4876 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 4877 4878 if (err) { 4879 dev_err(&pdev->dev, "Wrong DMA config\n"); 4880 return -EINVAL; 4881 } 4882 } 4883 4884 spin_lock_init(ð->page_lock); 4885 spin_lock_init(ð->tx_irq_lock); 4886 spin_lock_init(ð->rx_irq_lock); 4887 spin_lock_init(ð->dim_lock); 4888 4889 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4890 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4891 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4892 4893 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4894 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4895 4896 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4897 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4898 "mediatek,ethsys"); 4899 if (IS_ERR(eth->ethsys)) { 4900 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4901 return PTR_ERR(eth->ethsys); 4902 } 4903 } 4904 4905 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4906 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4907 "mediatek,infracfg"); 4908 if (IS_ERR(eth->infra)) { 4909 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4910 return PTR_ERR(eth->infra); 4911 } 4912 } 4913 4914 if (of_dma_is_coherent(pdev->dev.of_node)) { 4915 struct regmap *cci; 4916 4917 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4918 "cci-control-port"); 4919 /* enable CPU/bus coherency */ 4920 if (!IS_ERR(cci)) 4921 regmap_write(cci, 0, 3); 4922 } 4923 4924 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4925 err = mtk_sgmii_init(eth); 4926 4927 if (err) 4928 return err; 4929 } 4930 4931 if (eth->soc->required_pctl) { 4932 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4933 "mediatek,pctl"); 4934 if (IS_ERR(eth->pctl)) { 4935 dev_err(&pdev->dev, "no pctl regmap found\n"); 4936 err = PTR_ERR(eth->pctl); 4937 goto err_destroy_sgmii; 4938 } 4939 } 4940 4941 if (mtk_is_netsys_v2_or_greater(eth)) { 4942 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4943 if (!res) { 4944 err = -EINVAL; 4945 goto err_destroy_sgmii; 4946 } 4947 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4948 if (mtk_is_netsys_v3_or_greater(eth)) { 4949 res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1); 4950 if (!res_sram) { 4951 err = -EINVAL; 4952 goto err_destroy_sgmii; 4953 } 4954 eth->phy_scratch_ring = res_sram->start; 4955 } else { 4956 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; 4957 } 4958 } 4959 } 4960 4961 if (eth->soc->offload_version) { 4962 for (i = 0;; i++) { 4963 struct device_node *np; 4964 phys_addr_t wdma_phy; 4965 u32 wdma_base; 4966 4967 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4968 break; 4969 4970 np = of_parse_phandle(pdev->dev.of_node, 4971 "mediatek,wed", i); 4972 if (!np) 4973 break; 4974 4975 wdma_base = eth->soc->reg_map->wdma_base[i]; 4976 wdma_phy = res ? res->start + wdma_base : 0; 4977 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4978 wdma_phy, i); 4979 } 4980 } 4981 4982 for (i = 0; i < 3; i++) { 4983 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4984 eth->irq[i] = eth->irq[0]; 4985 else 4986 eth->irq[i] = platform_get_irq(pdev, i); 4987 if (eth->irq[i] < 0) { 4988 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4989 err = -ENXIO; 4990 goto err_wed_exit; 4991 } 4992 } 4993 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4994 eth->clks[i] = devm_clk_get(eth->dev, 4995 mtk_clks_source_name[i]); 4996 if (IS_ERR(eth->clks[i])) { 4997 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4998 err = -EPROBE_DEFER; 4999 goto err_wed_exit; 5000 } 5001 if (eth->soc->required_clks & BIT(i)) { 5002 dev_err(&pdev->dev, "clock %s not found\n", 5003 mtk_clks_source_name[i]); 5004 err = -EINVAL; 5005 goto err_wed_exit; 5006 } 5007 eth->clks[i] = NULL; 5008 } 5009 } 5010 5011 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 5012 INIT_WORK(ð->pending_work, mtk_pending_work); 5013 5014 err = mtk_hw_init(eth, false); 5015 if (err) 5016 goto err_wed_exit; 5017 5018 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 5019 5020 for_each_child_of_node(pdev->dev.of_node, mac_np) { 5021 if (!of_device_is_compatible(mac_np, 5022 "mediatek,eth-mac")) 5023 continue; 5024 5025 if (!of_device_is_available(mac_np)) 5026 continue; 5027 5028 err = mtk_add_mac(eth, mac_np); 5029 if (err) { 5030 of_node_put(mac_np); 5031 goto err_deinit_hw; 5032 } 5033 } 5034 5035 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 5036 err = devm_request_irq(eth->dev, eth->irq[0], 5037 mtk_handle_irq, 0, 5038 dev_name(eth->dev), eth); 5039 } else { 5040 err = devm_request_irq(eth->dev, eth->irq[1], 5041 mtk_handle_irq_tx, 0, 5042 dev_name(eth->dev), eth); 5043 if (err) 5044 goto err_free_dev; 5045 5046 err = devm_request_irq(eth->dev, eth->irq[2], 5047 mtk_handle_irq_rx, 0, 5048 dev_name(eth->dev), eth); 5049 } 5050 if (err) 5051 goto err_free_dev; 5052 5053 /* No MT7628/88 support yet */ 5054 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 5055 err = mtk_mdio_init(eth); 5056 if (err) 5057 goto err_free_dev; 5058 } 5059 5060 if (eth->soc->offload_version) { 5061 u8 ppe_num = eth->soc->ppe_num; 5062 5063 ppe_num = min_t(u8, ARRAY_SIZE(eth->ppe), ppe_num); 5064 for (i = 0; i < ppe_num; i++) { 5065 u32 ppe_addr = eth->soc->reg_map->ppe_base; 5066 5067 ppe_addr += (i == 2 ? 0xc00 : i * 0x400); 5068 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); 5069 5070 if (!eth->ppe[i]) { 5071 err = -ENOMEM; 5072 goto err_deinit_ppe; 5073 } 5074 err = mtk_eth_offload_init(eth, i); 5075 5076 if (err) 5077 goto err_deinit_ppe; 5078 } 5079 } 5080 5081 for (i = 0; i < MTK_MAX_DEVS; i++) { 5082 if (!eth->netdev[i]) 5083 continue; 5084 5085 err = register_netdev(eth->netdev[i]); 5086 if (err) { 5087 dev_err(eth->dev, "error bringing up device\n"); 5088 goto err_deinit_ppe; 5089 } else 5090 netif_info(eth, probe, eth->netdev[i], 5091 "mediatek frame engine at 0x%08lx, irq %d\n", 5092 eth->netdev[i]->base_addr, eth->irq[0]); 5093 } 5094 5095 /* we run 2 devices on the same DMA ring so we need a dummy device 5096 * for NAPI to work 5097 */ 5098 eth->dummy_dev = alloc_netdev_dummy(0); 5099 if (!eth->dummy_dev) { 5100 err = -ENOMEM; 5101 dev_err(eth->dev, "failed to allocated dummy device\n"); 5102 goto err_unreg_netdev; 5103 } 5104 netif_napi_add(eth->dummy_dev, ð->tx_napi, mtk_napi_tx); 5105 netif_napi_add(eth->dummy_dev, ð->rx_napi, mtk_napi_rx); 5106 5107 platform_set_drvdata(pdev, eth); 5108 schedule_delayed_work(ð->reset.monitor_work, 5109 MTK_DMA_MONITOR_TIMEOUT); 5110 5111 return 0; 5112 5113 err_unreg_netdev: 5114 mtk_unreg_dev(eth); 5115 err_deinit_ppe: 5116 mtk_ppe_deinit(eth); 5117 mtk_mdio_cleanup(eth); 5118 err_free_dev: 5119 mtk_free_dev(eth); 5120 err_deinit_hw: 5121 mtk_hw_deinit(eth); 5122 err_wed_exit: 5123 mtk_wed_exit(); 5124 err_destroy_sgmii: 5125 mtk_sgmii_destroy(eth); 5126 5127 return err; 5128 } 5129 5130 static void mtk_remove(struct platform_device *pdev) 5131 { 5132 struct mtk_eth *eth = platform_get_drvdata(pdev); 5133 struct mtk_mac *mac; 5134 int i; 5135 5136 /* stop all devices to make sure that dma is properly shut down */ 5137 for (i = 0; i < MTK_MAX_DEVS; i++) { 5138 if (!eth->netdev[i]) 5139 continue; 5140 mtk_stop(eth->netdev[i]); 5141 mac = netdev_priv(eth->netdev[i]); 5142 phylink_disconnect_phy(mac->phylink); 5143 } 5144 5145 mtk_wed_exit(); 5146 mtk_hw_deinit(eth); 5147 5148 netif_napi_del(ð->tx_napi); 5149 netif_napi_del(ð->rx_napi); 5150 mtk_cleanup(eth); 5151 free_netdev(eth->dummy_dev); 5152 mtk_mdio_cleanup(eth); 5153 } 5154 5155 static const struct mtk_soc_data mt2701_data = { 5156 .reg_map = &mtk_reg_map, 5157 .caps = MT7623_CAPS | MTK_HWLRO, 5158 .hw_features = MTK_HW_FEATURES, 5159 .required_clks = MT7623_CLKS_BITMAP, 5160 .required_pctl = true, 5161 .version = 1, 5162 .tx = { 5163 .desc_size = sizeof(struct mtk_tx_dma), 5164 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5165 .dma_len_offset = 16, 5166 .dma_size = MTK_DMA_SIZE(2K), 5167 .fq_dma_size = MTK_DMA_SIZE(2K), 5168 }, 5169 .rx = { 5170 .desc_size = sizeof(struct mtk_rx_dma), 5171 .irq_done_mask = MTK_RX_DONE_INT, 5172 .dma_l4_valid = RX_DMA_L4_VALID, 5173 .dma_size = MTK_DMA_SIZE(2K), 5174 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5175 .dma_len_offset = 16, 5176 }, 5177 }; 5178 5179 static const struct mtk_soc_data mt7621_data = { 5180 .reg_map = &mtk_reg_map, 5181 .caps = MT7621_CAPS, 5182 .hw_features = MTK_HW_FEATURES, 5183 .required_clks = MT7621_CLKS_BITMAP, 5184 .required_pctl = false, 5185 .version = 1, 5186 .offload_version = 1, 5187 .ppe_num = 1, 5188 .hash_offset = 2, 5189 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5190 .tx = { 5191 .desc_size = sizeof(struct mtk_tx_dma), 5192 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5193 .dma_len_offset = 16, 5194 .dma_size = MTK_DMA_SIZE(2K), 5195 .fq_dma_size = MTK_DMA_SIZE(2K), 5196 }, 5197 .rx = { 5198 .desc_size = sizeof(struct mtk_rx_dma), 5199 .irq_done_mask = MTK_RX_DONE_INT, 5200 .dma_l4_valid = RX_DMA_L4_VALID, 5201 .dma_size = MTK_DMA_SIZE(2K), 5202 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5203 .dma_len_offset = 16, 5204 }, 5205 }; 5206 5207 static const struct mtk_soc_data mt7622_data = { 5208 .reg_map = &mtk_reg_map, 5209 .ana_rgc3 = 0x2028, 5210 .caps = MT7622_CAPS | MTK_HWLRO, 5211 .hw_features = MTK_HW_FEATURES, 5212 .required_clks = MT7622_CLKS_BITMAP, 5213 .required_pctl = false, 5214 .version = 1, 5215 .offload_version = 2, 5216 .ppe_num = 1, 5217 .hash_offset = 2, 5218 .has_accounting = true, 5219 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5220 .tx = { 5221 .desc_size = sizeof(struct mtk_tx_dma), 5222 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5223 .dma_len_offset = 16, 5224 .dma_size = MTK_DMA_SIZE(2K), 5225 .fq_dma_size = MTK_DMA_SIZE(2K), 5226 }, 5227 .rx = { 5228 .desc_size = sizeof(struct mtk_rx_dma), 5229 .irq_done_mask = MTK_RX_DONE_INT, 5230 .dma_l4_valid = RX_DMA_L4_VALID, 5231 .dma_size = MTK_DMA_SIZE(2K), 5232 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5233 .dma_len_offset = 16, 5234 }, 5235 }; 5236 5237 static const struct mtk_soc_data mt7623_data = { 5238 .reg_map = &mtk_reg_map, 5239 .caps = MT7623_CAPS | MTK_HWLRO, 5240 .hw_features = MTK_HW_FEATURES, 5241 .required_clks = MT7623_CLKS_BITMAP, 5242 .required_pctl = true, 5243 .version = 1, 5244 .offload_version = 1, 5245 .ppe_num = 1, 5246 .hash_offset = 2, 5247 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5248 .disable_pll_modes = true, 5249 .tx = { 5250 .desc_size = sizeof(struct mtk_tx_dma), 5251 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5252 .dma_len_offset = 16, 5253 .dma_size = MTK_DMA_SIZE(2K), 5254 .fq_dma_size = MTK_DMA_SIZE(2K), 5255 }, 5256 .rx = { 5257 .desc_size = sizeof(struct mtk_rx_dma), 5258 .irq_done_mask = MTK_RX_DONE_INT, 5259 .dma_l4_valid = RX_DMA_L4_VALID, 5260 .dma_size = MTK_DMA_SIZE(2K), 5261 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5262 .dma_len_offset = 16, 5263 }, 5264 }; 5265 5266 static const struct mtk_soc_data mt7629_data = { 5267 .reg_map = &mtk_reg_map, 5268 .ana_rgc3 = 0x128, 5269 .caps = MT7629_CAPS | MTK_HWLRO, 5270 .hw_features = MTK_HW_FEATURES, 5271 .required_clks = MT7629_CLKS_BITMAP, 5272 .required_pctl = false, 5273 .has_accounting = true, 5274 .version = 1, 5275 .tx = { 5276 .desc_size = sizeof(struct mtk_tx_dma), 5277 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5278 .dma_len_offset = 16, 5279 .dma_size = MTK_DMA_SIZE(2K), 5280 .fq_dma_size = MTK_DMA_SIZE(2K), 5281 }, 5282 .rx = { 5283 .desc_size = sizeof(struct mtk_rx_dma), 5284 .irq_done_mask = MTK_RX_DONE_INT, 5285 .dma_l4_valid = RX_DMA_L4_VALID, 5286 .dma_size = MTK_DMA_SIZE(2K), 5287 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5288 .dma_len_offset = 16, 5289 }, 5290 }; 5291 5292 static const struct mtk_soc_data mt7981_data = { 5293 .reg_map = &mt7986_reg_map, 5294 .ana_rgc3 = 0x128, 5295 .caps = MT7981_CAPS, 5296 .hw_features = MTK_HW_FEATURES, 5297 .required_clks = MT7981_CLKS_BITMAP, 5298 .required_pctl = false, 5299 .version = 2, 5300 .offload_version = 2, 5301 .ppe_num = 2, 5302 .hash_offset = 4, 5303 .has_accounting = true, 5304 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5305 .tx = { 5306 .desc_size = sizeof(struct mtk_tx_dma_v2), 5307 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5308 .dma_len_offset = 8, 5309 .dma_size = MTK_DMA_SIZE(2K), 5310 .fq_dma_size = MTK_DMA_SIZE(2K), 5311 }, 5312 .rx = { 5313 .desc_size = sizeof(struct mtk_rx_dma), 5314 .irq_done_mask = MTK_RX_DONE_INT, 5315 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5316 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5317 .dma_len_offset = 16, 5318 .dma_size = MTK_DMA_SIZE(2K), 5319 }, 5320 }; 5321 5322 static const struct mtk_soc_data mt7986_data = { 5323 .reg_map = &mt7986_reg_map, 5324 .ana_rgc3 = 0x128, 5325 .caps = MT7986_CAPS, 5326 .hw_features = MTK_HW_FEATURES, 5327 .required_clks = MT7986_CLKS_BITMAP, 5328 .required_pctl = false, 5329 .version = 2, 5330 .offload_version = 2, 5331 .ppe_num = 2, 5332 .hash_offset = 4, 5333 .has_accounting = true, 5334 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5335 .tx = { 5336 .desc_size = sizeof(struct mtk_tx_dma_v2), 5337 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5338 .dma_len_offset = 8, 5339 .dma_size = MTK_DMA_SIZE(2K), 5340 .fq_dma_size = MTK_DMA_SIZE(2K), 5341 }, 5342 .rx = { 5343 .desc_size = sizeof(struct mtk_rx_dma), 5344 .irq_done_mask = MTK_RX_DONE_INT, 5345 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5346 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5347 .dma_len_offset = 16, 5348 .dma_size = MTK_DMA_SIZE(2K), 5349 }, 5350 }; 5351 5352 static const struct mtk_soc_data mt7988_data = { 5353 .reg_map = &mt7988_reg_map, 5354 .ana_rgc3 = 0x128, 5355 .caps = MT7988_CAPS, 5356 .hw_features = MTK_HW_FEATURES, 5357 .required_clks = MT7988_CLKS_BITMAP, 5358 .required_pctl = false, 5359 .version = 3, 5360 .offload_version = 2, 5361 .ppe_num = 3, 5362 .hash_offset = 4, 5363 .has_accounting = true, 5364 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, 5365 .tx = { 5366 .desc_size = sizeof(struct mtk_tx_dma_v2), 5367 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5368 .dma_len_offset = 8, 5369 .dma_size = MTK_DMA_SIZE(2K), 5370 .fq_dma_size = MTK_DMA_SIZE(4K), 5371 }, 5372 .rx = { 5373 .desc_size = sizeof(struct mtk_rx_dma_v2), 5374 .irq_done_mask = MTK_RX_DONE_INT_V2, 5375 .dma_l4_valid = RX_DMA_L4_VALID_V2, 5376 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5377 .dma_len_offset = 8, 5378 .dma_size = MTK_DMA_SIZE(2K), 5379 }, 5380 }; 5381 5382 static const struct mtk_soc_data rt5350_data = { 5383 .reg_map = &mt7628_reg_map, 5384 .caps = MT7628_CAPS, 5385 .hw_features = MTK_HW_FEATURES_MT7628, 5386 .required_clks = MT7628_CLKS_BITMAP, 5387 .required_pctl = false, 5388 .version = 1, 5389 .tx = { 5390 .desc_size = sizeof(struct mtk_tx_dma), 5391 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5392 .dma_len_offset = 16, 5393 .dma_size = MTK_DMA_SIZE(2K), 5394 }, 5395 .rx = { 5396 .desc_size = sizeof(struct mtk_rx_dma), 5397 .irq_done_mask = MTK_RX_DONE_INT, 5398 .dma_l4_valid = RX_DMA_L4_VALID_PDMA, 5399 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5400 .dma_len_offset = 16, 5401 .dma_size = MTK_DMA_SIZE(2K), 5402 }, 5403 }; 5404 5405 const struct of_device_id of_mtk_match[] = { 5406 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, 5407 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, 5408 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, 5409 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, 5410 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, 5411 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, 5412 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, 5413 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, 5414 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, 5415 {}, 5416 }; 5417 MODULE_DEVICE_TABLE(of, of_mtk_match); 5418 5419 static struct platform_driver mtk_driver = { 5420 .probe = mtk_probe, 5421 .remove = mtk_remove, 5422 .driver = { 5423 .name = "mtk_soc_eth", 5424 .of_match_table = of_mtk_match, 5425 }, 5426 }; 5427 5428 module_platform_driver(mtk_driver); 5429 5430 MODULE_LICENSE("GPL"); 5431 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 5432 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 5433