1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/regmap.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/if_vlan.h> 18 #include <linux/reset.h> 19 #include <linux/tcp.h> 20 #include <linux/interrupt.h> 21 #include <linux/pinctrl/devinfo.h> 22 #include <linux/phylink.h> 23 #include <linux/jhash.h> 24 #include <linux/bitfield.h> 25 #include <net/dsa.h> 26 #include <net/dst_metadata.h> 27 28 #include "mtk_eth_soc.h" 29 #include "mtk_wed.h" 30 31 static int mtk_msg_level = -1; 32 module_param_named(msg_level, mtk_msg_level, int, 0); 33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 34 35 #define MTK_ETHTOOL_STAT(x) { #x, \ 36 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 37 38 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 39 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 40 sizeof(u64) } 41 42 static const struct mtk_reg_map mtk_reg_map = { 43 .tx_irq_mask = 0x1a1c, 44 .tx_irq_status = 0x1a18, 45 .pdma = { 46 .rx_ptr = 0x0900, 47 .rx_cnt_cfg = 0x0904, 48 .pcrx_ptr = 0x0908, 49 .glo_cfg = 0x0a04, 50 .rst_idx = 0x0a08, 51 .delay_irq = 0x0a0c, 52 .irq_status = 0x0a20, 53 .irq_mask = 0x0a28, 54 .int_grp = 0x0a50, 55 }, 56 .qdma = { 57 .qtx_cfg = 0x1800, 58 .qtx_sch = 0x1804, 59 .rx_ptr = 0x1900, 60 .rx_cnt_cfg = 0x1904, 61 .qcrx_ptr = 0x1908, 62 .glo_cfg = 0x1a04, 63 .rst_idx = 0x1a08, 64 .delay_irq = 0x1a0c, 65 .fc_th = 0x1a10, 66 .tx_sch_rate = 0x1a14, 67 .int_grp = 0x1a20, 68 .hred = 0x1a44, 69 .ctx_ptr = 0x1b00, 70 .dtx_ptr = 0x1b04, 71 .crx_ptr = 0x1b10, 72 .drx_ptr = 0x1b14, 73 .fq_head = 0x1b20, 74 .fq_tail = 0x1b24, 75 .fq_count = 0x1b28, 76 .fq_blen = 0x1b2c, 77 }, 78 .gdm1_cnt = 0x2400, 79 .gdma_to_ppe = 0x4444, 80 .ppe_base = 0x0c00, 81 .wdma_base = { 82 [0] = 0x2800, 83 [1] = 0x2c00, 84 }, 85 }; 86 87 static const struct mtk_reg_map mt7628_reg_map = { 88 .tx_irq_mask = 0x0a28, 89 .tx_irq_status = 0x0a20, 90 .pdma = { 91 .rx_ptr = 0x0900, 92 .rx_cnt_cfg = 0x0904, 93 .pcrx_ptr = 0x0908, 94 .glo_cfg = 0x0a04, 95 .rst_idx = 0x0a08, 96 .delay_irq = 0x0a0c, 97 .irq_status = 0x0a20, 98 .irq_mask = 0x0a28, 99 .int_grp = 0x0a50, 100 }, 101 }; 102 103 static const struct mtk_reg_map mt7986_reg_map = { 104 .tx_irq_mask = 0x461c, 105 .tx_irq_status = 0x4618, 106 .pdma = { 107 .rx_ptr = 0x6100, 108 .rx_cnt_cfg = 0x6104, 109 .pcrx_ptr = 0x6108, 110 .glo_cfg = 0x6204, 111 .rst_idx = 0x6208, 112 .delay_irq = 0x620c, 113 .irq_status = 0x6220, 114 .irq_mask = 0x6228, 115 .int_grp = 0x6250, 116 }, 117 .qdma = { 118 .qtx_cfg = 0x4400, 119 .qtx_sch = 0x4404, 120 .rx_ptr = 0x4500, 121 .rx_cnt_cfg = 0x4504, 122 .qcrx_ptr = 0x4508, 123 .glo_cfg = 0x4604, 124 .rst_idx = 0x4608, 125 .delay_irq = 0x460c, 126 .fc_th = 0x4610, 127 .int_grp = 0x4620, 128 .hred = 0x4644, 129 .ctx_ptr = 0x4700, 130 .dtx_ptr = 0x4704, 131 .crx_ptr = 0x4710, 132 .drx_ptr = 0x4714, 133 .fq_head = 0x4720, 134 .fq_tail = 0x4724, 135 .fq_count = 0x4728, 136 .fq_blen = 0x472c, 137 .tx_sch_rate = 0x4798, 138 }, 139 .gdm1_cnt = 0x1c00, 140 .gdma_to_ppe = 0x3333, 141 .ppe_base = 0x2000, 142 .wdma_base = { 143 [0] = 0x4800, 144 [1] = 0x4c00, 145 }, 146 }; 147 148 /* strings used by ethtool */ 149 static const struct mtk_ethtool_stats { 150 char str[ETH_GSTRING_LEN]; 151 u32 offset; 152 } mtk_ethtool_stats[] = { 153 MTK_ETHTOOL_STAT(tx_bytes), 154 MTK_ETHTOOL_STAT(tx_packets), 155 MTK_ETHTOOL_STAT(tx_skip), 156 MTK_ETHTOOL_STAT(tx_collisions), 157 MTK_ETHTOOL_STAT(rx_bytes), 158 MTK_ETHTOOL_STAT(rx_packets), 159 MTK_ETHTOOL_STAT(rx_overflow), 160 MTK_ETHTOOL_STAT(rx_fcs_errors), 161 MTK_ETHTOOL_STAT(rx_short_errors), 162 MTK_ETHTOOL_STAT(rx_long_errors), 163 MTK_ETHTOOL_STAT(rx_checksum_errors), 164 MTK_ETHTOOL_STAT(rx_flow_control_packets), 165 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 166 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 167 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 168 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 169 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 170 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 171 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 172 }; 173 174 static const char * const mtk_clks_source_name[] = { 175 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 176 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 177 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 178 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" 179 }; 180 181 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 182 { 183 __raw_writel(val, eth->base + reg); 184 } 185 186 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 187 { 188 return __raw_readl(eth->base + reg); 189 } 190 191 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 192 { 193 u32 val; 194 195 val = mtk_r32(eth, reg); 196 val &= ~mask; 197 val |= set; 198 mtk_w32(eth, val, reg); 199 return reg; 200 } 201 202 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 203 { 204 unsigned long t_start = jiffies; 205 206 while (1) { 207 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 208 return 0; 209 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 210 break; 211 cond_resched(); 212 } 213 214 dev_err(eth->dev, "mdio: MDIO timeout\n"); 215 return -ETIMEDOUT; 216 } 217 218 static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 219 u32 write_data) 220 { 221 int ret; 222 223 ret = mtk_mdio_busy_wait(eth); 224 if (ret < 0) 225 return ret; 226 227 if (phy_reg & MII_ADDR_C45) { 228 mtk_w32(eth, PHY_IAC_ACCESS | 229 PHY_IAC_START_C45 | 230 PHY_IAC_CMD_C45_ADDR | 231 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 232 PHY_IAC_ADDR(phy_addr) | 233 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 234 MTK_PHY_IAC); 235 236 ret = mtk_mdio_busy_wait(eth); 237 if (ret < 0) 238 return ret; 239 240 mtk_w32(eth, PHY_IAC_ACCESS | 241 PHY_IAC_START_C45 | 242 PHY_IAC_CMD_WRITE | 243 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 244 PHY_IAC_ADDR(phy_addr) | 245 PHY_IAC_DATA(write_data), 246 MTK_PHY_IAC); 247 } else { 248 mtk_w32(eth, PHY_IAC_ACCESS | 249 PHY_IAC_START_C22 | 250 PHY_IAC_CMD_WRITE | 251 PHY_IAC_REG(phy_reg) | 252 PHY_IAC_ADDR(phy_addr) | 253 PHY_IAC_DATA(write_data), 254 MTK_PHY_IAC); 255 } 256 257 ret = mtk_mdio_busy_wait(eth); 258 if (ret < 0) 259 return ret; 260 261 return 0; 262 } 263 264 static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 265 { 266 int ret; 267 268 ret = mtk_mdio_busy_wait(eth); 269 if (ret < 0) 270 return ret; 271 272 if (phy_reg & MII_ADDR_C45) { 273 mtk_w32(eth, PHY_IAC_ACCESS | 274 PHY_IAC_START_C45 | 275 PHY_IAC_CMD_C45_ADDR | 276 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 277 PHY_IAC_ADDR(phy_addr) | 278 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 279 MTK_PHY_IAC); 280 281 ret = mtk_mdio_busy_wait(eth); 282 if (ret < 0) 283 return ret; 284 285 mtk_w32(eth, PHY_IAC_ACCESS | 286 PHY_IAC_START_C45 | 287 PHY_IAC_CMD_C45_READ | 288 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 289 PHY_IAC_ADDR(phy_addr), 290 MTK_PHY_IAC); 291 } else { 292 mtk_w32(eth, PHY_IAC_ACCESS | 293 PHY_IAC_START_C22 | 294 PHY_IAC_CMD_C22_READ | 295 PHY_IAC_REG(phy_reg) | 296 PHY_IAC_ADDR(phy_addr), 297 MTK_PHY_IAC); 298 } 299 300 ret = mtk_mdio_busy_wait(eth); 301 if (ret < 0) 302 return ret; 303 304 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 305 } 306 307 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 308 int phy_reg, u16 val) 309 { 310 struct mtk_eth *eth = bus->priv; 311 312 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 313 } 314 315 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 316 { 317 struct mtk_eth *eth = bus->priv; 318 319 return _mtk_mdio_read(eth, phy_addr, phy_reg); 320 } 321 322 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 323 phy_interface_t interface) 324 { 325 u32 val; 326 327 /* Check DDR memory type. 328 * Currently TRGMII mode with DDR2 memory is not supported. 329 */ 330 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 331 if (interface == PHY_INTERFACE_MODE_TRGMII && 332 val & SYSCFG_DRAM_TYPE_DDR2) { 333 dev_err(eth->dev, 334 "TRGMII mode with DDR2 memory is not supported!\n"); 335 return -EOPNOTSUPP; 336 } 337 338 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 339 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 340 341 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 342 ETHSYS_TRGMII_MT7621_MASK, val); 343 344 return 0; 345 } 346 347 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 348 phy_interface_t interface, int speed) 349 { 350 u32 val; 351 int ret; 352 353 if (interface == PHY_INTERFACE_MODE_TRGMII) { 354 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 355 val = 500000000; 356 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 357 if (ret) 358 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 359 return; 360 } 361 362 val = (speed == SPEED_1000) ? 363 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 364 mtk_w32(eth, val, INTF_MODE); 365 366 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 367 ETHSYS_TRGMII_CLK_SEL362_5, 368 ETHSYS_TRGMII_CLK_SEL362_5); 369 370 val = (speed == SPEED_1000) ? 250000000 : 500000000; 371 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 372 if (ret) 373 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 374 375 val = (speed == SPEED_1000) ? 376 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 377 mtk_w32(eth, val, TRGMII_RCK_CTRL); 378 379 val = (speed == SPEED_1000) ? 380 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 381 mtk_w32(eth, val, TRGMII_TCK_CTRL); 382 } 383 384 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 385 phy_interface_t interface) 386 { 387 struct mtk_mac *mac = container_of(config, struct mtk_mac, 388 phylink_config); 389 struct mtk_eth *eth = mac->hw; 390 unsigned int sid; 391 392 if (interface == PHY_INTERFACE_MODE_SGMII || 393 phy_interface_mode_is_8023z(interface)) { 394 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 395 0 : mac->id; 396 397 return mtk_sgmii_select_pcs(eth->sgmii, sid); 398 } 399 400 return NULL; 401 } 402 403 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 404 const struct phylink_link_state *state) 405 { 406 struct mtk_mac *mac = container_of(config, struct mtk_mac, 407 phylink_config); 408 struct mtk_eth *eth = mac->hw; 409 int val, ge_mode, err = 0; 410 u32 i; 411 412 /* MT76x8 has no hardware settings between for the MAC */ 413 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 414 mac->interface != state->interface) { 415 /* Setup soc pin functions */ 416 switch (state->interface) { 417 case PHY_INTERFACE_MODE_TRGMII: 418 if (mac->id) 419 goto err_phy; 420 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 421 MTK_GMAC1_TRGMII)) 422 goto err_phy; 423 fallthrough; 424 case PHY_INTERFACE_MODE_RGMII_TXID: 425 case PHY_INTERFACE_MODE_RGMII_RXID: 426 case PHY_INTERFACE_MODE_RGMII_ID: 427 case PHY_INTERFACE_MODE_RGMII: 428 case PHY_INTERFACE_MODE_MII: 429 case PHY_INTERFACE_MODE_REVMII: 430 case PHY_INTERFACE_MODE_RMII: 431 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 432 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 433 if (err) 434 goto init_err; 435 } 436 break; 437 case PHY_INTERFACE_MODE_1000BASEX: 438 case PHY_INTERFACE_MODE_2500BASEX: 439 case PHY_INTERFACE_MODE_SGMII: 440 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 441 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 442 if (err) 443 goto init_err; 444 } 445 break; 446 case PHY_INTERFACE_MODE_GMII: 447 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 448 err = mtk_gmac_gephy_path_setup(eth, mac->id); 449 if (err) 450 goto init_err; 451 } 452 break; 453 default: 454 goto err_phy; 455 } 456 457 /* Setup clock for 1st gmac */ 458 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 459 !phy_interface_mode_is_8023z(state->interface) && 460 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 461 if (MTK_HAS_CAPS(mac->hw->soc->caps, 462 MTK_TRGMII_MT7621_CLK)) { 463 if (mt7621_gmac0_rgmii_adjust(mac->hw, 464 state->interface)) 465 goto err_phy; 466 } else { 467 /* FIXME: this is incorrect. Not only does it 468 * use state->speed (which is not guaranteed 469 * to be correct) but it also makes use of it 470 * in a code path that will only be reachable 471 * when the PHY interface mode changes, not 472 * when the speed changes. Consequently, RGMII 473 * is probably broken. 474 */ 475 mtk_gmac0_rgmii_adjust(mac->hw, 476 state->interface, 477 state->speed); 478 479 /* mt7623_pad_clk_setup */ 480 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 481 mtk_w32(mac->hw, 482 TD_DM_DRVP(8) | TD_DM_DRVN(8), 483 TRGMII_TD_ODT(i)); 484 485 /* Assert/release MT7623 RXC reset */ 486 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 487 TRGMII_RCK_CTRL); 488 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 489 } 490 } 491 492 ge_mode = 0; 493 switch (state->interface) { 494 case PHY_INTERFACE_MODE_MII: 495 case PHY_INTERFACE_MODE_GMII: 496 ge_mode = 1; 497 break; 498 case PHY_INTERFACE_MODE_REVMII: 499 ge_mode = 2; 500 break; 501 case PHY_INTERFACE_MODE_RMII: 502 if (mac->id) 503 goto err_phy; 504 ge_mode = 3; 505 break; 506 default: 507 break; 508 } 509 510 /* put the gmac into the right mode */ 511 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 512 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 513 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 514 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 515 516 mac->interface = state->interface; 517 } 518 519 /* SGMII */ 520 if (state->interface == PHY_INTERFACE_MODE_SGMII || 521 phy_interface_mode_is_8023z(state->interface)) { 522 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 523 * being setup done. 524 */ 525 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 526 527 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 528 SYSCFG0_SGMII_MASK, 529 ~(u32)SYSCFG0_SGMII_MASK); 530 531 /* Save the syscfg0 value for mac_finish */ 532 mac->syscfg0 = val; 533 } else if (phylink_autoneg_inband(mode)) { 534 dev_err(eth->dev, 535 "In-band mode not supported in non SGMII mode!\n"); 536 return; 537 } 538 539 return; 540 541 err_phy: 542 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 543 mac->id, phy_modes(state->interface)); 544 return; 545 546 init_err: 547 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 548 mac->id, phy_modes(state->interface), err); 549 } 550 551 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 552 phy_interface_t interface) 553 { 554 struct mtk_mac *mac = container_of(config, struct mtk_mac, 555 phylink_config); 556 struct mtk_eth *eth = mac->hw; 557 u32 mcr_cur, mcr_new; 558 559 /* Enable SGMII */ 560 if (interface == PHY_INTERFACE_MODE_SGMII || 561 phy_interface_mode_is_8023z(interface)) 562 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 563 SYSCFG0_SGMII_MASK, mac->syscfg0); 564 565 /* Setup gmac */ 566 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 567 mcr_new = mcr_cur; 568 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 569 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 570 571 /* Only update control register when needed! */ 572 if (mcr_new != mcr_cur) 573 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 574 575 return 0; 576 } 577 578 static void mtk_mac_pcs_get_state(struct phylink_config *config, 579 struct phylink_link_state *state) 580 { 581 struct mtk_mac *mac = container_of(config, struct mtk_mac, 582 phylink_config); 583 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 584 585 state->link = (pmsr & MAC_MSR_LINK); 586 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 587 588 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 589 case 0: 590 state->speed = SPEED_10; 591 break; 592 case MAC_MSR_SPEED_100: 593 state->speed = SPEED_100; 594 break; 595 case MAC_MSR_SPEED_1000: 596 state->speed = SPEED_1000; 597 break; 598 default: 599 state->speed = SPEED_UNKNOWN; 600 break; 601 } 602 603 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 604 if (pmsr & MAC_MSR_RX_FC) 605 state->pause |= MLO_PAUSE_RX; 606 if (pmsr & MAC_MSR_TX_FC) 607 state->pause |= MLO_PAUSE_TX; 608 } 609 610 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 611 phy_interface_t interface) 612 { 613 struct mtk_mac *mac = container_of(config, struct mtk_mac, 614 phylink_config); 615 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 616 617 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 618 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 619 } 620 621 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 622 int speed) 623 { 624 const struct mtk_soc_data *soc = eth->soc; 625 u32 ofs, val; 626 627 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 628 return; 629 630 val = MTK_QTX_SCH_MIN_RATE_EN | 631 /* minimum: 10 Mbps */ 632 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 633 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 634 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 635 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 636 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 637 638 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 639 switch (speed) { 640 case SPEED_10: 641 val |= MTK_QTX_SCH_MAX_RATE_EN | 642 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 643 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 644 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 645 break; 646 case SPEED_100: 647 val |= MTK_QTX_SCH_MAX_RATE_EN | 648 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 649 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 650 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 651 break; 652 case SPEED_1000: 653 val |= MTK_QTX_SCH_MAX_RATE_EN | 654 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 655 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 656 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 657 break; 658 default: 659 break; 660 } 661 } else { 662 switch (speed) { 663 case SPEED_10: 664 val |= MTK_QTX_SCH_MAX_RATE_EN | 665 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 666 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 667 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 668 break; 669 case SPEED_100: 670 val |= MTK_QTX_SCH_MAX_RATE_EN | 671 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 672 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 673 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 674 break; 675 case SPEED_1000: 676 val |= MTK_QTX_SCH_MAX_RATE_EN | 677 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 678 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 679 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 680 break; 681 default: 682 break; 683 } 684 } 685 686 ofs = MTK_QTX_OFFSET * idx; 687 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 688 } 689 690 static void mtk_mac_link_up(struct phylink_config *config, 691 struct phy_device *phy, 692 unsigned int mode, phy_interface_t interface, 693 int speed, int duplex, bool tx_pause, bool rx_pause) 694 { 695 struct mtk_mac *mac = container_of(config, struct mtk_mac, 696 phylink_config); 697 u32 mcr; 698 699 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 700 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 701 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 702 MAC_MCR_FORCE_RX_FC); 703 704 /* Configure speed */ 705 switch (speed) { 706 case SPEED_2500: 707 case SPEED_1000: 708 mcr |= MAC_MCR_SPEED_1000; 709 break; 710 case SPEED_100: 711 mcr |= MAC_MCR_SPEED_100; 712 break; 713 } 714 715 mtk_set_queue_speed(mac->hw, mac->id, speed); 716 717 /* Configure duplex */ 718 if (duplex == DUPLEX_FULL) 719 mcr |= MAC_MCR_FORCE_DPX; 720 721 /* Configure pause modes - phylink will avoid these for half duplex */ 722 if (tx_pause) 723 mcr |= MAC_MCR_FORCE_TX_FC; 724 if (rx_pause) 725 mcr |= MAC_MCR_FORCE_RX_FC; 726 727 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 728 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 729 } 730 731 static const struct phylink_mac_ops mtk_phylink_ops = { 732 .mac_select_pcs = mtk_mac_select_pcs, 733 .mac_pcs_get_state = mtk_mac_pcs_get_state, 734 .mac_config = mtk_mac_config, 735 .mac_finish = mtk_mac_finish, 736 .mac_link_down = mtk_mac_link_down, 737 .mac_link_up = mtk_mac_link_up, 738 }; 739 740 static int mtk_mdio_init(struct mtk_eth *eth) 741 { 742 struct device_node *mii_np; 743 int ret; 744 745 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 746 if (!mii_np) { 747 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 748 return -ENODEV; 749 } 750 751 if (!of_device_is_available(mii_np)) { 752 ret = -ENODEV; 753 goto err_put_node; 754 } 755 756 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 757 if (!eth->mii_bus) { 758 ret = -ENOMEM; 759 goto err_put_node; 760 } 761 762 eth->mii_bus->name = "mdio"; 763 eth->mii_bus->read = mtk_mdio_read; 764 eth->mii_bus->write = mtk_mdio_write; 765 eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; 766 eth->mii_bus->priv = eth; 767 eth->mii_bus->parent = eth->dev; 768 769 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 770 ret = of_mdiobus_register(eth->mii_bus, mii_np); 771 772 err_put_node: 773 of_node_put(mii_np); 774 return ret; 775 } 776 777 static void mtk_mdio_cleanup(struct mtk_eth *eth) 778 { 779 if (!eth->mii_bus) 780 return; 781 782 mdiobus_unregister(eth->mii_bus); 783 } 784 785 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 786 { 787 unsigned long flags; 788 u32 val; 789 790 spin_lock_irqsave(ð->tx_irq_lock, flags); 791 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 792 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 793 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 794 } 795 796 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 797 { 798 unsigned long flags; 799 u32 val; 800 801 spin_lock_irqsave(ð->tx_irq_lock, flags); 802 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 803 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 804 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 805 } 806 807 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 808 { 809 unsigned long flags; 810 u32 val; 811 812 spin_lock_irqsave(ð->rx_irq_lock, flags); 813 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 814 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 815 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 816 } 817 818 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 819 { 820 unsigned long flags; 821 u32 val; 822 823 spin_lock_irqsave(ð->rx_irq_lock, flags); 824 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 825 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 826 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 827 } 828 829 static int mtk_set_mac_address(struct net_device *dev, void *p) 830 { 831 int ret = eth_mac_addr(dev, p); 832 struct mtk_mac *mac = netdev_priv(dev); 833 struct mtk_eth *eth = mac->hw; 834 const char *macaddr = dev->dev_addr; 835 836 if (ret) 837 return ret; 838 839 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 840 return -EBUSY; 841 842 spin_lock_bh(&mac->hw->page_lock); 843 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 844 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 845 MT7628_SDM_MAC_ADRH); 846 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 847 (macaddr[4] << 8) | macaddr[5], 848 MT7628_SDM_MAC_ADRL); 849 } else { 850 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 851 MTK_GDMA_MAC_ADRH(mac->id)); 852 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 853 (macaddr[4] << 8) | macaddr[5], 854 MTK_GDMA_MAC_ADRL(mac->id)); 855 } 856 spin_unlock_bh(&mac->hw->page_lock); 857 858 return 0; 859 } 860 861 void mtk_stats_update_mac(struct mtk_mac *mac) 862 { 863 struct mtk_hw_stats *hw_stats = mac->hw_stats; 864 struct mtk_eth *eth = mac->hw; 865 866 u64_stats_update_begin(&hw_stats->syncp); 867 868 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 869 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 870 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 871 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 872 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 873 hw_stats->rx_checksum_errors += 874 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 875 } else { 876 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 877 unsigned int offs = hw_stats->reg_offset; 878 u64 stats; 879 880 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 881 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 882 if (stats) 883 hw_stats->rx_bytes += (stats << 32); 884 hw_stats->rx_packets += 885 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 886 hw_stats->rx_overflow += 887 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 888 hw_stats->rx_fcs_errors += 889 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 890 hw_stats->rx_short_errors += 891 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 892 hw_stats->rx_long_errors += 893 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 894 hw_stats->rx_checksum_errors += 895 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 896 hw_stats->rx_flow_control_packets += 897 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 898 hw_stats->tx_skip += 899 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 900 hw_stats->tx_collisions += 901 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 902 hw_stats->tx_bytes += 903 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 904 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 905 if (stats) 906 hw_stats->tx_bytes += (stats << 32); 907 hw_stats->tx_packets += 908 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 909 } 910 911 u64_stats_update_end(&hw_stats->syncp); 912 } 913 914 static void mtk_stats_update(struct mtk_eth *eth) 915 { 916 int i; 917 918 for (i = 0; i < MTK_MAC_COUNT; i++) { 919 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 920 continue; 921 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 922 mtk_stats_update_mac(eth->mac[i]); 923 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 924 } 925 } 926 } 927 928 static void mtk_get_stats64(struct net_device *dev, 929 struct rtnl_link_stats64 *storage) 930 { 931 struct mtk_mac *mac = netdev_priv(dev); 932 struct mtk_hw_stats *hw_stats = mac->hw_stats; 933 unsigned int start; 934 935 if (netif_running(dev) && netif_device_present(dev)) { 936 if (spin_trylock_bh(&hw_stats->stats_lock)) { 937 mtk_stats_update_mac(mac); 938 spin_unlock_bh(&hw_stats->stats_lock); 939 } 940 } 941 942 do { 943 start = u64_stats_fetch_begin(&hw_stats->syncp); 944 storage->rx_packets = hw_stats->rx_packets; 945 storage->tx_packets = hw_stats->tx_packets; 946 storage->rx_bytes = hw_stats->rx_bytes; 947 storage->tx_bytes = hw_stats->tx_bytes; 948 storage->collisions = hw_stats->tx_collisions; 949 storage->rx_length_errors = hw_stats->rx_short_errors + 950 hw_stats->rx_long_errors; 951 storage->rx_over_errors = hw_stats->rx_overflow; 952 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 953 storage->rx_errors = hw_stats->rx_checksum_errors; 954 storage->tx_aborted_errors = hw_stats->tx_skip; 955 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 956 957 storage->tx_errors = dev->stats.tx_errors; 958 storage->rx_dropped = dev->stats.rx_dropped; 959 storage->tx_dropped = dev->stats.tx_dropped; 960 } 961 962 static inline int mtk_max_frag_size(int mtu) 963 { 964 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 965 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 966 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 967 968 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 969 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 970 } 971 972 static inline int mtk_max_buf_size(int frag_size) 973 { 974 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 975 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 976 977 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 978 979 return buf_size; 980 } 981 982 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 983 struct mtk_rx_dma_v2 *dma_rxd) 984 { 985 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 986 if (!(rxd->rxd2 & RX_DMA_DONE)) 987 return false; 988 989 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 990 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 991 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 992 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 993 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 994 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 995 } 996 997 return true; 998 } 999 1000 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1001 { 1002 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1003 unsigned long data; 1004 1005 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1006 get_order(size)); 1007 1008 return (void *)data; 1009 } 1010 1011 /* the qdma core needs scratch memory to be setup */ 1012 static int mtk_init_fq_dma(struct mtk_eth *eth) 1013 { 1014 const struct mtk_soc_data *soc = eth->soc; 1015 dma_addr_t phy_ring_tail; 1016 int cnt = MTK_QDMA_RING_SIZE; 1017 dma_addr_t dma_addr; 1018 int i; 1019 1020 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1021 cnt * soc->txrx.txd_size, 1022 ð->phy_scratch_ring, 1023 GFP_KERNEL); 1024 if (unlikely(!eth->scratch_ring)) 1025 return -ENOMEM; 1026 1027 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1028 if (unlikely(!eth->scratch_head)) 1029 return -ENOMEM; 1030 1031 dma_addr = dma_map_single(eth->dma_dev, 1032 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 1033 DMA_FROM_DEVICE); 1034 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1035 return -ENOMEM; 1036 1037 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 1038 1039 for (i = 0; i < cnt; i++) { 1040 struct mtk_tx_dma_v2 *txd; 1041 1042 txd = eth->scratch_ring + i * soc->txrx.txd_size; 1043 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1044 if (i < cnt - 1) 1045 txd->txd2 = eth->phy_scratch_ring + 1046 (i + 1) * soc->txrx.txd_size; 1047 1048 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1049 txd->txd4 = 0; 1050 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 1051 txd->txd5 = 0; 1052 txd->txd6 = 0; 1053 txd->txd7 = 0; 1054 txd->txd8 = 0; 1055 } 1056 } 1057 1058 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1059 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1060 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1061 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1062 1063 return 0; 1064 } 1065 1066 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1067 { 1068 return ring->dma + (desc - ring->phys); 1069 } 1070 1071 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1072 void *txd, u32 txd_size) 1073 { 1074 int idx = (txd - ring->dma) / txd_size; 1075 1076 return &ring->buf[idx]; 1077 } 1078 1079 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1080 struct mtk_tx_dma *dma) 1081 { 1082 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1083 } 1084 1085 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1086 { 1087 return (dma - ring->dma) / txd_size; 1088 } 1089 1090 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1091 struct xdp_frame_bulk *bq, bool napi) 1092 { 1093 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1094 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1095 dma_unmap_single(eth->dma_dev, 1096 dma_unmap_addr(tx_buf, dma_addr0), 1097 dma_unmap_len(tx_buf, dma_len0), 1098 DMA_TO_DEVICE); 1099 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1100 dma_unmap_page(eth->dma_dev, 1101 dma_unmap_addr(tx_buf, dma_addr0), 1102 dma_unmap_len(tx_buf, dma_len0), 1103 DMA_TO_DEVICE); 1104 } 1105 } else { 1106 if (dma_unmap_len(tx_buf, dma_len0)) { 1107 dma_unmap_page(eth->dma_dev, 1108 dma_unmap_addr(tx_buf, dma_addr0), 1109 dma_unmap_len(tx_buf, dma_len0), 1110 DMA_TO_DEVICE); 1111 } 1112 1113 if (dma_unmap_len(tx_buf, dma_len1)) { 1114 dma_unmap_page(eth->dma_dev, 1115 dma_unmap_addr(tx_buf, dma_addr1), 1116 dma_unmap_len(tx_buf, dma_len1), 1117 DMA_TO_DEVICE); 1118 } 1119 } 1120 1121 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1122 if (tx_buf->type == MTK_TYPE_SKB) { 1123 struct sk_buff *skb = tx_buf->data; 1124 1125 if (napi) 1126 napi_consume_skb(skb, napi); 1127 else 1128 dev_kfree_skb_any(skb); 1129 } else { 1130 struct xdp_frame *xdpf = tx_buf->data; 1131 1132 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1133 xdp_return_frame_rx_napi(xdpf); 1134 else if (bq) 1135 xdp_return_frame_bulk(xdpf, bq); 1136 else 1137 xdp_return_frame(xdpf); 1138 } 1139 } 1140 tx_buf->flags = 0; 1141 tx_buf->data = NULL; 1142 } 1143 1144 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1145 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1146 size_t size, int idx) 1147 { 1148 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1149 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1150 dma_unmap_len_set(tx_buf, dma_len0, size); 1151 } else { 1152 if (idx & 1) { 1153 txd->txd3 = mapped_addr; 1154 txd->txd2 |= TX_DMA_PLEN1(size); 1155 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1156 dma_unmap_len_set(tx_buf, dma_len1, size); 1157 } else { 1158 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1159 txd->txd1 = mapped_addr; 1160 txd->txd2 = TX_DMA_PLEN0(size); 1161 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1162 dma_unmap_len_set(tx_buf, dma_len0, size); 1163 } 1164 } 1165 } 1166 1167 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1168 struct mtk_tx_dma_desc_info *info) 1169 { 1170 struct mtk_mac *mac = netdev_priv(dev); 1171 struct mtk_eth *eth = mac->hw; 1172 struct mtk_tx_dma *desc = txd; 1173 u32 data; 1174 1175 WRITE_ONCE(desc->txd1, info->addr); 1176 1177 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1178 FIELD_PREP(TX_DMA_PQID, info->qid); 1179 if (info->last) 1180 data |= TX_DMA_LS0; 1181 WRITE_ONCE(desc->txd3, data); 1182 1183 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1184 if (info->first) { 1185 if (info->gso) 1186 data |= TX_DMA_TSO; 1187 /* tx checksum offload */ 1188 if (info->csum) 1189 data |= TX_DMA_CHKSUM; 1190 /* vlan header offload */ 1191 if (info->vlan) 1192 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1193 } 1194 WRITE_ONCE(desc->txd4, data); 1195 } 1196 1197 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1198 struct mtk_tx_dma_desc_info *info) 1199 { 1200 struct mtk_mac *mac = netdev_priv(dev); 1201 struct mtk_tx_dma_v2 *desc = txd; 1202 struct mtk_eth *eth = mac->hw; 1203 u32 data; 1204 1205 WRITE_ONCE(desc->txd1, info->addr); 1206 1207 data = TX_DMA_PLEN0(info->size); 1208 if (info->last) 1209 data |= TX_DMA_LS0; 1210 WRITE_ONCE(desc->txd3, data); 1211 1212 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ 1213 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1214 WRITE_ONCE(desc->txd4, data); 1215 1216 data = 0; 1217 if (info->first) { 1218 if (info->gso) 1219 data |= TX_DMA_TSO_V2; 1220 /* tx checksum offload */ 1221 if (info->csum) 1222 data |= TX_DMA_CHKSUM_V2; 1223 } 1224 WRITE_ONCE(desc->txd5, data); 1225 1226 data = 0; 1227 if (info->first && info->vlan) 1228 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1229 WRITE_ONCE(desc->txd6, data); 1230 1231 WRITE_ONCE(desc->txd7, 0); 1232 WRITE_ONCE(desc->txd8, 0); 1233 } 1234 1235 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1236 struct mtk_tx_dma_desc_info *info) 1237 { 1238 struct mtk_mac *mac = netdev_priv(dev); 1239 struct mtk_eth *eth = mac->hw; 1240 1241 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1242 mtk_tx_set_dma_desc_v2(dev, txd, info); 1243 else 1244 mtk_tx_set_dma_desc_v1(dev, txd, info); 1245 } 1246 1247 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1248 int tx_num, struct mtk_tx_ring *ring, bool gso) 1249 { 1250 struct mtk_tx_dma_desc_info txd_info = { 1251 .size = skb_headlen(skb), 1252 .gso = gso, 1253 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1254 .vlan = skb_vlan_tag_present(skb), 1255 .qid = skb_get_queue_mapping(skb), 1256 .vlan_tci = skb_vlan_tag_get(skb), 1257 .first = true, 1258 .last = !skb_is_nonlinear(skb), 1259 }; 1260 struct netdev_queue *txq; 1261 struct mtk_mac *mac = netdev_priv(dev); 1262 struct mtk_eth *eth = mac->hw; 1263 const struct mtk_soc_data *soc = eth->soc; 1264 struct mtk_tx_dma *itxd, *txd; 1265 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1266 struct mtk_tx_buf *itx_buf, *tx_buf; 1267 int i, n_desc = 1; 1268 int queue = skb_get_queue_mapping(skb); 1269 int k = 0; 1270 1271 txq = netdev_get_tx_queue(dev, queue); 1272 itxd = ring->next_free; 1273 itxd_pdma = qdma_to_pdma(ring, itxd); 1274 if (itxd == ring->last_free) 1275 return -ENOMEM; 1276 1277 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1278 memset(itx_buf, 0, sizeof(*itx_buf)); 1279 1280 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1281 DMA_TO_DEVICE); 1282 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1283 return -ENOMEM; 1284 1285 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1286 1287 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1288 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1289 MTK_TX_FLAGS_FPORT1; 1290 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1291 k++); 1292 1293 /* TX SG offload */ 1294 txd = itxd; 1295 txd_pdma = qdma_to_pdma(ring, txd); 1296 1297 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1298 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1299 unsigned int offset = 0; 1300 int frag_size = skb_frag_size(frag); 1301 1302 while (frag_size) { 1303 bool new_desc = true; 1304 1305 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1306 (i & 0x1)) { 1307 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1308 txd_pdma = qdma_to_pdma(ring, txd); 1309 if (txd == ring->last_free) 1310 goto err_dma; 1311 1312 n_desc++; 1313 } else { 1314 new_desc = false; 1315 } 1316 1317 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1318 txd_info.size = min_t(unsigned int, frag_size, 1319 soc->txrx.dma_max_len); 1320 txd_info.qid = queue; 1321 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1322 !(frag_size - txd_info.size); 1323 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1324 offset, txd_info.size, 1325 DMA_TO_DEVICE); 1326 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1327 goto err_dma; 1328 1329 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1330 1331 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1332 soc->txrx.txd_size); 1333 if (new_desc) 1334 memset(tx_buf, 0, sizeof(*tx_buf)); 1335 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1336 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1337 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1338 MTK_TX_FLAGS_FPORT1; 1339 1340 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1341 txd_info.size, k++); 1342 1343 frag_size -= txd_info.size; 1344 offset += txd_info.size; 1345 } 1346 } 1347 1348 /* store skb to cleanup */ 1349 itx_buf->type = MTK_TYPE_SKB; 1350 itx_buf->data = skb; 1351 1352 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1353 if (k & 0x1) 1354 txd_pdma->txd2 |= TX_DMA_LS0; 1355 else 1356 txd_pdma->txd2 |= TX_DMA_LS1; 1357 } 1358 1359 netdev_tx_sent_queue(txq, skb->len); 1360 skb_tx_timestamp(skb); 1361 1362 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1363 atomic_sub(n_desc, &ring->free_count); 1364 1365 /* make sure that all changes to the dma ring are flushed before we 1366 * continue 1367 */ 1368 wmb(); 1369 1370 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1371 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1372 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1373 } else { 1374 int next_idx; 1375 1376 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1377 ring->dma_size); 1378 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1379 } 1380 1381 return 0; 1382 1383 err_dma: 1384 do { 1385 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1386 1387 /* unmap dma */ 1388 mtk_tx_unmap(eth, tx_buf, NULL, false); 1389 1390 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1391 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1392 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1393 1394 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1395 itxd_pdma = qdma_to_pdma(ring, itxd); 1396 } while (itxd != txd); 1397 1398 return -ENOMEM; 1399 } 1400 1401 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1402 { 1403 int i, nfrags = 1; 1404 skb_frag_t *frag; 1405 1406 if (skb_is_gso(skb)) { 1407 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1408 frag = &skb_shinfo(skb)->frags[i]; 1409 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1410 eth->soc->txrx.dma_max_len); 1411 } 1412 } else { 1413 nfrags += skb_shinfo(skb)->nr_frags; 1414 } 1415 1416 return nfrags; 1417 } 1418 1419 static int mtk_queue_stopped(struct mtk_eth *eth) 1420 { 1421 int i; 1422 1423 for (i = 0; i < MTK_MAC_COUNT; i++) { 1424 if (!eth->netdev[i]) 1425 continue; 1426 if (netif_queue_stopped(eth->netdev[i])) 1427 return 1; 1428 } 1429 1430 return 0; 1431 } 1432 1433 static void mtk_wake_queue(struct mtk_eth *eth) 1434 { 1435 int i; 1436 1437 for (i = 0; i < MTK_MAC_COUNT; i++) { 1438 if (!eth->netdev[i]) 1439 continue; 1440 netif_tx_wake_all_queues(eth->netdev[i]); 1441 } 1442 } 1443 1444 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1445 { 1446 struct mtk_mac *mac = netdev_priv(dev); 1447 struct mtk_eth *eth = mac->hw; 1448 struct mtk_tx_ring *ring = ð->tx_ring; 1449 struct net_device_stats *stats = &dev->stats; 1450 bool gso = false; 1451 int tx_num; 1452 1453 /* normally we can rely on the stack not calling this more than once, 1454 * however we have 2 queues running on the same ring so we need to lock 1455 * the ring access 1456 */ 1457 spin_lock(ð->page_lock); 1458 1459 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1460 goto drop; 1461 1462 tx_num = mtk_cal_txd_req(eth, skb); 1463 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1464 netif_tx_stop_all_queues(dev); 1465 netif_err(eth, tx_queued, dev, 1466 "Tx Ring full when queue awake!\n"); 1467 spin_unlock(ð->page_lock); 1468 return NETDEV_TX_BUSY; 1469 } 1470 1471 /* TSO: fill MSS info in tcp checksum field */ 1472 if (skb_is_gso(skb)) { 1473 if (skb_cow_head(skb, 0)) { 1474 netif_warn(eth, tx_err, dev, 1475 "GSO expand head fail.\n"); 1476 goto drop; 1477 } 1478 1479 if (skb_shinfo(skb)->gso_type & 1480 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1481 gso = true; 1482 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1483 } 1484 } 1485 1486 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1487 goto drop; 1488 1489 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1490 netif_tx_stop_all_queues(dev); 1491 1492 spin_unlock(ð->page_lock); 1493 1494 return NETDEV_TX_OK; 1495 1496 drop: 1497 spin_unlock(ð->page_lock); 1498 stats->tx_dropped++; 1499 dev_kfree_skb_any(skb); 1500 return NETDEV_TX_OK; 1501 } 1502 1503 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1504 { 1505 int i; 1506 struct mtk_rx_ring *ring; 1507 int idx; 1508 1509 if (!eth->hwlro) 1510 return ð->rx_ring[0]; 1511 1512 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1513 struct mtk_rx_dma *rxd; 1514 1515 ring = ð->rx_ring[i]; 1516 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1517 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1518 if (rxd->rxd2 & RX_DMA_DONE) { 1519 ring->calc_idx_update = true; 1520 return ring; 1521 } 1522 } 1523 1524 return NULL; 1525 } 1526 1527 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1528 { 1529 struct mtk_rx_ring *ring; 1530 int i; 1531 1532 if (!eth->hwlro) { 1533 ring = ð->rx_ring[0]; 1534 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1535 } else { 1536 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1537 ring = ð->rx_ring[i]; 1538 if (ring->calc_idx_update) { 1539 ring->calc_idx_update = false; 1540 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1541 } 1542 } 1543 } 1544 } 1545 1546 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1547 { 1548 return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2); 1549 } 1550 1551 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1552 struct xdp_rxq_info *xdp_q, 1553 int id, int size) 1554 { 1555 struct page_pool_params pp_params = { 1556 .order = 0, 1557 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1558 .pool_size = size, 1559 .nid = NUMA_NO_NODE, 1560 .dev = eth->dma_dev, 1561 .offset = MTK_PP_HEADROOM, 1562 .max_len = MTK_PP_MAX_BUF_SIZE, 1563 }; 1564 struct page_pool *pp; 1565 int err; 1566 1567 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1568 : DMA_FROM_DEVICE; 1569 pp = page_pool_create(&pp_params); 1570 if (IS_ERR(pp)) 1571 return pp; 1572 1573 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, eth->rx_napi.napi_id, 1574 id, PAGE_SIZE); 1575 if (err < 0) 1576 goto err_free_pp; 1577 1578 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1579 if (err) 1580 goto err_unregister_rxq; 1581 1582 return pp; 1583 1584 err_unregister_rxq: 1585 xdp_rxq_info_unreg(xdp_q); 1586 err_free_pp: 1587 page_pool_destroy(pp); 1588 1589 return ERR_PTR(err); 1590 } 1591 1592 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1593 gfp_t gfp_mask) 1594 { 1595 struct page *page; 1596 1597 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1598 if (!page) 1599 return NULL; 1600 1601 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1602 return page_address(page); 1603 } 1604 1605 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1606 { 1607 if (ring->page_pool) 1608 page_pool_put_full_page(ring->page_pool, 1609 virt_to_head_page(data), napi); 1610 else 1611 skb_free_frag(data); 1612 } 1613 1614 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1615 struct mtk_tx_dma_desc_info *txd_info, 1616 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1617 void *data, u16 headroom, int index, bool dma_map) 1618 { 1619 struct mtk_tx_ring *ring = ð->tx_ring; 1620 struct mtk_mac *mac = netdev_priv(dev); 1621 struct mtk_tx_dma *txd_pdma; 1622 1623 if (dma_map) { /* ndo_xdp_xmit */ 1624 txd_info->addr = dma_map_single(eth->dma_dev, data, 1625 txd_info->size, DMA_TO_DEVICE); 1626 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1627 return -ENOMEM; 1628 1629 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1630 } else { 1631 struct page *page = virt_to_head_page(data); 1632 1633 txd_info->addr = page_pool_get_dma_addr(page) + 1634 sizeof(struct xdp_frame) + headroom; 1635 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1636 txd_info->size, DMA_BIDIRECTIONAL); 1637 } 1638 mtk_tx_set_dma_desc(dev, txd, txd_info); 1639 1640 tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; 1641 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1642 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1643 1644 txd_pdma = qdma_to_pdma(ring, txd); 1645 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1646 index); 1647 1648 return 0; 1649 } 1650 1651 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1652 struct net_device *dev, bool dma_map) 1653 { 1654 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1655 const struct mtk_soc_data *soc = eth->soc; 1656 struct mtk_tx_ring *ring = ð->tx_ring; 1657 struct mtk_mac *mac = netdev_priv(dev); 1658 struct mtk_tx_dma_desc_info txd_info = { 1659 .size = xdpf->len, 1660 .first = true, 1661 .last = !xdp_frame_has_frags(xdpf), 1662 .qid = mac->id, 1663 }; 1664 int err, index = 0, n_desc = 1, nr_frags; 1665 struct mtk_tx_buf *htx_buf, *tx_buf; 1666 struct mtk_tx_dma *htxd, *txd; 1667 void *data = xdpf->data; 1668 1669 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1670 return -EBUSY; 1671 1672 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1673 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1674 return -EBUSY; 1675 1676 spin_lock(ð->page_lock); 1677 1678 txd = ring->next_free; 1679 if (txd == ring->last_free) { 1680 spin_unlock(ð->page_lock); 1681 return -ENOMEM; 1682 } 1683 htxd = txd; 1684 1685 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1686 memset(tx_buf, 0, sizeof(*tx_buf)); 1687 htx_buf = tx_buf; 1688 1689 for (;;) { 1690 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1691 data, xdpf->headroom, index, dma_map); 1692 if (err < 0) 1693 goto unmap; 1694 1695 if (txd_info.last) 1696 break; 1697 1698 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1699 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1700 if (txd == ring->last_free) 1701 goto unmap; 1702 1703 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1704 soc->txrx.txd_size); 1705 memset(tx_buf, 0, sizeof(*tx_buf)); 1706 n_desc++; 1707 } 1708 1709 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1710 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1711 txd_info.last = index + 1 == nr_frags; 1712 txd_info.qid = mac->id; 1713 data = skb_frag_address(&sinfo->frags[index]); 1714 1715 index++; 1716 } 1717 /* store xdpf for cleanup */ 1718 htx_buf->data = xdpf; 1719 1720 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1721 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1722 1723 if (index & 1) 1724 txd_pdma->txd2 |= TX_DMA_LS0; 1725 else 1726 txd_pdma->txd2 |= TX_DMA_LS1; 1727 } 1728 1729 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1730 atomic_sub(n_desc, &ring->free_count); 1731 1732 /* make sure that all changes to the dma ring are flushed before we 1733 * continue 1734 */ 1735 wmb(); 1736 1737 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1738 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1739 } else { 1740 int idx; 1741 1742 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1743 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1744 MT7628_TX_CTX_IDX0); 1745 } 1746 1747 spin_unlock(ð->page_lock); 1748 1749 return 0; 1750 1751 unmap: 1752 while (htxd != txd) { 1753 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1754 mtk_tx_unmap(eth, tx_buf, NULL, false); 1755 1756 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1757 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1758 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1759 1760 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1761 } 1762 1763 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1764 } 1765 1766 spin_unlock(ð->page_lock); 1767 1768 return err; 1769 } 1770 1771 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1772 struct xdp_frame **frames, u32 flags) 1773 { 1774 struct mtk_mac *mac = netdev_priv(dev); 1775 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1776 struct mtk_eth *eth = mac->hw; 1777 int i, nxmit = 0; 1778 1779 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1780 return -EINVAL; 1781 1782 for (i = 0; i < num_frame; i++) { 1783 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1784 break; 1785 nxmit++; 1786 } 1787 1788 u64_stats_update_begin(&hw_stats->syncp); 1789 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1790 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1791 u64_stats_update_end(&hw_stats->syncp); 1792 1793 return nxmit; 1794 } 1795 1796 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1797 struct xdp_buff *xdp, struct net_device *dev) 1798 { 1799 struct mtk_mac *mac = netdev_priv(dev); 1800 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1801 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1802 struct bpf_prog *prog; 1803 u32 act = XDP_PASS; 1804 1805 rcu_read_lock(); 1806 1807 prog = rcu_dereference(eth->prog); 1808 if (!prog) 1809 goto out; 1810 1811 act = bpf_prog_run_xdp(prog, xdp); 1812 switch (act) { 1813 case XDP_PASS: 1814 count = &hw_stats->xdp_stats.rx_xdp_pass; 1815 goto update_stats; 1816 case XDP_REDIRECT: 1817 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1818 act = XDP_DROP; 1819 break; 1820 } 1821 1822 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1823 goto update_stats; 1824 case XDP_TX: { 1825 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1826 1827 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1828 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1829 act = XDP_DROP; 1830 break; 1831 } 1832 1833 count = &hw_stats->xdp_stats.rx_xdp_tx; 1834 goto update_stats; 1835 } 1836 default: 1837 bpf_warn_invalid_xdp_action(dev, prog, act); 1838 fallthrough; 1839 case XDP_ABORTED: 1840 trace_xdp_exception(dev, prog, act); 1841 fallthrough; 1842 case XDP_DROP: 1843 break; 1844 } 1845 1846 page_pool_put_full_page(ring->page_pool, 1847 virt_to_head_page(xdp->data), true); 1848 1849 update_stats: 1850 u64_stats_update_begin(&hw_stats->syncp); 1851 *count = *count + 1; 1852 u64_stats_update_end(&hw_stats->syncp); 1853 out: 1854 rcu_read_unlock(); 1855 1856 return act; 1857 } 1858 1859 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1860 struct mtk_eth *eth) 1861 { 1862 struct dim_sample dim_sample = {}; 1863 struct mtk_rx_ring *ring; 1864 bool xdp_flush = false; 1865 int idx; 1866 struct sk_buff *skb; 1867 u8 *data, *new_data; 1868 struct mtk_rx_dma_v2 *rxd, trxd; 1869 int done = 0, bytes = 0; 1870 1871 while (done < budget) { 1872 unsigned int pktlen, *rxdcsum; 1873 struct net_device *netdev; 1874 dma_addr_t dma_addr; 1875 u32 hash, reason; 1876 int mac = 0; 1877 1878 ring = mtk_get_rx_ring(eth); 1879 if (unlikely(!ring)) 1880 goto rx_done; 1881 1882 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1883 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1884 data = ring->data[idx]; 1885 1886 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 1887 break; 1888 1889 /* find out which mac the packet come from. values start at 1 */ 1890 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1891 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; 1892 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 1893 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1894 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 1895 1896 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1897 !eth->netdev[mac])) 1898 goto release_desc; 1899 1900 netdev = eth->netdev[mac]; 1901 1902 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1903 goto release_desc; 1904 1905 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1906 1907 /* alloc new buffer */ 1908 if (ring->page_pool) { 1909 struct page *page = virt_to_head_page(data); 1910 struct xdp_buff xdp; 1911 u32 ret; 1912 1913 new_data = mtk_page_pool_get_buff(ring->page_pool, 1914 &dma_addr, 1915 GFP_ATOMIC); 1916 if (unlikely(!new_data)) { 1917 netdev->stats.rx_dropped++; 1918 goto release_desc; 1919 } 1920 1921 dma_sync_single_for_cpu(eth->dma_dev, 1922 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 1923 pktlen, page_pool_get_dma_dir(ring->page_pool)); 1924 1925 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 1926 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 1927 false); 1928 xdp_buff_clear_frags_flag(&xdp); 1929 1930 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 1931 if (ret == XDP_REDIRECT) 1932 xdp_flush = true; 1933 1934 if (ret != XDP_PASS) 1935 goto skip_rx; 1936 1937 skb = build_skb(data, PAGE_SIZE); 1938 if (unlikely(!skb)) { 1939 page_pool_put_full_page(ring->page_pool, 1940 page, true); 1941 netdev->stats.rx_dropped++; 1942 goto skip_rx; 1943 } 1944 1945 skb_reserve(skb, xdp.data - xdp.data_hard_start); 1946 skb_put(skb, xdp.data_end - xdp.data); 1947 skb_mark_for_recycle(skb); 1948 } else { 1949 if (ring->frag_size <= PAGE_SIZE) 1950 new_data = napi_alloc_frag(ring->frag_size); 1951 else 1952 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 1953 1954 if (unlikely(!new_data)) { 1955 netdev->stats.rx_dropped++; 1956 goto release_desc; 1957 } 1958 1959 dma_addr = dma_map_single(eth->dma_dev, 1960 new_data + NET_SKB_PAD + eth->ip_align, 1961 ring->buf_size, DMA_FROM_DEVICE); 1962 if (unlikely(dma_mapping_error(eth->dma_dev, 1963 dma_addr))) { 1964 skb_free_frag(new_data); 1965 netdev->stats.rx_dropped++; 1966 goto release_desc; 1967 } 1968 1969 dma_unmap_single(eth->dma_dev, trxd.rxd1, 1970 ring->buf_size, DMA_FROM_DEVICE); 1971 1972 skb = build_skb(data, ring->frag_size); 1973 if (unlikely(!skb)) { 1974 netdev->stats.rx_dropped++; 1975 skb_free_frag(data); 1976 goto skip_rx; 1977 } 1978 1979 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1980 skb_put(skb, pktlen); 1981 } 1982 1983 skb->dev = netdev; 1984 bytes += skb->len; 1985 1986 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1987 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 1988 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 1989 if (hash != MTK_RXD5_FOE_ENTRY) 1990 skb_set_hash(skb, jhash_1word(hash, 0), 1991 PKT_HASH_TYPE_L4); 1992 rxdcsum = &trxd.rxd3; 1993 } else { 1994 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 1995 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 1996 if (hash != MTK_RXD4_FOE_ENTRY) 1997 skb_set_hash(skb, jhash_1word(hash, 0), 1998 PKT_HASH_TYPE_L4); 1999 rxdcsum = &trxd.rxd4; 2000 } 2001 2002 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 2003 skb->ip_summed = CHECKSUM_UNNECESSARY; 2004 else 2005 skb_checksum_none_assert(skb); 2006 skb->protocol = eth_type_trans(skb, netdev); 2007 2008 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2009 mtk_ppe_check_skb(eth->ppe[0], skb, hash); 2010 2011 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2012 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2013 if (trxd.rxd3 & RX_DMA_VTAG_V2) 2014 __vlan_hwaccel_put_tag(skb, 2015 htons(RX_DMA_VPID(trxd.rxd4)), 2016 RX_DMA_VID(trxd.rxd4)); 2017 } else if (trxd.rxd2 & RX_DMA_VTAG) { 2018 __vlan_hwaccel_put_tag(skb, htons(RX_DMA_VPID(trxd.rxd3)), 2019 RX_DMA_VID(trxd.rxd3)); 2020 } 2021 } 2022 2023 /* When using VLAN untagging in combination with DSA, the 2024 * hardware treats the MTK special tag as a VLAN and untags it. 2025 */ 2026 if (skb_vlan_tag_present(skb) && netdev_uses_dsa(netdev)) { 2027 unsigned int port = ntohs(skb->vlan_proto) & GENMASK(2, 0); 2028 2029 if (port < ARRAY_SIZE(eth->dsa_meta) && 2030 eth->dsa_meta[port]) 2031 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2032 2033 __vlan_hwaccel_clear_tag(skb); 2034 } 2035 2036 skb_record_rx_queue(skb, 0); 2037 napi_gro_receive(napi, skb); 2038 2039 skip_rx: 2040 ring->data[idx] = new_data; 2041 rxd->rxd1 = (unsigned int)dma_addr; 2042 release_desc: 2043 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2044 rxd->rxd2 = RX_DMA_LSO; 2045 else 2046 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2047 2048 ring->calc_idx = idx; 2049 done++; 2050 } 2051 2052 rx_done: 2053 if (done) { 2054 /* make sure that all changes to the dma ring are flushed before 2055 * we continue 2056 */ 2057 wmb(); 2058 mtk_update_rx_cpu_idx(eth); 2059 } 2060 2061 eth->rx_packets += done; 2062 eth->rx_bytes += bytes; 2063 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2064 &dim_sample); 2065 net_dim(ð->rx_dim, dim_sample); 2066 2067 if (xdp_flush) 2068 xdp_do_flush_map(); 2069 2070 return done; 2071 } 2072 2073 struct mtk_poll_state { 2074 struct netdev_queue *txq; 2075 unsigned int total; 2076 unsigned int done; 2077 unsigned int bytes; 2078 }; 2079 2080 static void 2081 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2082 struct sk_buff *skb) 2083 { 2084 struct netdev_queue *txq; 2085 struct net_device *dev; 2086 unsigned int bytes = skb->len; 2087 2088 state->total++; 2089 eth->tx_packets++; 2090 eth->tx_bytes += bytes; 2091 2092 dev = eth->netdev[mac]; 2093 if (!dev) 2094 return; 2095 2096 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2097 if (state->txq == txq) { 2098 state->done++; 2099 state->bytes += bytes; 2100 return; 2101 } 2102 2103 if (state->txq) 2104 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2105 2106 state->txq = txq; 2107 state->done = 1; 2108 state->bytes = bytes; 2109 } 2110 2111 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2112 struct mtk_poll_state *state) 2113 { 2114 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2115 struct mtk_tx_ring *ring = ð->tx_ring; 2116 struct mtk_tx_buf *tx_buf; 2117 struct xdp_frame_bulk bq; 2118 struct mtk_tx_dma *desc; 2119 u32 cpu, dma; 2120 2121 cpu = ring->last_free_ptr; 2122 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2123 2124 desc = mtk_qdma_phys_to_virt(ring, cpu); 2125 xdp_frame_bulk_init(&bq); 2126 2127 while ((cpu != dma) && budget) { 2128 u32 next_cpu = desc->txd2; 2129 int mac = 0; 2130 2131 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2132 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2133 break; 2134 2135 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2136 eth->soc->txrx.txd_size); 2137 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 2138 mac = 1; 2139 2140 if (!tx_buf->data) 2141 break; 2142 2143 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2144 if (tx_buf->type == MTK_TYPE_SKB) 2145 mtk_poll_tx_done(eth, state, mac, tx_buf->data); 2146 2147 budget--; 2148 } 2149 mtk_tx_unmap(eth, tx_buf, &bq, true); 2150 2151 ring->last_free = desc; 2152 atomic_inc(&ring->free_count); 2153 2154 cpu = next_cpu; 2155 } 2156 xdp_flush_frame_bulk(&bq); 2157 2158 ring->last_free_ptr = cpu; 2159 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2160 2161 return budget; 2162 } 2163 2164 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2165 struct mtk_poll_state *state) 2166 { 2167 struct mtk_tx_ring *ring = ð->tx_ring; 2168 struct mtk_tx_buf *tx_buf; 2169 struct xdp_frame_bulk bq; 2170 struct mtk_tx_dma *desc; 2171 u32 cpu, dma; 2172 2173 cpu = ring->cpu_idx; 2174 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2175 xdp_frame_bulk_init(&bq); 2176 2177 while ((cpu != dma) && budget) { 2178 tx_buf = &ring->buf[cpu]; 2179 if (!tx_buf->data) 2180 break; 2181 2182 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2183 if (tx_buf->type == MTK_TYPE_SKB) 2184 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2185 budget--; 2186 } 2187 mtk_tx_unmap(eth, tx_buf, &bq, true); 2188 2189 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2190 ring->last_free = desc; 2191 atomic_inc(&ring->free_count); 2192 2193 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2194 } 2195 xdp_flush_frame_bulk(&bq); 2196 2197 ring->cpu_idx = cpu; 2198 2199 return budget; 2200 } 2201 2202 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2203 { 2204 struct mtk_tx_ring *ring = ð->tx_ring; 2205 struct dim_sample dim_sample = {}; 2206 struct mtk_poll_state state = {}; 2207 2208 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2209 budget = mtk_poll_tx_qdma(eth, budget, &state); 2210 else 2211 budget = mtk_poll_tx_pdma(eth, budget, &state); 2212 2213 if (state.txq) 2214 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2215 2216 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2217 &dim_sample); 2218 net_dim(ð->tx_dim, dim_sample); 2219 2220 if (mtk_queue_stopped(eth) && 2221 (atomic_read(&ring->free_count) > ring->thresh)) 2222 mtk_wake_queue(eth); 2223 2224 return state.total; 2225 } 2226 2227 static void mtk_handle_status_irq(struct mtk_eth *eth) 2228 { 2229 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2230 2231 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2232 mtk_stats_update(eth); 2233 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2234 MTK_INT_STATUS2); 2235 } 2236 } 2237 2238 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2239 { 2240 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2241 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2242 int tx_done = 0; 2243 2244 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2245 mtk_handle_status_irq(eth); 2246 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2247 tx_done = mtk_poll_tx(eth, budget); 2248 2249 if (unlikely(netif_msg_intr(eth))) { 2250 dev_info(eth->dev, 2251 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2252 mtk_r32(eth, reg_map->tx_irq_status), 2253 mtk_r32(eth, reg_map->tx_irq_mask)); 2254 } 2255 2256 if (tx_done == budget) 2257 return budget; 2258 2259 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2260 return budget; 2261 2262 if (napi_complete_done(napi, tx_done)) 2263 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2264 2265 return tx_done; 2266 } 2267 2268 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2269 { 2270 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2271 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2272 int rx_done_total = 0; 2273 2274 mtk_handle_status_irq(eth); 2275 2276 do { 2277 int rx_done; 2278 2279 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2280 reg_map->pdma.irq_status); 2281 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2282 rx_done_total += rx_done; 2283 2284 if (unlikely(netif_msg_intr(eth))) { 2285 dev_info(eth->dev, 2286 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2287 mtk_r32(eth, reg_map->pdma.irq_status), 2288 mtk_r32(eth, reg_map->pdma.irq_mask)); 2289 } 2290 2291 if (rx_done_total == budget) 2292 return budget; 2293 2294 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2295 eth->soc->txrx.rx_irq_done_mask); 2296 2297 if (napi_complete_done(napi, rx_done_total)) 2298 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2299 2300 return rx_done_total; 2301 } 2302 2303 static int mtk_tx_alloc(struct mtk_eth *eth) 2304 { 2305 const struct mtk_soc_data *soc = eth->soc; 2306 struct mtk_tx_ring *ring = ð->tx_ring; 2307 int i, sz = soc->txrx.txd_size; 2308 struct mtk_tx_dma_v2 *txd; 2309 int ring_size; 2310 u32 ofs, val; 2311 2312 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2313 ring_size = MTK_QDMA_RING_SIZE; 2314 else 2315 ring_size = MTK_DMA_SIZE; 2316 2317 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2318 GFP_KERNEL); 2319 if (!ring->buf) 2320 goto no_tx_mem; 2321 2322 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2323 &ring->phys, GFP_KERNEL); 2324 if (!ring->dma) 2325 goto no_tx_mem; 2326 2327 for (i = 0; i < ring_size; i++) { 2328 int next = (i + 1) % ring_size; 2329 u32 next_ptr = ring->phys + next * sz; 2330 2331 txd = ring->dma + i * sz; 2332 txd->txd2 = next_ptr; 2333 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2334 txd->txd4 = 0; 2335 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 2336 txd->txd5 = 0; 2337 txd->txd6 = 0; 2338 txd->txd7 = 0; 2339 txd->txd8 = 0; 2340 } 2341 } 2342 2343 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2344 * only as the framework. The real HW descriptors are the PDMA 2345 * descriptors in ring->dma_pdma. 2346 */ 2347 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2348 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2349 &ring->phys_pdma, GFP_KERNEL); 2350 if (!ring->dma_pdma) 2351 goto no_tx_mem; 2352 2353 for (i = 0; i < ring_size; i++) { 2354 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2355 ring->dma_pdma[i].txd4 = 0; 2356 } 2357 } 2358 2359 ring->dma_size = ring_size; 2360 atomic_set(&ring->free_count, ring_size - 2); 2361 ring->next_free = ring->dma; 2362 ring->last_free = (void *)txd; 2363 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2364 ring->thresh = MAX_SKB_FRAGS; 2365 2366 /* make sure that all changes to the dma ring are flushed before we 2367 * continue 2368 */ 2369 wmb(); 2370 2371 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2372 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2373 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2374 mtk_w32(eth, 2375 ring->phys + ((ring_size - 1) * sz), 2376 soc->reg_map->qdma.crx_ptr); 2377 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2378 2379 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2380 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2381 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2382 2383 val = MTK_QTX_SCH_MIN_RATE_EN | 2384 /* minimum: 10 Mbps */ 2385 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2386 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2387 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2388 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2389 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2390 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2391 ofs += MTK_QTX_OFFSET; 2392 } 2393 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2394 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2395 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2396 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2397 } else { 2398 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2399 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2400 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2401 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2402 } 2403 2404 return 0; 2405 2406 no_tx_mem: 2407 return -ENOMEM; 2408 } 2409 2410 static void mtk_tx_clean(struct mtk_eth *eth) 2411 { 2412 const struct mtk_soc_data *soc = eth->soc; 2413 struct mtk_tx_ring *ring = ð->tx_ring; 2414 int i; 2415 2416 if (ring->buf) { 2417 for (i = 0; i < ring->dma_size; i++) 2418 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2419 kfree(ring->buf); 2420 ring->buf = NULL; 2421 } 2422 2423 if (ring->dma) { 2424 dma_free_coherent(eth->dma_dev, 2425 ring->dma_size * soc->txrx.txd_size, 2426 ring->dma, ring->phys); 2427 ring->dma = NULL; 2428 } 2429 2430 if (ring->dma_pdma) { 2431 dma_free_coherent(eth->dma_dev, 2432 ring->dma_size * soc->txrx.txd_size, 2433 ring->dma_pdma, ring->phys_pdma); 2434 ring->dma_pdma = NULL; 2435 } 2436 } 2437 2438 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2439 { 2440 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2441 struct mtk_rx_ring *ring; 2442 int rx_data_len, rx_dma_size; 2443 int i; 2444 2445 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2446 if (ring_no) 2447 return -EINVAL; 2448 ring = ð->rx_ring_qdma; 2449 } else { 2450 ring = ð->rx_ring[ring_no]; 2451 } 2452 2453 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2454 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2455 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2456 } else { 2457 rx_data_len = ETH_DATA_LEN; 2458 rx_dma_size = MTK_DMA_SIZE; 2459 } 2460 2461 ring->frag_size = mtk_max_frag_size(rx_data_len); 2462 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2463 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2464 GFP_KERNEL); 2465 if (!ring->data) 2466 return -ENOMEM; 2467 2468 if (mtk_page_pool_enabled(eth)) { 2469 struct page_pool *pp; 2470 2471 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2472 rx_dma_size); 2473 if (IS_ERR(pp)) 2474 return PTR_ERR(pp); 2475 2476 ring->page_pool = pp; 2477 } 2478 2479 ring->dma = dma_alloc_coherent(eth->dma_dev, 2480 rx_dma_size * eth->soc->txrx.rxd_size, 2481 &ring->phys, GFP_KERNEL); 2482 if (!ring->dma) 2483 return -ENOMEM; 2484 2485 for (i = 0; i < rx_dma_size; i++) { 2486 struct mtk_rx_dma_v2 *rxd; 2487 dma_addr_t dma_addr; 2488 void *data; 2489 2490 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2491 if (ring->page_pool) { 2492 data = mtk_page_pool_get_buff(ring->page_pool, 2493 &dma_addr, GFP_KERNEL); 2494 if (!data) 2495 return -ENOMEM; 2496 } else { 2497 if (ring->frag_size <= PAGE_SIZE) 2498 data = netdev_alloc_frag(ring->frag_size); 2499 else 2500 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2501 2502 if (!data) 2503 return -ENOMEM; 2504 2505 dma_addr = dma_map_single(eth->dma_dev, 2506 data + NET_SKB_PAD + eth->ip_align, 2507 ring->buf_size, DMA_FROM_DEVICE); 2508 if (unlikely(dma_mapping_error(eth->dma_dev, 2509 dma_addr))) { 2510 skb_free_frag(data); 2511 return -ENOMEM; 2512 } 2513 } 2514 rxd->rxd1 = (unsigned int)dma_addr; 2515 ring->data[i] = data; 2516 2517 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2518 rxd->rxd2 = RX_DMA_LSO; 2519 else 2520 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2521 2522 rxd->rxd3 = 0; 2523 rxd->rxd4 = 0; 2524 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2525 rxd->rxd5 = 0; 2526 rxd->rxd6 = 0; 2527 rxd->rxd7 = 0; 2528 rxd->rxd8 = 0; 2529 } 2530 } 2531 2532 ring->dma_size = rx_dma_size; 2533 ring->calc_idx_update = false; 2534 ring->calc_idx = rx_dma_size - 1; 2535 if (rx_flag == MTK_RX_FLAGS_QDMA) 2536 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2537 ring_no * MTK_QRX_OFFSET; 2538 else 2539 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2540 ring_no * MTK_QRX_OFFSET; 2541 /* make sure that all changes to the dma ring are flushed before we 2542 * continue 2543 */ 2544 wmb(); 2545 2546 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2547 mtk_w32(eth, ring->phys, 2548 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2549 mtk_w32(eth, rx_dma_size, 2550 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2551 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2552 reg_map->qdma.rst_idx); 2553 } else { 2554 mtk_w32(eth, ring->phys, 2555 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2556 mtk_w32(eth, rx_dma_size, 2557 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2558 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2559 reg_map->pdma.rst_idx); 2560 } 2561 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2562 2563 return 0; 2564 } 2565 2566 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 2567 { 2568 int i; 2569 2570 if (ring->data && ring->dma) { 2571 for (i = 0; i < ring->dma_size; i++) { 2572 struct mtk_rx_dma *rxd; 2573 2574 if (!ring->data[i]) 2575 continue; 2576 2577 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2578 if (!rxd->rxd1) 2579 continue; 2580 2581 dma_unmap_single(eth->dma_dev, rxd->rxd1, 2582 ring->buf_size, DMA_FROM_DEVICE); 2583 mtk_rx_put_buff(ring, ring->data[i], false); 2584 } 2585 kfree(ring->data); 2586 ring->data = NULL; 2587 } 2588 2589 if (ring->dma) { 2590 dma_free_coherent(eth->dma_dev, 2591 ring->dma_size * eth->soc->txrx.rxd_size, 2592 ring->dma, ring->phys); 2593 ring->dma = NULL; 2594 } 2595 2596 if (ring->page_pool) { 2597 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2598 xdp_rxq_info_unreg(&ring->xdp_q); 2599 page_pool_destroy(ring->page_pool); 2600 ring->page_pool = NULL; 2601 } 2602 } 2603 2604 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2605 { 2606 int i; 2607 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2608 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2609 2610 /* set LRO rings to auto-learn modes */ 2611 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2612 2613 /* validate LRO ring */ 2614 ring_ctrl_dw2 |= MTK_RING_VLD; 2615 2616 /* set AGE timer (unit: 20us) */ 2617 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2618 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2619 2620 /* set max AGG timer (unit: 20us) */ 2621 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2622 2623 /* set max LRO AGG count */ 2624 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2625 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2626 2627 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2628 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2629 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2630 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2631 } 2632 2633 /* IPv4 checksum update enable */ 2634 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2635 2636 /* switch priority comparison to packet count mode */ 2637 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2638 2639 /* bandwidth threshold setting */ 2640 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2641 2642 /* auto-learn score delta setting */ 2643 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2644 2645 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2646 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2647 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2648 2649 /* set HW LRO mode & the max aggregation count for rx packets */ 2650 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2651 2652 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2653 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2654 2655 /* enable HW LRO */ 2656 lro_ctrl_dw0 |= MTK_LRO_EN; 2657 2658 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2659 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2660 2661 return 0; 2662 } 2663 2664 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2665 { 2666 int i; 2667 u32 val; 2668 2669 /* relinquish lro rings, flush aggregated packets */ 2670 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2671 2672 /* wait for relinquishments done */ 2673 for (i = 0; i < 10; i++) { 2674 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2675 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2676 msleep(20); 2677 continue; 2678 } 2679 break; 2680 } 2681 2682 /* invalidate lro rings */ 2683 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2684 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2685 2686 /* disable HW LRO */ 2687 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2688 } 2689 2690 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2691 { 2692 u32 reg_val; 2693 2694 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2695 2696 /* invalidate the IP setting */ 2697 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2698 2699 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2700 2701 /* validate the IP setting */ 2702 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2703 } 2704 2705 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2706 { 2707 u32 reg_val; 2708 2709 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2710 2711 /* invalidate the IP setting */ 2712 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2713 2714 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2715 } 2716 2717 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2718 { 2719 int cnt = 0; 2720 int i; 2721 2722 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2723 if (mac->hwlro_ip[i]) 2724 cnt++; 2725 } 2726 2727 return cnt; 2728 } 2729 2730 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2731 struct ethtool_rxnfc *cmd) 2732 { 2733 struct ethtool_rx_flow_spec *fsp = 2734 (struct ethtool_rx_flow_spec *)&cmd->fs; 2735 struct mtk_mac *mac = netdev_priv(dev); 2736 struct mtk_eth *eth = mac->hw; 2737 int hwlro_idx; 2738 2739 if ((fsp->flow_type != TCP_V4_FLOW) || 2740 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2741 (fsp->location > 1)) 2742 return -EINVAL; 2743 2744 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2745 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2746 2747 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2748 2749 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2750 2751 return 0; 2752 } 2753 2754 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2755 struct ethtool_rxnfc *cmd) 2756 { 2757 struct ethtool_rx_flow_spec *fsp = 2758 (struct ethtool_rx_flow_spec *)&cmd->fs; 2759 struct mtk_mac *mac = netdev_priv(dev); 2760 struct mtk_eth *eth = mac->hw; 2761 int hwlro_idx; 2762 2763 if (fsp->location > 1) 2764 return -EINVAL; 2765 2766 mac->hwlro_ip[fsp->location] = 0; 2767 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2768 2769 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2770 2771 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2772 2773 return 0; 2774 } 2775 2776 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2777 { 2778 struct mtk_mac *mac = netdev_priv(dev); 2779 struct mtk_eth *eth = mac->hw; 2780 int i, hwlro_idx; 2781 2782 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2783 mac->hwlro_ip[i] = 0; 2784 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2785 2786 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2787 } 2788 2789 mac->hwlro_ip_cnt = 0; 2790 } 2791 2792 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2793 struct ethtool_rxnfc *cmd) 2794 { 2795 struct mtk_mac *mac = netdev_priv(dev); 2796 struct ethtool_rx_flow_spec *fsp = 2797 (struct ethtool_rx_flow_spec *)&cmd->fs; 2798 2799 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2800 return -EINVAL; 2801 2802 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2803 fsp->flow_type = TCP_V4_FLOW; 2804 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2805 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2806 2807 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2808 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2809 fsp->h_u.tcp_ip4_spec.psrc = 0; 2810 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2811 fsp->h_u.tcp_ip4_spec.pdst = 0; 2812 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2813 fsp->h_u.tcp_ip4_spec.tos = 0; 2814 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2815 2816 return 0; 2817 } 2818 2819 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2820 struct ethtool_rxnfc *cmd, 2821 u32 *rule_locs) 2822 { 2823 struct mtk_mac *mac = netdev_priv(dev); 2824 int cnt = 0; 2825 int i; 2826 2827 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2828 if (mac->hwlro_ip[i]) { 2829 rule_locs[cnt] = i; 2830 cnt++; 2831 } 2832 } 2833 2834 cmd->rule_cnt = cnt; 2835 2836 return 0; 2837 } 2838 2839 static netdev_features_t mtk_fix_features(struct net_device *dev, 2840 netdev_features_t features) 2841 { 2842 if (!(features & NETIF_F_LRO)) { 2843 struct mtk_mac *mac = netdev_priv(dev); 2844 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2845 2846 if (ip_cnt) { 2847 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2848 2849 features |= NETIF_F_LRO; 2850 } 2851 } 2852 2853 return features; 2854 } 2855 2856 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2857 { 2858 struct mtk_mac *mac = netdev_priv(dev); 2859 struct mtk_eth *eth = mac->hw; 2860 netdev_features_t diff = dev->features ^ features; 2861 int i; 2862 2863 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 2864 mtk_hwlro_netdev_disable(dev); 2865 2866 /* Set RX VLAN offloading */ 2867 if (!(diff & NETIF_F_HW_VLAN_CTAG_RX)) 2868 return 0; 2869 2870 mtk_w32(eth, !!(features & NETIF_F_HW_VLAN_CTAG_RX), 2871 MTK_CDMP_EG_CTRL); 2872 2873 /* sync features with other MAC */ 2874 for (i = 0; i < MTK_MAC_COUNT; i++) { 2875 if (!eth->netdev[i] || eth->netdev[i] == dev) 2876 continue; 2877 eth->netdev[i]->features &= ~NETIF_F_HW_VLAN_CTAG_RX; 2878 eth->netdev[i]->features |= features & NETIF_F_HW_VLAN_CTAG_RX; 2879 } 2880 2881 return 0; 2882 } 2883 2884 /* wait for DMA to finish whatever it is doing before we start using it again */ 2885 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2886 { 2887 unsigned int reg; 2888 int ret; 2889 u32 val; 2890 2891 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2892 reg = eth->soc->reg_map->qdma.glo_cfg; 2893 else 2894 reg = eth->soc->reg_map->pdma.glo_cfg; 2895 2896 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2897 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2898 5, MTK_DMA_BUSY_TIMEOUT_US); 2899 if (ret) 2900 dev_err(eth->dev, "DMA init timeout\n"); 2901 2902 return ret; 2903 } 2904 2905 static int mtk_dma_init(struct mtk_eth *eth) 2906 { 2907 int err; 2908 u32 i; 2909 2910 if (mtk_dma_busy_wait(eth)) 2911 return -EBUSY; 2912 2913 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2914 /* QDMA needs scratch memory for internal reordering of the 2915 * descriptors 2916 */ 2917 err = mtk_init_fq_dma(eth); 2918 if (err) 2919 return err; 2920 } 2921 2922 err = mtk_tx_alloc(eth); 2923 if (err) 2924 return err; 2925 2926 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2927 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2928 if (err) 2929 return err; 2930 } 2931 2932 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2933 if (err) 2934 return err; 2935 2936 if (eth->hwlro) { 2937 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2938 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2939 if (err) 2940 return err; 2941 } 2942 err = mtk_hwlro_rx_init(eth); 2943 if (err) 2944 return err; 2945 } 2946 2947 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2948 /* Enable random early drop and set drop threshold 2949 * automatically 2950 */ 2951 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2952 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 2953 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 2954 } 2955 2956 return 0; 2957 } 2958 2959 static void mtk_dma_free(struct mtk_eth *eth) 2960 { 2961 const struct mtk_soc_data *soc = eth->soc; 2962 int i; 2963 2964 for (i = 0; i < MTK_MAC_COUNT; i++) 2965 if (eth->netdev[i]) 2966 netdev_reset_queue(eth->netdev[i]); 2967 if (eth->scratch_ring) { 2968 dma_free_coherent(eth->dma_dev, 2969 MTK_QDMA_RING_SIZE * soc->txrx.txd_size, 2970 eth->scratch_ring, eth->phy_scratch_ring); 2971 eth->scratch_ring = NULL; 2972 eth->phy_scratch_ring = 0; 2973 } 2974 mtk_tx_clean(eth); 2975 mtk_rx_clean(eth, ð->rx_ring[0]); 2976 mtk_rx_clean(eth, ð->rx_ring_qdma); 2977 2978 if (eth->hwlro) { 2979 mtk_hwlro_rx_uninit(eth); 2980 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2981 mtk_rx_clean(eth, ð->rx_ring[i]); 2982 } 2983 2984 kfree(eth->scratch_head); 2985 } 2986 2987 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2988 { 2989 struct mtk_mac *mac = netdev_priv(dev); 2990 struct mtk_eth *eth = mac->hw; 2991 2992 eth->netdev[mac->id]->stats.tx_errors++; 2993 netif_err(eth, tx_err, dev, 2994 "transmit timed out\n"); 2995 schedule_work(ð->pending_work); 2996 } 2997 2998 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2999 { 3000 struct mtk_eth *eth = _eth; 3001 3002 eth->rx_events++; 3003 if (likely(napi_schedule_prep(ð->rx_napi))) { 3004 __napi_schedule(ð->rx_napi); 3005 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3006 } 3007 3008 return IRQ_HANDLED; 3009 } 3010 3011 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3012 { 3013 struct mtk_eth *eth = _eth; 3014 3015 eth->tx_events++; 3016 if (likely(napi_schedule_prep(ð->tx_napi))) { 3017 __napi_schedule(ð->tx_napi); 3018 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3019 } 3020 3021 return IRQ_HANDLED; 3022 } 3023 3024 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3025 { 3026 struct mtk_eth *eth = _eth; 3027 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3028 3029 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3030 eth->soc->txrx.rx_irq_done_mask) { 3031 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3032 eth->soc->txrx.rx_irq_done_mask) 3033 mtk_handle_irq_rx(irq, _eth); 3034 } 3035 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3036 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3037 mtk_handle_irq_tx(irq, _eth); 3038 } 3039 3040 return IRQ_HANDLED; 3041 } 3042 3043 #ifdef CONFIG_NET_POLL_CONTROLLER 3044 static void mtk_poll_controller(struct net_device *dev) 3045 { 3046 struct mtk_mac *mac = netdev_priv(dev); 3047 struct mtk_eth *eth = mac->hw; 3048 3049 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3050 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3051 mtk_handle_irq_rx(eth->irq[2], dev); 3052 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3053 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 3054 } 3055 #endif 3056 3057 static int mtk_start_dma(struct mtk_eth *eth) 3058 { 3059 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3060 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3061 int err; 3062 3063 err = mtk_dma_init(eth); 3064 if (err) { 3065 mtk_dma_free(eth); 3066 return err; 3067 } 3068 3069 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3070 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3071 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3072 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3073 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3074 3075 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3076 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3077 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3078 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3079 else 3080 val |= MTK_RX_BT_32DWORDS; 3081 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3082 3083 mtk_w32(eth, 3084 MTK_RX_DMA_EN | rx_2b_offset | 3085 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3086 reg_map->pdma.glo_cfg); 3087 } else { 3088 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3089 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3090 reg_map->pdma.glo_cfg); 3091 } 3092 3093 return 0; 3094 } 3095 3096 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 3097 { 3098 int i; 3099 3100 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3101 return; 3102 3103 for (i = 0; i < MTK_MAC_COUNT; i++) { 3104 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3105 3106 /* default setup the forward port to send frame to PDMA */ 3107 val &= ~0xffff; 3108 3109 /* Enable RX checksum */ 3110 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3111 3112 val |= config; 3113 3114 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0])) 3115 val |= MTK_GDMA_SPECIAL_TAG; 3116 3117 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 3118 } 3119 /* Reset and enable PSE */ 3120 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3121 mtk_w32(eth, 0, MTK_RST_GL); 3122 } 3123 3124 3125 static bool mtk_uses_dsa(struct net_device *dev) 3126 { 3127 #if IS_ENABLED(CONFIG_NET_DSA) 3128 return netdev_uses_dsa(dev) && 3129 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3130 #else 3131 return false; 3132 #endif 3133 } 3134 3135 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3136 { 3137 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3138 struct mtk_eth *eth = mac->hw; 3139 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3140 struct ethtool_link_ksettings s; 3141 struct net_device *ldev; 3142 struct list_head *iter; 3143 struct dsa_port *dp; 3144 3145 if (event != NETDEV_CHANGE) 3146 return NOTIFY_DONE; 3147 3148 netdev_for_each_lower_dev(dev, ldev, iter) { 3149 if (netdev_priv(ldev) == mac) 3150 goto found; 3151 } 3152 3153 return NOTIFY_DONE; 3154 3155 found: 3156 if (!dsa_slave_dev_check(dev)) 3157 return NOTIFY_DONE; 3158 3159 if (__ethtool_get_link_ksettings(dev, &s)) 3160 return NOTIFY_DONE; 3161 3162 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3163 return NOTIFY_DONE; 3164 3165 dp = dsa_port_from_netdev(dev); 3166 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3167 return NOTIFY_DONE; 3168 3169 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3170 3171 return NOTIFY_DONE; 3172 } 3173 3174 static int mtk_open(struct net_device *dev) 3175 { 3176 struct mtk_mac *mac = netdev_priv(dev); 3177 struct mtk_eth *eth = mac->hw; 3178 int i, err; 3179 3180 if (mtk_uses_dsa(dev) && !eth->prog) { 3181 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3182 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3183 3184 if (md_dst) 3185 continue; 3186 3187 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3188 GFP_KERNEL); 3189 if (!md_dst) 3190 return -ENOMEM; 3191 3192 md_dst->u.port_info.port_id = i; 3193 eth->dsa_meta[i] = md_dst; 3194 } 3195 } else { 3196 /* Hardware special tag parsing needs to be disabled if at least 3197 * one MAC does not use DSA. 3198 */ 3199 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3200 val &= ~MTK_CDMP_STAG_EN; 3201 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3202 } 3203 3204 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3205 if (err) { 3206 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3207 err); 3208 return err; 3209 } 3210 3211 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3212 if (!refcount_read(ð->dma_refcnt)) { 3213 const struct mtk_soc_data *soc = eth->soc; 3214 u32 gdm_config; 3215 int i; 3216 3217 err = mtk_start_dma(eth); 3218 if (err) { 3219 phylink_disconnect_phy(mac->phylink); 3220 return err; 3221 } 3222 3223 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3224 mtk_ppe_start(eth->ppe[i]); 3225 3226 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe 3227 : MTK_GDMA_TO_PDMA; 3228 mtk_gdm_config(eth, gdm_config); 3229 3230 napi_enable(ð->tx_napi); 3231 napi_enable(ð->rx_napi); 3232 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3233 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); 3234 refcount_set(ð->dma_refcnt, 1); 3235 } 3236 else 3237 refcount_inc(ð->dma_refcnt); 3238 3239 phylink_start(mac->phylink); 3240 netif_tx_start_all_queues(dev); 3241 3242 return 0; 3243 } 3244 3245 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3246 { 3247 u32 val; 3248 int i; 3249 3250 /* stop the dma engine */ 3251 spin_lock_bh(ð->page_lock); 3252 val = mtk_r32(eth, glo_cfg); 3253 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3254 glo_cfg); 3255 spin_unlock_bh(ð->page_lock); 3256 3257 /* wait for dma stop */ 3258 for (i = 0; i < 10; i++) { 3259 val = mtk_r32(eth, glo_cfg); 3260 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3261 msleep(20); 3262 continue; 3263 } 3264 break; 3265 } 3266 } 3267 3268 static int mtk_stop(struct net_device *dev) 3269 { 3270 struct mtk_mac *mac = netdev_priv(dev); 3271 struct mtk_eth *eth = mac->hw; 3272 int i; 3273 3274 phylink_stop(mac->phylink); 3275 3276 netif_tx_disable(dev); 3277 3278 phylink_disconnect_phy(mac->phylink); 3279 3280 /* only shutdown DMA if this is the last user */ 3281 if (!refcount_dec_and_test(ð->dma_refcnt)) 3282 return 0; 3283 3284 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3285 3286 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3287 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3288 napi_disable(ð->tx_napi); 3289 napi_disable(ð->rx_napi); 3290 3291 cancel_work_sync(ð->rx_dim.work); 3292 cancel_work_sync(ð->tx_dim.work); 3293 3294 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3295 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3296 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3297 3298 mtk_dma_free(eth); 3299 3300 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3301 mtk_ppe_stop(eth->ppe[i]); 3302 3303 return 0; 3304 } 3305 3306 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3307 struct netlink_ext_ack *extack) 3308 { 3309 struct mtk_mac *mac = netdev_priv(dev); 3310 struct mtk_eth *eth = mac->hw; 3311 struct bpf_prog *old_prog; 3312 bool need_update; 3313 3314 if (eth->hwlro) { 3315 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3316 return -EOPNOTSUPP; 3317 } 3318 3319 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3320 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3321 return -EOPNOTSUPP; 3322 } 3323 3324 need_update = !!eth->prog != !!prog; 3325 if (netif_running(dev) && need_update) 3326 mtk_stop(dev); 3327 3328 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3329 if (old_prog) 3330 bpf_prog_put(old_prog); 3331 3332 if (netif_running(dev) && need_update) 3333 return mtk_open(dev); 3334 3335 return 0; 3336 } 3337 3338 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3339 { 3340 switch (xdp->command) { 3341 case XDP_SETUP_PROG: 3342 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3343 default: 3344 return -EINVAL; 3345 } 3346 } 3347 3348 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3349 { 3350 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3351 reset_bits, 3352 reset_bits); 3353 3354 usleep_range(1000, 1100); 3355 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3356 reset_bits, 3357 ~reset_bits); 3358 mdelay(10); 3359 } 3360 3361 static void mtk_clk_disable(struct mtk_eth *eth) 3362 { 3363 int clk; 3364 3365 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3366 clk_disable_unprepare(eth->clks[clk]); 3367 } 3368 3369 static int mtk_clk_enable(struct mtk_eth *eth) 3370 { 3371 int clk, ret; 3372 3373 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3374 ret = clk_prepare_enable(eth->clks[clk]); 3375 if (ret) 3376 goto err_disable_clks; 3377 } 3378 3379 return 0; 3380 3381 err_disable_clks: 3382 while (--clk >= 0) 3383 clk_disable_unprepare(eth->clks[clk]); 3384 3385 return ret; 3386 } 3387 3388 static void mtk_dim_rx(struct work_struct *work) 3389 { 3390 struct dim *dim = container_of(work, struct dim, work); 3391 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3392 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3393 struct dim_cq_moder cur_profile; 3394 u32 val, cur; 3395 3396 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3397 dim->profile_ix); 3398 spin_lock_bh(ð->dim_lock); 3399 3400 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3401 val &= MTK_PDMA_DELAY_TX_MASK; 3402 val |= MTK_PDMA_DELAY_RX_EN; 3403 3404 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3405 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3406 3407 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3408 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3409 3410 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3411 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3412 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3413 3414 spin_unlock_bh(ð->dim_lock); 3415 3416 dim->state = DIM_START_MEASURE; 3417 } 3418 3419 static void mtk_dim_tx(struct work_struct *work) 3420 { 3421 struct dim *dim = container_of(work, struct dim, work); 3422 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3423 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3424 struct dim_cq_moder cur_profile; 3425 u32 val, cur; 3426 3427 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3428 dim->profile_ix); 3429 spin_lock_bh(ð->dim_lock); 3430 3431 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3432 val &= MTK_PDMA_DELAY_RX_MASK; 3433 val |= MTK_PDMA_DELAY_TX_EN; 3434 3435 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3436 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3437 3438 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3439 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3440 3441 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3442 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3443 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3444 3445 spin_unlock_bh(ð->dim_lock); 3446 3447 dim->state = DIM_START_MEASURE; 3448 } 3449 3450 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3451 { 3452 struct mtk_eth *eth = mac->hw; 3453 u32 mcr_cur, mcr_new; 3454 3455 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3456 return; 3457 3458 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3459 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3460 3461 if (val <= 1518) 3462 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3463 else if (val <= 1536) 3464 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3465 else if (val <= 1552) 3466 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3467 else 3468 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3469 3470 if (mcr_new != mcr_cur) 3471 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3472 } 3473 3474 static int mtk_hw_init(struct mtk_eth *eth) 3475 { 3476 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3477 ETHSYS_DMA_AG_MAP_PPE; 3478 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3479 int i, val, ret; 3480 3481 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 3482 return 0; 3483 3484 pm_runtime_enable(eth->dev); 3485 pm_runtime_get_sync(eth->dev); 3486 3487 ret = mtk_clk_enable(eth); 3488 if (ret) 3489 goto err_disable_pm; 3490 3491 if (eth->ethsys) 3492 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3493 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3494 3495 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3496 ret = device_reset(eth->dev); 3497 if (ret) { 3498 dev_err(eth->dev, "MAC reset failed!\n"); 3499 goto err_disable_pm; 3500 } 3501 3502 /* set interrupt delays based on current Net DIM sample */ 3503 mtk_dim_rx(ð->rx_dim.work); 3504 mtk_dim_tx(ð->tx_dim.work); 3505 3506 /* disable delay and normal interrupt */ 3507 mtk_tx_irq_disable(eth, ~0); 3508 mtk_rx_irq_disable(eth, ~0); 3509 3510 return 0; 3511 } 3512 3513 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3514 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3515 val = RSTCTRL_PPE0_V2; 3516 } else { 3517 val = RSTCTRL_PPE0; 3518 } 3519 3520 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3521 val |= RSTCTRL_PPE1; 3522 3523 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3524 3525 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3526 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3527 0x3ffffff); 3528 3529 /* Set FE to PDMAv2 if necessary */ 3530 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3531 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3532 } 3533 3534 if (eth->pctl) { 3535 /* Set GE2 driving and slew rate */ 3536 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3537 3538 /* set GE2 TDSEL */ 3539 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3540 3541 /* set GE2 TUNE */ 3542 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3543 } 3544 3545 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3546 * up with the more appropriate value when mtk_mac_config call is being 3547 * invoked. 3548 */ 3549 for (i = 0; i < MTK_MAC_COUNT; i++) { 3550 struct net_device *dev = eth->netdev[i]; 3551 3552 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3553 if (dev) { 3554 struct mtk_mac *mac = netdev_priv(dev); 3555 3556 mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN); 3557 } 3558 } 3559 3560 /* Indicates CDM to parse the MTK special tag from CPU 3561 * which also is working out for untag packets. 3562 */ 3563 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3564 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3565 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3566 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3567 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 3568 } 3569 3570 /* Enable RX VLan Offloading */ 3571 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3572 3573 /* set interrupt delays based on current Net DIM sample */ 3574 mtk_dim_rx(ð->rx_dim.work); 3575 mtk_dim_tx(ð->tx_dim.work); 3576 3577 /* disable delay and normal interrupt */ 3578 mtk_tx_irq_disable(eth, ~0); 3579 mtk_rx_irq_disable(eth, ~0); 3580 3581 /* FE int grouping */ 3582 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3583 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3584 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3585 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3586 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3587 3588 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3589 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 3590 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3591 3592 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 3593 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 3594 3595 /* PSE Free Queue Flow Control */ 3596 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3597 3598 /* PSE config input queue threshold */ 3599 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3600 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3601 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3602 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3603 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3604 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3605 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3606 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3607 3608 /* PSE config output queue threshold */ 3609 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3610 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3611 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3612 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3613 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3614 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3615 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3616 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3617 3618 /* GDM and CDM Threshold */ 3619 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 3620 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 3621 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 3622 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 3623 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 3624 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 3625 } 3626 3627 return 0; 3628 3629 err_disable_pm: 3630 pm_runtime_put_sync(eth->dev); 3631 pm_runtime_disable(eth->dev); 3632 3633 return ret; 3634 } 3635 3636 static int mtk_hw_deinit(struct mtk_eth *eth) 3637 { 3638 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 3639 return 0; 3640 3641 mtk_clk_disable(eth); 3642 3643 pm_runtime_put_sync(eth->dev); 3644 pm_runtime_disable(eth->dev); 3645 3646 return 0; 3647 } 3648 3649 static int __init mtk_init(struct net_device *dev) 3650 { 3651 struct mtk_mac *mac = netdev_priv(dev); 3652 struct mtk_eth *eth = mac->hw; 3653 int ret; 3654 3655 ret = of_get_ethdev_address(mac->of_node, dev); 3656 if (ret) { 3657 /* If the mac address is invalid, use random mac address */ 3658 eth_hw_addr_random(dev); 3659 dev_err(eth->dev, "generated random MAC address %pM\n", 3660 dev->dev_addr); 3661 } 3662 3663 return 0; 3664 } 3665 3666 static void mtk_uninit(struct net_device *dev) 3667 { 3668 struct mtk_mac *mac = netdev_priv(dev); 3669 struct mtk_eth *eth = mac->hw; 3670 3671 phylink_disconnect_phy(mac->phylink); 3672 mtk_tx_irq_disable(eth, ~0); 3673 mtk_rx_irq_disable(eth, ~0); 3674 } 3675 3676 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 3677 { 3678 int length = new_mtu + MTK_RX_ETH_HLEN; 3679 struct mtk_mac *mac = netdev_priv(dev); 3680 struct mtk_eth *eth = mac->hw; 3681 3682 if (rcu_access_pointer(eth->prog) && 3683 length > MTK_PP_MAX_BUF_SIZE) { 3684 netdev_err(dev, "Invalid MTU for XDP mode\n"); 3685 return -EINVAL; 3686 } 3687 3688 mtk_set_mcr_max_rx(mac, length); 3689 dev->mtu = new_mtu; 3690 3691 return 0; 3692 } 3693 3694 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3695 { 3696 struct mtk_mac *mac = netdev_priv(dev); 3697 3698 switch (cmd) { 3699 case SIOCGMIIPHY: 3700 case SIOCGMIIREG: 3701 case SIOCSMIIREG: 3702 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 3703 default: 3704 break; 3705 } 3706 3707 return -EOPNOTSUPP; 3708 } 3709 3710 static void mtk_pending_work(struct work_struct *work) 3711 { 3712 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 3713 int err, i; 3714 unsigned long restart = 0; 3715 3716 rtnl_lock(); 3717 3718 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 3719 set_bit(MTK_RESETTING, ð->state); 3720 3721 /* stop all devices to make sure that dma is properly shut down */ 3722 for (i = 0; i < MTK_MAC_COUNT; i++) { 3723 if (!eth->netdev[i]) 3724 continue; 3725 mtk_stop(eth->netdev[i]); 3726 __set_bit(i, &restart); 3727 } 3728 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 3729 3730 /* restart underlying hardware such as power, clock, pin mux 3731 * and the connected phy 3732 */ 3733 mtk_hw_deinit(eth); 3734 3735 if (eth->dev->pins) 3736 pinctrl_select_state(eth->dev->pins->p, 3737 eth->dev->pins->default_state); 3738 mtk_hw_init(eth); 3739 3740 /* restart DMA and enable IRQs */ 3741 for (i = 0; i < MTK_MAC_COUNT; i++) { 3742 if (!test_bit(i, &restart)) 3743 continue; 3744 err = mtk_open(eth->netdev[i]); 3745 if (err) { 3746 netif_alert(eth, ifup, eth->netdev[i], 3747 "Driver up/down cycle failed, closing device.\n"); 3748 dev_close(eth->netdev[i]); 3749 } 3750 } 3751 3752 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 3753 3754 clear_bit(MTK_RESETTING, ð->state); 3755 3756 rtnl_unlock(); 3757 } 3758 3759 static int mtk_free_dev(struct mtk_eth *eth) 3760 { 3761 int i; 3762 3763 for (i = 0; i < MTK_MAC_COUNT; i++) { 3764 if (!eth->netdev[i]) 3765 continue; 3766 free_netdev(eth->netdev[i]); 3767 } 3768 3769 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3770 if (!eth->dsa_meta[i]) 3771 break; 3772 metadata_dst_free(eth->dsa_meta[i]); 3773 } 3774 3775 return 0; 3776 } 3777 3778 static int mtk_unreg_dev(struct mtk_eth *eth) 3779 { 3780 int i; 3781 3782 for (i = 0; i < MTK_MAC_COUNT; i++) { 3783 struct mtk_mac *mac; 3784 if (!eth->netdev[i]) 3785 continue; 3786 mac = netdev_priv(eth->netdev[i]); 3787 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3788 unregister_netdevice_notifier(&mac->device_notifier); 3789 unregister_netdev(eth->netdev[i]); 3790 } 3791 3792 return 0; 3793 } 3794 3795 static int mtk_cleanup(struct mtk_eth *eth) 3796 { 3797 mtk_unreg_dev(eth); 3798 mtk_free_dev(eth); 3799 cancel_work_sync(ð->pending_work); 3800 3801 return 0; 3802 } 3803 3804 static int mtk_get_link_ksettings(struct net_device *ndev, 3805 struct ethtool_link_ksettings *cmd) 3806 { 3807 struct mtk_mac *mac = netdev_priv(ndev); 3808 3809 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3810 return -EBUSY; 3811 3812 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 3813 } 3814 3815 static int mtk_set_link_ksettings(struct net_device *ndev, 3816 const struct ethtool_link_ksettings *cmd) 3817 { 3818 struct mtk_mac *mac = netdev_priv(ndev); 3819 3820 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3821 return -EBUSY; 3822 3823 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 3824 } 3825 3826 static void mtk_get_drvinfo(struct net_device *dev, 3827 struct ethtool_drvinfo *info) 3828 { 3829 struct mtk_mac *mac = netdev_priv(dev); 3830 3831 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 3832 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 3833 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 3834 } 3835 3836 static u32 mtk_get_msglevel(struct net_device *dev) 3837 { 3838 struct mtk_mac *mac = netdev_priv(dev); 3839 3840 return mac->hw->msg_enable; 3841 } 3842 3843 static void mtk_set_msglevel(struct net_device *dev, u32 value) 3844 { 3845 struct mtk_mac *mac = netdev_priv(dev); 3846 3847 mac->hw->msg_enable = value; 3848 } 3849 3850 static int mtk_nway_reset(struct net_device *dev) 3851 { 3852 struct mtk_mac *mac = netdev_priv(dev); 3853 3854 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3855 return -EBUSY; 3856 3857 if (!mac->phylink) 3858 return -ENOTSUPP; 3859 3860 return phylink_ethtool_nway_reset(mac->phylink); 3861 } 3862 3863 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3864 { 3865 int i; 3866 3867 switch (stringset) { 3868 case ETH_SS_STATS: { 3869 struct mtk_mac *mac = netdev_priv(dev); 3870 3871 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 3872 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 3873 data += ETH_GSTRING_LEN; 3874 } 3875 if (mtk_page_pool_enabled(mac->hw)) 3876 page_pool_ethtool_stats_get_strings(data); 3877 break; 3878 } 3879 default: 3880 break; 3881 } 3882 } 3883 3884 static int mtk_get_sset_count(struct net_device *dev, int sset) 3885 { 3886 switch (sset) { 3887 case ETH_SS_STATS: { 3888 int count = ARRAY_SIZE(mtk_ethtool_stats); 3889 struct mtk_mac *mac = netdev_priv(dev); 3890 3891 if (mtk_page_pool_enabled(mac->hw)) 3892 count += page_pool_ethtool_stats_get_count(); 3893 return count; 3894 } 3895 default: 3896 return -EOPNOTSUPP; 3897 } 3898 } 3899 3900 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 3901 { 3902 struct page_pool_stats stats = {}; 3903 int i; 3904 3905 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 3906 struct mtk_rx_ring *ring = ð->rx_ring[i]; 3907 3908 if (!ring->page_pool) 3909 continue; 3910 3911 page_pool_get_stats(ring->page_pool, &stats); 3912 } 3913 page_pool_ethtool_stats_get(data, &stats); 3914 } 3915 3916 static void mtk_get_ethtool_stats(struct net_device *dev, 3917 struct ethtool_stats *stats, u64 *data) 3918 { 3919 struct mtk_mac *mac = netdev_priv(dev); 3920 struct mtk_hw_stats *hwstats = mac->hw_stats; 3921 u64 *data_src, *data_dst; 3922 unsigned int start; 3923 int i; 3924 3925 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3926 return; 3927 3928 if (netif_running(dev) && netif_device_present(dev)) { 3929 if (spin_trylock_bh(&hwstats->stats_lock)) { 3930 mtk_stats_update_mac(mac); 3931 spin_unlock_bh(&hwstats->stats_lock); 3932 } 3933 } 3934 3935 data_src = (u64 *)hwstats; 3936 3937 do { 3938 data_dst = data; 3939 start = u64_stats_fetch_begin(&hwstats->syncp); 3940 3941 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 3942 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 3943 if (mtk_page_pool_enabled(mac->hw)) 3944 mtk_ethtool_pp_stats(mac->hw, data_dst); 3945 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 3946 } 3947 3948 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 3949 u32 *rule_locs) 3950 { 3951 int ret = -EOPNOTSUPP; 3952 3953 switch (cmd->cmd) { 3954 case ETHTOOL_GRXRINGS: 3955 if (dev->hw_features & NETIF_F_LRO) { 3956 cmd->data = MTK_MAX_RX_RING_NUM; 3957 ret = 0; 3958 } 3959 break; 3960 case ETHTOOL_GRXCLSRLCNT: 3961 if (dev->hw_features & NETIF_F_LRO) { 3962 struct mtk_mac *mac = netdev_priv(dev); 3963 3964 cmd->rule_cnt = mac->hwlro_ip_cnt; 3965 ret = 0; 3966 } 3967 break; 3968 case ETHTOOL_GRXCLSRULE: 3969 if (dev->hw_features & NETIF_F_LRO) 3970 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 3971 break; 3972 case ETHTOOL_GRXCLSRLALL: 3973 if (dev->hw_features & NETIF_F_LRO) 3974 ret = mtk_hwlro_get_fdir_all(dev, cmd, 3975 rule_locs); 3976 break; 3977 default: 3978 break; 3979 } 3980 3981 return ret; 3982 } 3983 3984 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3985 { 3986 int ret = -EOPNOTSUPP; 3987 3988 switch (cmd->cmd) { 3989 case ETHTOOL_SRXCLSRLINS: 3990 if (dev->hw_features & NETIF_F_LRO) 3991 ret = mtk_hwlro_add_ipaddr(dev, cmd); 3992 break; 3993 case ETHTOOL_SRXCLSRLDEL: 3994 if (dev->hw_features & NETIF_F_LRO) 3995 ret = mtk_hwlro_del_ipaddr(dev, cmd); 3996 break; 3997 default: 3998 break; 3999 } 4000 4001 return ret; 4002 } 4003 4004 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4005 struct net_device *sb_dev) 4006 { 4007 struct mtk_mac *mac = netdev_priv(dev); 4008 unsigned int queue = 0; 4009 4010 if (netdev_uses_dsa(dev)) 4011 queue = skb_get_queue_mapping(skb) + 3; 4012 else 4013 queue = mac->id; 4014 4015 if (queue >= dev->num_tx_queues) 4016 queue = 0; 4017 4018 return queue; 4019 } 4020 4021 static const struct ethtool_ops mtk_ethtool_ops = { 4022 .get_link_ksettings = mtk_get_link_ksettings, 4023 .set_link_ksettings = mtk_set_link_ksettings, 4024 .get_drvinfo = mtk_get_drvinfo, 4025 .get_msglevel = mtk_get_msglevel, 4026 .set_msglevel = mtk_set_msglevel, 4027 .nway_reset = mtk_nway_reset, 4028 .get_link = ethtool_op_get_link, 4029 .get_strings = mtk_get_strings, 4030 .get_sset_count = mtk_get_sset_count, 4031 .get_ethtool_stats = mtk_get_ethtool_stats, 4032 .get_rxnfc = mtk_get_rxnfc, 4033 .set_rxnfc = mtk_set_rxnfc, 4034 }; 4035 4036 static const struct net_device_ops mtk_netdev_ops = { 4037 .ndo_init = mtk_init, 4038 .ndo_uninit = mtk_uninit, 4039 .ndo_open = mtk_open, 4040 .ndo_stop = mtk_stop, 4041 .ndo_start_xmit = mtk_start_xmit, 4042 .ndo_set_mac_address = mtk_set_mac_address, 4043 .ndo_validate_addr = eth_validate_addr, 4044 .ndo_eth_ioctl = mtk_do_ioctl, 4045 .ndo_change_mtu = mtk_change_mtu, 4046 .ndo_tx_timeout = mtk_tx_timeout, 4047 .ndo_get_stats64 = mtk_get_stats64, 4048 .ndo_fix_features = mtk_fix_features, 4049 .ndo_set_features = mtk_set_features, 4050 #ifdef CONFIG_NET_POLL_CONTROLLER 4051 .ndo_poll_controller = mtk_poll_controller, 4052 #endif 4053 .ndo_setup_tc = mtk_eth_setup_tc, 4054 .ndo_bpf = mtk_xdp, 4055 .ndo_xdp_xmit = mtk_xdp_xmit, 4056 .ndo_select_queue = mtk_select_queue, 4057 }; 4058 4059 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4060 { 4061 const __be32 *_id = of_get_property(np, "reg", NULL); 4062 phy_interface_t phy_mode; 4063 struct phylink *phylink; 4064 struct mtk_mac *mac; 4065 int id, err; 4066 int txqs = 1; 4067 4068 if (!_id) { 4069 dev_err(eth->dev, "missing mac id\n"); 4070 return -EINVAL; 4071 } 4072 4073 id = be32_to_cpup(_id); 4074 if (id >= MTK_MAC_COUNT) { 4075 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4076 return -EINVAL; 4077 } 4078 4079 if (eth->netdev[id]) { 4080 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4081 return -EINVAL; 4082 } 4083 4084 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4085 txqs = MTK_QDMA_NUM_QUEUES; 4086 4087 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4088 if (!eth->netdev[id]) { 4089 dev_err(eth->dev, "alloc_etherdev failed\n"); 4090 return -ENOMEM; 4091 } 4092 mac = netdev_priv(eth->netdev[id]); 4093 eth->mac[id] = mac; 4094 mac->id = id; 4095 mac->hw = eth; 4096 mac->of_node = np; 4097 4098 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4099 mac->hwlro_ip_cnt = 0; 4100 4101 mac->hw_stats = devm_kzalloc(eth->dev, 4102 sizeof(*mac->hw_stats), 4103 GFP_KERNEL); 4104 if (!mac->hw_stats) { 4105 dev_err(eth->dev, "failed to allocate counter memory\n"); 4106 err = -ENOMEM; 4107 goto free_netdev; 4108 } 4109 spin_lock_init(&mac->hw_stats->stats_lock); 4110 u64_stats_init(&mac->hw_stats->syncp); 4111 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 4112 4113 /* phylink create */ 4114 err = of_get_phy_mode(np, &phy_mode); 4115 if (err) { 4116 dev_err(eth->dev, "incorrect phy-mode\n"); 4117 goto free_netdev; 4118 } 4119 4120 /* mac config is not set */ 4121 mac->interface = PHY_INTERFACE_MODE_NA; 4122 mac->speed = SPEED_UNKNOWN; 4123 4124 mac->phylink_config.dev = ð->netdev[id]->dev; 4125 mac->phylink_config.type = PHYLINK_NETDEV; 4126 /* This driver makes use of state->speed in mac_config */ 4127 mac->phylink_config.legacy_pre_march2020 = true; 4128 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4129 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4130 4131 __set_bit(PHY_INTERFACE_MODE_MII, 4132 mac->phylink_config.supported_interfaces); 4133 __set_bit(PHY_INTERFACE_MODE_GMII, 4134 mac->phylink_config.supported_interfaces); 4135 4136 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4137 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4138 4139 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4140 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4141 mac->phylink_config.supported_interfaces); 4142 4143 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4144 __set_bit(PHY_INTERFACE_MODE_SGMII, 4145 mac->phylink_config.supported_interfaces); 4146 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4147 mac->phylink_config.supported_interfaces); 4148 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4149 mac->phylink_config.supported_interfaces); 4150 } 4151 4152 phylink = phylink_create(&mac->phylink_config, 4153 of_fwnode_handle(mac->of_node), 4154 phy_mode, &mtk_phylink_ops); 4155 if (IS_ERR(phylink)) { 4156 err = PTR_ERR(phylink); 4157 goto free_netdev; 4158 } 4159 4160 mac->phylink = phylink; 4161 4162 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4163 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4164 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4165 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4166 4167 eth->netdev[id]->hw_features = eth->soc->hw_features; 4168 if (eth->hwlro) 4169 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4170 4171 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4172 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 4173 eth->netdev[id]->features |= eth->soc->hw_features; 4174 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4175 4176 eth->netdev[id]->irq = eth->irq[0]; 4177 eth->netdev[id]->dev.of_node = np; 4178 4179 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4180 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4181 else 4182 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4183 4184 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4185 mac->device_notifier.notifier_call = mtk_device_event; 4186 register_netdevice_notifier(&mac->device_notifier); 4187 } 4188 4189 return 0; 4190 4191 free_netdev: 4192 free_netdev(eth->netdev[id]); 4193 return err; 4194 } 4195 4196 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4197 { 4198 struct net_device *dev, *tmp; 4199 LIST_HEAD(dev_list); 4200 int i; 4201 4202 rtnl_lock(); 4203 4204 for (i = 0; i < MTK_MAC_COUNT; i++) { 4205 dev = eth->netdev[i]; 4206 4207 if (!dev || !(dev->flags & IFF_UP)) 4208 continue; 4209 4210 list_add_tail(&dev->close_list, &dev_list); 4211 } 4212 4213 dev_close_many(&dev_list, false); 4214 4215 eth->dma_dev = dma_dev; 4216 4217 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4218 list_del_init(&dev->close_list); 4219 dev_open(dev, NULL); 4220 } 4221 4222 rtnl_unlock(); 4223 } 4224 4225 static int mtk_probe(struct platform_device *pdev) 4226 { 4227 struct resource *res = NULL; 4228 struct device_node *mac_np; 4229 struct mtk_eth *eth; 4230 int err, i; 4231 4232 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4233 if (!eth) 4234 return -ENOMEM; 4235 4236 eth->soc = of_device_get_match_data(&pdev->dev); 4237 4238 eth->dev = &pdev->dev; 4239 eth->dma_dev = &pdev->dev; 4240 eth->base = devm_platform_ioremap_resource(pdev, 0); 4241 if (IS_ERR(eth->base)) 4242 return PTR_ERR(eth->base); 4243 4244 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4245 eth->ip_align = NET_IP_ALIGN; 4246 4247 spin_lock_init(ð->page_lock); 4248 spin_lock_init(ð->tx_irq_lock); 4249 spin_lock_init(ð->rx_irq_lock); 4250 spin_lock_init(ð->dim_lock); 4251 4252 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4253 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4254 4255 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4256 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4257 4258 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4259 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4260 "mediatek,ethsys"); 4261 if (IS_ERR(eth->ethsys)) { 4262 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4263 return PTR_ERR(eth->ethsys); 4264 } 4265 } 4266 4267 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4268 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4269 "mediatek,infracfg"); 4270 if (IS_ERR(eth->infra)) { 4271 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4272 return PTR_ERR(eth->infra); 4273 } 4274 } 4275 4276 if (of_dma_is_coherent(pdev->dev.of_node)) { 4277 struct regmap *cci; 4278 4279 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4280 "cci-control-port"); 4281 /* enable CPU/bus coherency */ 4282 if (!IS_ERR(cci)) 4283 regmap_write(cci, 0, 3); 4284 } 4285 4286 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4287 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 4288 GFP_KERNEL); 4289 if (!eth->sgmii) 4290 return -ENOMEM; 4291 4292 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 4293 eth->soc->ana_rgc3); 4294 4295 if (err) 4296 return err; 4297 } 4298 4299 if (eth->soc->required_pctl) { 4300 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4301 "mediatek,pctl"); 4302 if (IS_ERR(eth->pctl)) { 4303 dev_err(&pdev->dev, "no pctl regmap found\n"); 4304 return PTR_ERR(eth->pctl); 4305 } 4306 } 4307 4308 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 4309 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4310 if (!res) 4311 return -EINVAL; 4312 } 4313 4314 if (eth->soc->offload_version) { 4315 for (i = 0;; i++) { 4316 struct device_node *np; 4317 phys_addr_t wdma_phy; 4318 u32 wdma_base; 4319 4320 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4321 break; 4322 4323 np = of_parse_phandle(pdev->dev.of_node, 4324 "mediatek,wed", i); 4325 if (!np) 4326 break; 4327 4328 wdma_base = eth->soc->reg_map->wdma_base[i]; 4329 wdma_phy = res ? res->start + wdma_base : 0; 4330 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4331 wdma_phy, i); 4332 } 4333 } 4334 4335 for (i = 0; i < 3; i++) { 4336 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4337 eth->irq[i] = eth->irq[0]; 4338 else 4339 eth->irq[i] = platform_get_irq(pdev, i); 4340 if (eth->irq[i] < 0) { 4341 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4342 err = -ENXIO; 4343 goto err_wed_exit; 4344 } 4345 } 4346 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4347 eth->clks[i] = devm_clk_get(eth->dev, 4348 mtk_clks_source_name[i]); 4349 if (IS_ERR(eth->clks[i])) { 4350 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4351 err = -EPROBE_DEFER; 4352 goto err_wed_exit; 4353 } 4354 if (eth->soc->required_clks & BIT(i)) { 4355 dev_err(&pdev->dev, "clock %s not found\n", 4356 mtk_clks_source_name[i]); 4357 err = -EINVAL; 4358 goto err_wed_exit; 4359 } 4360 eth->clks[i] = NULL; 4361 } 4362 } 4363 4364 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4365 INIT_WORK(ð->pending_work, mtk_pending_work); 4366 4367 err = mtk_hw_init(eth); 4368 if (err) 4369 goto err_wed_exit; 4370 4371 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4372 4373 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4374 if (!of_device_is_compatible(mac_np, 4375 "mediatek,eth-mac")) 4376 continue; 4377 4378 if (!of_device_is_available(mac_np)) 4379 continue; 4380 4381 err = mtk_add_mac(eth, mac_np); 4382 if (err) { 4383 of_node_put(mac_np); 4384 goto err_deinit_hw; 4385 } 4386 } 4387 4388 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4389 err = devm_request_irq(eth->dev, eth->irq[0], 4390 mtk_handle_irq, 0, 4391 dev_name(eth->dev), eth); 4392 } else { 4393 err = devm_request_irq(eth->dev, eth->irq[1], 4394 mtk_handle_irq_tx, 0, 4395 dev_name(eth->dev), eth); 4396 if (err) 4397 goto err_free_dev; 4398 4399 err = devm_request_irq(eth->dev, eth->irq[2], 4400 mtk_handle_irq_rx, 0, 4401 dev_name(eth->dev), eth); 4402 } 4403 if (err) 4404 goto err_free_dev; 4405 4406 /* No MT7628/88 support yet */ 4407 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4408 err = mtk_mdio_init(eth); 4409 if (err) 4410 goto err_free_dev; 4411 } 4412 4413 if (eth->soc->offload_version) { 4414 u32 num_ppe; 4415 4416 num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; 4417 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4418 for (i = 0; i < num_ppe; i++) { 4419 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; 4420 4421 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, 4422 eth->soc->offload_version, i); 4423 if (!eth->ppe[i]) { 4424 err = -ENOMEM; 4425 goto err_deinit_ppe; 4426 } 4427 } 4428 4429 err = mtk_eth_offload_init(eth); 4430 if (err) 4431 goto err_deinit_ppe; 4432 } 4433 4434 for (i = 0; i < MTK_MAX_DEVS; i++) { 4435 if (!eth->netdev[i]) 4436 continue; 4437 4438 err = register_netdev(eth->netdev[i]); 4439 if (err) { 4440 dev_err(eth->dev, "error bringing up device\n"); 4441 goto err_deinit_ppe; 4442 } else 4443 netif_info(eth, probe, eth->netdev[i], 4444 "mediatek frame engine at 0x%08lx, irq %d\n", 4445 eth->netdev[i]->base_addr, eth->irq[0]); 4446 } 4447 4448 /* we run 2 devices on the same DMA ring so we need a dummy device 4449 * for NAPI to work 4450 */ 4451 init_dummy_netdev(ð->dummy_dev); 4452 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); 4453 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); 4454 4455 platform_set_drvdata(pdev, eth); 4456 4457 return 0; 4458 4459 err_deinit_ppe: 4460 mtk_ppe_deinit(eth); 4461 mtk_mdio_cleanup(eth); 4462 err_free_dev: 4463 mtk_free_dev(eth); 4464 err_deinit_hw: 4465 mtk_hw_deinit(eth); 4466 err_wed_exit: 4467 mtk_wed_exit(); 4468 4469 return err; 4470 } 4471 4472 static int mtk_remove(struct platform_device *pdev) 4473 { 4474 struct mtk_eth *eth = platform_get_drvdata(pdev); 4475 struct mtk_mac *mac; 4476 int i; 4477 4478 /* stop all devices to make sure that dma is properly shut down */ 4479 for (i = 0; i < MTK_MAC_COUNT; i++) { 4480 if (!eth->netdev[i]) 4481 continue; 4482 mtk_stop(eth->netdev[i]); 4483 mac = netdev_priv(eth->netdev[i]); 4484 phylink_disconnect_phy(mac->phylink); 4485 } 4486 4487 mtk_wed_exit(); 4488 mtk_hw_deinit(eth); 4489 4490 netif_napi_del(ð->tx_napi); 4491 netif_napi_del(ð->rx_napi); 4492 mtk_cleanup(eth); 4493 mtk_mdio_cleanup(eth); 4494 4495 return 0; 4496 } 4497 4498 static const struct mtk_soc_data mt2701_data = { 4499 .reg_map = &mtk_reg_map, 4500 .caps = MT7623_CAPS | MTK_HWLRO, 4501 .hw_features = MTK_HW_FEATURES, 4502 .required_clks = MT7623_CLKS_BITMAP, 4503 .required_pctl = true, 4504 .txrx = { 4505 .txd_size = sizeof(struct mtk_tx_dma), 4506 .rxd_size = sizeof(struct mtk_rx_dma), 4507 .rx_irq_done_mask = MTK_RX_DONE_INT, 4508 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4509 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4510 .dma_len_offset = 16, 4511 }, 4512 }; 4513 4514 static const struct mtk_soc_data mt7621_data = { 4515 .reg_map = &mtk_reg_map, 4516 .caps = MT7621_CAPS, 4517 .hw_features = MTK_HW_FEATURES, 4518 .required_clks = MT7621_CLKS_BITMAP, 4519 .required_pctl = false, 4520 .offload_version = 1, 4521 .hash_offset = 2, 4522 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4523 .txrx = { 4524 .txd_size = sizeof(struct mtk_tx_dma), 4525 .rxd_size = sizeof(struct mtk_rx_dma), 4526 .rx_irq_done_mask = MTK_RX_DONE_INT, 4527 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4528 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4529 .dma_len_offset = 16, 4530 }, 4531 }; 4532 4533 static const struct mtk_soc_data mt7622_data = { 4534 .reg_map = &mtk_reg_map, 4535 .ana_rgc3 = 0x2028, 4536 .caps = MT7622_CAPS | MTK_HWLRO, 4537 .hw_features = MTK_HW_FEATURES, 4538 .required_clks = MT7622_CLKS_BITMAP, 4539 .required_pctl = false, 4540 .offload_version = 2, 4541 .hash_offset = 2, 4542 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4543 .txrx = { 4544 .txd_size = sizeof(struct mtk_tx_dma), 4545 .rxd_size = sizeof(struct mtk_rx_dma), 4546 .rx_irq_done_mask = MTK_RX_DONE_INT, 4547 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4548 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4549 .dma_len_offset = 16, 4550 }, 4551 }; 4552 4553 static const struct mtk_soc_data mt7623_data = { 4554 .reg_map = &mtk_reg_map, 4555 .caps = MT7623_CAPS | MTK_HWLRO, 4556 .hw_features = MTK_HW_FEATURES, 4557 .required_clks = MT7623_CLKS_BITMAP, 4558 .required_pctl = true, 4559 .offload_version = 1, 4560 .hash_offset = 2, 4561 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4562 .txrx = { 4563 .txd_size = sizeof(struct mtk_tx_dma), 4564 .rxd_size = sizeof(struct mtk_rx_dma), 4565 .rx_irq_done_mask = MTK_RX_DONE_INT, 4566 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4567 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4568 .dma_len_offset = 16, 4569 }, 4570 }; 4571 4572 static const struct mtk_soc_data mt7629_data = { 4573 .reg_map = &mtk_reg_map, 4574 .ana_rgc3 = 0x128, 4575 .caps = MT7629_CAPS | MTK_HWLRO, 4576 .hw_features = MTK_HW_FEATURES, 4577 .required_clks = MT7629_CLKS_BITMAP, 4578 .required_pctl = false, 4579 .txrx = { 4580 .txd_size = sizeof(struct mtk_tx_dma), 4581 .rxd_size = sizeof(struct mtk_rx_dma), 4582 .rx_irq_done_mask = MTK_RX_DONE_INT, 4583 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4584 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4585 .dma_len_offset = 16, 4586 }, 4587 }; 4588 4589 static const struct mtk_soc_data mt7986_data = { 4590 .reg_map = &mt7986_reg_map, 4591 .ana_rgc3 = 0x128, 4592 .caps = MT7986_CAPS, 4593 .hw_features = MTK_HW_FEATURES, 4594 .required_clks = MT7986_CLKS_BITMAP, 4595 .required_pctl = false, 4596 .offload_version = 2, 4597 .hash_offset = 4, 4598 .foe_entry_size = sizeof(struct mtk_foe_entry), 4599 .txrx = { 4600 .txd_size = sizeof(struct mtk_tx_dma_v2), 4601 .rxd_size = sizeof(struct mtk_rx_dma_v2), 4602 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 4603 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 4604 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 4605 .dma_len_offset = 8, 4606 }, 4607 }; 4608 4609 static const struct mtk_soc_data rt5350_data = { 4610 .reg_map = &mt7628_reg_map, 4611 .caps = MT7628_CAPS, 4612 .hw_features = MTK_HW_FEATURES_MT7628, 4613 .required_clks = MT7628_CLKS_BITMAP, 4614 .required_pctl = false, 4615 .txrx = { 4616 .txd_size = sizeof(struct mtk_tx_dma), 4617 .rxd_size = sizeof(struct mtk_rx_dma), 4618 .rx_irq_done_mask = MTK_RX_DONE_INT, 4619 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 4620 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4621 .dma_len_offset = 16, 4622 }, 4623 }; 4624 4625 const struct of_device_id of_mtk_match[] = { 4626 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 4627 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 4628 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 4629 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 4630 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 4631 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, 4632 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 4633 {}, 4634 }; 4635 MODULE_DEVICE_TABLE(of, of_mtk_match); 4636 4637 static struct platform_driver mtk_driver = { 4638 .probe = mtk_probe, 4639 .remove = mtk_remove, 4640 .driver = { 4641 .name = "mtk_soc_eth", 4642 .of_match_table = of_mtk_match, 4643 }, 4644 }; 4645 4646 module_platform_driver(mtk_driver); 4647 4648 MODULE_LICENSE("GPL"); 4649 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 4650 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 4651