1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/regmap.h> 14 #include <linux/clk.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/if_vlan.h> 17 #include <linux/reset.h> 18 #include <linux/tcp.h> 19 #include <linux/interrupt.h> 20 #include <linux/pinctrl/devinfo.h> 21 22 #include "mtk_eth_soc.h" 23 24 static int mtk_msg_level = -1; 25 module_param_named(msg_level, mtk_msg_level, int, 0); 26 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 27 28 #define MTK_ETHTOOL_STAT(x) { #x, \ 29 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 30 31 /* strings used by ethtool */ 32 static const struct mtk_ethtool_stats { 33 char str[ETH_GSTRING_LEN]; 34 u32 offset; 35 } mtk_ethtool_stats[] = { 36 MTK_ETHTOOL_STAT(tx_bytes), 37 MTK_ETHTOOL_STAT(tx_packets), 38 MTK_ETHTOOL_STAT(tx_skip), 39 MTK_ETHTOOL_STAT(tx_collisions), 40 MTK_ETHTOOL_STAT(rx_bytes), 41 MTK_ETHTOOL_STAT(rx_packets), 42 MTK_ETHTOOL_STAT(rx_overflow), 43 MTK_ETHTOOL_STAT(rx_fcs_errors), 44 MTK_ETHTOOL_STAT(rx_short_errors), 45 MTK_ETHTOOL_STAT(rx_long_errors), 46 MTK_ETHTOOL_STAT(rx_checksum_errors), 47 MTK_ETHTOOL_STAT(rx_flow_control_packets), 48 }; 49 50 static const char * const mtk_clks_source_name[] = { 51 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 52 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 53 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 54 "sgmii_ck", "eth2pll", 55 }; 56 57 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 58 { 59 __raw_writel(val, eth->base + reg); 60 } 61 62 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 63 { 64 return __raw_readl(eth->base + reg); 65 } 66 67 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 68 { 69 unsigned long t_start = jiffies; 70 71 while (1) { 72 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 73 return 0; 74 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 75 break; 76 usleep_range(10, 20); 77 } 78 79 dev_err(eth->dev, "mdio: MDIO timeout\n"); 80 return -1; 81 } 82 83 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 84 u32 phy_register, u32 write_data) 85 { 86 if (mtk_mdio_busy_wait(eth)) 87 return -1; 88 89 write_data &= 0xffff; 90 91 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 92 (phy_register << PHY_IAC_REG_SHIFT) | 93 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 94 MTK_PHY_IAC); 95 96 if (mtk_mdio_busy_wait(eth)) 97 return -1; 98 99 return 0; 100 } 101 102 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 103 { 104 u32 d; 105 106 if (mtk_mdio_busy_wait(eth)) 107 return 0xffff; 108 109 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 110 (phy_reg << PHY_IAC_REG_SHIFT) | 111 (phy_addr << PHY_IAC_ADDR_SHIFT), 112 MTK_PHY_IAC); 113 114 if (mtk_mdio_busy_wait(eth)) 115 return 0xffff; 116 117 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 118 119 return d; 120 } 121 122 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 123 int phy_reg, u16 val) 124 { 125 struct mtk_eth *eth = bus->priv; 126 127 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 128 } 129 130 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 131 { 132 struct mtk_eth *eth = bus->priv; 133 134 return _mtk_mdio_read(eth, phy_addr, phy_reg); 135 } 136 137 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 138 { 139 u32 val; 140 int ret; 141 142 val = (speed == SPEED_1000) ? 143 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 144 mtk_w32(eth, val, INTF_MODE); 145 146 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 147 ETHSYS_TRGMII_CLK_SEL362_5, 148 ETHSYS_TRGMII_CLK_SEL362_5); 149 150 val = (speed == SPEED_1000) ? 250000000 : 500000000; 151 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 152 if (ret) 153 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 154 155 val = (speed == SPEED_1000) ? 156 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 157 mtk_w32(eth, val, TRGMII_RCK_CTRL); 158 159 val = (speed == SPEED_1000) ? 160 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 161 mtk_w32(eth, val, TRGMII_TCK_CTRL); 162 } 163 164 static void mtk_phy_link_adjust(struct net_device *dev) 165 { 166 struct mtk_mac *mac = netdev_priv(dev); 167 u16 lcl_adv = 0, rmt_adv = 0; 168 u8 flowctrl; 169 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 170 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 171 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 172 MAC_MCR_BACKPR_EN; 173 174 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 175 return; 176 177 switch (dev->phydev->speed) { 178 case SPEED_1000: 179 mcr |= MAC_MCR_SPEED_1000; 180 break; 181 case SPEED_100: 182 mcr |= MAC_MCR_SPEED_100; 183 break; 184 } 185 186 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 187 !mac->id && !mac->trgmii) 188 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); 189 190 if (dev->phydev->link) 191 mcr |= MAC_MCR_FORCE_LINK; 192 193 if (dev->phydev->duplex) { 194 mcr |= MAC_MCR_FORCE_DPX; 195 196 if (dev->phydev->pause) 197 rmt_adv = LPA_PAUSE_CAP; 198 if (dev->phydev->asym_pause) 199 rmt_adv |= LPA_PAUSE_ASYM; 200 201 lcl_adv = linkmode_adv_to_lcl_adv_t(dev->phydev->advertising); 202 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 203 204 if (flowctrl & FLOW_CTRL_TX) 205 mcr |= MAC_MCR_FORCE_TX_FC; 206 if (flowctrl & FLOW_CTRL_RX) 207 mcr |= MAC_MCR_FORCE_RX_FC; 208 209 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 210 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 211 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 212 } 213 214 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 215 216 if (!of_phy_is_fixed_link(mac->of_node)) 217 phy_print_status(dev->phydev); 218 } 219 220 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 221 struct device_node *phy_node) 222 { 223 struct phy_device *phydev; 224 int phy_mode; 225 226 phy_mode = of_get_phy_mode(phy_node); 227 if (phy_mode < 0) { 228 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 229 return -EINVAL; 230 } 231 232 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 233 mtk_phy_link_adjust, 0, phy_mode); 234 if (!phydev) { 235 dev_err(eth->dev, "could not connect to PHY\n"); 236 return -ENODEV; 237 } 238 239 dev_info(eth->dev, 240 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 241 mac->id, phydev_name(phydev), phydev->phy_id, 242 phydev->drv->name); 243 244 return 0; 245 } 246 247 static int mtk_phy_connect(struct net_device *dev) 248 { 249 struct mtk_mac *mac = netdev_priv(dev); 250 struct mtk_eth *eth; 251 struct device_node *np; 252 u32 val; 253 int err; 254 255 eth = mac->hw; 256 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 257 if (!np && of_phy_is_fixed_link(mac->of_node)) 258 if (!of_phy_register_fixed_link(mac->of_node)) 259 np = of_node_get(mac->of_node); 260 if (!np) 261 return -ENODEV; 262 263 err = mtk_setup_hw_path(eth, mac->id, of_get_phy_mode(np)); 264 if (err) 265 goto err_phy; 266 267 mac->ge_mode = 0; 268 switch (of_get_phy_mode(np)) { 269 case PHY_INTERFACE_MODE_TRGMII: 270 mac->trgmii = true; 271 case PHY_INTERFACE_MODE_RGMII_TXID: 272 case PHY_INTERFACE_MODE_RGMII_RXID: 273 case PHY_INTERFACE_MODE_RGMII_ID: 274 case PHY_INTERFACE_MODE_RGMII: 275 case PHY_INTERFACE_MODE_SGMII: 276 break; 277 case PHY_INTERFACE_MODE_MII: 278 case PHY_INTERFACE_MODE_GMII: 279 mac->ge_mode = 1; 280 break; 281 case PHY_INTERFACE_MODE_REVMII: 282 mac->ge_mode = 2; 283 break; 284 case PHY_INTERFACE_MODE_RMII: 285 if (!mac->id) 286 goto err_phy; 287 mac->ge_mode = 3; 288 break; 289 default: 290 goto err_phy; 291 } 292 293 /* put the gmac into the right mode */ 294 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 295 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 296 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); 297 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 298 299 /* couple phydev to net_device */ 300 if (mtk_phy_connect_node(eth, mac, np)) 301 goto err_phy; 302 303 of_node_put(np); 304 305 return 0; 306 307 err_phy: 308 if (of_phy_is_fixed_link(mac->of_node)) 309 of_phy_deregister_fixed_link(mac->of_node); 310 of_node_put(np); 311 dev_err(eth->dev, "%s: invalid phy\n", __func__); 312 return -EINVAL; 313 } 314 315 static int mtk_mdio_init(struct mtk_eth *eth) 316 { 317 struct device_node *mii_np; 318 int ret; 319 320 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 321 if (!mii_np) { 322 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 323 return -ENODEV; 324 } 325 326 if (!of_device_is_available(mii_np)) { 327 ret = -ENODEV; 328 goto err_put_node; 329 } 330 331 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 332 if (!eth->mii_bus) { 333 ret = -ENOMEM; 334 goto err_put_node; 335 } 336 337 eth->mii_bus->name = "mdio"; 338 eth->mii_bus->read = mtk_mdio_read; 339 eth->mii_bus->write = mtk_mdio_write; 340 eth->mii_bus->priv = eth; 341 eth->mii_bus->parent = eth->dev; 342 343 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 344 ret = of_mdiobus_register(eth->mii_bus, mii_np); 345 346 err_put_node: 347 of_node_put(mii_np); 348 return ret; 349 } 350 351 static void mtk_mdio_cleanup(struct mtk_eth *eth) 352 { 353 if (!eth->mii_bus) 354 return; 355 356 mdiobus_unregister(eth->mii_bus); 357 } 358 359 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 360 { 361 unsigned long flags; 362 u32 val; 363 364 spin_lock_irqsave(ð->tx_irq_lock, flags); 365 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 366 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 367 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 368 } 369 370 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 371 { 372 unsigned long flags; 373 u32 val; 374 375 spin_lock_irqsave(ð->tx_irq_lock, flags); 376 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 377 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 378 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 379 } 380 381 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 382 { 383 unsigned long flags; 384 u32 val; 385 386 spin_lock_irqsave(ð->rx_irq_lock, flags); 387 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 388 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 389 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 390 } 391 392 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 393 { 394 unsigned long flags; 395 u32 val; 396 397 spin_lock_irqsave(ð->rx_irq_lock, flags); 398 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 399 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 400 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 401 } 402 403 static int mtk_set_mac_address(struct net_device *dev, void *p) 404 { 405 int ret = eth_mac_addr(dev, p); 406 struct mtk_mac *mac = netdev_priv(dev); 407 const char *macaddr = dev->dev_addr; 408 409 if (ret) 410 return ret; 411 412 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 413 return -EBUSY; 414 415 spin_lock_bh(&mac->hw->page_lock); 416 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 417 MTK_GDMA_MAC_ADRH(mac->id)); 418 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 419 (macaddr[4] << 8) | macaddr[5], 420 MTK_GDMA_MAC_ADRL(mac->id)); 421 spin_unlock_bh(&mac->hw->page_lock); 422 423 return 0; 424 } 425 426 void mtk_stats_update_mac(struct mtk_mac *mac) 427 { 428 struct mtk_hw_stats *hw_stats = mac->hw_stats; 429 unsigned int base = MTK_GDM1_TX_GBCNT; 430 u64 stats; 431 432 base += hw_stats->reg_offset; 433 434 u64_stats_update_begin(&hw_stats->syncp); 435 436 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 437 stats = mtk_r32(mac->hw, base + 0x04); 438 if (stats) 439 hw_stats->rx_bytes += (stats << 32); 440 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 441 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 442 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 443 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 444 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 445 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 446 hw_stats->rx_flow_control_packets += 447 mtk_r32(mac->hw, base + 0x24); 448 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 449 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 450 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 451 stats = mtk_r32(mac->hw, base + 0x34); 452 if (stats) 453 hw_stats->tx_bytes += (stats << 32); 454 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 455 u64_stats_update_end(&hw_stats->syncp); 456 } 457 458 static void mtk_stats_update(struct mtk_eth *eth) 459 { 460 int i; 461 462 for (i = 0; i < MTK_MAC_COUNT; i++) { 463 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 464 continue; 465 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 466 mtk_stats_update_mac(eth->mac[i]); 467 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 468 } 469 } 470 } 471 472 static void mtk_get_stats64(struct net_device *dev, 473 struct rtnl_link_stats64 *storage) 474 { 475 struct mtk_mac *mac = netdev_priv(dev); 476 struct mtk_hw_stats *hw_stats = mac->hw_stats; 477 unsigned int start; 478 479 if (netif_running(dev) && netif_device_present(dev)) { 480 if (spin_trylock_bh(&hw_stats->stats_lock)) { 481 mtk_stats_update_mac(mac); 482 spin_unlock_bh(&hw_stats->stats_lock); 483 } 484 } 485 486 do { 487 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 488 storage->rx_packets = hw_stats->rx_packets; 489 storage->tx_packets = hw_stats->tx_packets; 490 storage->rx_bytes = hw_stats->rx_bytes; 491 storage->tx_bytes = hw_stats->tx_bytes; 492 storage->collisions = hw_stats->tx_collisions; 493 storage->rx_length_errors = hw_stats->rx_short_errors + 494 hw_stats->rx_long_errors; 495 storage->rx_over_errors = hw_stats->rx_overflow; 496 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 497 storage->rx_errors = hw_stats->rx_checksum_errors; 498 storage->tx_aborted_errors = hw_stats->tx_skip; 499 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 500 501 storage->tx_errors = dev->stats.tx_errors; 502 storage->rx_dropped = dev->stats.rx_dropped; 503 storage->tx_dropped = dev->stats.tx_dropped; 504 } 505 506 static inline int mtk_max_frag_size(int mtu) 507 { 508 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 509 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 510 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 511 512 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 513 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 514 } 515 516 static inline int mtk_max_buf_size(int frag_size) 517 { 518 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 519 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 520 521 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 522 523 return buf_size; 524 } 525 526 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 527 struct mtk_rx_dma *dma_rxd) 528 { 529 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 530 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 531 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 532 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 533 } 534 535 /* the qdma core needs scratch memory to be setup */ 536 static int mtk_init_fq_dma(struct mtk_eth *eth) 537 { 538 dma_addr_t phy_ring_tail; 539 int cnt = MTK_DMA_SIZE; 540 dma_addr_t dma_addr; 541 int i; 542 543 eth->scratch_ring = dma_alloc_coherent(eth->dev, 544 cnt * sizeof(struct mtk_tx_dma), 545 ð->phy_scratch_ring, 546 GFP_ATOMIC); 547 if (unlikely(!eth->scratch_ring)) 548 return -ENOMEM; 549 550 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 551 GFP_KERNEL); 552 if (unlikely(!eth->scratch_head)) 553 return -ENOMEM; 554 555 dma_addr = dma_map_single(eth->dev, 556 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 557 DMA_FROM_DEVICE); 558 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 559 return -ENOMEM; 560 561 phy_ring_tail = eth->phy_scratch_ring + 562 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 563 564 for (i = 0; i < cnt; i++) { 565 eth->scratch_ring[i].txd1 = 566 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 567 if (i < cnt - 1) 568 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 569 ((i + 1) * sizeof(struct mtk_tx_dma))); 570 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 571 } 572 573 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 574 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 575 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 576 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 577 578 return 0; 579 } 580 581 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 582 { 583 void *ret = ring->dma; 584 585 return ret + (desc - ring->phys); 586 } 587 588 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 589 struct mtk_tx_dma *txd) 590 { 591 int idx = txd - ring->dma; 592 593 return &ring->buf[idx]; 594 } 595 596 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 597 { 598 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 599 dma_unmap_single(eth->dev, 600 dma_unmap_addr(tx_buf, dma_addr0), 601 dma_unmap_len(tx_buf, dma_len0), 602 DMA_TO_DEVICE); 603 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 604 dma_unmap_page(eth->dev, 605 dma_unmap_addr(tx_buf, dma_addr0), 606 dma_unmap_len(tx_buf, dma_len0), 607 DMA_TO_DEVICE); 608 } 609 tx_buf->flags = 0; 610 if (tx_buf->skb && 611 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 612 dev_kfree_skb_any(tx_buf->skb); 613 tx_buf->skb = NULL; 614 } 615 616 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 617 int tx_num, struct mtk_tx_ring *ring, bool gso) 618 { 619 struct mtk_mac *mac = netdev_priv(dev); 620 struct mtk_eth *eth = mac->hw; 621 struct mtk_tx_dma *itxd, *txd; 622 struct mtk_tx_buf *itx_buf, *tx_buf; 623 dma_addr_t mapped_addr; 624 unsigned int nr_frags; 625 int i, n_desc = 1; 626 u32 txd4 = 0, fport; 627 628 itxd = ring->next_free; 629 if (itxd == ring->last_free) 630 return -ENOMEM; 631 632 /* set the forward port */ 633 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 634 txd4 |= fport; 635 636 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 637 memset(itx_buf, 0, sizeof(*itx_buf)); 638 639 if (gso) 640 txd4 |= TX_DMA_TSO; 641 642 /* TX Checksum offload */ 643 if (skb->ip_summed == CHECKSUM_PARTIAL) 644 txd4 |= TX_DMA_CHKSUM; 645 646 /* VLAN header offload */ 647 if (skb_vlan_tag_present(skb)) 648 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 649 650 mapped_addr = dma_map_single(eth->dev, skb->data, 651 skb_headlen(skb), DMA_TO_DEVICE); 652 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 653 return -ENOMEM; 654 655 WRITE_ONCE(itxd->txd1, mapped_addr); 656 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 657 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 658 MTK_TX_FLAGS_FPORT1; 659 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr); 660 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb)); 661 662 /* TX SG offload */ 663 txd = itxd; 664 nr_frags = skb_shinfo(skb)->nr_frags; 665 for (i = 0; i < nr_frags; i++) { 666 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 667 unsigned int offset = 0; 668 int frag_size = skb_frag_size(frag); 669 670 while (frag_size) { 671 bool last_frag = false; 672 unsigned int frag_map_size; 673 674 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 675 if (txd == ring->last_free) 676 goto err_dma; 677 678 n_desc++; 679 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 680 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 681 frag_map_size, 682 DMA_TO_DEVICE); 683 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 684 goto err_dma; 685 686 if (i == nr_frags - 1 && 687 (frag_size - frag_map_size) == 0) 688 last_frag = true; 689 690 WRITE_ONCE(txd->txd1, mapped_addr); 691 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 692 TX_DMA_PLEN0(frag_map_size) | 693 last_frag * TX_DMA_LS0)); 694 WRITE_ONCE(txd->txd4, fport); 695 696 tx_buf = mtk_desc_to_tx_buf(ring, txd); 697 memset(tx_buf, 0, sizeof(*tx_buf)); 698 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 699 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 700 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 701 MTK_TX_FLAGS_FPORT1; 702 703 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 704 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 705 frag_size -= frag_map_size; 706 offset += frag_map_size; 707 } 708 } 709 710 /* store skb to cleanup */ 711 itx_buf->skb = skb; 712 713 WRITE_ONCE(itxd->txd4, txd4); 714 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 715 (!nr_frags * TX_DMA_LS0))); 716 717 netdev_sent_queue(dev, skb->len); 718 skb_tx_timestamp(skb); 719 720 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 721 atomic_sub(n_desc, &ring->free_count); 722 723 /* make sure that all changes to the dma ring are flushed before we 724 * continue 725 */ 726 wmb(); 727 728 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 729 !netdev_xmit_more()) 730 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 731 732 return 0; 733 734 err_dma: 735 do { 736 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 737 738 /* unmap dma */ 739 mtk_tx_unmap(eth, tx_buf); 740 741 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 742 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 743 } while (itxd != txd); 744 745 return -ENOMEM; 746 } 747 748 static inline int mtk_cal_txd_req(struct sk_buff *skb) 749 { 750 int i, nfrags; 751 struct skb_frag_struct *frag; 752 753 nfrags = 1; 754 if (skb_is_gso(skb)) { 755 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 756 frag = &skb_shinfo(skb)->frags[i]; 757 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 758 } 759 } else { 760 nfrags += skb_shinfo(skb)->nr_frags; 761 } 762 763 return nfrags; 764 } 765 766 static int mtk_queue_stopped(struct mtk_eth *eth) 767 { 768 int i; 769 770 for (i = 0; i < MTK_MAC_COUNT; i++) { 771 if (!eth->netdev[i]) 772 continue; 773 if (netif_queue_stopped(eth->netdev[i])) 774 return 1; 775 } 776 777 return 0; 778 } 779 780 static void mtk_wake_queue(struct mtk_eth *eth) 781 { 782 int i; 783 784 for (i = 0; i < MTK_MAC_COUNT; i++) { 785 if (!eth->netdev[i]) 786 continue; 787 netif_wake_queue(eth->netdev[i]); 788 } 789 } 790 791 static void mtk_stop_queue(struct mtk_eth *eth) 792 { 793 int i; 794 795 for (i = 0; i < MTK_MAC_COUNT; i++) { 796 if (!eth->netdev[i]) 797 continue; 798 netif_stop_queue(eth->netdev[i]); 799 } 800 } 801 802 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 803 { 804 struct mtk_mac *mac = netdev_priv(dev); 805 struct mtk_eth *eth = mac->hw; 806 struct mtk_tx_ring *ring = ð->tx_ring; 807 struct net_device_stats *stats = &dev->stats; 808 bool gso = false; 809 int tx_num; 810 811 /* normally we can rely on the stack not calling this more than once, 812 * however we have 2 queues running on the same ring so we need to lock 813 * the ring access 814 */ 815 spin_lock(ð->page_lock); 816 817 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 818 goto drop; 819 820 tx_num = mtk_cal_txd_req(skb); 821 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 822 mtk_stop_queue(eth); 823 netif_err(eth, tx_queued, dev, 824 "Tx Ring full when queue awake!\n"); 825 spin_unlock(ð->page_lock); 826 return NETDEV_TX_BUSY; 827 } 828 829 /* TSO: fill MSS info in tcp checksum field */ 830 if (skb_is_gso(skb)) { 831 if (skb_cow_head(skb, 0)) { 832 netif_warn(eth, tx_err, dev, 833 "GSO expand head fail.\n"); 834 goto drop; 835 } 836 837 if (skb_shinfo(skb)->gso_type & 838 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 839 gso = true; 840 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 841 } 842 } 843 844 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 845 goto drop; 846 847 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 848 mtk_stop_queue(eth); 849 850 spin_unlock(ð->page_lock); 851 852 return NETDEV_TX_OK; 853 854 drop: 855 spin_unlock(ð->page_lock); 856 stats->tx_dropped++; 857 dev_kfree_skb_any(skb); 858 return NETDEV_TX_OK; 859 } 860 861 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 862 { 863 int i; 864 struct mtk_rx_ring *ring; 865 int idx; 866 867 if (!eth->hwlro) 868 return ð->rx_ring[0]; 869 870 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 871 ring = ð->rx_ring[i]; 872 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 873 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 874 ring->calc_idx_update = true; 875 return ring; 876 } 877 } 878 879 return NULL; 880 } 881 882 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 883 { 884 struct mtk_rx_ring *ring; 885 int i; 886 887 if (!eth->hwlro) { 888 ring = ð->rx_ring[0]; 889 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 890 } else { 891 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 892 ring = ð->rx_ring[i]; 893 if (ring->calc_idx_update) { 894 ring->calc_idx_update = false; 895 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 896 } 897 } 898 } 899 } 900 901 static int mtk_poll_rx(struct napi_struct *napi, int budget, 902 struct mtk_eth *eth) 903 { 904 struct mtk_rx_ring *ring; 905 int idx; 906 struct sk_buff *skb; 907 u8 *data, *new_data; 908 struct mtk_rx_dma *rxd, trxd; 909 int done = 0; 910 911 while (done < budget) { 912 struct net_device *netdev; 913 unsigned int pktlen; 914 dma_addr_t dma_addr; 915 int mac = 0; 916 917 ring = mtk_get_rx_ring(eth); 918 if (unlikely(!ring)) 919 goto rx_done; 920 921 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 922 rxd = &ring->dma[idx]; 923 data = ring->data[idx]; 924 925 mtk_rx_get_desc(&trxd, rxd); 926 if (!(trxd.rxd2 & RX_DMA_DONE)) 927 break; 928 929 /* find out which mac the packet come from. values start at 1 */ 930 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 931 RX_DMA_FPORT_MASK; 932 mac--; 933 934 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 935 !eth->netdev[mac])) 936 goto release_desc; 937 938 netdev = eth->netdev[mac]; 939 940 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 941 goto release_desc; 942 943 /* alloc new buffer */ 944 new_data = napi_alloc_frag(ring->frag_size); 945 if (unlikely(!new_data)) { 946 netdev->stats.rx_dropped++; 947 goto release_desc; 948 } 949 dma_addr = dma_map_single(eth->dev, 950 new_data + NET_SKB_PAD, 951 ring->buf_size, 952 DMA_FROM_DEVICE); 953 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 954 skb_free_frag(new_data); 955 netdev->stats.rx_dropped++; 956 goto release_desc; 957 } 958 959 /* receive data */ 960 skb = build_skb(data, ring->frag_size); 961 if (unlikely(!skb)) { 962 skb_free_frag(new_data); 963 netdev->stats.rx_dropped++; 964 goto release_desc; 965 } 966 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 967 968 dma_unmap_single(eth->dev, trxd.rxd1, 969 ring->buf_size, DMA_FROM_DEVICE); 970 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 971 skb->dev = netdev; 972 skb_put(skb, pktlen); 973 if (trxd.rxd4 & RX_DMA_L4_VALID) 974 skb->ip_summed = CHECKSUM_UNNECESSARY; 975 else 976 skb_checksum_none_assert(skb); 977 skb->protocol = eth_type_trans(skb, netdev); 978 979 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 980 RX_DMA_VID(trxd.rxd3)) 981 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 982 RX_DMA_VID(trxd.rxd3)); 983 skb_record_rx_queue(skb, 0); 984 napi_gro_receive(napi, skb); 985 986 ring->data[idx] = new_data; 987 rxd->rxd1 = (unsigned int)dma_addr; 988 989 release_desc: 990 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 991 992 ring->calc_idx = idx; 993 994 done++; 995 } 996 997 rx_done: 998 if (done) { 999 /* make sure that all changes to the dma ring are flushed before 1000 * we continue 1001 */ 1002 wmb(); 1003 mtk_update_rx_cpu_idx(eth); 1004 } 1005 1006 return done; 1007 } 1008 1009 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1010 { 1011 struct mtk_tx_ring *ring = ð->tx_ring; 1012 struct mtk_tx_dma *desc; 1013 struct sk_buff *skb; 1014 struct mtk_tx_buf *tx_buf; 1015 unsigned int done[MTK_MAX_DEVS]; 1016 unsigned int bytes[MTK_MAX_DEVS]; 1017 u32 cpu, dma; 1018 int total = 0, i; 1019 1020 memset(done, 0, sizeof(done)); 1021 memset(bytes, 0, sizeof(bytes)); 1022 1023 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1024 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1025 1026 desc = mtk_qdma_phys_to_virt(ring, cpu); 1027 1028 while ((cpu != dma) && budget) { 1029 u32 next_cpu = desc->txd2; 1030 int mac = 0; 1031 1032 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1033 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1034 break; 1035 1036 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1037 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1038 mac = 1; 1039 1040 skb = tx_buf->skb; 1041 if (!skb) 1042 break; 1043 1044 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1045 bytes[mac] += skb->len; 1046 done[mac]++; 1047 budget--; 1048 } 1049 mtk_tx_unmap(eth, tx_buf); 1050 1051 ring->last_free = desc; 1052 atomic_inc(&ring->free_count); 1053 1054 cpu = next_cpu; 1055 } 1056 1057 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1058 1059 for (i = 0; i < MTK_MAC_COUNT; i++) { 1060 if (!eth->netdev[i] || !done[i]) 1061 continue; 1062 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1063 total += done[i]; 1064 } 1065 1066 if (mtk_queue_stopped(eth) && 1067 (atomic_read(&ring->free_count) > ring->thresh)) 1068 mtk_wake_queue(eth); 1069 1070 return total; 1071 } 1072 1073 static void mtk_handle_status_irq(struct mtk_eth *eth) 1074 { 1075 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1076 1077 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1078 mtk_stats_update(eth); 1079 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1080 MTK_INT_STATUS2); 1081 } 1082 } 1083 1084 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1085 { 1086 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1087 u32 status, mask; 1088 int tx_done = 0; 1089 1090 mtk_handle_status_irq(eth); 1091 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 1092 tx_done = mtk_poll_tx(eth, budget); 1093 1094 if (unlikely(netif_msg_intr(eth))) { 1095 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1096 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1097 dev_info(eth->dev, 1098 "done tx %d, intr 0x%08x/0x%x\n", 1099 tx_done, status, mask); 1100 } 1101 1102 if (tx_done == budget) 1103 return budget; 1104 1105 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1106 if (status & MTK_TX_DONE_INT) 1107 return budget; 1108 1109 napi_complete(napi); 1110 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1111 1112 return tx_done; 1113 } 1114 1115 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1116 { 1117 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1118 u32 status, mask; 1119 int rx_done = 0; 1120 int remain_budget = budget; 1121 1122 mtk_handle_status_irq(eth); 1123 1124 poll_again: 1125 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1126 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1127 1128 if (unlikely(netif_msg_intr(eth))) { 1129 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1130 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1131 dev_info(eth->dev, 1132 "done rx %d, intr 0x%08x/0x%x\n", 1133 rx_done, status, mask); 1134 } 1135 if (rx_done == remain_budget) 1136 return budget; 1137 1138 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1139 if (status & MTK_RX_DONE_INT) { 1140 remain_budget -= rx_done; 1141 goto poll_again; 1142 } 1143 napi_complete(napi); 1144 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1145 1146 return rx_done + budget - remain_budget; 1147 } 1148 1149 static int mtk_tx_alloc(struct mtk_eth *eth) 1150 { 1151 struct mtk_tx_ring *ring = ð->tx_ring; 1152 int i, sz = sizeof(*ring->dma); 1153 1154 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1155 GFP_KERNEL); 1156 if (!ring->buf) 1157 goto no_tx_mem; 1158 1159 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1160 &ring->phys, GFP_ATOMIC); 1161 if (!ring->dma) 1162 goto no_tx_mem; 1163 1164 for (i = 0; i < MTK_DMA_SIZE; i++) { 1165 int next = (i + 1) % MTK_DMA_SIZE; 1166 u32 next_ptr = ring->phys + next * sz; 1167 1168 ring->dma[i].txd2 = next_ptr; 1169 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1170 } 1171 1172 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1173 ring->next_free = &ring->dma[0]; 1174 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1175 ring->thresh = MAX_SKB_FRAGS; 1176 1177 /* make sure that all changes to the dma ring are flushed before we 1178 * continue 1179 */ 1180 wmb(); 1181 1182 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1183 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1184 mtk_w32(eth, 1185 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1186 MTK_QTX_CRX_PTR); 1187 mtk_w32(eth, 1188 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1189 MTK_QTX_DRX_PTR); 1190 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1191 1192 return 0; 1193 1194 no_tx_mem: 1195 return -ENOMEM; 1196 } 1197 1198 static void mtk_tx_clean(struct mtk_eth *eth) 1199 { 1200 struct mtk_tx_ring *ring = ð->tx_ring; 1201 int i; 1202 1203 if (ring->buf) { 1204 for (i = 0; i < MTK_DMA_SIZE; i++) 1205 mtk_tx_unmap(eth, &ring->buf[i]); 1206 kfree(ring->buf); 1207 ring->buf = NULL; 1208 } 1209 1210 if (ring->dma) { 1211 dma_free_coherent(eth->dev, 1212 MTK_DMA_SIZE * sizeof(*ring->dma), 1213 ring->dma, 1214 ring->phys); 1215 ring->dma = NULL; 1216 } 1217 } 1218 1219 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1220 { 1221 struct mtk_rx_ring *ring; 1222 int rx_data_len, rx_dma_size; 1223 int i; 1224 u32 offset = 0; 1225 1226 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1227 if (ring_no) 1228 return -EINVAL; 1229 ring = ð->rx_ring_qdma; 1230 offset = 0x1000; 1231 } else { 1232 ring = ð->rx_ring[ring_no]; 1233 } 1234 1235 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1236 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1237 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1238 } else { 1239 rx_data_len = ETH_DATA_LEN; 1240 rx_dma_size = MTK_DMA_SIZE; 1241 } 1242 1243 ring->frag_size = mtk_max_frag_size(rx_data_len); 1244 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1245 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1246 GFP_KERNEL); 1247 if (!ring->data) 1248 return -ENOMEM; 1249 1250 for (i = 0; i < rx_dma_size; i++) { 1251 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1252 if (!ring->data[i]) 1253 return -ENOMEM; 1254 } 1255 1256 ring->dma = dma_alloc_coherent(eth->dev, 1257 rx_dma_size * sizeof(*ring->dma), 1258 &ring->phys, GFP_ATOMIC); 1259 if (!ring->dma) 1260 return -ENOMEM; 1261 1262 for (i = 0; i < rx_dma_size; i++) { 1263 dma_addr_t dma_addr = dma_map_single(eth->dev, 1264 ring->data[i] + NET_SKB_PAD, 1265 ring->buf_size, 1266 DMA_FROM_DEVICE); 1267 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1268 return -ENOMEM; 1269 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1270 1271 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1272 } 1273 ring->dma_size = rx_dma_size; 1274 ring->calc_idx_update = false; 1275 ring->calc_idx = rx_dma_size - 1; 1276 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1277 /* make sure that all changes to the dma ring are flushed before we 1278 * continue 1279 */ 1280 wmb(); 1281 1282 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1283 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1284 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1285 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1286 1287 return 0; 1288 } 1289 1290 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1291 { 1292 int i; 1293 1294 if (ring->data && ring->dma) { 1295 for (i = 0; i < ring->dma_size; i++) { 1296 if (!ring->data[i]) 1297 continue; 1298 if (!ring->dma[i].rxd1) 1299 continue; 1300 dma_unmap_single(eth->dev, 1301 ring->dma[i].rxd1, 1302 ring->buf_size, 1303 DMA_FROM_DEVICE); 1304 skb_free_frag(ring->data[i]); 1305 } 1306 kfree(ring->data); 1307 ring->data = NULL; 1308 } 1309 1310 if (ring->dma) { 1311 dma_free_coherent(eth->dev, 1312 ring->dma_size * sizeof(*ring->dma), 1313 ring->dma, 1314 ring->phys); 1315 ring->dma = NULL; 1316 } 1317 } 1318 1319 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1320 { 1321 int i; 1322 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1323 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1324 1325 /* set LRO rings to auto-learn modes */ 1326 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1327 1328 /* validate LRO ring */ 1329 ring_ctrl_dw2 |= MTK_RING_VLD; 1330 1331 /* set AGE timer (unit: 20us) */ 1332 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1333 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1334 1335 /* set max AGG timer (unit: 20us) */ 1336 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1337 1338 /* set max LRO AGG count */ 1339 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1340 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1341 1342 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1343 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1344 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1345 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1346 } 1347 1348 /* IPv4 checksum update enable */ 1349 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1350 1351 /* switch priority comparison to packet count mode */ 1352 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1353 1354 /* bandwidth threshold setting */ 1355 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1356 1357 /* auto-learn score delta setting */ 1358 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1359 1360 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1361 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1362 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1363 1364 /* set HW LRO mode & the max aggregation count for rx packets */ 1365 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1366 1367 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1368 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1369 1370 /* enable HW LRO */ 1371 lro_ctrl_dw0 |= MTK_LRO_EN; 1372 1373 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1374 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1375 1376 return 0; 1377 } 1378 1379 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1380 { 1381 int i; 1382 u32 val; 1383 1384 /* relinquish lro rings, flush aggregated packets */ 1385 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1386 1387 /* wait for relinquishments done */ 1388 for (i = 0; i < 10; i++) { 1389 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1390 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1391 msleep(20); 1392 continue; 1393 } 1394 break; 1395 } 1396 1397 /* invalidate lro rings */ 1398 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1399 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1400 1401 /* disable HW LRO */ 1402 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1403 } 1404 1405 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1406 { 1407 u32 reg_val; 1408 1409 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1410 1411 /* invalidate the IP setting */ 1412 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1413 1414 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1415 1416 /* validate the IP setting */ 1417 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1418 } 1419 1420 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1421 { 1422 u32 reg_val; 1423 1424 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1425 1426 /* invalidate the IP setting */ 1427 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1428 1429 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1430 } 1431 1432 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1433 { 1434 int cnt = 0; 1435 int i; 1436 1437 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1438 if (mac->hwlro_ip[i]) 1439 cnt++; 1440 } 1441 1442 return cnt; 1443 } 1444 1445 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1446 struct ethtool_rxnfc *cmd) 1447 { 1448 struct ethtool_rx_flow_spec *fsp = 1449 (struct ethtool_rx_flow_spec *)&cmd->fs; 1450 struct mtk_mac *mac = netdev_priv(dev); 1451 struct mtk_eth *eth = mac->hw; 1452 int hwlro_idx; 1453 1454 if ((fsp->flow_type != TCP_V4_FLOW) || 1455 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1456 (fsp->location > 1)) 1457 return -EINVAL; 1458 1459 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1460 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1461 1462 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1463 1464 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1465 1466 return 0; 1467 } 1468 1469 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1470 struct ethtool_rxnfc *cmd) 1471 { 1472 struct ethtool_rx_flow_spec *fsp = 1473 (struct ethtool_rx_flow_spec *)&cmd->fs; 1474 struct mtk_mac *mac = netdev_priv(dev); 1475 struct mtk_eth *eth = mac->hw; 1476 int hwlro_idx; 1477 1478 if (fsp->location > 1) 1479 return -EINVAL; 1480 1481 mac->hwlro_ip[fsp->location] = 0; 1482 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1483 1484 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1485 1486 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1487 1488 return 0; 1489 } 1490 1491 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1492 { 1493 struct mtk_mac *mac = netdev_priv(dev); 1494 struct mtk_eth *eth = mac->hw; 1495 int i, hwlro_idx; 1496 1497 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1498 mac->hwlro_ip[i] = 0; 1499 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1500 1501 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1502 } 1503 1504 mac->hwlro_ip_cnt = 0; 1505 } 1506 1507 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1508 struct ethtool_rxnfc *cmd) 1509 { 1510 struct mtk_mac *mac = netdev_priv(dev); 1511 struct ethtool_rx_flow_spec *fsp = 1512 (struct ethtool_rx_flow_spec *)&cmd->fs; 1513 1514 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1515 fsp->flow_type = TCP_V4_FLOW; 1516 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1517 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1518 1519 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1520 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1521 fsp->h_u.tcp_ip4_spec.psrc = 0; 1522 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1523 fsp->h_u.tcp_ip4_spec.pdst = 0; 1524 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1525 fsp->h_u.tcp_ip4_spec.tos = 0; 1526 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1527 1528 return 0; 1529 } 1530 1531 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1532 struct ethtool_rxnfc *cmd, 1533 u32 *rule_locs) 1534 { 1535 struct mtk_mac *mac = netdev_priv(dev); 1536 int cnt = 0; 1537 int i; 1538 1539 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1540 if (mac->hwlro_ip[i]) { 1541 rule_locs[cnt] = i; 1542 cnt++; 1543 } 1544 } 1545 1546 cmd->rule_cnt = cnt; 1547 1548 return 0; 1549 } 1550 1551 static netdev_features_t mtk_fix_features(struct net_device *dev, 1552 netdev_features_t features) 1553 { 1554 if (!(features & NETIF_F_LRO)) { 1555 struct mtk_mac *mac = netdev_priv(dev); 1556 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1557 1558 if (ip_cnt) { 1559 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1560 1561 features |= NETIF_F_LRO; 1562 } 1563 } 1564 1565 return features; 1566 } 1567 1568 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1569 { 1570 int err = 0; 1571 1572 if (!((dev->features ^ features) & NETIF_F_LRO)) 1573 return 0; 1574 1575 if (!(features & NETIF_F_LRO)) 1576 mtk_hwlro_netdev_disable(dev); 1577 1578 return err; 1579 } 1580 1581 /* wait for DMA to finish whatever it is doing before we start using it again */ 1582 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1583 { 1584 unsigned long t_start = jiffies; 1585 1586 while (1) { 1587 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1588 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1589 return 0; 1590 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1591 break; 1592 } 1593 1594 dev_err(eth->dev, "DMA init timeout\n"); 1595 return -1; 1596 } 1597 1598 static int mtk_dma_init(struct mtk_eth *eth) 1599 { 1600 int err; 1601 u32 i; 1602 1603 if (mtk_dma_busy_wait(eth)) 1604 return -EBUSY; 1605 1606 /* QDMA needs scratch memory for internal reordering of the 1607 * descriptors 1608 */ 1609 err = mtk_init_fq_dma(eth); 1610 if (err) 1611 return err; 1612 1613 err = mtk_tx_alloc(eth); 1614 if (err) 1615 return err; 1616 1617 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 1618 if (err) 1619 return err; 1620 1621 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 1622 if (err) 1623 return err; 1624 1625 if (eth->hwlro) { 1626 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1627 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 1628 if (err) 1629 return err; 1630 } 1631 err = mtk_hwlro_rx_init(eth); 1632 if (err) 1633 return err; 1634 } 1635 1636 /* Enable random early drop and set drop threshold automatically */ 1637 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1638 MTK_QDMA_FC_THRES); 1639 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1640 1641 return 0; 1642 } 1643 1644 static void mtk_dma_free(struct mtk_eth *eth) 1645 { 1646 int i; 1647 1648 for (i = 0; i < MTK_MAC_COUNT; i++) 1649 if (eth->netdev[i]) 1650 netdev_reset_queue(eth->netdev[i]); 1651 if (eth->scratch_ring) { 1652 dma_free_coherent(eth->dev, 1653 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1654 eth->scratch_ring, 1655 eth->phy_scratch_ring); 1656 eth->scratch_ring = NULL; 1657 eth->phy_scratch_ring = 0; 1658 } 1659 mtk_tx_clean(eth); 1660 mtk_rx_clean(eth, ð->rx_ring[0]); 1661 mtk_rx_clean(eth, ð->rx_ring_qdma); 1662 1663 if (eth->hwlro) { 1664 mtk_hwlro_rx_uninit(eth); 1665 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1666 mtk_rx_clean(eth, ð->rx_ring[i]); 1667 } 1668 1669 kfree(eth->scratch_head); 1670 } 1671 1672 static void mtk_tx_timeout(struct net_device *dev) 1673 { 1674 struct mtk_mac *mac = netdev_priv(dev); 1675 struct mtk_eth *eth = mac->hw; 1676 1677 eth->netdev[mac->id]->stats.tx_errors++; 1678 netif_err(eth, tx_err, dev, 1679 "transmit timed out\n"); 1680 schedule_work(ð->pending_work); 1681 } 1682 1683 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1684 { 1685 struct mtk_eth *eth = _eth; 1686 1687 if (likely(napi_schedule_prep(ð->rx_napi))) { 1688 __napi_schedule(ð->rx_napi); 1689 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1690 } 1691 1692 return IRQ_HANDLED; 1693 } 1694 1695 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1696 { 1697 struct mtk_eth *eth = _eth; 1698 1699 if (likely(napi_schedule_prep(ð->tx_napi))) { 1700 __napi_schedule(ð->tx_napi); 1701 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1702 } 1703 1704 return IRQ_HANDLED; 1705 } 1706 1707 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 1708 { 1709 struct mtk_eth *eth = _eth; 1710 1711 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 1712 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 1713 mtk_handle_irq_rx(irq, _eth); 1714 } 1715 if (mtk_r32(eth, MTK_QDMA_INT_MASK) & MTK_TX_DONE_INT) { 1716 if (mtk_r32(eth, MTK_QMTK_INT_STATUS) & MTK_TX_DONE_INT) 1717 mtk_handle_irq_tx(irq, _eth); 1718 } 1719 1720 return IRQ_HANDLED; 1721 } 1722 1723 #ifdef CONFIG_NET_POLL_CONTROLLER 1724 static void mtk_poll_controller(struct net_device *dev) 1725 { 1726 struct mtk_mac *mac = netdev_priv(dev); 1727 struct mtk_eth *eth = mac->hw; 1728 1729 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1730 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1731 mtk_handle_irq_rx(eth->irq[2], dev); 1732 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1733 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1734 } 1735 #endif 1736 1737 static int mtk_start_dma(struct mtk_eth *eth) 1738 { 1739 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 1740 int err; 1741 1742 err = mtk_dma_init(eth); 1743 if (err) { 1744 mtk_dma_free(eth); 1745 return err; 1746 } 1747 1748 mtk_w32(eth, 1749 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 1750 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 1751 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1752 MTK_RX_BT_32DWORDS, 1753 MTK_QDMA_GLO_CFG); 1754 1755 mtk_w32(eth, 1756 MTK_RX_DMA_EN | rx_2b_offset | 1757 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 1758 MTK_PDMA_GLO_CFG); 1759 1760 return 0; 1761 } 1762 1763 static int mtk_open(struct net_device *dev) 1764 { 1765 struct mtk_mac *mac = netdev_priv(dev); 1766 struct mtk_eth *eth = mac->hw; 1767 1768 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1769 if (!refcount_read(ð->dma_refcnt)) { 1770 int err = mtk_start_dma(eth); 1771 1772 if (err) 1773 return err; 1774 1775 napi_enable(ð->tx_napi); 1776 napi_enable(ð->rx_napi); 1777 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1778 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1779 refcount_set(ð->dma_refcnt, 1); 1780 } 1781 else 1782 refcount_inc(ð->dma_refcnt); 1783 1784 phy_start(dev->phydev); 1785 netif_start_queue(dev); 1786 1787 return 0; 1788 } 1789 1790 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1791 { 1792 u32 val; 1793 int i; 1794 1795 /* stop the dma engine */ 1796 spin_lock_bh(ð->page_lock); 1797 val = mtk_r32(eth, glo_cfg); 1798 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1799 glo_cfg); 1800 spin_unlock_bh(ð->page_lock); 1801 1802 /* wait for dma stop */ 1803 for (i = 0; i < 10; i++) { 1804 val = mtk_r32(eth, glo_cfg); 1805 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1806 msleep(20); 1807 continue; 1808 } 1809 break; 1810 } 1811 } 1812 1813 static int mtk_stop(struct net_device *dev) 1814 { 1815 struct mtk_mac *mac = netdev_priv(dev); 1816 struct mtk_eth *eth = mac->hw; 1817 1818 netif_tx_disable(dev); 1819 phy_stop(dev->phydev); 1820 1821 /* only shutdown DMA if this is the last user */ 1822 if (!refcount_dec_and_test(ð->dma_refcnt)) 1823 return 0; 1824 1825 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1826 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1827 napi_disable(ð->tx_napi); 1828 napi_disable(ð->rx_napi); 1829 1830 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1831 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 1832 1833 mtk_dma_free(eth); 1834 1835 return 0; 1836 } 1837 1838 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 1839 { 1840 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1841 reset_bits, 1842 reset_bits); 1843 1844 usleep_range(1000, 1100); 1845 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1846 reset_bits, 1847 ~reset_bits); 1848 mdelay(10); 1849 } 1850 1851 static void mtk_clk_disable(struct mtk_eth *eth) 1852 { 1853 int clk; 1854 1855 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 1856 clk_disable_unprepare(eth->clks[clk]); 1857 } 1858 1859 static int mtk_clk_enable(struct mtk_eth *eth) 1860 { 1861 int clk, ret; 1862 1863 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 1864 ret = clk_prepare_enable(eth->clks[clk]); 1865 if (ret) 1866 goto err_disable_clks; 1867 } 1868 1869 return 0; 1870 1871 err_disable_clks: 1872 while (--clk >= 0) 1873 clk_disable_unprepare(eth->clks[clk]); 1874 1875 return ret; 1876 } 1877 1878 static int mtk_hw_init(struct mtk_eth *eth) 1879 { 1880 int i, val, ret; 1881 1882 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 1883 return 0; 1884 1885 pm_runtime_enable(eth->dev); 1886 pm_runtime_get_sync(eth->dev); 1887 1888 ret = mtk_clk_enable(eth); 1889 if (ret) 1890 goto err_disable_pm; 1891 1892 ethsys_reset(eth, RSTCTRL_FE); 1893 ethsys_reset(eth, RSTCTRL_PPE); 1894 1895 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 1896 for (i = 0; i < MTK_MAC_COUNT; i++) { 1897 if (!eth->mac[i]) 1898 continue; 1899 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); 1900 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); 1901 } 1902 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1903 1904 if (eth->pctl) { 1905 /* Set GE2 driving and slew rate */ 1906 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1907 1908 /* set GE2 TDSEL */ 1909 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1910 1911 /* set GE2 TUNE */ 1912 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1913 } 1914 1915 /* Set linkdown as the default for each GMAC. Its own MCR would be set 1916 * up with the more appropriate value when mtk_phy_link_adjust call is 1917 * being invoked. 1918 */ 1919 for (i = 0; i < MTK_MAC_COUNT; i++) 1920 mtk_w32(eth, 0, MTK_MAC_MCR(i)); 1921 1922 /* Indicates CDM to parse the MTK special tag from CPU 1923 * which also is working out for untag packets. 1924 */ 1925 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 1926 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 1927 1928 /* Enable RX VLan Offloading */ 1929 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1930 1931 /* enable interrupt delay for RX */ 1932 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 1933 1934 /* disable delay and normal interrupt */ 1935 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1936 mtk_tx_irq_disable(eth, ~0); 1937 mtk_rx_irq_disable(eth, ~0); 1938 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1939 mtk_w32(eth, 0, MTK_RST_GL); 1940 1941 /* FE int grouping */ 1942 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1943 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1944 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1945 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1946 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1947 1948 for (i = 0; i < 2; i++) { 1949 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1950 1951 /* setup the forward port to send frame to PDMA */ 1952 val &= ~0xffff; 1953 1954 /* Enable RX checksum */ 1955 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1956 1957 /* setup the mac dma */ 1958 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 1959 } 1960 1961 return 0; 1962 1963 err_disable_pm: 1964 pm_runtime_put_sync(eth->dev); 1965 pm_runtime_disable(eth->dev); 1966 1967 return ret; 1968 } 1969 1970 static int mtk_hw_deinit(struct mtk_eth *eth) 1971 { 1972 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 1973 return 0; 1974 1975 mtk_clk_disable(eth); 1976 1977 pm_runtime_put_sync(eth->dev); 1978 pm_runtime_disable(eth->dev); 1979 1980 return 0; 1981 } 1982 1983 static int __init mtk_init(struct net_device *dev) 1984 { 1985 struct mtk_mac *mac = netdev_priv(dev); 1986 struct mtk_eth *eth = mac->hw; 1987 const char *mac_addr; 1988 1989 mac_addr = of_get_mac_address(mac->of_node); 1990 if (!IS_ERR(mac_addr)) 1991 ether_addr_copy(dev->dev_addr, mac_addr); 1992 1993 /* If the mac address is invalid, use random mac address */ 1994 if (!is_valid_ether_addr(dev->dev_addr)) { 1995 eth_hw_addr_random(dev); 1996 dev_err(eth->dev, "generated random MAC address %pM\n", 1997 dev->dev_addr); 1998 } 1999 2000 return mtk_phy_connect(dev); 2001 } 2002 2003 static void mtk_uninit(struct net_device *dev) 2004 { 2005 struct mtk_mac *mac = netdev_priv(dev); 2006 struct mtk_eth *eth = mac->hw; 2007 2008 phy_disconnect(dev->phydev); 2009 if (of_phy_is_fixed_link(mac->of_node)) 2010 of_phy_deregister_fixed_link(mac->of_node); 2011 mtk_tx_irq_disable(eth, ~0); 2012 mtk_rx_irq_disable(eth, ~0); 2013 } 2014 2015 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2016 { 2017 switch (cmd) { 2018 case SIOCGMIIPHY: 2019 case SIOCGMIIREG: 2020 case SIOCSMIIREG: 2021 return phy_mii_ioctl(dev->phydev, ifr, cmd); 2022 default: 2023 break; 2024 } 2025 2026 return -EOPNOTSUPP; 2027 } 2028 2029 static void mtk_pending_work(struct work_struct *work) 2030 { 2031 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2032 int err, i; 2033 unsigned long restart = 0; 2034 2035 rtnl_lock(); 2036 2037 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2038 2039 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2040 cpu_relax(); 2041 2042 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2043 /* stop all devices to make sure that dma is properly shut down */ 2044 for (i = 0; i < MTK_MAC_COUNT; i++) { 2045 if (!eth->netdev[i]) 2046 continue; 2047 mtk_stop(eth->netdev[i]); 2048 __set_bit(i, &restart); 2049 } 2050 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2051 2052 /* restart underlying hardware such as power, clock, pin mux 2053 * and the connected phy 2054 */ 2055 mtk_hw_deinit(eth); 2056 2057 if (eth->dev->pins) 2058 pinctrl_select_state(eth->dev->pins->p, 2059 eth->dev->pins->default_state); 2060 mtk_hw_init(eth); 2061 2062 for (i = 0; i < MTK_MAC_COUNT; i++) { 2063 if (!eth->mac[i] || 2064 of_phy_is_fixed_link(eth->mac[i]->of_node)) 2065 continue; 2066 err = phy_init_hw(eth->netdev[i]->phydev); 2067 if (err) 2068 dev_err(eth->dev, "%s: PHY init failed.\n", 2069 eth->netdev[i]->name); 2070 } 2071 2072 /* restart DMA and enable IRQs */ 2073 for (i = 0; i < MTK_MAC_COUNT; i++) { 2074 if (!test_bit(i, &restart)) 2075 continue; 2076 err = mtk_open(eth->netdev[i]); 2077 if (err) { 2078 netif_alert(eth, ifup, eth->netdev[i], 2079 "Driver up/down cycle failed, closing device.\n"); 2080 dev_close(eth->netdev[i]); 2081 } 2082 } 2083 2084 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2085 2086 clear_bit_unlock(MTK_RESETTING, ð->state); 2087 2088 rtnl_unlock(); 2089 } 2090 2091 static int mtk_free_dev(struct mtk_eth *eth) 2092 { 2093 int i; 2094 2095 for (i = 0; i < MTK_MAC_COUNT; i++) { 2096 if (!eth->netdev[i]) 2097 continue; 2098 free_netdev(eth->netdev[i]); 2099 } 2100 2101 return 0; 2102 } 2103 2104 static int mtk_unreg_dev(struct mtk_eth *eth) 2105 { 2106 int i; 2107 2108 for (i = 0; i < MTK_MAC_COUNT; i++) { 2109 if (!eth->netdev[i]) 2110 continue; 2111 unregister_netdev(eth->netdev[i]); 2112 } 2113 2114 return 0; 2115 } 2116 2117 static int mtk_cleanup(struct mtk_eth *eth) 2118 { 2119 mtk_unreg_dev(eth); 2120 mtk_free_dev(eth); 2121 cancel_work_sync(ð->pending_work); 2122 2123 return 0; 2124 } 2125 2126 static int mtk_get_link_ksettings(struct net_device *ndev, 2127 struct ethtool_link_ksettings *cmd) 2128 { 2129 struct mtk_mac *mac = netdev_priv(ndev); 2130 2131 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2132 return -EBUSY; 2133 2134 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2135 2136 return 0; 2137 } 2138 2139 static int mtk_set_link_ksettings(struct net_device *ndev, 2140 const struct ethtool_link_ksettings *cmd) 2141 { 2142 struct mtk_mac *mac = netdev_priv(ndev); 2143 2144 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2145 return -EBUSY; 2146 2147 return phy_ethtool_ksettings_set(ndev->phydev, cmd); 2148 } 2149 2150 static void mtk_get_drvinfo(struct net_device *dev, 2151 struct ethtool_drvinfo *info) 2152 { 2153 struct mtk_mac *mac = netdev_priv(dev); 2154 2155 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2156 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2157 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2158 } 2159 2160 static u32 mtk_get_msglevel(struct net_device *dev) 2161 { 2162 struct mtk_mac *mac = netdev_priv(dev); 2163 2164 return mac->hw->msg_enable; 2165 } 2166 2167 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2168 { 2169 struct mtk_mac *mac = netdev_priv(dev); 2170 2171 mac->hw->msg_enable = value; 2172 } 2173 2174 static int mtk_nway_reset(struct net_device *dev) 2175 { 2176 struct mtk_mac *mac = netdev_priv(dev); 2177 2178 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2179 return -EBUSY; 2180 2181 return genphy_restart_aneg(dev->phydev); 2182 } 2183 2184 static u32 mtk_get_link(struct net_device *dev) 2185 { 2186 struct mtk_mac *mac = netdev_priv(dev); 2187 int err; 2188 2189 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2190 return -EBUSY; 2191 2192 err = genphy_update_link(dev->phydev); 2193 if (err) 2194 return ethtool_op_get_link(dev); 2195 2196 return dev->phydev->link; 2197 } 2198 2199 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2200 { 2201 int i; 2202 2203 switch (stringset) { 2204 case ETH_SS_STATS: 2205 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2206 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2207 data += ETH_GSTRING_LEN; 2208 } 2209 break; 2210 } 2211 } 2212 2213 static int mtk_get_sset_count(struct net_device *dev, int sset) 2214 { 2215 switch (sset) { 2216 case ETH_SS_STATS: 2217 return ARRAY_SIZE(mtk_ethtool_stats); 2218 default: 2219 return -EOPNOTSUPP; 2220 } 2221 } 2222 2223 static void mtk_get_ethtool_stats(struct net_device *dev, 2224 struct ethtool_stats *stats, u64 *data) 2225 { 2226 struct mtk_mac *mac = netdev_priv(dev); 2227 struct mtk_hw_stats *hwstats = mac->hw_stats; 2228 u64 *data_src, *data_dst; 2229 unsigned int start; 2230 int i; 2231 2232 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2233 return; 2234 2235 if (netif_running(dev) && netif_device_present(dev)) { 2236 if (spin_trylock_bh(&hwstats->stats_lock)) { 2237 mtk_stats_update_mac(mac); 2238 spin_unlock_bh(&hwstats->stats_lock); 2239 } 2240 } 2241 2242 data_src = (u64 *)hwstats; 2243 2244 do { 2245 data_dst = data; 2246 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2247 2248 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2249 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2250 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2251 } 2252 2253 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2254 u32 *rule_locs) 2255 { 2256 int ret = -EOPNOTSUPP; 2257 2258 switch (cmd->cmd) { 2259 case ETHTOOL_GRXRINGS: 2260 if (dev->hw_features & NETIF_F_LRO) { 2261 cmd->data = MTK_MAX_RX_RING_NUM; 2262 ret = 0; 2263 } 2264 break; 2265 case ETHTOOL_GRXCLSRLCNT: 2266 if (dev->hw_features & NETIF_F_LRO) { 2267 struct mtk_mac *mac = netdev_priv(dev); 2268 2269 cmd->rule_cnt = mac->hwlro_ip_cnt; 2270 ret = 0; 2271 } 2272 break; 2273 case ETHTOOL_GRXCLSRULE: 2274 if (dev->hw_features & NETIF_F_LRO) 2275 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2276 break; 2277 case ETHTOOL_GRXCLSRLALL: 2278 if (dev->hw_features & NETIF_F_LRO) 2279 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2280 rule_locs); 2281 break; 2282 default: 2283 break; 2284 } 2285 2286 return ret; 2287 } 2288 2289 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2290 { 2291 int ret = -EOPNOTSUPP; 2292 2293 switch (cmd->cmd) { 2294 case ETHTOOL_SRXCLSRLINS: 2295 if (dev->hw_features & NETIF_F_LRO) 2296 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2297 break; 2298 case ETHTOOL_SRXCLSRLDEL: 2299 if (dev->hw_features & NETIF_F_LRO) 2300 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2301 break; 2302 default: 2303 break; 2304 } 2305 2306 return ret; 2307 } 2308 2309 static const struct ethtool_ops mtk_ethtool_ops = { 2310 .get_link_ksettings = mtk_get_link_ksettings, 2311 .set_link_ksettings = mtk_set_link_ksettings, 2312 .get_drvinfo = mtk_get_drvinfo, 2313 .get_msglevel = mtk_get_msglevel, 2314 .set_msglevel = mtk_set_msglevel, 2315 .nway_reset = mtk_nway_reset, 2316 .get_link = mtk_get_link, 2317 .get_strings = mtk_get_strings, 2318 .get_sset_count = mtk_get_sset_count, 2319 .get_ethtool_stats = mtk_get_ethtool_stats, 2320 .get_rxnfc = mtk_get_rxnfc, 2321 .set_rxnfc = mtk_set_rxnfc, 2322 }; 2323 2324 static const struct net_device_ops mtk_netdev_ops = { 2325 .ndo_init = mtk_init, 2326 .ndo_uninit = mtk_uninit, 2327 .ndo_open = mtk_open, 2328 .ndo_stop = mtk_stop, 2329 .ndo_start_xmit = mtk_start_xmit, 2330 .ndo_set_mac_address = mtk_set_mac_address, 2331 .ndo_validate_addr = eth_validate_addr, 2332 .ndo_do_ioctl = mtk_do_ioctl, 2333 .ndo_tx_timeout = mtk_tx_timeout, 2334 .ndo_get_stats64 = mtk_get_stats64, 2335 .ndo_fix_features = mtk_fix_features, 2336 .ndo_set_features = mtk_set_features, 2337 #ifdef CONFIG_NET_POLL_CONTROLLER 2338 .ndo_poll_controller = mtk_poll_controller, 2339 #endif 2340 }; 2341 2342 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2343 { 2344 struct mtk_mac *mac; 2345 const __be32 *_id = of_get_property(np, "reg", NULL); 2346 int id, err; 2347 2348 if (!_id) { 2349 dev_err(eth->dev, "missing mac id\n"); 2350 return -EINVAL; 2351 } 2352 2353 id = be32_to_cpup(_id); 2354 if (id >= MTK_MAC_COUNT) { 2355 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2356 return -EINVAL; 2357 } 2358 2359 if (eth->netdev[id]) { 2360 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2361 return -EINVAL; 2362 } 2363 2364 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2365 if (!eth->netdev[id]) { 2366 dev_err(eth->dev, "alloc_etherdev failed\n"); 2367 return -ENOMEM; 2368 } 2369 mac = netdev_priv(eth->netdev[id]); 2370 eth->mac[id] = mac; 2371 mac->id = id; 2372 mac->hw = eth; 2373 mac->of_node = np; 2374 2375 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2376 mac->hwlro_ip_cnt = 0; 2377 2378 mac->hw_stats = devm_kzalloc(eth->dev, 2379 sizeof(*mac->hw_stats), 2380 GFP_KERNEL); 2381 if (!mac->hw_stats) { 2382 dev_err(eth->dev, "failed to allocate counter memory\n"); 2383 err = -ENOMEM; 2384 goto free_netdev; 2385 } 2386 spin_lock_init(&mac->hw_stats->stats_lock); 2387 u64_stats_init(&mac->hw_stats->syncp); 2388 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2389 2390 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2391 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2392 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2393 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2394 2395 eth->netdev[id]->hw_features = MTK_HW_FEATURES; 2396 if (eth->hwlro) 2397 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2398 2399 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 2400 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2401 eth->netdev[id]->features |= MTK_HW_FEATURES; 2402 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2403 2404 eth->netdev[id]->irq = eth->irq[0]; 2405 eth->netdev[id]->dev.of_node = np; 2406 2407 return 0; 2408 2409 free_netdev: 2410 free_netdev(eth->netdev[id]); 2411 return err; 2412 } 2413 2414 static int mtk_probe(struct platform_device *pdev) 2415 { 2416 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2417 struct device_node *mac_np; 2418 struct mtk_eth *eth; 2419 int err; 2420 int i; 2421 2422 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2423 if (!eth) 2424 return -ENOMEM; 2425 2426 eth->soc = of_device_get_match_data(&pdev->dev); 2427 2428 eth->dev = &pdev->dev; 2429 eth->base = devm_ioremap_resource(&pdev->dev, res); 2430 if (IS_ERR(eth->base)) 2431 return PTR_ERR(eth->base); 2432 2433 spin_lock_init(ð->page_lock); 2434 spin_lock_init(ð->tx_irq_lock); 2435 spin_lock_init(ð->rx_irq_lock); 2436 2437 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2438 "mediatek,ethsys"); 2439 if (IS_ERR(eth->ethsys)) { 2440 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2441 return PTR_ERR(eth->ethsys); 2442 } 2443 2444 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 2445 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2446 "mediatek,infracfg"); 2447 if (IS_ERR(eth->infra)) { 2448 dev_err(&pdev->dev, "no infracfg regmap found\n"); 2449 return PTR_ERR(eth->infra); 2450 } 2451 } 2452 2453 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2454 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 2455 GFP_KERNEL); 2456 if (!eth->sgmii) 2457 return -ENOMEM; 2458 2459 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 2460 eth->soc->ana_rgc3); 2461 2462 if (err) 2463 return err; 2464 } 2465 2466 if (eth->soc->required_pctl) { 2467 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2468 "mediatek,pctl"); 2469 if (IS_ERR(eth->pctl)) { 2470 dev_err(&pdev->dev, "no pctl regmap found\n"); 2471 return PTR_ERR(eth->pctl); 2472 } 2473 } 2474 2475 for (i = 0; i < 3; i++) { 2476 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 2477 eth->irq[i] = eth->irq[0]; 2478 else 2479 eth->irq[i] = platform_get_irq(pdev, i); 2480 if (eth->irq[i] < 0) { 2481 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2482 return -ENXIO; 2483 } 2484 } 2485 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2486 eth->clks[i] = devm_clk_get(eth->dev, 2487 mtk_clks_source_name[i]); 2488 if (IS_ERR(eth->clks[i])) { 2489 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2490 return -EPROBE_DEFER; 2491 if (eth->soc->required_clks & BIT(i)) { 2492 dev_err(&pdev->dev, "clock %s not found\n", 2493 mtk_clks_source_name[i]); 2494 return -EINVAL; 2495 } 2496 eth->clks[i] = NULL; 2497 } 2498 } 2499 2500 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2501 INIT_WORK(ð->pending_work, mtk_pending_work); 2502 2503 err = mtk_hw_init(eth); 2504 if (err) 2505 return err; 2506 2507 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 2508 2509 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2510 if (!of_device_is_compatible(mac_np, 2511 "mediatek,eth-mac")) 2512 continue; 2513 2514 if (!of_device_is_available(mac_np)) 2515 continue; 2516 2517 err = mtk_add_mac(eth, mac_np); 2518 if (err) 2519 goto err_deinit_hw; 2520 } 2521 2522 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 2523 err = devm_request_irq(eth->dev, eth->irq[0], 2524 mtk_handle_irq, 0, 2525 dev_name(eth->dev), eth); 2526 } else { 2527 err = devm_request_irq(eth->dev, eth->irq[1], 2528 mtk_handle_irq_tx, 0, 2529 dev_name(eth->dev), eth); 2530 if (err) 2531 goto err_free_dev; 2532 2533 err = devm_request_irq(eth->dev, eth->irq[2], 2534 mtk_handle_irq_rx, 0, 2535 dev_name(eth->dev), eth); 2536 } 2537 if (err) 2538 goto err_free_dev; 2539 2540 err = mtk_mdio_init(eth); 2541 if (err) 2542 goto err_free_dev; 2543 2544 for (i = 0; i < MTK_MAX_DEVS; i++) { 2545 if (!eth->netdev[i]) 2546 continue; 2547 2548 err = register_netdev(eth->netdev[i]); 2549 if (err) { 2550 dev_err(eth->dev, "error bringing up device\n"); 2551 goto err_deinit_mdio; 2552 } else 2553 netif_info(eth, probe, eth->netdev[i], 2554 "mediatek frame engine at 0x%08lx, irq %d\n", 2555 eth->netdev[i]->base_addr, eth->irq[0]); 2556 } 2557 2558 /* we run 2 devices on the same DMA ring so we need a dummy device 2559 * for NAPI to work 2560 */ 2561 init_dummy_netdev(ð->dummy_dev); 2562 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 2563 MTK_NAPI_WEIGHT); 2564 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 2565 MTK_NAPI_WEIGHT); 2566 2567 platform_set_drvdata(pdev, eth); 2568 2569 return 0; 2570 2571 err_deinit_mdio: 2572 mtk_mdio_cleanup(eth); 2573 err_free_dev: 2574 mtk_free_dev(eth); 2575 err_deinit_hw: 2576 mtk_hw_deinit(eth); 2577 2578 return err; 2579 } 2580 2581 static int mtk_remove(struct platform_device *pdev) 2582 { 2583 struct mtk_eth *eth = platform_get_drvdata(pdev); 2584 int i; 2585 2586 /* stop all devices to make sure that dma is properly shut down */ 2587 for (i = 0; i < MTK_MAC_COUNT; i++) { 2588 if (!eth->netdev[i]) 2589 continue; 2590 mtk_stop(eth->netdev[i]); 2591 } 2592 2593 mtk_hw_deinit(eth); 2594 2595 netif_napi_del(ð->tx_napi); 2596 netif_napi_del(ð->rx_napi); 2597 mtk_cleanup(eth); 2598 mtk_mdio_cleanup(eth); 2599 2600 return 0; 2601 } 2602 2603 static const struct mtk_soc_data mt2701_data = { 2604 .caps = MT7623_CAPS | MTK_HWLRO, 2605 .required_clks = MT7623_CLKS_BITMAP, 2606 .required_pctl = true, 2607 }; 2608 2609 static const struct mtk_soc_data mt7621_data = { 2610 .caps = MTK_SHARED_INT, 2611 .required_clks = MT7621_CLKS_BITMAP, 2612 .required_pctl = false, 2613 }; 2614 2615 static const struct mtk_soc_data mt7622_data = { 2616 .ana_rgc3 = 0x2028, 2617 .caps = MT7622_CAPS | MTK_HWLRO, 2618 .required_clks = MT7622_CLKS_BITMAP, 2619 .required_pctl = false, 2620 }; 2621 2622 static const struct mtk_soc_data mt7623_data = { 2623 .caps = MT7623_CAPS | MTK_HWLRO, 2624 .required_clks = MT7623_CLKS_BITMAP, 2625 .required_pctl = true, 2626 }; 2627 2628 static const struct mtk_soc_data mt7629_data = { 2629 .ana_rgc3 = 0x128, 2630 .caps = MT7629_CAPS | MTK_HWLRO, 2631 .required_clks = MT7629_CLKS_BITMAP, 2632 .required_pctl = false, 2633 }; 2634 2635 const struct of_device_id of_mtk_match[] = { 2636 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 2637 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 2638 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 2639 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 2640 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 2641 {}, 2642 }; 2643 MODULE_DEVICE_TABLE(of, of_mtk_match); 2644 2645 static struct platform_driver mtk_driver = { 2646 .probe = mtk_probe, 2647 .remove = mtk_remove, 2648 .driver = { 2649 .name = "mtk_soc_eth", 2650 .of_match_table = of_mtk_match, 2651 }, 2652 }; 2653 2654 module_platform_driver(mtk_driver); 2655 2656 MODULE_LICENSE("GPL"); 2657 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 2658 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 2659