1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #include <linux/of_device.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/regmap.h> 20 #include <linux/clk.h> 21 #include <linux/if_vlan.h> 22 #include <linux/reset.h> 23 #include <linux/tcp.h> 24 25 #include "mtk_eth_soc.h" 26 27 static int mtk_msg_level = -1; 28 module_param_named(msg_level, mtk_msg_level, int, 0); 29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 30 31 #define MTK_ETHTOOL_STAT(x) { #x, \ 32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 33 34 /* strings used by ethtool */ 35 static const struct mtk_ethtool_stats { 36 char str[ETH_GSTRING_LEN]; 37 u32 offset; 38 } mtk_ethtool_stats[] = { 39 MTK_ETHTOOL_STAT(tx_bytes), 40 MTK_ETHTOOL_STAT(tx_packets), 41 MTK_ETHTOOL_STAT(tx_skip), 42 MTK_ETHTOOL_STAT(tx_collisions), 43 MTK_ETHTOOL_STAT(rx_bytes), 44 MTK_ETHTOOL_STAT(rx_packets), 45 MTK_ETHTOOL_STAT(rx_overflow), 46 MTK_ETHTOOL_STAT(rx_fcs_errors), 47 MTK_ETHTOOL_STAT(rx_short_errors), 48 MTK_ETHTOOL_STAT(rx_long_errors), 49 MTK_ETHTOOL_STAT(rx_checksum_errors), 50 MTK_ETHTOOL_STAT(rx_flow_control_packets), 51 }; 52 53 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 54 { 55 __raw_writel(val, eth->base + reg); 56 } 57 58 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 59 { 60 return __raw_readl(eth->base + reg); 61 } 62 63 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 64 { 65 unsigned long t_start = jiffies; 66 67 while (1) { 68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 69 return 0; 70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 71 break; 72 usleep_range(10, 20); 73 } 74 75 dev_err(eth->dev, "mdio: MDIO timeout\n"); 76 return -1; 77 } 78 79 u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 80 u32 phy_register, u32 write_data) 81 { 82 if (mtk_mdio_busy_wait(eth)) 83 return -1; 84 85 write_data &= 0xffff; 86 87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 88 (phy_register << PHY_IAC_REG_SHIFT) | 89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 90 MTK_PHY_IAC); 91 92 if (mtk_mdio_busy_wait(eth)) 93 return -1; 94 95 return 0; 96 } 97 98 u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 99 { 100 u32 d; 101 102 if (mtk_mdio_busy_wait(eth)) 103 return 0xffff; 104 105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 106 (phy_reg << PHY_IAC_REG_SHIFT) | 107 (phy_addr << PHY_IAC_ADDR_SHIFT), 108 MTK_PHY_IAC); 109 110 if (mtk_mdio_busy_wait(eth)) 111 return 0xffff; 112 113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 114 115 return d; 116 } 117 118 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 119 int phy_reg, u16 val) 120 { 121 struct mtk_eth *eth = bus->priv; 122 123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 124 } 125 126 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 127 { 128 struct mtk_eth *eth = bus->priv; 129 130 return _mtk_mdio_read(eth, phy_addr, phy_reg); 131 } 132 133 static void mtk_phy_link_adjust(struct net_device *dev) 134 { 135 struct mtk_mac *mac = netdev_priv(dev); 136 u16 lcl_adv = 0, rmt_adv = 0; 137 u8 flowctrl; 138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 141 MAC_MCR_BACKPR_EN; 142 143 switch (mac->phy_dev->speed) { 144 case SPEED_1000: 145 mcr |= MAC_MCR_SPEED_1000; 146 break; 147 case SPEED_100: 148 mcr |= MAC_MCR_SPEED_100; 149 break; 150 }; 151 152 if (mac->phy_dev->link) 153 mcr |= MAC_MCR_FORCE_LINK; 154 155 if (mac->phy_dev->duplex) { 156 mcr |= MAC_MCR_FORCE_DPX; 157 158 if (mac->phy_dev->pause) 159 rmt_adv = LPA_PAUSE_CAP; 160 if (mac->phy_dev->asym_pause) 161 rmt_adv |= LPA_PAUSE_ASYM; 162 163 if (mac->phy_dev->advertising & ADVERTISED_Pause) 164 lcl_adv |= ADVERTISE_PAUSE_CAP; 165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause) 166 lcl_adv |= ADVERTISE_PAUSE_ASYM; 167 168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 169 170 if (flowctrl & FLOW_CTRL_TX) 171 mcr |= MAC_MCR_FORCE_TX_FC; 172 if (flowctrl & FLOW_CTRL_RX) 173 mcr |= MAC_MCR_FORCE_RX_FC; 174 175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 178 } 179 180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 181 182 if (mac->phy_dev->link) 183 netif_carrier_on(dev); 184 else 185 netif_carrier_off(dev); 186 } 187 188 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 189 struct device_node *phy_node) 190 { 191 const __be32 *_addr = NULL; 192 struct phy_device *phydev; 193 int phy_mode, addr; 194 195 _addr = of_get_property(phy_node, "reg", NULL); 196 197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) { 198 pr_err("%s: invalid phy address\n", phy_node->name); 199 return -EINVAL; 200 } 201 addr = be32_to_cpu(*_addr); 202 phy_mode = of_get_phy_mode(phy_node); 203 if (phy_mode < 0) { 204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 205 return -EINVAL; 206 } 207 208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 209 mtk_phy_link_adjust, 0, phy_mode); 210 if (!phydev) { 211 dev_err(eth->dev, "could not connect to PHY\n"); 212 return -ENODEV; 213 } 214 215 dev_info(eth->dev, 216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 217 mac->id, phydev_name(phydev), phydev->phy_id, 218 phydev->drv->name); 219 220 mac->phy_dev = phydev; 221 222 return 0; 223 } 224 225 static int mtk_phy_connect(struct mtk_mac *mac) 226 { 227 struct mtk_eth *eth = mac->hw; 228 struct device_node *np; 229 u32 val, ge_mode; 230 231 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 232 if (!np && of_phy_is_fixed_link(mac->of_node)) 233 if (!of_phy_register_fixed_link(mac->of_node)) 234 np = of_node_get(mac->of_node); 235 if (!np) 236 return -ENODEV; 237 238 switch (of_get_phy_mode(np)) { 239 case PHY_INTERFACE_MODE_RGMII_TXID: 240 case PHY_INTERFACE_MODE_RGMII_RXID: 241 case PHY_INTERFACE_MODE_RGMII_ID: 242 case PHY_INTERFACE_MODE_RGMII: 243 ge_mode = 0; 244 break; 245 case PHY_INTERFACE_MODE_MII: 246 ge_mode = 1; 247 break; 248 case PHY_INTERFACE_MODE_RMII: 249 ge_mode = 2; 250 break; 251 default: 252 dev_err(eth->dev, "invalid phy_mode\n"); 253 return -1; 254 } 255 256 /* put the gmac into the right mode */ 257 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 258 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 259 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 260 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 261 262 mtk_phy_connect_node(eth, mac, np); 263 mac->phy_dev->autoneg = AUTONEG_ENABLE; 264 mac->phy_dev->speed = 0; 265 mac->phy_dev->duplex = 0; 266 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause | 267 SUPPORTED_Asym_Pause; 268 mac->phy_dev->advertising = mac->phy_dev->supported | 269 ADVERTISED_Autoneg; 270 phy_start_aneg(mac->phy_dev); 271 272 return 0; 273 } 274 275 static int mtk_mdio_init(struct mtk_eth *eth) 276 { 277 struct device_node *mii_np; 278 int err; 279 280 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 281 if (!mii_np) { 282 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 283 return -ENODEV; 284 } 285 286 if (!of_device_is_available(mii_np)) { 287 err = 0; 288 goto err_put_node; 289 } 290 291 eth->mii_bus = mdiobus_alloc(); 292 if (!eth->mii_bus) { 293 err = -ENOMEM; 294 goto err_put_node; 295 } 296 297 eth->mii_bus->name = "mdio"; 298 eth->mii_bus->read = mtk_mdio_read; 299 eth->mii_bus->write = mtk_mdio_write; 300 eth->mii_bus->priv = eth; 301 eth->mii_bus->parent = eth->dev; 302 303 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name); 304 err = of_mdiobus_register(eth->mii_bus, mii_np); 305 if (err) 306 goto err_free_bus; 307 308 return 0; 309 310 err_free_bus: 311 mdiobus_free(eth->mii_bus); 312 313 err_put_node: 314 of_node_put(mii_np); 315 eth->mii_bus = NULL; 316 return err; 317 } 318 319 static void mtk_mdio_cleanup(struct mtk_eth *eth) 320 { 321 if (!eth->mii_bus) 322 return; 323 324 mdiobus_unregister(eth->mii_bus); 325 of_node_put(eth->mii_bus->dev.of_node); 326 mdiobus_free(eth->mii_bus); 327 } 328 329 static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask) 330 { 331 u32 val; 332 333 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 334 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 335 /* flush write */ 336 mtk_r32(eth, MTK_QDMA_INT_MASK); 337 } 338 339 static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask) 340 { 341 u32 val; 342 343 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 344 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 345 /* flush write */ 346 mtk_r32(eth, MTK_QDMA_INT_MASK); 347 } 348 349 static int mtk_set_mac_address(struct net_device *dev, void *p) 350 { 351 int ret = eth_mac_addr(dev, p); 352 struct mtk_mac *mac = netdev_priv(dev); 353 const char *macaddr = dev->dev_addr; 354 unsigned long flags; 355 356 if (ret) 357 return ret; 358 359 spin_lock_irqsave(&mac->hw->page_lock, flags); 360 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 361 MTK_GDMA_MAC_ADRH(mac->id)); 362 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 363 (macaddr[4] << 8) | macaddr[5], 364 MTK_GDMA_MAC_ADRL(mac->id)); 365 spin_unlock_irqrestore(&mac->hw->page_lock, flags); 366 367 return 0; 368 } 369 370 void mtk_stats_update_mac(struct mtk_mac *mac) 371 { 372 struct mtk_hw_stats *hw_stats = mac->hw_stats; 373 unsigned int base = MTK_GDM1_TX_GBCNT; 374 u64 stats; 375 376 base += hw_stats->reg_offset; 377 378 u64_stats_update_begin(&hw_stats->syncp); 379 380 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 381 stats = mtk_r32(mac->hw, base + 0x04); 382 if (stats) 383 hw_stats->rx_bytes += (stats << 32); 384 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 385 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 386 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 387 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 388 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 389 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 390 hw_stats->rx_flow_control_packets += 391 mtk_r32(mac->hw, base + 0x24); 392 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 393 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 394 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 395 stats = mtk_r32(mac->hw, base + 0x34); 396 if (stats) 397 hw_stats->tx_bytes += (stats << 32); 398 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 399 u64_stats_update_end(&hw_stats->syncp); 400 } 401 402 static void mtk_stats_update(struct mtk_eth *eth) 403 { 404 int i; 405 406 for (i = 0; i < MTK_MAC_COUNT; i++) { 407 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 408 continue; 409 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 410 mtk_stats_update_mac(eth->mac[i]); 411 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 412 } 413 } 414 } 415 416 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev, 417 struct rtnl_link_stats64 *storage) 418 { 419 struct mtk_mac *mac = netdev_priv(dev); 420 struct mtk_hw_stats *hw_stats = mac->hw_stats; 421 unsigned int start; 422 423 if (netif_running(dev) && netif_device_present(dev)) { 424 if (spin_trylock(&hw_stats->stats_lock)) { 425 mtk_stats_update_mac(mac); 426 spin_unlock(&hw_stats->stats_lock); 427 } 428 } 429 430 do { 431 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 432 storage->rx_packets = hw_stats->rx_packets; 433 storage->tx_packets = hw_stats->tx_packets; 434 storage->rx_bytes = hw_stats->rx_bytes; 435 storage->tx_bytes = hw_stats->tx_bytes; 436 storage->collisions = hw_stats->tx_collisions; 437 storage->rx_length_errors = hw_stats->rx_short_errors + 438 hw_stats->rx_long_errors; 439 storage->rx_over_errors = hw_stats->rx_overflow; 440 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 441 storage->rx_errors = hw_stats->rx_checksum_errors; 442 storage->tx_aborted_errors = hw_stats->tx_skip; 443 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 444 445 storage->tx_errors = dev->stats.tx_errors; 446 storage->rx_dropped = dev->stats.rx_dropped; 447 storage->tx_dropped = dev->stats.tx_dropped; 448 449 return storage; 450 } 451 452 static inline int mtk_max_frag_size(int mtu) 453 { 454 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 455 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 456 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 457 458 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 459 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 460 } 461 462 static inline int mtk_max_buf_size(int frag_size) 463 { 464 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 465 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 466 467 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 468 469 return buf_size; 470 } 471 472 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 473 struct mtk_rx_dma *dma_rxd) 474 { 475 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 476 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 477 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 478 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 479 } 480 481 /* the qdma core needs scratch memory to be setup */ 482 static int mtk_init_fq_dma(struct mtk_eth *eth) 483 { 484 dma_addr_t phy_ring_head, phy_ring_tail; 485 int cnt = MTK_DMA_SIZE; 486 dma_addr_t dma_addr; 487 int i; 488 489 eth->scratch_ring = dma_alloc_coherent(eth->dev, 490 cnt * sizeof(struct mtk_tx_dma), 491 &phy_ring_head, 492 GFP_ATOMIC | __GFP_ZERO); 493 if (unlikely(!eth->scratch_ring)) 494 return -ENOMEM; 495 496 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 497 GFP_KERNEL); 498 dma_addr = dma_map_single(eth->dev, 499 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 500 DMA_FROM_DEVICE); 501 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 502 return -ENOMEM; 503 504 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt); 505 phy_ring_tail = phy_ring_head + 506 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 507 508 for (i = 0; i < cnt; i++) { 509 eth->scratch_ring[i].txd1 = 510 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 511 if (i < cnt - 1) 512 eth->scratch_ring[i].txd2 = (phy_ring_head + 513 ((i + 1) * sizeof(struct mtk_tx_dma))); 514 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 515 } 516 517 mtk_w32(eth, phy_ring_head, MTK_QDMA_FQ_HEAD); 518 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 519 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 520 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 521 522 return 0; 523 } 524 525 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 526 { 527 void *ret = ring->dma; 528 529 return ret + (desc - ring->phys); 530 } 531 532 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 533 struct mtk_tx_dma *txd) 534 { 535 int idx = txd - ring->dma; 536 537 return &ring->buf[idx]; 538 } 539 540 static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf) 541 { 542 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 543 dma_unmap_single(dev, 544 dma_unmap_addr(tx_buf, dma_addr0), 545 dma_unmap_len(tx_buf, dma_len0), 546 DMA_TO_DEVICE); 547 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 548 dma_unmap_page(dev, 549 dma_unmap_addr(tx_buf, dma_addr0), 550 dma_unmap_len(tx_buf, dma_len0), 551 DMA_TO_DEVICE); 552 } 553 tx_buf->flags = 0; 554 if (tx_buf->skb && 555 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 556 dev_kfree_skb_any(tx_buf->skb); 557 tx_buf->skb = NULL; 558 } 559 560 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 561 int tx_num, struct mtk_tx_ring *ring, bool gso) 562 { 563 struct mtk_mac *mac = netdev_priv(dev); 564 struct mtk_eth *eth = mac->hw; 565 struct mtk_tx_dma *itxd, *txd; 566 struct mtk_tx_buf *tx_buf; 567 dma_addr_t mapped_addr; 568 unsigned int nr_frags; 569 int i, n_desc = 1; 570 u32 txd4 = 0; 571 572 itxd = ring->next_free; 573 if (itxd == ring->last_free) 574 return -ENOMEM; 575 576 /* set the forward port */ 577 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT; 578 579 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 580 memset(tx_buf, 0, sizeof(*tx_buf)); 581 582 if (gso) 583 txd4 |= TX_DMA_TSO; 584 585 /* TX Checksum offload */ 586 if (skb->ip_summed == CHECKSUM_PARTIAL) 587 txd4 |= TX_DMA_CHKSUM; 588 589 /* VLAN header offload */ 590 if (skb_vlan_tag_present(skb)) 591 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 592 593 mapped_addr = dma_map_single(&dev->dev, skb->data, 594 skb_headlen(skb), DMA_TO_DEVICE); 595 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr))) 596 return -ENOMEM; 597 598 WRITE_ONCE(itxd->txd1, mapped_addr); 599 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 600 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 601 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb)); 602 603 /* TX SG offload */ 604 txd = itxd; 605 nr_frags = skb_shinfo(skb)->nr_frags; 606 for (i = 0; i < nr_frags; i++) { 607 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 608 unsigned int offset = 0; 609 int frag_size = skb_frag_size(frag); 610 611 while (frag_size) { 612 bool last_frag = false; 613 unsigned int frag_map_size; 614 615 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 616 if (txd == ring->last_free) 617 goto err_dma; 618 619 n_desc++; 620 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 621 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset, 622 frag_map_size, 623 DMA_TO_DEVICE); 624 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr))) 625 goto err_dma; 626 627 if (i == nr_frags - 1 && 628 (frag_size - frag_map_size) == 0) 629 last_frag = true; 630 631 WRITE_ONCE(txd->txd1, mapped_addr); 632 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 633 TX_DMA_PLEN0(frag_map_size) | 634 last_frag * TX_DMA_LS0)); 635 WRITE_ONCE(txd->txd4, 0); 636 637 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 638 tx_buf = mtk_desc_to_tx_buf(ring, txd); 639 memset(tx_buf, 0, sizeof(*tx_buf)); 640 641 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 642 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 643 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 644 frag_size -= frag_map_size; 645 offset += frag_map_size; 646 } 647 } 648 649 /* store skb to cleanup */ 650 tx_buf->skb = skb; 651 652 WRITE_ONCE(itxd->txd4, txd4); 653 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 654 (!nr_frags * TX_DMA_LS0))); 655 656 netdev_sent_queue(dev, skb->len); 657 skb_tx_timestamp(skb); 658 659 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 660 atomic_sub(n_desc, &ring->free_count); 661 662 /* make sure that all changes to the dma ring are flushed before we 663 * continue 664 */ 665 wmb(); 666 667 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) 668 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 669 670 return 0; 671 672 err_dma: 673 do { 674 tx_buf = mtk_desc_to_tx_buf(ring, txd); 675 676 /* unmap dma */ 677 mtk_tx_unmap(&dev->dev, tx_buf); 678 679 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 680 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 681 } while (itxd != txd); 682 683 return -ENOMEM; 684 } 685 686 static inline int mtk_cal_txd_req(struct sk_buff *skb) 687 { 688 int i, nfrags; 689 struct skb_frag_struct *frag; 690 691 nfrags = 1; 692 if (skb_is_gso(skb)) { 693 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 694 frag = &skb_shinfo(skb)->frags[i]; 695 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 696 } 697 } else { 698 nfrags += skb_shinfo(skb)->nr_frags; 699 } 700 701 return nfrags; 702 } 703 704 static void mtk_wake_queue(struct mtk_eth *eth) 705 { 706 int i; 707 708 for (i = 0; i < MTK_MAC_COUNT; i++) { 709 if (!eth->netdev[i]) 710 continue; 711 netif_wake_queue(eth->netdev[i]); 712 } 713 } 714 715 static void mtk_stop_queue(struct mtk_eth *eth) 716 { 717 int i; 718 719 for (i = 0; i < MTK_MAC_COUNT; i++) { 720 if (!eth->netdev[i]) 721 continue; 722 netif_stop_queue(eth->netdev[i]); 723 } 724 } 725 726 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 727 { 728 struct mtk_mac *mac = netdev_priv(dev); 729 struct mtk_eth *eth = mac->hw; 730 struct mtk_tx_ring *ring = ð->tx_ring; 731 struct net_device_stats *stats = &dev->stats; 732 unsigned long flags; 733 bool gso = false; 734 int tx_num; 735 736 /* normally we can rely on the stack not calling this more than once, 737 * however we have 2 queues running on the same ring so we need to lock 738 * the ring access 739 */ 740 spin_lock_irqsave(ð->page_lock, flags); 741 742 tx_num = mtk_cal_txd_req(skb); 743 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 744 mtk_stop_queue(eth); 745 netif_err(eth, tx_queued, dev, 746 "Tx Ring full when queue awake!\n"); 747 spin_unlock_irqrestore(ð->page_lock, flags); 748 return NETDEV_TX_BUSY; 749 } 750 751 /* TSO: fill MSS info in tcp checksum field */ 752 if (skb_is_gso(skb)) { 753 if (skb_cow_head(skb, 0)) { 754 netif_warn(eth, tx_err, dev, 755 "GSO expand head fail.\n"); 756 goto drop; 757 } 758 759 if (skb_shinfo(skb)->gso_type & 760 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 761 gso = true; 762 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 763 } 764 } 765 766 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 767 goto drop; 768 769 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) { 770 mtk_stop_queue(eth); 771 if (unlikely(atomic_read(&ring->free_count) > 772 ring->thresh)) 773 mtk_wake_queue(eth); 774 } 775 spin_unlock_irqrestore(ð->page_lock, flags); 776 777 return NETDEV_TX_OK; 778 779 drop: 780 spin_unlock_irqrestore(ð->page_lock, flags); 781 stats->tx_dropped++; 782 dev_kfree_skb(skb); 783 return NETDEV_TX_OK; 784 } 785 786 static int mtk_poll_rx(struct napi_struct *napi, int budget, 787 struct mtk_eth *eth, u32 rx_intr) 788 { 789 struct mtk_rx_ring *ring = ð->rx_ring; 790 int idx = ring->calc_idx; 791 struct sk_buff *skb; 792 u8 *data, *new_data; 793 struct mtk_rx_dma *rxd, trxd; 794 int done = 0; 795 796 while (done < budget) { 797 struct net_device *netdev; 798 unsigned int pktlen; 799 dma_addr_t dma_addr; 800 int mac = 0; 801 802 idx = NEXT_RX_DESP_IDX(idx); 803 rxd = &ring->dma[idx]; 804 data = ring->data[idx]; 805 806 mtk_rx_get_desc(&trxd, rxd); 807 if (!(trxd.rxd2 & RX_DMA_DONE)) 808 break; 809 810 /* find out which mac the packet come from. values start at 1 */ 811 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 812 RX_DMA_FPORT_MASK; 813 mac--; 814 815 netdev = eth->netdev[mac]; 816 817 /* alloc new buffer */ 818 new_data = napi_alloc_frag(ring->frag_size); 819 if (unlikely(!new_data)) { 820 netdev->stats.rx_dropped++; 821 goto release_desc; 822 } 823 dma_addr = dma_map_single(ð->netdev[mac]->dev, 824 new_data + NET_SKB_PAD, 825 ring->buf_size, 826 DMA_FROM_DEVICE); 827 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) { 828 skb_free_frag(new_data); 829 goto release_desc; 830 } 831 832 /* receive data */ 833 skb = build_skb(data, ring->frag_size); 834 if (unlikely(!skb)) { 835 put_page(virt_to_head_page(new_data)); 836 goto release_desc; 837 } 838 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 839 840 dma_unmap_single(&netdev->dev, trxd.rxd1, 841 ring->buf_size, DMA_FROM_DEVICE); 842 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 843 skb->dev = netdev; 844 skb_put(skb, pktlen); 845 if (trxd.rxd4 & RX_DMA_L4_VALID) 846 skb->ip_summed = CHECKSUM_UNNECESSARY; 847 else 848 skb_checksum_none_assert(skb); 849 skb->protocol = eth_type_trans(skb, netdev); 850 851 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 852 RX_DMA_VID(trxd.rxd3)) 853 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 854 RX_DMA_VID(trxd.rxd3)); 855 napi_gro_receive(napi, skb); 856 857 ring->data[idx] = new_data; 858 rxd->rxd1 = (unsigned int)dma_addr; 859 860 release_desc: 861 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 862 863 ring->calc_idx = idx; 864 /* make sure that all changes to the dma ring are flushed before 865 * we continue 866 */ 867 wmb(); 868 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0); 869 done++; 870 } 871 872 if (done < budget) 873 mtk_w32(eth, rx_intr, MTK_QMTK_INT_STATUS); 874 875 return done; 876 } 877 878 static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again) 879 { 880 struct mtk_tx_ring *ring = ð->tx_ring; 881 struct mtk_tx_dma *desc; 882 struct sk_buff *skb; 883 struct mtk_tx_buf *tx_buf; 884 int total = 0, done[MTK_MAX_DEVS]; 885 unsigned int bytes[MTK_MAX_DEVS]; 886 u32 cpu, dma; 887 static int condition; 888 int i; 889 890 memset(done, 0, sizeof(done)); 891 memset(bytes, 0, sizeof(bytes)); 892 893 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 894 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 895 896 desc = mtk_qdma_phys_to_virt(ring, cpu); 897 898 while ((cpu != dma) && budget) { 899 u32 next_cpu = desc->txd2; 900 int mac; 901 902 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 903 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 904 break; 905 906 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) & 907 TX_DMA_FPORT_MASK; 908 mac--; 909 910 tx_buf = mtk_desc_to_tx_buf(ring, desc); 911 skb = tx_buf->skb; 912 if (!skb) { 913 condition = 1; 914 break; 915 } 916 917 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 918 bytes[mac] += skb->len; 919 done[mac]++; 920 budget--; 921 } 922 mtk_tx_unmap(eth->dev, tx_buf); 923 924 ring->last_free->txd2 = next_cpu; 925 ring->last_free = desc; 926 atomic_inc(&ring->free_count); 927 928 cpu = next_cpu; 929 } 930 931 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 932 933 for (i = 0; i < MTK_MAC_COUNT; i++) { 934 if (!eth->netdev[i] || !done[i]) 935 continue; 936 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 937 total += done[i]; 938 } 939 940 /* read hw index again make sure no new tx packet */ 941 if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR)) 942 *tx_again = true; 943 else 944 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 945 946 if (!total) 947 return 0; 948 949 if (atomic_read(&ring->free_count) > ring->thresh) 950 mtk_wake_queue(eth); 951 952 return total; 953 } 954 955 static int mtk_poll(struct napi_struct *napi, int budget) 956 { 957 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 958 u32 status, status2, mask, tx_intr, rx_intr, status_intr; 959 int tx_done, rx_done; 960 bool tx_again = false; 961 962 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 963 status2 = mtk_r32(eth, MTK_INT_STATUS2); 964 tx_intr = MTK_TX_DONE_INT; 965 rx_intr = MTK_RX_DONE_INT; 966 status_intr = (MTK_GDM1_AF | MTK_GDM2_AF); 967 tx_done = 0; 968 rx_done = 0; 969 tx_again = 0; 970 971 if (status & tx_intr) 972 tx_done = mtk_poll_tx(eth, budget, &tx_again); 973 974 if (status & rx_intr) 975 rx_done = mtk_poll_rx(napi, budget, eth, rx_intr); 976 977 if (unlikely(status2 & status_intr)) { 978 mtk_stats_update(eth); 979 mtk_w32(eth, status_intr, MTK_INT_STATUS2); 980 } 981 982 if (unlikely(netif_msg_intr(eth))) { 983 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 984 netdev_info(eth->netdev[0], 985 "done tx %d, rx %d, intr 0x%08x/0x%x\n", 986 tx_done, rx_done, status, mask); 987 } 988 989 if (tx_again || rx_done == budget) 990 return budget; 991 992 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 993 if (status & (tx_intr | rx_intr)) 994 return budget; 995 996 napi_complete(napi); 997 mtk_irq_enable(eth, tx_intr | rx_intr); 998 999 return rx_done; 1000 } 1001 1002 static int mtk_tx_alloc(struct mtk_eth *eth) 1003 { 1004 struct mtk_tx_ring *ring = ð->tx_ring; 1005 int i, sz = sizeof(*ring->dma); 1006 1007 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1008 GFP_KERNEL); 1009 if (!ring->buf) 1010 goto no_tx_mem; 1011 1012 ring->dma = dma_alloc_coherent(eth->dev, 1013 MTK_DMA_SIZE * sz, 1014 &ring->phys, 1015 GFP_ATOMIC | __GFP_ZERO); 1016 if (!ring->dma) 1017 goto no_tx_mem; 1018 1019 memset(ring->dma, 0, MTK_DMA_SIZE * sz); 1020 for (i = 0; i < MTK_DMA_SIZE; i++) { 1021 int next = (i + 1) % MTK_DMA_SIZE; 1022 u32 next_ptr = ring->phys + next * sz; 1023 1024 ring->dma[i].txd2 = next_ptr; 1025 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1026 } 1027 1028 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1029 ring->next_free = &ring->dma[0]; 1030 ring->last_free = &ring->dma[MTK_DMA_SIZE - 2]; 1031 ring->thresh = max((unsigned long)MTK_DMA_SIZE >> 2, 1032 MAX_SKB_FRAGS); 1033 1034 /* make sure that all changes to the dma ring are flushed before we 1035 * continue 1036 */ 1037 wmb(); 1038 1039 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1040 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1041 mtk_w32(eth, 1042 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1043 MTK_QTX_CRX_PTR); 1044 mtk_w32(eth, 1045 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1046 MTK_QTX_DRX_PTR); 1047 1048 return 0; 1049 1050 no_tx_mem: 1051 return -ENOMEM; 1052 } 1053 1054 static void mtk_tx_clean(struct mtk_eth *eth) 1055 { 1056 struct mtk_tx_ring *ring = ð->tx_ring; 1057 int i; 1058 1059 if (ring->buf) { 1060 for (i = 0; i < MTK_DMA_SIZE; i++) 1061 mtk_tx_unmap(eth->dev, &ring->buf[i]); 1062 kfree(ring->buf); 1063 ring->buf = NULL; 1064 } 1065 1066 if (ring->dma) { 1067 dma_free_coherent(eth->dev, 1068 MTK_DMA_SIZE * sizeof(*ring->dma), 1069 ring->dma, 1070 ring->phys); 1071 ring->dma = NULL; 1072 } 1073 } 1074 1075 static int mtk_rx_alloc(struct mtk_eth *eth) 1076 { 1077 struct mtk_rx_ring *ring = ð->rx_ring; 1078 int i; 1079 1080 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN); 1081 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1082 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data), 1083 GFP_KERNEL); 1084 if (!ring->data) 1085 return -ENOMEM; 1086 1087 for (i = 0; i < MTK_DMA_SIZE; i++) { 1088 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1089 if (!ring->data[i]) 1090 return -ENOMEM; 1091 } 1092 1093 ring->dma = dma_alloc_coherent(eth->dev, 1094 MTK_DMA_SIZE * sizeof(*ring->dma), 1095 &ring->phys, 1096 GFP_ATOMIC | __GFP_ZERO); 1097 if (!ring->dma) 1098 return -ENOMEM; 1099 1100 for (i = 0; i < MTK_DMA_SIZE; i++) { 1101 dma_addr_t dma_addr = dma_map_single(eth->dev, 1102 ring->data[i] + NET_SKB_PAD, 1103 ring->buf_size, 1104 DMA_FROM_DEVICE); 1105 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1106 return -ENOMEM; 1107 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1108 1109 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1110 } 1111 ring->calc_idx = MTK_DMA_SIZE - 1; 1112 /* make sure that all changes to the dma ring are flushed before we 1113 * continue 1114 */ 1115 wmb(); 1116 1117 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0); 1118 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0); 1119 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0); 1120 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX); 1121 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1122 1123 return 0; 1124 } 1125 1126 static void mtk_rx_clean(struct mtk_eth *eth) 1127 { 1128 struct mtk_rx_ring *ring = ð->rx_ring; 1129 int i; 1130 1131 if (ring->data && ring->dma) { 1132 for (i = 0; i < MTK_DMA_SIZE; i++) { 1133 if (!ring->data[i]) 1134 continue; 1135 if (!ring->dma[i].rxd1) 1136 continue; 1137 dma_unmap_single(eth->dev, 1138 ring->dma[i].rxd1, 1139 ring->buf_size, 1140 DMA_FROM_DEVICE); 1141 skb_free_frag(ring->data[i]); 1142 } 1143 kfree(ring->data); 1144 ring->data = NULL; 1145 } 1146 1147 if (ring->dma) { 1148 dma_free_coherent(eth->dev, 1149 MTK_DMA_SIZE * sizeof(*ring->dma), 1150 ring->dma, 1151 ring->phys); 1152 ring->dma = NULL; 1153 } 1154 } 1155 1156 /* wait for DMA to finish whatever it is doing before we start using it again */ 1157 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1158 { 1159 unsigned long t_start = jiffies; 1160 1161 while (1) { 1162 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1163 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1164 return 0; 1165 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1166 break; 1167 } 1168 1169 dev_err(eth->dev, "DMA init timeout\n"); 1170 return -1; 1171 } 1172 1173 static int mtk_dma_init(struct mtk_eth *eth) 1174 { 1175 int err; 1176 1177 if (mtk_dma_busy_wait(eth)) 1178 return -EBUSY; 1179 1180 /* QDMA needs scratch memory for internal reordering of the 1181 * descriptors 1182 */ 1183 err = mtk_init_fq_dma(eth); 1184 if (err) 1185 return err; 1186 1187 err = mtk_tx_alloc(eth); 1188 if (err) 1189 return err; 1190 1191 err = mtk_rx_alloc(eth); 1192 if (err) 1193 return err; 1194 1195 /* Enable random early drop and set drop threshold automatically */ 1196 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1197 MTK_QDMA_FC_THRES); 1198 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1199 1200 return 0; 1201 } 1202 1203 static void mtk_dma_free(struct mtk_eth *eth) 1204 { 1205 int i; 1206 1207 for (i = 0; i < MTK_MAC_COUNT; i++) 1208 if (eth->netdev[i]) 1209 netdev_reset_queue(eth->netdev[i]); 1210 mtk_tx_clean(eth); 1211 mtk_rx_clean(eth); 1212 kfree(eth->scratch_head); 1213 } 1214 1215 static void mtk_tx_timeout(struct net_device *dev) 1216 { 1217 struct mtk_mac *mac = netdev_priv(dev); 1218 struct mtk_eth *eth = mac->hw; 1219 1220 eth->netdev[mac->id]->stats.tx_errors++; 1221 netif_err(eth, tx_err, dev, 1222 "transmit timed out\n"); 1223 schedule_work(ð->pending_work); 1224 } 1225 1226 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 1227 { 1228 struct mtk_eth *eth = _eth; 1229 u32 status; 1230 1231 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1232 if (unlikely(!status)) 1233 return IRQ_NONE; 1234 1235 if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) { 1236 if (likely(napi_schedule_prep(ð->rx_napi))) 1237 __napi_schedule(ð->rx_napi); 1238 } else { 1239 mtk_w32(eth, status, MTK_QMTK_INT_STATUS); 1240 } 1241 mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT)); 1242 1243 return IRQ_HANDLED; 1244 } 1245 1246 #ifdef CONFIG_NET_POLL_CONTROLLER 1247 static void mtk_poll_controller(struct net_device *dev) 1248 { 1249 struct mtk_mac *mac = netdev_priv(dev); 1250 struct mtk_eth *eth = mac->hw; 1251 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT; 1252 1253 mtk_irq_disable(eth, int_mask); 1254 mtk_handle_irq(dev->irq, dev); 1255 mtk_irq_enable(eth, int_mask); 1256 } 1257 #endif 1258 1259 static int mtk_start_dma(struct mtk_eth *eth) 1260 { 1261 int err; 1262 1263 err = mtk_dma_init(eth); 1264 if (err) { 1265 mtk_dma_free(eth); 1266 return err; 1267 } 1268 1269 mtk_w32(eth, 1270 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN | 1271 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS | 1272 MTK_RX_BT_32DWORDS, 1273 MTK_QDMA_GLO_CFG); 1274 1275 return 0; 1276 } 1277 1278 static int mtk_open(struct net_device *dev) 1279 { 1280 struct mtk_mac *mac = netdev_priv(dev); 1281 struct mtk_eth *eth = mac->hw; 1282 1283 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1284 if (!atomic_read(ð->dma_refcnt)) { 1285 int err = mtk_start_dma(eth); 1286 1287 if (err) 1288 return err; 1289 1290 napi_enable(ð->rx_napi); 1291 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT); 1292 } 1293 atomic_inc(ð->dma_refcnt); 1294 1295 phy_start(mac->phy_dev); 1296 netif_start_queue(dev); 1297 1298 return 0; 1299 } 1300 1301 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1302 { 1303 unsigned long flags; 1304 u32 val; 1305 int i; 1306 1307 /* stop the dma engine */ 1308 spin_lock_irqsave(ð->page_lock, flags); 1309 val = mtk_r32(eth, glo_cfg); 1310 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1311 glo_cfg); 1312 spin_unlock_irqrestore(ð->page_lock, flags); 1313 1314 /* wait for dma stop */ 1315 for (i = 0; i < 10; i++) { 1316 val = mtk_r32(eth, glo_cfg); 1317 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1318 msleep(20); 1319 continue; 1320 } 1321 break; 1322 } 1323 } 1324 1325 static int mtk_stop(struct net_device *dev) 1326 { 1327 struct mtk_mac *mac = netdev_priv(dev); 1328 struct mtk_eth *eth = mac->hw; 1329 1330 netif_tx_disable(dev); 1331 phy_stop(mac->phy_dev); 1332 1333 /* only shutdown DMA if this is the last user */ 1334 if (!atomic_dec_and_test(ð->dma_refcnt)) 1335 return 0; 1336 1337 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT); 1338 napi_disable(ð->rx_napi); 1339 1340 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1341 1342 mtk_dma_free(eth); 1343 1344 return 0; 1345 } 1346 1347 static int __init mtk_hw_init(struct mtk_eth *eth) 1348 { 1349 int err, i; 1350 1351 /* reset the frame engine */ 1352 reset_control_assert(eth->rstc); 1353 usleep_range(10, 20); 1354 reset_control_deassert(eth->rstc); 1355 usleep_range(10, 20); 1356 1357 /* Set GE2 driving and slew rate */ 1358 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1359 1360 /* set GE2 TDSEL */ 1361 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1362 1363 /* set GE2 TUNE */ 1364 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1365 1366 /* GE1, Force 1000M/FD, FC ON */ 1367 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0)); 1368 1369 /* GE2, Force 1000M/FD, FC ON */ 1370 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1)); 1371 1372 /* Enable RX VLan Offloading */ 1373 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1374 1375 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0, 1376 dev_name(eth->dev), eth); 1377 if (err) 1378 return err; 1379 1380 err = mtk_mdio_init(eth); 1381 if (err) 1382 return err; 1383 1384 /* disable delay and normal interrupt */ 1385 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1386 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT); 1387 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1388 mtk_w32(eth, 0, MTK_RST_GL); 1389 1390 /* FE int grouping */ 1391 mtk_w32(eth, 0, MTK_FE_INT_GRP); 1392 1393 for (i = 0; i < 2; i++) { 1394 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1395 1396 /* setup the forward port to send frame to QDMA */ 1397 val &= ~0xffff; 1398 val |= 0x5555; 1399 1400 /* Enable RX checksum */ 1401 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1402 1403 /* setup the mac dma */ 1404 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 1405 } 1406 1407 return 0; 1408 } 1409 1410 static int __init mtk_init(struct net_device *dev) 1411 { 1412 struct mtk_mac *mac = netdev_priv(dev); 1413 struct mtk_eth *eth = mac->hw; 1414 const char *mac_addr; 1415 1416 mac_addr = of_get_mac_address(mac->of_node); 1417 if (mac_addr) 1418 ether_addr_copy(dev->dev_addr, mac_addr); 1419 1420 /* If the mac address is invalid, use random mac address */ 1421 if (!is_valid_ether_addr(dev->dev_addr)) { 1422 random_ether_addr(dev->dev_addr); 1423 dev_err(eth->dev, "generated random MAC address %pM\n", 1424 dev->dev_addr); 1425 dev->addr_assign_type = NET_ADDR_RANDOM; 1426 } 1427 1428 return mtk_phy_connect(mac); 1429 } 1430 1431 static void mtk_uninit(struct net_device *dev) 1432 { 1433 struct mtk_mac *mac = netdev_priv(dev); 1434 struct mtk_eth *eth = mac->hw; 1435 1436 phy_disconnect(mac->phy_dev); 1437 mtk_mdio_cleanup(eth); 1438 mtk_irq_disable(eth, ~0); 1439 free_irq(dev->irq, dev); 1440 } 1441 1442 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1443 { 1444 struct mtk_mac *mac = netdev_priv(dev); 1445 1446 switch (cmd) { 1447 case SIOCGMIIPHY: 1448 case SIOCGMIIREG: 1449 case SIOCSMIIREG: 1450 return phy_mii_ioctl(mac->phy_dev, ifr, cmd); 1451 default: 1452 break; 1453 } 1454 1455 return -EOPNOTSUPP; 1456 } 1457 1458 static void mtk_pending_work(struct work_struct *work) 1459 { 1460 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 1461 int err, i; 1462 unsigned long restart = 0; 1463 1464 rtnl_lock(); 1465 1466 /* stop all devices to make sure that dma is properly shut down */ 1467 for (i = 0; i < MTK_MAC_COUNT; i++) { 1468 if (!eth->netdev[i]) 1469 continue; 1470 mtk_stop(eth->netdev[i]); 1471 __set_bit(i, &restart); 1472 } 1473 1474 /* restart DMA and enable IRQs */ 1475 for (i = 0; i < MTK_MAC_COUNT; i++) { 1476 if (!test_bit(i, &restart)) 1477 continue; 1478 err = mtk_open(eth->netdev[i]); 1479 if (err) { 1480 netif_alert(eth, ifup, eth->netdev[i], 1481 "Driver up/down cycle failed, closing device.\n"); 1482 dev_close(eth->netdev[i]); 1483 } 1484 } 1485 rtnl_unlock(); 1486 } 1487 1488 static int mtk_cleanup(struct mtk_eth *eth) 1489 { 1490 int i; 1491 1492 for (i = 0; i < MTK_MAC_COUNT; i++) { 1493 if (!eth->netdev[i]) 1494 continue; 1495 1496 unregister_netdev(eth->netdev[i]); 1497 free_netdev(eth->netdev[i]); 1498 } 1499 cancel_work_sync(ð->pending_work); 1500 1501 return 0; 1502 } 1503 1504 static int mtk_get_settings(struct net_device *dev, 1505 struct ethtool_cmd *cmd) 1506 { 1507 struct mtk_mac *mac = netdev_priv(dev); 1508 int err; 1509 1510 err = phy_read_status(mac->phy_dev); 1511 if (err) 1512 return -ENODEV; 1513 1514 return phy_ethtool_gset(mac->phy_dev, cmd); 1515 } 1516 1517 static int mtk_set_settings(struct net_device *dev, 1518 struct ethtool_cmd *cmd) 1519 { 1520 struct mtk_mac *mac = netdev_priv(dev); 1521 1522 if (cmd->phy_address != mac->phy_dev->mdio.addr) { 1523 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus, 1524 cmd->phy_address); 1525 if (!mac->phy_dev) 1526 return -ENODEV; 1527 } 1528 1529 return phy_ethtool_sset(mac->phy_dev, cmd); 1530 } 1531 1532 static void mtk_get_drvinfo(struct net_device *dev, 1533 struct ethtool_drvinfo *info) 1534 { 1535 struct mtk_mac *mac = netdev_priv(dev); 1536 1537 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 1538 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 1539 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 1540 } 1541 1542 static u32 mtk_get_msglevel(struct net_device *dev) 1543 { 1544 struct mtk_mac *mac = netdev_priv(dev); 1545 1546 return mac->hw->msg_enable; 1547 } 1548 1549 static void mtk_set_msglevel(struct net_device *dev, u32 value) 1550 { 1551 struct mtk_mac *mac = netdev_priv(dev); 1552 1553 mac->hw->msg_enable = value; 1554 } 1555 1556 static int mtk_nway_reset(struct net_device *dev) 1557 { 1558 struct mtk_mac *mac = netdev_priv(dev); 1559 1560 return genphy_restart_aneg(mac->phy_dev); 1561 } 1562 1563 static u32 mtk_get_link(struct net_device *dev) 1564 { 1565 struct mtk_mac *mac = netdev_priv(dev); 1566 int err; 1567 1568 err = genphy_update_link(mac->phy_dev); 1569 if (err) 1570 return ethtool_op_get_link(dev); 1571 1572 return mac->phy_dev->link; 1573 } 1574 1575 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1576 { 1577 int i; 1578 1579 switch (stringset) { 1580 case ETH_SS_STATS: 1581 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 1582 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 1583 data += ETH_GSTRING_LEN; 1584 } 1585 break; 1586 } 1587 } 1588 1589 static int mtk_get_sset_count(struct net_device *dev, int sset) 1590 { 1591 switch (sset) { 1592 case ETH_SS_STATS: 1593 return ARRAY_SIZE(mtk_ethtool_stats); 1594 default: 1595 return -EOPNOTSUPP; 1596 } 1597 } 1598 1599 static void mtk_get_ethtool_stats(struct net_device *dev, 1600 struct ethtool_stats *stats, u64 *data) 1601 { 1602 struct mtk_mac *mac = netdev_priv(dev); 1603 struct mtk_hw_stats *hwstats = mac->hw_stats; 1604 u64 *data_src, *data_dst; 1605 unsigned int start; 1606 int i; 1607 1608 if (netif_running(dev) && netif_device_present(dev)) { 1609 if (spin_trylock(&hwstats->stats_lock)) { 1610 mtk_stats_update_mac(mac); 1611 spin_unlock(&hwstats->stats_lock); 1612 } 1613 } 1614 1615 do { 1616 data_src = (u64*)hwstats; 1617 data_dst = data; 1618 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 1619 1620 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 1621 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 1622 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 1623 } 1624 1625 static struct ethtool_ops mtk_ethtool_ops = { 1626 .get_settings = mtk_get_settings, 1627 .set_settings = mtk_set_settings, 1628 .get_drvinfo = mtk_get_drvinfo, 1629 .get_msglevel = mtk_get_msglevel, 1630 .set_msglevel = mtk_set_msglevel, 1631 .nway_reset = mtk_nway_reset, 1632 .get_link = mtk_get_link, 1633 .get_strings = mtk_get_strings, 1634 .get_sset_count = mtk_get_sset_count, 1635 .get_ethtool_stats = mtk_get_ethtool_stats, 1636 }; 1637 1638 static const struct net_device_ops mtk_netdev_ops = { 1639 .ndo_init = mtk_init, 1640 .ndo_uninit = mtk_uninit, 1641 .ndo_open = mtk_open, 1642 .ndo_stop = mtk_stop, 1643 .ndo_start_xmit = mtk_start_xmit, 1644 .ndo_set_mac_address = mtk_set_mac_address, 1645 .ndo_validate_addr = eth_validate_addr, 1646 .ndo_do_ioctl = mtk_do_ioctl, 1647 .ndo_change_mtu = eth_change_mtu, 1648 .ndo_tx_timeout = mtk_tx_timeout, 1649 .ndo_get_stats64 = mtk_get_stats64, 1650 #ifdef CONFIG_NET_POLL_CONTROLLER 1651 .ndo_poll_controller = mtk_poll_controller, 1652 #endif 1653 }; 1654 1655 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 1656 { 1657 struct mtk_mac *mac; 1658 const __be32 *_id = of_get_property(np, "reg", NULL); 1659 int id, err; 1660 1661 if (!_id) { 1662 dev_err(eth->dev, "missing mac id\n"); 1663 return -EINVAL; 1664 } 1665 1666 id = be32_to_cpup(_id); 1667 if (id >= MTK_MAC_COUNT) { 1668 dev_err(eth->dev, "%d is not a valid mac id\n", id); 1669 return -EINVAL; 1670 } 1671 1672 if (eth->netdev[id]) { 1673 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 1674 return -EINVAL; 1675 } 1676 1677 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 1678 if (!eth->netdev[id]) { 1679 dev_err(eth->dev, "alloc_etherdev failed\n"); 1680 return -ENOMEM; 1681 } 1682 mac = netdev_priv(eth->netdev[id]); 1683 eth->mac[id] = mac; 1684 mac->id = id; 1685 mac->hw = eth; 1686 mac->of_node = np; 1687 1688 mac->hw_stats = devm_kzalloc(eth->dev, 1689 sizeof(*mac->hw_stats), 1690 GFP_KERNEL); 1691 if (!mac->hw_stats) { 1692 dev_err(eth->dev, "failed to allocate counter memory\n"); 1693 err = -ENOMEM; 1694 goto free_netdev; 1695 } 1696 spin_lock_init(&mac->hw_stats->stats_lock); 1697 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 1698 1699 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 1700 eth->netdev[id]->watchdog_timeo = HZ; 1701 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 1702 eth->netdev[id]->base_addr = (unsigned long)eth->base; 1703 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 1704 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 1705 eth->netdev[id]->features |= MTK_HW_FEATURES; 1706 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 1707 1708 err = register_netdev(eth->netdev[id]); 1709 if (err) { 1710 dev_err(eth->dev, "error bringing up device\n"); 1711 goto free_netdev; 1712 } 1713 eth->netdev[id]->irq = eth->irq; 1714 netif_info(eth, probe, eth->netdev[id], 1715 "mediatek frame engine at 0x%08lx, irq %d\n", 1716 eth->netdev[id]->base_addr, eth->netdev[id]->irq); 1717 1718 return 0; 1719 1720 free_netdev: 1721 free_netdev(eth->netdev[id]); 1722 return err; 1723 } 1724 1725 static int mtk_probe(struct platform_device *pdev) 1726 { 1727 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1728 struct device_node *mac_np; 1729 const struct of_device_id *match; 1730 struct mtk_soc_data *soc; 1731 struct mtk_eth *eth; 1732 int err; 1733 1734 match = of_match_device(of_mtk_match, &pdev->dev); 1735 soc = (struct mtk_soc_data *)match->data; 1736 1737 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 1738 if (!eth) 1739 return -ENOMEM; 1740 1741 eth->base = devm_ioremap_resource(&pdev->dev, res); 1742 if (IS_ERR(eth->base)) 1743 return PTR_ERR(eth->base); 1744 1745 spin_lock_init(ð->page_lock); 1746 1747 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1748 "mediatek,ethsys"); 1749 if (IS_ERR(eth->ethsys)) { 1750 dev_err(&pdev->dev, "no ethsys regmap found\n"); 1751 return PTR_ERR(eth->ethsys); 1752 } 1753 1754 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1755 "mediatek,pctl"); 1756 if (IS_ERR(eth->pctl)) { 1757 dev_err(&pdev->dev, "no pctl regmap found\n"); 1758 return PTR_ERR(eth->pctl); 1759 } 1760 1761 eth->rstc = devm_reset_control_get(&pdev->dev, "eth"); 1762 if (IS_ERR(eth->rstc)) { 1763 dev_err(&pdev->dev, "no eth reset found\n"); 1764 return PTR_ERR(eth->rstc); 1765 } 1766 1767 eth->irq = platform_get_irq(pdev, 0); 1768 if (eth->irq < 0) { 1769 dev_err(&pdev->dev, "no IRQ resource found\n"); 1770 return -ENXIO; 1771 } 1772 1773 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif"); 1774 eth->clk_esw = devm_clk_get(&pdev->dev, "esw"); 1775 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1"); 1776 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2"); 1777 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) || 1778 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif)) 1779 return -ENODEV; 1780 1781 clk_prepare_enable(eth->clk_ethif); 1782 clk_prepare_enable(eth->clk_esw); 1783 clk_prepare_enable(eth->clk_gp1); 1784 clk_prepare_enable(eth->clk_gp2); 1785 1786 eth->dev = &pdev->dev; 1787 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 1788 INIT_WORK(ð->pending_work, mtk_pending_work); 1789 1790 err = mtk_hw_init(eth); 1791 if (err) 1792 return err; 1793 1794 for_each_child_of_node(pdev->dev.of_node, mac_np) { 1795 if (!of_device_is_compatible(mac_np, 1796 "mediatek,eth-mac")) 1797 continue; 1798 1799 if (!of_device_is_available(mac_np)) 1800 continue; 1801 1802 err = mtk_add_mac(eth, mac_np); 1803 if (err) 1804 goto err_free_dev; 1805 } 1806 1807 /* we run 2 devices on the same DMA ring so we need a dummy device 1808 * for NAPI to work 1809 */ 1810 init_dummy_netdev(ð->dummy_dev); 1811 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_poll, 1812 MTK_NAPI_WEIGHT); 1813 1814 platform_set_drvdata(pdev, eth); 1815 1816 return 0; 1817 1818 err_free_dev: 1819 mtk_cleanup(eth); 1820 return err; 1821 } 1822 1823 static int mtk_remove(struct platform_device *pdev) 1824 { 1825 struct mtk_eth *eth = platform_get_drvdata(pdev); 1826 1827 clk_disable_unprepare(eth->clk_ethif); 1828 clk_disable_unprepare(eth->clk_esw); 1829 clk_disable_unprepare(eth->clk_gp1); 1830 clk_disable_unprepare(eth->clk_gp2); 1831 1832 netif_napi_del(ð->rx_napi); 1833 mtk_cleanup(eth); 1834 platform_set_drvdata(pdev, NULL); 1835 1836 return 0; 1837 } 1838 1839 const struct of_device_id of_mtk_match[] = { 1840 { .compatible = "mediatek,mt7623-eth" }, 1841 {}, 1842 }; 1843 1844 static struct platform_driver mtk_driver = { 1845 .probe = mtk_probe, 1846 .remove = mtk_remove, 1847 .driver = { 1848 .name = "mtk_soc_eth", 1849 .owner = THIS_MODULE, 1850 .of_match_table = of_mtk_match, 1851 }, 1852 }; 1853 1854 module_platform_driver(mtk_driver); 1855 1856 MODULE_LICENSE("GPL"); 1857 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 1858 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 1859