1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/clk.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/if_vlan.h> 19 #include <linux/reset.h> 20 #include <linux/tcp.h> 21 #include <linux/interrupt.h> 22 #include <linux/pinctrl/devinfo.h> 23 #include <linux/phylink.h> 24 #include <linux/pcs/pcs-mtk-lynxi.h> 25 #include <linux/jhash.h> 26 #include <linux/bitfield.h> 27 #include <net/dsa.h> 28 #include <net/dst_metadata.h> 29 #include <net/page_pool/helpers.h> 30 31 #include "mtk_eth_soc.h" 32 #include "mtk_wed.h" 33 34 static int mtk_msg_level = -1; 35 module_param_named(msg_level, mtk_msg_level, int, 0); 36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 37 38 #define MTK_ETHTOOL_STAT(x) { #x, \ 39 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 40 41 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 42 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 43 sizeof(u64) } 44 45 static const struct mtk_reg_map mtk_reg_map = { 46 .tx_irq_mask = 0x1a1c, 47 .tx_irq_status = 0x1a18, 48 .pdma = { 49 .rx_ptr = 0x0900, 50 .rx_cnt_cfg = 0x0904, 51 .pcrx_ptr = 0x0908, 52 .glo_cfg = 0x0a04, 53 .rst_idx = 0x0a08, 54 .delay_irq = 0x0a0c, 55 .irq_status = 0x0a20, 56 .irq_mask = 0x0a28, 57 .adma_rx_dbg0 = 0x0a38, 58 .int_grp = 0x0a50, 59 }, 60 .qdma = { 61 .qtx_cfg = 0x1800, 62 .qtx_sch = 0x1804, 63 .rx_ptr = 0x1900, 64 .rx_cnt_cfg = 0x1904, 65 .qcrx_ptr = 0x1908, 66 .glo_cfg = 0x1a04, 67 .rst_idx = 0x1a08, 68 .delay_irq = 0x1a0c, 69 .fc_th = 0x1a10, 70 .tx_sch_rate = 0x1a14, 71 .int_grp = 0x1a20, 72 .hred = 0x1a44, 73 .ctx_ptr = 0x1b00, 74 .dtx_ptr = 0x1b04, 75 .crx_ptr = 0x1b10, 76 .drx_ptr = 0x1b14, 77 .fq_head = 0x1b20, 78 .fq_tail = 0x1b24, 79 .fq_count = 0x1b28, 80 .fq_blen = 0x1b2c, 81 }, 82 .gdm1_cnt = 0x2400, 83 .gdma_to_ppe = 0x4444, 84 .ppe_base = 0x0c00, 85 .wdma_base = { 86 [0] = 0x2800, 87 [1] = 0x2c00, 88 }, 89 .pse_iq_sta = 0x0110, 90 .pse_oq_sta = 0x0118, 91 }; 92 93 static const struct mtk_reg_map mt7628_reg_map = { 94 .tx_irq_mask = 0x0a28, 95 .tx_irq_status = 0x0a20, 96 .pdma = { 97 .rx_ptr = 0x0900, 98 .rx_cnt_cfg = 0x0904, 99 .pcrx_ptr = 0x0908, 100 .glo_cfg = 0x0a04, 101 .rst_idx = 0x0a08, 102 .delay_irq = 0x0a0c, 103 .irq_status = 0x0a20, 104 .irq_mask = 0x0a28, 105 .int_grp = 0x0a50, 106 }, 107 }; 108 109 static const struct mtk_reg_map mt7986_reg_map = { 110 .tx_irq_mask = 0x461c, 111 .tx_irq_status = 0x4618, 112 .pdma = { 113 .rx_ptr = 0x6100, 114 .rx_cnt_cfg = 0x6104, 115 .pcrx_ptr = 0x6108, 116 .glo_cfg = 0x6204, 117 .rst_idx = 0x6208, 118 .delay_irq = 0x620c, 119 .irq_status = 0x6220, 120 .irq_mask = 0x6228, 121 .adma_rx_dbg0 = 0x6238, 122 .int_grp = 0x6250, 123 }, 124 .qdma = { 125 .qtx_cfg = 0x4400, 126 .qtx_sch = 0x4404, 127 .rx_ptr = 0x4500, 128 .rx_cnt_cfg = 0x4504, 129 .qcrx_ptr = 0x4508, 130 .glo_cfg = 0x4604, 131 .rst_idx = 0x4608, 132 .delay_irq = 0x460c, 133 .fc_th = 0x4610, 134 .int_grp = 0x4620, 135 .hred = 0x4644, 136 .ctx_ptr = 0x4700, 137 .dtx_ptr = 0x4704, 138 .crx_ptr = 0x4710, 139 .drx_ptr = 0x4714, 140 .fq_head = 0x4720, 141 .fq_tail = 0x4724, 142 .fq_count = 0x4728, 143 .fq_blen = 0x472c, 144 .tx_sch_rate = 0x4798, 145 }, 146 .gdm1_cnt = 0x1c00, 147 .gdma_to_ppe = 0x3333, 148 .ppe_base = 0x2000, 149 .wdma_base = { 150 [0] = 0x4800, 151 [1] = 0x4c00, 152 }, 153 .pse_iq_sta = 0x0180, 154 .pse_oq_sta = 0x01a0, 155 }; 156 157 static const struct mtk_reg_map mt7988_reg_map = { 158 .tx_irq_mask = 0x461c, 159 .tx_irq_status = 0x4618, 160 .pdma = { 161 .rx_ptr = 0x6900, 162 .rx_cnt_cfg = 0x6904, 163 .pcrx_ptr = 0x6908, 164 .glo_cfg = 0x6a04, 165 .rst_idx = 0x6a08, 166 .delay_irq = 0x6a0c, 167 .irq_status = 0x6a20, 168 .irq_mask = 0x6a28, 169 .adma_rx_dbg0 = 0x6a38, 170 .int_grp = 0x6a50, 171 }, 172 .qdma = { 173 .qtx_cfg = 0x4400, 174 .qtx_sch = 0x4404, 175 .rx_ptr = 0x4500, 176 .rx_cnt_cfg = 0x4504, 177 .qcrx_ptr = 0x4508, 178 .glo_cfg = 0x4604, 179 .rst_idx = 0x4608, 180 .delay_irq = 0x460c, 181 .fc_th = 0x4610, 182 .int_grp = 0x4620, 183 .hred = 0x4644, 184 .ctx_ptr = 0x4700, 185 .dtx_ptr = 0x4704, 186 .crx_ptr = 0x4710, 187 .drx_ptr = 0x4714, 188 .fq_head = 0x4720, 189 .fq_tail = 0x4724, 190 .fq_count = 0x4728, 191 .fq_blen = 0x472c, 192 .tx_sch_rate = 0x4798, 193 }, 194 .gdm1_cnt = 0x1c00, 195 .gdma_to_ppe = 0x3333, 196 .ppe_base = 0x2000, 197 .wdma_base = { 198 [0] = 0x4800, 199 [1] = 0x4c00, 200 }, 201 .pse_iq_sta = 0x0180, 202 .pse_oq_sta = 0x01a0, 203 }; 204 205 /* strings used by ethtool */ 206 static const struct mtk_ethtool_stats { 207 char str[ETH_GSTRING_LEN]; 208 u32 offset; 209 } mtk_ethtool_stats[] = { 210 MTK_ETHTOOL_STAT(tx_bytes), 211 MTK_ETHTOOL_STAT(tx_packets), 212 MTK_ETHTOOL_STAT(tx_skip), 213 MTK_ETHTOOL_STAT(tx_collisions), 214 MTK_ETHTOOL_STAT(rx_bytes), 215 MTK_ETHTOOL_STAT(rx_packets), 216 MTK_ETHTOOL_STAT(rx_overflow), 217 MTK_ETHTOOL_STAT(rx_fcs_errors), 218 MTK_ETHTOOL_STAT(rx_short_errors), 219 MTK_ETHTOOL_STAT(rx_long_errors), 220 MTK_ETHTOOL_STAT(rx_checksum_errors), 221 MTK_ETHTOOL_STAT(rx_flow_control_packets), 222 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 223 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 224 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 225 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 226 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 227 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 228 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 229 }; 230 231 static const char * const mtk_clks_source_name[] = { 232 "ethif", 233 "sgmiitop", 234 "esw", 235 "gp0", 236 "gp1", 237 "gp2", 238 "gp3", 239 "xgp1", 240 "xgp2", 241 "xgp3", 242 "crypto", 243 "fe", 244 "trgpll", 245 "sgmii_tx250m", 246 "sgmii_rx250m", 247 "sgmii_cdr_ref", 248 "sgmii_cdr_fb", 249 "sgmii2_tx250m", 250 "sgmii2_rx250m", 251 "sgmii2_cdr_ref", 252 "sgmii2_cdr_fb", 253 "sgmii_ck", 254 "eth2pll", 255 "wocpu0", 256 "wocpu1", 257 "netsys0", 258 "netsys1", 259 "ethwarp_wocpu2", 260 "ethwarp_wocpu1", 261 "ethwarp_wocpu0", 262 "top_usxgmii0_sel", 263 "top_usxgmii1_sel", 264 "top_sgm0_sel", 265 "top_sgm1_sel", 266 "top_xfi_phy0_xtal_sel", 267 "top_xfi_phy1_xtal_sel", 268 "top_eth_gmii_sel", 269 "top_eth_refck_50m_sel", 270 "top_eth_sys_200m_sel", 271 "top_eth_sys_sel", 272 "top_eth_xgmii_sel", 273 "top_eth_mii_sel", 274 "top_netsys_sel", 275 "top_netsys_500m_sel", 276 "top_netsys_pao_2x_sel", 277 "top_netsys_sync_250m_sel", 278 "top_netsys_ppefb_250m_sel", 279 "top_netsys_warp_sel", 280 }; 281 282 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 283 { 284 __raw_writel(val, eth->base + reg); 285 } 286 287 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 288 { 289 return __raw_readl(eth->base + reg); 290 } 291 292 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) 293 { 294 u32 val; 295 296 val = mtk_r32(eth, reg); 297 val &= ~mask; 298 val |= set; 299 mtk_w32(eth, val, reg); 300 return reg; 301 } 302 303 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 304 { 305 unsigned long t_start = jiffies; 306 307 while (1) { 308 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 309 return 0; 310 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 311 break; 312 cond_resched(); 313 } 314 315 dev_err(eth->dev, "mdio: MDIO timeout\n"); 316 return -ETIMEDOUT; 317 } 318 319 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 320 u32 write_data) 321 { 322 int ret; 323 324 ret = mtk_mdio_busy_wait(eth); 325 if (ret < 0) 326 return ret; 327 328 mtk_w32(eth, PHY_IAC_ACCESS | 329 PHY_IAC_START_C22 | 330 PHY_IAC_CMD_WRITE | 331 PHY_IAC_REG(phy_reg) | 332 PHY_IAC_ADDR(phy_addr) | 333 PHY_IAC_DATA(write_data), 334 MTK_PHY_IAC); 335 336 ret = mtk_mdio_busy_wait(eth); 337 if (ret < 0) 338 return ret; 339 340 return 0; 341 } 342 343 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 344 u32 devad, u32 phy_reg, u32 write_data) 345 { 346 int ret; 347 348 ret = mtk_mdio_busy_wait(eth); 349 if (ret < 0) 350 return ret; 351 352 mtk_w32(eth, PHY_IAC_ACCESS | 353 PHY_IAC_START_C45 | 354 PHY_IAC_CMD_C45_ADDR | 355 PHY_IAC_REG(devad) | 356 PHY_IAC_ADDR(phy_addr) | 357 PHY_IAC_DATA(phy_reg), 358 MTK_PHY_IAC); 359 360 ret = mtk_mdio_busy_wait(eth); 361 if (ret < 0) 362 return ret; 363 364 mtk_w32(eth, PHY_IAC_ACCESS | 365 PHY_IAC_START_C45 | 366 PHY_IAC_CMD_WRITE | 367 PHY_IAC_REG(devad) | 368 PHY_IAC_ADDR(phy_addr) | 369 PHY_IAC_DATA(write_data), 370 MTK_PHY_IAC); 371 372 ret = mtk_mdio_busy_wait(eth); 373 if (ret < 0) 374 return ret; 375 376 return 0; 377 } 378 379 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 380 { 381 int ret; 382 383 ret = mtk_mdio_busy_wait(eth); 384 if (ret < 0) 385 return ret; 386 387 mtk_w32(eth, PHY_IAC_ACCESS | 388 PHY_IAC_START_C22 | 389 PHY_IAC_CMD_C22_READ | 390 PHY_IAC_REG(phy_reg) | 391 PHY_IAC_ADDR(phy_addr), 392 MTK_PHY_IAC); 393 394 ret = mtk_mdio_busy_wait(eth); 395 if (ret < 0) 396 return ret; 397 398 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 399 } 400 401 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 402 u32 devad, u32 phy_reg) 403 { 404 int ret; 405 406 ret = mtk_mdio_busy_wait(eth); 407 if (ret < 0) 408 return ret; 409 410 mtk_w32(eth, PHY_IAC_ACCESS | 411 PHY_IAC_START_C45 | 412 PHY_IAC_CMD_C45_ADDR | 413 PHY_IAC_REG(devad) | 414 PHY_IAC_ADDR(phy_addr) | 415 PHY_IAC_DATA(phy_reg), 416 MTK_PHY_IAC); 417 418 ret = mtk_mdio_busy_wait(eth); 419 if (ret < 0) 420 return ret; 421 422 mtk_w32(eth, PHY_IAC_ACCESS | 423 PHY_IAC_START_C45 | 424 PHY_IAC_CMD_C45_READ | 425 PHY_IAC_REG(devad) | 426 PHY_IAC_ADDR(phy_addr), 427 MTK_PHY_IAC); 428 429 ret = mtk_mdio_busy_wait(eth); 430 if (ret < 0) 431 return ret; 432 433 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 434 } 435 436 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 437 int phy_reg, u16 val) 438 { 439 struct mtk_eth *eth = bus->priv; 440 441 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 442 } 443 444 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 445 int devad, int phy_reg, u16 val) 446 { 447 struct mtk_eth *eth = bus->priv; 448 449 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 450 } 451 452 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 453 { 454 struct mtk_eth *eth = bus->priv; 455 456 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 457 } 458 459 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 460 int phy_reg) 461 { 462 struct mtk_eth *eth = bus->priv; 463 464 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 465 } 466 467 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 468 phy_interface_t interface) 469 { 470 u32 val; 471 472 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 473 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 474 475 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 476 ETHSYS_TRGMII_MT7621_MASK, val); 477 478 return 0; 479 } 480 481 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 482 phy_interface_t interface) 483 { 484 int ret; 485 486 if (interface == PHY_INTERFACE_MODE_TRGMII) { 487 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 488 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); 489 if (ret) 490 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 491 return; 492 } 493 494 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); 495 } 496 497 static void mtk_setup_bridge_switch(struct mtk_eth *eth) 498 { 499 /* Force Port1 XGMAC Link Up */ 500 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), 501 MTK_XGMAC_STS(MTK_GMAC1_ID)); 502 503 /* Adjust GSW bridge IPG to 11 */ 504 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, 505 (GSW_IPG_11 << GSWTX_IPG_SHIFT) | 506 (GSW_IPG_11 << GSWRX_IPG_SHIFT), 507 MTK_GSW_CFG); 508 } 509 510 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 511 phy_interface_t interface) 512 { 513 struct mtk_mac *mac = container_of(config, struct mtk_mac, 514 phylink_config); 515 struct mtk_eth *eth = mac->hw; 516 unsigned int sid; 517 518 if (interface == PHY_INTERFACE_MODE_SGMII || 519 phy_interface_mode_is_8023z(interface)) { 520 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 521 0 : mac->id; 522 523 return eth->sgmii_pcs[sid]; 524 } 525 526 return NULL; 527 } 528 529 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 530 const struct phylink_link_state *state) 531 { 532 struct mtk_mac *mac = container_of(config, struct mtk_mac, 533 phylink_config); 534 struct mtk_eth *eth = mac->hw; 535 int val, ge_mode, err = 0; 536 u32 i; 537 538 /* MT76x8 has no hardware settings between for the MAC */ 539 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 540 mac->interface != state->interface) { 541 /* Setup soc pin functions */ 542 switch (state->interface) { 543 case PHY_INTERFACE_MODE_TRGMII: 544 case PHY_INTERFACE_MODE_RGMII_TXID: 545 case PHY_INTERFACE_MODE_RGMII_RXID: 546 case PHY_INTERFACE_MODE_RGMII_ID: 547 case PHY_INTERFACE_MODE_RGMII: 548 case PHY_INTERFACE_MODE_MII: 549 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 550 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 551 if (err) 552 goto init_err; 553 } 554 break; 555 case PHY_INTERFACE_MODE_1000BASEX: 556 case PHY_INTERFACE_MODE_2500BASEX: 557 case PHY_INTERFACE_MODE_SGMII: 558 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 559 if (err) 560 goto init_err; 561 break; 562 case PHY_INTERFACE_MODE_GMII: 563 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 564 err = mtk_gmac_gephy_path_setup(eth, mac->id); 565 if (err) 566 goto init_err; 567 } 568 break; 569 case PHY_INTERFACE_MODE_INTERNAL: 570 break; 571 default: 572 goto err_phy; 573 } 574 575 /* Setup clock for 1st gmac */ 576 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 577 !phy_interface_mode_is_8023z(state->interface) && 578 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 579 if (MTK_HAS_CAPS(mac->hw->soc->caps, 580 MTK_TRGMII_MT7621_CLK)) { 581 if (mt7621_gmac0_rgmii_adjust(mac->hw, 582 state->interface)) 583 goto err_phy; 584 } else { 585 mtk_gmac0_rgmii_adjust(mac->hw, 586 state->interface); 587 588 /* mt7623_pad_clk_setup */ 589 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 590 mtk_w32(mac->hw, 591 TD_DM_DRVP(8) | TD_DM_DRVN(8), 592 TRGMII_TD_ODT(i)); 593 594 /* Assert/release MT7623 RXC reset */ 595 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 596 TRGMII_RCK_CTRL); 597 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 598 } 599 } 600 601 switch (state->interface) { 602 case PHY_INTERFACE_MODE_MII: 603 case PHY_INTERFACE_MODE_GMII: 604 ge_mode = 1; 605 break; 606 default: 607 ge_mode = 0; 608 break; 609 } 610 611 /* put the gmac into the right mode */ 612 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 613 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 614 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 615 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 616 617 mac->interface = state->interface; 618 } 619 620 /* SGMII */ 621 if (state->interface == PHY_INTERFACE_MODE_SGMII || 622 phy_interface_mode_is_8023z(state->interface)) { 623 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 624 * being setup done. 625 */ 626 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 627 628 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 629 SYSCFG0_SGMII_MASK, 630 ~(u32)SYSCFG0_SGMII_MASK); 631 632 /* Save the syscfg0 value for mac_finish */ 633 mac->syscfg0 = val; 634 } else if (phylink_autoneg_inband(mode)) { 635 dev_err(eth->dev, 636 "In-band mode not supported in non SGMII mode!\n"); 637 return; 638 } 639 640 /* Setup gmac */ 641 if (mtk_is_netsys_v3_or_greater(eth) && 642 mac->interface == PHY_INTERFACE_MODE_INTERNAL) { 643 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); 644 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); 645 646 mtk_setup_bridge_switch(eth); 647 } 648 649 return; 650 651 err_phy: 652 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 653 mac->id, phy_modes(state->interface)); 654 return; 655 656 init_err: 657 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 658 mac->id, phy_modes(state->interface), err); 659 } 660 661 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 662 phy_interface_t interface) 663 { 664 struct mtk_mac *mac = container_of(config, struct mtk_mac, 665 phylink_config); 666 struct mtk_eth *eth = mac->hw; 667 u32 mcr_cur, mcr_new; 668 669 /* Enable SGMII */ 670 if (interface == PHY_INTERFACE_MODE_SGMII || 671 phy_interface_mode_is_8023z(interface)) 672 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 673 SYSCFG0_SGMII_MASK, mac->syscfg0); 674 675 /* Setup gmac */ 676 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 677 mcr_new = mcr_cur; 678 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 679 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK | 680 MAC_MCR_RX_FIFO_CLR_DIS; 681 682 /* Only update control register when needed! */ 683 if (mcr_new != mcr_cur) 684 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 685 686 return 0; 687 } 688 689 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 690 phy_interface_t interface) 691 { 692 struct mtk_mac *mac = container_of(config, struct mtk_mac, 693 phylink_config); 694 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 695 696 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 697 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 698 } 699 700 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 701 int speed) 702 { 703 const struct mtk_soc_data *soc = eth->soc; 704 u32 ofs, val; 705 706 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 707 return; 708 709 val = MTK_QTX_SCH_MIN_RATE_EN | 710 /* minimum: 10 Mbps */ 711 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 712 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 713 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 714 if (mtk_is_netsys_v1(eth)) 715 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 716 717 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 718 switch (speed) { 719 case SPEED_10: 720 val |= MTK_QTX_SCH_MAX_RATE_EN | 721 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 722 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 723 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 724 break; 725 case SPEED_100: 726 val |= MTK_QTX_SCH_MAX_RATE_EN | 727 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 728 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 729 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 730 break; 731 case SPEED_1000: 732 val |= MTK_QTX_SCH_MAX_RATE_EN | 733 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 734 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 735 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 736 break; 737 default: 738 break; 739 } 740 } else { 741 switch (speed) { 742 case SPEED_10: 743 val |= MTK_QTX_SCH_MAX_RATE_EN | 744 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 745 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 746 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 747 break; 748 case SPEED_100: 749 val |= MTK_QTX_SCH_MAX_RATE_EN | 750 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 751 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 752 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 753 break; 754 case SPEED_1000: 755 val |= MTK_QTX_SCH_MAX_RATE_EN | 756 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 757 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 758 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 759 break; 760 default: 761 break; 762 } 763 } 764 765 ofs = MTK_QTX_OFFSET * idx; 766 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 767 } 768 769 static void mtk_mac_link_up(struct phylink_config *config, 770 struct phy_device *phy, 771 unsigned int mode, phy_interface_t interface, 772 int speed, int duplex, bool tx_pause, bool rx_pause) 773 { 774 struct mtk_mac *mac = container_of(config, struct mtk_mac, 775 phylink_config); 776 u32 mcr; 777 778 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 779 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 780 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 781 MAC_MCR_FORCE_RX_FC); 782 783 /* Configure speed */ 784 mac->speed = speed; 785 switch (speed) { 786 case SPEED_2500: 787 case SPEED_1000: 788 mcr |= MAC_MCR_SPEED_1000; 789 break; 790 case SPEED_100: 791 mcr |= MAC_MCR_SPEED_100; 792 break; 793 } 794 795 /* Configure duplex */ 796 if (duplex == DUPLEX_FULL) 797 mcr |= MAC_MCR_FORCE_DPX; 798 799 /* Configure pause modes - phylink will avoid these for half duplex */ 800 if (tx_pause) 801 mcr |= MAC_MCR_FORCE_TX_FC; 802 if (rx_pause) 803 mcr |= MAC_MCR_FORCE_RX_FC; 804 805 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 806 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 807 } 808 809 static const struct phylink_mac_ops mtk_phylink_ops = { 810 .mac_select_pcs = mtk_mac_select_pcs, 811 .mac_config = mtk_mac_config, 812 .mac_finish = mtk_mac_finish, 813 .mac_link_down = mtk_mac_link_down, 814 .mac_link_up = mtk_mac_link_up, 815 }; 816 817 static int mtk_mdio_init(struct mtk_eth *eth) 818 { 819 unsigned int max_clk = 2500000, divider; 820 struct device_node *mii_np; 821 int ret; 822 u32 val; 823 824 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 825 if (!mii_np) { 826 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 827 return -ENODEV; 828 } 829 830 if (!of_device_is_available(mii_np)) { 831 ret = -ENODEV; 832 goto err_put_node; 833 } 834 835 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 836 if (!eth->mii_bus) { 837 ret = -ENOMEM; 838 goto err_put_node; 839 } 840 841 eth->mii_bus->name = "mdio"; 842 eth->mii_bus->read = mtk_mdio_read_c22; 843 eth->mii_bus->write = mtk_mdio_write_c22; 844 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 845 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 846 eth->mii_bus->priv = eth; 847 eth->mii_bus->parent = eth->dev; 848 849 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 850 851 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { 852 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { 853 dev_err(eth->dev, "MDIO clock frequency out of range"); 854 ret = -EINVAL; 855 goto err_put_node; 856 } 857 max_clk = val; 858 } 859 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 860 861 /* Configure MDC Turbo Mode */ 862 if (mtk_is_netsys_v3_or_greater(eth)) 863 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); 864 865 /* Configure MDC Divider */ 866 val = FIELD_PREP(PPSC_MDC_CFG, divider); 867 if (!mtk_is_netsys_v3_or_greater(eth)) 868 val |= PPSC_MDC_TURBO; 869 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); 870 871 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); 872 873 ret = of_mdiobus_register(eth->mii_bus, mii_np); 874 875 err_put_node: 876 of_node_put(mii_np); 877 return ret; 878 } 879 880 static void mtk_mdio_cleanup(struct mtk_eth *eth) 881 { 882 if (!eth->mii_bus) 883 return; 884 885 mdiobus_unregister(eth->mii_bus); 886 } 887 888 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 889 { 890 unsigned long flags; 891 u32 val; 892 893 spin_lock_irqsave(ð->tx_irq_lock, flags); 894 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 895 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 896 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 897 } 898 899 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 900 { 901 unsigned long flags; 902 u32 val; 903 904 spin_lock_irqsave(ð->tx_irq_lock, flags); 905 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 906 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 907 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 908 } 909 910 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 911 { 912 unsigned long flags; 913 u32 val; 914 915 spin_lock_irqsave(ð->rx_irq_lock, flags); 916 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 917 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 918 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 919 } 920 921 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 922 { 923 unsigned long flags; 924 u32 val; 925 926 spin_lock_irqsave(ð->rx_irq_lock, flags); 927 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 928 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 929 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 930 } 931 932 static int mtk_set_mac_address(struct net_device *dev, void *p) 933 { 934 int ret = eth_mac_addr(dev, p); 935 struct mtk_mac *mac = netdev_priv(dev); 936 struct mtk_eth *eth = mac->hw; 937 const char *macaddr = dev->dev_addr; 938 939 if (ret) 940 return ret; 941 942 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 943 return -EBUSY; 944 945 spin_lock_bh(&mac->hw->page_lock); 946 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 947 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 948 MT7628_SDM_MAC_ADRH); 949 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 950 (macaddr[4] << 8) | macaddr[5], 951 MT7628_SDM_MAC_ADRL); 952 } else { 953 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 954 MTK_GDMA_MAC_ADRH(mac->id)); 955 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 956 (macaddr[4] << 8) | macaddr[5], 957 MTK_GDMA_MAC_ADRL(mac->id)); 958 } 959 spin_unlock_bh(&mac->hw->page_lock); 960 961 return 0; 962 } 963 964 void mtk_stats_update_mac(struct mtk_mac *mac) 965 { 966 struct mtk_hw_stats *hw_stats = mac->hw_stats; 967 struct mtk_eth *eth = mac->hw; 968 969 u64_stats_update_begin(&hw_stats->syncp); 970 971 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 972 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 973 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 974 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 975 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 976 hw_stats->rx_checksum_errors += 977 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 978 } else { 979 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 980 unsigned int offs = hw_stats->reg_offset; 981 u64 stats; 982 983 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 984 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 985 if (stats) 986 hw_stats->rx_bytes += (stats << 32); 987 hw_stats->rx_packets += 988 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 989 hw_stats->rx_overflow += 990 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 991 hw_stats->rx_fcs_errors += 992 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 993 hw_stats->rx_short_errors += 994 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 995 hw_stats->rx_long_errors += 996 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 997 hw_stats->rx_checksum_errors += 998 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 999 hw_stats->rx_flow_control_packets += 1000 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 1001 1002 if (mtk_is_netsys_v3_or_greater(eth)) { 1003 hw_stats->tx_skip += 1004 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); 1005 hw_stats->tx_collisions += 1006 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); 1007 hw_stats->tx_bytes += 1008 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); 1009 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); 1010 if (stats) 1011 hw_stats->tx_bytes += (stats << 32); 1012 hw_stats->tx_packets += 1013 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); 1014 } else { 1015 hw_stats->tx_skip += 1016 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 1017 hw_stats->tx_collisions += 1018 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 1019 hw_stats->tx_bytes += 1020 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 1021 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 1022 if (stats) 1023 hw_stats->tx_bytes += (stats << 32); 1024 hw_stats->tx_packets += 1025 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 1026 } 1027 } 1028 1029 u64_stats_update_end(&hw_stats->syncp); 1030 } 1031 1032 static void mtk_stats_update(struct mtk_eth *eth) 1033 { 1034 int i; 1035 1036 for (i = 0; i < MTK_MAX_DEVS; i++) { 1037 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 1038 continue; 1039 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 1040 mtk_stats_update_mac(eth->mac[i]); 1041 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 1042 } 1043 } 1044 } 1045 1046 static void mtk_get_stats64(struct net_device *dev, 1047 struct rtnl_link_stats64 *storage) 1048 { 1049 struct mtk_mac *mac = netdev_priv(dev); 1050 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1051 unsigned int start; 1052 1053 if (netif_running(dev) && netif_device_present(dev)) { 1054 if (spin_trylock_bh(&hw_stats->stats_lock)) { 1055 mtk_stats_update_mac(mac); 1056 spin_unlock_bh(&hw_stats->stats_lock); 1057 } 1058 } 1059 1060 do { 1061 start = u64_stats_fetch_begin(&hw_stats->syncp); 1062 storage->rx_packets = hw_stats->rx_packets; 1063 storage->tx_packets = hw_stats->tx_packets; 1064 storage->rx_bytes = hw_stats->rx_bytes; 1065 storage->tx_bytes = hw_stats->tx_bytes; 1066 storage->collisions = hw_stats->tx_collisions; 1067 storage->rx_length_errors = hw_stats->rx_short_errors + 1068 hw_stats->rx_long_errors; 1069 storage->rx_over_errors = hw_stats->rx_overflow; 1070 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1071 storage->rx_errors = hw_stats->rx_checksum_errors; 1072 storage->tx_aborted_errors = hw_stats->tx_skip; 1073 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1074 1075 storage->tx_errors = dev->stats.tx_errors; 1076 storage->rx_dropped = dev->stats.rx_dropped; 1077 storage->tx_dropped = dev->stats.tx_dropped; 1078 } 1079 1080 static inline int mtk_max_frag_size(int mtu) 1081 { 1082 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1083 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1084 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1085 1086 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1087 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1088 } 1089 1090 static inline int mtk_max_buf_size(int frag_size) 1091 { 1092 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1093 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1094 1095 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1096 1097 return buf_size; 1098 } 1099 1100 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1101 struct mtk_rx_dma_v2 *dma_rxd) 1102 { 1103 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1104 if (!(rxd->rxd2 & RX_DMA_DONE)) 1105 return false; 1106 1107 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1108 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1109 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1110 if (mtk_is_netsys_v2_or_greater(eth)) { 1111 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1112 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1113 } 1114 1115 return true; 1116 } 1117 1118 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1119 { 1120 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1121 unsigned long data; 1122 1123 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1124 get_order(size)); 1125 1126 return (void *)data; 1127 } 1128 1129 /* the qdma core needs scratch memory to be setup */ 1130 static int mtk_init_fq_dma(struct mtk_eth *eth) 1131 { 1132 const struct mtk_soc_data *soc = eth->soc; 1133 dma_addr_t phy_ring_tail; 1134 int cnt = MTK_QDMA_RING_SIZE; 1135 dma_addr_t dma_addr; 1136 int i; 1137 1138 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) 1139 eth->scratch_ring = eth->sram_base; 1140 else 1141 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1142 cnt * soc->txrx.txd_size, 1143 ð->phy_scratch_ring, 1144 GFP_KERNEL); 1145 if (unlikely(!eth->scratch_ring)) 1146 return -ENOMEM; 1147 1148 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1149 if (unlikely(!eth->scratch_head)) 1150 return -ENOMEM; 1151 1152 dma_addr = dma_map_single(eth->dma_dev, 1153 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 1154 DMA_FROM_DEVICE); 1155 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1156 return -ENOMEM; 1157 1158 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 1159 1160 for (i = 0; i < cnt; i++) { 1161 struct mtk_tx_dma_v2 *txd; 1162 1163 txd = eth->scratch_ring + i * soc->txrx.txd_size; 1164 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1165 if (i < cnt - 1) 1166 txd->txd2 = eth->phy_scratch_ring + 1167 (i + 1) * soc->txrx.txd_size; 1168 1169 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1170 txd->txd4 = 0; 1171 if (mtk_is_netsys_v2_or_greater(eth)) { 1172 txd->txd5 = 0; 1173 txd->txd6 = 0; 1174 txd->txd7 = 0; 1175 txd->txd8 = 0; 1176 } 1177 } 1178 1179 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1180 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1181 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1182 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1183 1184 return 0; 1185 } 1186 1187 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1188 { 1189 return ring->dma + (desc - ring->phys); 1190 } 1191 1192 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1193 void *txd, u32 txd_size) 1194 { 1195 int idx = (txd - ring->dma) / txd_size; 1196 1197 return &ring->buf[idx]; 1198 } 1199 1200 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1201 struct mtk_tx_dma *dma) 1202 { 1203 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1204 } 1205 1206 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1207 { 1208 return (dma - ring->dma) / txd_size; 1209 } 1210 1211 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1212 struct xdp_frame_bulk *bq, bool napi) 1213 { 1214 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1215 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1216 dma_unmap_single(eth->dma_dev, 1217 dma_unmap_addr(tx_buf, dma_addr0), 1218 dma_unmap_len(tx_buf, dma_len0), 1219 DMA_TO_DEVICE); 1220 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1221 dma_unmap_page(eth->dma_dev, 1222 dma_unmap_addr(tx_buf, dma_addr0), 1223 dma_unmap_len(tx_buf, dma_len0), 1224 DMA_TO_DEVICE); 1225 } 1226 } else { 1227 if (dma_unmap_len(tx_buf, dma_len0)) { 1228 dma_unmap_page(eth->dma_dev, 1229 dma_unmap_addr(tx_buf, dma_addr0), 1230 dma_unmap_len(tx_buf, dma_len0), 1231 DMA_TO_DEVICE); 1232 } 1233 1234 if (dma_unmap_len(tx_buf, dma_len1)) { 1235 dma_unmap_page(eth->dma_dev, 1236 dma_unmap_addr(tx_buf, dma_addr1), 1237 dma_unmap_len(tx_buf, dma_len1), 1238 DMA_TO_DEVICE); 1239 } 1240 } 1241 1242 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1243 if (tx_buf->type == MTK_TYPE_SKB) { 1244 struct sk_buff *skb = tx_buf->data; 1245 1246 if (napi) 1247 napi_consume_skb(skb, napi); 1248 else 1249 dev_kfree_skb_any(skb); 1250 } else { 1251 struct xdp_frame *xdpf = tx_buf->data; 1252 1253 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1254 xdp_return_frame_rx_napi(xdpf); 1255 else if (bq) 1256 xdp_return_frame_bulk(xdpf, bq); 1257 else 1258 xdp_return_frame(xdpf); 1259 } 1260 } 1261 tx_buf->flags = 0; 1262 tx_buf->data = NULL; 1263 } 1264 1265 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1266 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1267 size_t size, int idx) 1268 { 1269 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1270 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1271 dma_unmap_len_set(tx_buf, dma_len0, size); 1272 } else { 1273 if (idx & 1) { 1274 txd->txd3 = mapped_addr; 1275 txd->txd2 |= TX_DMA_PLEN1(size); 1276 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1277 dma_unmap_len_set(tx_buf, dma_len1, size); 1278 } else { 1279 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1280 txd->txd1 = mapped_addr; 1281 txd->txd2 = TX_DMA_PLEN0(size); 1282 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1283 dma_unmap_len_set(tx_buf, dma_len0, size); 1284 } 1285 } 1286 } 1287 1288 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1289 struct mtk_tx_dma_desc_info *info) 1290 { 1291 struct mtk_mac *mac = netdev_priv(dev); 1292 struct mtk_eth *eth = mac->hw; 1293 struct mtk_tx_dma *desc = txd; 1294 u32 data; 1295 1296 WRITE_ONCE(desc->txd1, info->addr); 1297 1298 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1299 FIELD_PREP(TX_DMA_PQID, info->qid); 1300 if (info->last) 1301 data |= TX_DMA_LS0; 1302 WRITE_ONCE(desc->txd3, data); 1303 1304 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1305 if (info->first) { 1306 if (info->gso) 1307 data |= TX_DMA_TSO; 1308 /* tx checksum offload */ 1309 if (info->csum) 1310 data |= TX_DMA_CHKSUM; 1311 /* vlan header offload */ 1312 if (info->vlan) 1313 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1314 } 1315 WRITE_ONCE(desc->txd4, data); 1316 } 1317 1318 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1319 struct mtk_tx_dma_desc_info *info) 1320 { 1321 struct mtk_mac *mac = netdev_priv(dev); 1322 struct mtk_tx_dma_v2 *desc = txd; 1323 struct mtk_eth *eth = mac->hw; 1324 u32 data; 1325 1326 WRITE_ONCE(desc->txd1, info->addr); 1327 1328 data = TX_DMA_PLEN0(info->size); 1329 if (info->last) 1330 data |= TX_DMA_LS0; 1331 1332 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 1333 data |= TX_DMA_PREP_ADDR64(info->addr); 1334 1335 WRITE_ONCE(desc->txd3, data); 1336 1337 /* set forward port */ 1338 switch (mac->id) { 1339 case MTK_GMAC1_ID: 1340 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; 1341 break; 1342 case MTK_GMAC2_ID: 1343 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; 1344 break; 1345 case MTK_GMAC3_ID: 1346 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; 1347 break; 1348 } 1349 1350 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1351 WRITE_ONCE(desc->txd4, data); 1352 1353 data = 0; 1354 if (info->first) { 1355 if (info->gso) 1356 data |= TX_DMA_TSO_V2; 1357 /* tx checksum offload */ 1358 if (info->csum) 1359 data |= TX_DMA_CHKSUM_V2; 1360 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) 1361 data |= TX_DMA_SPTAG_V3; 1362 } 1363 WRITE_ONCE(desc->txd5, data); 1364 1365 data = 0; 1366 if (info->first && info->vlan) 1367 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1368 WRITE_ONCE(desc->txd6, data); 1369 1370 WRITE_ONCE(desc->txd7, 0); 1371 WRITE_ONCE(desc->txd8, 0); 1372 } 1373 1374 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1375 struct mtk_tx_dma_desc_info *info) 1376 { 1377 struct mtk_mac *mac = netdev_priv(dev); 1378 struct mtk_eth *eth = mac->hw; 1379 1380 if (mtk_is_netsys_v2_or_greater(eth)) 1381 mtk_tx_set_dma_desc_v2(dev, txd, info); 1382 else 1383 mtk_tx_set_dma_desc_v1(dev, txd, info); 1384 } 1385 1386 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1387 int tx_num, struct mtk_tx_ring *ring, bool gso) 1388 { 1389 struct mtk_tx_dma_desc_info txd_info = { 1390 .size = skb_headlen(skb), 1391 .gso = gso, 1392 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1393 .vlan = skb_vlan_tag_present(skb), 1394 .qid = skb_get_queue_mapping(skb), 1395 .vlan_tci = skb_vlan_tag_get(skb), 1396 .first = true, 1397 .last = !skb_is_nonlinear(skb), 1398 }; 1399 struct netdev_queue *txq; 1400 struct mtk_mac *mac = netdev_priv(dev); 1401 struct mtk_eth *eth = mac->hw; 1402 const struct mtk_soc_data *soc = eth->soc; 1403 struct mtk_tx_dma *itxd, *txd; 1404 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1405 struct mtk_tx_buf *itx_buf, *tx_buf; 1406 int i, n_desc = 1; 1407 int queue = skb_get_queue_mapping(skb); 1408 int k = 0; 1409 1410 txq = netdev_get_tx_queue(dev, queue); 1411 itxd = ring->next_free; 1412 itxd_pdma = qdma_to_pdma(ring, itxd); 1413 if (itxd == ring->last_free) 1414 return -ENOMEM; 1415 1416 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1417 memset(itx_buf, 0, sizeof(*itx_buf)); 1418 1419 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1420 DMA_TO_DEVICE); 1421 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1422 return -ENOMEM; 1423 1424 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1425 1426 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1427 itx_buf->mac_id = mac->id; 1428 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1429 k++); 1430 1431 /* TX SG offload */ 1432 txd = itxd; 1433 txd_pdma = qdma_to_pdma(ring, txd); 1434 1435 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1436 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1437 unsigned int offset = 0; 1438 int frag_size = skb_frag_size(frag); 1439 1440 while (frag_size) { 1441 bool new_desc = true; 1442 1443 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1444 (i & 0x1)) { 1445 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1446 txd_pdma = qdma_to_pdma(ring, txd); 1447 if (txd == ring->last_free) 1448 goto err_dma; 1449 1450 n_desc++; 1451 } else { 1452 new_desc = false; 1453 } 1454 1455 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1456 txd_info.size = min_t(unsigned int, frag_size, 1457 soc->txrx.dma_max_len); 1458 txd_info.qid = queue; 1459 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1460 !(frag_size - txd_info.size); 1461 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1462 offset, txd_info.size, 1463 DMA_TO_DEVICE); 1464 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1465 goto err_dma; 1466 1467 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1468 1469 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1470 soc->txrx.txd_size); 1471 if (new_desc) 1472 memset(tx_buf, 0, sizeof(*tx_buf)); 1473 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1474 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1475 tx_buf->mac_id = mac->id; 1476 1477 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1478 txd_info.size, k++); 1479 1480 frag_size -= txd_info.size; 1481 offset += txd_info.size; 1482 } 1483 } 1484 1485 /* store skb to cleanup */ 1486 itx_buf->type = MTK_TYPE_SKB; 1487 itx_buf->data = skb; 1488 1489 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1490 if (k & 0x1) 1491 txd_pdma->txd2 |= TX_DMA_LS0; 1492 else 1493 txd_pdma->txd2 |= TX_DMA_LS1; 1494 } 1495 1496 netdev_tx_sent_queue(txq, skb->len); 1497 skb_tx_timestamp(skb); 1498 1499 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1500 atomic_sub(n_desc, &ring->free_count); 1501 1502 /* make sure that all changes to the dma ring are flushed before we 1503 * continue 1504 */ 1505 wmb(); 1506 1507 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1508 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1509 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1510 } else { 1511 int next_idx; 1512 1513 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1514 ring->dma_size); 1515 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1516 } 1517 1518 return 0; 1519 1520 err_dma: 1521 do { 1522 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1523 1524 /* unmap dma */ 1525 mtk_tx_unmap(eth, tx_buf, NULL, false); 1526 1527 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1528 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1529 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1530 1531 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1532 itxd_pdma = qdma_to_pdma(ring, itxd); 1533 } while (itxd != txd); 1534 1535 return -ENOMEM; 1536 } 1537 1538 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1539 { 1540 int i, nfrags = 1; 1541 skb_frag_t *frag; 1542 1543 if (skb_is_gso(skb)) { 1544 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1545 frag = &skb_shinfo(skb)->frags[i]; 1546 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1547 eth->soc->txrx.dma_max_len); 1548 } 1549 } else { 1550 nfrags += skb_shinfo(skb)->nr_frags; 1551 } 1552 1553 return nfrags; 1554 } 1555 1556 static int mtk_queue_stopped(struct mtk_eth *eth) 1557 { 1558 int i; 1559 1560 for (i = 0; i < MTK_MAX_DEVS; i++) { 1561 if (!eth->netdev[i]) 1562 continue; 1563 if (netif_queue_stopped(eth->netdev[i])) 1564 return 1; 1565 } 1566 1567 return 0; 1568 } 1569 1570 static void mtk_wake_queue(struct mtk_eth *eth) 1571 { 1572 int i; 1573 1574 for (i = 0; i < MTK_MAX_DEVS; i++) { 1575 if (!eth->netdev[i]) 1576 continue; 1577 netif_tx_wake_all_queues(eth->netdev[i]); 1578 } 1579 } 1580 1581 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1582 { 1583 struct mtk_mac *mac = netdev_priv(dev); 1584 struct mtk_eth *eth = mac->hw; 1585 struct mtk_tx_ring *ring = ð->tx_ring; 1586 struct net_device_stats *stats = &dev->stats; 1587 bool gso = false; 1588 int tx_num; 1589 1590 /* normally we can rely on the stack not calling this more than once, 1591 * however we have 2 queues running on the same ring so we need to lock 1592 * the ring access 1593 */ 1594 spin_lock(ð->page_lock); 1595 1596 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1597 goto drop; 1598 1599 tx_num = mtk_cal_txd_req(eth, skb); 1600 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1601 netif_tx_stop_all_queues(dev); 1602 netif_err(eth, tx_queued, dev, 1603 "Tx Ring full when queue awake!\n"); 1604 spin_unlock(ð->page_lock); 1605 return NETDEV_TX_BUSY; 1606 } 1607 1608 /* TSO: fill MSS info in tcp checksum field */ 1609 if (skb_is_gso(skb)) { 1610 if (skb_cow_head(skb, 0)) { 1611 netif_warn(eth, tx_err, dev, 1612 "GSO expand head fail.\n"); 1613 goto drop; 1614 } 1615 1616 if (skb_shinfo(skb)->gso_type & 1617 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1618 gso = true; 1619 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1620 } 1621 } 1622 1623 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1624 goto drop; 1625 1626 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1627 netif_tx_stop_all_queues(dev); 1628 1629 spin_unlock(ð->page_lock); 1630 1631 return NETDEV_TX_OK; 1632 1633 drop: 1634 spin_unlock(ð->page_lock); 1635 stats->tx_dropped++; 1636 dev_kfree_skb_any(skb); 1637 return NETDEV_TX_OK; 1638 } 1639 1640 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1641 { 1642 int i; 1643 struct mtk_rx_ring *ring; 1644 int idx; 1645 1646 if (!eth->hwlro) 1647 return ð->rx_ring[0]; 1648 1649 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1650 struct mtk_rx_dma *rxd; 1651 1652 ring = ð->rx_ring[i]; 1653 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1654 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1655 if (rxd->rxd2 & RX_DMA_DONE) { 1656 ring->calc_idx_update = true; 1657 return ring; 1658 } 1659 } 1660 1661 return NULL; 1662 } 1663 1664 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1665 { 1666 struct mtk_rx_ring *ring; 1667 int i; 1668 1669 if (!eth->hwlro) { 1670 ring = ð->rx_ring[0]; 1671 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1672 } else { 1673 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1674 ring = ð->rx_ring[i]; 1675 if (ring->calc_idx_update) { 1676 ring->calc_idx_update = false; 1677 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1678 } 1679 } 1680 } 1681 } 1682 1683 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1684 { 1685 return mtk_is_netsys_v2_or_greater(eth); 1686 } 1687 1688 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1689 struct xdp_rxq_info *xdp_q, 1690 int id, int size) 1691 { 1692 struct page_pool_params pp_params = { 1693 .order = 0, 1694 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1695 .pool_size = size, 1696 .nid = NUMA_NO_NODE, 1697 .dev = eth->dma_dev, 1698 .offset = MTK_PP_HEADROOM, 1699 .max_len = MTK_PP_MAX_BUF_SIZE, 1700 }; 1701 struct page_pool *pp; 1702 int err; 1703 1704 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1705 : DMA_FROM_DEVICE; 1706 pp = page_pool_create(&pp_params); 1707 if (IS_ERR(pp)) 1708 return pp; 1709 1710 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id, 1711 eth->rx_napi.napi_id, PAGE_SIZE); 1712 if (err < 0) 1713 goto err_free_pp; 1714 1715 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1716 if (err) 1717 goto err_unregister_rxq; 1718 1719 return pp; 1720 1721 err_unregister_rxq: 1722 xdp_rxq_info_unreg(xdp_q); 1723 err_free_pp: 1724 page_pool_destroy(pp); 1725 1726 return ERR_PTR(err); 1727 } 1728 1729 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1730 gfp_t gfp_mask) 1731 { 1732 struct page *page; 1733 1734 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1735 if (!page) 1736 return NULL; 1737 1738 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1739 return page_address(page); 1740 } 1741 1742 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1743 { 1744 if (ring->page_pool) 1745 page_pool_put_full_page(ring->page_pool, 1746 virt_to_head_page(data), napi); 1747 else 1748 skb_free_frag(data); 1749 } 1750 1751 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1752 struct mtk_tx_dma_desc_info *txd_info, 1753 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1754 void *data, u16 headroom, int index, bool dma_map) 1755 { 1756 struct mtk_tx_ring *ring = ð->tx_ring; 1757 struct mtk_mac *mac = netdev_priv(dev); 1758 struct mtk_tx_dma *txd_pdma; 1759 1760 if (dma_map) { /* ndo_xdp_xmit */ 1761 txd_info->addr = dma_map_single(eth->dma_dev, data, 1762 txd_info->size, DMA_TO_DEVICE); 1763 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1764 return -ENOMEM; 1765 1766 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1767 } else { 1768 struct page *page = virt_to_head_page(data); 1769 1770 txd_info->addr = page_pool_get_dma_addr(page) + 1771 sizeof(struct xdp_frame) + headroom; 1772 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1773 txd_info->size, DMA_BIDIRECTIONAL); 1774 } 1775 mtk_tx_set_dma_desc(dev, txd, txd_info); 1776 1777 tx_buf->mac_id = mac->id; 1778 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1779 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1780 1781 txd_pdma = qdma_to_pdma(ring, txd); 1782 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1783 index); 1784 1785 return 0; 1786 } 1787 1788 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1789 struct net_device *dev, bool dma_map) 1790 { 1791 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1792 const struct mtk_soc_data *soc = eth->soc; 1793 struct mtk_tx_ring *ring = ð->tx_ring; 1794 struct mtk_mac *mac = netdev_priv(dev); 1795 struct mtk_tx_dma_desc_info txd_info = { 1796 .size = xdpf->len, 1797 .first = true, 1798 .last = !xdp_frame_has_frags(xdpf), 1799 .qid = mac->id, 1800 }; 1801 int err, index = 0, n_desc = 1, nr_frags; 1802 struct mtk_tx_buf *htx_buf, *tx_buf; 1803 struct mtk_tx_dma *htxd, *txd; 1804 void *data = xdpf->data; 1805 1806 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1807 return -EBUSY; 1808 1809 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1810 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1811 return -EBUSY; 1812 1813 spin_lock(ð->page_lock); 1814 1815 txd = ring->next_free; 1816 if (txd == ring->last_free) { 1817 spin_unlock(ð->page_lock); 1818 return -ENOMEM; 1819 } 1820 htxd = txd; 1821 1822 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1823 memset(tx_buf, 0, sizeof(*tx_buf)); 1824 htx_buf = tx_buf; 1825 1826 for (;;) { 1827 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1828 data, xdpf->headroom, index, dma_map); 1829 if (err < 0) 1830 goto unmap; 1831 1832 if (txd_info.last) 1833 break; 1834 1835 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1836 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1837 if (txd == ring->last_free) 1838 goto unmap; 1839 1840 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1841 soc->txrx.txd_size); 1842 memset(tx_buf, 0, sizeof(*tx_buf)); 1843 n_desc++; 1844 } 1845 1846 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1847 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1848 txd_info.last = index + 1 == nr_frags; 1849 txd_info.qid = mac->id; 1850 data = skb_frag_address(&sinfo->frags[index]); 1851 1852 index++; 1853 } 1854 /* store xdpf for cleanup */ 1855 htx_buf->data = xdpf; 1856 1857 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1858 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1859 1860 if (index & 1) 1861 txd_pdma->txd2 |= TX_DMA_LS0; 1862 else 1863 txd_pdma->txd2 |= TX_DMA_LS1; 1864 } 1865 1866 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1867 atomic_sub(n_desc, &ring->free_count); 1868 1869 /* make sure that all changes to the dma ring are flushed before we 1870 * continue 1871 */ 1872 wmb(); 1873 1874 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1875 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1876 } else { 1877 int idx; 1878 1879 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1880 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1881 MT7628_TX_CTX_IDX0); 1882 } 1883 1884 spin_unlock(ð->page_lock); 1885 1886 return 0; 1887 1888 unmap: 1889 while (htxd != txd) { 1890 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1891 mtk_tx_unmap(eth, tx_buf, NULL, false); 1892 1893 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1894 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1895 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1896 1897 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1898 } 1899 1900 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1901 } 1902 1903 spin_unlock(ð->page_lock); 1904 1905 return err; 1906 } 1907 1908 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1909 struct xdp_frame **frames, u32 flags) 1910 { 1911 struct mtk_mac *mac = netdev_priv(dev); 1912 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1913 struct mtk_eth *eth = mac->hw; 1914 int i, nxmit = 0; 1915 1916 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1917 return -EINVAL; 1918 1919 for (i = 0; i < num_frame; i++) { 1920 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1921 break; 1922 nxmit++; 1923 } 1924 1925 u64_stats_update_begin(&hw_stats->syncp); 1926 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1927 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1928 u64_stats_update_end(&hw_stats->syncp); 1929 1930 return nxmit; 1931 } 1932 1933 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1934 struct xdp_buff *xdp, struct net_device *dev) 1935 { 1936 struct mtk_mac *mac = netdev_priv(dev); 1937 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1938 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1939 struct bpf_prog *prog; 1940 u32 act = XDP_PASS; 1941 1942 rcu_read_lock(); 1943 1944 prog = rcu_dereference(eth->prog); 1945 if (!prog) 1946 goto out; 1947 1948 act = bpf_prog_run_xdp(prog, xdp); 1949 switch (act) { 1950 case XDP_PASS: 1951 count = &hw_stats->xdp_stats.rx_xdp_pass; 1952 goto update_stats; 1953 case XDP_REDIRECT: 1954 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1955 act = XDP_DROP; 1956 break; 1957 } 1958 1959 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1960 goto update_stats; 1961 case XDP_TX: { 1962 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1963 1964 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1965 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1966 act = XDP_DROP; 1967 break; 1968 } 1969 1970 count = &hw_stats->xdp_stats.rx_xdp_tx; 1971 goto update_stats; 1972 } 1973 default: 1974 bpf_warn_invalid_xdp_action(dev, prog, act); 1975 fallthrough; 1976 case XDP_ABORTED: 1977 trace_xdp_exception(dev, prog, act); 1978 fallthrough; 1979 case XDP_DROP: 1980 break; 1981 } 1982 1983 page_pool_put_full_page(ring->page_pool, 1984 virt_to_head_page(xdp->data), true); 1985 1986 update_stats: 1987 u64_stats_update_begin(&hw_stats->syncp); 1988 *count = *count + 1; 1989 u64_stats_update_end(&hw_stats->syncp); 1990 out: 1991 rcu_read_unlock(); 1992 1993 return act; 1994 } 1995 1996 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1997 struct mtk_eth *eth) 1998 { 1999 struct dim_sample dim_sample = {}; 2000 struct mtk_rx_ring *ring; 2001 bool xdp_flush = false; 2002 int idx; 2003 struct sk_buff *skb; 2004 u64 addr64 = 0; 2005 u8 *data, *new_data; 2006 struct mtk_rx_dma_v2 *rxd, trxd; 2007 int done = 0, bytes = 0; 2008 2009 while (done < budget) { 2010 unsigned int pktlen, *rxdcsum; 2011 struct net_device *netdev; 2012 dma_addr_t dma_addr; 2013 u32 hash, reason; 2014 int mac = 0; 2015 2016 ring = mtk_get_rx_ring(eth); 2017 if (unlikely(!ring)) 2018 goto rx_done; 2019 2020 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 2021 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 2022 data = ring->data[idx]; 2023 2024 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 2025 break; 2026 2027 /* find out which mac the packet come from. values start at 1 */ 2028 if (mtk_is_netsys_v2_or_greater(eth)) { 2029 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); 2030 2031 switch (val) { 2032 case PSE_GDM1_PORT: 2033 case PSE_GDM2_PORT: 2034 mac = val - 1; 2035 break; 2036 case PSE_GDM3_PORT: 2037 mac = MTK_GMAC3_ID; 2038 break; 2039 default: 2040 break; 2041 } 2042 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 2043 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { 2044 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 2045 } 2046 2047 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || 2048 !eth->netdev[mac])) 2049 goto release_desc; 2050 2051 netdev = eth->netdev[mac]; 2052 2053 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 2054 goto release_desc; 2055 2056 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 2057 2058 /* alloc new buffer */ 2059 if (ring->page_pool) { 2060 struct page *page = virt_to_head_page(data); 2061 struct xdp_buff xdp; 2062 u32 ret; 2063 2064 new_data = mtk_page_pool_get_buff(ring->page_pool, 2065 &dma_addr, 2066 GFP_ATOMIC); 2067 if (unlikely(!new_data)) { 2068 netdev->stats.rx_dropped++; 2069 goto release_desc; 2070 } 2071 2072 dma_sync_single_for_cpu(eth->dma_dev, 2073 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 2074 pktlen, page_pool_get_dma_dir(ring->page_pool)); 2075 2076 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 2077 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 2078 false); 2079 xdp_buff_clear_frags_flag(&xdp); 2080 2081 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 2082 if (ret == XDP_REDIRECT) 2083 xdp_flush = true; 2084 2085 if (ret != XDP_PASS) 2086 goto skip_rx; 2087 2088 skb = build_skb(data, PAGE_SIZE); 2089 if (unlikely(!skb)) { 2090 page_pool_put_full_page(ring->page_pool, 2091 page, true); 2092 netdev->stats.rx_dropped++; 2093 goto skip_rx; 2094 } 2095 2096 skb_reserve(skb, xdp.data - xdp.data_hard_start); 2097 skb_put(skb, xdp.data_end - xdp.data); 2098 skb_mark_for_recycle(skb); 2099 } else { 2100 if (ring->frag_size <= PAGE_SIZE) 2101 new_data = napi_alloc_frag(ring->frag_size); 2102 else 2103 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2104 2105 if (unlikely(!new_data)) { 2106 netdev->stats.rx_dropped++; 2107 goto release_desc; 2108 } 2109 2110 dma_addr = dma_map_single(eth->dma_dev, 2111 new_data + NET_SKB_PAD + eth->ip_align, 2112 ring->buf_size, DMA_FROM_DEVICE); 2113 if (unlikely(dma_mapping_error(eth->dma_dev, 2114 dma_addr))) { 2115 skb_free_frag(new_data); 2116 netdev->stats.rx_dropped++; 2117 goto release_desc; 2118 } 2119 2120 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2121 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2); 2122 2123 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), 2124 ring->buf_size, DMA_FROM_DEVICE); 2125 2126 skb = build_skb(data, ring->frag_size); 2127 if (unlikely(!skb)) { 2128 netdev->stats.rx_dropped++; 2129 skb_free_frag(data); 2130 goto skip_rx; 2131 } 2132 2133 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2134 skb_put(skb, pktlen); 2135 } 2136 2137 skb->dev = netdev; 2138 bytes += skb->len; 2139 2140 if (mtk_is_netsys_v2_or_greater(eth)) { 2141 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2142 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2143 if (hash != MTK_RXD5_FOE_ENTRY) 2144 skb_set_hash(skb, jhash_1word(hash, 0), 2145 PKT_HASH_TYPE_L4); 2146 rxdcsum = &trxd.rxd3; 2147 } else { 2148 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2149 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2150 if (hash != MTK_RXD4_FOE_ENTRY) 2151 skb_set_hash(skb, jhash_1word(hash, 0), 2152 PKT_HASH_TYPE_L4); 2153 rxdcsum = &trxd.rxd4; 2154 } 2155 2156 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 2157 skb->ip_summed = CHECKSUM_UNNECESSARY; 2158 else 2159 skb_checksum_none_assert(skb); 2160 skb->protocol = eth_type_trans(skb, netdev); 2161 2162 /* When using VLAN untagging in combination with DSA, the 2163 * hardware treats the MTK special tag as a VLAN and untags it. 2164 */ 2165 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && 2166 netdev_uses_dsa(netdev)) { 2167 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 2168 2169 if (port < ARRAY_SIZE(eth->dsa_meta) && 2170 eth->dsa_meta[port]) 2171 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2172 } 2173 2174 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2175 mtk_ppe_check_skb(eth->ppe[0], skb, hash); 2176 2177 skb_record_rx_queue(skb, 0); 2178 napi_gro_receive(napi, skb); 2179 2180 skip_rx: 2181 ring->data[idx] = new_data; 2182 rxd->rxd1 = (unsigned int)dma_addr; 2183 release_desc: 2184 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2185 rxd->rxd2 = RX_DMA_LSO; 2186 else 2187 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2188 2189 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2190 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2191 2192 ring->calc_idx = idx; 2193 done++; 2194 } 2195 2196 rx_done: 2197 if (done) { 2198 /* make sure that all changes to the dma ring are flushed before 2199 * we continue 2200 */ 2201 wmb(); 2202 mtk_update_rx_cpu_idx(eth); 2203 } 2204 2205 eth->rx_packets += done; 2206 eth->rx_bytes += bytes; 2207 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2208 &dim_sample); 2209 net_dim(ð->rx_dim, dim_sample); 2210 2211 if (xdp_flush) 2212 xdp_do_flush_map(); 2213 2214 return done; 2215 } 2216 2217 struct mtk_poll_state { 2218 struct netdev_queue *txq; 2219 unsigned int total; 2220 unsigned int done; 2221 unsigned int bytes; 2222 }; 2223 2224 static void 2225 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2226 struct sk_buff *skb) 2227 { 2228 struct netdev_queue *txq; 2229 struct net_device *dev; 2230 unsigned int bytes = skb->len; 2231 2232 state->total++; 2233 eth->tx_packets++; 2234 eth->tx_bytes += bytes; 2235 2236 dev = eth->netdev[mac]; 2237 if (!dev) 2238 return; 2239 2240 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2241 if (state->txq == txq) { 2242 state->done++; 2243 state->bytes += bytes; 2244 return; 2245 } 2246 2247 if (state->txq) 2248 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2249 2250 state->txq = txq; 2251 state->done = 1; 2252 state->bytes = bytes; 2253 } 2254 2255 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2256 struct mtk_poll_state *state) 2257 { 2258 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2259 struct mtk_tx_ring *ring = ð->tx_ring; 2260 struct mtk_tx_buf *tx_buf; 2261 struct xdp_frame_bulk bq; 2262 struct mtk_tx_dma *desc; 2263 u32 cpu, dma; 2264 2265 cpu = ring->last_free_ptr; 2266 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2267 2268 desc = mtk_qdma_phys_to_virt(ring, cpu); 2269 xdp_frame_bulk_init(&bq); 2270 2271 while ((cpu != dma) && budget) { 2272 u32 next_cpu = desc->txd2; 2273 2274 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2275 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2276 break; 2277 2278 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2279 eth->soc->txrx.txd_size); 2280 if (!tx_buf->data) 2281 break; 2282 2283 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2284 if (tx_buf->type == MTK_TYPE_SKB) 2285 mtk_poll_tx_done(eth, state, tx_buf->mac_id, 2286 tx_buf->data); 2287 2288 budget--; 2289 } 2290 mtk_tx_unmap(eth, tx_buf, &bq, true); 2291 2292 ring->last_free = desc; 2293 atomic_inc(&ring->free_count); 2294 2295 cpu = next_cpu; 2296 } 2297 xdp_flush_frame_bulk(&bq); 2298 2299 ring->last_free_ptr = cpu; 2300 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2301 2302 return budget; 2303 } 2304 2305 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2306 struct mtk_poll_state *state) 2307 { 2308 struct mtk_tx_ring *ring = ð->tx_ring; 2309 struct mtk_tx_buf *tx_buf; 2310 struct xdp_frame_bulk bq; 2311 struct mtk_tx_dma *desc; 2312 u32 cpu, dma; 2313 2314 cpu = ring->cpu_idx; 2315 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2316 xdp_frame_bulk_init(&bq); 2317 2318 while ((cpu != dma) && budget) { 2319 tx_buf = &ring->buf[cpu]; 2320 if (!tx_buf->data) 2321 break; 2322 2323 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2324 if (tx_buf->type == MTK_TYPE_SKB) 2325 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2326 budget--; 2327 } 2328 mtk_tx_unmap(eth, tx_buf, &bq, true); 2329 2330 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2331 ring->last_free = desc; 2332 atomic_inc(&ring->free_count); 2333 2334 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2335 } 2336 xdp_flush_frame_bulk(&bq); 2337 2338 ring->cpu_idx = cpu; 2339 2340 return budget; 2341 } 2342 2343 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2344 { 2345 struct mtk_tx_ring *ring = ð->tx_ring; 2346 struct dim_sample dim_sample = {}; 2347 struct mtk_poll_state state = {}; 2348 2349 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2350 budget = mtk_poll_tx_qdma(eth, budget, &state); 2351 else 2352 budget = mtk_poll_tx_pdma(eth, budget, &state); 2353 2354 if (state.txq) 2355 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2356 2357 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2358 &dim_sample); 2359 net_dim(ð->tx_dim, dim_sample); 2360 2361 if (mtk_queue_stopped(eth) && 2362 (atomic_read(&ring->free_count) > ring->thresh)) 2363 mtk_wake_queue(eth); 2364 2365 return state.total; 2366 } 2367 2368 static void mtk_handle_status_irq(struct mtk_eth *eth) 2369 { 2370 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2371 2372 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2373 mtk_stats_update(eth); 2374 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2375 MTK_INT_STATUS2); 2376 } 2377 } 2378 2379 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2380 { 2381 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2382 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2383 int tx_done = 0; 2384 2385 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2386 mtk_handle_status_irq(eth); 2387 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2388 tx_done = mtk_poll_tx(eth, budget); 2389 2390 if (unlikely(netif_msg_intr(eth))) { 2391 dev_info(eth->dev, 2392 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2393 mtk_r32(eth, reg_map->tx_irq_status), 2394 mtk_r32(eth, reg_map->tx_irq_mask)); 2395 } 2396 2397 if (tx_done == budget) 2398 return budget; 2399 2400 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2401 return budget; 2402 2403 if (napi_complete_done(napi, tx_done)) 2404 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2405 2406 return tx_done; 2407 } 2408 2409 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2410 { 2411 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2412 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2413 int rx_done_total = 0; 2414 2415 mtk_handle_status_irq(eth); 2416 2417 do { 2418 int rx_done; 2419 2420 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2421 reg_map->pdma.irq_status); 2422 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2423 rx_done_total += rx_done; 2424 2425 if (unlikely(netif_msg_intr(eth))) { 2426 dev_info(eth->dev, 2427 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2428 mtk_r32(eth, reg_map->pdma.irq_status), 2429 mtk_r32(eth, reg_map->pdma.irq_mask)); 2430 } 2431 2432 if (rx_done_total == budget) 2433 return budget; 2434 2435 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2436 eth->soc->txrx.rx_irq_done_mask); 2437 2438 if (napi_complete_done(napi, rx_done_total)) 2439 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2440 2441 return rx_done_total; 2442 } 2443 2444 static int mtk_tx_alloc(struct mtk_eth *eth) 2445 { 2446 const struct mtk_soc_data *soc = eth->soc; 2447 struct mtk_tx_ring *ring = ð->tx_ring; 2448 int i, sz = soc->txrx.txd_size; 2449 struct mtk_tx_dma_v2 *txd; 2450 int ring_size; 2451 u32 ofs, val; 2452 2453 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2454 ring_size = MTK_QDMA_RING_SIZE; 2455 else 2456 ring_size = MTK_DMA_SIZE; 2457 2458 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2459 GFP_KERNEL); 2460 if (!ring->buf) 2461 goto no_tx_mem; 2462 2463 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { 2464 ring->dma = eth->sram_base + ring_size * sz; 2465 ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz; 2466 } else { 2467 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2468 &ring->phys, GFP_KERNEL); 2469 } 2470 2471 if (!ring->dma) 2472 goto no_tx_mem; 2473 2474 for (i = 0; i < ring_size; i++) { 2475 int next = (i + 1) % ring_size; 2476 u32 next_ptr = ring->phys + next * sz; 2477 2478 txd = ring->dma + i * sz; 2479 txd->txd2 = next_ptr; 2480 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2481 txd->txd4 = 0; 2482 if (mtk_is_netsys_v2_or_greater(eth)) { 2483 txd->txd5 = 0; 2484 txd->txd6 = 0; 2485 txd->txd7 = 0; 2486 txd->txd8 = 0; 2487 } 2488 } 2489 2490 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2491 * only as the framework. The real HW descriptors are the PDMA 2492 * descriptors in ring->dma_pdma. 2493 */ 2494 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2495 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2496 &ring->phys_pdma, GFP_KERNEL); 2497 if (!ring->dma_pdma) 2498 goto no_tx_mem; 2499 2500 for (i = 0; i < ring_size; i++) { 2501 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2502 ring->dma_pdma[i].txd4 = 0; 2503 } 2504 } 2505 2506 ring->dma_size = ring_size; 2507 atomic_set(&ring->free_count, ring_size - 2); 2508 ring->next_free = ring->dma; 2509 ring->last_free = (void *)txd; 2510 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2511 ring->thresh = MAX_SKB_FRAGS; 2512 2513 /* make sure that all changes to the dma ring are flushed before we 2514 * continue 2515 */ 2516 wmb(); 2517 2518 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2519 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2520 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2521 mtk_w32(eth, 2522 ring->phys + ((ring_size - 1) * sz), 2523 soc->reg_map->qdma.crx_ptr); 2524 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2525 2526 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2527 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2528 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2529 2530 val = MTK_QTX_SCH_MIN_RATE_EN | 2531 /* minimum: 10 Mbps */ 2532 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2533 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2534 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2535 if (mtk_is_netsys_v1(eth)) 2536 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2537 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2538 ofs += MTK_QTX_OFFSET; 2539 } 2540 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2541 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2542 if (mtk_is_netsys_v2_or_greater(eth)) 2543 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2544 } else { 2545 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2546 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2547 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2548 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2549 } 2550 2551 return 0; 2552 2553 no_tx_mem: 2554 return -ENOMEM; 2555 } 2556 2557 static void mtk_tx_clean(struct mtk_eth *eth) 2558 { 2559 const struct mtk_soc_data *soc = eth->soc; 2560 struct mtk_tx_ring *ring = ð->tx_ring; 2561 int i; 2562 2563 if (ring->buf) { 2564 for (i = 0; i < ring->dma_size; i++) 2565 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2566 kfree(ring->buf); 2567 ring->buf = NULL; 2568 } 2569 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { 2570 dma_free_coherent(eth->dma_dev, 2571 ring->dma_size * soc->txrx.txd_size, 2572 ring->dma, ring->phys); 2573 ring->dma = NULL; 2574 } 2575 2576 if (ring->dma_pdma) { 2577 dma_free_coherent(eth->dma_dev, 2578 ring->dma_size * soc->txrx.txd_size, 2579 ring->dma_pdma, ring->phys_pdma); 2580 ring->dma_pdma = NULL; 2581 } 2582 } 2583 2584 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2585 { 2586 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2587 struct mtk_rx_ring *ring; 2588 int rx_data_len, rx_dma_size, tx_ring_size; 2589 int i; 2590 2591 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2592 tx_ring_size = MTK_QDMA_RING_SIZE; 2593 else 2594 tx_ring_size = MTK_DMA_SIZE; 2595 2596 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2597 if (ring_no) 2598 return -EINVAL; 2599 ring = ð->rx_ring_qdma; 2600 } else { 2601 ring = ð->rx_ring[ring_no]; 2602 } 2603 2604 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2605 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2606 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2607 } else { 2608 rx_data_len = ETH_DATA_LEN; 2609 rx_dma_size = MTK_DMA_SIZE; 2610 } 2611 2612 ring->frag_size = mtk_max_frag_size(rx_data_len); 2613 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2614 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2615 GFP_KERNEL); 2616 if (!ring->data) 2617 return -ENOMEM; 2618 2619 if (mtk_page_pool_enabled(eth)) { 2620 struct page_pool *pp; 2621 2622 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2623 rx_dma_size); 2624 if (IS_ERR(pp)) 2625 return PTR_ERR(pp); 2626 2627 ring->page_pool = pp; 2628 } 2629 2630 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || 2631 rx_flag != MTK_RX_FLAGS_NORMAL) { 2632 ring->dma = dma_alloc_coherent(eth->dma_dev, 2633 rx_dma_size * eth->soc->txrx.rxd_size, 2634 &ring->phys, GFP_KERNEL); 2635 } else { 2636 struct mtk_tx_ring *tx_ring = ð->tx_ring; 2637 2638 ring->dma = tx_ring->dma + tx_ring_size * 2639 eth->soc->txrx.txd_size * (ring_no + 1); 2640 ring->phys = tx_ring->phys + tx_ring_size * 2641 eth->soc->txrx.txd_size * (ring_no + 1); 2642 } 2643 2644 if (!ring->dma) 2645 return -ENOMEM; 2646 2647 for (i = 0; i < rx_dma_size; i++) { 2648 struct mtk_rx_dma_v2 *rxd; 2649 dma_addr_t dma_addr; 2650 void *data; 2651 2652 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2653 if (ring->page_pool) { 2654 data = mtk_page_pool_get_buff(ring->page_pool, 2655 &dma_addr, GFP_KERNEL); 2656 if (!data) 2657 return -ENOMEM; 2658 } else { 2659 if (ring->frag_size <= PAGE_SIZE) 2660 data = netdev_alloc_frag(ring->frag_size); 2661 else 2662 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2663 2664 if (!data) 2665 return -ENOMEM; 2666 2667 dma_addr = dma_map_single(eth->dma_dev, 2668 data + NET_SKB_PAD + eth->ip_align, 2669 ring->buf_size, DMA_FROM_DEVICE); 2670 if (unlikely(dma_mapping_error(eth->dma_dev, 2671 dma_addr))) { 2672 skb_free_frag(data); 2673 return -ENOMEM; 2674 } 2675 } 2676 rxd->rxd1 = (unsigned int)dma_addr; 2677 ring->data[i] = data; 2678 2679 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2680 rxd->rxd2 = RX_DMA_LSO; 2681 else 2682 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2683 2684 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2685 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2686 2687 rxd->rxd3 = 0; 2688 rxd->rxd4 = 0; 2689 if (mtk_is_netsys_v2_or_greater(eth)) { 2690 rxd->rxd5 = 0; 2691 rxd->rxd6 = 0; 2692 rxd->rxd7 = 0; 2693 rxd->rxd8 = 0; 2694 } 2695 } 2696 2697 ring->dma_size = rx_dma_size; 2698 ring->calc_idx_update = false; 2699 ring->calc_idx = rx_dma_size - 1; 2700 if (rx_flag == MTK_RX_FLAGS_QDMA) 2701 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2702 ring_no * MTK_QRX_OFFSET; 2703 else 2704 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2705 ring_no * MTK_QRX_OFFSET; 2706 /* make sure that all changes to the dma ring are flushed before we 2707 * continue 2708 */ 2709 wmb(); 2710 2711 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2712 mtk_w32(eth, ring->phys, 2713 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2714 mtk_w32(eth, rx_dma_size, 2715 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2716 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2717 reg_map->qdma.rst_idx); 2718 } else { 2719 mtk_w32(eth, ring->phys, 2720 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2721 mtk_w32(eth, rx_dma_size, 2722 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2723 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2724 reg_map->pdma.rst_idx); 2725 } 2726 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2727 2728 return 0; 2729 } 2730 2731 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) 2732 { 2733 u64 addr64 = 0; 2734 int i; 2735 2736 if (ring->data && ring->dma) { 2737 for (i = 0; i < ring->dma_size; i++) { 2738 struct mtk_rx_dma *rxd; 2739 2740 if (!ring->data[i]) 2741 continue; 2742 2743 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2744 if (!rxd->rxd1) 2745 continue; 2746 2747 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2748 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); 2749 2750 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), 2751 ring->buf_size, DMA_FROM_DEVICE); 2752 mtk_rx_put_buff(ring, ring->data[i], false); 2753 } 2754 kfree(ring->data); 2755 ring->data = NULL; 2756 } 2757 2758 if (!in_sram && ring->dma) { 2759 dma_free_coherent(eth->dma_dev, 2760 ring->dma_size * eth->soc->txrx.rxd_size, 2761 ring->dma, ring->phys); 2762 ring->dma = NULL; 2763 } 2764 2765 if (ring->page_pool) { 2766 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2767 xdp_rxq_info_unreg(&ring->xdp_q); 2768 page_pool_destroy(ring->page_pool); 2769 ring->page_pool = NULL; 2770 } 2771 } 2772 2773 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2774 { 2775 int i; 2776 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2777 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2778 2779 /* set LRO rings to auto-learn modes */ 2780 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2781 2782 /* validate LRO ring */ 2783 ring_ctrl_dw2 |= MTK_RING_VLD; 2784 2785 /* set AGE timer (unit: 20us) */ 2786 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2787 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2788 2789 /* set max AGG timer (unit: 20us) */ 2790 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2791 2792 /* set max LRO AGG count */ 2793 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2794 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2795 2796 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2797 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2798 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2799 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2800 } 2801 2802 /* IPv4 checksum update enable */ 2803 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2804 2805 /* switch priority comparison to packet count mode */ 2806 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2807 2808 /* bandwidth threshold setting */ 2809 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2810 2811 /* auto-learn score delta setting */ 2812 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2813 2814 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2815 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2816 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2817 2818 /* set HW LRO mode & the max aggregation count for rx packets */ 2819 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2820 2821 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2822 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2823 2824 /* enable HW LRO */ 2825 lro_ctrl_dw0 |= MTK_LRO_EN; 2826 2827 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2828 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2829 2830 return 0; 2831 } 2832 2833 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2834 { 2835 int i; 2836 u32 val; 2837 2838 /* relinquish lro rings, flush aggregated packets */ 2839 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2840 2841 /* wait for relinquishments done */ 2842 for (i = 0; i < 10; i++) { 2843 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2844 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2845 msleep(20); 2846 continue; 2847 } 2848 break; 2849 } 2850 2851 /* invalidate lro rings */ 2852 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2853 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2854 2855 /* disable HW LRO */ 2856 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2857 } 2858 2859 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2860 { 2861 u32 reg_val; 2862 2863 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2864 2865 /* invalidate the IP setting */ 2866 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2867 2868 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2869 2870 /* validate the IP setting */ 2871 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2872 } 2873 2874 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2875 { 2876 u32 reg_val; 2877 2878 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2879 2880 /* invalidate the IP setting */ 2881 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2882 2883 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2884 } 2885 2886 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2887 { 2888 int cnt = 0; 2889 int i; 2890 2891 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2892 if (mac->hwlro_ip[i]) 2893 cnt++; 2894 } 2895 2896 return cnt; 2897 } 2898 2899 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2900 struct ethtool_rxnfc *cmd) 2901 { 2902 struct ethtool_rx_flow_spec *fsp = 2903 (struct ethtool_rx_flow_spec *)&cmd->fs; 2904 struct mtk_mac *mac = netdev_priv(dev); 2905 struct mtk_eth *eth = mac->hw; 2906 int hwlro_idx; 2907 2908 if ((fsp->flow_type != TCP_V4_FLOW) || 2909 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2910 (fsp->location > 1)) 2911 return -EINVAL; 2912 2913 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2914 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2915 2916 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2917 2918 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2919 2920 return 0; 2921 } 2922 2923 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2924 struct ethtool_rxnfc *cmd) 2925 { 2926 struct ethtool_rx_flow_spec *fsp = 2927 (struct ethtool_rx_flow_spec *)&cmd->fs; 2928 struct mtk_mac *mac = netdev_priv(dev); 2929 struct mtk_eth *eth = mac->hw; 2930 int hwlro_idx; 2931 2932 if (fsp->location > 1) 2933 return -EINVAL; 2934 2935 mac->hwlro_ip[fsp->location] = 0; 2936 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2937 2938 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2939 2940 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2941 2942 return 0; 2943 } 2944 2945 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2946 { 2947 struct mtk_mac *mac = netdev_priv(dev); 2948 struct mtk_eth *eth = mac->hw; 2949 int i, hwlro_idx; 2950 2951 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2952 mac->hwlro_ip[i] = 0; 2953 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2954 2955 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2956 } 2957 2958 mac->hwlro_ip_cnt = 0; 2959 } 2960 2961 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2962 struct ethtool_rxnfc *cmd) 2963 { 2964 struct mtk_mac *mac = netdev_priv(dev); 2965 struct ethtool_rx_flow_spec *fsp = 2966 (struct ethtool_rx_flow_spec *)&cmd->fs; 2967 2968 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2969 return -EINVAL; 2970 2971 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2972 fsp->flow_type = TCP_V4_FLOW; 2973 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2974 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2975 2976 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2977 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2978 fsp->h_u.tcp_ip4_spec.psrc = 0; 2979 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2980 fsp->h_u.tcp_ip4_spec.pdst = 0; 2981 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2982 fsp->h_u.tcp_ip4_spec.tos = 0; 2983 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2984 2985 return 0; 2986 } 2987 2988 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2989 struct ethtool_rxnfc *cmd, 2990 u32 *rule_locs) 2991 { 2992 struct mtk_mac *mac = netdev_priv(dev); 2993 int cnt = 0; 2994 int i; 2995 2996 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2997 if (mac->hwlro_ip[i]) { 2998 rule_locs[cnt] = i; 2999 cnt++; 3000 } 3001 } 3002 3003 cmd->rule_cnt = cnt; 3004 3005 return 0; 3006 } 3007 3008 static netdev_features_t mtk_fix_features(struct net_device *dev, 3009 netdev_features_t features) 3010 { 3011 if (!(features & NETIF_F_LRO)) { 3012 struct mtk_mac *mac = netdev_priv(dev); 3013 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3014 3015 if (ip_cnt) { 3016 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 3017 3018 features |= NETIF_F_LRO; 3019 } 3020 } 3021 3022 return features; 3023 } 3024 3025 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 3026 { 3027 netdev_features_t diff = dev->features ^ features; 3028 3029 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 3030 mtk_hwlro_netdev_disable(dev); 3031 3032 return 0; 3033 } 3034 3035 /* wait for DMA to finish whatever it is doing before we start using it again */ 3036 static int mtk_dma_busy_wait(struct mtk_eth *eth) 3037 { 3038 unsigned int reg; 3039 int ret; 3040 u32 val; 3041 3042 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3043 reg = eth->soc->reg_map->qdma.glo_cfg; 3044 else 3045 reg = eth->soc->reg_map->pdma.glo_cfg; 3046 3047 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 3048 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 3049 5, MTK_DMA_BUSY_TIMEOUT_US); 3050 if (ret) 3051 dev_err(eth->dev, "DMA init timeout\n"); 3052 3053 return ret; 3054 } 3055 3056 static int mtk_dma_init(struct mtk_eth *eth) 3057 { 3058 int err; 3059 u32 i; 3060 3061 if (mtk_dma_busy_wait(eth)) 3062 return -EBUSY; 3063 3064 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3065 /* QDMA needs scratch memory for internal reordering of the 3066 * descriptors 3067 */ 3068 err = mtk_init_fq_dma(eth); 3069 if (err) 3070 return err; 3071 } 3072 3073 err = mtk_tx_alloc(eth); 3074 if (err) 3075 return err; 3076 3077 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3078 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 3079 if (err) 3080 return err; 3081 } 3082 3083 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 3084 if (err) 3085 return err; 3086 3087 if (eth->hwlro) { 3088 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 3089 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 3090 if (err) 3091 return err; 3092 } 3093 err = mtk_hwlro_rx_init(eth); 3094 if (err) 3095 return err; 3096 } 3097 3098 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3099 /* Enable random early drop and set drop threshold 3100 * automatically 3101 */ 3102 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 3103 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 3104 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 3105 } 3106 3107 return 0; 3108 } 3109 3110 static void mtk_dma_free(struct mtk_eth *eth) 3111 { 3112 const struct mtk_soc_data *soc = eth->soc; 3113 int i; 3114 3115 for (i = 0; i < MTK_MAX_DEVS; i++) 3116 if (eth->netdev[i]) 3117 netdev_reset_queue(eth->netdev[i]); 3118 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { 3119 dma_free_coherent(eth->dma_dev, 3120 MTK_QDMA_RING_SIZE * soc->txrx.txd_size, 3121 eth->scratch_ring, eth->phy_scratch_ring); 3122 eth->scratch_ring = NULL; 3123 eth->phy_scratch_ring = 0; 3124 } 3125 mtk_tx_clean(eth); 3126 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); 3127 mtk_rx_clean(eth, ð->rx_ring_qdma, false); 3128 3129 if (eth->hwlro) { 3130 mtk_hwlro_rx_uninit(eth); 3131 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3132 mtk_rx_clean(eth, ð->rx_ring[i], false); 3133 } 3134 3135 kfree(eth->scratch_head); 3136 } 3137 3138 static bool mtk_hw_reset_check(struct mtk_eth *eth) 3139 { 3140 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3141 3142 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3143 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3144 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3145 } 3146 3147 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3148 { 3149 struct mtk_mac *mac = netdev_priv(dev); 3150 struct mtk_eth *eth = mac->hw; 3151 3152 if (test_bit(MTK_RESETTING, ð->state)) 3153 return; 3154 3155 if (!mtk_hw_reset_check(eth)) 3156 return; 3157 3158 eth->netdev[mac->id]->stats.tx_errors++; 3159 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3160 3161 schedule_work(ð->pending_work); 3162 } 3163 3164 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3165 { 3166 struct mtk_eth *eth = _eth; 3167 3168 eth->rx_events++; 3169 if (likely(napi_schedule_prep(ð->rx_napi))) { 3170 __napi_schedule(ð->rx_napi); 3171 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3172 } 3173 3174 return IRQ_HANDLED; 3175 } 3176 3177 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3178 { 3179 struct mtk_eth *eth = _eth; 3180 3181 eth->tx_events++; 3182 if (likely(napi_schedule_prep(ð->tx_napi))) { 3183 __napi_schedule(ð->tx_napi); 3184 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3185 } 3186 3187 return IRQ_HANDLED; 3188 } 3189 3190 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3191 { 3192 struct mtk_eth *eth = _eth; 3193 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3194 3195 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3196 eth->soc->txrx.rx_irq_done_mask) { 3197 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3198 eth->soc->txrx.rx_irq_done_mask) 3199 mtk_handle_irq_rx(irq, _eth); 3200 } 3201 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3202 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3203 mtk_handle_irq_tx(irq, _eth); 3204 } 3205 3206 return IRQ_HANDLED; 3207 } 3208 3209 #ifdef CONFIG_NET_POLL_CONTROLLER 3210 static void mtk_poll_controller(struct net_device *dev) 3211 { 3212 struct mtk_mac *mac = netdev_priv(dev); 3213 struct mtk_eth *eth = mac->hw; 3214 3215 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3216 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3217 mtk_handle_irq_rx(eth->irq[2], dev); 3218 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3219 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 3220 } 3221 #endif 3222 3223 static int mtk_start_dma(struct mtk_eth *eth) 3224 { 3225 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3226 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3227 int err; 3228 3229 err = mtk_dma_init(eth); 3230 if (err) { 3231 mtk_dma_free(eth); 3232 return err; 3233 } 3234 3235 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3236 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3237 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3238 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3239 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3240 3241 if (mtk_is_netsys_v2_or_greater(eth)) 3242 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3243 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3244 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3245 else 3246 val |= MTK_RX_BT_32DWORDS; 3247 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3248 3249 mtk_w32(eth, 3250 MTK_RX_DMA_EN | rx_2b_offset | 3251 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3252 reg_map->pdma.glo_cfg); 3253 } else { 3254 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3255 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3256 reg_map->pdma.glo_cfg); 3257 } 3258 3259 return 0; 3260 } 3261 3262 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 3263 { 3264 int i; 3265 3266 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3267 return; 3268 3269 for (i = 0; i < MTK_MAX_DEVS; i++) { 3270 u32 val; 3271 3272 if (!eth->netdev[i]) 3273 continue; 3274 3275 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3276 3277 /* default setup the forward port to send frame to PDMA */ 3278 val &= ~0xffff; 3279 3280 /* Enable RX checksum */ 3281 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3282 3283 val |= config; 3284 3285 if (netdev_uses_dsa(eth->netdev[i])) 3286 val |= MTK_GDMA_SPECIAL_TAG; 3287 3288 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 3289 } 3290 /* Reset and enable PSE */ 3291 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3292 mtk_w32(eth, 0, MTK_RST_GL); 3293 } 3294 3295 3296 static bool mtk_uses_dsa(struct net_device *dev) 3297 { 3298 #if IS_ENABLED(CONFIG_NET_DSA) 3299 return netdev_uses_dsa(dev) && 3300 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3301 #else 3302 return false; 3303 #endif 3304 } 3305 3306 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3307 { 3308 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3309 struct mtk_eth *eth = mac->hw; 3310 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3311 struct ethtool_link_ksettings s; 3312 struct net_device *ldev; 3313 struct list_head *iter; 3314 struct dsa_port *dp; 3315 3316 if (event != NETDEV_CHANGE) 3317 return NOTIFY_DONE; 3318 3319 netdev_for_each_lower_dev(dev, ldev, iter) { 3320 if (netdev_priv(ldev) == mac) 3321 goto found; 3322 } 3323 3324 return NOTIFY_DONE; 3325 3326 found: 3327 if (!dsa_slave_dev_check(dev)) 3328 return NOTIFY_DONE; 3329 3330 if (__ethtool_get_link_ksettings(dev, &s)) 3331 return NOTIFY_DONE; 3332 3333 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3334 return NOTIFY_DONE; 3335 3336 dp = dsa_port_from_netdev(dev); 3337 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3338 return NOTIFY_DONE; 3339 3340 if (mac->speed > 0 && mac->speed <= s.base.speed) 3341 s.base.speed = 0; 3342 3343 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3344 3345 return NOTIFY_DONE; 3346 } 3347 3348 static int mtk_open(struct net_device *dev) 3349 { 3350 struct mtk_mac *mac = netdev_priv(dev); 3351 struct mtk_eth *eth = mac->hw; 3352 int i, err; 3353 3354 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3355 if (err) { 3356 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3357 err); 3358 return err; 3359 } 3360 3361 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3362 if (!refcount_read(ð->dma_refcnt)) { 3363 const struct mtk_soc_data *soc = eth->soc; 3364 u32 gdm_config; 3365 int i; 3366 3367 err = mtk_start_dma(eth); 3368 if (err) { 3369 phylink_disconnect_phy(mac->phylink); 3370 return err; 3371 } 3372 3373 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3374 mtk_ppe_start(eth->ppe[i]); 3375 3376 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe 3377 : MTK_GDMA_TO_PDMA; 3378 mtk_gdm_config(eth, gdm_config); 3379 3380 napi_enable(ð->tx_napi); 3381 napi_enable(ð->rx_napi); 3382 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3383 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); 3384 refcount_set(ð->dma_refcnt, 1); 3385 } 3386 else 3387 refcount_inc(ð->dma_refcnt); 3388 3389 phylink_start(mac->phylink); 3390 netif_tx_start_all_queues(dev); 3391 3392 if (mtk_is_netsys_v2_or_greater(eth)) 3393 return 0; 3394 3395 if (mtk_uses_dsa(dev) && !eth->prog) { 3396 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3397 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3398 3399 if (md_dst) 3400 continue; 3401 3402 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3403 GFP_KERNEL); 3404 if (!md_dst) 3405 return -ENOMEM; 3406 3407 md_dst->u.port_info.port_id = i; 3408 eth->dsa_meta[i] = md_dst; 3409 } 3410 } else { 3411 /* Hardware DSA untagging and VLAN RX offloading need to be 3412 * disabled if at least one MAC does not use DSA. 3413 */ 3414 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3415 3416 val &= ~MTK_CDMP_STAG_EN; 3417 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3418 3419 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); 3420 } 3421 3422 return 0; 3423 } 3424 3425 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3426 { 3427 u32 val; 3428 int i; 3429 3430 /* stop the dma engine */ 3431 spin_lock_bh(ð->page_lock); 3432 val = mtk_r32(eth, glo_cfg); 3433 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3434 glo_cfg); 3435 spin_unlock_bh(ð->page_lock); 3436 3437 /* wait for dma stop */ 3438 for (i = 0; i < 10; i++) { 3439 val = mtk_r32(eth, glo_cfg); 3440 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3441 msleep(20); 3442 continue; 3443 } 3444 break; 3445 } 3446 } 3447 3448 static int mtk_stop(struct net_device *dev) 3449 { 3450 struct mtk_mac *mac = netdev_priv(dev); 3451 struct mtk_eth *eth = mac->hw; 3452 int i; 3453 3454 phylink_stop(mac->phylink); 3455 3456 netif_tx_disable(dev); 3457 3458 phylink_disconnect_phy(mac->phylink); 3459 3460 /* only shutdown DMA if this is the last user */ 3461 if (!refcount_dec_and_test(ð->dma_refcnt)) 3462 return 0; 3463 3464 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3465 3466 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3467 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3468 napi_disable(ð->tx_napi); 3469 napi_disable(ð->rx_napi); 3470 3471 cancel_work_sync(ð->rx_dim.work); 3472 cancel_work_sync(ð->tx_dim.work); 3473 3474 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3475 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3476 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3477 3478 mtk_dma_free(eth); 3479 3480 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3481 mtk_ppe_stop(eth->ppe[i]); 3482 3483 return 0; 3484 } 3485 3486 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3487 struct netlink_ext_ack *extack) 3488 { 3489 struct mtk_mac *mac = netdev_priv(dev); 3490 struct mtk_eth *eth = mac->hw; 3491 struct bpf_prog *old_prog; 3492 bool need_update; 3493 3494 if (eth->hwlro) { 3495 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3496 return -EOPNOTSUPP; 3497 } 3498 3499 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3500 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3501 return -EOPNOTSUPP; 3502 } 3503 3504 need_update = !!eth->prog != !!prog; 3505 if (netif_running(dev) && need_update) 3506 mtk_stop(dev); 3507 3508 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3509 if (old_prog) 3510 bpf_prog_put(old_prog); 3511 3512 if (netif_running(dev) && need_update) 3513 return mtk_open(dev); 3514 3515 return 0; 3516 } 3517 3518 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3519 { 3520 switch (xdp->command) { 3521 case XDP_SETUP_PROG: 3522 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3523 default: 3524 return -EINVAL; 3525 } 3526 } 3527 3528 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3529 { 3530 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3531 reset_bits, 3532 reset_bits); 3533 3534 usleep_range(1000, 1100); 3535 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3536 reset_bits, 3537 ~reset_bits); 3538 mdelay(10); 3539 } 3540 3541 static void mtk_clk_disable(struct mtk_eth *eth) 3542 { 3543 int clk; 3544 3545 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3546 clk_disable_unprepare(eth->clks[clk]); 3547 } 3548 3549 static int mtk_clk_enable(struct mtk_eth *eth) 3550 { 3551 int clk, ret; 3552 3553 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3554 ret = clk_prepare_enable(eth->clks[clk]); 3555 if (ret) 3556 goto err_disable_clks; 3557 } 3558 3559 return 0; 3560 3561 err_disable_clks: 3562 while (--clk >= 0) 3563 clk_disable_unprepare(eth->clks[clk]); 3564 3565 return ret; 3566 } 3567 3568 static void mtk_dim_rx(struct work_struct *work) 3569 { 3570 struct dim *dim = container_of(work, struct dim, work); 3571 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3572 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3573 struct dim_cq_moder cur_profile; 3574 u32 val, cur; 3575 3576 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3577 dim->profile_ix); 3578 spin_lock_bh(ð->dim_lock); 3579 3580 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3581 val &= MTK_PDMA_DELAY_TX_MASK; 3582 val |= MTK_PDMA_DELAY_RX_EN; 3583 3584 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3585 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3586 3587 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3588 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3589 3590 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3591 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3592 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3593 3594 spin_unlock_bh(ð->dim_lock); 3595 3596 dim->state = DIM_START_MEASURE; 3597 } 3598 3599 static void mtk_dim_tx(struct work_struct *work) 3600 { 3601 struct dim *dim = container_of(work, struct dim, work); 3602 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3603 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3604 struct dim_cq_moder cur_profile; 3605 u32 val, cur; 3606 3607 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3608 dim->profile_ix); 3609 spin_lock_bh(ð->dim_lock); 3610 3611 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3612 val &= MTK_PDMA_DELAY_RX_MASK; 3613 val |= MTK_PDMA_DELAY_TX_EN; 3614 3615 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3616 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3617 3618 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3619 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3620 3621 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3622 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3623 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3624 3625 spin_unlock_bh(ð->dim_lock); 3626 3627 dim->state = DIM_START_MEASURE; 3628 } 3629 3630 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3631 { 3632 struct mtk_eth *eth = mac->hw; 3633 u32 mcr_cur, mcr_new; 3634 3635 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3636 return; 3637 3638 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3639 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3640 3641 if (val <= 1518) 3642 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3643 else if (val <= 1536) 3644 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3645 else if (val <= 1552) 3646 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3647 else 3648 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3649 3650 if (mcr_new != mcr_cur) 3651 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3652 } 3653 3654 static void mtk_hw_reset(struct mtk_eth *eth) 3655 { 3656 u32 val; 3657 3658 if (mtk_is_netsys_v2_or_greater(eth)) 3659 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3660 3661 if (mtk_is_netsys_v3_or_greater(eth)) { 3662 val = RSTCTRL_PPE0_V3; 3663 3664 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3665 val |= RSTCTRL_PPE1_V3; 3666 3667 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3668 val |= RSTCTRL_PPE2; 3669 3670 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3671 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3672 val = RSTCTRL_PPE0_V2; 3673 3674 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3675 val |= RSTCTRL_PPE1; 3676 } else { 3677 val = RSTCTRL_PPE0; 3678 } 3679 3680 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3681 3682 if (mtk_is_netsys_v3_or_greater(eth)) 3683 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3684 0x6f8ff); 3685 else if (mtk_is_netsys_v2_or_greater(eth)) 3686 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3687 0x3ffffff); 3688 } 3689 3690 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3691 { 3692 u32 val; 3693 3694 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3695 return val; 3696 } 3697 3698 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3699 { 3700 u32 rst_mask, val; 3701 3702 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3703 RSTCTRL_FE); 3704 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3705 val & RSTCTRL_FE, 1, 1000)) { 3706 dev_err(eth->dev, "warm reset failed\n"); 3707 mtk_hw_reset(eth); 3708 return; 3709 } 3710 3711 if (mtk_is_netsys_v3_or_greater(eth)) { 3712 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3; 3713 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3714 rst_mask |= RSTCTRL_PPE1_V3; 3715 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3716 rst_mask |= RSTCTRL_PPE2; 3717 3718 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3719 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3720 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3721 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3722 rst_mask |= RSTCTRL_PPE1; 3723 } else { 3724 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3725 } 3726 3727 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3728 3729 udelay(1); 3730 val = mtk_hw_reset_read(eth); 3731 if (!(val & rst_mask)) 3732 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3733 val, rst_mask); 3734 3735 rst_mask |= RSTCTRL_FE; 3736 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3737 3738 udelay(1); 3739 val = mtk_hw_reset_read(eth); 3740 if (val & rst_mask) 3741 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3742 val, rst_mask); 3743 } 3744 3745 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3746 { 3747 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3748 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3749 bool oq_hang, cdm1_busy, adma_busy; 3750 bool wtx_busy, cdm_full, oq_free; 3751 u32 wdidx, val, gdm1_fc, gdm2_fc; 3752 bool qfsm_hang, qfwd_hang; 3753 bool ret = false; 3754 3755 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3756 return false; 3757 3758 /* WDMA sanity checks */ 3759 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3760 3761 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3762 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3763 3764 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3765 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3766 3767 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3768 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3769 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3770 3771 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3772 if (++eth->reset.wdma_hang_count > 2) { 3773 eth->reset.wdma_hang_count = 0; 3774 ret = true; 3775 } 3776 goto out; 3777 } 3778 3779 /* QDMA sanity checks */ 3780 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3781 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3782 3783 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3784 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3785 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3786 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3787 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3788 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3789 3790 if (qfsm_hang && qfwd_hang && 3791 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3792 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3793 if (++eth->reset.qdma_hang_count > 2) { 3794 eth->reset.qdma_hang_count = 0; 3795 ret = true; 3796 } 3797 goto out; 3798 } 3799 3800 /* ADMA sanity checks */ 3801 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3802 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3803 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3804 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3805 3806 if (oq_hang && cdm1_busy && adma_busy) { 3807 if (++eth->reset.adma_hang_count > 2) { 3808 eth->reset.adma_hang_count = 0; 3809 ret = true; 3810 } 3811 goto out; 3812 } 3813 3814 eth->reset.wdma_hang_count = 0; 3815 eth->reset.qdma_hang_count = 0; 3816 eth->reset.adma_hang_count = 0; 3817 out: 3818 eth->reset.wdidx = wdidx; 3819 3820 return ret; 3821 } 3822 3823 static void mtk_hw_reset_monitor_work(struct work_struct *work) 3824 { 3825 struct delayed_work *del_work = to_delayed_work(work); 3826 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3827 reset.monitor_work); 3828 3829 if (test_bit(MTK_RESETTING, ð->state)) 3830 goto out; 3831 3832 /* DMA stuck checks */ 3833 if (mtk_hw_check_dma_hang(eth)) 3834 schedule_work(ð->pending_work); 3835 3836 out: 3837 schedule_delayed_work(ð->reset.monitor_work, 3838 MTK_DMA_MONITOR_TIMEOUT); 3839 } 3840 3841 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3842 { 3843 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3844 ETHSYS_DMA_AG_MAP_PPE; 3845 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3846 int i, val, ret; 3847 3848 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3849 return 0; 3850 3851 if (!reset) { 3852 pm_runtime_enable(eth->dev); 3853 pm_runtime_get_sync(eth->dev); 3854 3855 ret = mtk_clk_enable(eth); 3856 if (ret) 3857 goto err_disable_pm; 3858 } 3859 3860 if (eth->ethsys) 3861 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3862 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3863 3864 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3865 ret = device_reset(eth->dev); 3866 if (ret) { 3867 dev_err(eth->dev, "MAC reset failed!\n"); 3868 goto err_disable_pm; 3869 } 3870 3871 /* set interrupt delays based on current Net DIM sample */ 3872 mtk_dim_rx(ð->rx_dim.work); 3873 mtk_dim_tx(ð->tx_dim.work); 3874 3875 /* disable delay and normal interrupt */ 3876 mtk_tx_irq_disable(eth, ~0); 3877 mtk_rx_irq_disable(eth, ~0); 3878 3879 return 0; 3880 } 3881 3882 msleep(100); 3883 3884 if (reset) 3885 mtk_hw_warm_reset(eth); 3886 else 3887 mtk_hw_reset(eth); 3888 3889 if (mtk_is_netsys_v2_or_greater(eth)) { 3890 /* Set FE to PDMAv2 if necessary */ 3891 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3892 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3893 } 3894 3895 if (eth->pctl) { 3896 /* Set GE2 driving and slew rate */ 3897 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3898 3899 /* set GE2 TDSEL */ 3900 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3901 3902 /* set GE2 TUNE */ 3903 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3904 } 3905 3906 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3907 * up with the more appropriate value when mtk_mac_config call is being 3908 * invoked. 3909 */ 3910 for (i = 0; i < MTK_MAX_DEVS; i++) { 3911 struct net_device *dev = eth->netdev[i]; 3912 3913 if (!dev) 3914 continue; 3915 3916 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3917 mtk_set_mcr_max_rx(netdev_priv(dev), 3918 dev->mtu + MTK_RX_ETH_HLEN); 3919 } 3920 3921 /* Indicates CDM to parse the MTK special tag from CPU 3922 * which also is working out for untag packets. 3923 */ 3924 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3925 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3926 if (mtk_is_netsys_v1(eth)) { 3927 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3928 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 3929 3930 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3931 } 3932 3933 /* set interrupt delays based on current Net DIM sample */ 3934 mtk_dim_rx(ð->rx_dim.work); 3935 mtk_dim_tx(ð->tx_dim.work); 3936 3937 /* disable delay and normal interrupt */ 3938 mtk_tx_irq_disable(eth, ~0); 3939 mtk_rx_irq_disable(eth, ~0); 3940 3941 /* FE int grouping */ 3942 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3943 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3944 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3945 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3946 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3947 3948 if (mtk_is_netsys_v3_or_greater(eth)) { 3949 /* PSE should not drop port1, port8 and port9 packets */ 3950 mtk_w32(eth, 0x00000302, PSE_DROP_CFG); 3951 3952 /* GDM and CDM Threshold */ 3953 mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); 3954 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); 3955 3956 /* Disable GDM1 RX CRC stripping */ 3957 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); 3958 3959 /* PSE GDM3 MIB counter has incorrect hw default values, 3960 * so the driver ought to read clear the values beforehand 3961 * in case ethtool retrieve wrong mib values. 3962 */ 3963 for (i = 0; i < 0x80; i += 0x4) 3964 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); 3965 } else if (!mtk_is_netsys_v1(eth)) { 3966 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 3967 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3968 3969 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 3970 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 3971 3972 /* PSE Free Queue Flow Control */ 3973 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3974 3975 /* PSE config input queue threshold */ 3976 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3977 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3978 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3979 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3980 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3981 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3982 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3983 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3984 3985 /* PSE config output queue threshold */ 3986 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3987 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3988 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3989 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3990 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3991 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3992 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3993 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3994 3995 /* GDM and CDM Threshold */ 3996 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 3997 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 3998 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 3999 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 4000 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 4001 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 4002 } 4003 4004 return 0; 4005 4006 err_disable_pm: 4007 if (!reset) { 4008 pm_runtime_put_sync(eth->dev); 4009 pm_runtime_disable(eth->dev); 4010 } 4011 4012 return ret; 4013 } 4014 4015 static int mtk_hw_deinit(struct mtk_eth *eth) 4016 { 4017 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 4018 return 0; 4019 4020 mtk_clk_disable(eth); 4021 4022 pm_runtime_put_sync(eth->dev); 4023 pm_runtime_disable(eth->dev); 4024 4025 return 0; 4026 } 4027 4028 static void mtk_uninit(struct net_device *dev) 4029 { 4030 struct mtk_mac *mac = netdev_priv(dev); 4031 struct mtk_eth *eth = mac->hw; 4032 4033 phylink_disconnect_phy(mac->phylink); 4034 mtk_tx_irq_disable(eth, ~0); 4035 mtk_rx_irq_disable(eth, ~0); 4036 } 4037 4038 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 4039 { 4040 int length = new_mtu + MTK_RX_ETH_HLEN; 4041 struct mtk_mac *mac = netdev_priv(dev); 4042 struct mtk_eth *eth = mac->hw; 4043 4044 if (rcu_access_pointer(eth->prog) && 4045 length > MTK_PP_MAX_BUF_SIZE) { 4046 netdev_err(dev, "Invalid MTU for XDP mode\n"); 4047 return -EINVAL; 4048 } 4049 4050 mtk_set_mcr_max_rx(mac, length); 4051 dev->mtu = new_mtu; 4052 4053 return 0; 4054 } 4055 4056 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4057 { 4058 struct mtk_mac *mac = netdev_priv(dev); 4059 4060 switch (cmd) { 4061 case SIOCGMIIPHY: 4062 case SIOCGMIIREG: 4063 case SIOCSMIIREG: 4064 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 4065 default: 4066 break; 4067 } 4068 4069 return -EOPNOTSUPP; 4070 } 4071 4072 static void mtk_prepare_for_reset(struct mtk_eth *eth) 4073 { 4074 u32 val; 4075 int i; 4076 4077 /* set FE PPE ports link down */ 4078 for (i = MTK_GMAC1_ID; 4079 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4080 i += 2) { 4081 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4082 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4083 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4084 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4085 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4086 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4087 } 4088 4089 /* adjust PPE configurations to prepare for reset */ 4090 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 4091 mtk_ppe_prepare_reset(eth->ppe[i]); 4092 4093 /* disable NETSYS interrupts */ 4094 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 4095 4096 /* force link down GMAC */ 4097 for (i = 0; i < 2; i++) { 4098 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 4099 mtk_w32(eth, val, MTK_MAC_MCR(i)); 4100 } 4101 } 4102 4103 static void mtk_pending_work(struct work_struct *work) 4104 { 4105 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 4106 unsigned long restart = 0; 4107 u32 val; 4108 int i; 4109 4110 rtnl_lock(); 4111 set_bit(MTK_RESETTING, ð->state); 4112 4113 mtk_prepare_for_reset(eth); 4114 mtk_wed_fe_reset(); 4115 /* Run again reset preliminary configuration in order to avoid any 4116 * possible race during FE reset since it can run releasing RTNL lock. 4117 */ 4118 mtk_prepare_for_reset(eth); 4119 4120 /* stop all devices to make sure that dma is properly shut down */ 4121 for (i = 0; i < MTK_MAX_DEVS; i++) { 4122 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 4123 continue; 4124 4125 mtk_stop(eth->netdev[i]); 4126 __set_bit(i, &restart); 4127 } 4128 4129 usleep_range(15000, 16000); 4130 4131 if (eth->dev->pins) 4132 pinctrl_select_state(eth->dev->pins->p, 4133 eth->dev->pins->default_state); 4134 mtk_hw_init(eth, true); 4135 4136 /* restart DMA and enable IRQs */ 4137 for (i = 0; i < MTK_MAX_DEVS; i++) { 4138 if (!eth->netdev[i] || !test_bit(i, &restart)) 4139 continue; 4140 4141 if (mtk_open(eth->netdev[i])) { 4142 netif_alert(eth, ifup, eth->netdev[i], 4143 "Driver up/down cycle failed\n"); 4144 dev_close(eth->netdev[i]); 4145 } 4146 } 4147 4148 /* set FE PPE ports link up */ 4149 for (i = MTK_GMAC1_ID; 4150 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4151 i += 2) { 4152 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4153 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4154 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4155 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4156 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4157 4158 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4159 } 4160 4161 clear_bit(MTK_RESETTING, ð->state); 4162 4163 mtk_wed_fe_reset_complete(); 4164 4165 rtnl_unlock(); 4166 } 4167 4168 static int mtk_free_dev(struct mtk_eth *eth) 4169 { 4170 int i; 4171 4172 for (i = 0; i < MTK_MAX_DEVS; i++) { 4173 if (!eth->netdev[i]) 4174 continue; 4175 free_netdev(eth->netdev[i]); 4176 } 4177 4178 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4179 if (!eth->dsa_meta[i]) 4180 break; 4181 metadata_dst_free(eth->dsa_meta[i]); 4182 } 4183 4184 return 0; 4185 } 4186 4187 static int mtk_unreg_dev(struct mtk_eth *eth) 4188 { 4189 int i; 4190 4191 for (i = 0; i < MTK_MAX_DEVS; i++) { 4192 struct mtk_mac *mac; 4193 if (!eth->netdev[i]) 4194 continue; 4195 mac = netdev_priv(eth->netdev[i]); 4196 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4197 unregister_netdevice_notifier(&mac->device_notifier); 4198 unregister_netdev(eth->netdev[i]); 4199 } 4200 4201 return 0; 4202 } 4203 4204 static void mtk_sgmii_destroy(struct mtk_eth *eth) 4205 { 4206 int i; 4207 4208 for (i = 0; i < MTK_MAX_DEVS; i++) 4209 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); 4210 } 4211 4212 static int mtk_cleanup(struct mtk_eth *eth) 4213 { 4214 mtk_sgmii_destroy(eth); 4215 mtk_unreg_dev(eth); 4216 mtk_free_dev(eth); 4217 cancel_work_sync(ð->pending_work); 4218 cancel_delayed_work_sync(ð->reset.monitor_work); 4219 4220 return 0; 4221 } 4222 4223 static int mtk_get_link_ksettings(struct net_device *ndev, 4224 struct ethtool_link_ksettings *cmd) 4225 { 4226 struct mtk_mac *mac = netdev_priv(ndev); 4227 4228 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4229 return -EBUSY; 4230 4231 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4232 } 4233 4234 static int mtk_set_link_ksettings(struct net_device *ndev, 4235 const struct ethtool_link_ksettings *cmd) 4236 { 4237 struct mtk_mac *mac = netdev_priv(ndev); 4238 4239 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4240 return -EBUSY; 4241 4242 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4243 } 4244 4245 static void mtk_get_drvinfo(struct net_device *dev, 4246 struct ethtool_drvinfo *info) 4247 { 4248 struct mtk_mac *mac = netdev_priv(dev); 4249 4250 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4251 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4252 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4253 } 4254 4255 static u32 mtk_get_msglevel(struct net_device *dev) 4256 { 4257 struct mtk_mac *mac = netdev_priv(dev); 4258 4259 return mac->hw->msg_enable; 4260 } 4261 4262 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4263 { 4264 struct mtk_mac *mac = netdev_priv(dev); 4265 4266 mac->hw->msg_enable = value; 4267 } 4268 4269 static int mtk_nway_reset(struct net_device *dev) 4270 { 4271 struct mtk_mac *mac = netdev_priv(dev); 4272 4273 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4274 return -EBUSY; 4275 4276 if (!mac->phylink) 4277 return -ENOTSUPP; 4278 4279 return phylink_ethtool_nway_reset(mac->phylink); 4280 } 4281 4282 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4283 { 4284 int i; 4285 4286 switch (stringset) { 4287 case ETH_SS_STATS: { 4288 struct mtk_mac *mac = netdev_priv(dev); 4289 4290 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 4291 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 4292 data += ETH_GSTRING_LEN; 4293 } 4294 if (mtk_page_pool_enabled(mac->hw)) 4295 page_pool_ethtool_stats_get_strings(data); 4296 break; 4297 } 4298 default: 4299 break; 4300 } 4301 } 4302 4303 static int mtk_get_sset_count(struct net_device *dev, int sset) 4304 { 4305 switch (sset) { 4306 case ETH_SS_STATS: { 4307 int count = ARRAY_SIZE(mtk_ethtool_stats); 4308 struct mtk_mac *mac = netdev_priv(dev); 4309 4310 if (mtk_page_pool_enabled(mac->hw)) 4311 count += page_pool_ethtool_stats_get_count(); 4312 return count; 4313 } 4314 default: 4315 return -EOPNOTSUPP; 4316 } 4317 } 4318 4319 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4320 { 4321 struct page_pool_stats stats = {}; 4322 int i; 4323 4324 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4325 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4326 4327 if (!ring->page_pool) 4328 continue; 4329 4330 page_pool_get_stats(ring->page_pool, &stats); 4331 } 4332 page_pool_ethtool_stats_get(data, &stats); 4333 } 4334 4335 static void mtk_get_ethtool_stats(struct net_device *dev, 4336 struct ethtool_stats *stats, u64 *data) 4337 { 4338 struct mtk_mac *mac = netdev_priv(dev); 4339 struct mtk_hw_stats *hwstats = mac->hw_stats; 4340 u64 *data_src, *data_dst; 4341 unsigned int start; 4342 int i; 4343 4344 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4345 return; 4346 4347 if (netif_running(dev) && netif_device_present(dev)) { 4348 if (spin_trylock_bh(&hwstats->stats_lock)) { 4349 mtk_stats_update_mac(mac); 4350 spin_unlock_bh(&hwstats->stats_lock); 4351 } 4352 } 4353 4354 data_src = (u64 *)hwstats; 4355 4356 do { 4357 data_dst = data; 4358 start = u64_stats_fetch_begin(&hwstats->syncp); 4359 4360 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4361 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4362 if (mtk_page_pool_enabled(mac->hw)) 4363 mtk_ethtool_pp_stats(mac->hw, data_dst); 4364 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4365 } 4366 4367 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4368 u32 *rule_locs) 4369 { 4370 int ret = -EOPNOTSUPP; 4371 4372 switch (cmd->cmd) { 4373 case ETHTOOL_GRXRINGS: 4374 if (dev->hw_features & NETIF_F_LRO) { 4375 cmd->data = MTK_MAX_RX_RING_NUM; 4376 ret = 0; 4377 } 4378 break; 4379 case ETHTOOL_GRXCLSRLCNT: 4380 if (dev->hw_features & NETIF_F_LRO) { 4381 struct mtk_mac *mac = netdev_priv(dev); 4382 4383 cmd->rule_cnt = mac->hwlro_ip_cnt; 4384 ret = 0; 4385 } 4386 break; 4387 case ETHTOOL_GRXCLSRULE: 4388 if (dev->hw_features & NETIF_F_LRO) 4389 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4390 break; 4391 case ETHTOOL_GRXCLSRLALL: 4392 if (dev->hw_features & NETIF_F_LRO) 4393 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4394 rule_locs); 4395 break; 4396 default: 4397 break; 4398 } 4399 4400 return ret; 4401 } 4402 4403 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4404 { 4405 int ret = -EOPNOTSUPP; 4406 4407 switch (cmd->cmd) { 4408 case ETHTOOL_SRXCLSRLINS: 4409 if (dev->hw_features & NETIF_F_LRO) 4410 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4411 break; 4412 case ETHTOOL_SRXCLSRLDEL: 4413 if (dev->hw_features & NETIF_F_LRO) 4414 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4415 break; 4416 default: 4417 break; 4418 } 4419 4420 return ret; 4421 } 4422 4423 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4424 struct net_device *sb_dev) 4425 { 4426 struct mtk_mac *mac = netdev_priv(dev); 4427 unsigned int queue = 0; 4428 4429 if (netdev_uses_dsa(dev)) 4430 queue = skb_get_queue_mapping(skb) + 3; 4431 else 4432 queue = mac->id; 4433 4434 if (queue >= dev->num_tx_queues) 4435 queue = 0; 4436 4437 return queue; 4438 } 4439 4440 static const struct ethtool_ops mtk_ethtool_ops = { 4441 .get_link_ksettings = mtk_get_link_ksettings, 4442 .set_link_ksettings = mtk_set_link_ksettings, 4443 .get_drvinfo = mtk_get_drvinfo, 4444 .get_msglevel = mtk_get_msglevel, 4445 .set_msglevel = mtk_set_msglevel, 4446 .nway_reset = mtk_nway_reset, 4447 .get_link = ethtool_op_get_link, 4448 .get_strings = mtk_get_strings, 4449 .get_sset_count = mtk_get_sset_count, 4450 .get_ethtool_stats = mtk_get_ethtool_stats, 4451 .get_rxnfc = mtk_get_rxnfc, 4452 .set_rxnfc = mtk_set_rxnfc, 4453 }; 4454 4455 static const struct net_device_ops mtk_netdev_ops = { 4456 .ndo_uninit = mtk_uninit, 4457 .ndo_open = mtk_open, 4458 .ndo_stop = mtk_stop, 4459 .ndo_start_xmit = mtk_start_xmit, 4460 .ndo_set_mac_address = mtk_set_mac_address, 4461 .ndo_validate_addr = eth_validate_addr, 4462 .ndo_eth_ioctl = mtk_do_ioctl, 4463 .ndo_change_mtu = mtk_change_mtu, 4464 .ndo_tx_timeout = mtk_tx_timeout, 4465 .ndo_get_stats64 = mtk_get_stats64, 4466 .ndo_fix_features = mtk_fix_features, 4467 .ndo_set_features = mtk_set_features, 4468 #ifdef CONFIG_NET_POLL_CONTROLLER 4469 .ndo_poll_controller = mtk_poll_controller, 4470 #endif 4471 .ndo_setup_tc = mtk_eth_setup_tc, 4472 .ndo_bpf = mtk_xdp, 4473 .ndo_xdp_xmit = mtk_xdp_xmit, 4474 .ndo_select_queue = mtk_select_queue, 4475 }; 4476 4477 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4478 { 4479 const __be32 *_id = of_get_property(np, "reg", NULL); 4480 phy_interface_t phy_mode; 4481 struct phylink *phylink; 4482 struct mtk_mac *mac; 4483 int id, err; 4484 int txqs = 1; 4485 u32 val; 4486 4487 if (!_id) { 4488 dev_err(eth->dev, "missing mac id\n"); 4489 return -EINVAL; 4490 } 4491 4492 id = be32_to_cpup(_id); 4493 if (id >= MTK_MAX_DEVS) { 4494 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4495 return -EINVAL; 4496 } 4497 4498 if (eth->netdev[id]) { 4499 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4500 return -EINVAL; 4501 } 4502 4503 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4504 txqs = MTK_QDMA_NUM_QUEUES; 4505 4506 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4507 if (!eth->netdev[id]) { 4508 dev_err(eth->dev, "alloc_etherdev failed\n"); 4509 return -ENOMEM; 4510 } 4511 mac = netdev_priv(eth->netdev[id]); 4512 eth->mac[id] = mac; 4513 mac->id = id; 4514 mac->hw = eth; 4515 mac->of_node = np; 4516 4517 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); 4518 if (err == -EPROBE_DEFER) 4519 return err; 4520 4521 if (err) { 4522 /* If the mac address is invalid, use random mac address */ 4523 eth_hw_addr_random(eth->netdev[id]); 4524 dev_err(eth->dev, "generated random MAC address %pM\n", 4525 eth->netdev[id]->dev_addr); 4526 } 4527 4528 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4529 mac->hwlro_ip_cnt = 0; 4530 4531 mac->hw_stats = devm_kzalloc(eth->dev, 4532 sizeof(*mac->hw_stats), 4533 GFP_KERNEL); 4534 if (!mac->hw_stats) { 4535 dev_err(eth->dev, "failed to allocate counter memory\n"); 4536 err = -ENOMEM; 4537 goto free_netdev; 4538 } 4539 spin_lock_init(&mac->hw_stats->stats_lock); 4540 u64_stats_init(&mac->hw_stats->syncp); 4541 4542 if (mtk_is_netsys_v3_or_greater(eth)) 4543 mac->hw_stats->reg_offset = id * 0x80; 4544 else 4545 mac->hw_stats->reg_offset = id * 0x40; 4546 4547 /* phylink create */ 4548 err = of_get_phy_mode(np, &phy_mode); 4549 if (err) { 4550 dev_err(eth->dev, "incorrect phy-mode\n"); 4551 goto free_netdev; 4552 } 4553 4554 /* mac config is not set */ 4555 mac->interface = PHY_INTERFACE_MODE_NA; 4556 mac->speed = SPEED_UNKNOWN; 4557 4558 mac->phylink_config.dev = ð->netdev[id]->dev; 4559 mac->phylink_config.type = PHYLINK_NETDEV; 4560 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4561 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4562 4563 /* MT7623 gmac0 is now missing its speed-specific PLL configuration 4564 * in its .mac_config method (since state->speed is not valid there. 4565 * Disable support for MII, GMII and RGMII. 4566 */ 4567 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { 4568 __set_bit(PHY_INTERFACE_MODE_MII, 4569 mac->phylink_config.supported_interfaces); 4570 __set_bit(PHY_INTERFACE_MODE_GMII, 4571 mac->phylink_config.supported_interfaces); 4572 4573 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4574 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4575 } 4576 4577 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4578 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4579 mac->phylink_config.supported_interfaces); 4580 4581 /* TRGMII is not permitted on MT7621 if using DDR2 */ 4582 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 4583 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 4584 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 4585 if (val & SYSCFG_DRAM_TYPE_DDR2) 4586 __clear_bit(PHY_INTERFACE_MODE_TRGMII, 4587 mac->phylink_config.supported_interfaces); 4588 } 4589 4590 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4591 __set_bit(PHY_INTERFACE_MODE_SGMII, 4592 mac->phylink_config.supported_interfaces); 4593 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4594 mac->phylink_config.supported_interfaces); 4595 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4596 mac->phylink_config.supported_interfaces); 4597 } 4598 4599 if (mtk_is_netsys_v3_or_greater(mac->hw) && 4600 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && 4601 id == MTK_GMAC1_ID) { 4602 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 4603 MAC_SYM_PAUSE | 4604 MAC_10000FD; 4605 phy_interface_zero(mac->phylink_config.supported_interfaces); 4606 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 4607 mac->phylink_config.supported_interfaces); 4608 } 4609 4610 phylink = phylink_create(&mac->phylink_config, 4611 of_fwnode_handle(mac->of_node), 4612 phy_mode, &mtk_phylink_ops); 4613 if (IS_ERR(phylink)) { 4614 err = PTR_ERR(phylink); 4615 goto free_netdev; 4616 } 4617 4618 mac->phylink = phylink; 4619 4620 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4621 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4622 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4623 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4624 4625 eth->netdev[id]->hw_features = eth->soc->hw_features; 4626 if (eth->hwlro) 4627 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4628 4629 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4630 ~NETIF_F_HW_VLAN_CTAG_TX; 4631 eth->netdev[id]->features |= eth->soc->hw_features; 4632 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4633 4634 eth->netdev[id]->irq = eth->irq[0]; 4635 eth->netdev[id]->dev.of_node = np; 4636 4637 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4638 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4639 else 4640 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4641 4642 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4643 mac->device_notifier.notifier_call = mtk_device_event; 4644 register_netdevice_notifier(&mac->device_notifier); 4645 } 4646 4647 if (mtk_page_pool_enabled(eth)) 4648 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4649 NETDEV_XDP_ACT_REDIRECT | 4650 NETDEV_XDP_ACT_NDO_XMIT | 4651 NETDEV_XDP_ACT_NDO_XMIT_SG; 4652 4653 return 0; 4654 4655 free_netdev: 4656 free_netdev(eth->netdev[id]); 4657 return err; 4658 } 4659 4660 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4661 { 4662 struct net_device *dev, *tmp; 4663 LIST_HEAD(dev_list); 4664 int i; 4665 4666 rtnl_lock(); 4667 4668 for (i = 0; i < MTK_MAX_DEVS; i++) { 4669 dev = eth->netdev[i]; 4670 4671 if (!dev || !(dev->flags & IFF_UP)) 4672 continue; 4673 4674 list_add_tail(&dev->close_list, &dev_list); 4675 } 4676 4677 dev_close_many(&dev_list, false); 4678 4679 eth->dma_dev = dma_dev; 4680 4681 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4682 list_del_init(&dev->close_list); 4683 dev_open(dev, NULL); 4684 } 4685 4686 rtnl_unlock(); 4687 } 4688 4689 static int mtk_sgmii_init(struct mtk_eth *eth) 4690 { 4691 struct device_node *np; 4692 struct regmap *regmap; 4693 u32 flags; 4694 int i; 4695 4696 for (i = 0; i < MTK_MAX_DEVS; i++) { 4697 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); 4698 if (!np) 4699 break; 4700 4701 regmap = syscon_node_to_regmap(np); 4702 flags = 0; 4703 if (of_property_read_bool(np, "mediatek,pnswap")) 4704 flags |= MTK_SGMII_FLAG_PN_SWAP; 4705 4706 of_node_put(np); 4707 4708 if (IS_ERR(regmap)) 4709 return PTR_ERR(regmap); 4710 4711 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, 4712 eth->soc->ana_rgc3, 4713 flags); 4714 } 4715 4716 return 0; 4717 } 4718 4719 static int mtk_probe(struct platform_device *pdev) 4720 { 4721 struct resource *res = NULL, *res_sram; 4722 struct device_node *mac_np; 4723 struct mtk_eth *eth; 4724 int err, i; 4725 4726 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4727 if (!eth) 4728 return -ENOMEM; 4729 4730 eth->soc = of_device_get_match_data(&pdev->dev); 4731 4732 eth->dev = &pdev->dev; 4733 eth->dma_dev = &pdev->dev; 4734 eth->base = devm_platform_ioremap_resource(pdev, 0); 4735 if (IS_ERR(eth->base)) 4736 return PTR_ERR(eth->base); 4737 4738 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4739 eth->ip_align = NET_IP_ALIGN; 4740 4741 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4742 /* SRAM is actual memory and supports transparent access just like DRAM. 4743 * Hence we don't require __iomem being set and don't need to use accessor 4744 * functions to read from or write to SRAM. 4745 */ 4746 if (mtk_is_netsys_v3_or_greater(eth)) { 4747 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1); 4748 if (IS_ERR(eth->sram_base)) 4749 return PTR_ERR(eth->sram_base); 4750 } else { 4751 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; 4752 } 4753 } 4754 4755 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { 4756 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); 4757 if (err) { 4758 dev_err(&pdev->dev, "Wrong DMA config\n"); 4759 return -EINVAL; 4760 } 4761 } 4762 4763 spin_lock_init(ð->page_lock); 4764 spin_lock_init(ð->tx_irq_lock); 4765 spin_lock_init(ð->rx_irq_lock); 4766 spin_lock_init(ð->dim_lock); 4767 4768 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4769 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4770 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4771 4772 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4773 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4774 4775 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4776 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4777 "mediatek,ethsys"); 4778 if (IS_ERR(eth->ethsys)) { 4779 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4780 return PTR_ERR(eth->ethsys); 4781 } 4782 } 4783 4784 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4785 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4786 "mediatek,infracfg"); 4787 if (IS_ERR(eth->infra)) { 4788 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4789 return PTR_ERR(eth->infra); 4790 } 4791 } 4792 4793 if (of_dma_is_coherent(pdev->dev.of_node)) { 4794 struct regmap *cci; 4795 4796 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4797 "cci-control-port"); 4798 /* enable CPU/bus coherency */ 4799 if (!IS_ERR(cci)) 4800 regmap_write(cci, 0, 3); 4801 } 4802 4803 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4804 err = mtk_sgmii_init(eth); 4805 4806 if (err) 4807 return err; 4808 } 4809 4810 if (eth->soc->required_pctl) { 4811 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4812 "mediatek,pctl"); 4813 if (IS_ERR(eth->pctl)) { 4814 dev_err(&pdev->dev, "no pctl regmap found\n"); 4815 err = PTR_ERR(eth->pctl); 4816 goto err_destroy_sgmii; 4817 } 4818 } 4819 4820 if (mtk_is_netsys_v2_or_greater(eth)) { 4821 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4822 if (!res) { 4823 err = -EINVAL; 4824 goto err_destroy_sgmii; 4825 } 4826 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4827 if (mtk_is_netsys_v3_or_greater(eth)) { 4828 res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1); 4829 if (!res_sram) { 4830 err = -EINVAL; 4831 goto err_destroy_sgmii; 4832 } 4833 eth->phy_scratch_ring = res_sram->start; 4834 } else { 4835 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; 4836 } 4837 } 4838 } 4839 4840 if (eth->soc->offload_version) { 4841 for (i = 0;; i++) { 4842 struct device_node *np; 4843 phys_addr_t wdma_phy; 4844 u32 wdma_base; 4845 4846 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4847 break; 4848 4849 np = of_parse_phandle(pdev->dev.of_node, 4850 "mediatek,wed", i); 4851 if (!np) 4852 break; 4853 4854 wdma_base = eth->soc->reg_map->wdma_base[i]; 4855 wdma_phy = res ? res->start + wdma_base : 0; 4856 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4857 wdma_phy, i); 4858 } 4859 } 4860 4861 for (i = 0; i < 3; i++) { 4862 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4863 eth->irq[i] = eth->irq[0]; 4864 else 4865 eth->irq[i] = platform_get_irq(pdev, i); 4866 if (eth->irq[i] < 0) { 4867 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4868 err = -ENXIO; 4869 goto err_wed_exit; 4870 } 4871 } 4872 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4873 eth->clks[i] = devm_clk_get(eth->dev, 4874 mtk_clks_source_name[i]); 4875 if (IS_ERR(eth->clks[i])) { 4876 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4877 err = -EPROBE_DEFER; 4878 goto err_wed_exit; 4879 } 4880 if (eth->soc->required_clks & BIT(i)) { 4881 dev_err(&pdev->dev, "clock %s not found\n", 4882 mtk_clks_source_name[i]); 4883 err = -EINVAL; 4884 goto err_wed_exit; 4885 } 4886 eth->clks[i] = NULL; 4887 } 4888 } 4889 4890 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4891 INIT_WORK(ð->pending_work, mtk_pending_work); 4892 4893 err = mtk_hw_init(eth, false); 4894 if (err) 4895 goto err_wed_exit; 4896 4897 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4898 4899 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4900 if (!of_device_is_compatible(mac_np, 4901 "mediatek,eth-mac")) 4902 continue; 4903 4904 if (!of_device_is_available(mac_np)) 4905 continue; 4906 4907 err = mtk_add_mac(eth, mac_np); 4908 if (err) { 4909 of_node_put(mac_np); 4910 goto err_deinit_hw; 4911 } 4912 } 4913 4914 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4915 err = devm_request_irq(eth->dev, eth->irq[0], 4916 mtk_handle_irq, 0, 4917 dev_name(eth->dev), eth); 4918 } else { 4919 err = devm_request_irq(eth->dev, eth->irq[1], 4920 mtk_handle_irq_tx, 0, 4921 dev_name(eth->dev), eth); 4922 if (err) 4923 goto err_free_dev; 4924 4925 err = devm_request_irq(eth->dev, eth->irq[2], 4926 mtk_handle_irq_rx, 0, 4927 dev_name(eth->dev), eth); 4928 } 4929 if (err) 4930 goto err_free_dev; 4931 4932 /* No MT7628/88 support yet */ 4933 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4934 err = mtk_mdio_init(eth); 4935 if (err) 4936 goto err_free_dev; 4937 } 4938 4939 if (eth->soc->offload_version) { 4940 u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1; 4941 4942 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4943 for (i = 0; i < num_ppe; i++) { 4944 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; 4945 4946 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); 4947 4948 if (!eth->ppe[i]) { 4949 err = -ENOMEM; 4950 goto err_deinit_ppe; 4951 } 4952 } 4953 4954 err = mtk_eth_offload_init(eth); 4955 if (err) 4956 goto err_deinit_ppe; 4957 } 4958 4959 for (i = 0; i < MTK_MAX_DEVS; i++) { 4960 if (!eth->netdev[i]) 4961 continue; 4962 4963 err = register_netdev(eth->netdev[i]); 4964 if (err) { 4965 dev_err(eth->dev, "error bringing up device\n"); 4966 goto err_deinit_ppe; 4967 } else 4968 netif_info(eth, probe, eth->netdev[i], 4969 "mediatek frame engine at 0x%08lx, irq %d\n", 4970 eth->netdev[i]->base_addr, eth->irq[0]); 4971 } 4972 4973 /* we run 2 devices on the same DMA ring so we need a dummy device 4974 * for NAPI to work 4975 */ 4976 init_dummy_netdev(ð->dummy_dev); 4977 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); 4978 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); 4979 4980 platform_set_drvdata(pdev, eth); 4981 schedule_delayed_work(ð->reset.monitor_work, 4982 MTK_DMA_MONITOR_TIMEOUT); 4983 4984 return 0; 4985 4986 err_deinit_ppe: 4987 mtk_ppe_deinit(eth); 4988 mtk_mdio_cleanup(eth); 4989 err_free_dev: 4990 mtk_free_dev(eth); 4991 err_deinit_hw: 4992 mtk_hw_deinit(eth); 4993 err_wed_exit: 4994 mtk_wed_exit(); 4995 err_destroy_sgmii: 4996 mtk_sgmii_destroy(eth); 4997 4998 return err; 4999 } 5000 5001 static int mtk_remove(struct platform_device *pdev) 5002 { 5003 struct mtk_eth *eth = platform_get_drvdata(pdev); 5004 struct mtk_mac *mac; 5005 int i; 5006 5007 /* stop all devices to make sure that dma is properly shut down */ 5008 for (i = 0; i < MTK_MAX_DEVS; i++) { 5009 if (!eth->netdev[i]) 5010 continue; 5011 mtk_stop(eth->netdev[i]); 5012 mac = netdev_priv(eth->netdev[i]); 5013 phylink_disconnect_phy(mac->phylink); 5014 } 5015 5016 mtk_wed_exit(); 5017 mtk_hw_deinit(eth); 5018 5019 netif_napi_del(ð->tx_napi); 5020 netif_napi_del(ð->rx_napi); 5021 mtk_cleanup(eth); 5022 mtk_mdio_cleanup(eth); 5023 5024 return 0; 5025 } 5026 5027 static const struct mtk_soc_data mt2701_data = { 5028 .reg_map = &mtk_reg_map, 5029 .caps = MT7623_CAPS | MTK_HWLRO, 5030 .hw_features = MTK_HW_FEATURES, 5031 .required_clks = MT7623_CLKS_BITMAP, 5032 .required_pctl = true, 5033 .version = 1, 5034 .txrx = { 5035 .txd_size = sizeof(struct mtk_tx_dma), 5036 .rxd_size = sizeof(struct mtk_rx_dma), 5037 .rx_irq_done_mask = MTK_RX_DONE_INT, 5038 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5039 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5040 .dma_len_offset = 16, 5041 }, 5042 }; 5043 5044 static const struct mtk_soc_data mt7621_data = { 5045 .reg_map = &mtk_reg_map, 5046 .caps = MT7621_CAPS, 5047 .hw_features = MTK_HW_FEATURES, 5048 .required_clks = MT7621_CLKS_BITMAP, 5049 .required_pctl = false, 5050 .version = 1, 5051 .offload_version = 1, 5052 .hash_offset = 2, 5053 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5054 .txrx = { 5055 .txd_size = sizeof(struct mtk_tx_dma), 5056 .rxd_size = sizeof(struct mtk_rx_dma), 5057 .rx_irq_done_mask = MTK_RX_DONE_INT, 5058 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5059 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5060 .dma_len_offset = 16, 5061 }, 5062 }; 5063 5064 static const struct mtk_soc_data mt7622_data = { 5065 .reg_map = &mtk_reg_map, 5066 .ana_rgc3 = 0x2028, 5067 .caps = MT7622_CAPS | MTK_HWLRO, 5068 .hw_features = MTK_HW_FEATURES, 5069 .required_clks = MT7622_CLKS_BITMAP, 5070 .required_pctl = false, 5071 .version = 1, 5072 .offload_version = 2, 5073 .hash_offset = 2, 5074 .has_accounting = true, 5075 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5076 .txrx = { 5077 .txd_size = sizeof(struct mtk_tx_dma), 5078 .rxd_size = sizeof(struct mtk_rx_dma), 5079 .rx_irq_done_mask = MTK_RX_DONE_INT, 5080 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5081 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5082 .dma_len_offset = 16, 5083 }, 5084 }; 5085 5086 static const struct mtk_soc_data mt7623_data = { 5087 .reg_map = &mtk_reg_map, 5088 .caps = MT7623_CAPS | MTK_HWLRO, 5089 .hw_features = MTK_HW_FEATURES, 5090 .required_clks = MT7623_CLKS_BITMAP, 5091 .required_pctl = true, 5092 .version = 1, 5093 .offload_version = 1, 5094 .hash_offset = 2, 5095 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5096 .disable_pll_modes = true, 5097 .txrx = { 5098 .txd_size = sizeof(struct mtk_tx_dma), 5099 .rxd_size = sizeof(struct mtk_rx_dma), 5100 .rx_irq_done_mask = MTK_RX_DONE_INT, 5101 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5102 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5103 .dma_len_offset = 16, 5104 }, 5105 }; 5106 5107 static const struct mtk_soc_data mt7629_data = { 5108 .reg_map = &mtk_reg_map, 5109 .ana_rgc3 = 0x128, 5110 .caps = MT7629_CAPS | MTK_HWLRO, 5111 .hw_features = MTK_HW_FEATURES, 5112 .required_clks = MT7629_CLKS_BITMAP, 5113 .required_pctl = false, 5114 .has_accounting = true, 5115 .version = 1, 5116 .txrx = { 5117 .txd_size = sizeof(struct mtk_tx_dma), 5118 .rxd_size = sizeof(struct mtk_rx_dma), 5119 .rx_irq_done_mask = MTK_RX_DONE_INT, 5120 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5121 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5122 .dma_len_offset = 16, 5123 }, 5124 }; 5125 5126 static const struct mtk_soc_data mt7981_data = { 5127 .reg_map = &mt7986_reg_map, 5128 .ana_rgc3 = 0x128, 5129 .caps = MT7981_CAPS, 5130 .hw_features = MTK_HW_FEATURES, 5131 .required_clks = MT7981_CLKS_BITMAP, 5132 .required_pctl = false, 5133 .version = 2, 5134 .offload_version = 2, 5135 .hash_offset = 4, 5136 .has_accounting = true, 5137 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5138 .txrx = { 5139 .txd_size = sizeof(struct mtk_tx_dma_v2), 5140 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5141 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5142 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5143 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5144 .dma_len_offset = 8, 5145 }, 5146 }; 5147 5148 static const struct mtk_soc_data mt7986_data = { 5149 .reg_map = &mt7986_reg_map, 5150 .ana_rgc3 = 0x128, 5151 .caps = MT7986_CAPS, 5152 .hw_features = MTK_HW_FEATURES, 5153 .required_clks = MT7986_CLKS_BITMAP, 5154 .required_pctl = false, 5155 .version = 2, 5156 .offload_version = 2, 5157 .hash_offset = 4, 5158 .has_accounting = true, 5159 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5160 .txrx = { 5161 .txd_size = sizeof(struct mtk_tx_dma_v2), 5162 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5163 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5164 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5165 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5166 .dma_len_offset = 8, 5167 }, 5168 }; 5169 5170 static const struct mtk_soc_data mt7988_data = { 5171 .reg_map = &mt7988_reg_map, 5172 .ana_rgc3 = 0x128, 5173 .caps = MT7988_CAPS, 5174 .hw_features = MTK_HW_FEATURES, 5175 .required_clks = MT7988_CLKS_BITMAP, 5176 .required_pctl = false, 5177 .version = 3, 5178 .offload_version = 2, 5179 .hash_offset = 4, 5180 .has_accounting = true, 5181 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, 5182 .txrx = { 5183 .txd_size = sizeof(struct mtk_tx_dma_v2), 5184 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5185 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5186 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5187 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5188 .dma_len_offset = 8, 5189 }, 5190 }; 5191 5192 static const struct mtk_soc_data rt5350_data = { 5193 .reg_map = &mt7628_reg_map, 5194 .caps = MT7628_CAPS, 5195 .hw_features = MTK_HW_FEATURES_MT7628, 5196 .required_clks = MT7628_CLKS_BITMAP, 5197 .required_pctl = false, 5198 .version = 1, 5199 .txrx = { 5200 .txd_size = sizeof(struct mtk_tx_dma), 5201 .rxd_size = sizeof(struct mtk_rx_dma), 5202 .rx_irq_done_mask = MTK_RX_DONE_INT, 5203 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 5204 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5205 .dma_len_offset = 16, 5206 }, 5207 }; 5208 5209 const struct of_device_id of_mtk_match[] = { 5210 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, 5211 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, 5212 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, 5213 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, 5214 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, 5215 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, 5216 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, 5217 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, 5218 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, 5219 {}, 5220 }; 5221 MODULE_DEVICE_TABLE(of, of_mtk_match); 5222 5223 static struct platform_driver mtk_driver = { 5224 .probe = mtk_probe, 5225 .remove = mtk_remove, 5226 .driver = { 5227 .name = "mtk_soc_eth", 5228 .of_match_table = of_mtk_match, 5229 }, 5230 }; 5231 5232 module_platform_driver(mtk_driver); 5233 5234 MODULE_LICENSE("GPL"); 5235 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 5236 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 5237