1 /* 2 * New driver for Marvell Yukon 2 chipset. 3 * Based on earlier sk98lin, and skge driver. 4 * 5 * This driver intentionally does not support all the features 6 * of the original driver such as link fail-over and link management because 7 * those should be done at higher levels. 8 * 9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/crc32.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/pci.h> 35 #include <linux/interrupt.h> 36 #include <linux/ip.h> 37 #include <linux/slab.h> 38 #include <net/ip.h> 39 #include <linux/tcp.h> 40 #include <linux/in.h> 41 #include <linux/delay.h> 42 #include <linux/workqueue.h> 43 #include <linux/if_vlan.h> 44 #include <linux/prefetch.h> 45 #include <linux/debugfs.h> 46 #include <linux/mii.h> 47 48 #include <asm/irq.h> 49 50 #include "sky2.h" 51 52 #define DRV_NAME "sky2" 53 #define DRV_VERSION "1.29" 54 55 /* 56 * The Yukon II chipset takes 64 bit command blocks (called list elements) 57 * that are organized into three (receive, transmit, status) different rings 58 * similar to Tigon3. 59 */ 60 61 #define RX_LE_SIZE 1024 62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) 63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) 64 #define RX_DEF_PENDING RX_MAX_PENDING 65 66 /* This is the worst case number of transmit list elements for a single skb: 67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */ 68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) 69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) 70 #define TX_MAX_PENDING 1024 71 #define TX_DEF_PENDING 127 72 73 #define TX_WATCHDOG (5 * HZ) 74 #define NAPI_WEIGHT 64 75 #define PHY_RETRIES 1000 76 77 #define SKY2_EEPROM_MAGIC 0x9955aabb 78 79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) 80 81 static const u32 default_msg = 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 85 86 static int debug = -1; /* defaults above */ 87 module_param(debug, int, 0); 88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 89 90 static int copybreak __read_mostly = 128; 91 module_param(copybreak, int, 0); 92 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 93 94 static int disable_msi = 0; 95 module_param(disable_msi, int, 0); 96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 97 98 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = { 99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ 102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ 106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ 115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ 140 { 0 } 141 }; 142 143 MODULE_DEVICE_TABLE(pci, sky2_id_table); 144 145 /* Avoid conditionals by using array */ 146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; 147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 149 150 static void sky2_set_multicast(struct net_device *dev); 151 static irqreturn_t sky2_intr(int irq, void *dev_id); 152 153 /* Access to PHY via serial interconnect */ 154 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) 155 { 156 int i; 157 158 gma_write16(hw, port, GM_SMI_DATA, val); 159 gma_write16(hw, port, GM_SMI_CTRL, 160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 161 162 for (i = 0; i < PHY_RETRIES; i++) { 163 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 164 if (ctrl == 0xffff) 165 goto io_error; 166 167 if (!(ctrl & GM_SMI_CT_BUSY)) 168 return 0; 169 170 udelay(10); 171 } 172 173 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); 174 return -ETIMEDOUT; 175 176 io_error: 177 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 178 return -EIO; 179 } 180 181 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) 182 { 183 int i; 184 185 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 186 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 187 188 for (i = 0; i < PHY_RETRIES; i++) { 189 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 190 if (ctrl == 0xffff) 191 goto io_error; 192 193 if (ctrl & GM_SMI_CT_RD_VAL) { 194 *val = gma_read16(hw, port, GM_SMI_DATA); 195 return 0; 196 } 197 198 udelay(10); 199 } 200 201 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); 202 return -ETIMEDOUT; 203 io_error: 204 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 205 return -EIO; 206 } 207 208 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) 209 { 210 u16 v; 211 __gm_phy_read(hw, port, reg, &v); 212 return v; 213 } 214 215 216 static void sky2_power_on(struct sky2_hw *hw) 217 { 218 /* switch power to VCC (WA for VAUX problem) */ 219 sky2_write8(hw, B0_POWER_CTRL, 220 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 221 222 /* disable Core Clock Division, */ 223 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 224 225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 226 /* enable bits are inverted */ 227 sky2_write8(hw, B2_Y2_CLK_GATE, 228 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 229 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 230 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 231 else 232 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 233 234 if (hw->flags & SKY2_HW_ADV_POWER_CTL) { 235 u32 reg; 236 237 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 238 239 reg = sky2_pci_read32(hw, PCI_DEV_REG4); 240 /* set all bits to 0 except bits 15..12 and 8 */ 241 reg &= P_ASPM_CONTROL_MSK; 242 sky2_pci_write32(hw, PCI_DEV_REG4, reg); 243 244 reg = sky2_pci_read32(hw, PCI_DEV_REG5); 245 /* set all bits to 0 except bits 28 & 27 */ 246 reg &= P_CTL_TIM_VMAIN_AV_MSK; 247 sky2_pci_write32(hw, PCI_DEV_REG5, reg); 248 249 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); 250 251 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); 252 253 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ 254 reg = sky2_read32(hw, B2_GP_IO); 255 reg |= GLB_GPIO_STAT_RACE_DIS; 256 sky2_write32(hw, B2_GP_IO, reg); 257 258 sky2_read32(hw, B2_GP_IO); 259 } 260 261 /* Turn on "driver loaded" LED */ 262 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); 263 } 264 265 static void sky2_power_aux(struct sky2_hw *hw) 266 { 267 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 268 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 269 else 270 /* enable bits are inverted */ 271 sky2_write8(hw, B2_Y2_CLK_GATE, 272 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 273 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 274 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 275 276 /* switch power to VAUX if supported and PME from D3cold */ 277 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && 278 pci_pme_capable(hw->pdev, PCI_D3cold)) 279 sky2_write8(hw, B0_POWER_CTRL, 280 (PC_VAUX_ENA | PC_VCC_ENA | 281 PC_VAUX_ON | PC_VCC_OFF)); 282 283 /* turn off "driver loaded LED" */ 284 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); 285 } 286 287 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) 288 { 289 u16 reg; 290 291 /* disable all GMAC IRQ's */ 292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 293 294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 295 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 296 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 297 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 298 299 reg = gma_read16(hw, port, GM_RX_CTRL); 300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 301 gma_write16(hw, port, GM_RX_CTRL, reg); 302 } 303 304 /* flow control to advertise bits */ 305 static const u16 copper_fc_adv[] = { 306 [FC_NONE] = 0, 307 [FC_TX] = PHY_M_AN_ASP, 308 [FC_RX] = PHY_M_AN_PC, 309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, 310 }; 311 312 /* flow control to advertise bits when using 1000BaseX */ 313 static const u16 fiber_fc_adv[] = { 314 [FC_NONE] = PHY_M_P_NO_PAUSE_X, 315 [FC_TX] = PHY_M_P_ASYM_MD_X, 316 [FC_RX] = PHY_M_P_SYM_MD_X, 317 [FC_BOTH] = PHY_M_P_BOTH_MD_X, 318 }; 319 320 /* flow control to GMA disable bits */ 321 static const u16 gm_fc_disable[] = { 322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, 323 [FC_TX] = GM_GPCR_FC_RX_DIS, 324 [FC_RX] = GM_GPCR_FC_TX_DIS, 325 [FC_BOTH] = 0, 326 }; 327 328 329 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 330 { 331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; 333 334 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 335 !(hw->flags & SKY2_HW_NEWER_PHY)) { 336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 337 338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 339 PHY_M_EC_MAC_S_MSK); 340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 341 342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ 343 if (hw->chip_id == CHIP_ID_YUKON_EC) 344 /* set downshift counter to 3x and enable downshift */ 345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 346 else 347 /* set master & slave downshift counter to 1x */ 348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 349 350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 351 } 352 353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 354 if (sky2_is_copper(hw)) { 355 if (!(hw->flags & SKY2_HW_GIGABIT)) { 356 /* enable automatic crossover */ 357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 358 359 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 360 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 361 u16 spec; 362 363 /* Enable Class A driver for FE+ A0 */ 364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); 365 spec |= PHY_M_FESC_SEL_CL_A; 366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); 367 } 368 } else { 369 /* disable energy detect */ 370 ctrl &= ~PHY_M_PC_EN_DET_MSK; 371 372 /* enable automatic crossover */ 373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 374 375 /* downshift on PHY 88E1112 and 88E1149 is changed */ 376 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 377 (hw->flags & SKY2_HW_NEWER_PHY)) { 378 /* set downshift counter to 3x and enable downshift */ 379 ctrl &= ~PHY_M_PC_DSC_MSK; 380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 381 } 382 } 383 } else { 384 /* workaround for deviation #4.88 (CRC errors) */ 385 /* disable Automatic Crossover */ 386 387 ctrl &= ~PHY_M_PC_MDIX_MSK; 388 } 389 390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 391 392 /* special setup for PHY 88E1112 Fiber */ 393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { 394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 395 396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 399 ctrl &= ~PHY_M_MAC_MD_MSK; 400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 402 403 if (hw->pmd_type == 'P') { 404 /* select page 1 to access Fiber registers */ 405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 406 407 /* for SFP-module set SIGDET polarity to low */ 408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 409 ctrl |= PHY_M_FIB_SIGD_POL; 410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 411 } 412 413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 414 } 415 416 ctrl = PHY_CT_RESET; 417 ct1000 = 0; 418 adv = PHY_AN_CSMA; 419 reg = 0; 420 421 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { 422 if (sky2_is_copper(hw)) { 423 if (sky2->advertising & ADVERTISED_1000baseT_Full) 424 ct1000 |= PHY_M_1000C_AFD; 425 if (sky2->advertising & ADVERTISED_1000baseT_Half) 426 ct1000 |= PHY_M_1000C_AHD; 427 if (sky2->advertising & ADVERTISED_100baseT_Full) 428 adv |= PHY_M_AN_100_FD; 429 if (sky2->advertising & ADVERTISED_100baseT_Half) 430 adv |= PHY_M_AN_100_HD; 431 if (sky2->advertising & ADVERTISED_10baseT_Full) 432 adv |= PHY_M_AN_10_FD; 433 if (sky2->advertising & ADVERTISED_10baseT_Half) 434 adv |= PHY_M_AN_10_HD; 435 436 } else { /* special defines for FIBER (88E1040S only) */ 437 if (sky2->advertising & ADVERTISED_1000baseT_Full) 438 adv |= PHY_M_AN_1000X_AFD; 439 if (sky2->advertising & ADVERTISED_1000baseT_Half) 440 adv |= PHY_M_AN_1000X_AHD; 441 } 442 443 /* Restart Auto-negotiation */ 444 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 445 } else { 446 /* forced speed/duplex settings */ 447 ct1000 = PHY_M_1000C_MSE; 448 449 /* Disable auto update for duplex flow control and duplex */ 450 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; 451 452 switch (sky2->speed) { 453 case SPEED_1000: 454 ctrl |= PHY_CT_SP1000; 455 reg |= GM_GPCR_SPEED_1000; 456 break; 457 case SPEED_100: 458 ctrl |= PHY_CT_SP100; 459 reg |= GM_GPCR_SPEED_100; 460 break; 461 } 462 463 if (sky2->duplex == DUPLEX_FULL) { 464 reg |= GM_GPCR_DUP_FULL; 465 ctrl |= PHY_CT_DUP_MD; 466 } else if (sky2->speed < SPEED_1000) 467 sky2->flow_mode = FC_NONE; 468 } 469 470 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { 471 if (sky2_is_copper(hw)) 472 adv |= copper_fc_adv[sky2->flow_mode]; 473 else 474 adv |= fiber_fc_adv[sky2->flow_mode]; 475 } else { 476 reg |= GM_GPCR_AU_FCT_DIS; 477 reg |= gm_fc_disable[sky2->flow_mode]; 478 479 /* Forward pause packets to GMAC? */ 480 if (sky2->flow_mode & FC_RX) 481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 482 else 483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 484 } 485 486 gma_write16(hw, port, GM_GP_CTRL, reg); 487 488 if (hw->flags & SKY2_HW_GIGABIT) 489 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 490 491 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 492 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 493 494 /* Setup Phy LED's */ 495 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 496 ledover = 0; 497 498 switch (hw->chip_id) { 499 case CHIP_ID_YUKON_FE: 500 /* on 88E3082 these bits are at 11..9 (shifted left) */ 501 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 502 503 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 504 505 /* delete ACT LED control bits */ 506 ctrl &= ~PHY_M_FELP_LED1_MSK; 507 /* change ACT LED control to blink mode */ 508 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 509 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 510 break; 511 512 case CHIP_ID_YUKON_FE_P: 513 /* Enable Link Partner Next Page */ 514 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 515 ctrl |= PHY_M_PC_ENA_LIP_NP; 516 517 /* disable Energy Detect and enable scrambler */ 518 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); 519 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 520 521 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ 522 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | 523 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | 524 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); 525 526 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 527 break; 528 529 case CHIP_ID_YUKON_XL: 530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 531 532 /* select page 3 to access LED control register */ 533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 534 535 /* set LED Function Control register */ 536 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 537 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 538 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 539 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 540 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 541 542 /* set Polarity Control register */ 543 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 544 (PHY_M_POLC_LS1_P_MIX(4) | 545 PHY_M_POLC_IS0_P_MIX(4) | 546 PHY_M_POLC_LOS_CTRL(2) | 547 PHY_M_POLC_INIT_CTRL(2) | 548 PHY_M_POLC_STA1_CTRL(2) | 549 PHY_M_POLC_STA0_CTRL(2))); 550 551 /* restore page register */ 552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 553 break; 554 555 case CHIP_ID_YUKON_EC_U: 556 case CHIP_ID_YUKON_EX: 557 case CHIP_ID_YUKON_SUPR: 558 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 559 560 /* select page 3 to access LED control register */ 561 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 562 563 /* set LED Function Control register */ 564 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 565 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 566 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 567 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 568 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 569 570 /* set Blink Rate in LED Timer Control Register */ 571 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 572 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 573 /* restore page register */ 574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 575 break; 576 577 default: 578 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 579 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 580 581 /* turn off the Rx LED (LED_RX) */ 582 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 583 } 584 585 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { 586 /* apply fixes in PHY AFE */ 587 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 588 589 /* increase differential signal amplitude in 10BASE-T */ 590 gm_phy_write(hw, port, 0x18, 0xaa99); 591 gm_phy_write(hw, port, 0x17, 0x2011); 592 593 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 594 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 595 gm_phy_write(hw, port, 0x18, 0xa204); 596 gm_phy_write(hw, port, 0x17, 0x2002); 597 } 598 599 /* set page register to 0 */ 600 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 601 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && 602 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 603 /* apply workaround for integrated resistors calibration */ 604 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 605 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 606 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 607 /* apply fixes in PHY AFE */ 608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 609 610 /* apply RDAC termination workaround */ 611 gm_phy_write(hw, port, 24, 0x2800); 612 gm_phy_write(hw, port, 23, 0x2001); 613 614 /* set page register back to 0 */ 615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 616 } else if (hw->chip_id != CHIP_ID_YUKON_EX && 617 hw->chip_id < CHIP_ID_YUKON_SUPR) { 618 /* no effect on Yukon-XL */ 619 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 620 621 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || 622 sky2->speed == SPEED_100) { 623 /* turn on 100 Mbps LED (LED_LINK100) */ 624 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 625 } 626 627 if (ledover) 628 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 629 630 } else if (hw->chip_id == CHIP_ID_YUKON_PRM && 631 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { 632 int i; 633 /* This a phy register setup workaround copied from vendor driver. */ 634 static const struct { 635 u16 reg, val; 636 } eee_afe[] = { 637 { 0x156, 0x58ce }, 638 { 0x153, 0x99eb }, 639 { 0x141, 0x8064 }, 640 /* { 0x155, 0x130b },*/ 641 { 0x000, 0x0000 }, 642 { 0x151, 0x8433 }, 643 { 0x14b, 0x8c44 }, 644 { 0x14c, 0x0f90 }, 645 { 0x14f, 0x39aa }, 646 /* { 0x154, 0x2f39 },*/ 647 { 0x14d, 0xba33 }, 648 { 0x144, 0x0048 }, 649 { 0x152, 0x2010 }, 650 /* { 0x158, 0x1223 },*/ 651 { 0x140, 0x4444 }, 652 { 0x154, 0x2f3b }, 653 { 0x158, 0xb203 }, 654 { 0x157, 0x2029 }, 655 }; 656 657 /* Start Workaround for OptimaEEE Rev.Z0 */ 658 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); 659 660 gm_phy_write(hw, port, 1, 0x4099); 661 gm_phy_write(hw, port, 3, 0x1120); 662 gm_phy_write(hw, port, 11, 0x113c); 663 gm_phy_write(hw, port, 14, 0x8100); 664 gm_phy_write(hw, port, 15, 0x112a); 665 gm_phy_write(hw, port, 17, 0x1008); 666 667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); 668 gm_phy_write(hw, port, 1, 0x20b0); 669 670 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 671 672 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) { 673 /* apply AFE settings */ 674 gm_phy_write(hw, port, 17, eee_afe[i].val); 675 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); 676 } 677 678 /* End Workaround for OptimaEEE */ 679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 680 681 /* Enable 10Base-Te (EEE) */ 682 if (hw->chip_id >= CHIP_ID_YUKON_PRM) { 683 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 684 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, 685 reg | PHY_M_10B_TE_ENABLE); 686 } 687 } 688 689 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 690 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) 691 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 692 else 693 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 694 } 695 696 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; 697 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; 698 699 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) 700 { 701 u32 reg1; 702 703 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 704 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 705 reg1 &= ~phy_power[port]; 706 707 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 708 reg1 |= coma_mode[port]; 709 710 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 712 sky2_pci_read32(hw, PCI_DEV_REG1); 713 714 if (hw->chip_id == CHIP_ID_YUKON_FE) 715 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); 716 else if (hw->flags & SKY2_HW_ADV_POWER_CTL) 717 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 718 } 719 720 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) 721 { 722 u32 reg1; 723 u16 ctrl; 724 725 /* release GPHY Control reset */ 726 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 727 728 /* release GMAC reset */ 729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 730 731 if (hw->flags & SKY2_HW_NEWER_PHY) { 732 /* select page 2 to access MAC control register */ 733 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 734 735 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 736 /* allow GMII Power Down */ 737 ctrl &= ~PHY_M_MAC_GMIF_PUP; 738 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 739 740 /* set page register back to 0 */ 741 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 742 } 743 744 /* setup General Purpose Control Register */ 745 gma_write16(hw, port, GM_GP_CTRL, 746 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | 747 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | 748 GM_GPCR_AU_SPD_DIS); 749 750 if (hw->chip_id != CHIP_ID_YUKON_EC) { 751 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 752 /* select page 2 to access MAC control register */ 753 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 754 755 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 756 /* enable Power Down */ 757 ctrl |= PHY_M_PC_POW_D_ENA; 758 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 759 760 /* set page register back to 0 */ 761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 762 } 763 764 /* set IEEE compatible Power Down Mode (dev. #4.99) */ 765 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); 766 } 767 768 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 769 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 770 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ 771 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 772 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 773 } 774 775 /* configure IPG according to used link speed */ 776 static void sky2_set_ipg(struct sky2_port *sky2) 777 { 778 u16 reg; 779 780 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); 781 reg &= ~GM_SMOD_IPG_MSK; 782 if (sky2->speed > SPEED_100) 783 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 784 else 785 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 786 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); 787 } 788 789 /* Enable Rx/Tx */ 790 static void sky2_enable_rx_tx(struct sky2_port *sky2) 791 { 792 struct sky2_hw *hw = sky2->hw; 793 unsigned port = sky2->port; 794 u16 reg; 795 796 reg = gma_read16(hw, port, GM_GP_CTRL); 797 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 798 gma_write16(hw, port, GM_GP_CTRL, reg); 799 } 800 801 /* Force a renegotiation */ 802 static void sky2_phy_reinit(struct sky2_port *sky2) 803 { 804 spin_lock_bh(&sky2->phy_lock); 805 sky2_phy_init(sky2->hw, sky2->port); 806 sky2_enable_rx_tx(sky2); 807 spin_unlock_bh(&sky2->phy_lock); 808 } 809 810 /* Put device in state to listen for Wake On Lan */ 811 static void sky2_wol_init(struct sky2_port *sky2) 812 { 813 struct sky2_hw *hw = sky2->hw; 814 unsigned port = sky2->port; 815 enum flow_control save_mode; 816 u16 ctrl; 817 818 /* Bring hardware out of reset */ 819 sky2_write16(hw, B0_CTST, CS_RST_CLR); 820 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 821 822 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 824 825 /* Force to 10/100 826 * sky2_reset will re-enable on resume 827 */ 828 save_mode = sky2->flow_mode; 829 ctrl = sky2->advertising; 830 831 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 832 sky2->flow_mode = FC_NONE; 833 834 spin_lock_bh(&sky2->phy_lock); 835 sky2_phy_power_up(hw, port); 836 sky2_phy_init(hw, port); 837 spin_unlock_bh(&sky2->phy_lock); 838 839 sky2->flow_mode = save_mode; 840 sky2->advertising = ctrl; 841 842 /* Set GMAC to no flow control and auto update for speed/duplex */ 843 gma_write16(hw, port, GM_GP_CTRL, 844 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 845 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 846 847 /* Set WOL address */ 848 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 849 sky2->netdev->dev_addr, ETH_ALEN); 850 851 /* Turn on appropriate WOL control bits */ 852 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 853 ctrl = 0; 854 if (sky2->wol & WAKE_PHY) 855 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 856 else 857 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 858 859 if (sky2->wol & WAKE_MAGIC) 860 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 861 else 862 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 863 864 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 865 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 866 867 /* Disable PiG firmware */ 868 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); 869 870 /* block receiver */ 871 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 872 } 873 874 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) 875 { 876 struct net_device *dev = hw->dev[port]; 877 878 if ( (hw->chip_id == CHIP_ID_YUKON_EX && 879 hw->chip_rev != CHIP_REV_YU_EX_A0) || 880 hw->chip_id >= CHIP_ID_YUKON_FE_P) { 881 /* Yukon-Extreme B0 and further Extreme devices */ 882 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 883 } else if (dev->mtu > ETH_DATA_LEN) { 884 /* set Tx GMAC FIFO Almost Empty Threshold */ 885 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 886 (ECU_JUMBO_WM << 16) | ECU_AE_THR); 887 888 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); 889 } else 890 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 891 } 892 893 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 894 { 895 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 896 u16 reg; 897 u32 rx_reg; 898 int i; 899 const u8 *addr = hw->dev[port]->dev_addr; 900 901 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 902 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 903 904 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 905 906 if (hw->chip_id == CHIP_ID_YUKON_XL && 907 hw->chip_rev == CHIP_REV_YU_XL_A0 && 908 port == 1) { 909 /* WA DEV_472 -- looks like crossed wires on port 2 */ 910 /* clear GMAC 1 Control reset */ 911 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 912 do { 913 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 914 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 915 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 916 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 917 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 918 } 919 920 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 921 922 /* Enable Transmit FIFO Underrun */ 923 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 924 925 spin_lock_bh(&sky2->phy_lock); 926 sky2_phy_power_up(hw, port); 927 sky2_phy_init(hw, port); 928 spin_unlock_bh(&sky2->phy_lock); 929 930 /* MIB clear */ 931 reg = gma_read16(hw, port, GM_PHY_ADDR); 932 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 933 934 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) 935 gma_read16(hw, port, i); 936 gma_write16(hw, port, GM_PHY_ADDR, reg); 937 938 /* transmit control */ 939 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 940 941 /* receive control reg: unicast + multicast + no FCS */ 942 gma_write16(hw, port, GM_RX_CTRL, 943 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 944 945 /* transmit flow control */ 946 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 947 948 /* transmit parameter */ 949 gma_write16(hw, port, GM_TX_PARAM, 950 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 951 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 952 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 953 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 954 955 /* serial mode register */ 956 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 957 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000); 958 959 if (hw->dev[port]->mtu > ETH_DATA_LEN) 960 reg |= GM_SMOD_JUMBO_ENA; 961 962 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 963 hw->chip_rev == CHIP_REV_YU_EC_U_B1) 964 reg |= GM_NEW_FLOW_CTRL; 965 966 gma_write16(hw, port, GM_SERIAL_MODE, reg); 967 968 /* virtual address for data */ 969 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 970 971 /* physical address: used for pause frames */ 972 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 973 974 /* ignore counter overflows */ 975 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 976 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 977 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 978 979 /* Configure Rx MAC FIFO */ 980 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 981 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 982 if (hw->chip_id == CHIP_ID_YUKON_EX || 983 hw->chip_id == CHIP_ID_YUKON_FE_P) 984 rx_reg |= GMF_RX_OVER_ON; 985 986 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); 987 988 if (hw->chip_id == CHIP_ID_YUKON_XL) { 989 /* Hardware errata - clear flush mask */ 990 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); 991 } else { 992 /* Flush Rx MAC FIFO on any flow control or error */ 993 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 994 } 995 996 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ 997 reg = RX_GMF_FL_THR_DEF + 1; 998 /* Another magic mystery workaround from sk98lin */ 999 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1000 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1001 reg = 0x178; 1002 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); 1003 1004 /* Configure Tx MAC FIFO */ 1005 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 1006 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 1007 1008 /* On chips without ram buffer, pause is controlled by MAC level */ 1009 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { 1010 /* Pause threshold is scaled by 8 in bytes */ 1011 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1012 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1013 reg = 1568 / 8; 1014 else 1015 reg = 1024 / 8; 1016 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); 1017 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); 1018 1019 sky2_set_tx_stfwd(hw, port); 1020 } 1021 1022 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1023 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 1024 /* disable dynamic watermark */ 1025 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); 1026 reg &= ~TX_DYN_WM_ENA; 1027 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); 1028 } 1029 } 1030 1031 /* Assign Ram Buffer allocation to queue */ 1032 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) 1033 { 1034 u32 end; 1035 1036 /* convert from K bytes to qwords used for hw register */ 1037 start *= 1024/8; 1038 space *= 1024/8; 1039 end = start + space - 1; 1040 1041 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 1042 sky2_write32(hw, RB_ADDR(q, RB_START), start); 1043 sky2_write32(hw, RB_ADDR(q, RB_END), end); 1044 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 1045 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 1046 1047 if (q == Q_R1 || q == Q_R2) { 1048 u32 tp = space - space/4; 1049 1050 /* On receive queue's set the thresholds 1051 * give receiver priority when > 3/4 full 1052 * send pause when down to 2K 1053 */ 1054 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 1055 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 1056 1057 tp = space - 2048/8; 1058 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 1059 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 1060 } else { 1061 /* Enable store & forward on Tx queue's because 1062 * Tx FIFO is only 1K on Yukon 1063 */ 1064 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 1065 } 1066 1067 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 1068 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 1069 } 1070 1071 /* Setup Bus Memory Interface */ 1072 static void sky2_qset(struct sky2_hw *hw, u16 q) 1073 { 1074 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 1075 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 1076 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 1077 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 1078 } 1079 1080 /* Setup prefetch unit registers. This is the interface between 1081 * hardware and driver list elements 1082 */ 1083 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, 1084 dma_addr_t addr, u32 last) 1085 { 1086 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1087 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 1088 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); 1089 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); 1090 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 1091 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 1092 1093 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 1094 } 1095 1096 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) 1097 { 1098 struct sky2_tx_le *le = sky2->tx_le + *slot; 1099 1100 *slot = RING_NEXT(*slot, sky2->tx_ring_size); 1101 le->ctrl = 0; 1102 return le; 1103 } 1104 1105 static void tx_init(struct sky2_port *sky2) 1106 { 1107 struct sky2_tx_le *le; 1108 1109 sky2->tx_prod = sky2->tx_cons = 0; 1110 sky2->tx_tcpsum = 0; 1111 sky2->tx_last_mss = 0; 1112 1113 le = get_tx_le(sky2, &sky2->tx_prod); 1114 le->addr = 0; 1115 le->opcode = OP_ADDR64 | HW_OWNER; 1116 sky2->tx_last_upper = 0; 1117 } 1118 1119 /* Update chip's next pointer */ 1120 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 1121 { 1122 /* Make sure write' to descriptors are complete before we tell hardware */ 1123 wmb(); 1124 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 1125 1126 /* Synchronize I/O on since next processor may write to tail */ 1127 mmiowb(); 1128 } 1129 1130 1131 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 1132 { 1133 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 1134 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 1135 le->ctrl = 0; 1136 return le; 1137 } 1138 1139 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) 1140 { 1141 unsigned size; 1142 1143 /* Space needed for frame data + headers rounded up */ 1144 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1145 1146 /* Stopping point for hardware truncation */ 1147 return (size - 8) / sizeof(u32); 1148 } 1149 1150 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) 1151 { 1152 struct rx_ring_info *re; 1153 unsigned size; 1154 1155 /* Space needed for frame data + headers rounded up */ 1156 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1157 1158 sky2->rx_nfrags = size >> PAGE_SHIFT; 1159 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); 1160 1161 /* Compute residue after pages */ 1162 size -= sky2->rx_nfrags << PAGE_SHIFT; 1163 1164 /* Optimize to handle small packets and headers */ 1165 if (size < copybreak) 1166 size = copybreak; 1167 if (size < ETH_HLEN) 1168 size = ETH_HLEN; 1169 1170 return size; 1171 } 1172 1173 /* Build description to hardware for one receive segment */ 1174 static void sky2_rx_add(struct sky2_port *sky2, u8 op, 1175 dma_addr_t map, unsigned len) 1176 { 1177 struct sky2_rx_le *le; 1178 1179 if (sizeof(dma_addr_t) > sizeof(u32)) { 1180 le = sky2_next_rx(sky2); 1181 le->addr = cpu_to_le32(upper_32_bits(map)); 1182 le->opcode = OP_ADDR64 | HW_OWNER; 1183 } 1184 1185 le = sky2_next_rx(sky2); 1186 le->addr = cpu_to_le32(lower_32_bits(map)); 1187 le->length = cpu_to_le16(len); 1188 le->opcode = op | HW_OWNER; 1189 } 1190 1191 /* Build description to hardware for one possibly fragmented skb */ 1192 static void sky2_rx_submit(struct sky2_port *sky2, 1193 const struct rx_ring_info *re) 1194 { 1195 int i; 1196 1197 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); 1198 1199 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) 1200 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); 1201 } 1202 1203 1204 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, 1205 unsigned size) 1206 { 1207 struct sk_buff *skb = re->skb; 1208 int i; 1209 1210 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); 1211 if (pci_dma_mapping_error(pdev, re->data_addr)) 1212 goto mapping_error; 1213 1214 dma_unmap_len_set(re, data_size, size); 1215 1216 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1217 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1218 1219 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0, 1220 skb_frag_size(frag), 1221 DMA_FROM_DEVICE); 1222 1223 if (dma_mapping_error(&pdev->dev, re->frag_addr[i])) 1224 goto map_page_error; 1225 } 1226 return 0; 1227 1228 map_page_error: 1229 while (--i >= 0) { 1230 pci_unmap_page(pdev, re->frag_addr[i], 1231 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1232 PCI_DMA_FROMDEVICE); 1233 } 1234 1235 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1236 PCI_DMA_FROMDEVICE); 1237 1238 mapping_error: 1239 if (net_ratelimit()) 1240 dev_warn(&pdev->dev, "%s: rx mapping error\n", 1241 skb->dev->name); 1242 return -EIO; 1243 } 1244 1245 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) 1246 { 1247 struct sk_buff *skb = re->skb; 1248 int i; 1249 1250 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1251 PCI_DMA_FROMDEVICE); 1252 1253 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) 1254 pci_unmap_page(pdev, re->frag_addr[i], 1255 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1256 PCI_DMA_FROMDEVICE); 1257 } 1258 1259 /* Tell chip where to start receive checksum. 1260 * Actually has two checksums, but set both same to avoid possible byte 1261 * order problems. 1262 */ 1263 static void rx_set_checksum(struct sky2_port *sky2) 1264 { 1265 struct sky2_rx_le *le = sky2_next_rx(sky2); 1266 1267 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); 1268 le->ctrl = 0; 1269 le->opcode = OP_TCPSTART | HW_OWNER; 1270 1271 sky2_write32(sky2->hw, 1272 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1273 (sky2->netdev->features & NETIF_F_RXCSUM) 1274 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 1275 } 1276 1277 /* Enable/disable receive hash calculation (RSS) */ 1278 static void rx_set_rss(struct net_device *dev, u32 features) 1279 { 1280 struct sky2_port *sky2 = netdev_priv(dev); 1281 struct sky2_hw *hw = sky2->hw; 1282 int i, nkeys = 4; 1283 1284 /* Supports IPv6 and other modes */ 1285 if (hw->flags & SKY2_HW_NEW_LE) { 1286 nkeys = 10; 1287 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); 1288 } 1289 1290 /* Program RSS initial values */ 1291 if (features & NETIF_F_RXHASH) { 1292 u32 key[nkeys]; 1293 1294 get_random_bytes(key, nkeys * sizeof(u32)); 1295 for (i = 0; i < nkeys; i++) 1296 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), 1297 key[i]); 1298 1299 /* Need to turn on (undocumented) flag to make hashing work */ 1300 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), 1301 RX_STFW_ENA); 1302 1303 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1304 BMU_ENA_RX_RSS_HASH); 1305 } else 1306 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1307 BMU_DIS_RX_RSS_HASH); 1308 } 1309 1310 /* 1311 * The RX Stop command will not work for Yukon-2 if the BMU does not 1312 * reach the end of packet and since we can't make sure that we have 1313 * incoming data, we must reset the BMU while it is not doing a DMA 1314 * transfer. Since it is possible that the RX path is still active, 1315 * the RX RAM buffer will be stopped first, so any possible incoming 1316 * data will not trigger a DMA. After the RAM buffer is stopped, the 1317 * BMU is polled until any DMA in progress is ended and only then it 1318 * will be reset. 1319 */ 1320 static void sky2_rx_stop(struct sky2_port *sky2) 1321 { 1322 struct sky2_hw *hw = sky2->hw; 1323 unsigned rxq = rxqaddr[sky2->port]; 1324 int i; 1325 1326 /* disable the RAM Buffer receive queue */ 1327 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 1328 1329 for (i = 0; i < 0xffff; i++) 1330 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 1331 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 1332 goto stopped; 1333 1334 netdev_warn(sky2->netdev, "receiver stop failed\n"); 1335 stopped: 1336 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 1337 1338 /* reset the Rx prefetch unit */ 1339 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1340 mmiowb(); 1341 } 1342 1343 /* Clean out receive buffer area, assumes receiver hardware stopped */ 1344 static void sky2_rx_clean(struct sky2_port *sky2) 1345 { 1346 unsigned i; 1347 1348 memset(sky2->rx_le, 0, RX_LE_BYTES); 1349 for (i = 0; i < sky2->rx_pending; i++) { 1350 struct rx_ring_info *re = sky2->rx_ring + i; 1351 1352 if (re->skb) { 1353 sky2_rx_unmap_skb(sky2->hw->pdev, re); 1354 kfree_skb(re->skb); 1355 re->skb = NULL; 1356 } 1357 } 1358 } 1359 1360 /* Basic MII support */ 1361 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1362 { 1363 struct mii_ioctl_data *data = if_mii(ifr); 1364 struct sky2_port *sky2 = netdev_priv(dev); 1365 struct sky2_hw *hw = sky2->hw; 1366 int err = -EOPNOTSUPP; 1367 1368 if (!netif_running(dev)) 1369 return -ENODEV; /* Phy still in reset */ 1370 1371 switch (cmd) { 1372 case SIOCGMIIPHY: 1373 data->phy_id = PHY_ADDR_MARV; 1374 1375 /* fallthru */ 1376 case SIOCGMIIREG: { 1377 u16 val = 0; 1378 1379 spin_lock_bh(&sky2->phy_lock); 1380 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); 1381 spin_unlock_bh(&sky2->phy_lock); 1382 1383 data->val_out = val; 1384 break; 1385 } 1386 1387 case SIOCSMIIREG: 1388 spin_lock_bh(&sky2->phy_lock); 1389 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, 1390 data->val_in); 1391 spin_unlock_bh(&sky2->phy_lock); 1392 break; 1393 } 1394 return err; 1395 } 1396 1397 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) 1398 1399 static void sky2_vlan_mode(struct net_device *dev, u32 features) 1400 { 1401 struct sky2_port *sky2 = netdev_priv(dev); 1402 struct sky2_hw *hw = sky2->hw; 1403 u16 port = sky2->port; 1404 1405 if (features & NETIF_F_HW_VLAN_RX) 1406 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1407 RX_VLAN_STRIP_ON); 1408 else 1409 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1410 RX_VLAN_STRIP_OFF); 1411 1412 if (features & NETIF_F_HW_VLAN_TX) { 1413 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1414 TX_VLAN_TAG_ON); 1415 1416 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 1417 } else { 1418 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1419 TX_VLAN_TAG_OFF); 1420 1421 /* Can't do transmit offload of vlan without hw vlan */ 1422 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; 1423 } 1424 } 1425 1426 /* Amount of required worst case padding in rx buffer */ 1427 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) 1428 { 1429 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; 1430 } 1431 1432 /* 1433 * Allocate an skb for receiving. If the MTU is large enough 1434 * make the skb non-linear with a fragment list of pages. 1435 */ 1436 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp) 1437 { 1438 struct sk_buff *skb; 1439 int i; 1440 1441 skb = __netdev_alloc_skb(sky2->netdev, 1442 sky2->rx_data_size + sky2_rx_pad(sky2->hw), 1443 gfp); 1444 if (!skb) 1445 goto nomem; 1446 1447 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { 1448 unsigned char *start; 1449 /* 1450 * Workaround for a bug in FIFO that cause hang 1451 * if the FIFO if the receive buffer is not 64 byte aligned. 1452 * The buffer returned from netdev_alloc_skb is 1453 * aligned except if slab debugging is enabled. 1454 */ 1455 start = PTR_ALIGN(skb->data, 8); 1456 skb_reserve(skb, start - skb->data); 1457 } else 1458 skb_reserve(skb, NET_IP_ALIGN); 1459 1460 for (i = 0; i < sky2->rx_nfrags; i++) { 1461 struct page *page = alloc_page(gfp); 1462 1463 if (!page) 1464 goto free_partial; 1465 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); 1466 } 1467 1468 return skb; 1469 free_partial: 1470 kfree_skb(skb); 1471 nomem: 1472 return NULL; 1473 } 1474 1475 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) 1476 { 1477 sky2_put_idx(sky2->hw, rxq, sky2->rx_put); 1478 } 1479 1480 static int sky2_alloc_rx_skbs(struct sky2_port *sky2) 1481 { 1482 struct sky2_hw *hw = sky2->hw; 1483 unsigned i; 1484 1485 sky2->rx_data_size = sky2_get_rx_data_size(sky2); 1486 1487 /* Fill Rx ring */ 1488 for (i = 0; i < sky2->rx_pending; i++) { 1489 struct rx_ring_info *re = sky2->rx_ring + i; 1490 1491 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL); 1492 if (!re->skb) 1493 return -ENOMEM; 1494 1495 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { 1496 dev_kfree_skb(re->skb); 1497 re->skb = NULL; 1498 return -ENOMEM; 1499 } 1500 } 1501 return 0; 1502 } 1503 1504 /* 1505 * Setup receiver buffer pool. 1506 * Normal case this ends up creating one list element for skb 1507 * in the receive ring. Worst case if using large MTU and each 1508 * allocation falls on a different 64 bit region, that results 1509 * in 6 list elements per ring entry. 1510 * One element is used for checksum enable/disable, and one 1511 * extra to avoid wrap. 1512 */ 1513 static void sky2_rx_start(struct sky2_port *sky2) 1514 { 1515 struct sky2_hw *hw = sky2->hw; 1516 struct rx_ring_info *re; 1517 unsigned rxq = rxqaddr[sky2->port]; 1518 unsigned i, thresh; 1519 1520 sky2->rx_put = sky2->rx_next = 0; 1521 sky2_qset(hw, rxq); 1522 1523 /* On PCI express lowering the watermark gives better performance */ 1524 if (pci_is_pcie(hw->pdev)) 1525 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); 1526 1527 /* These chips have no ram buffer? 1528 * MAC Rx RAM Read is controlled by hardware */ 1529 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1530 hw->chip_rev > CHIP_REV_YU_EC_U_A0) 1531 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); 1532 1533 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 1534 1535 if (!(hw->flags & SKY2_HW_NEW_LE)) 1536 rx_set_checksum(sky2); 1537 1538 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 1539 rx_set_rss(sky2->netdev, sky2->netdev->features); 1540 1541 /* submit Rx ring */ 1542 for (i = 0; i < sky2->rx_pending; i++) { 1543 re = sky2->rx_ring + i; 1544 sky2_rx_submit(sky2, re); 1545 } 1546 1547 /* 1548 * The receiver hangs if it receives frames larger than the 1549 * packet buffer. As a workaround, truncate oversize frames, but 1550 * the register is limited to 9 bits, so if you do frames > 2052 1551 * you better get the MTU right! 1552 */ 1553 thresh = sky2_get_rx_threshold(sky2); 1554 if (thresh > 0x1ff) 1555 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); 1556 else { 1557 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); 1558 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 1559 } 1560 1561 /* Tell chip about available buffers */ 1562 sky2_rx_update(sky2, rxq); 1563 1564 if (hw->chip_id == CHIP_ID_YUKON_EX || 1565 hw->chip_id == CHIP_ID_YUKON_SUPR) { 1566 /* 1567 * Disable flushing of non ASF packets; 1568 * must be done after initializing the BMUs; 1569 * drivers without ASF support should do this too, otherwise 1570 * it may happen that they cannot run on ASF devices; 1571 * remember that the MAC FIFO isn't reset during initialization. 1572 */ 1573 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); 1574 } 1575 1576 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { 1577 /* Enable RX Home Address & Routing Header checksum fix */ 1578 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), 1579 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); 1580 1581 /* Enable TX Home Address & Routing Header checksum fix */ 1582 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), 1583 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); 1584 } 1585 } 1586 1587 static int sky2_alloc_buffers(struct sky2_port *sky2) 1588 { 1589 struct sky2_hw *hw = sky2->hw; 1590 1591 /* must be power of 2 */ 1592 sky2->tx_le = pci_alloc_consistent(hw->pdev, 1593 sky2->tx_ring_size * 1594 sizeof(struct sky2_tx_le), 1595 &sky2->tx_le_map); 1596 if (!sky2->tx_le) 1597 goto nomem; 1598 1599 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), 1600 GFP_KERNEL); 1601 if (!sky2->tx_ring) 1602 goto nomem; 1603 1604 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, 1605 &sky2->rx_le_map); 1606 if (!sky2->rx_le) 1607 goto nomem; 1608 memset(sky2->rx_le, 0, RX_LE_BYTES); 1609 1610 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), 1611 GFP_KERNEL); 1612 if (!sky2->rx_ring) 1613 goto nomem; 1614 1615 return sky2_alloc_rx_skbs(sky2); 1616 nomem: 1617 return -ENOMEM; 1618 } 1619 1620 static void sky2_free_buffers(struct sky2_port *sky2) 1621 { 1622 struct sky2_hw *hw = sky2->hw; 1623 1624 sky2_rx_clean(sky2); 1625 1626 if (sky2->rx_le) { 1627 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1628 sky2->rx_le, sky2->rx_le_map); 1629 sky2->rx_le = NULL; 1630 } 1631 if (sky2->tx_le) { 1632 pci_free_consistent(hw->pdev, 1633 sky2->tx_ring_size * sizeof(struct sky2_tx_le), 1634 sky2->tx_le, sky2->tx_le_map); 1635 sky2->tx_le = NULL; 1636 } 1637 kfree(sky2->tx_ring); 1638 kfree(sky2->rx_ring); 1639 1640 sky2->tx_ring = NULL; 1641 sky2->rx_ring = NULL; 1642 } 1643 1644 static void sky2_hw_up(struct sky2_port *sky2) 1645 { 1646 struct sky2_hw *hw = sky2->hw; 1647 unsigned port = sky2->port; 1648 u32 ramsize; 1649 int cap; 1650 struct net_device *otherdev = hw->dev[sky2->port^1]; 1651 1652 tx_init(sky2); 1653 1654 /* 1655 * On dual port PCI-X card, there is an problem where status 1656 * can be received out of order due to split transactions 1657 */ 1658 if (otherdev && netif_running(otherdev) && 1659 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { 1660 u16 cmd; 1661 1662 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); 1663 cmd &= ~PCI_X_CMD_MAX_SPLIT; 1664 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); 1665 } 1666 1667 sky2_mac_init(hw, port); 1668 1669 /* Register is number of 4K blocks on internal RAM buffer. */ 1670 ramsize = sky2_read8(hw, B2_E_0) * 4; 1671 if (ramsize > 0) { 1672 u32 rxspace; 1673 1674 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); 1675 if (ramsize < 16) 1676 rxspace = ramsize / 2; 1677 else 1678 rxspace = 8 + (2*(ramsize - 16))/3; 1679 1680 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1681 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); 1682 1683 /* Make sure SyncQ is disabled */ 1684 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1685 RB_RST_SET); 1686 } 1687 1688 sky2_qset(hw, txqaddr[port]); 1689 1690 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ 1691 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) 1692 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); 1693 1694 /* Set almost empty threshold */ 1695 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1696 hw->chip_rev == CHIP_REV_YU_EC_U_A0) 1697 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); 1698 1699 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1700 sky2->tx_ring_size - 1); 1701 1702 sky2_vlan_mode(sky2->netdev, sky2->netdev->features); 1703 netdev_update_features(sky2->netdev); 1704 1705 sky2_rx_start(sky2); 1706 } 1707 1708 /* Setup device IRQ and enable napi to process */ 1709 static int sky2_setup_irq(struct sky2_hw *hw, const char *name) 1710 { 1711 struct pci_dev *pdev = hw->pdev; 1712 int err; 1713 1714 err = request_irq(pdev->irq, sky2_intr, 1715 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, 1716 name, hw); 1717 if (err) 1718 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 1719 else { 1720 napi_enable(&hw->napi); 1721 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 1722 sky2_read32(hw, B0_IMSK); 1723 } 1724 1725 return err; 1726 } 1727 1728 1729 /* Bring up network interface. */ 1730 static int sky2_up(struct net_device *dev) 1731 { 1732 struct sky2_port *sky2 = netdev_priv(dev); 1733 struct sky2_hw *hw = sky2->hw; 1734 unsigned port = sky2->port; 1735 u32 imask; 1736 int err; 1737 1738 netif_carrier_off(dev); 1739 1740 err = sky2_alloc_buffers(sky2); 1741 if (err) 1742 goto err_out; 1743 1744 /* With single port, IRQ is setup when device is brought up */ 1745 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name))) 1746 goto err_out; 1747 1748 sky2_hw_up(sky2); 1749 1750 /* Enable interrupts from phy/mac for port */ 1751 imask = sky2_read32(hw, B0_IMSK); 1752 imask |= portirq_msk[port]; 1753 sky2_write32(hw, B0_IMSK, imask); 1754 sky2_read32(hw, B0_IMSK); 1755 1756 netif_info(sky2, ifup, dev, "enabling interface\n"); 1757 1758 return 0; 1759 1760 err_out: 1761 sky2_free_buffers(sky2); 1762 return err; 1763 } 1764 1765 /* Modular subtraction in ring */ 1766 static inline int tx_inuse(const struct sky2_port *sky2) 1767 { 1768 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); 1769 } 1770 1771 /* Number of list elements available for next tx */ 1772 static inline int tx_avail(const struct sky2_port *sky2) 1773 { 1774 return sky2->tx_pending - tx_inuse(sky2); 1775 } 1776 1777 /* Estimate of number of transmit list elements required */ 1778 static unsigned tx_le_req(const struct sk_buff *skb) 1779 { 1780 unsigned count; 1781 1782 count = (skb_shinfo(skb)->nr_frags + 1) 1783 * (sizeof(dma_addr_t) / sizeof(u32)); 1784 1785 if (skb_is_gso(skb)) 1786 ++count; 1787 else if (sizeof(dma_addr_t) == sizeof(u32)) 1788 ++count; /* possible vlan */ 1789 1790 if (skb->ip_summed == CHECKSUM_PARTIAL) 1791 ++count; 1792 1793 return count; 1794 } 1795 1796 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) 1797 { 1798 if (re->flags & TX_MAP_SINGLE) 1799 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr), 1800 dma_unmap_len(re, maplen), 1801 PCI_DMA_TODEVICE); 1802 else if (re->flags & TX_MAP_PAGE) 1803 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr), 1804 dma_unmap_len(re, maplen), 1805 PCI_DMA_TODEVICE); 1806 re->flags = 0; 1807 } 1808 1809 /* 1810 * Put one packet in ring for transmit. 1811 * A single packet can generate multiple list elements, and 1812 * the number of ring elements will probably be less than the number 1813 * of list elements used. 1814 */ 1815 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, 1816 struct net_device *dev) 1817 { 1818 struct sky2_port *sky2 = netdev_priv(dev); 1819 struct sky2_hw *hw = sky2->hw; 1820 struct sky2_tx_le *le = NULL; 1821 struct tx_ring_info *re; 1822 unsigned i, len; 1823 dma_addr_t mapping; 1824 u32 upper; 1825 u16 slot; 1826 u16 mss; 1827 u8 ctrl; 1828 1829 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) 1830 return NETDEV_TX_BUSY; 1831 1832 len = skb_headlen(skb); 1833 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); 1834 1835 if (pci_dma_mapping_error(hw->pdev, mapping)) 1836 goto mapping_error; 1837 1838 slot = sky2->tx_prod; 1839 netif_printk(sky2, tx_queued, KERN_DEBUG, dev, 1840 "tx queued, slot %u, len %d\n", slot, skb->len); 1841 1842 /* Send high bits if needed */ 1843 upper = upper_32_bits(mapping); 1844 if (upper != sky2->tx_last_upper) { 1845 le = get_tx_le(sky2, &slot); 1846 le->addr = cpu_to_le32(upper); 1847 sky2->tx_last_upper = upper; 1848 le->opcode = OP_ADDR64 | HW_OWNER; 1849 } 1850 1851 /* Check for TCP Segmentation Offload */ 1852 mss = skb_shinfo(skb)->gso_size; 1853 if (mss != 0) { 1854 1855 if (!(hw->flags & SKY2_HW_NEW_LE)) 1856 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); 1857 1858 if (mss != sky2->tx_last_mss) { 1859 le = get_tx_le(sky2, &slot); 1860 le->addr = cpu_to_le32(mss); 1861 1862 if (hw->flags & SKY2_HW_NEW_LE) 1863 le->opcode = OP_MSS | HW_OWNER; 1864 else 1865 le->opcode = OP_LRGLEN | HW_OWNER; 1866 sky2->tx_last_mss = mss; 1867 } 1868 } 1869 1870 ctrl = 0; 1871 1872 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ 1873 if (vlan_tx_tag_present(skb)) { 1874 if (!le) { 1875 le = get_tx_le(sky2, &slot); 1876 le->addr = 0; 1877 le->opcode = OP_VLAN|HW_OWNER; 1878 } else 1879 le->opcode |= OP_VLAN; 1880 le->length = cpu_to_be16(vlan_tx_tag_get(skb)); 1881 ctrl |= INS_VLAN; 1882 } 1883 1884 /* Handle TCP checksum offload */ 1885 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1886 /* On Yukon EX (some versions) encoding change. */ 1887 if (hw->flags & SKY2_HW_AUTO_TX_SUM) 1888 ctrl |= CALSUM; /* auto checksum */ 1889 else { 1890 const unsigned offset = skb_transport_offset(skb); 1891 u32 tcpsum; 1892 1893 tcpsum = offset << 16; /* sum start */ 1894 tcpsum |= offset + skb->csum_offset; /* sum write */ 1895 1896 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1897 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 1898 ctrl |= UDPTCP; 1899 1900 if (tcpsum != sky2->tx_tcpsum) { 1901 sky2->tx_tcpsum = tcpsum; 1902 1903 le = get_tx_le(sky2, &slot); 1904 le->addr = cpu_to_le32(tcpsum); 1905 le->length = 0; /* initial checksum value */ 1906 le->ctrl = 1; /* one packet */ 1907 le->opcode = OP_TCPLISW | HW_OWNER; 1908 } 1909 } 1910 } 1911 1912 re = sky2->tx_ring + slot; 1913 re->flags = TX_MAP_SINGLE; 1914 dma_unmap_addr_set(re, mapaddr, mapping); 1915 dma_unmap_len_set(re, maplen, len); 1916 1917 le = get_tx_le(sky2, &slot); 1918 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1919 le->length = cpu_to_le16(len); 1920 le->ctrl = ctrl; 1921 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); 1922 1923 1924 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1925 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1926 1927 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0, 1928 skb_frag_size(frag), DMA_TO_DEVICE); 1929 1930 if (dma_mapping_error(&hw->pdev->dev, mapping)) 1931 goto mapping_unwind; 1932 1933 upper = upper_32_bits(mapping); 1934 if (upper != sky2->tx_last_upper) { 1935 le = get_tx_le(sky2, &slot); 1936 le->addr = cpu_to_le32(upper); 1937 sky2->tx_last_upper = upper; 1938 le->opcode = OP_ADDR64 | HW_OWNER; 1939 } 1940 1941 re = sky2->tx_ring + slot; 1942 re->flags = TX_MAP_PAGE; 1943 dma_unmap_addr_set(re, mapaddr, mapping); 1944 dma_unmap_len_set(re, maplen, skb_frag_size(frag)); 1945 1946 le = get_tx_le(sky2, &slot); 1947 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1948 le->length = cpu_to_le16(skb_frag_size(frag)); 1949 le->ctrl = ctrl; 1950 le->opcode = OP_BUFFER | HW_OWNER; 1951 } 1952 1953 re->skb = skb; 1954 le->ctrl |= EOP; 1955 1956 sky2->tx_prod = slot; 1957 1958 if (tx_avail(sky2) <= MAX_SKB_TX_LE) 1959 netif_stop_queue(dev); 1960 1961 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1962 1963 return NETDEV_TX_OK; 1964 1965 mapping_unwind: 1966 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { 1967 re = sky2->tx_ring + i; 1968 1969 sky2_tx_unmap(hw->pdev, re); 1970 } 1971 1972 mapping_error: 1973 if (net_ratelimit()) 1974 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 1975 dev_kfree_skb(skb); 1976 return NETDEV_TX_OK; 1977 } 1978 1979 /* 1980 * Free ring elements from starting at tx_cons until "done" 1981 * 1982 * NB: 1983 * 1. The hardware will tell us about partial completion of multi-part 1984 * buffers so make sure not to free skb to early. 1985 * 2. This may run in parallel start_xmit because the it only 1986 * looks at the tail of the queue of FIFO (tx_cons), not 1987 * the head (tx_prod) 1988 */ 1989 static void sky2_tx_complete(struct sky2_port *sky2, u16 done) 1990 { 1991 struct net_device *dev = sky2->netdev; 1992 unsigned idx; 1993 1994 BUG_ON(done >= sky2->tx_ring_size); 1995 1996 for (idx = sky2->tx_cons; idx != done; 1997 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 1998 struct tx_ring_info *re = sky2->tx_ring + idx; 1999 struct sk_buff *skb = re->skb; 2000 2001 sky2_tx_unmap(sky2->hw->pdev, re); 2002 2003 if (skb) { 2004 netif_printk(sky2, tx_done, KERN_DEBUG, dev, 2005 "tx done %u\n", idx); 2006 2007 u64_stats_update_begin(&sky2->tx_stats.syncp); 2008 ++sky2->tx_stats.packets; 2009 sky2->tx_stats.bytes += skb->len; 2010 u64_stats_update_end(&sky2->tx_stats.syncp); 2011 2012 re->skb = NULL; 2013 dev_kfree_skb_any(skb); 2014 2015 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); 2016 } 2017 } 2018 2019 sky2->tx_cons = idx; 2020 smp_mb(); 2021 } 2022 2023 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) 2024 { 2025 /* Disable Force Sync bit and Enable Alloc bit */ 2026 sky2_write8(hw, SK_REG(port, TXA_CTRL), 2027 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2028 2029 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2030 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2031 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2032 2033 /* Reset the PCI FIFO of the async Tx queue */ 2034 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 2035 BMU_RST_SET | BMU_FIFO_RST); 2036 2037 /* Reset the Tx prefetch units */ 2038 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 2039 PREF_UNIT_RST_SET); 2040 2041 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2042 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2043 } 2044 2045 static void sky2_hw_down(struct sky2_port *sky2) 2046 { 2047 struct sky2_hw *hw = sky2->hw; 2048 unsigned port = sky2->port; 2049 u16 ctrl; 2050 2051 /* Force flow control off */ 2052 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2053 2054 /* Stop transmitter */ 2055 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 2056 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 2057 2058 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2059 RB_RST_SET | RB_DIS_OP_MD); 2060 2061 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2062 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 2063 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2064 2065 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2066 2067 /* Workaround shared GMAC reset */ 2068 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && 2069 port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 2070 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2071 2072 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2073 2074 /* Force any delayed status interrupt and NAPI */ 2075 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); 2076 sky2_write32(hw, STAT_TX_TIMER_CNT, 0); 2077 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); 2078 sky2_read8(hw, STAT_ISR_TIMER_CTRL); 2079 2080 sky2_rx_stop(sky2); 2081 2082 spin_lock_bh(&sky2->phy_lock); 2083 sky2_phy_power_down(hw, port); 2084 spin_unlock_bh(&sky2->phy_lock); 2085 2086 sky2_tx_reset(hw, port); 2087 2088 /* Free any pending frames stuck in HW queue */ 2089 sky2_tx_complete(sky2, sky2->tx_prod); 2090 } 2091 2092 /* Network shutdown */ 2093 static int sky2_down(struct net_device *dev) 2094 { 2095 struct sky2_port *sky2 = netdev_priv(dev); 2096 struct sky2_hw *hw = sky2->hw; 2097 2098 /* Never really got started! */ 2099 if (!sky2->tx_le) 2100 return 0; 2101 2102 netif_info(sky2, ifdown, dev, "disabling interface\n"); 2103 2104 /* Disable port IRQ */ 2105 sky2_write32(hw, B0_IMSK, 2106 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]); 2107 sky2_read32(hw, B0_IMSK); 2108 2109 if (hw->ports == 1) { 2110 napi_disable(&hw->napi); 2111 free_irq(hw->pdev->irq, hw); 2112 } else { 2113 synchronize_irq(hw->pdev->irq); 2114 napi_synchronize(&hw->napi); 2115 } 2116 2117 sky2_hw_down(sky2); 2118 2119 sky2_free_buffers(sky2); 2120 2121 return 0; 2122 } 2123 2124 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) 2125 { 2126 if (hw->flags & SKY2_HW_FIBRE_PHY) 2127 return SPEED_1000; 2128 2129 if (!(hw->flags & SKY2_HW_GIGABIT)) { 2130 if (aux & PHY_M_PS_SPEED_100) 2131 return SPEED_100; 2132 else 2133 return SPEED_10; 2134 } 2135 2136 switch (aux & PHY_M_PS_SPEED_MSK) { 2137 case PHY_M_PS_SPEED_1000: 2138 return SPEED_1000; 2139 case PHY_M_PS_SPEED_100: 2140 return SPEED_100; 2141 default: 2142 return SPEED_10; 2143 } 2144 } 2145 2146 static void sky2_link_up(struct sky2_port *sky2) 2147 { 2148 struct sky2_hw *hw = sky2->hw; 2149 unsigned port = sky2->port; 2150 static const char *fc_name[] = { 2151 [FC_NONE] = "none", 2152 [FC_TX] = "tx", 2153 [FC_RX] = "rx", 2154 [FC_BOTH] = "both", 2155 }; 2156 2157 sky2_set_ipg(sky2); 2158 2159 sky2_enable_rx_tx(sky2); 2160 2161 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 2162 2163 netif_carrier_on(sky2->netdev); 2164 2165 mod_timer(&hw->watchdog_timer, jiffies + 1); 2166 2167 /* Turn on link LED */ 2168 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 2169 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 2170 2171 netif_info(sky2, link, sky2->netdev, 2172 "Link is up at %d Mbps, %s duplex, flow control %s\n", 2173 sky2->speed, 2174 sky2->duplex == DUPLEX_FULL ? "full" : "half", 2175 fc_name[sky2->flow_status]); 2176 } 2177 2178 static void sky2_link_down(struct sky2_port *sky2) 2179 { 2180 struct sky2_hw *hw = sky2->hw; 2181 unsigned port = sky2->port; 2182 u16 reg; 2183 2184 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 2185 2186 reg = gma_read16(hw, port, GM_GP_CTRL); 2187 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2188 gma_write16(hw, port, GM_GP_CTRL, reg); 2189 2190 netif_carrier_off(sky2->netdev); 2191 2192 /* Turn off link LED */ 2193 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 2194 2195 netif_info(sky2, link, sky2->netdev, "Link is down\n"); 2196 2197 sky2_phy_init(hw, port); 2198 } 2199 2200 static enum flow_control sky2_flow(int rx, int tx) 2201 { 2202 if (rx) 2203 return tx ? FC_BOTH : FC_RX; 2204 else 2205 return tx ? FC_TX : FC_NONE; 2206 } 2207 2208 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 2209 { 2210 struct sky2_hw *hw = sky2->hw; 2211 unsigned port = sky2->port; 2212 u16 advert, lpa; 2213 2214 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2215 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 2216 if (lpa & PHY_M_AN_RF) { 2217 netdev_err(sky2->netdev, "remote fault\n"); 2218 return -1; 2219 } 2220 2221 if (!(aux & PHY_M_PS_SPDUP_RES)) { 2222 netdev_err(sky2->netdev, "speed/duplex mismatch\n"); 2223 return -1; 2224 } 2225 2226 sky2->speed = sky2_phy_speed(hw, aux); 2227 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2228 2229 /* Since the pause result bits seem to in different positions on 2230 * different chips. look at registers. 2231 */ 2232 if (hw->flags & SKY2_HW_FIBRE_PHY) { 2233 /* Shift for bits in fiber PHY */ 2234 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); 2235 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); 2236 2237 if (advert & ADVERTISE_1000XPAUSE) 2238 advert |= ADVERTISE_PAUSE_CAP; 2239 if (advert & ADVERTISE_1000XPSE_ASYM) 2240 advert |= ADVERTISE_PAUSE_ASYM; 2241 if (lpa & LPA_1000XPAUSE) 2242 lpa |= LPA_PAUSE_CAP; 2243 if (lpa & LPA_1000XPAUSE_ASYM) 2244 lpa |= LPA_PAUSE_ASYM; 2245 } 2246 2247 sky2->flow_status = FC_NONE; 2248 if (advert & ADVERTISE_PAUSE_CAP) { 2249 if (lpa & LPA_PAUSE_CAP) 2250 sky2->flow_status = FC_BOTH; 2251 else if (advert & ADVERTISE_PAUSE_ASYM) 2252 sky2->flow_status = FC_RX; 2253 } else if (advert & ADVERTISE_PAUSE_ASYM) { 2254 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) 2255 sky2->flow_status = FC_TX; 2256 } 2257 2258 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && 2259 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) 2260 sky2->flow_status = FC_NONE; 2261 2262 if (sky2->flow_status & FC_TX) 2263 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2264 else 2265 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2266 2267 return 0; 2268 } 2269 2270 /* Interrupt from PHY */ 2271 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) 2272 { 2273 struct net_device *dev = hw->dev[port]; 2274 struct sky2_port *sky2 = netdev_priv(dev); 2275 u16 istatus, phystat; 2276 2277 if (!netif_running(dev)) 2278 return; 2279 2280 spin_lock(&sky2->phy_lock); 2281 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2282 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2283 2284 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", 2285 istatus, phystat); 2286 2287 if (istatus & PHY_M_IS_AN_COMPL) { 2288 if (sky2_autoneg_done(sky2, phystat) == 0 && 2289 !netif_carrier_ok(dev)) 2290 sky2_link_up(sky2); 2291 goto out; 2292 } 2293 2294 if (istatus & PHY_M_IS_LSP_CHANGE) 2295 sky2->speed = sky2_phy_speed(hw, phystat); 2296 2297 if (istatus & PHY_M_IS_DUP_CHANGE) 2298 sky2->duplex = 2299 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2300 2301 if (istatus & PHY_M_IS_LST_CHANGE) { 2302 if (phystat & PHY_M_PS_LINK_UP) 2303 sky2_link_up(sky2); 2304 else 2305 sky2_link_down(sky2); 2306 } 2307 out: 2308 spin_unlock(&sky2->phy_lock); 2309 } 2310 2311 /* Special quick link interrupt (Yukon-2 Optima only) */ 2312 static void sky2_qlink_intr(struct sky2_hw *hw) 2313 { 2314 struct sky2_port *sky2 = netdev_priv(hw->dev[0]); 2315 u32 imask; 2316 u16 phy; 2317 2318 /* disable irq */ 2319 imask = sky2_read32(hw, B0_IMSK); 2320 imask &= ~Y2_IS_PHY_QLNK; 2321 sky2_write32(hw, B0_IMSK, imask); 2322 2323 /* reset PHY Link Detect */ 2324 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); 2325 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2326 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); 2327 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2328 2329 sky2_link_up(sky2); 2330 } 2331 2332 /* Transmit timeout is only called if we are running, carrier is up 2333 * and tx queue is full (stopped). 2334 */ 2335 static void sky2_tx_timeout(struct net_device *dev) 2336 { 2337 struct sky2_port *sky2 = netdev_priv(dev); 2338 struct sky2_hw *hw = sky2->hw; 2339 2340 netif_err(sky2, timer, dev, "tx timeout\n"); 2341 2342 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", 2343 sky2->tx_cons, sky2->tx_prod, 2344 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 2345 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); 2346 2347 /* can't restart safely under softirq */ 2348 schedule_work(&hw->restart_work); 2349 } 2350 2351 static int sky2_change_mtu(struct net_device *dev, int new_mtu) 2352 { 2353 struct sky2_port *sky2 = netdev_priv(dev); 2354 struct sky2_hw *hw = sky2->hw; 2355 unsigned port = sky2->port; 2356 int err; 2357 u16 ctl, mode; 2358 u32 imask; 2359 2360 /* MTU size outside the spec */ 2361 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) 2362 return -EINVAL; 2363 2364 /* MTU > 1500 on yukon FE and FE+ not allowed */ 2365 if (new_mtu > ETH_DATA_LEN && 2366 (hw->chip_id == CHIP_ID_YUKON_FE || 2367 hw->chip_id == CHIP_ID_YUKON_FE_P)) 2368 return -EINVAL; 2369 2370 if (!netif_running(dev)) { 2371 dev->mtu = new_mtu; 2372 netdev_update_features(dev); 2373 return 0; 2374 } 2375 2376 imask = sky2_read32(hw, B0_IMSK); 2377 sky2_write32(hw, B0_IMSK, 0); 2378 2379 dev->trans_start = jiffies; /* prevent tx timeout */ 2380 napi_disable(&hw->napi); 2381 netif_tx_disable(dev); 2382 2383 synchronize_irq(hw->pdev->irq); 2384 2385 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) 2386 sky2_set_tx_stfwd(hw, port); 2387 2388 ctl = gma_read16(hw, port, GM_GP_CTRL); 2389 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); 2390 sky2_rx_stop(sky2); 2391 sky2_rx_clean(sky2); 2392 2393 dev->mtu = new_mtu; 2394 netdev_update_features(dev); 2395 2396 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA; 2397 if (sky2->speed > SPEED_100) 2398 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 2399 else 2400 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 2401 2402 if (dev->mtu > ETH_DATA_LEN) 2403 mode |= GM_SMOD_JUMBO_ENA; 2404 2405 gma_write16(hw, port, GM_SERIAL_MODE, mode); 2406 2407 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); 2408 2409 err = sky2_alloc_rx_skbs(sky2); 2410 if (!err) 2411 sky2_rx_start(sky2); 2412 else 2413 sky2_rx_clean(sky2); 2414 sky2_write32(hw, B0_IMSK, imask); 2415 2416 sky2_read32(hw, B0_Y2_SP_LISR); 2417 napi_enable(&hw->napi); 2418 2419 if (err) 2420 dev_close(dev); 2421 else { 2422 gma_write16(hw, port, GM_GP_CTRL, ctl); 2423 2424 netif_wake_queue(dev); 2425 } 2426 2427 return err; 2428 } 2429 2430 /* For small just reuse existing skb for next receive */ 2431 static struct sk_buff *receive_copy(struct sky2_port *sky2, 2432 const struct rx_ring_info *re, 2433 unsigned length) 2434 { 2435 struct sk_buff *skb; 2436 2437 skb = netdev_alloc_skb_ip_align(sky2->netdev, length); 2438 if (likely(skb)) { 2439 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, 2440 length, PCI_DMA_FROMDEVICE); 2441 skb_copy_from_linear_data(re->skb, skb->data, length); 2442 skb->ip_summed = re->skb->ip_summed; 2443 skb->csum = re->skb->csum; 2444 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, 2445 length, PCI_DMA_FROMDEVICE); 2446 re->skb->ip_summed = CHECKSUM_NONE; 2447 skb_put(skb, length); 2448 } 2449 return skb; 2450 } 2451 2452 /* Adjust length of skb with fragments to match received data */ 2453 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, 2454 unsigned int length) 2455 { 2456 int i, num_frags; 2457 unsigned int size; 2458 2459 /* put header into skb */ 2460 size = min(length, hdr_space); 2461 skb->tail += size; 2462 skb->len += size; 2463 length -= size; 2464 2465 num_frags = skb_shinfo(skb)->nr_frags; 2466 for (i = 0; i < num_frags; i++) { 2467 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2468 2469 if (length == 0) { 2470 /* don't need this page */ 2471 __skb_frag_unref(frag); 2472 --skb_shinfo(skb)->nr_frags; 2473 } else { 2474 size = min(length, (unsigned) PAGE_SIZE); 2475 2476 skb_frag_size_set(frag, size); 2477 skb->data_len += size; 2478 skb->truesize += PAGE_SIZE; 2479 skb->len += size; 2480 length -= size; 2481 } 2482 } 2483 } 2484 2485 /* Normal packet - take skb from ring element and put in a new one */ 2486 static struct sk_buff *receive_new(struct sky2_port *sky2, 2487 struct rx_ring_info *re, 2488 unsigned int length) 2489 { 2490 struct sk_buff *skb; 2491 struct rx_ring_info nre; 2492 unsigned hdr_space = sky2->rx_data_size; 2493 2494 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC); 2495 if (unlikely(!nre.skb)) 2496 goto nobuf; 2497 2498 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) 2499 goto nomap; 2500 2501 skb = re->skb; 2502 sky2_rx_unmap_skb(sky2->hw->pdev, re); 2503 prefetch(skb->data); 2504 *re = nre; 2505 2506 if (skb_shinfo(skb)->nr_frags) 2507 skb_put_frags(skb, hdr_space, length); 2508 else 2509 skb_put(skb, length); 2510 return skb; 2511 2512 nomap: 2513 dev_kfree_skb(nre.skb); 2514 nobuf: 2515 return NULL; 2516 } 2517 2518 /* 2519 * Receive one packet. 2520 * For larger packets, get new buffer. 2521 */ 2522 static struct sk_buff *sky2_receive(struct net_device *dev, 2523 u16 length, u32 status) 2524 { 2525 struct sky2_port *sky2 = netdev_priv(dev); 2526 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; 2527 struct sk_buff *skb = NULL; 2528 u16 count = (status & GMR_FS_LEN) >> 16; 2529 2530 if (status & GMR_FS_VLAN) 2531 count -= VLAN_HLEN; /* Account for vlan tag */ 2532 2533 netif_printk(sky2, rx_status, KERN_DEBUG, dev, 2534 "rx slot %u status 0x%x len %d\n", 2535 sky2->rx_next, status, length); 2536 2537 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 2538 prefetch(sky2->rx_ring + sky2->rx_next); 2539 2540 /* This chip has hardware problems that generates bogus status. 2541 * So do only marginal checking and expect higher level protocols 2542 * to handle crap frames. 2543 */ 2544 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && 2545 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && 2546 length != count) 2547 goto okay; 2548 2549 if (status & GMR_FS_ANY_ERR) 2550 goto error; 2551 2552 if (!(status & GMR_FS_RX_OK)) 2553 goto resubmit; 2554 2555 /* if length reported by DMA does not match PHY, packet was truncated */ 2556 if (length != count) 2557 goto error; 2558 2559 okay: 2560 if (length < copybreak) 2561 skb = receive_copy(sky2, re, length); 2562 else 2563 skb = receive_new(sky2, re, length); 2564 2565 dev->stats.rx_dropped += (skb == NULL); 2566 2567 resubmit: 2568 sky2_rx_submit(sky2, re); 2569 2570 return skb; 2571 2572 error: 2573 ++dev->stats.rx_errors; 2574 2575 if (net_ratelimit()) 2576 netif_info(sky2, rx_err, dev, 2577 "rx error, status 0x%x length %d\n", status, length); 2578 2579 goto resubmit; 2580 } 2581 2582 /* Transmit complete */ 2583 static inline void sky2_tx_done(struct net_device *dev, u16 last) 2584 { 2585 struct sky2_port *sky2 = netdev_priv(dev); 2586 2587 if (netif_running(dev)) { 2588 sky2_tx_complete(sky2, last); 2589 2590 /* Wake unless it's detached, and called e.g. from sky2_down() */ 2591 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) 2592 netif_wake_queue(dev); 2593 } 2594 } 2595 2596 static inline void sky2_skb_rx(const struct sky2_port *sky2, 2597 u32 status, struct sk_buff *skb) 2598 { 2599 if (status & GMR_FS_VLAN) 2600 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag)); 2601 2602 if (skb->ip_summed == CHECKSUM_NONE) 2603 netif_receive_skb(skb); 2604 else 2605 napi_gro_receive(&sky2->hw->napi, skb); 2606 } 2607 2608 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, 2609 unsigned packets, unsigned bytes) 2610 { 2611 struct net_device *dev = hw->dev[port]; 2612 struct sky2_port *sky2 = netdev_priv(dev); 2613 2614 if (packets == 0) 2615 return; 2616 2617 u64_stats_update_begin(&sky2->rx_stats.syncp); 2618 sky2->rx_stats.packets += packets; 2619 sky2->rx_stats.bytes += bytes; 2620 u64_stats_update_end(&sky2->rx_stats.syncp); 2621 2622 dev->last_rx = jiffies; 2623 sky2_rx_update(netdev_priv(dev), rxqaddr[port]); 2624 } 2625 2626 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) 2627 { 2628 /* If this happens then driver assuming wrong format for chip type */ 2629 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); 2630 2631 /* Both checksum counters are programmed to start at 2632 * the same offset, so unless there is a problem they 2633 * should match. This failure is an early indication that 2634 * hardware receive checksumming won't work. 2635 */ 2636 if (likely((u16)(status >> 16) == (u16)status)) { 2637 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; 2638 skb->ip_summed = CHECKSUM_COMPLETE; 2639 skb->csum = le16_to_cpu(status); 2640 } else { 2641 dev_notice(&sky2->hw->pdev->dev, 2642 "%s: receive checksum problem (status = %#x)\n", 2643 sky2->netdev->name, status); 2644 2645 /* Disable checksum offload 2646 * It will be reenabled on next ndo_set_features, but if it's 2647 * really broken, will get disabled again 2648 */ 2649 sky2->netdev->features &= ~NETIF_F_RXCSUM; 2650 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 2651 BMU_DIS_RX_CHKSUM); 2652 } 2653 } 2654 2655 static void sky2_rx_hash(struct sky2_port *sky2, u32 status) 2656 { 2657 struct sk_buff *skb; 2658 2659 skb = sky2->rx_ring[sky2->rx_next].skb; 2660 skb->rxhash = le32_to_cpu(status); 2661 } 2662 2663 /* Process status response ring */ 2664 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) 2665 { 2666 int work_done = 0; 2667 unsigned int total_bytes[2] = { 0 }; 2668 unsigned int total_packets[2] = { 0 }; 2669 2670 rmb(); 2671 do { 2672 struct sky2_port *sky2; 2673 struct sky2_status_le *le = hw->st_le + hw->st_idx; 2674 unsigned port; 2675 struct net_device *dev; 2676 struct sk_buff *skb; 2677 u32 status; 2678 u16 length; 2679 u8 opcode = le->opcode; 2680 2681 if (!(opcode & HW_OWNER)) 2682 break; 2683 2684 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); 2685 2686 port = le->css & CSS_LINK_BIT; 2687 dev = hw->dev[port]; 2688 sky2 = netdev_priv(dev); 2689 length = le16_to_cpu(le->length); 2690 status = le32_to_cpu(le->status); 2691 2692 le->opcode = 0; 2693 switch (opcode & ~HW_OWNER) { 2694 case OP_RXSTAT: 2695 total_packets[port]++; 2696 total_bytes[port] += length; 2697 2698 skb = sky2_receive(dev, length, status); 2699 if (!skb) 2700 break; 2701 2702 /* This chip reports checksum status differently */ 2703 if (hw->flags & SKY2_HW_NEW_LE) { 2704 if ((dev->features & NETIF_F_RXCSUM) && 2705 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && 2706 (le->css & CSS_TCPUDPCSOK)) 2707 skb->ip_summed = CHECKSUM_UNNECESSARY; 2708 else 2709 skb->ip_summed = CHECKSUM_NONE; 2710 } 2711 2712 skb->protocol = eth_type_trans(skb, dev); 2713 2714 sky2_skb_rx(sky2, status, skb); 2715 2716 /* Stop after net poll weight */ 2717 if (++work_done >= to_do) 2718 goto exit_loop; 2719 break; 2720 2721 case OP_RXVLAN: 2722 sky2->rx_tag = length; 2723 break; 2724 2725 case OP_RXCHKSVLAN: 2726 sky2->rx_tag = length; 2727 /* fall through */ 2728 case OP_RXCHKS: 2729 if (likely(dev->features & NETIF_F_RXCSUM)) 2730 sky2_rx_checksum(sky2, status); 2731 break; 2732 2733 case OP_RSS_HASH: 2734 sky2_rx_hash(sky2, status); 2735 break; 2736 2737 case OP_TXINDEXLE: 2738 /* TX index reports status for both ports */ 2739 sky2_tx_done(hw->dev[0], status & 0xfff); 2740 if (hw->dev[1]) 2741 sky2_tx_done(hw->dev[1], 2742 ((status >> 24) & 0xff) 2743 | (u16)(length & 0xf) << 8); 2744 break; 2745 2746 default: 2747 if (net_ratelimit()) 2748 pr_warning("unknown status opcode 0x%x\n", opcode); 2749 } 2750 } while (hw->st_idx != idx); 2751 2752 /* Fully processed status ring so clear irq */ 2753 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2754 2755 exit_loop: 2756 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); 2757 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); 2758 2759 return work_done; 2760 } 2761 2762 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) 2763 { 2764 struct net_device *dev = hw->dev[port]; 2765 2766 if (net_ratelimit()) 2767 netdev_info(dev, "hw error interrupt status 0x%x\n", status); 2768 2769 if (status & Y2_IS_PAR_RD1) { 2770 if (net_ratelimit()) 2771 netdev_err(dev, "ram data read parity error\n"); 2772 /* Clear IRQ */ 2773 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 2774 } 2775 2776 if (status & Y2_IS_PAR_WR1) { 2777 if (net_ratelimit()) 2778 netdev_err(dev, "ram data write parity error\n"); 2779 2780 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 2781 } 2782 2783 if (status & Y2_IS_PAR_MAC1) { 2784 if (net_ratelimit()) 2785 netdev_err(dev, "MAC parity error\n"); 2786 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 2787 } 2788 2789 if (status & Y2_IS_PAR_RX1) { 2790 if (net_ratelimit()) 2791 netdev_err(dev, "RX parity error\n"); 2792 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 2793 } 2794 2795 if (status & Y2_IS_TCP_TXA1) { 2796 if (net_ratelimit()) 2797 netdev_err(dev, "TCP segmentation error\n"); 2798 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 2799 } 2800 } 2801 2802 static void sky2_hw_intr(struct sky2_hw *hw) 2803 { 2804 struct pci_dev *pdev = hw->pdev; 2805 u32 status = sky2_read32(hw, B0_HWE_ISRC); 2806 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2807 2808 status &= hwmsk; 2809 2810 if (status & Y2_IS_TIST_OV) 2811 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2812 2813 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2814 u16 pci_err; 2815 2816 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2817 pci_err = sky2_pci_read16(hw, PCI_STATUS); 2818 if (net_ratelimit()) 2819 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", 2820 pci_err); 2821 2822 sky2_pci_write16(hw, PCI_STATUS, 2823 pci_err | PCI_STATUS_ERROR_BITS); 2824 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2825 } 2826 2827 if (status & Y2_IS_PCI_EXP) { 2828 /* PCI-Express uncorrectable Error occurred */ 2829 u32 err; 2830 2831 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2832 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2833 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 2834 0xfffffffful); 2835 if (net_ratelimit()) 2836 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); 2837 2838 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2839 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2840 } 2841 2842 if (status & Y2_HWE_L1_MASK) 2843 sky2_hw_error(hw, 0, status); 2844 status >>= 8; 2845 if (status & Y2_HWE_L1_MASK) 2846 sky2_hw_error(hw, 1, status); 2847 } 2848 2849 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) 2850 { 2851 struct net_device *dev = hw->dev[port]; 2852 struct sky2_port *sky2 = netdev_priv(dev); 2853 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2854 2855 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); 2856 2857 if (status & GM_IS_RX_CO_OV) 2858 gma_read16(hw, port, GM_RX_IRQ_SRC); 2859 2860 if (status & GM_IS_TX_CO_OV) 2861 gma_read16(hw, port, GM_TX_IRQ_SRC); 2862 2863 if (status & GM_IS_RX_FF_OR) { 2864 ++dev->stats.rx_fifo_errors; 2865 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2866 } 2867 2868 if (status & GM_IS_TX_FF_UR) { 2869 ++dev->stats.tx_fifo_errors; 2870 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2871 } 2872 } 2873 2874 /* This should never happen it is a bug. */ 2875 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) 2876 { 2877 struct net_device *dev = hw->dev[port]; 2878 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); 2879 2880 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", 2881 dev->name, (unsigned) q, (unsigned) idx, 2882 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); 2883 2884 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); 2885 } 2886 2887 static int sky2_rx_hung(struct net_device *dev) 2888 { 2889 struct sky2_port *sky2 = netdev_priv(dev); 2890 struct sky2_hw *hw = sky2->hw; 2891 unsigned port = sky2->port; 2892 unsigned rxq = rxqaddr[port]; 2893 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); 2894 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); 2895 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); 2896 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); 2897 2898 /* If idle and MAC or PCI is stuck */ 2899 if (sky2->check.last == dev->last_rx && 2900 ((mac_rp == sky2->check.mac_rp && 2901 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || 2902 /* Check if the PCI RX hang */ 2903 (fifo_rp == sky2->check.fifo_rp && 2904 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { 2905 netdev_printk(KERN_DEBUG, dev, 2906 "hung mac %d:%d fifo %d (%d:%d)\n", 2907 mac_lev, mac_rp, fifo_lev, 2908 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); 2909 return 1; 2910 } else { 2911 sky2->check.last = dev->last_rx; 2912 sky2->check.mac_rp = mac_rp; 2913 sky2->check.mac_lev = mac_lev; 2914 sky2->check.fifo_rp = fifo_rp; 2915 sky2->check.fifo_lev = fifo_lev; 2916 return 0; 2917 } 2918 } 2919 2920 static void sky2_watchdog(unsigned long arg) 2921 { 2922 struct sky2_hw *hw = (struct sky2_hw *) arg; 2923 2924 /* Check for lost IRQ once a second */ 2925 if (sky2_read32(hw, B0_ISRC)) { 2926 napi_schedule(&hw->napi); 2927 } else { 2928 int i, active = 0; 2929 2930 for (i = 0; i < hw->ports; i++) { 2931 struct net_device *dev = hw->dev[i]; 2932 if (!netif_running(dev)) 2933 continue; 2934 ++active; 2935 2936 /* For chips with Rx FIFO, check if stuck */ 2937 if ((hw->flags & SKY2_HW_RAM_BUFFER) && 2938 sky2_rx_hung(dev)) { 2939 netdev_info(dev, "receiver hang detected\n"); 2940 schedule_work(&hw->restart_work); 2941 return; 2942 } 2943 } 2944 2945 if (active == 0) 2946 return; 2947 } 2948 2949 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); 2950 } 2951 2952 /* Hardware/software error handling */ 2953 static void sky2_err_intr(struct sky2_hw *hw, u32 status) 2954 { 2955 if (net_ratelimit()) 2956 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); 2957 2958 if (status & Y2_IS_HW_ERR) 2959 sky2_hw_intr(hw); 2960 2961 if (status & Y2_IS_IRQ_MAC1) 2962 sky2_mac_intr(hw, 0); 2963 2964 if (status & Y2_IS_IRQ_MAC2) 2965 sky2_mac_intr(hw, 1); 2966 2967 if (status & Y2_IS_CHK_RX1) 2968 sky2_le_error(hw, 0, Q_R1); 2969 2970 if (status & Y2_IS_CHK_RX2) 2971 sky2_le_error(hw, 1, Q_R2); 2972 2973 if (status & Y2_IS_CHK_TXA1) 2974 sky2_le_error(hw, 0, Q_XA1); 2975 2976 if (status & Y2_IS_CHK_TXA2) 2977 sky2_le_error(hw, 1, Q_XA2); 2978 } 2979 2980 static int sky2_poll(struct napi_struct *napi, int work_limit) 2981 { 2982 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); 2983 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 2984 int work_done = 0; 2985 u16 idx; 2986 2987 if (unlikely(status & Y2_IS_ERROR)) 2988 sky2_err_intr(hw, status); 2989 2990 if (status & Y2_IS_IRQ_PHY1) 2991 sky2_phy_intr(hw, 0); 2992 2993 if (status & Y2_IS_IRQ_PHY2) 2994 sky2_phy_intr(hw, 1); 2995 2996 if (status & Y2_IS_PHY_QLNK) 2997 sky2_qlink_intr(hw); 2998 2999 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { 3000 work_done += sky2_status_intr(hw, work_limit - work_done, idx); 3001 3002 if (work_done >= work_limit) 3003 goto done; 3004 } 3005 3006 napi_complete(napi); 3007 sky2_read32(hw, B0_Y2_SP_LISR); 3008 done: 3009 3010 return work_done; 3011 } 3012 3013 static irqreturn_t sky2_intr(int irq, void *dev_id) 3014 { 3015 struct sky2_hw *hw = dev_id; 3016 u32 status; 3017 3018 /* Reading this mask interrupts as side effect */ 3019 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 3020 if (status == 0 || status == ~0) 3021 return IRQ_NONE; 3022 3023 prefetch(&hw->st_le[hw->st_idx]); 3024 3025 napi_schedule(&hw->napi); 3026 3027 return IRQ_HANDLED; 3028 } 3029 3030 #ifdef CONFIG_NET_POLL_CONTROLLER 3031 static void sky2_netpoll(struct net_device *dev) 3032 { 3033 struct sky2_port *sky2 = netdev_priv(dev); 3034 3035 napi_schedule(&sky2->hw->napi); 3036 } 3037 #endif 3038 3039 /* Chip internal frequency for clock calculations */ 3040 static u32 sky2_mhz(const struct sky2_hw *hw) 3041 { 3042 switch (hw->chip_id) { 3043 case CHIP_ID_YUKON_EC: 3044 case CHIP_ID_YUKON_EC_U: 3045 case CHIP_ID_YUKON_EX: 3046 case CHIP_ID_YUKON_SUPR: 3047 case CHIP_ID_YUKON_UL_2: 3048 case CHIP_ID_YUKON_OPT: 3049 case CHIP_ID_YUKON_PRM: 3050 case CHIP_ID_YUKON_OP_2: 3051 return 125; 3052 3053 case CHIP_ID_YUKON_FE: 3054 return 100; 3055 3056 case CHIP_ID_YUKON_FE_P: 3057 return 50; 3058 3059 case CHIP_ID_YUKON_XL: 3060 return 156; 3061 3062 default: 3063 BUG(); 3064 } 3065 } 3066 3067 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) 3068 { 3069 return sky2_mhz(hw) * us; 3070 } 3071 3072 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) 3073 { 3074 return clk / sky2_mhz(hw); 3075 } 3076 3077 3078 static int __devinit sky2_init(struct sky2_hw *hw) 3079 { 3080 u8 t8; 3081 3082 /* Enable all clocks and check for bad PCI access */ 3083 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 3084 3085 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3086 3087 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 3088 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 3089 3090 switch (hw->chip_id) { 3091 case CHIP_ID_YUKON_XL: 3092 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; 3093 if (hw->chip_rev < CHIP_REV_YU_XL_A2) 3094 hw->flags |= SKY2_HW_RSS_BROKEN; 3095 break; 3096 3097 case CHIP_ID_YUKON_EC_U: 3098 hw->flags = SKY2_HW_GIGABIT 3099 | SKY2_HW_NEWER_PHY 3100 | SKY2_HW_ADV_POWER_CTL; 3101 break; 3102 3103 case CHIP_ID_YUKON_EX: 3104 hw->flags = SKY2_HW_GIGABIT 3105 | SKY2_HW_NEWER_PHY 3106 | SKY2_HW_NEW_LE 3107 | SKY2_HW_ADV_POWER_CTL 3108 | SKY2_HW_RSS_CHKSUM; 3109 3110 /* New transmit checksum */ 3111 if (hw->chip_rev != CHIP_REV_YU_EX_B0) 3112 hw->flags |= SKY2_HW_AUTO_TX_SUM; 3113 break; 3114 3115 case CHIP_ID_YUKON_EC: 3116 /* This rev is really old, and requires untested workarounds */ 3117 if (hw->chip_rev == CHIP_REV_YU_EC_A1) { 3118 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); 3119 return -EOPNOTSUPP; 3120 } 3121 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; 3122 break; 3123 3124 case CHIP_ID_YUKON_FE: 3125 hw->flags = SKY2_HW_RSS_BROKEN; 3126 break; 3127 3128 case CHIP_ID_YUKON_FE_P: 3129 hw->flags = SKY2_HW_NEWER_PHY 3130 | SKY2_HW_NEW_LE 3131 | SKY2_HW_AUTO_TX_SUM 3132 | SKY2_HW_ADV_POWER_CTL; 3133 3134 /* The workaround for status conflicts VLAN tag detection. */ 3135 if (hw->chip_rev == CHIP_REV_YU_FE2_A0) 3136 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; 3137 break; 3138 3139 case CHIP_ID_YUKON_SUPR: 3140 hw->flags = SKY2_HW_GIGABIT 3141 | SKY2_HW_NEWER_PHY 3142 | SKY2_HW_NEW_LE 3143 | SKY2_HW_AUTO_TX_SUM 3144 | SKY2_HW_ADV_POWER_CTL; 3145 3146 if (hw->chip_rev == CHIP_REV_YU_SU_A0) 3147 hw->flags |= SKY2_HW_RSS_CHKSUM; 3148 break; 3149 3150 case CHIP_ID_YUKON_UL_2: 3151 hw->flags = SKY2_HW_GIGABIT 3152 | SKY2_HW_ADV_POWER_CTL; 3153 break; 3154 3155 case CHIP_ID_YUKON_OPT: 3156 case CHIP_ID_YUKON_PRM: 3157 case CHIP_ID_YUKON_OP_2: 3158 hw->flags = SKY2_HW_GIGABIT 3159 | SKY2_HW_NEW_LE 3160 | SKY2_HW_ADV_POWER_CTL; 3161 break; 3162 3163 default: 3164 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3165 hw->chip_id); 3166 return -EOPNOTSUPP; 3167 } 3168 3169 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 3170 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') 3171 hw->flags |= SKY2_HW_FIBRE_PHY; 3172 3173 hw->ports = 1; 3174 t8 = sky2_read8(hw, B2_Y2_HW_RES); 3175 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 3176 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 3177 ++hw->ports; 3178 } 3179 3180 if (sky2_read8(hw, B2_E_0)) 3181 hw->flags |= SKY2_HW_RAM_BUFFER; 3182 3183 return 0; 3184 } 3185 3186 static void sky2_reset(struct sky2_hw *hw) 3187 { 3188 struct pci_dev *pdev = hw->pdev; 3189 u16 status; 3190 int i; 3191 u32 hwe_mask = Y2_HWE_ALL_MASK; 3192 3193 /* disable ASF */ 3194 if (hw->chip_id == CHIP_ID_YUKON_EX 3195 || hw->chip_id == CHIP_ID_YUKON_SUPR) { 3196 sky2_write32(hw, CPU_WDOG, 0); 3197 status = sky2_read16(hw, HCU_CCSR); 3198 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | 3199 HCU_CCSR_UC_STATE_MSK); 3200 /* 3201 * CPU clock divider shouldn't be used because 3202 * - ASF firmware may malfunction 3203 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks 3204 */ 3205 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; 3206 sky2_write16(hw, HCU_CCSR, status); 3207 sky2_write32(hw, CPU_WDOG, 0); 3208 } else 3209 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 3210 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 3211 3212 /* do a SW reset */ 3213 sky2_write8(hw, B0_CTST, CS_RST_SET); 3214 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3215 3216 /* allow writes to PCI config */ 3217 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3218 3219 /* clear PCI errors, if any */ 3220 status = sky2_pci_read16(hw, PCI_STATUS); 3221 status |= PCI_STATUS_ERROR_BITS; 3222 sky2_pci_write16(hw, PCI_STATUS, status); 3223 3224 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 3225 3226 if (pci_is_pcie(pdev)) { 3227 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 3228 0xfffffffful); 3229 3230 /* If error bit is stuck on ignore it */ 3231 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) 3232 dev_info(&pdev->dev, "ignoring stuck error report bit\n"); 3233 else 3234 hwe_mask |= Y2_IS_PCI_EXP; 3235 } 3236 3237 sky2_power_on(hw); 3238 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3239 3240 for (i = 0; i < hw->ports; i++) { 3241 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3242 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3243 3244 if (hw->chip_id == CHIP_ID_YUKON_EX || 3245 hw->chip_id == CHIP_ID_YUKON_SUPR) 3246 sky2_write16(hw, SK_REG(i, GMAC_CTRL), 3247 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON 3248 | GMC_BYP_RETR_ON); 3249 3250 } 3251 3252 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { 3253 /* enable MACSec clock gating */ 3254 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); 3255 } 3256 3257 if (hw->chip_id == CHIP_ID_YUKON_OPT || 3258 hw->chip_id == CHIP_ID_YUKON_PRM || 3259 hw->chip_id == CHIP_ID_YUKON_OP_2) { 3260 u16 reg; 3261 u32 msk; 3262 3263 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 3264 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ 3265 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); 3266 3267 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ 3268 reg = 10; 3269 3270 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3271 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3272 } else { 3273 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ 3274 reg = 3; 3275 } 3276 3277 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; 3278 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; 3279 3280 /* reset PHY Link Detect */ 3281 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3282 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); 3283 3284 /* enable PHY Quick Link */ 3285 msk = sky2_read32(hw, B0_IMSK); 3286 msk |= Y2_IS_PHY_QLNK; 3287 sky2_write32(hw, B0_IMSK, msk); 3288 3289 /* check if PSMv2 was running before */ 3290 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); 3291 if (reg & PCI_EXP_LNKCTL_ASPMC) 3292 /* restore the PCIe Link Control register */ 3293 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, 3294 reg); 3295 3296 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3297 3298 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3299 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3300 } 3301 3302 /* Clear I2C IRQ noise */ 3303 sky2_write32(hw, B2_I2C_IRQ, 1); 3304 3305 /* turn off hardware timer (unused) */ 3306 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 3307 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3308 3309 /* Turn off descriptor polling */ 3310 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 3311 3312 /* Turn off receive timestamp */ 3313 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 3314 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3315 3316 /* enable the Tx Arbiters */ 3317 for (i = 0; i < hw->ports; i++) 3318 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3319 3320 /* Initialize ram interface */ 3321 for (i = 0; i < hw->ports; i++) { 3322 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 3323 3324 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 3325 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 3326 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 3327 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 3328 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 3329 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 3330 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 3331 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 3332 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 3333 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 3334 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 3335 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 3336 } 3337 3338 sky2_write32(hw, B0_HWE_IMSK, hwe_mask); 3339 3340 for (i = 0; i < hw->ports; i++) 3341 sky2_gmac_reset(hw, i); 3342 3343 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); 3344 hw->st_idx = 0; 3345 3346 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 3347 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 3348 3349 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 3350 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 3351 3352 /* Set the list last index */ 3353 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); 3354 3355 sky2_write16(hw, STAT_TX_IDX_TH, 10); 3356 sky2_write8(hw, STAT_FIFO_WM, 16); 3357 3358 /* set Status-FIFO ISR watermark */ 3359 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 3360 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 3361 else 3362 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 3363 3364 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 3365 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); 3366 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 3367 3368 /* enable status unit */ 3369 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 3370 3371 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 3372 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 3373 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 3374 } 3375 3376 /* Take device down (offline). 3377 * Equivalent to doing dev_stop() but this does not 3378 * inform upper layers of the transition. 3379 */ 3380 static void sky2_detach(struct net_device *dev) 3381 { 3382 if (netif_running(dev)) { 3383 netif_tx_lock(dev); 3384 netif_device_detach(dev); /* stop txq */ 3385 netif_tx_unlock(dev); 3386 sky2_down(dev); 3387 } 3388 } 3389 3390 /* Bring device back after doing sky2_detach */ 3391 static int sky2_reattach(struct net_device *dev) 3392 { 3393 int err = 0; 3394 3395 if (netif_running(dev)) { 3396 err = sky2_up(dev); 3397 if (err) { 3398 netdev_info(dev, "could not restart %d\n", err); 3399 dev_close(dev); 3400 } else { 3401 netif_device_attach(dev); 3402 sky2_set_multicast(dev); 3403 } 3404 } 3405 3406 return err; 3407 } 3408 3409 static void sky2_all_down(struct sky2_hw *hw) 3410 { 3411 int i; 3412 3413 sky2_read32(hw, B0_IMSK); 3414 sky2_write32(hw, B0_IMSK, 0); 3415 synchronize_irq(hw->pdev->irq); 3416 napi_disable(&hw->napi); 3417 3418 for (i = 0; i < hw->ports; i++) { 3419 struct net_device *dev = hw->dev[i]; 3420 struct sky2_port *sky2 = netdev_priv(dev); 3421 3422 if (!netif_running(dev)) 3423 continue; 3424 3425 netif_carrier_off(dev); 3426 netif_tx_disable(dev); 3427 sky2_hw_down(sky2); 3428 } 3429 } 3430 3431 static void sky2_all_up(struct sky2_hw *hw) 3432 { 3433 u32 imask = Y2_IS_BASE; 3434 int i; 3435 3436 for (i = 0; i < hw->ports; i++) { 3437 struct net_device *dev = hw->dev[i]; 3438 struct sky2_port *sky2 = netdev_priv(dev); 3439 3440 if (!netif_running(dev)) 3441 continue; 3442 3443 sky2_hw_up(sky2); 3444 sky2_set_multicast(dev); 3445 imask |= portirq_msk[i]; 3446 netif_wake_queue(dev); 3447 } 3448 3449 sky2_write32(hw, B0_IMSK, imask); 3450 sky2_read32(hw, B0_IMSK); 3451 3452 sky2_read32(hw, B0_Y2_SP_LISR); 3453 napi_enable(&hw->napi); 3454 } 3455 3456 static void sky2_restart(struct work_struct *work) 3457 { 3458 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); 3459 3460 rtnl_lock(); 3461 3462 sky2_all_down(hw); 3463 sky2_reset(hw); 3464 sky2_all_up(hw); 3465 3466 rtnl_unlock(); 3467 } 3468 3469 static inline u8 sky2_wol_supported(const struct sky2_hw *hw) 3470 { 3471 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; 3472 } 3473 3474 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3475 { 3476 const struct sky2_port *sky2 = netdev_priv(dev); 3477 3478 wol->supported = sky2_wol_supported(sky2->hw); 3479 wol->wolopts = sky2->wol; 3480 } 3481 3482 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3483 { 3484 struct sky2_port *sky2 = netdev_priv(dev); 3485 struct sky2_hw *hw = sky2->hw; 3486 bool enable_wakeup = false; 3487 int i; 3488 3489 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || 3490 !device_can_wakeup(&hw->pdev->dev)) 3491 return -EOPNOTSUPP; 3492 3493 sky2->wol = wol->wolopts; 3494 3495 for (i = 0; i < hw->ports; i++) { 3496 struct net_device *dev = hw->dev[i]; 3497 struct sky2_port *sky2 = netdev_priv(dev); 3498 3499 if (sky2->wol) 3500 enable_wakeup = true; 3501 } 3502 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); 3503 3504 return 0; 3505 } 3506 3507 static u32 sky2_supported_modes(const struct sky2_hw *hw) 3508 { 3509 if (sky2_is_copper(hw)) { 3510 u32 modes = SUPPORTED_10baseT_Half 3511 | SUPPORTED_10baseT_Full 3512 | SUPPORTED_100baseT_Half 3513 | SUPPORTED_100baseT_Full; 3514 3515 if (hw->flags & SKY2_HW_GIGABIT) 3516 modes |= SUPPORTED_1000baseT_Half 3517 | SUPPORTED_1000baseT_Full; 3518 return modes; 3519 } else 3520 return SUPPORTED_1000baseT_Half 3521 | SUPPORTED_1000baseT_Full; 3522 } 3523 3524 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3525 { 3526 struct sky2_port *sky2 = netdev_priv(dev); 3527 struct sky2_hw *hw = sky2->hw; 3528 3529 ecmd->transceiver = XCVR_INTERNAL; 3530 ecmd->supported = sky2_supported_modes(hw); 3531 ecmd->phy_address = PHY_ADDR_MARV; 3532 if (sky2_is_copper(hw)) { 3533 ecmd->port = PORT_TP; 3534 ethtool_cmd_speed_set(ecmd, sky2->speed); 3535 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP; 3536 } else { 3537 ethtool_cmd_speed_set(ecmd, SPEED_1000); 3538 ecmd->port = PORT_FIBRE; 3539 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; 3540 } 3541 3542 ecmd->advertising = sky2->advertising; 3543 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) 3544 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3545 ecmd->duplex = sky2->duplex; 3546 return 0; 3547 } 3548 3549 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3550 { 3551 struct sky2_port *sky2 = netdev_priv(dev); 3552 const struct sky2_hw *hw = sky2->hw; 3553 u32 supported = sky2_supported_modes(hw); 3554 3555 if (ecmd->autoneg == AUTONEG_ENABLE) { 3556 if (ecmd->advertising & ~supported) 3557 return -EINVAL; 3558 3559 if (sky2_is_copper(hw)) 3560 sky2->advertising = ecmd->advertising | 3561 ADVERTISED_TP | 3562 ADVERTISED_Autoneg; 3563 else 3564 sky2->advertising = ecmd->advertising | 3565 ADVERTISED_FIBRE | 3566 ADVERTISED_Autoneg; 3567 3568 sky2->flags |= SKY2_FLAG_AUTO_SPEED; 3569 sky2->duplex = -1; 3570 sky2->speed = -1; 3571 } else { 3572 u32 setting; 3573 u32 speed = ethtool_cmd_speed(ecmd); 3574 3575 switch (speed) { 3576 case SPEED_1000: 3577 if (ecmd->duplex == DUPLEX_FULL) 3578 setting = SUPPORTED_1000baseT_Full; 3579 else if (ecmd->duplex == DUPLEX_HALF) 3580 setting = SUPPORTED_1000baseT_Half; 3581 else 3582 return -EINVAL; 3583 break; 3584 case SPEED_100: 3585 if (ecmd->duplex == DUPLEX_FULL) 3586 setting = SUPPORTED_100baseT_Full; 3587 else if (ecmd->duplex == DUPLEX_HALF) 3588 setting = SUPPORTED_100baseT_Half; 3589 else 3590 return -EINVAL; 3591 break; 3592 3593 case SPEED_10: 3594 if (ecmd->duplex == DUPLEX_FULL) 3595 setting = SUPPORTED_10baseT_Full; 3596 else if (ecmd->duplex == DUPLEX_HALF) 3597 setting = SUPPORTED_10baseT_Half; 3598 else 3599 return -EINVAL; 3600 break; 3601 default: 3602 return -EINVAL; 3603 } 3604 3605 if ((setting & supported) == 0) 3606 return -EINVAL; 3607 3608 sky2->speed = speed; 3609 sky2->duplex = ecmd->duplex; 3610 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; 3611 } 3612 3613 if (netif_running(dev)) { 3614 sky2_phy_reinit(sky2); 3615 sky2_set_multicast(dev); 3616 } 3617 3618 return 0; 3619 } 3620 3621 static void sky2_get_drvinfo(struct net_device *dev, 3622 struct ethtool_drvinfo *info) 3623 { 3624 struct sky2_port *sky2 = netdev_priv(dev); 3625 3626 strcpy(info->driver, DRV_NAME); 3627 strcpy(info->version, DRV_VERSION); 3628 strcpy(info->fw_version, "N/A"); 3629 strcpy(info->bus_info, pci_name(sky2->hw->pdev)); 3630 } 3631 3632 static const struct sky2_stat { 3633 char name[ETH_GSTRING_LEN]; 3634 u16 offset; 3635 } sky2_stats[] = { 3636 { "tx_bytes", GM_TXO_OK_HI }, 3637 { "rx_bytes", GM_RXO_OK_HI }, 3638 { "tx_broadcast", GM_TXF_BC_OK }, 3639 { "rx_broadcast", GM_RXF_BC_OK }, 3640 { "tx_multicast", GM_TXF_MC_OK }, 3641 { "rx_multicast", GM_RXF_MC_OK }, 3642 { "tx_unicast", GM_TXF_UC_OK }, 3643 { "rx_unicast", GM_RXF_UC_OK }, 3644 { "tx_mac_pause", GM_TXF_MPAUSE }, 3645 { "rx_mac_pause", GM_RXF_MPAUSE }, 3646 { "collisions", GM_TXF_COL }, 3647 { "late_collision",GM_TXF_LAT_COL }, 3648 { "aborted", GM_TXF_ABO_COL }, 3649 { "single_collisions", GM_TXF_SNG_COL }, 3650 { "multi_collisions", GM_TXF_MUL_COL }, 3651 3652 { "rx_short", GM_RXF_SHT }, 3653 { "rx_runt", GM_RXE_FRAG }, 3654 { "rx_64_byte_packets", GM_RXF_64B }, 3655 { "rx_65_to_127_byte_packets", GM_RXF_127B }, 3656 { "rx_128_to_255_byte_packets", GM_RXF_255B }, 3657 { "rx_256_to_511_byte_packets", GM_RXF_511B }, 3658 { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, 3659 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, 3660 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, 3661 { "rx_too_long", GM_RXF_LNG_ERR }, 3662 { "rx_fifo_overflow", GM_RXE_FIFO_OV }, 3663 { "rx_jabber", GM_RXF_JAB_PKT }, 3664 { "rx_fcs_error", GM_RXF_FCS_ERR }, 3665 3666 { "tx_64_byte_packets", GM_TXF_64B }, 3667 { "tx_65_to_127_byte_packets", GM_TXF_127B }, 3668 { "tx_128_to_255_byte_packets", GM_TXF_255B }, 3669 { "tx_256_to_511_byte_packets", GM_TXF_511B }, 3670 { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, 3671 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, 3672 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, 3673 { "tx_fifo_underrun", GM_TXE_FIFO_UR }, 3674 }; 3675 3676 static u32 sky2_get_msglevel(struct net_device *netdev) 3677 { 3678 struct sky2_port *sky2 = netdev_priv(netdev); 3679 return sky2->msg_enable; 3680 } 3681 3682 static int sky2_nway_reset(struct net_device *dev) 3683 { 3684 struct sky2_port *sky2 = netdev_priv(dev); 3685 3686 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) 3687 return -EINVAL; 3688 3689 sky2_phy_reinit(sky2); 3690 sky2_set_multicast(dev); 3691 3692 return 0; 3693 } 3694 3695 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) 3696 { 3697 struct sky2_hw *hw = sky2->hw; 3698 unsigned port = sky2->port; 3699 int i; 3700 3701 data[0] = get_stats64(hw, port, GM_TXO_OK_LO); 3702 data[1] = get_stats64(hw, port, GM_RXO_OK_LO); 3703 3704 for (i = 2; i < count; i++) 3705 data[i] = get_stats32(hw, port, sky2_stats[i].offset); 3706 } 3707 3708 static void sky2_set_msglevel(struct net_device *netdev, u32 value) 3709 { 3710 struct sky2_port *sky2 = netdev_priv(netdev); 3711 sky2->msg_enable = value; 3712 } 3713 3714 static int sky2_get_sset_count(struct net_device *dev, int sset) 3715 { 3716 switch (sset) { 3717 case ETH_SS_STATS: 3718 return ARRAY_SIZE(sky2_stats); 3719 default: 3720 return -EOPNOTSUPP; 3721 } 3722 } 3723 3724 static void sky2_get_ethtool_stats(struct net_device *dev, 3725 struct ethtool_stats *stats, u64 * data) 3726 { 3727 struct sky2_port *sky2 = netdev_priv(dev); 3728 3729 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); 3730 } 3731 3732 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) 3733 { 3734 int i; 3735 3736 switch (stringset) { 3737 case ETH_SS_STATS: 3738 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) 3739 memcpy(data + i * ETH_GSTRING_LEN, 3740 sky2_stats[i].name, ETH_GSTRING_LEN); 3741 break; 3742 } 3743 } 3744 3745 static int sky2_set_mac_address(struct net_device *dev, void *p) 3746 { 3747 struct sky2_port *sky2 = netdev_priv(dev); 3748 struct sky2_hw *hw = sky2->hw; 3749 unsigned port = sky2->port; 3750 const struct sockaddr *addr = p; 3751 3752 if (!is_valid_ether_addr(addr->sa_data)) 3753 return -EADDRNOTAVAIL; 3754 3755 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 3756 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, 3757 dev->dev_addr, ETH_ALEN); 3758 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, 3759 dev->dev_addr, ETH_ALEN); 3760 3761 /* virtual address for data */ 3762 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3763 3764 /* physical address: used for pause frames */ 3765 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3766 3767 return 0; 3768 } 3769 3770 static inline void sky2_add_filter(u8 filter[8], const u8 *addr) 3771 { 3772 u32 bit; 3773 3774 bit = ether_crc(ETH_ALEN, addr) & 63; 3775 filter[bit >> 3] |= 1 << (bit & 7); 3776 } 3777 3778 static void sky2_set_multicast(struct net_device *dev) 3779 { 3780 struct sky2_port *sky2 = netdev_priv(dev); 3781 struct sky2_hw *hw = sky2->hw; 3782 unsigned port = sky2->port; 3783 struct netdev_hw_addr *ha; 3784 u16 reg; 3785 u8 filter[8]; 3786 int rx_pause; 3787 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 3788 3789 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); 3790 memset(filter, 0, sizeof(filter)); 3791 3792 reg = gma_read16(hw, port, GM_RX_CTRL); 3793 reg |= GM_RXCR_UCF_ENA; 3794 3795 if (dev->flags & IFF_PROMISC) /* promiscuous */ 3796 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 3797 else if (dev->flags & IFF_ALLMULTI) 3798 memset(filter, 0xff, sizeof(filter)); 3799 else if (netdev_mc_empty(dev) && !rx_pause) 3800 reg &= ~GM_RXCR_MCF_ENA; 3801 else { 3802 reg |= GM_RXCR_MCF_ENA; 3803 3804 if (rx_pause) 3805 sky2_add_filter(filter, pause_mc_addr); 3806 3807 netdev_for_each_mc_addr(ha, dev) 3808 sky2_add_filter(filter, ha->addr); 3809 } 3810 3811 gma_write16(hw, port, GM_MC_ADDR_H1, 3812 (u16) filter[0] | ((u16) filter[1] << 8)); 3813 gma_write16(hw, port, GM_MC_ADDR_H2, 3814 (u16) filter[2] | ((u16) filter[3] << 8)); 3815 gma_write16(hw, port, GM_MC_ADDR_H3, 3816 (u16) filter[4] | ((u16) filter[5] << 8)); 3817 gma_write16(hw, port, GM_MC_ADDR_H4, 3818 (u16) filter[6] | ((u16) filter[7] << 8)); 3819 3820 gma_write16(hw, port, GM_RX_CTRL, reg); 3821 } 3822 3823 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev, 3824 struct rtnl_link_stats64 *stats) 3825 { 3826 struct sky2_port *sky2 = netdev_priv(dev); 3827 struct sky2_hw *hw = sky2->hw; 3828 unsigned port = sky2->port; 3829 unsigned int start; 3830 u64 _bytes, _packets; 3831 3832 do { 3833 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp); 3834 _bytes = sky2->rx_stats.bytes; 3835 _packets = sky2->rx_stats.packets; 3836 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start)); 3837 3838 stats->rx_packets = _packets; 3839 stats->rx_bytes = _bytes; 3840 3841 do { 3842 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp); 3843 _bytes = sky2->tx_stats.bytes; 3844 _packets = sky2->tx_stats.packets; 3845 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start)); 3846 3847 stats->tx_packets = _packets; 3848 stats->tx_bytes = _bytes; 3849 3850 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) 3851 + get_stats32(hw, port, GM_RXF_BC_OK); 3852 3853 stats->collisions = get_stats32(hw, port, GM_TXF_COL); 3854 3855 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); 3856 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); 3857 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) 3858 + get_stats32(hw, port, GM_RXE_FRAG); 3859 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); 3860 3861 stats->rx_dropped = dev->stats.rx_dropped; 3862 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 3863 stats->tx_fifo_errors = dev->stats.tx_fifo_errors; 3864 3865 return stats; 3866 } 3867 3868 /* Can have one global because blinking is controlled by 3869 * ethtool and that is always under RTNL mutex 3870 */ 3871 static void sky2_led(struct sky2_port *sky2, enum led_mode mode) 3872 { 3873 struct sky2_hw *hw = sky2->hw; 3874 unsigned port = sky2->port; 3875 3876 spin_lock_bh(&sky2->phy_lock); 3877 if (hw->chip_id == CHIP_ID_YUKON_EC_U || 3878 hw->chip_id == CHIP_ID_YUKON_EX || 3879 hw->chip_id == CHIP_ID_YUKON_SUPR) { 3880 u16 pg; 3881 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3882 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3883 3884 switch (mode) { 3885 case MO_LED_OFF: 3886 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3887 PHY_M_LEDC_LOS_CTRL(8) | 3888 PHY_M_LEDC_INIT_CTRL(8) | 3889 PHY_M_LEDC_STA1_CTRL(8) | 3890 PHY_M_LEDC_STA0_CTRL(8)); 3891 break; 3892 case MO_LED_ON: 3893 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3894 PHY_M_LEDC_LOS_CTRL(9) | 3895 PHY_M_LEDC_INIT_CTRL(9) | 3896 PHY_M_LEDC_STA1_CTRL(9) | 3897 PHY_M_LEDC_STA0_CTRL(9)); 3898 break; 3899 case MO_LED_BLINK: 3900 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3901 PHY_M_LEDC_LOS_CTRL(0xa) | 3902 PHY_M_LEDC_INIT_CTRL(0xa) | 3903 PHY_M_LEDC_STA1_CTRL(0xa) | 3904 PHY_M_LEDC_STA0_CTRL(0xa)); 3905 break; 3906 case MO_LED_NORM: 3907 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3908 PHY_M_LEDC_LOS_CTRL(1) | 3909 PHY_M_LEDC_INIT_CTRL(8) | 3910 PHY_M_LEDC_STA1_CTRL(7) | 3911 PHY_M_LEDC_STA0_CTRL(7)); 3912 } 3913 3914 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3915 } else 3916 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 3917 PHY_M_LED_MO_DUP(mode) | 3918 PHY_M_LED_MO_10(mode) | 3919 PHY_M_LED_MO_100(mode) | 3920 PHY_M_LED_MO_1000(mode) | 3921 PHY_M_LED_MO_RX(mode) | 3922 PHY_M_LED_MO_TX(mode)); 3923 3924 spin_unlock_bh(&sky2->phy_lock); 3925 } 3926 3927 /* blink LED's for finding board */ 3928 static int sky2_set_phys_id(struct net_device *dev, 3929 enum ethtool_phys_id_state state) 3930 { 3931 struct sky2_port *sky2 = netdev_priv(dev); 3932 3933 switch (state) { 3934 case ETHTOOL_ID_ACTIVE: 3935 return 1; /* cycle on/off once per second */ 3936 case ETHTOOL_ID_INACTIVE: 3937 sky2_led(sky2, MO_LED_NORM); 3938 break; 3939 case ETHTOOL_ID_ON: 3940 sky2_led(sky2, MO_LED_ON); 3941 break; 3942 case ETHTOOL_ID_OFF: 3943 sky2_led(sky2, MO_LED_OFF); 3944 break; 3945 } 3946 3947 return 0; 3948 } 3949 3950 static void sky2_get_pauseparam(struct net_device *dev, 3951 struct ethtool_pauseparam *ecmd) 3952 { 3953 struct sky2_port *sky2 = netdev_priv(dev); 3954 3955 switch (sky2->flow_mode) { 3956 case FC_NONE: 3957 ecmd->tx_pause = ecmd->rx_pause = 0; 3958 break; 3959 case FC_TX: 3960 ecmd->tx_pause = 1, ecmd->rx_pause = 0; 3961 break; 3962 case FC_RX: 3963 ecmd->tx_pause = 0, ecmd->rx_pause = 1; 3964 break; 3965 case FC_BOTH: 3966 ecmd->tx_pause = ecmd->rx_pause = 1; 3967 } 3968 3969 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) 3970 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3971 } 3972 3973 static int sky2_set_pauseparam(struct net_device *dev, 3974 struct ethtool_pauseparam *ecmd) 3975 { 3976 struct sky2_port *sky2 = netdev_priv(dev); 3977 3978 if (ecmd->autoneg == AUTONEG_ENABLE) 3979 sky2->flags |= SKY2_FLAG_AUTO_PAUSE; 3980 else 3981 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; 3982 3983 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); 3984 3985 if (netif_running(dev)) 3986 sky2_phy_reinit(sky2); 3987 3988 return 0; 3989 } 3990 3991 static int sky2_get_coalesce(struct net_device *dev, 3992 struct ethtool_coalesce *ecmd) 3993 { 3994 struct sky2_port *sky2 = netdev_priv(dev); 3995 struct sky2_hw *hw = sky2->hw; 3996 3997 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) 3998 ecmd->tx_coalesce_usecs = 0; 3999 else { 4000 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); 4001 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); 4002 } 4003 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); 4004 4005 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) 4006 ecmd->rx_coalesce_usecs = 0; 4007 else { 4008 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); 4009 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); 4010 } 4011 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); 4012 4013 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) 4014 ecmd->rx_coalesce_usecs_irq = 0; 4015 else { 4016 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); 4017 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); 4018 } 4019 4020 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); 4021 4022 return 0; 4023 } 4024 4025 /* Note: this affect both ports */ 4026 static int sky2_set_coalesce(struct net_device *dev, 4027 struct ethtool_coalesce *ecmd) 4028 { 4029 struct sky2_port *sky2 = netdev_priv(dev); 4030 struct sky2_hw *hw = sky2->hw; 4031 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); 4032 4033 if (ecmd->tx_coalesce_usecs > tmax || 4034 ecmd->rx_coalesce_usecs > tmax || 4035 ecmd->rx_coalesce_usecs_irq > tmax) 4036 return -EINVAL; 4037 4038 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) 4039 return -EINVAL; 4040 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) 4041 return -EINVAL; 4042 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) 4043 return -EINVAL; 4044 4045 if (ecmd->tx_coalesce_usecs == 0) 4046 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 4047 else { 4048 sky2_write32(hw, STAT_TX_TIMER_INI, 4049 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); 4050 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 4051 } 4052 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); 4053 4054 if (ecmd->rx_coalesce_usecs == 0) 4055 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); 4056 else { 4057 sky2_write32(hw, STAT_LEV_TIMER_INI, 4058 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); 4059 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 4060 } 4061 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); 4062 4063 if (ecmd->rx_coalesce_usecs_irq == 0) 4064 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); 4065 else { 4066 sky2_write32(hw, STAT_ISR_TIMER_INI, 4067 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); 4068 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 4069 } 4070 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); 4071 return 0; 4072 } 4073 4074 static void sky2_get_ringparam(struct net_device *dev, 4075 struct ethtool_ringparam *ering) 4076 { 4077 struct sky2_port *sky2 = netdev_priv(dev); 4078 4079 ering->rx_max_pending = RX_MAX_PENDING; 4080 ering->tx_max_pending = TX_MAX_PENDING; 4081 4082 ering->rx_pending = sky2->rx_pending; 4083 ering->tx_pending = sky2->tx_pending; 4084 } 4085 4086 static int sky2_set_ringparam(struct net_device *dev, 4087 struct ethtool_ringparam *ering) 4088 { 4089 struct sky2_port *sky2 = netdev_priv(dev); 4090 4091 if (ering->rx_pending > RX_MAX_PENDING || 4092 ering->rx_pending < 8 || 4093 ering->tx_pending < TX_MIN_PENDING || 4094 ering->tx_pending > TX_MAX_PENDING) 4095 return -EINVAL; 4096 4097 sky2_detach(dev); 4098 4099 sky2->rx_pending = ering->rx_pending; 4100 sky2->tx_pending = ering->tx_pending; 4101 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1); 4102 4103 return sky2_reattach(dev); 4104 } 4105 4106 static int sky2_get_regs_len(struct net_device *dev) 4107 { 4108 return 0x4000; 4109 } 4110 4111 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) 4112 { 4113 /* This complicated switch statement is to make sure and 4114 * only access regions that are unreserved. 4115 * Some blocks are only valid on dual port cards. 4116 */ 4117 switch (b) { 4118 /* second port */ 4119 case 5: /* Tx Arbiter 2 */ 4120 case 9: /* RX2 */ 4121 case 14 ... 15: /* TX2 */ 4122 case 17: case 19: /* Ram Buffer 2 */ 4123 case 22 ... 23: /* Tx Ram Buffer 2 */ 4124 case 25: /* Rx MAC Fifo 1 */ 4125 case 27: /* Tx MAC Fifo 2 */ 4126 case 31: /* GPHY 2 */ 4127 case 40 ... 47: /* Pattern Ram 2 */ 4128 case 52: case 54: /* TCP Segmentation 2 */ 4129 case 112 ... 116: /* GMAC 2 */ 4130 return hw->ports > 1; 4131 4132 case 0: /* Control */ 4133 case 2: /* Mac address */ 4134 case 4: /* Tx Arbiter 1 */ 4135 case 7: /* PCI express reg */ 4136 case 8: /* RX1 */ 4137 case 12 ... 13: /* TX1 */ 4138 case 16: case 18:/* Rx Ram Buffer 1 */ 4139 case 20 ... 21: /* Tx Ram Buffer 1 */ 4140 case 24: /* Rx MAC Fifo 1 */ 4141 case 26: /* Tx MAC Fifo 1 */ 4142 case 28 ... 29: /* Descriptor and status unit */ 4143 case 30: /* GPHY 1*/ 4144 case 32 ... 39: /* Pattern Ram 1 */ 4145 case 48: case 50: /* TCP Segmentation 1 */ 4146 case 56 ... 60: /* PCI space */ 4147 case 80 ... 84: /* GMAC 1 */ 4148 return 1; 4149 4150 default: 4151 return 0; 4152 } 4153 } 4154 4155 /* 4156 * Returns copy of control register region 4157 * Note: ethtool_get_regs always provides full size (16k) buffer 4158 */ 4159 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4160 void *p) 4161 { 4162 const struct sky2_port *sky2 = netdev_priv(dev); 4163 const void __iomem *io = sky2->hw->regs; 4164 unsigned int b; 4165 4166 regs->version = 1; 4167 4168 for (b = 0; b < 128; b++) { 4169 /* skip poisonous diagnostic ram region in block 3 */ 4170 if (b == 3) 4171 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); 4172 else if (sky2_reg_access_ok(sky2->hw, b)) 4173 memcpy_fromio(p, io, 128); 4174 else 4175 memset(p, 0, 128); 4176 4177 p += 128; 4178 io += 128; 4179 } 4180 } 4181 4182 static int sky2_get_eeprom_len(struct net_device *dev) 4183 { 4184 struct sky2_port *sky2 = netdev_priv(dev); 4185 struct sky2_hw *hw = sky2->hw; 4186 u16 reg2; 4187 4188 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4189 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4190 } 4191 4192 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) 4193 { 4194 unsigned long start = jiffies; 4195 4196 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { 4197 /* Can take up to 10.6 ms for write */ 4198 if (time_after(jiffies, start + HZ/4)) { 4199 dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); 4200 return -ETIMEDOUT; 4201 } 4202 mdelay(1); 4203 } 4204 4205 return 0; 4206 } 4207 4208 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, 4209 u16 offset, size_t length) 4210 { 4211 int rc = 0; 4212 4213 while (length > 0) { 4214 u32 val; 4215 4216 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); 4217 rc = sky2_vpd_wait(hw, cap, 0); 4218 if (rc) 4219 break; 4220 4221 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); 4222 4223 memcpy(data, &val, min(sizeof(val), length)); 4224 offset += sizeof(u32); 4225 data += sizeof(u32); 4226 length -= sizeof(u32); 4227 } 4228 4229 return rc; 4230 } 4231 4232 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, 4233 u16 offset, unsigned int length) 4234 { 4235 unsigned int i; 4236 int rc = 0; 4237 4238 for (i = 0; i < length; i += sizeof(u32)) { 4239 u32 val = *(u32 *)(data + i); 4240 4241 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); 4242 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); 4243 4244 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); 4245 if (rc) 4246 break; 4247 } 4248 return rc; 4249 } 4250 4251 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4252 u8 *data) 4253 { 4254 struct sky2_port *sky2 = netdev_priv(dev); 4255 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4256 4257 if (!cap) 4258 return -EINVAL; 4259 4260 eeprom->magic = SKY2_EEPROM_MAGIC; 4261 4262 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4263 } 4264 4265 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4266 u8 *data) 4267 { 4268 struct sky2_port *sky2 = netdev_priv(dev); 4269 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4270 4271 if (!cap) 4272 return -EINVAL; 4273 4274 if (eeprom->magic != SKY2_EEPROM_MAGIC) 4275 return -EINVAL; 4276 4277 /* Partial writes not supported */ 4278 if ((eeprom->offset & 3) || (eeprom->len & 3)) 4279 return -EINVAL; 4280 4281 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4282 } 4283 4284 static u32 sky2_fix_features(struct net_device *dev, u32 features) 4285 { 4286 const struct sky2_port *sky2 = netdev_priv(dev); 4287 const struct sky2_hw *hw = sky2->hw; 4288 4289 /* In order to do Jumbo packets on these chips, need to turn off the 4290 * transmit store/forward. Therefore checksum offload won't work. 4291 */ 4292 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { 4293 netdev_info(dev, "checksum offload not possible with jumbo frames\n"); 4294 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM); 4295 } 4296 4297 /* Some hardware requires receive checksum for RSS to work. */ 4298 if ( (features & NETIF_F_RXHASH) && 4299 !(features & NETIF_F_RXCSUM) && 4300 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { 4301 netdev_info(dev, "receive hashing forces receive checksum\n"); 4302 features |= NETIF_F_RXCSUM; 4303 } 4304 4305 return features; 4306 } 4307 4308 static int sky2_set_features(struct net_device *dev, u32 features) 4309 { 4310 struct sky2_port *sky2 = netdev_priv(dev); 4311 u32 changed = dev->features ^ features; 4312 4313 if (changed & NETIF_F_RXCSUM) { 4314 u32 on = features & NETIF_F_RXCSUM; 4315 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 4316 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 4317 } 4318 4319 if (changed & NETIF_F_RXHASH) 4320 rx_set_rss(dev, features); 4321 4322 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX)) 4323 sky2_vlan_mode(dev, features); 4324 4325 return 0; 4326 } 4327 4328 static const struct ethtool_ops sky2_ethtool_ops = { 4329 .get_settings = sky2_get_settings, 4330 .set_settings = sky2_set_settings, 4331 .get_drvinfo = sky2_get_drvinfo, 4332 .get_wol = sky2_get_wol, 4333 .set_wol = sky2_set_wol, 4334 .get_msglevel = sky2_get_msglevel, 4335 .set_msglevel = sky2_set_msglevel, 4336 .nway_reset = sky2_nway_reset, 4337 .get_regs_len = sky2_get_regs_len, 4338 .get_regs = sky2_get_regs, 4339 .get_link = ethtool_op_get_link, 4340 .get_eeprom_len = sky2_get_eeprom_len, 4341 .get_eeprom = sky2_get_eeprom, 4342 .set_eeprom = sky2_set_eeprom, 4343 .get_strings = sky2_get_strings, 4344 .get_coalesce = sky2_get_coalesce, 4345 .set_coalesce = sky2_set_coalesce, 4346 .get_ringparam = sky2_get_ringparam, 4347 .set_ringparam = sky2_set_ringparam, 4348 .get_pauseparam = sky2_get_pauseparam, 4349 .set_pauseparam = sky2_set_pauseparam, 4350 .set_phys_id = sky2_set_phys_id, 4351 .get_sset_count = sky2_get_sset_count, 4352 .get_ethtool_stats = sky2_get_ethtool_stats, 4353 }; 4354 4355 #ifdef CONFIG_SKY2_DEBUG 4356 4357 static struct dentry *sky2_debug; 4358 4359 4360 /* 4361 * Read and parse the first part of Vital Product Data 4362 */ 4363 #define VPD_SIZE 128 4364 #define VPD_MAGIC 0x82 4365 4366 static const struct vpd_tag { 4367 char tag[2]; 4368 char *label; 4369 } vpd_tags[] = { 4370 { "PN", "Part Number" }, 4371 { "EC", "Engineering Level" }, 4372 { "MN", "Manufacturer" }, 4373 { "SN", "Serial Number" }, 4374 { "YA", "Asset Tag" }, 4375 { "VL", "First Error Log Message" }, 4376 { "VF", "Second Error Log Message" }, 4377 { "VB", "Boot Agent ROM Configuration" }, 4378 { "VE", "EFI UNDI Configuration" }, 4379 }; 4380 4381 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) 4382 { 4383 size_t vpd_size; 4384 loff_t offs; 4385 u8 len; 4386 unsigned char *buf; 4387 u16 reg2; 4388 4389 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4390 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4391 4392 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); 4393 buf = kmalloc(vpd_size, GFP_KERNEL); 4394 if (!buf) { 4395 seq_puts(seq, "no memory!\n"); 4396 return; 4397 } 4398 4399 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { 4400 seq_puts(seq, "VPD read failed\n"); 4401 goto out; 4402 } 4403 4404 if (buf[0] != VPD_MAGIC) { 4405 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); 4406 goto out; 4407 } 4408 len = buf[1]; 4409 if (len == 0 || len > vpd_size - 4) { 4410 seq_printf(seq, "Invalid id length: %d\n", len); 4411 goto out; 4412 } 4413 4414 seq_printf(seq, "%.*s\n", len, buf + 3); 4415 offs = len + 3; 4416 4417 while (offs < vpd_size - 4) { 4418 int i; 4419 4420 if (!memcmp("RW", buf + offs, 2)) /* end marker */ 4421 break; 4422 len = buf[offs + 2]; 4423 if (offs + len + 3 >= vpd_size) 4424 break; 4425 4426 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { 4427 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { 4428 seq_printf(seq, " %s: %.*s\n", 4429 vpd_tags[i].label, len, buf + offs + 3); 4430 break; 4431 } 4432 } 4433 offs += len + 3; 4434 } 4435 out: 4436 kfree(buf); 4437 } 4438 4439 static int sky2_debug_show(struct seq_file *seq, void *v) 4440 { 4441 struct net_device *dev = seq->private; 4442 const struct sky2_port *sky2 = netdev_priv(dev); 4443 struct sky2_hw *hw = sky2->hw; 4444 unsigned port = sky2->port; 4445 unsigned idx, last; 4446 int sop; 4447 4448 sky2_show_vpd(seq, hw); 4449 4450 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", 4451 sky2_read32(hw, B0_ISRC), 4452 sky2_read32(hw, B0_IMSK), 4453 sky2_read32(hw, B0_Y2_SP_ICR)); 4454 4455 if (!netif_running(dev)) { 4456 seq_printf(seq, "network not running\n"); 4457 return 0; 4458 } 4459 4460 napi_disable(&hw->napi); 4461 last = sky2_read16(hw, STAT_PUT_IDX); 4462 4463 seq_printf(seq, "Status ring %u\n", hw->st_size); 4464 if (hw->st_idx == last) 4465 seq_puts(seq, "Status ring (empty)\n"); 4466 else { 4467 seq_puts(seq, "Status ring\n"); 4468 for (idx = hw->st_idx; idx != last && idx < hw->st_size; 4469 idx = RING_NEXT(idx, hw->st_size)) { 4470 const struct sky2_status_le *le = hw->st_le + idx; 4471 seq_printf(seq, "[%d] %#x %d %#x\n", 4472 idx, le->opcode, le->length, le->status); 4473 } 4474 seq_puts(seq, "\n"); 4475 } 4476 4477 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", 4478 sky2->tx_cons, sky2->tx_prod, 4479 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 4480 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); 4481 4482 /* Dump contents of tx ring */ 4483 sop = 1; 4484 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; 4485 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 4486 const struct sky2_tx_le *le = sky2->tx_le + idx; 4487 u32 a = le32_to_cpu(le->addr); 4488 4489 if (sop) 4490 seq_printf(seq, "%u:", idx); 4491 sop = 0; 4492 4493 switch (le->opcode & ~HW_OWNER) { 4494 case OP_ADDR64: 4495 seq_printf(seq, " %#x:", a); 4496 break; 4497 case OP_LRGLEN: 4498 seq_printf(seq, " mtu=%d", a); 4499 break; 4500 case OP_VLAN: 4501 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); 4502 break; 4503 case OP_TCPLISW: 4504 seq_printf(seq, " csum=%#x", a); 4505 break; 4506 case OP_LARGESEND: 4507 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); 4508 break; 4509 case OP_PACKET: 4510 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); 4511 break; 4512 case OP_BUFFER: 4513 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); 4514 break; 4515 default: 4516 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, 4517 a, le16_to_cpu(le->length)); 4518 } 4519 4520 if (le->ctrl & EOP) { 4521 seq_putc(seq, '\n'); 4522 sop = 1; 4523 } 4524 } 4525 4526 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", 4527 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), 4528 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), 4529 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); 4530 4531 sky2_read32(hw, B0_Y2_SP_LISR); 4532 napi_enable(&hw->napi); 4533 return 0; 4534 } 4535 4536 static int sky2_debug_open(struct inode *inode, struct file *file) 4537 { 4538 return single_open(file, sky2_debug_show, inode->i_private); 4539 } 4540 4541 static const struct file_operations sky2_debug_fops = { 4542 .owner = THIS_MODULE, 4543 .open = sky2_debug_open, 4544 .read = seq_read, 4545 .llseek = seq_lseek, 4546 .release = single_release, 4547 }; 4548 4549 /* 4550 * Use network device events to create/remove/rename 4551 * debugfs file entries 4552 */ 4553 static int sky2_device_event(struct notifier_block *unused, 4554 unsigned long event, void *ptr) 4555 { 4556 struct net_device *dev = ptr; 4557 struct sky2_port *sky2 = netdev_priv(dev); 4558 4559 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug) 4560 return NOTIFY_DONE; 4561 4562 switch (event) { 4563 case NETDEV_CHANGENAME: 4564 if (sky2->debugfs) { 4565 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, 4566 sky2_debug, dev->name); 4567 } 4568 break; 4569 4570 case NETDEV_GOING_DOWN: 4571 if (sky2->debugfs) { 4572 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); 4573 debugfs_remove(sky2->debugfs); 4574 sky2->debugfs = NULL; 4575 } 4576 break; 4577 4578 case NETDEV_UP: 4579 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, 4580 sky2_debug, dev, 4581 &sky2_debug_fops); 4582 if (IS_ERR(sky2->debugfs)) 4583 sky2->debugfs = NULL; 4584 } 4585 4586 return NOTIFY_DONE; 4587 } 4588 4589 static struct notifier_block sky2_notifier = { 4590 .notifier_call = sky2_device_event, 4591 }; 4592 4593 4594 static __init void sky2_debug_init(void) 4595 { 4596 struct dentry *ent; 4597 4598 ent = debugfs_create_dir("sky2", NULL); 4599 if (!ent || IS_ERR(ent)) 4600 return; 4601 4602 sky2_debug = ent; 4603 register_netdevice_notifier(&sky2_notifier); 4604 } 4605 4606 static __exit void sky2_debug_cleanup(void) 4607 { 4608 if (sky2_debug) { 4609 unregister_netdevice_notifier(&sky2_notifier); 4610 debugfs_remove(sky2_debug); 4611 sky2_debug = NULL; 4612 } 4613 } 4614 4615 #else 4616 #define sky2_debug_init() 4617 #define sky2_debug_cleanup() 4618 #endif 4619 4620 /* Two copies of network device operations to handle special case of 4621 not allowing netpoll on second port */ 4622 static const struct net_device_ops sky2_netdev_ops[2] = { 4623 { 4624 .ndo_open = sky2_up, 4625 .ndo_stop = sky2_down, 4626 .ndo_start_xmit = sky2_xmit_frame, 4627 .ndo_do_ioctl = sky2_ioctl, 4628 .ndo_validate_addr = eth_validate_addr, 4629 .ndo_set_mac_address = sky2_set_mac_address, 4630 .ndo_set_rx_mode = sky2_set_multicast, 4631 .ndo_change_mtu = sky2_change_mtu, 4632 .ndo_fix_features = sky2_fix_features, 4633 .ndo_set_features = sky2_set_features, 4634 .ndo_tx_timeout = sky2_tx_timeout, 4635 .ndo_get_stats64 = sky2_get_stats, 4636 #ifdef CONFIG_NET_POLL_CONTROLLER 4637 .ndo_poll_controller = sky2_netpoll, 4638 #endif 4639 }, 4640 { 4641 .ndo_open = sky2_up, 4642 .ndo_stop = sky2_down, 4643 .ndo_start_xmit = sky2_xmit_frame, 4644 .ndo_do_ioctl = sky2_ioctl, 4645 .ndo_validate_addr = eth_validate_addr, 4646 .ndo_set_mac_address = sky2_set_mac_address, 4647 .ndo_set_rx_mode = sky2_set_multicast, 4648 .ndo_change_mtu = sky2_change_mtu, 4649 .ndo_fix_features = sky2_fix_features, 4650 .ndo_set_features = sky2_set_features, 4651 .ndo_tx_timeout = sky2_tx_timeout, 4652 .ndo_get_stats64 = sky2_get_stats, 4653 }, 4654 }; 4655 4656 /* Initialize network device */ 4657 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, 4658 unsigned port, 4659 int highmem, int wol) 4660 { 4661 struct sky2_port *sky2; 4662 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 4663 4664 if (!dev) { 4665 dev_err(&hw->pdev->dev, "etherdev alloc failed\n"); 4666 return NULL; 4667 } 4668 4669 SET_NETDEV_DEV(dev, &hw->pdev->dev); 4670 dev->irq = hw->pdev->irq; 4671 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); 4672 dev->watchdog_timeo = TX_WATCHDOG; 4673 dev->netdev_ops = &sky2_netdev_ops[port]; 4674 4675 sky2 = netdev_priv(dev); 4676 sky2->netdev = dev; 4677 sky2->hw = hw; 4678 sky2->msg_enable = netif_msg_init(debug, default_msg); 4679 4680 /* Auto speed and flow control */ 4681 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; 4682 if (hw->chip_id != CHIP_ID_YUKON_XL) 4683 dev->hw_features |= NETIF_F_RXCSUM; 4684 4685 sky2->flow_mode = FC_BOTH; 4686 4687 sky2->duplex = -1; 4688 sky2->speed = -1; 4689 sky2->advertising = sky2_supported_modes(hw); 4690 sky2->wol = wol; 4691 4692 spin_lock_init(&sky2->phy_lock); 4693 4694 sky2->tx_pending = TX_DEF_PENDING; 4695 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1); 4696 sky2->rx_pending = RX_DEF_PENDING; 4697 4698 hw->dev[port] = dev; 4699 4700 sky2->port = port; 4701 4702 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; 4703 4704 if (highmem) 4705 dev->features |= NETIF_F_HIGHDMA; 4706 4707 /* Enable receive hashing unless hardware is known broken */ 4708 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 4709 dev->hw_features |= NETIF_F_RXHASH; 4710 4711 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { 4712 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 4713 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 4714 } 4715 4716 dev->features |= dev->hw_features; 4717 4718 /* read the mac address */ 4719 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); 4720 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 4721 4722 return dev; 4723 } 4724 4725 static void __devinit sky2_show_addr(struct net_device *dev) 4726 { 4727 const struct sky2_port *sky2 = netdev_priv(dev); 4728 4729 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); 4730 } 4731 4732 /* Handle software interrupt used during MSI test */ 4733 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id) 4734 { 4735 struct sky2_hw *hw = dev_id; 4736 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 4737 4738 if (status == 0) 4739 return IRQ_NONE; 4740 4741 if (status & Y2_IS_IRQ_SW) { 4742 hw->flags |= SKY2_HW_USE_MSI; 4743 wake_up(&hw->msi_wait); 4744 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4745 } 4746 sky2_write32(hw, B0_Y2_SP_ICR, 2); 4747 4748 return IRQ_HANDLED; 4749 } 4750 4751 /* Test interrupt path by forcing a a software IRQ */ 4752 static int __devinit sky2_test_msi(struct sky2_hw *hw) 4753 { 4754 struct pci_dev *pdev = hw->pdev; 4755 int err; 4756 4757 init_waitqueue_head(&hw->msi_wait); 4758 4759 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 4760 4761 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); 4762 if (err) { 4763 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 4764 return err; 4765 } 4766 4767 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 4768 sky2_read8(hw, B0_CTST); 4769 4770 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); 4771 4772 if (!(hw->flags & SKY2_HW_USE_MSI)) { 4773 /* MSI test failed, go back to INTx mode */ 4774 dev_info(&pdev->dev, "No interrupt generated using MSI, " 4775 "switching to INTx mode.\n"); 4776 4777 err = -EOPNOTSUPP; 4778 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4779 } 4780 4781 sky2_write32(hw, B0_IMSK, 0); 4782 sky2_read32(hw, B0_IMSK); 4783 4784 free_irq(pdev->irq, hw); 4785 4786 return err; 4787 } 4788 4789 /* This driver supports yukon2 chipset only */ 4790 static const char *sky2_name(u8 chipid, char *buf, int sz) 4791 { 4792 const char *name[] = { 4793 "XL", /* 0xb3 */ 4794 "EC Ultra", /* 0xb4 */ 4795 "Extreme", /* 0xb5 */ 4796 "EC", /* 0xb6 */ 4797 "FE", /* 0xb7 */ 4798 "FE+", /* 0xb8 */ 4799 "Supreme", /* 0xb9 */ 4800 "UL 2", /* 0xba */ 4801 "Unknown", /* 0xbb */ 4802 "Optima", /* 0xbc */ 4803 "Optima Prime", /* 0xbd */ 4804 "Optima 2", /* 0xbe */ 4805 }; 4806 4807 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2) 4808 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); 4809 else 4810 snprintf(buf, sz, "(chip %#x)", chipid); 4811 return buf; 4812 } 4813 4814 static int __devinit sky2_probe(struct pci_dev *pdev, 4815 const struct pci_device_id *ent) 4816 { 4817 struct net_device *dev, *dev1; 4818 struct sky2_hw *hw; 4819 int err, using_dac = 0, wol_default; 4820 u32 reg; 4821 char buf1[16]; 4822 4823 err = pci_enable_device(pdev); 4824 if (err) { 4825 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4826 goto err_out; 4827 } 4828 4829 /* Get configuration information 4830 * Note: only regular PCI config access once to test for HW issues 4831 * other PCI access through shared memory for speed and to 4832 * avoid MMCONFIG problems. 4833 */ 4834 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 4835 if (err) { 4836 dev_err(&pdev->dev, "PCI read config failed\n"); 4837 goto err_out; 4838 } 4839 4840 if (~reg == 0) { 4841 dev_err(&pdev->dev, "PCI configuration read error\n"); 4842 goto err_out; 4843 } 4844 4845 err = pci_request_regions(pdev, DRV_NAME); 4846 if (err) { 4847 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 4848 goto err_out_disable; 4849 } 4850 4851 pci_set_master(pdev); 4852 4853 if (sizeof(dma_addr_t) > sizeof(u32) && 4854 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { 4855 using_dac = 1; 4856 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4857 if (err < 0) { 4858 dev_err(&pdev->dev, "unable to obtain 64 bit DMA " 4859 "for consistent allocations\n"); 4860 goto err_out_free_regions; 4861 } 4862 } else { 4863 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4864 if (err) { 4865 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4866 goto err_out_free_regions; 4867 } 4868 } 4869 4870 4871 #ifdef __BIG_ENDIAN 4872 /* The sk98lin vendor driver uses hardware byte swapping but 4873 * this driver uses software swapping. 4874 */ 4875 reg &= ~PCI_REV_DESC; 4876 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 4877 if (err) { 4878 dev_err(&pdev->dev, "PCI write config failed\n"); 4879 goto err_out_free_regions; 4880 } 4881 #endif 4882 4883 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; 4884 4885 err = -ENOMEM; 4886 4887 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 4888 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 4889 if (!hw) { 4890 dev_err(&pdev->dev, "cannot allocate hardware struct\n"); 4891 goto err_out_free_regions; 4892 } 4893 4894 hw->pdev = pdev; 4895 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 4896 4897 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 4898 if (!hw->regs) { 4899 dev_err(&pdev->dev, "cannot map device registers\n"); 4900 goto err_out_free_hw; 4901 } 4902 4903 err = sky2_init(hw); 4904 if (err) 4905 goto err_out_iounmap; 4906 4907 /* ring for status responses */ 4908 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); 4909 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 4910 &hw->st_dma); 4911 if (!hw->st_le) 4912 goto err_out_reset; 4913 4914 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", 4915 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); 4916 4917 sky2_reset(hw); 4918 4919 dev = sky2_init_netdev(hw, 0, using_dac, wol_default); 4920 if (!dev) { 4921 err = -ENOMEM; 4922 goto err_out_free_pci; 4923 } 4924 4925 if (!disable_msi && pci_enable_msi(pdev) == 0) { 4926 err = sky2_test_msi(hw); 4927 if (err == -EOPNOTSUPP) 4928 pci_disable_msi(pdev); 4929 else if (err) 4930 goto err_out_free_netdev; 4931 } 4932 4933 err = register_netdev(dev); 4934 if (err) { 4935 dev_err(&pdev->dev, "cannot register net device\n"); 4936 goto err_out_free_netdev; 4937 } 4938 4939 netif_carrier_off(dev); 4940 4941 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); 4942 4943 sky2_show_addr(dev); 4944 4945 if (hw->ports > 1) { 4946 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); 4947 if (!dev1) { 4948 err = -ENOMEM; 4949 goto err_out_unregister; 4950 } 4951 4952 err = register_netdev(dev1); 4953 if (err) { 4954 dev_err(&pdev->dev, "cannot register second net device\n"); 4955 goto err_out_free_dev1; 4956 } 4957 4958 err = sky2_setup_irq(hw, hw->irq_name); 4959 if (err) 4960 goto err_out_unregister_dev1; 4961 4962 sky2_show_addr(dev1); 4963 } 4964 4965 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); 4966 INIT_WORK(&hw->restart_work, sky2_restart); 4967 4968 pci_set_drvdata(pdev, hw); 4969 pdev->d3_delay = 150; 4970 4971 return 0; 4972 4973 err_out_unregister_dev1: 4974 unregister_netdev(dev1); 4975 err_out_free_dev1: 4976 free_netdev(dev1); 4977 err_out_unregister: 4978 if (hw->flags & SKY2_HW_USE_MSI) 4979 pci_disable_msi(pdev); 4980 unregister_netdev(dev); 4981 err_out_free_netdev: 4982 free_netdev(dev); 4983 err_out_free_pci: 4984 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 4985 hw->st_le, hw->st_dma); 4986 err_out_reset: 4987 sky2_write8(hw, B0_CTST, CS_RST_SET); 4988 err_out_iounmap: 4989 iounmap(hw->regs); 4990 err_out_free_hw: 4991 kfree(hw); 4992 err_out_free_regions: 4993 pci_release_regions(pdev); 4994 err_out_disable: 4995 pci_disable_device(pdev); 4996 err_out: 4997 pci_set_drvdata(pdev, NULL); 4998 return err; 4999 } 5000 5001 static void __devexit sky2_remove(struct pci_dev *pdev) 5002 { 5003 struct sky2_hw *hw = pci_get_drvdata(pdev); 5004 int i; 5005 5006 if (!hw) 5007 return; 5008 5009 del_timer_sync(&hw->watchdog_timer); 5010 cancel_work_sync(&hw->restart_work); 5011 5012 for (i = hw->ports-1; i >= 0; --i) 5013 unregister_netdev(hw->dev[i]); 5014 5015 sky2_write32(hw, B0_IMSK, 0); 5016 sky2_read32(hw, B0_IMSK); 5017 5018 sky2_power_aux(hw); 5019 5020 sky2_write8(hw, B0_CTST, CS_RST_SET); 5021 sky2_read8(hw, B0_CTST); 5022 5023 if (hw->ports > 1) { 5024 napi_disable(&hw->napi); 5025 free_irq(pdev->irq, hw); 5026 } 5027 5028 if (hw->flags & SKY2_HW_USE_MSI) 5029 pci_disable_msi(pdev); 5030 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5031 hw->st_le, hw->st_dma); 5032 pci_release_regions(pdev); 5033 pci_disable_device(pdev); 5034 5035 for (i = hw->ports-1; i >= 0; --i) 5036 free_netdev(hw->dev[i]); 5037 5038 iounmap(hw->regs); 5039 kfree(hw); 5040 5041 pci_set_drvdata(pdev, NULL); 5042 } 5043 5044 static int sky2_suspend(struct device *dev) 5045 { 5046 struct pci_dev *pdev = to_pci_dev(dev); 5047 struct sky2_hw *hw = pci_get_drvdata(pdev); 5048 int i; 5049 5050 if (!hw) 5051 return 0; 5052 5053 del_timer_sync(&hw->watchdog_timer); 5054 cancel_work_sync(&hw->restart_work); 5055 5056 rtnl_lock(); 5057 5058 sky2_all_down(hw); 5059 for (i = 0; i < hw->ports; i++) { 5060 struct net_device *dev = hw->dev[i]; 5061 struct sky2_port *sky2 = netdev_priv(dev); 5062 5063 if (sky2->wol) 5064 sky2_wol_init(sky2); 5065 } 5066 5067 sky2_power_aux(hw); 5068 rtnl_unlock(); 5069 5070 return 0; 5071 } 5072 5073 #ifdef CONFIG_PM_SLEEP 5074 static int sky2_resume(struct device *dev) 5075 { 5076 struct pci_dev *pdev = to_pci_dev(dev); 5077 struct sky2_hw *hw = pci_get_drvdata(pdev); 5078 int err; 5079 5080 if (!hw) 5081 return 0; 5082 5083 /* Re-enable all clocks */ 5084 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); 5085 if (err) { 5086 dev_err(&pdev->dev, "PCI write config failed\n"); 5087 goto out; 5088 } 5089 5090 rtnl_lock(); 5091 sky2_reset(hw); 5092 sky2_all_up(hw); 5093 rtnl_unlock(); 5094 5095 return 0; 5096 out: 5097 5098 dev_err(&pdev->dev, "resume failed (%d)\n", err); 5099 pci_disable_device(pdev); 5100 return err; 5101 } 5102 5103 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); 5104 #define SKY2_PM_OPS (&sky2_pm_ops) 5105 5106 #else 5107 5108 #define SKY2_PM_OPS NULL 5109 #endif 5110 5111 static void sky2_shutdown(struct pci_dev *pdev) 5112 { 5113 sky2_suspend(&pdev->dev); 5114 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 5115 pci_set_power_state(pdev, PCI_D3hot); 5116 } 5117 5118 static struct pci_driver sky2_driver = { 5119 .name = DRV_NAME, 5120 .id_table = sky2_id_table, 5121 .probe = sky2_probe, 5122 .remove = __devexit_p(sky2_remove), 5123 .shutdown = sky2_shutdown, 5124 .driver.pm = SKY2_PM_OPS, 5125 }; 5126 5127 static int __init sky2_init_module(void) 5128 { 5129 pr_info("driver version " DRV_VERSION "\n"); 5130 5131 sky2_debug_init(); 5132 return pci_register_driver(&sky2_driver); 5133 } 5134 5135 static void __exit sky2_cleanup_module(void) 5136 { 5137 pci_unregister_driver(&sky2_driver); 5138 sky2_debug_cleanup(); 5139 } 5140 5141 module_init(sky2_init_module); 5142 module_exit(sky2_cleanup_module); 5143 5144 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); 5145 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 5146 MODULE_LICENSE("GPL"); 5147 MODULE_VERSION(DRV_VERSION); 5148