1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * New driver for Marvell Yukon 2 chipset. 4 * Based on earlier sk98lin, and skge driver. 5 * 6 * This driver intentionally does not support all the features 7 * of the original driver such as link fail-over and link management because 8 * those should be done at higher levels. 9 * 10 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/crc32.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/netdevice.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/pci.h> 23 #include <linux/interrupt.h> 24 #include <linux/ip.h> 25 #include <linux/slab.h> 26 #include <net/ip.h> 27 #include <linux/tcp.h> 28 #include <linux/in.h> 29 #include <linux/delay.h> 30 #include <linux/workqueue.h> 31 #include <linux/if_vlan.h> 32 #include <linux/prefetch.h> 33 #include <linux/debugfs.h> 34 #include <linux/mii.h> 35 #include <linux/of_net.h> 36 #include <linux/dmi.h> 37 #include <linux/skbuff_ref.h> 38 39 #include <asm/irq.h> 40 41 #include "sky2.h" 42 43 #define DRV_NAME "sky2" 44 #define DRV_VERSION "1.30" 45 46 /* 47 * The Yukon II chipset takes 64 bit command blocks (called list elements) 48 * that are organized into three (receive, transmit, status) different rings 49 * similar to Tigon3. 50 */ 51 52 #define RX_LE_SIZE 1024 53 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) 54 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) 55 #define RX_DEF_PENDING RX_MAX_PENDING 56 57 /* This is the worst case number of transmit list elements for a single skb: 58 * VLAN:GSO + CKSUM + Data + skb_frags * DMA 59 */ 60 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) 61 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) 62 #define TX_MAX_PENDING 1024 63 #define TX_DEF_PENDING 63 64 65 #define TX_WATCHDOG (5 * HZ) 66 #define PHY_RETRIES 1000 67 68 #define SKY2_EEPROM_MAGIC 0x9955aabb 69 70 #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) 71 72 static const u32 default_msg = 73 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 74 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR 75 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 76 77 static int debug = -1; /* defaults above */ 78 module_param(debug, int, 0); 79 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 80 81 static int copybreak __read_mostly = 128; 82 module_param(copybreak, int, 0); 83 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 84 85 static int disable_msi = -1; 86 module_param(disable_msi, int, 0); 87 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 88 89 static int legacy_pme = 0; 90 module_param(legacy_pme, int, 0); 91 MODULE_PARM_DESC(legacy_pme, "Legacy power management"); 92 93 static const struct pci_device_id sky2_id_table[] = { 94 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 95 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 96 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ 97 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 98 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 99 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ 100 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ 101 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ 102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ 103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ 104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ 105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ 106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ 115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4373) }, /* 88E8075 */ 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */ 137 { 0 } 138 }; 139 140 MODULE_DEVICE_TABLE(pci, sky2_id_table); 141 142 /* Avoid conditionals by using array */ 143 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; 144 static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 145 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 146 147 static void sky2_set_multicast(struct net_device *dev); 148 static irqreturn_t sky2_intr(int irq, void *dev_id); 149 150 /* Access to PHY via serial interconnect */ 151 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) 152 { 153 int i; 154 155 gma_write16(hw, port, GM_SMI_DATA, val); 156 gma_write16(hw, port, GM_SMI_CTRL, 157 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 158 159 for (i = 0; i < PHY_RETRIES; i++) { 160 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 161 if (ctrl == 0xffff) 162 goto io_error; 163 164 if (!(ctrl & GM_SMI_CT_BUSY)) 165 return 0; 166 167 udelay(10); 168 } 169 170 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); 171 return -ETIMEDOUT; 172 173 io_error: 174 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 175 return -EIO; 176 } 177 178 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) 179 { 180 int i; 181 182 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 183 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 184 185 for (i = 0; i < PHY_RETRIES; i++) { 186 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 187 if (ctrl == 0xffff) 188 goto io_error; 189 190 if (ctrl & GM_SMI_CT_RD_VAL) { 191 *val = gma_read16(hw, port, GM_SMI_DATA); 192 return 0; 193 } 194 195 udelay(10); 196 } 197 198 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); 199 return -ETIMEDOUT; 200 io_error: 201 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 202 return -EIO; 203 } 204 205 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) 206 { 207 u16 v = 0; 208 __gm_phy_read(hw, port, reg, &v); 209 return v; 210 } 211 212 213 static void sky2_power_on(struct sky2_hw *hw) 214 { 215 /* switch power to VCC (WA for VAUX problem) */ 216 sky2_write8(hw, B0_POWER_CTRL, 217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 218 219 /* disable Core Clock Division, */ 220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 221 222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 223 /* enable bits are inverted */ 224 sky2_write8(hw, B2_Y2_CLK_GATE, 225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 228 else 229 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 230 231 if (hw->flags & SKY2_HW_ADV_POWER_CTL) { 232 u32 reg; 233 234 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 235 236 reg = sky2_pci_read32(hw, PCI_DEV_REG4); 237 /* set all bits to 0 except bits 15..12 and 8 */ 238 reg &= P_ASPM_CONTROL_MSK; 239 sky2_pci_write32(hw, PCI_DEV_REG4, reg); 240 241 reg = sky2_pci_read32(hw, PCI_DEV_REG5); 242 /* set all bits to 0 except bits 28 & 27 */ 243 reg &= P_CTL_TIM_VMAIN_AV_MSK; 244 sky2_pci_write32(hw, PCI_DEV_REG5, reg); 245 246 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); 247 248 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); 249 250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ 251 reg = sky2_read32(hw, B2_GP_IO); 252 reg |= GLB_GPIO_STAT_RACE_DIS; 253 sky2_write32(hw, B2_GP_IO, reg); 254 255 sky2_read32(hw, B2_GP_IO); 256 } 257 258 /* Turn on "driver loaded" LED */ 259 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); 260 } 261 262 static void sky2_power_aux(struct sky2_hw *hw) 263 { 264 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 265 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 266 else 267 /* enable bits are inverted */ 268 sky2_write8(hw, B2_Y2_CLK_GATE, 269 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 270 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 271 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 272 273 /* switch power to VAUX if supported and PME from D3cold */ 274 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && 275 pci_pme_capable(hw->pdev, PCI_D3cold)) 276 sky2_write8(hw, B0_POWER_CTRL, 277 (PC_VAUX_ENA | PC_VCC_ENA | 278 PC_VAUX_ON | PC_VCC_OFF)); 279 280 /* turn off "driver loaded LED" */ 281 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); 282 } 283 284 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) 285 { 286 u16 reg; 287 288 /* disable all GMAC IRQ's */ 289 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 290 291 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 292 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 293 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 294 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 295 296 reg = gma_read16(hw, port, GM_RX_CTRL); 297 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 298 gma_write16(hw, port, GM_RX_CTRL, reg); 299 } 300 301 /* flow control to advertise bits */ 302 static const u16 copper_fc_adv[] = { 303 [FC_NONE] = 0, 304 [FC_TX] = PHY_M_AN_ASP, 305 [FC_RX] = PHY_M_AN_PC, 306 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, 307 }; 308 309 /* flow control to advertise bits when using 1000BaseX */ 310 static const u16 fiber_fc_adv[] = { 311 [FC_NONE] = PHY_M_P_NO_PAUSE_X, 312 [FC_TX] = PHY_M_P_ASYM_MD_X, 313 [FC_RX] = PHY_M_P_SYM_MD_X, 314 [FC_BOTH] = PHY_M_P_BOTH_MD_X, 315 }; 316 317 /* flow control to GMA disable bits */ 318 static const u16 gm_fc_disable[] = { 319 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, 320 [FC_TX] = GM_GPCR_FC_RX_DIS, 321 [FC_RX] = GM_GPCR_FC_TX_DIS, 322 [FC_BOTH] = 0, 323 }; 324 325 326 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 327 { 328 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 329 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; 330 331 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 332 !(hw->flags & SKY2_HW_NEWER_PHY)) { 333 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 334 335 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 336 PHY_M_EC_MAC_S_MSK); 337 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 338 339 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ 340 if (hw->chip_id == CHIP_ID_YUKON_EC) 341 /* set downshift counter to 3x and enable downshift */ 342 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 343 else 344 /* set master & slave downshift counter to 1x */ 345 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 346 347 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 348 } 349 350 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 351 if (sky2_is_copper(hw)) { 352 if (!(hw->flags & SKY2_HW_GIGABIT)) { 353 /* enable automatic crossover */ 354 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 355 356 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 357 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 358 u16 spec; 359 360 /* Enable Class A driver for FE+ A0 */ 361 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); 362 spec |= PHY_M_FESC_SEL_CL_A; 363 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); 364 } 365 } else { 366 /* disable energy detect */ 367 ctrl &= ~PHY_M_PC_EN_DET_MSK; 368 369 /* enable automatic crossover */ 370 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 371 372 /* downshift on PHY 88E1112 and 88E1149 is changed */ 373 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 374 (hw->flags & SKY2_HW_NEWER_PHY)) { 375 /* set downshift counter to 3x and enable downshift */ 376 ctrl &= ~PHY_M_PC_DSC_MSK; 377 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 378 } 379 } 380 } else { 381 /* workaround for deviation #4.88 (CRC errors) */ 382 /* disable Automatic Crossover */ 383 384 ctrl &= ~PHY_M_PC_MDIX_MSK; 385 } 386 387 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 388 389 /* special setup for PHY 88E1112 Fiber */ 390 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { 391 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 392 393 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 394 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 395 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 396 ctrl &= ~PHY_M_MAC_MD_MSK; 397 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 398 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 399 400 if (hw->pmd_type == 'P') { 401 /* select page 1 to access Fiber registers */ 402 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 403 404 /* for SFP-module set SIGDET polarity to low */ 405 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 406 ctrl |= PHY_M_FIB_SIGD_POL; 407 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 408 } 409 410 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 411 } 412 413 ctrl = PHY_CT_RESET; 414 ct1000 = 0; 415 adv = PHY_AN_CSMA; 416 reg = 0; 417 418 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { 419 if (sky2_is_copper(hw)) { 420 if (sky2->advertising & ADVERTISED_1000baseT_Full) 421 ct1000 |= PHY_M_1000C_AFD; 422 if (sky2->advertising & ADVERTISED_1000baseT_Half) 423 ct1000 |= PHY_M_1000C_AHD; 424 if (sky2->advertising & ADVERTISED_100baseT_Full) 425 adv |= PHY_M_AN_100_FD; 426 if (sky2->advertising & ADVERTISED_100baseT_Half) 427 adv |= PHY_M_AN_100_HD; 428 if (sky2->advertising & ADVERTISED_10baseT_Full) 429 adv |= PHY_M_AN_10_FD; 430 if (sky2->advertising & ADVERTISED_10baseT_Half) 431 adv |= PHY_M_AN_10_HD; 432 433 } else { /* special defines for FIBER (88E1040S only) */ 434 if (sky2->advertising & ADVERTISED_1000baseT_Full) 435 adv |= PHY_M_AN_1000X_AFD; 436 if (sky2->advertising & ADVERTISED_1000baseT_Half) 437 adv |= PHY_M_AN_1000X_AHD; 438 } 439 440 /* Restart Auto-negotiation */ 441 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 442 } else { 443 /* forced speed/duplex settings */ 444 ct1000 = PHY_M_1000C_MSE; 445 446 /* Disable auto update for duplex flow control and duplex */ 447 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; 448 449 switch (sky2->speed) { 450 case SPEED_1000: 451 ctrl |= PHY_CT_SP1000; 452 reg |= GM_GPCR_SPEED_1000; 453 break; 454 case SPEED_100: 455 ctrl |= PHY_CT_SP100; 456 reg |= GM_GPCR_SPEED_100; 457 break; 458 } 459 460 if (sky2->duplex == DUPLEX_FULL) { 461 reg |= GM_GPCR_DUP_FULL; 462 ctrl |= PHY_CT_DUP_MD; 463 } else if (sky2->speed < SPEED_1000) 464 sky2->flow_mode = FC_NONE; 465 } 466 467 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { 468 if (sky2_is_copper(hw)) 469 adv |= copper_fc_adv[sky2->flow_mode]; 470 else 471 adv |= fiber_fc_adv[sky2->flow_mode]; 472 } else { 473 reg |= GM_GPCR_AU_FCT_DIS; 474 reg |= gm_fc_disable[sky2->flow_mode]; 475 476 /* Forward pause packets to GMAC? */ 477 if (sky2->flow_mode & FC_RX) 478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 479 else 480 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 481 } 482 483 gma_write16(hw, port, GM_GP_CTRL, reg); 484 485 if (hw->flags & SKY2_HW_GIGABIT) 486 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 487 488 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 489 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 490 491 /* Setup Phy LED's */ 492 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 493 ledover = 0; 494 495 switch (hw->chip_id) { 496 case CHIP_ID_YUKON_FE: 497 /* on 88E3082 these bits are at 11..9 (shifted left) */ 498 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 499 500 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 501 502 /* delete ACT LED control bits */ 503 ctrl &= ~PHY_M_FELP_LED1_MSK; 504 /* change ACT LED control to blink mode */ 505 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 506 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 507 break; 508 509 case CHIP_ID_YUKON_FE_P: 510 /* Enable Link Partner Next Page */ 511 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 512 ctrl |= PHY_M_PC_ENA_LIP_NP; 513 514 /* disable Energy Detect and enable scrambler */ 515 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); 516 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 517 518 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ 519 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | 520 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | 521 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); 522 523 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 524 break; 525 526 case CHIP_ID_YUKON_XL: 527 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 528 529 /* select page 3 to access LED control register */ 530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 531 532 /* set LED Function Control register */ 533 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 534 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 535 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 536 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 537 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 538 539 /* set Polarity Control register */ 540 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 541 (PHY_M_POLC_LS1_P_MIX(4) | 542 PHY_M_POLC_IS0_P_MIX(4) | 543 PHY_M_POLC_LOS_CTRL(2) | 544 PHY_M_POLC_INIT_CTRL(2) | 545 PHY_M_POLC_STA1_CTRL(2) | 546 PHY_M_POLC_STA0_CTRL(2))); 547 548 /* restore page register */ 549 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 550 break; 551 552 case CHIP_ID_YUKON_EC_U: 553 case CHIP_ID_YUKON_EX: 554 case CHIP_ID_YUKON_SUPR: 555 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 556 557 /* select page 3 to access LED control register */ 558 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 559 560 /* set LED Function Control register */ 561 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 562 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 563 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 564 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 565 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 566 567 /* set Blink Rate in LED Timer Control Register */ 568 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 569 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 570 /* restore page register */ 571 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 572 break; 573 574 default: 575 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 576 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 577 578 /* turn off the Rx LED (LED_RX) */ 579 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 580 } 581 582 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { 583 /* apply fixes in PHY AFE */ 584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 585 586 /* increase differential signal amplitude in 10BASE-T */ 587 gm_phy_write(hw, port, 0x18, 0xaa99); 588 gm_phy_write(hw, port, 0x17, 0x2011); 589 590 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 591 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 592 gm_phy_write(hw, port, 0x18, 0xa204); 593 gm_phy_write(hw, port, 0x17, 0x2002); 594 } 595 596 /* set page register to 0 */ 597 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 598 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && 599 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 600 /* apply workaround for integrated resistors calibration */ 601 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 602 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 603 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 604 /* apply fixes in PHY AFE */ 605 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 606 607 /* apply RDAC termination workaround */ 608 gm_phy_write(hw, port, 24, 0x2800); 609 gm_phy_write(hw, port, 23, 0x2001); 610 611 /* set page register back to 0 */ 612 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 613 } else if (hw->chip_id != CHIP_ID_YUKON_EX && 614 hw->chip_id < CHIP_ID_YUKON_SUPR) { 615 /* no effect on Yukon-XL */ 616 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 617 618 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || 619 sky2->speed == SPEED_100) { 620 /* turn on 100 Mbps LED (LED_LINK100) */ 621 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 622 } 623 624 if (ledover) 625 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 626 627 } else if (hw->chip_id == CHIP_ID_YUKON_PRM && 628 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { 629 int i; 630 /* This a phy register setup workaround copied from vendor driver. */ 631 static const struct { 632 u16 reg, val; 633 } eee_afe[] = { 634 { 0x156, 0x58ce }, 635 { 0x153, 0x99eb }, 636 { 0x141, 0x8064 }, 637 /* { 0x155, 0x130b },*/ 638 { 0x000, 0x0000 }, 639 { 0x151, 0x8433 }, 640 { 0x14b, 0x8c44 }, 641 { 0x14c, 0x0f90 }, 642 { 0x14f, 0x39aa }, 643 /* { 0x154, 0x2f39 },*/ 644 { 0x14d, 0xba33 }, 645 { 0x144, 0x0048 }, 646 { 0x152, 0x2010 }, 647 /* { 0x158, 0x1223 },*/ 648 { 0x140, 0x4444 }, 649 { 0x154, 0x2f3b }, 650 { 0x158, 0xb203 }, 651 { 0x157, 0x2029 }, 652 }; 653 654 /* Start Workaround for OptimaEEE Rev.Z0 */ 655 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); 656 657 gm_phy_write(hw, port, 1, 0x4099); 658 gm_phy_write(hw, port, 3, 0x1120); 659 gm_phy_write(hw, port, 11, 0x113c); 660 gm_phy_write(hw, port, 14, 0x8100); 661 gm_phy_write(hw, port, 15, 0x112a); 662 gm_phy_write(hw, port, 17, 0x1008); 663 664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); 665 gm_phy_write(hw, port, 1, 0x20b0); 666 667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 668 669 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) { 670 /* apply AFE settings */ 671 gm_phy_write(hw, port, 17, eee_afe[i].val); 672 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); 673 } 674 675 /* End Workaround for OptimaEEE */ 676 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 677 678 /* Enable 10Base-Te (EEE) */ 679 if (hw->chip_id >= CHIP_ID_YUKON_PRM) { 680 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 681 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, 682 reg | PHY_M_10B_TE_ENABLE); 683 } 684 } 685 686 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 687 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) 688 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 689 else 690 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 691 } 692 693 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; 694 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; 695 696 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) 697 { 698 u32 reg1; 699 700 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 701 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 702 reg1 &= ~phy_power[port]; 703 704 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 705 reg1 |= coma_mode[port]; 706 707 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 708 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 709 sky2_pci_read32(hw, PCI_DEV_REG1); 710 711 if (hw->chip_id == CHIP_ID_YUKON_FE) 712 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); 713 else if (hw->flags & SKY2_HW_ADV_POWER_CTL) 714 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 715 } 716 717 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) 718 { 719 u32 reg1; 720 u16 ctrl; 721 722 /* release GPHY Control reset */ 723 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 724 725 /* release GMAC reset */ 726 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 727 728 if (hw->flags & SKY2_HW_NEWER_PHY) { 729 /* select page 2 to access MAC control register */ 730 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 731 732 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 733 /* allow GMII Power Down */ 734 ctrl &= ~PHY_M_MAC_GMIF_PUP; 735 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 736 737 /* set page register back to 0 */ 738 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 739 } 740 741 /* setup General Purpose Control Register */ 742 gma_write16(hw, port, GM_GP_CTRL, 743 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | 744 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | 745 GM_GPCR_AU_SPD_DIS); 746 747 if (hw->chip_id != CHIP_ID_YUKON_EC) { 748 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 749 /* select page 2 to access MAC control register */ 750 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 751 752 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 753 /* enable Power Down */ 754 ctrl |= PHY_M_PC_POW_D_ENA; 755 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 756 757 /* set page register back to 0 */ 758 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 759 } 760 761 /* set IEEE compatible Power Down Mode (dev. #4.99) */ 762 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); 763 } 764 765 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 766 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 767 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ 768 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 769 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 770 } 771 772 /* configure IPG according to used link speed */ 773 static void sky2_set_ipg(struct sky2_port *sky2) 774 { 775 u16 reg; 776 777 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); 778 reg &= ~GM_SMOD_IPG_MSK; 779 if (sky2->speed > SPEED_100) 780 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 781 else 782 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 783 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); 784 } 785 786 /* Enable Rx/Tx */ 787 static void sky2_enable_rx_tx(struct sky2_port *sky2) 788 { 789 struct sky2_hw *hw = sky2->hw; 790 unsigned port = sky2->port; 791 u16 reg; 792 793 reg = gma_read16(hw, port, GM_GP_CTRL); 794 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 795 gma_write16(hw, port, GM_GP_CTRL, reg); 796 } 797 798 /* Force a renegotiation */ 799 static void sky2_phy_reinit(struct sky2_port *sky2) 800 { 801 spin_lock_bh(&sky2->phy_lock); 802 sky2_phy_init(sky2->hw, sky2->port); 803 sky2_enable_rx_tx(sky2); 804 spin_unlock_bh(&sky2->phy_lock); 805 } 806 807 /* Put device in state to listen for Wake On Lan */ 808 static void sky2_wol_init(struct sky2_port *sky2) 809 { 810 struct sky2_hw *hw = sky2->hw; 811 unsigned port = sky2->port; 812 enum flow_control save_mode; 813 u16 ctrl; 814 815 /* Bring hardware out of reset */ 816 sky2_write16(hw, B0_CTST, CS_RST_CLR); 817 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 818 819 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 820 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 821 822 /* Force to 10/100 823 * sky2_reset will re-enable on resume 824 */ 825 save_mode = sky2->flow_mode; 826 ctrl = sky2->advertising; 827 828 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 829 sky2->flow_mode = FC_NONE; 830 831 spin_lock_bh(&sky2->phy_lock); 832 sky2_phy_power_up(hw, port); 833 sky2_phy_init(hw, port); 834 spin_unlock_bh(&sky2->phy_lock); 835 836 sky2->flow_mode = save_mode; 837 sky2->advertising = ctrl; 838 839 /* Set GMAC to no flow control and auto update for speed/duplex */ 840 gma_write16(hw, port, GM_GP_CTRL, 841 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 842 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 843 844 /* Set WOL address */ 845 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 846 sky2->netdev->dev_addr, ETH_ALEN); 847 848 /* Turn on appropriate WOL control bits */ 849 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 850 ctrl = 0; 851 if (sky2->wol & WAKE_PHY) 852 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 853 else 854 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 855 856 if (sky2->wol & WAKE_MAGIC) 857 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 858 else 859 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 860 861 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 862 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 863 864 /* Disable PiG firmware */ 865 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); 866 867 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */ 868 if (legacy_pme) { 869 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 870 reg1 |= PCI_Y2_PME_LEGACY; 871 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 872 } 873 874 /* block receiver */ 875 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 876 sky2_read32(hw, B0_CTST); 877 } 878 879 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) 880 { 881 struct net_device *dev = hw->dev[port]; 882 883 if ( (hw->chip_id == CHIP_ID_YUKON_EX && 884 hw->chip_rev != CHIP_REV_YU_EX_A0) || 885 hw->chip_id >= CHIP_ID_YUKON_FE_P) { 886 /* Yukon-Extreme B0 and further Extreme devices */ 887 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 888 } else if (dev->mtu > ETH_DATA_LEN) { 889 /* set Tx GMAC FIFO Almost Empty Threshold */ 890 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 891 (ECU_JUMBO_WM << 16) | ECU_AE_THR); 892 893 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); 894 } else 895 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 896 } 897 898 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 899 { 900 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 901 u16 reg; 902 u32 rx_reg; 903 int i; 904 const u8 *addr = hw->dev[port]->dev_addr; 905 906 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 907 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 908 909 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 910 911 if (hw->chip_id == CHIP_ID_YUKON_XL && 912 hw->chip_rev == CHIP_REV_YU_XL_A0 && 913 port == 1) { 914 /* WA DEV_472 -- looks like crossed wires on port 2 */ 915 /* clear GMAC 1 Control reset */ 916 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 917 do { 918 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 919 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 920 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 921 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 922 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 923 } 924 925 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 926 927 /* Enable Transmit FIFO Underrun */ 928 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 929 930 spin_lock_bh(&sky2->phy_lock); 931 sky2_phy_power_up(hw, port); 932 sky2_phy_init(hw, port); 933 spin_unlock_bh(&sky2->phy_lock); 934 935 /* MIB clear */ 936 reg = gma_read16(hw, port, GM_PHY_ADDR); 937 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 938 939 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) 940 gma_read16(hw, port, i); 941 gma_write16(hw, port, GM_PHY_ADDR, reg); 942 943 /* transmit control */ 944 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 945 946 /* receive control reg: unicast + multicast + no FCS */ 947 gma_write16(hw, port, GM_RX_CTRL, 948 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 949 950 /* transmit flow control */ 951 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 952 953 /* transmit parameter */ 954 gma_write16(hw, port, GM_TX_PARAM, 955 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 956 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 957 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 958 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 959 960 /* serial mode register */ 961 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 962 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000); 963 964 if (hw->dev[port]->mtu > ETH_DATA_LEN) 965 reg |= GM_SMOD_JUMBO_ENA; 966 967 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 968 hw->chip_rev == CHIP_REV_YU_EC_U_B1) 969 reg |= GM_NEW_FLOW_CTRL; 970 971 gma_write16(hw, port, GM_SERIAL_MODE, reg); 972 973 /* virtual address for data */ 974 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 975 976 /* physical address: used for pause frames */ 977 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 978 979 /* ignore counter overflows */ 980 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 981 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 982 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 983 984 /* Configure Rx MAC FIFO */ 985 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 986 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 987 if (hw->chip_id == CHIP_ID_YUKON_EX || 988 hw->chip_id == CHIP_ID_YUKON_FE_P) 989 rx_reg |= GMF_RX_OVER_ON; 990 991 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); 992 993 if (hw->chip_id == CHIP_ID_YUKON_XL) { 994 /* Hardware errata - clear flush mask */ 995 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); 996 } else { 997 /* Flush Rx MAC FIFO on any flow control or error */ 998 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 999 } 1000 1001 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ 1002 reg = RX_GMF_FL_THR_DEF + 1; 1003 /* Another magic mystery workaround from sk98lin */ 1004 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1005 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1006 reg = 0x178; 1007 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); 1008 1009 /* Configure Tx MAC FIFO */ 1010 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 1011 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 1012 1013 /* On chips without ram buffer, pause is controlled by MAC level */ 1014 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { 1015 /* Pause threshold is scaled by 8 in bytes */ 1016 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1017 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1018 reg = 1568 / 8; 1019 else 1020 reg = 1024 / 8; 1021 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); 1022 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); 1023 1024 sky2_set_tx_stfwd(hw, port); 1025 } 1026 1027 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1028 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 1029 /* disable dynamic watermark */ 1030 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); 1031 reg &= ~TX_DYN_WM_ENA; 1032 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); 1033 } 1034 } 1035 1036 /* Assign Ram Buffer allocation to queue */ 1037 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) 1038 { 1039 u32 end; 1040 1041 /* convert from K bytes to qwords used for hw register */ 1042 start *= 1024/8; 1043 space *= 1024/8; 1044 end = start + space - 1; 1045 1046 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 1047 sky2_write32(hw, RB_ADDR(q, RB_START), start); 1048 sky2_write32(hw, RB_ADDR(q, RB_END), end); 1049 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 1050 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 1051 1052 if (q == Q_R1 || q == Q_R2) { 1053 u32 tp = space - space/4; 1054 1055 /* On receive queue's set the thresholds 1056 * give receiver priority when > 3/4 full 1057 * send pause when down to 2K 1058 */ 1059 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 1060 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 1061 1062 tp = space - 8192/8; 1063 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 1064 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 1065 } else { 1066 /* Enable store & forward on Tx queue's because 1067 * Tx FIFO is only 1K on Yukon 1068 */ 1069 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 1070 } 1071 1072 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 1073 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 1074 } 1075 1076 /* Setup Bus Memory Interface */ 1077 static void sky2_qset(struct sky2_hw *hw, u16 q) 1078 { 1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 1080 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 1081 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 1082 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 1083 } 1084 1085 /* Setup prefetch unit registers. This is the interface between 1086 * hardware and driver list elements 1087 */ 1088 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, 1089 dma_addr_t addr, u32 last) 1090 { 1091 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1092 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 1093 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); 1094 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); 1095 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 1096 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 1097 1098 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 1099 } 1100 1101 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) 1102 { 1103 struct sky2_tx_le *le = sky2->tx_le + *slot; 1104 1105 *slot = RING_NEXT(*slot, sky2->tx_ring_size); 1106 le->ctrl = 0; 1107 return le; 1108 } 1109 1110 static void tx_init(struct sky2_port *sky2) 1111 { 1112 struct sky2_tx_le *le; 1113 1114 sky2->tx_prod = sky2->tx_cons = 0; 1115 sky2->tx_tcpsum = 0; 1116 sky2->tx_last_mss = 0; 1117 netdev_reset_queue(sky2->netdev); 1118 1119 le = get_tx_le(sky2, &sky2->tx_prod); 1120 le->addr = 0; 1121 le->opcode = OP_ADDR64 | HW_OWNER; 1122 sky2->tx_last_upper = 0; 1123 } 1124 1125 /* Update chip's next pointer */ 1126 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 1127 { 1128 /* Make sure write' to descriptors are complete before we tell hardware */ 1129 wmb(); 1130 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 1131 } 1132 1133 1134 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 1135 { 1136 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 1137 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 1138 le->ctrl = 0; 1139 return le; 1140 } 1141 1142 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) 1143 { 1144 unsigned size; 1145 1146 /* Space needed for frame data + headers rounded up */ 1147 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1148 1149 /* Stopping point for hardware truncation */ 1150 return (size - 8) / sizeof(u32); 1151 } 1152 1153 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) 1154 { 1155 struct rx_ring_info *re; 1156 unsigned size; 1157 1158 /* Space needed for frame data + headers rounded up */ 1159 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1160 1161 sky2->rx_nfrags = size >> PAGE_SHIFT; 1162 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); 1163 1164 /* Compute residue after pages */ 1165 size -= sky2->rx_nfrags << PAGE_SHIFT; 1166 1167 /* Optimize to handle small packets and headers */ 1168 if (size < copybreak) 1169 size = copybreak; 1170 if (size < ETH_HLEN) 1171 size = ETH_HLEN; 1172 1173 return size; 1174 } 1175 1176 /* Build description to hardware for one receive segment */ 1177 static void sky2_rx_add(struct sky2_port *sky2, u8 op, 1178 dma_addr_t map, unsigned len) 1179 { 1180 struct sky2_rx_le *le; 1181 1182 if (sizeof(dma_addr_t) > sizeof(u32)) { 1183 le = sky2_next_rx(sky2); 1184 le->addr = cpu_to_le32(upper_32_bits(map)); 1185 le->opcode = OP_ADDR64 | HW_OWNER; 1186 } 1187 1188 le = sky2_next_rx(sky2); 1189 le->addr = cpu_to_le32(lower_32_bits(map)); 1190 le->length = cpu_to_le16(len); 1191 le->opcode = op | HW_OWNER; 1192 } 1193 1194 /* Build description to hardware for one possibly fragmented skb */ 1195 static void sky2_rx_submit(struct sky2_port *sky2, 1196 const struct rx_ring_info *re) 1197 { 1198 int i; 1199 1200 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); 1201 1202 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) 1203 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); 1204 } 1205 1206 1207 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, 1208 unsigned size) 1209 { 1210 struct sk_buff *skb = re->skb; 1211 int i; 1212 1213 re->data_addr = dma_map_single(&pdev->dev, skb->data, size, 1214 DMA_FROM_DEVICE); 1215 if (dma_mapping_error(&pdev->dev, re->data_addr)) 1216 goto mapping_error; 1217 1218 dma_unmap_len_set(re, data_size, size); 1219 1220 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1221 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1222 1223 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0, 1224 skb_frag_size(frag), 1225 DMA_FROM_DEVICE); 1226 1227 if (dma_mapping_error(&pdev->dev, re->frag_addr[i])) 1228 goto map_page_error; 1229 } 1230 return 0; 1231 1232 map_page_error: 1233 while (--i >= 0) { 1234 dma_unmap_page(&pdev->dev, re->frag_addr[i], 1235 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1236 DMA_FROM_DEVICE); 1237 } 1238 1239 dma_unmap_single(&pdev->dev, re->data_addr, 1240 dma_unmap_len(re, data_size), DMA_FROM_DEVICE); 1241 1242 mapping_error: 1243 if (net_ratelimit()) 1244 dev_warn(&pdev->dev, "%s: rx mapping error\n", 1245 skb->dev->name); 1246 return -EIO; 1247 } 1248 1249 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) 1250 { 1251 struct sk_buff *skb = re->skb; 1252 int i; 1253 1254 dma_unmap_single(&pdev->dev, re->data_addr, 1255 dma_unmap_len(re, data_size), DMA_FROM_DEVICE); 1256 1257 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) 1258 dma_unmap_page(&pdev->dev, re->frag_addr[i], 1259 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1260 DMA_FROM_DEVICE); 1261 } 1262 1263 /* Tell chip where to start receive checksum. 1264 * Actually has two checksums, but set both same to avoid possible byte 1265 * order problems. 1266 */ 1267 static void rx_set_checksum(struct sky2_port *sky2) 1268 { 1269 struct sky2_rx_le *le = sky2_next_rx(sky2); 1270 1271 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); 1272 le->ctrl = 0; 1273 le->opcode = OP_TCPSTART | HW_OWNER; 1274 1275 sky2_write32(sky2->hw, 1276 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1277 (sky2->netdev->features & NETIF_F_RXCSUM) 1278 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 1279 } 1280 1281 /* Enable/disable receive hash calculation (RSS) */ 1282 static void rx_set_rss(struct net_device *dev, netdev_features_t features) 1283 { 1284 struct sky2_port *sky2 = netdev_priv(dev); 1285 struct sky2_hw *hw = sky2->hw; 1286 int i, nkeys = 4; 1287 1288 /* Supports IPv6 and other modes */ 1289 if (hw->flags & SKY2_HW_NEW_LE) { 1290 nkeys = 10; 1291 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); 1292 } 1293 1294 /* Program RSS initial values */ 1295 if (features & NETIF_F_RXHASH) { 1296 u32 rss_key[10]; 1297 1298 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 1299 for (i = 0; i < nkeys; i++) 1300 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), 1301 rss_key[i]); 1302 1303 /* Need to turn on (undocumented) flag to make hashing work */ 1304 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), 1305 RX_STFW_ENA); 1306 1307 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1308 BMU_ENA_RX_RSS_HASH); 1309 } else 1310 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1311 BMU_DIS_RX_RSS_HASH); 1312 } 1313 1314 /* 1315 * The RX Stop command will not work for Yukon-2 if the BMU does not 1316 * reach the end of packet and since we can't make sure that we have 1317 * incoming data, we must reset the BMU while it is not doing a DMA 1318 * transfer. Since it is possible that the RX path is still active, 1319 * the RX RAM buffer will be stopped first, so any possible incoming 1320 * data will not trigger a DMA. After the RAM buffer is stopped, the 1321 * BMU is polled until any DMA in progress is ended and only then it 1322 * will be reset. 1323 */ 1324 static void sky2_rx_stop(struct sky2_port *sky2) 1325 { 1326 struct sky2_hw *hw = sky2->hw; 1327 unsigned rxq = rxqaddr[sky2->port]; 1328 int i; 1329 1330 /* disable the RAM Buffer receive queue */ 1331 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 1332 1333 for (i = 0; i < 0xffff; i++) 1334 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 1335 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 1336 goto stopped; 1337 1338 netdev_warn(sky2->netdev, "receiver stop failed\n"); 1339 stopped: 1340 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 1341 1342 /* reset the Rx prefetch unit */ 1343 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1344 } 1345 1346 /* Clean out receive buffer area, assumes receiver hardware stopped */ 1347 static void sky2_rx_clean(struct sky2_port *sky2) 1348 { 1349 unsigned i; 1350 1351 if (sky2->rx_le) 1352 memset(sky2->rx_le, 0, RX_LE_BYTES); 1353 1354 for (i = 0; i < sky2->rx_pending; i++) { 1355 struct rx_ring_info *re = sky2->rx_ring + i; 1356 1357 if (re->skb) { 1358 sky2_rx_unmap_skb(sky2->hw->pdev, re); 1359 kfree_skb(re->skb); 1360 re->skb = NULL; 1361 } 1362 } 1363 } 1364 1365 /* Basic MII support */ 1366 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1367 { 1368 struct mii_ioctl_data *data = if_mii(ifr); 1369 struct sky2_port *sky2 = netdev_priv(dev); 1370 struct sky2_hw *hw = sky2->hw; 1371 int err = -EOPNOTSUPP; 1372 1373 if (!netif_running(dev)) 1374 return -ENODEV; /* Phy still in reset */ 1375 1376 switch (cmd) { 1377 case SIOCGMIIPHY: 1378 data->phy_id = PHY_ADDR_MARV; 1379 1380 fallthrough; 1381 case SIOCGMIIREG: { 1382 u16 val = 0; 1383 1384 spin_lock_bh(&sky2->phy_lock); 1385 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); 1386 spin_unlock_bh(&sky2->phy_lock); 1387 1388 data->val_out = val; 1389 break; 1390 } 1391 1392 case SIOCSMIIREG: 1393 spin_lock_bh(&sky2->phy_lock); 1394 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, 1395 data->val_in); 1396 spin_unlock_bh(&sky2->phy_lock); 1397 break; 1398 } 1399 return err; 1400 } 1401 1402 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) 1403 1404 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features) 1405 { 1406 struct sky2_port *sky2 = netdev_priv(dev); 1407 struct sky2_hw *hw = sky2->hw; 1408 u16 port = sky2->port; 1409 1410 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1411 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1412 RX_VLAN_STRIP_ON); 1413 else 1414 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1415 RX_VLAN_STRIP_OFF); 1416 1417 if (features & NETIF_F_HW_VLAN_CTAG_TX) { 1418 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1419 TX_VLAN_TAG_ON); 1420 1421 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 1422 } else { 1423 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1424 TX_VLAN_TAG_OFF); 1425 1426 /* Can't do transmit offload of vlan without hw vlan */ 1427 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; 1428 } 1429 } 1430 1431 /* Amount of required worst case padding in rx buffer */ 1432 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) 1433 { 1434 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; 1435 } 1436 1437 /* 1438 * Allocate an skb for receiving. If the MTU is large enough 1439 * make the skb non-linear with a fragment list of pages. 1440 */ 1441 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp) 1442 { 1443 struct sk_buff *skb; 1444 int i; 1445 1446 skb = __netdev_alloc_skb(sky2->netdev, 1447 sky2->rx_data_size + sky2_rx_pad(sky2->hw), 1448 gfp); 1449 if (!skb) 1450 goto nomem; 1451 1452 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { 1453 unsigned char *start; 1454 /* 1455 * Workaround for a bug in FIFO that cause hang 1456 * if the FIFO if the receive buffer is not 64 byte aligned. 1457 * The buffer returned from netdev_alloc_skb is 1458 * aligned except if slab debugging is enabled. 1459 */ 1460 start = PTR_ALIGN(skb->data, 8); 1461 skb_reserve(skb, start - skb->data); 1462 } else 1463 skb_reserve(skb, NET_IP_ALIGN); 1464 1465 for (i = 0; i < sky2->rx_nfrags; i++) { 1466 struct page *page = alloc_page(gfp); 1467 1468 if (!page) 1469 goto free_partial; 1470 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); 1471 } 1472 1473 return skb; 1474 free_partial: 1475 kfree_skb(skb); 1476 nomem: 1477 return NULL; 1478 } 1479 1480 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) 1481 { 1482 sky2_put_idx(sky2->hw, rxq, sky2->rx_put); 1483 } 1484 1485 static int sky2_alloc_rx_skbs(struct sky2_port *sky2) 1486 { 1487 struct sky2_hw *hw = sky2->hw; 1488 unsigned i; 1489 1490 sky2->rx_data_size = sky2_get_rx_data_size(sky2); 1491 1492 /* Fill Rx ring */ 1493 for (i = 0; i < sky2->rx_pending; i++) { 1494 struct rx_ring_info *re = sky2->rx_ring + i; 1495 1496 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL); 1497 if (!re->skb) 1498 return -ENOMEM; 1499 1500 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { 1501 dev_kfree_skb(re->skb); 1502 re->skb = NULL; 1503 return -ENOMEM; 1504 } 1505 } 1506 return 0; 1507 } 1508 1509 /* 1510 * Setup receiver buffer pool. 1511 * Normal case this ends up creating one list element for skb 1512 * in the receive ring. Worst case if using large MTU and each 1513 * allocation falls on a different 64 bit region, that results 1514 * in 6 list elements per ring entry. 1515 * One element is used for checksum enable/disable, and one 1516 * extra to avoid wrap. 1517 */ 1518 static void sky2_rx_start(struct sky2_port *sky2) 1519 { 1520 struct sky2_hw *hw = sky2->hw; 1521 struct rx_ring_info *re; 1522 unsigned rxq = rxqaddr[sky2->port]; 1523 unsigned i, thresh; 1524 1525 sky2->rx_put = sky2->rx_next = 0; 1526 sky2_qset(hw, rxq); 1527 1528 /* On PCI express lowering the watermark gives better performance */ 1529 if (pci_is_pcie(hw->pdev)) 1530 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); 1531 1532 /* These chips have no ram buffer? 1533 * MAC Rx RAM Read is controlled by hardware 1534 */ 1535 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1536 hw->chip_rev > CHIP_REV_YU_EC_U_A0) 1537 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); 1538 1539 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 1540 1541 if (!(hw->flags & SKY2_HW_NEW_LE)) 1542 rx_set_checksum(sky2); 1543 1544 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 1545 rx_set_rss(sky2->netdev, sky2->netdev->features); 1546 1547 /* submit Rx ring */ 1548 for (i = 0; i < sky2->rx_pending; i++) { 1549 re = sky2->rx_ring + i; 1550 sky2_rx_submit(sky2, re); 1551 } 1552 1553 /* 1554 * The receiver hangs if it receives frames larger than the 1555 * packet buffer. As a workaround, truncate oversize frames, but 1556 * the register is limited to 9 bits, so if you do frames > 2052 1557 * you better get the MTU right! 1558 */ 1559 thresh = sky2_get_rx_threshold(sky2); 1560 if (thresh > 0x1ff) 1561 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); 1562 else { 1563 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); 1564 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 1565 } 1566 1567 /* Tell chip about available buffers */ 1568 sky2_rx_update(sky2, rxq); 1569 1570 if (hw->chip_id == CHIP_ID_YUKON_EX || 1571 hw->chip_id == CHIP_ID_YUKON_SUPR) { 1572 /* 1573 * Disable flushing of non ASF packets; 1574 * must be done after initializing the BMUs; 1575 * drivers without ASF support should do this too, otherwise 1576 * it may happen that they cannot run on ASF devices; 1577 * remember that the MAC FIFO isn't reset during initialization. 1578 */ 1579 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); 1580 } 1581 1582 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { 1583 /* Enable RX Home Address & Routing Header checksum fix */ 1584 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), 1585 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); 1586 1587 /* Enable TX Home Address & Routing Header checksum fix */ 1588 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), 1589 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); 1590 } 1591 } 1592 1593 static int sky2_alloc_buffers(struct sky2_port *sky2) 1594 { 1595 struct sky2_hw *hw = sky2->hw; 1596 1597 /* must be power of 2 */ 1598 sky2->tx_le = dma_alloc_coherent(&hw->pdev->dev, 1599 sky2->tx_ring_size * sizeof(struct sky2_tx_le), 1600 &sky2->tx_le_map, GFP_KERNEL); 1601 if (!sky2->tx_le) 1602 goto nomem; 1603 1604 sky2->tx_ring = kzalloc_objs(struct tx_ring_info, sky2->tx_ring_size); 1605 if (!sky2->tx_ring) 1606 goto nomem; 1607 1608 sky2->rx_le = dma_alloc_coherent(&hw->pdev->dev, RX_LE_BYTES, 1609 &sky2->rx_le_map, GFP_KERNEL); 1610 if (!sky2->rx_le) 1611 goto nomem; 1612 1613 sky2->rx_ring = kzalloc_objs(struct rx_ring_info, sky2->rx_pending); 1614 if (!sky2->rx_ring) 1615 goto nomem; 1616 1617 return sky2_alloc_rx_skbs(sky2); 1618 nomem: 1619 return -ENOMEM; 1620 } 1621 1622 static void sky2_free_buffers(struct sky2_port *sky2) 1623 { 1624 struct sky2_hw *hw = sky2->hw; 1625 1626 sky2_rx_clean(sky2); 1627 1628 if (sky2->rx_le) { 1629 dma_free_coherent(&hw->pdev->dev, RX_LE_BYTES, sky2->rx_le, 1630 sky2->rx_le_map); 1631 sky2->rx_le = NULL; 1632 } 1633 if (sky2->tx_le) { 1634 dma_free_coherent(&hw->pdev->dev, 1635 sky2->tx_ring_size * sizeof(struct sky2_tx_le), 1636 sky2->tx_le, sky2->tx_le_map); 1637 sky2->tx_le = NULL; 1638 } 1639 kfree(sky2->tx_ring); 1640 kfree(sky2->rx_ring); 1641 1642 sky2->tx_ring = NULL; 1643 sky2->rx_ring = NULL; 1644 } 1645 1646 static void sky2_hw_up(struct sky2_port *sky2) 1647 { 1648 struct sky2_hw *hw = sky2->hw; 1649 unsigned port = sky2->port; 1650 u32 ramsize; 1651 int cap; 1652 struct net_device *otherdev = hw->dev[sky2->port^1]; 1653 1654 tx_init(sky2); 1655 1656 /* 1657 * On dual port PCI-X card, there is an problem where status 1658 * can be received out of order due to split transactions 1659 */ 1660 if (otherdev && netif_running(otherdev) && 1661 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { 1662 u16 cmd; 1663 1664 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); 1665 cmd &= ~PCI_X_CMD_MAX_SPLIT; 1666 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); 1667 } 1668 1669 sky2_mac_init(hw, port); 1670 1671 /* Register is number of 4K blocks on internal RAM buffer. */ 1672 ramsize = sky2_read8(hw, B2_E_0) * 4; 1673 if (ramsize > 0) { 1674 u32 rxspace; 1675 1676 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); 1677 if (ramsize < 16) 1678 rxspace = ramsize / 2; 1679 else 1680 rxspace = 8 + (2*(ramsize - 16))/3; 1681 1682 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1683 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); 1684 1685 /* Make sure SyncQ is disabled */ 1686 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1687 RB_RST_SET); 1688 } 1689 1690 sky2_qset(hw, txqaddr[port]); 1691 1692 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ 1693 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) 1694 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); 1695 1696 /* Set almost empty threshold */ 1697 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1698 hw->chip_rev == CHIP_REV_YU_EC_U_A0) 1699 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); 1700 1701 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1702 sky2->tx_ring_size - 1); 1703 1704 sky2_vlan_mode(sky2->netdev, sky2->netdev->features); 1705 netdev_update_features(sky2->netdev); 1706 1707 sky2_rx_start(sky2); 1708 } 1709 1710 /* Setup device IRQ and enable napi to process */ 1711 static int sky2_setup_irq(struct sky2_hw *hw, const char *name) 1712 { 1713 struct pci_dev *pdev = hw->pdev; 1714 int err; 1715 1716 err = request_irq(pdev->irq, sky2_intr, 1717 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, 1718 name, hw); 1719 if (err) 1720 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 1721 else { 1722 hw->flags |= SKY2_HW_IRQ_SETUP; 1723 1724 napi_enable(&hw->napi); 1725 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 1726 sky2_read32(hw, B0_IMSK); 1727 } 1728 1729 return err; 1730 } 1731 1732 1733 /* Bring up network interface. */ 1734 static int sky2_open(struct net_device *dev) 1735 { 1736 struct sky2_port *sky2 = netdev_priv(dev); 1737 struct sky2_hw *hw = sky2->hw; 1738 unsigned port = sky2->port; 1739 u32 imask; 1740 int err; 1741 1742 netif_carrier_off(dev); 1743 1744 err = sky2_alloc_buffers(sky2); 1745 if (err) 1746 goto err_out; 1747 1748 /* With single port, IRQ is setup when device is brought up */ 1749 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name))) 1750 goto err_out; 1751 1752 sky2_hw_up(sky2); 1753 1754 /* Enable interrupts from phy/mac for port */ 1755 imask = sky2_read32(hw, B0_IMSK); 1756 1757 if (hw->chip_id == CHIP_ID_YUKON_OPT || 1758 hw->chip_id == CHIP_ID_YUKON_PRM || 1759 hw->chip_id == CHIP_ID_YUKON_OP_2) 1760 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */ 1761 1762 imask |= portirq_msk[port]; 1763 sky2_write32(hw, B0_IMSK, imask); 1764 sky2_read32(hw, B0_IMSK); 1765 1766 netif_info(sky2, ifup, dev, "enabling interface\n"); 1767 1768 return 0; 1769 1770 err_out: 1771 sky2_free_buffers(sky2); 1772 return err; 1773 } 1774 1775 /* Modular subtraction in ring */ 1776 static inline int tx_inuse(const struct sky2_port *sky2) 1777 { 1778 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); 1779 } 1780 1781 /* Number of list elements available for next tx */ 1782 static inline int tx_avail(const struct sky2_port *sky2) 1783 { 1784 return sky2->tx_pending - tx_inuse(sky2); 1785 } 1786 1787 /* Estimate of number of transmit list elements required */ 1788 static unsigned tx_le_req(const struct sk_buff *skb) 1789 { 1790 unsigned count; 1791 1792 count = (skb_shinfo(skb)->nr_frags + 1) 1793 * (sizeof(dma_addr_t) / sizeof(u32)); 1794 1795 if (skb_is_gso(skb)) 1796 ++count; 1797 else if (sizeof(dma_addr_t) == sizeof(u32)) 1798 ++count; /* possible vlan */ 1799 1800 if (skb->ip_summed == CHECKSUM_PARTIAL) 1801 ++count; 1802 1803 return count; 1804 } 1805 1806 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) 1807 { 1808 if (re->flags & TX_MAP_SINGLE) 1809 dma_unmap_single(&pdev->dev, dma_unmap_addr(re, mapaddr), 1810 dma_unmap_len(re, maplen), DMA_TO_DEVICE); 1811 else if (re->flags & TX_MAP_PAGE) 1812 dma_unmap_page(&pdev->dev, dma_unmap_addr(re, mapaddr), 1813 dma_unmap_len(re, maplen), DMA_TO_DEVICE); 1814 re->flags = 0; 1815 } 1816 1817 /* 1818 * Put one packet in ring for transmit. 1819 * A single packet can generate multiple list elements, and 1820 * the number of ring elements will probably be less than the number 1821 * of list elements used. 1822 */ 1823 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, 1824 struct net_device *dev) 1825 { 1826 struct sky2_port *sky2 = netdev_priv(dev); 1827 struct sky2_hw *hw = sky2->hw; 1828 struct sky2_tx_le *le = NULL; 1829 struct tx_ring_info *re; 1830 unsigned i, len; 1831 dma_addr_t mapping; 1832 u32 upper; 1833 u16 slot; 1834 u16 mss; 1835 u8 ctrl; 1836 1837 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) 1838 return NETDEV_TX_BUSY; 1839 1840 len = skb_headlen(skb); 1841 mapping = dma_map_single(&hw->pdev->dev, skb->data, len, 1842 DMA_TO_DEVICE); 1843 1844 if (dma_mapping_error(&hw->pdev->dev, mapping)) 1845 goto mapping_error; 1846 1847 slot = sky2->tx_prod; 1848 netif_printk(sky2, tx_queued, KERN_DEBUG, dev, 1849 "tx queued, slot %u, len %d\n", slot, skb->len); 1850 1851 /* Send high bits if needed */ 1852 upper = upper_32_bits(mapping); 1853 if (upper != sky2->tx_last_upper) { 1854 le = get_tx_le(sky2, &slot); 1855 le->addr = cpu_to_le32(upper); 1856 sky2->tx_last_upper = upper; 1857 le->opcode = OP_ADDR64 | HW_OWNER; 1858 } 1859 1860 /* Check for TCP Segmentation Offload */ 1861 mss = skb_shinfo(skb)->gso_size; 1862 if (mss != 0) { 1863 1864 if (!(hw->flags & SKY2_HW_NEW_LE)) 1865 mss += skb_tcp_all_headers(skb); 1866 1867 if (mss != sky2->tx_last_mss) { 1868 le = get_tx_le(sky2, &slot); 1869 le->addr = cpu_to_le32(mss); 1870 1871 if (hw->flags & SKY2_HW_NEW_LE) 1872 le->opcode = OP_MSS | HW_OWNER; 1873 else 1874 le->opcode = OP_LRGLEN | HW_OWNER; 1875 sky2->tx_last_mss = mss; 1876 } 1877 } 1878 1879 ctrl = 0; 1880 1881 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ 1882 if (skb_vlan_tag_present(skb)) { 1883 if (!le) { 1884 le = get_tx_le(sky2, &slot); 1885 le->addr = 0; 1886 le->opcode = OP_VLAN|HW_OWNER; 1887 } else 1888 le->opcode |= OP_VLAN; 1889 le->length = cpu_to_be16(skb_vlan_tag_get(skb)); 1890 ctrl |= INS_VLAN; 1891 } 1892 1893 /* Handle TCP checksum offload */ 1894 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1895 /* On Yukon EX (some versions) encoding change. */ 1896 if (hw->flags & SKY2_HW_AUTO_TX_SUM) 1897 ctrl |= CALSUM; /* auto checksum */ 1898 else { 1899 const unsigned offset = skb_transport_offset(skb); 1900 u32 tcpsum; 1901 1902 tcpsum = offset << 16; /* sum start */ 1903 tcpsum |= offset + skb->csum_offset; /* sum write */ 1904 1905 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1906 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 1907 ctrl |= UDPTCP; 1908 1909 if (tcpsum != sky2->tx_tcpsum) { 1910 sky2->tx_tcpsum = tcpsum; 1911 1912 le = get_tx_le(sky2, &slot); 1913 le->addr = cpu_to_le32(tcpsum); 1914 le->length = 0; /* initial checksum value */ 1915 le->ctrl = 1; /* one packet */ 1916 le->opcode = OP_TCPLISW | HW_OWNER; 1917 } 1918 } 1919 } 1920 1921 re = sky2->tx_ring + slot; 1922 re->flags = TX_MAP_SINGLE; 1923 dma_unmap_addr_set(re, mapaddr, mapping); 1924 dma_unmap_len_set(re, maplen, len); 1925 1926 le = get_tx_le(sky2, &slot); 1927 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1928 le->length = cpu_to_le16(len); 1929 le->ctrl = ctrl; 1930 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); 1931 1932 1933 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1934 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1935 1936 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0, 1937 skb_frag_size(frag), DMA_TO_DEVICE); 1938 1939 if (dma_mapping_error(&hw->pdev->dev, mapping)) 1940 goto mapping_unwind; 1941 1942 upper = upper_32_bits(mapping); 1943 if (upper != sky2->tx_last_upper) { 1944 le = get_tx_le(sky2, &slot); 1945 le->addr = cpu_to_le32(upper); 1946 sky2->tx_last_upper = upper; 1947 le->opcode = OP_ADDR64 | HW_OWNER; 1948 } 1949 1950 re = sky2->tx_ring + slot; 1951 re->flags = TX_MAP_PAGE; 1952 dma_unmap_addr_set(re, mapaddr, mapping); 1953 dma_unmap_len_set(re, maplen, skb_frag_size(frag)); 1954 1955 le = get_tx_le(sky2, &slot); 1956 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1957 le->length = cpu_to_le16(skb_frag_size(frag)); 1958 le->ctrl = ctrl; 1959 le->opcode = OP_BUFFER | HW_OWNER; 1960 } 1961 1962 re->skb = skb; 1963 le->ctrl |= EOP; 1964 1965 sky2->tx_prod = slot; 1966 1967 if (tx_avail(sky2) <= MAX_SKB_TX_LE) 1968 netif_stop_queue(dev); 1969 1970 netdev_sent_queue(dev, skb->len); 1971 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1972 1973 return NETDEV_TX_OK; 1974 1975 mapping_unwind: 1976 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { 1977 re = sky2->tx_ring + i; 1978 1979 sky2_tx_unmap(hw->pdev, re); 1980 } 1981 1982 mapping_error: 1983 if (net_ratelimit()) 1984 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 1985 dev_kfree_skb_any(skb); 1986 return NETDEV_TX_OK; 1987 } 1988 1989 /* 1990 * Free ring elements from starting at tx_cons until "done" 1991 * 1992 * NB: 1993 * 1. The hardware will tell us about partial completion of multi-part 1994 * buffers so make sure not to free skb to early. 1995 * 2. This may run in parallel start_xmit because the it only 1996 * looks at the tail of the queue of FIFO (tx_cons), not 1997 * the head (tx_prod) 1998 */ 1999 static void sky2_tx_complete(struct sky2_port *sky2, u16 done) 2000 { 2001 struct net_device *dev = sky2->netdev; 2002 u16 idx; 2003 unsigned int bytes_compl = 0, pkts_compl = 0; 2004 2005 BUG_ON(done >= sky2->tx_ring_size); 2006 2007 for (idx = sky2->tx_cons; idx != done; 2008 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 2009 struct tx_ring_info *re = sky2->tx_ring + idx; 2010 struct sk_buff *skb = re->skb; 2011 2012 sky2_tx_unmap(sky2->hw->pdev, re); 2013 2014 if (skb) { 2015 netif_printk(sky2, tx_done, KERN_DEBUG, dev, 2016 "tx done %u\n", idx); 2017 2018 pkts_compl++; 2019 bytes_compl += skb->len; 2020 2021 re->skb = NULL; 2022 dev_kfree_skb_any(skb); 2023 2024 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); 2025 } 2026 } 2027 2028 sky2->tx_cons = idx; 2029 smp_mb(); 2030 2031 netdev_completed_queue(dev, pkts_compl, bytes_compl); 2032 2033 u64_stats_update_begin(&sky2->tx_stats.syncp); 2034 sky2->tx_stats.packets += pkts_compl; 2035 sky2->tx_stats.bytes += bytes_compl; 2036 u64_stats_update_end(&sky2->tx_stats.syncp); 2037 } 2038 2039 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) 2040 { 2041 /* Disable Force Sync bit and Enable Alloc bit */ 2042 sky2_write8(hw, SK_REG(port, TXA_CTRL), 2043 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2044 2045 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2046 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2047 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2048 2049 /* Reset the PCI FIFO of the async Tx queue */ 2050 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 2051 BMU_RST_SET | BMU_FIFO_RST); 2052 2053 /* Reset the Tx prefetch units */ 2054 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 2055 PREF_UNIT_RST_SET); 2056 2057 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2058 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2059 2060 sky2_read32(hw, B0_CTST); 2061 } 2062 2063 static void sky2_hw_down(struct sky2_port *sky2) 2064 { 2065 struct sky2_hw *hw = sky2->hw; 2066 unsigned port = sky2->port; 2067 u16 ctrl; 2068 2069 /* Force flow control off */ 2070 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2071 2072 /* Stop transmitter */ 2073 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 2074 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 2075 2076 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2077 RB_RST_SET | RB_DIS_OP_MD); 2078 2079 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2080 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 2081 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2082 2083 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2084 2085 /* Workaround shared GMAC reset */ 2086 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && 2087 port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 2088 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2089 2090 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2091 2092 /* Force any delayed status interrupt and NAPI */ 2093 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); 2094 sky2_write32(hw, STAT_TX_TIMER_CNT, 0); 2095 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); 2096 sky2_read8(hw, STAT_ISR_TIMER_CTRL); 2097 2098 sky2_rx_stop(sky2); 2099 2100 spin_lock_bh(&sky2->phy_lock); 2101 sky2_phy_power_down(hw, port); 2102 spin_unlock_bh(&sky2->phy_lock); 2103 2104 sky2_tx_reset(hw, port); 2105 2106 /* Free any pending frames stuck in HW queue */ 2107 sky2_tx_complete(sky2, sky2->tx_prod); 2108 } 2109 2110 /* Network shutdown */ 2111 static int sky2_close(struct net_device *dev) 2112 { 2113 struct sky2_port *sky2 = netdev_priv(dev); 2114 struct sky2_hw *hw = sky2->hw; 2115 2116 /* Never really got started! */ 2117 if (!sky2->tx_le) 2118 return 0; 2119 2120 netif_info(sky2, ifdown, dev, "disabling interface\n"); 2121 2122 if (hw->ports == 1) { 2123 sky2_write32(hw, B0_IMSK, 0); 2124 sky2_read32(hw, B0_IMSK); 2125 2126 napi_disable(&hw->napi); 2127 free_irq(hw->pdev->irq, hw); 2128 hw->flags &= ~SKY2_HW_IRQ_SETUP; 2129 } else { 2130 u32 imask; 2131 2132 /* Disable port IRQ */ 2133 imask = sky2_read32(hw, B0_IMSK); 2134 imask &= ~portirq_msk[sky2->port]; 2135 sky2_write32(hw, B0_IMSK, imask); 2136 sky2_read32(hw, B0_IMSK); 2137 2138 synchronize_irq(hw->pdev->irq); 2139 napi_synchronize(&hw->napi); 2140 } 2141 2142 sky2_hw_down(sky2); 2143 2144 sky2_free_buffers(sky2); 2145 2146 return 0; 2147 } 2148 2149 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) 2150 { 2151 if (hw->flags & SKY2_HW_FIBRE_PHY) 2152 return SPEED_1000; 2153 2154 if (!(hw->flags & SKY2_HW_GIGABIT)) { 2155 if (aux & PHY_M_PS_SPEED_100) 2156 return SPEED_100; 2157 else 2158 return SPEED_10; 2159 } 2160 2161 switch (aux & PHY_M_PS_SPEED_MSK) { 2162 case PHY_M_PS_SPEED_1000: 2163 return SPEED_1000; 2164 case PHY_M_PS_SPEED_100: 2165 return SPEED_100; 2166 default: 2167 return SPEED_10; 2168 } 2169 } 2170 2171 static void sky2_link_up(struct sky2_port *sky2) 2172 { 2173 struct sky2_hw *hw = sky2->hw; 2174 unsigned port = sky2->port; 2175 static const char *fc_name[] = { 2176 [FC_NONE] = "none", 2177 [FC_TX] = "tx", 2178 [FC_RX] = "rx", 2179 [FC_BOTH] = "both", 2180 }; 2181 2182 sky2_set_ipg(sky2); 2183 2184 sky2_enable_rx_tx(sky2); 2185 2186 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 2187 2188 netif_carrier_on(sky2->netdev); 2189 2190 mod_timer(&hw->watchdog_timer, jiffies + 1); 2191 2192 /* Turn on link LED */ 2193 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 2194 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 2195 2196 netif_info(sky2, link, sky2->netdev, 2197 "Link is up at %d Mbps, %s duplex, flow control %s\n", 2198 sky2->speed, 2199 sky2->duplex == DUPLEX_FULL ? "full" : "half", 2200 fc_name[sky2->flow_status]); 2201 } 2202 2203 static void sky2_link_down(struct sky2_port *sky2) 2204 { 2205 struct sky2_hw *hw = sky2->hw; 2206 unsigned port = sky2->port; 2207 u16 reg; 2208 2209 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 2210 2211 reg = gma_read16(hw, port, GM_GP_CTRL); 2212 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2213 gma_write16(hw, port, GM_GP_CTRL, reg); 2214 2215 netif_carrier_off(sky2->netdev); 2216 2217 /* Turn off link LED */ 2218 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 2219 2220 netif_info(sky2, link, sky2->netdev, "Link is down\n"); 2221 2222 sky2_phy_init(hw, port); 2223 } 2224 2225 static enum flow_control sky2_flow(int rx, int tx) 2226 { 2227 if (rx) 2228 return tx ? FC_BOTH : FC_RX; 2229 else 2230 return tx ? FC_TX : FC_NONE; 2231 } 2232 2233 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 2234 { 2235 struct sky2_hw *hw = sky2->hw; 2236 unsigned port = sky2->port; 2237 u16 advert, lpa; 2238 2239 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2240 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 2241 if (lpa & PHY_M_AN_RF) { 2242 netdev_err(sky2->netdev, "remote fault\n"); 2243 return -1; 2244 } 2245 2246 if (!(aux & PHY_M_PS_SPDUP_RES)) { 2247 netdev_err(sky2->netdev, "speed/duplex mismatch\n"); 2248 return -1; 2249 } 2250 2251 sky2->speed = sky2_phy_speed(hw, aux); 2252 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2253 2254 /* Since the pause result bits seem to in different positions on 2255 * different chips. look at registers. 2256 */ 2257 if (hw->flags & SKY2_HW_FIBRE_PHY) { 2258 /* Shift for bits in fiber PHY */ 2259 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); 2260 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); 2261 2262 if (advert & ADVERTISE_1000XPAUSE) 2263 advert |= ADVERTISE_PAUSE_CAP; 2264 if (advert & ADVERTISE_1000XPSE_ASYM) 2265 advert |= ADVERTISE_PAUSE_ASYM; 2266 if (lpa & LPA_1000XPAUSE) 2267 lpa |= LPA_PAUSE_CAP; 2268 if (lpa & LPA_1000XPAUSE_ASYM) 2269 lpa |= LPA_PAUSE_ASYM; 2270 } 2271 2272 sky2->flow_status = FC_NONE; 2273 if (advert & ADVERTISE_PAUSE_CAP) { 2274 if (lpa & LPA_PAUSE_CAP) 2275 sky2->flow_status = FC_BOTH; 2276 else if (advert & ADVERTISE_PAUSE_ASYM) 2277 sky2->flow_status = FC_RX; 2278 } else if (advert & ADVERTISE_PAUSE_ASYM) { 2279 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) 2280 sky2->flow_status = FC_TX; 2281 } 2282 2283 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && 2284 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) 2285 sky2->flow_status = FC_NONE; 2286 2287 if (sky2->flow_status & FC_TX) 2288 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2289 else 2290 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2291 2292 return 0; 2293 } 2294 2295 /* Interrupt from PHY */ 2296 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) 2297 { 2298 struct net_device *dev = hw->dev[port]; 2299 struct sky2_port *sky2 = netdev_priv(dev); 2300 u16 istatus, phystat; 2301 2302 if (!netif_running(dev)) 2303 return; 2304 2305 spin_lock(&sky2->phy_lock); 2306 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2307 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2308 2309 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", 2310 istatus, phystat); 2311 2312 if (istatus & PHY_M_IS_AN_COMPL) { 2313 if (sky2_autoneg_done(sky2, phystat) == 0 && 2314 !netif_carrier_ok(dev)) 2315 sky2_link_up(sky2); 2316 goto out; 2317 } 2318 2319 if (istatus & PHY_M_IS_LSP_CHANGE) 2320 sky2->speed = sky2_phy_speed(hw, phystat); 2321 2322 if (istatus & PHY_M_IS_DUP_CHANGE) 2323 sky2->duplex = 2324 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2325 2326 if (istatus & PHY_M_IS_LST_CHANGE) { 2327 if (phystat & PHY_M_PS_LINK_UP) 2328 sky2_link_up(sky2); 2329 else 2330 sky2_link_down(sky2); 2331 } 2332 out: 2333 spin_unlock(&sky2->phy_lock); 2334 } 2335 2336 /* Special quick link interrupt (Yukon-2 Optima only) */ 2337 static void sky2_qlink_intr(struct sky2_hw *hw) 2338 { 2339 struct sky2_port *sky2 = netdev_priv(hw->dev[0]); 2340 u32 imask; 2341 u16 phy; 2342 2343 /* disable irq */ 2344 imask = sky2_read32(hw, B0_IMSK); 2345 imask &= ~Y2_IS_PHY_QLNK; 2346 sky2_write32(hw, B0_IMSK, imask); 2347 2348 /* reset PHY Link Detect */ 2349 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); 2350 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2351 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); 2352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2353 2354 sky2_link_up(sky2); 2355 } 2356 2357 /* Transmit timeout is only called if we are running, carrier is up 2358 * and tx queue is full (stopped). 2359 */ 2360 static void sky2_tx_timeout(struct net_device *dev, unsigned int txqueue) 2361 { 2362 struct sky2_port *sky2 = netdev_priv(dev); 2363 struct sky2_hw *hw = sky2->hw; 2364 2365 netif_err(sky2, timer, dev, "tx timeout\n"); 2366 2367 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", 2368 sky2->tx_cons, sky2->tx_prod, 2369 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 2370 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); 2371 2372 /* can't restart safely under softirq */ 2373 schedule_work(&hw->restart_work); 2374 } 2375 2376 static int sky2_change_mtu(struct net_device *dev, int new_mtu) 2377 { 2378 struct sky2_port *sky2 = netdev_priv(dev); 2379 struct sky2_hw *hw = sky2->hw; 2380 unsigned port = sky2->port; 2381 int err; 2382 u16 ctl, mode; 2383 u32 imask; 2384 2385 if (!netif_running(dev)) { 2386 WRITE_ONCE(dev->mtu, new_mtu); 2387 netdev_update_features(dev); 2388 return 0; 2389 } 2390 2391 imask = sky2_read32(hw, B0_IMSK); 2392 sky2_write32(hw, B0_IMSK, 0); 2393 sky2_read32(hw, B0_IMSK); 2394 2395 netif_trans_update(dev); /* prevent tx timeout */ 2396 napi_disable(&hw->napi); 2397 netif_tx_disable(dev); 2398 2399 synchronize_irq(hw->pdev->irq); 2400 2401 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) 2402 sky2_set_tx_stfwd(hw, port); 2403 2404 ctl = gma_read16(hw, port, GM_GP_CTRL); 2405 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); 2406 sky2_rx_stop(sky2); 2407 sky2_rx_clean(sky2); 2408 2409 WRITE_ONCE(dev->mtu, new_mtu); 2410 netdev_update_features(dev); 2411 2412 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA; 2413 if (sky2->speed > SPEED_100) 2414 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 2415 else 2416 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 2417 2418 if (dev->mtu > ETH_DATA_LEN) 2419 mode |= GM_SMOD_JUMBO_ENA; 2420 2421 gma_write16(hw, port, GM_SERIAL_MODE, mode); 2422 2423 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); 2424 2425 err = sky2_alloc_rx_skbs(sky2); 2426 if (!err) 2427 sky2_rx_start(sky2); 2428 else 2429 sky2_rx_clean(sky2); 2430 sky2_write32(hw, B0_IMSK, imask); 2431 2432 sky2_read32(hw, B0_Y2_SP_LISR); 2433 napi_enable(&hw->napi); 2434 2435 if (err) 2436 dev_close(dev); 2437 else { 2438 gma_write16(hw, port, GM_GP_CTRL, ctl); 2439 2440 netif_wake_queue(dev); 2441 } 2442 2443 return err; 2444 } 2445 2446 static inline bool needs_copy(const struct rx_ring_info *re, 2447 unsigned length) 2448 { 2449 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2450 /* Some architectures need the IP header to be aligned */ 2451 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32))) 2452 return true; 2453 #endif 2454 return length < copybreak; 2455 } 2456 2457 /* For small just reuse existing skb for next receive */ 2458 static struct sk_buff *receive_copy(struct sky2_port *sky2, 2459 const struct rx_ring_info *re, 2460 unsigned length) 2461 { 2462 struct sk_buff *skb; 2463 2464 skb = netdev_alloc_skb_ip_align(sky2->netdev, length); 2465 if (likely(skb)) { 2466 dma_sync_single_for_cpu(&sky2->hw->pdev->dev, re->data_addr, 2467 length, DMA_FROM_DEVICE); 2468 skb_copy_from_linear_data(re->skb, skb->data, length); 2469 skb->ip_summed = re->skb->ip_summed; 2470 skb->csum = re->skb->csum; 2471 skb_copy_hash(skb, re->skb); 2472 __vlan_hwaccel_copy_tag(skb, re->skb); 2473 2474 dma_sync_single_for_device(&sky2->hw->pdev->dev, 2475 re->data_addr, length, 2476 DMA_FROM_DEVICE); 2477 __vlan_hwaccel_clear_tag(re->skb); 2478 skb_clear_hash(re->skb); 2479 re->skb->ip_summed = CHECKSUM_NONE; 2480 skb_put(skb, length); 2481 } 2482 return skb; 2483 } 2484 2485 /* Adjust length of skb with fragments to match received data */ 2486 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, 2487 unsigned int length) 2488 { 2489 int i, num_frags; 2490 unsigned int size; 2491 2492 /* put header into skb */ 2493 size = min(length, hdr_space); 2494 skb->tail += size; 2495 skb->len += size; 2496 length -= size; 2497 2498 num_frags = skb_shinfo(skb)->nr_frags; 2499 for (i = 0; i < num_frags; i++) { 2500 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2501 2502 if (length == 0) { 2503 /* don't need this page */ 2504 __skb_frag_unref(frag, false); 2505 --skb_shinfo(skb)->nr_frags; 2506 } else { 2507 size = min(length, (unsigned) PAGE_SIZE); 2508 2509 skb_frag_size_set(frag, size); 2510 skb->data_len += size; 2511 skb->truesize += PAGE_SIZE; 2512 skb->len += size; 2513 length -= size; 2514 } 2515 } 2516 } 2517 2518 /* Normal packet - take skb from ring element and put in a new one */ 2519 static struct sk_buff *receive_new(struct sky2_port *sky2, 2520 struct rx_ring_info *re, 2521 unsigned int length) 2522 { 2523 struct sk_buff *skb; 2524 struct rx_ring_info nre; 2525 unsigned hdr_space = sky2->rx_data_size; 2526 2527 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC); 2528 if (unlikely(!nre.skb)) 2529 goto nobuf; 2530 2531 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) 2532 goto nomap; 2533 2534 skb = re->skb; 2535 sky2_rx_unmap_skb(sky2->hw->pdev, re); 2536 prefetch(skb->data); 2537 *re = nre; 2538 2539 if (skb_shinfo(skb)->nr_frags) 2540 skb_put_frags(skb, hdr_space, length); 2541 else 2542 skb_put(skb, length); 2543 return skb; 2544 2545 nomap: 2546 dev_kfree_skb(nre.skb); 2547 nobuf: 2548 return NULL; 2549 } 2550 2551 /* 2552 * Receive one packet. 2553 * For larger packets, get new buffer. 2554 */ 2555 static struct sk_buff *sky2_receive(struct net_device *dev, 2556 u16 length, u32 status) 2557 { 2558 struct sky2_port *sky2 = netdev_priv(dev); 2559 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; 2560 struct sk_buff *skb = NULL; 2561 u16 count = (status & GMR_FS_LEN) >> 16; 2562 2563 netif_printk(sky2, rx_status, KERN_DEBUG, dev, 2564 "rx slot %u status 0x%x len %d\n", 2565 sky2->rx_next, status, length); 2566 2567 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 2568 prefetch(sky2->rx_ring + sky2->rx_next); 2569 2570 if (skb_vlan_tag_present(re->skb)) 2571 count -= VLAN_HLEN; /* Account for vlan tag */ 2572 2573 /* This chip has hardware problems that generates bogus status. 2574 * So do only marginal checking and expect higher level protocols 2575 * to handle crap frames. 2576 */ 2577 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && 2578 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && 2579 length != count) 2580 goto okay; 2581 2582 if (status & GMR_FS_ANY_ERR) 2583 goto error; 2584 2585 if (!(status & GMR_FS_RX_OK)) 2586 goto resubmit; 2587 2588 /* if length reported by DMA does not match PHY, packet was truncated */ 2589 if (length != count) 2590 goto error; 2591 2592 okay: 2593 if (needs_copy(re, length)) 2594 skb = receive_copy(sky2, re, length); 2595 else 2596 skb = receive_new(sky2, re, length); 2597 2598 dev->stats.rx_dropped += (skb == NULL); 2599 2600 resubmit: 2601 sky2_rx_submit(sky2, re); 2602 2603 return skb; 2604 2605 error: 2606 ++dev->stats.rx_errors; 2607 2608 if (net_ratelimit()) 2609 netif_info(sky2, rx_err, dev, 2610 "rx error, status 0x%x length %d\n", status, length); 2611 2612 goto resubmit; 2613 } 2614 2615 /* Transmit complete */ 2616 static inline void sky2_tx_done(struct net_device *dev, u16 last) 2617 { 2618 struct sky2_port *sky2 = netdev_priv(dev); 2619 2620 if (netif_running(dev)) { 2621 sky2_tx_complete(sky2, last); 2622 2623 /* Wake unless it's detached, and called e.g. from sky2_close() */ 2624 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) 2625 netif_wake_queue(dev); 2626 } 2627 } 2628 2629 static inline void sky2_skb_rx(const struct sky2_port *sky2, 2630 struct sk_buff *skb) 2631 { 2632 if (skb->ip_summed == CHECKSUM_NONE) 2633 netif_receive_skb(skb); 2634 else 2635 napi_gro_receive(&sky2->hw->napi, skb); 2636 } 2637 2638 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, 2639 unsigned packets, unsigned bytes) 2640 { 2641 struct net_device *dev = hw->dev[port]; 2642 struct sky2_port *sky2 = netdev_priv(dev); 2643 2644 if (packets == 0) 2645 return; 2646 2647 u64_stats_update_begin(&sky2->rx_stats.syncp); 2648 sky2->rx_stats.packets += packets; 2649 sky2->rx_stats.bytes += bytes; 2650 u64_stats_update_end(&sky2->rx_stats.syncp); 2651 2652 sky2->last_rx = jiffies; 2653 sky2_rx_update(netdev_priv(dev), rxqaddr[port]); 2654 } 2655 2656 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) 2657 { 2658 /* If this happens then driver assuming wrong format for chip type */ 2659 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); 2660 2661 /* Both checksum counters are programmed to start at 2662 * the same offset, so unless there is a problem they 2663 * should match. This failure is an early indication that 2664 * hardware receive checksumming won't work. 2665 */ 2666 if (likely((u16)(status >> 16) == (u16)status)) { 2667 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; 2668 skb->ip_summed = CHECKSUM_COMPLETE; 2669 skb->csum = le16_to_cpu(status); 2670 } else { 2671 dev_notice(&sky2->hw->pdev->dev, 2672 "%s: receive checksum problem (status = %#x)\n", 2673 sky2->netdev->name, status); 2674 2675 /* Disable checksum offload 2676 * It will be reenabled on next ndo_set_features, but if it's 2677 * really broken, will get disabled again 2678 */ 2679 sky2->netdev->features &= ~NETIF_F_RXCSUM; 2680 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 2681 BMU_DIS_RX_CHKSUM); 2682 } 2683 } 2684 2685 static void sky2_rx_tag(struct sky2_port *sky2, u16 length) 2686 { 2687 struct sk_buff *skb; 2688 2689 skb = sky2->rx_ring[sky2->rx_next].skb; 2690 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length)); 2691 } 2692 2693 static void sky2_rx_hash(struct sky2_port *sky2, u32 status) 2694 { 2695 struct sk_buff *skb; 2696 2697 skb = sky2->rx_ring[sky2->rx_next].skb; 2698 skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3); 2699 } 2700 2701 /* Process status response ring */ 2702 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) 2703 { 2704 int work_done = 0; 2705 unsigned int total_bytes[2] = { 0 }; 2706 unsigned int total_packets[2] = { 0 }; 2707 2708 if (to_do <= 0) 2709 return work_done; 2710 2711 rmb(); 2712 do { 2713 struct sky2_port *sky2; 2714 struct sky2_status_le *le = hw->st_le + hw->st_idx; 2715 unsigned port; 2716 struct net_device *dev; 2717 struct sk_buff *skb; 2718 u32 status; 2719 u16 length; 2720 u8 opcode = le->opcode; 2721 2722 if (!(opcode & HW_OWNER)) 2723 break; 2724 2725 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); 2726 2727 port = le->css & CSS_LINK_BIT; 2728 dev = hw->dev[port]; 2729 sky2 = netdev_priv(dev); 2730 length = le16_to_cpu(le->length); 2731 status = le32_to_cpu(le->status); 2732 2733 le->opcode = 0; 2734 switch (opcode & ~HW_OWNER) { 2735 case OP_RXSTAT: 2736 total_packets[port]++; 2737 total_bytes[port] += length; 2738 2739 skb = sky2_receive(dev, length, status); 2740 if (!skb) 2741 break; 2742 2743 /* This chip reports checksum status differently */ 2744 if (hw->flags & SKY2_HW_NEW_LE) { 2745 if ((dev->features & NETIF_F_RXCSUM) && 2746 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && 2747 (le->css & CSS_TCPUDPCSOK)) 2748 skb->ip_summed = CHECKSUM_UNNECESSARY; 2749 else 2750 skb->ip_summed = CHECKSUM_NONE; 2751 } 2752 2753 skb->protocol = eth_type_trans(skb, dev); 2754 sky2_skb_rx(sky2, skb); 2755 2756 /* Stop after net poll weight */ 2757 if (++work_done >= to_do) 2758 goto exit_loop; 2759 break; 2760 2761 case OP_RXVLAN: 2762 sky2_rx_tag(sky2, length); 2763 break; 2764 2765 case OP_RXCHKSVLAN: 2766 sky2_rx_tag(sky2, length); 2767 fallthrough; 2768 case OP_RXCHKS: 2769 if (likely(dev->features & NETIF_F_RXCSUM)) 2770 sky2_rx_checksum(sky2, status); 2771 break; 2772 2773 case OP_RSS_HASH: 2774 sky2_rx_hash(sky2, status); 2775 break; 2776 2777 case OP_TXINDEXLE: 2778 /* TX index reports status for both ports */ 2779 sky2_tx_done(hw->dev[0], status & 0xfff); 2780 if (hw->dev[1]) 2781 sky2_tx_done(hw->dev[1], 2782 ((status >> 24) & 0xff) 2783 | (u16)(length & 0xf) << 8); 2784 break; 2785 2786 default: 2787 if (net_ratelimit()) 2788 pr_warn("unknown status opcode 0x%x\n", opcode); 2789 } 2790 } while (hw->st_idx != idx); 2791 2792 /* Fully processed status ring so clear irq */ 2793 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2794 2795 exit_loop: 2796 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); 2797 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); 2798 2799 return work_done; 2800 } 2801 2802 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) 2803 { 2804 struct net_device *dev = hw->dev[port]; 2805 2806 if (net_ratelimit()) 2807 netdev_info(dev, "hw error interrupt status 0x%x\n", status); 2808 2809 if (status & Y2_IS_PAR_RD1) { 2810 if (net_ratelimit()) 2811 netdev_err(dev, "ram data read parity error\n"); 2812 /* Clear IRQ */ 2813 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 2814 } 2815 2816 if (status & Y2_IS_PAR_WR1) { 2817 if (net_ratelimit()) 2818 netdev_err(dev, "ram data write parity error\n"); 2819 2820 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 2821 } 2822 2823 if (status & Y2_IS_PAR_MAC1) { 2824 if (net_ratelimit()) 2825 netdev_err(dev, "MAC parity error\n"); 2826 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 2827 } 2828 2829 if (status & Y2_IS_PAR_RX1) { 2830 if (net_ratelimit()) 2831 netdev_err(dev, "RX parity error\n"); 2832 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 2833 } 2834 2835 if (status & Y2_IS_TCP_TXA1) { 2836 if (net_ratelimit()) 2837 netdev_err(dev, "TCP segmentation error\n"); 2838 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 2839 } 2840 } 2841 2842 static void sky2_hw_intr(struct sky2_hw *hw) 2843 { 2844 struct pci_dev *pdev = hw->pdev; 2845 u32 status = sky2_read32(hw, B0_HWE_ISRC); 2846 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2847 2848 status &= hwmsk; 2849 2850 if (status & Y2_IS_TIST_OV) 2851 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2852 2853 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2854 u16 pci_err; 2855 2856 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2857 pci_err = sky2_pci_read16(hw, PCI_STATUS); 2858 if (net_ratelimit()) 2859 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", 2860 pci_err); 2861 2862 sky2_pci_write16(hw, PCI_STATUS, 2863 pci_err | PCI_STATUS_ERROR_BITS); 2864 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2865 } 2866 2867 if (status & Y2_IS_PCI_EXP) { 2868 /* PCI-Express uncorrectable Error occurred */ 2869 u32 err; 2870 2871 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2872 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2873 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 2874 0xfffffffful); 2875 if (net_ratelimit()) 2876 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); 2877 2878 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2879 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2880 } 2881 2882 if (status & Y2_HWE_L1_MASK) 2883 sky2_hw_error(hw, 0, status); 2884 status >>= 8; 2885 if (status & Y2_HWE_L1_MASK) 2886 sky2_hw_error(hw, 1, status); 2887 } 2888 2889 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) 2890 { 2891 struct net_device *dev = hw->dev[port]; 2892 struct sky2_port *sky2 = netdev_priv(dev); 2893 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2894 2895 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); 2896 2897 if (status & GM_IS_RX_CO_OV) 2898 gma_read16(hw, port, GM_RX_IRQ_SRC); 2899 2900 if (status & GM_IS_TX_CO_OV) 2901 gma_read16(hw, port, GM_TX_IRQ_SRC); 2902 2903 if (status & GM_IS_RX_FF_OR) { 2904 ++dev->stats.rx_fifo_errors; 2905 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2906 } 2907 2908 if (status & GM_IS_TX_FF_UR) { 2909 ++dev->stats.tx_fifo_errors; 2910 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2911 } 2912 } 2913 2914 /* This should never happen it is a bug. */ 2915 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) 2916 { 2917 struct net_device *dev = hw->dev[port]; 2918 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); 2919 2920 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", 2921 dev->name, (unsigned) q, (unsigned) idx, 2922 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); 2923 2924 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); 2925 } 2926 2927 static int sky2_rx_hung(struct net_device *dev) 2928 { 2929 struct sky2_port *sky2 = netdev_priv(dev); 2930 struct sky2_hw *hw = sky2->hw; 2931 unsigned port = sky2->port; 2932 unsigned rxq = rxqaddr[port]; 2933 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); 2934 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); 2935 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); 2936 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); 2937 2938 /* If idle and MAC or PCI is stuck */ 2939 if (sky2->check.last == sky2->last_rx && 2940 ((mac_rp == sky2->check.mac_rp && 2941 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || 2942 /* Check if the PCI RX hang */ 2943 (fifo_rp == sky2->check.fifo_rp && 2944 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { 2945 netdev_printk(KERN_DEBUG, dev, 2946 "hung mac %d:%d fifo %d (%d:%d)\n", 2947 mac_lev, mac_rp, fifo_lev, 2948 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); 2949 return 1; 2950 } else { 2951 sky2->check.last = sky2->last_rx; 2952 sky2->check.mac_rp = mac_rp; 2953 sky2->check.mac_lev = mac_lev; 2954 sky2->check.fifo_rp = fifo_rp; 2955 sky2->check.fifo_lev = fifo_lev; 2956 return 0; 2957 } 2958 } 2959 2960 static void sky2_watchdog(struct timer_list *t) 2961 { 2962 struct sky2_hw *hw = timer_container_of(hw, t, watchdog_timer); 2963 2964 /* Check for lost IRQ once a second */ 2965 if (sky2_read32(hw, B0_ISRC)) { 2966 napi_schedule(&hw->napi); 2967 } else { 2968 int i, active = 0; 2969 2970 for (i = 0; i < hw->ports; i++) { 2971 struct net_device *dev = hw->dev[i]; 2972 if (!netif_running(dev)) 2973 continue; 2974 ++active; 2975 2976 /* For chips with Rx FIFO, check if stuck */ 2977 if ((hw->flags & SKY2_HW_RAM_BUFFER) && 2978 sky2_rx_hung(dev)) { 2979 netdev_info(dev, "receiver hang detected\n"); 2980 schedule_work(&hw->restart_work); 2981 return; 2982 } 2983 } 2984 2985 if (active == 0) 2986 return; 2987 } 2988 2989 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); 2990 } 2991 2992 /* Hardware/software error handling */ 2993 static void sky2_err_intr(struct sky2_hw *hw, u32 status) 2994 { 2995 if (net_ratelimit()) 2996 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); 2997 2998 if (status & Y2_IS_HW_ERR) 2999 sky2_hw_intr(hw); 3000 3001 if (status & Y2_IS_IRQ_MAC1) 3002 sky2_mac_intr(hw, 0); 3003 3004 if (status & Y2_IS_IRQ_MAC2) 3005 sky2_mac_intr(hw, 1); 3006 3007 if (status & Y2_IS_CHK_RX1) 3008 sky2_le_error(hw, 0, Q_R1); 3009 3010 if (status & Y2_IS_CHK_RX2) 3011 sky2_le_error(hw, 1, Q_R2); 3012 3013 if (status & Y2_IS_CHK_TXA1) 3014 sky2_le_error(hw, 0, Q_XA1); 3015 3016 if (status & Y2_IS_CHK_TXA2) 3017 sky2_le_error(hw, 1, Q_XA2); 3018 } 3019 3020 static int sky2_poll(struct napi_struct *napi, int work_limit) 3021 { 3022 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); 3023 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 3024 int work_done = 0; 3025 u16 idx; 3026 3027 if (unlikely(status & Y2_IS_ERROR)) 3028 sky2_err_intr(hw, status); 3029 3030 if (status & Y2_IS_IRQ_PHY1) 3031 sky2_phy_intr(hw, 0); 3032 3033 if (status & Y2_IS_IRQ_PHY2) 3034 sky2_phy_intr(hw, 1); 3035 3036 if (status & Y2_IS_PHY_QLNK) 3037 sky2_qlink_intr(hw); 3038 3039 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { 3040 work_done += sky2_status_intr(hw, work_limit - work_done, idx); 3041 3042 if (work_done >= work_limit) 3043 goto done; 3044 } 3045 3046 napi_complete_done(napi, work_done); 3047 sky2_read32(hw, B0_Y2_SP_LISR); 3048 done: 3049 3050 return work_done; 3051 } 3052 3053 static irqreturn_t sky2_intr(int irq, void *dev_id) 3054 { 3055 struct sky2_hw *hw = dev_id; 3056 u32 status; 3057 3058 /* Reading this mask interrupts as side effect */ 3059 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 3060 if (status == 0 || status == ~0) { 3061 sky2_write32(hw, B0_Y2_SP_ICR, 2); 3062 return IRQ_NONE; 3063 } 3064 3065 prefetch(&hw->st_le[hw->st_idx]); 3066 3067 napi_schedule(&hw->napi); 3068 3069 return IRQ_HANDLED; 3070 } 3071 3072 #ifdef CONFIG_NET_POLL_CONTROLLER 3073 static void sky2_netpoll(struct net_device *dev) 3074 { 3075 struct sky2_port *sky2 = netdev_priv(dev); 3076 3077 napi_schedule(&sky2->hw->napi); 3078 } 3079 #endif 3080 3081 /* Chip internal frequency for clock calculations */ 3082 static u32 sky2_mhz(const struct sky2_hw *hw) 3083 { 3084 switch (hw->chip_id) { 3085 case CHIP_ID_YUKON_EC: 3086 case CHIP_ID_YUKON_EC_U: 3087 case CHIP_ID_YUKON_EX: 3088 case CHIP_ID_YUKON_SUPR: 3089 case CHIP_ID_YUKON_UL_2: 3090 case CHIP_ID_YUKON_OPT: 3091 case CHIP_ID_YUKON_PRM: 3092 case CHIP_ID_YUKON_OP_2: 3093 return 125; 3094 3095 case CHIP_ID_YUKON_FE: 3096 return 100; 3097 3098 case CHIP_ID_YUKON_FE_P: 3099 return 50; 3100 3101 case CHIP_ID_YUKON_XL: 3102 return 156; 3103 3104 default: 3105 BUG(); 3106 } 3107 } 3108 3109 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) 3110 { 3111 return sky2_mhz(hw) * us; 3112 } 3113 3114 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) 3115 { 3116 return clk / sky2_mhz(hw); 3117 } 3118 3119 3120 static int sky2_init(struct sky2_hw *hw) 3121 { 3122 u8 t8; 3123 3124 /* Enable all clocks and check for bad PCI access */ 3125 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 3126 3127 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3128 3129 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 3130 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 3131 3132 switch (hw->chip_id) { 3133 case CHIP_ID_YUKON_XL: 3134 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; 3135 if (hw->chip_rev < CHIP_REV_YU_XL_A2) 3136 hw->flags |= SKY2_HW_RSS_BROKEN; 3137 break; 3138 3139 case CHIP_ID_YUKON_EC_U: 3140 hw->flags = SKY2_HW_GIGABIT 3141 | SKY2_HW_NEWER_PHY 3142 | SKY2_HW_ADV_POWER_CTL; 3143 break; 3144 3145 case CHIP_ID_YUKON_EX: 3146 hw->flags = SKY2_HW_GIGABIT 3147 | SKY2_HW_NEWER_PHY 3148 | SKY2_HW_NEW_LE 3149 | SKY2_HW_ADV_POWER_CTL 3150 | SKY2_HW_RSS_CHKSUM; 3151 3152 /* New transmit checksum */ 3153 if (hw->chip_rev != CHIP_REV_YU_EX_B0) 3154 hw->flags |= SKY2_HW_AUTO_TX_SUM; 3155 break; 3156 3157 case CHIP_ID_YUKON_EC: 3158 /* This rev is really old, and requires untested workarounds */ 3159 if (hw->chip_rev == CHIP_REV_YU_EC_A1) { 3160 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); 3161 return -EOPNOTSUPP; 3162 } 3163 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; 3164 break; 3165 3166 case CHIP_ID_YUKON_FE: 3167 hw->flags = SKY2_HW_RSS_BROKEN; 3168 break; 3169 3170 case CHIP_ID_YUKON_FE_P: 3171 hw->flags = SKY2_HW_NEWER_PHY 3172 | SKY2_HW_NEW_LE 3173 | SKY2_HW_AUTO_TX_SUM 3174 | SKY2_HW_ADV_POWER_CTL; 3175 3176 /* The workaround for status conflicts VLAN tag detection. */ 3177 if (hw->chip_rev == CHIP_REV_YU_FE2_A0) 3178 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; 3179 break; 3180 3181 case CHIP_ID_YUKON_SUPR: 3182 hw->flags = SKY2_HW_GIGABIT 3183 | SKY2_HW_NEWER_PHY 3184 | SKY2_HW_NEW_LE 3185 | SKY2_HW_AUTO_TX_SUM 3186 | SKY2_HW_ADV_POWER_CTL; 3187 3188 if (hw->chip_rev == CHIP_REV_YU_SU_A0) 3189 hw->flags |= SKY2_HW_RSS_CHKSUM; 3190 break; 3191 3192 case CHIP_ID_YUKON_UL_2: 3193 hw->flags = SKY2_HW_GIGABIT 3194 | SKY2_HW_ADV_POWER_CTL; 3195 break; 3196 3197 case CHIP_ID_YUKON_OPT: 3198 case CHIP_ID_YUKON_PRM: 3199 case CHIP_ID_YUKON_OP_2: 3200 hw->flags = SKY2_HW_GIGABIT 3201 | SKY2_HW_NEW_LE 3202 | SKY2_HW_ADV_POWER_CTL; 3203 break; 3204 3205 default: 3206 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3207 hw->chip_id); 3208 return -EOPNOTSUPP; 3209 } 3210 3211 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 3212 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') 3213 hw->flags |= SKY2_HW_FIBRE_PHY; 3214 3215 hw->ports = 1; 3216 t8 = sky2_read8(hw, B2_Y2_HW_RES); 3217 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 3218 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 3219 ++hw->ports; 3220 } 3221 3222 if (sky2_read8(hw, B2_E_0)) 3223 hw->flags |= SKY2_HW_RAM_BUFFER; 3224 3225 return 0; 3226 } 3227 3228 static void sky2_reset(struct sky2_hw *hw) 3229 { 3230 struct pci_dev *pdev = hw->pdev; 3231 u16 status; 3232 int i; 3233 u32 hwe_mask = Y2_HWE_ALL_MASK; 3234 3235 /* disable ASF */ 3236 if (hw->chip_id == CHIP_ID_YUKON_EX 3237 || hw->chip_id == CHIP_ID_YUKON_SUPR) { 3238 sky2_write32(hw, CPU_WDOG, 0); 3239 status = sky2_read16(hw, HCU_CCSR); 3240 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | 3241 HCU_CCSR_UC_STATE_MSK); 3242 /* 3243 * CPU clock divider shouldn't be used because 3244 * - ASF firmware may malfunction 3245 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks 3246 */ 3247 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; 3248 sky2_write16(hw, HCU_CCSR, status); 3249 sky2_write32(hw, CPU_WDOG, 0); 3250 } else 3251 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 3252 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 3253 3254 /* do a SW reset */ 3255 sky2_write8(hw, B0_CTST, CS_RST_SET); 3256 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3257 3258 /* allow writes to PCI config */ 3259 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3260 3261 /* clear PCI errors, if any */ 3262 status = sky2_pci_read16(hw, PCI_STATUS); 3263 status |= PCI_STATUS_ERROR_BITS; 3264 sky2_pci_write16(hw, PCI_STATUS, status); 3265 3266 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 3267 3268 if (pci_is_pcie(pdev)) { 3269 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 3270 0xfffffffful); 3271 3272 /* If error bit is stuck on ignore it */ 3273 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) 3274 dev_info(&pdev->dev, "ignoring stuck error report bit\n"); 3275 else 3276 hwe_mask |= Y2_IS_PCI_EXP; 3277 } 3278 3279 sky2_power_on(hw); 3280 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3281 3282 for (i = 0; i < hw->ports; i++) { 3283 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3284 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3285 3286 if (hw->chip_id == CHIP_ID_YUKON_EX || 3287 hw->chip_id == CHIP_ID_YUKON_SUPR) 3288 sky2_write16(hw, SK_REG(i, GMAC_CTRL), 3289 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON 3290 | GMC_BYP_RETR_ON); 3291 3292 } 3293 3294 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { 3295 /* enable MACSec clock gating */ 3296 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); 3297 } 3298 3299 if (hw->chip_id == CHIP_ID_YUKON_OPT || 3300 hw->chip_id == CHIP_ID_YUKON_PRM || 3301 hw->chip_id == CHIP_ID_YUKON_OP_2) { 3302 u16 reg; 3303 3304 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 3305 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ 3306 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); 3307 3308 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ 3309 reg = 10; 3310 3311 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3312 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3313 } else { 3314 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ 3315 reg = 3; 3316 } 3317 3318 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; 3319 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; 3320 3321 /* reset PHY Link Detect */ 3322 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3323 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); 3324 3325 /* check if PSMv2 was running before */ 3326 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); 3327 if (reg & PCI_EXP_LNKCTL_ASPMC) 3328 /* restore the PCIe Link Control register */ 3329 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, 3330 reg); 3331 3332 if (hw->chip_id == CHIP_ID_YUKON_PRM && 3333 hw->chip_rev == CHIP_REV_YU_PRM_A0) { 3334 /* change PHY Interrupt polarity to low active */ 3335 reg = sky2_read16(hw, GPHY_CTRL); 3336 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL); 3337 3338 /* adapt HW for low active PHY Interrupt */ 3339 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL); 3340 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1); 3341 } 3342 3343 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3344 3345 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3346 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3347 } 3348 3349 /* Clear I2C IRQ noise */ 3350 sky2_write32(hw, B2_I2C_IRQ, 1); 3351 3352 /* turn off hardware timer (unused) */ 3353 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 3354 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3355 3356 /* Turn off descriptor polling */ 3357 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 3358 3359 /* Turn off receive timestamp */ 3360 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 3361 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3362 3363 /* enable the Tx Arbiters */ 3364 for (i = 0; i < hw->ports; i++) 3365 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3366 3367 /* Initialize ram interface */ 3368 for (i = 0; i < hw->ports; i++) { 3369 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 3370 3371 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 3372 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 3373 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 3374 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 3375 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 3376 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 3377 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 3378 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 3379 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 3380 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 3381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 3382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 3383 } 3384 3385 sky2_write32(hw, B0_HWE_IMSK, hwe_mask); 3386 3387 for (i = 0; i < hw->ports; i++) 3388 sky2_gmac_reset(hw, i); 3389 3390 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); 3391 hw->st_idx = 0; 3392 3393 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 3394 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 3395 3396 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 3397 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 3398 3399 /* Set the list last index */ 3400 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); 3401 3402 sky2_write16(hw, STAT_TX_IDX_TH, 10); 3403 sky2_write8(hw, STAT_FIFO_WM, 16); 3404 3405 /* set Status-FIFO ISR watermark */ 3406 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 3407 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 3408 else 3409 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 3410 3411 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 3412 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); 3413 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 3414 3415 /* enable status unit */ 3416 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 3417 3418 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 3419 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 3420 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 3421 } 3422 3423 /* Take device down (offline). 3424 * Equivalent to doing dev_stop() but this does not 3425 * inform upper layers of the transition. 3426 */ 3427 static void sky2_detach(struct net_device *dev) 3428 { 3429 if (netif_running(dev)) { 3430 netif_tx_lock(dev); 3431 netif_device_detach(dev); /* stop txq */ 3432 netif_tx_unlock(dev); 3433 sky2_close(dev); 3434 } 3435 } 3436 3437 /* Bring device back after doing sky2_detach */ 3438 static int sky2_reattach(struct net_device *dev) 3439 { 3440 int err = 0; 3441 3442 if (netif_running(dev)) { 3443 err = sky2_open(dev); 3444 if (err) { 3445 netdev_info(dev, "could not restart %d\n", err); 3446 dev_close(dev); 3447 } else { 3448 netif_device_attach(dev); 3449 sky2_set_multicast(dev); 3450 } 3451 } 3452 3453 return err; 3454 } 3455 3456 static void sky2_all_down(struct sky2_hw *hw) 3457 { 3458 int i; 3459 3460 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3461 sky2_write32(hw, B0_IMSK, 0); 3462 sky2_read32(hw, B0_IMSK); 3463 3464 synchronize_irq(hw->pdev->irq); 3465 napi_disable(&hw->napi); 3466 } 3467 3468 for (i = 0; i < hw->ports; i++) { 3469 struct net_device *dev = hw->dev[i]; 3470 struct sky2_port *sky2 = netdev_priv(dev); 3471 3472 if (!netif_running(dev)) 3473 continue; 3474 3475 netif_carrier_off(dev); 3476 netif_tx_disable(dev); 3477 sky2_hw_down(sky2); 3478 } 3479 } 3480 3481 static void sky2_all_up(struct sky2_hw *hw) 3482 { 3483 u32 imask = Y2_IS_BASE; 3484 int i; 3485 3486 for (i = 0; i < hw->ports; i++) { 3487 struct net_device *dev = hw->dev[i]; 3488 struct sky2_port *sky2 = netdev_priv(dev); 3489 3490 if (!netif_running(dev)) 3491 continue; 3492 3493 sky2_hw_up(sky2); 3494 sky2_set_multicast(dev); 3495 imask |= portirq_msk[i]; 3496 netif_wake_queue(dev); 3497 } 3498 3499 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3500 sky2_write32(hw, B0_IMSK, imask); 3501 sky2_read32(hw, B0_IMSK); 3502 sky2_read32(hw, B0_Y2_SP_LISR); 3503 napi_enable(&hw->napi); 3504 } 3505 } 3506 3507 static void sky2_restart(struct work_struct *work) 3508 { 3509 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); 3510 3511 rtnl_lock(); 3512 3513 sky2_all_down(hw); 3514 sky2_reset(hw); 3515 sky2_all_up(hw); 3516 3517 rtnl_unlock(); 3518 } 3519 3520 static inline u8 sky2_wol_supported(const struct sky2_hw *hw) 3521 { 3522 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; 3523 } 3524 3525 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3526 { 3527 const struct sky2_port *sky2 = netdev_priv(dev); 3528 3529 wol->supported = sky2_wol_supported(sky2->hw); 3530 wol->wolopts = sky2->wol; 3531 } 3532 3533 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3534 { 3535 struct sky2_port *sky2 = netdev_priv(dev); 3536 struct sky2_hw *hw = sky2->hw; 3537 bool enable_wakeup = false; 3538 int i; 3539 3540 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || 3541 !device_can_wakeup(&hw->pdev->dev)) 3542 return -EOPNOTSUPP; 3543 3544 sky2->wol = wol->wolopts; 3545 3546 for (i = 0; i < hw->ports; i++) { 3547 struct net_device *dev = hw->dev[i]; 3548 struct sky2_port *sky2 = netdev_priv(dev); 3549 3550 if (sky2->wol) 3551 enable_wakeup = true; 3552 } 3553 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); 3554 3555 return 0; 3556 } 3557 3558 static u32 sky2_supported_modes(const struct sky2_hw *hw) 3559 { 3560 if (sky2_is_copper(hw)) { 3561 u32 modes = SUPPORTED_10baseT_Half 3562 | SUPPORTED_10baseT_Full 3563 | SUPPORTED_100baseT_Half 3564 | SUPPORTED_100baseT_Full; 3565 3566 if (hw->flags & SKY2_HW_GIGABIT) 3567 modes |= SUPPORTED_1000baseT_Half 3568 | SUPPORTED_1000baseT_Full; 3569 return modes; 3570 } else 3571 return SUPPORTED_1000baseT_Half 3572 | SUPPORTED_1000baseT_Full; 3573 } 3574 3575 static int sky2_get_link_ksettings(struct net_device *dev, 3576 struct ethtool_link_ksettings *cmd) 3577 { 3578 struct sky2_port *sky2 = netdev_priv(dev); 3579 struct sky2_hw *hw = sky2->hw; 3580 u32 supported, advertising; 3581 3582 supported = sky2_supported_modes(hw); 3583 cmd->base.phy_address = PHY_ADDR_MARV; 3584 if (sky2_is_copper(hw)) { 3585 cmd->base.port = PORT_TP; 3586 cmd->base.speed = sky2->speed; 3587 supported |= SUPPORTED_Autoneg | SUPPORTED_TP; 3588 } else { 3589 cmd->base.speed = SPEED_1000; 3590 cmd->base.port = PORT_FIBRE; 3591 supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; 3592 } 3593 3594 advertising = sky2->advertising; 3595 cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) 3596 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3597 cmd->base.duplex = sky2->duplex; 3598 3599 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3600 supported); 3601 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3602 advertising); 3603 3604 return 0; 3605 } 3606 3607 static int sky2_set_link_ksettings(struct net_device *dev, 3608 const struct ethtool_link_ksettings *cmd) 3609 { 3610 struct sky2_port *sky2 = netdev_priv(dev); 3611 const struct sky2_hw *hw = sky2->hw; 3612 u32 supported = sky2_supported_modes(hw); 3613 u32 new_advertising; 3614 3615 ethtool_convert_link_mode_to_legacy_u32(&new_advertising, 3616 cmd->link_modes.advertising); 3617 3618 if (cmd->base.autoneg == AUTONEG_ENABLE) { 3619 if (new_advertising & ~supported) 3620 return -EINVAL; 3621 3622 if (sky2_is_copper(hw)) 3623 sky2->advertising = new_advertising | 3624 ADVERTISED_TP | 3625 ADVERTISED_Autoneg; 3626 else 3627 sky2->advertising = new_advertising | 3628 ADVERTISED_FIBRE | 3629 ADVERTISED_Autoneg; 3630 3631 sky2->flags |= SKY2_FLAG_AUTO_SPEED; 3632 sky2->duplex = -1; 3633 sky2->speed = -1; 3634 } else { 3635 u32 setting; 3636 u32 speed = cmd->base.speed; 3637 3638 switch (speed) { 3639 case SPEED_1000: 3640 if (cmd->base.duplex == DUPLEX_FULL) 3641 setting = SUPPORTED_1000baseT_Full; 3642 else if (cmd->base.duplex == DUPLEX_HALF) 3643 setting = SUPPORTED_1000baseT_Half; 3644 else 3645 return -EINVAL; 3646 break; 3647 case SPEED_100: 3648 if (cmd->base.duplex == DUPLEX_FULL) 3649 setting = SUPPORTED_100baseT_Full; 3650 else if (cmd->base.duplex == DUPLEX_HALF) 3651 setting = SUPPORTED_100baseT_Half; 3652 else 3653 return -EINVAL; 3654 break; 3655 3656 case SPEED_10: 3657 if (cmd->base.duplex == DUPLEX_FULL) 3658 setting = SUPPORTED_10baseT_Full; 3659 else if (cmd->base.duplex == DUPLEX_HALF) 3660 setting = SUPPORTED_10baseT_Half; 3661 else 3662 return -EINVAL; 3663 break; 3664 default: 3665 return -EINVAL; 3666 } 3667 3668 if ((setting & supported) == 0) 3669 return -EINVAL; 3670 3671 sky2->speed = speed; 3672 sky2->duplex = cmd->base.duplex; 3673 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; 3674 } 3675 3676 if (netif_running(dev)) { 3677 sky2_phy_reinit(sky2); 3678 sky2_set_multicast(dev); 3679 } 3680 3681 return 0; 3682 } 3683 3684 static void sky2_get_drvinfo(struct net_device *dev, 3685 struct ethtool_drvinfo *info) 3686 { 3687 struct sky2_port *sky2 = netdev_priv(dev); 3688 3689 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 3690 strscpy(info->version, DRV_VERSION, sizeof(info->version)); 3691 strscpy(info->bus_info, pci_name(sky2->hw->pdev), 3692 sizeof(info->bus_info)); 3693 } 3694 3695 static const struct sky2_stat { 3696 char name[ETH_GSTRING_LEN]; 3697 u16 offset; 3698 } sky2_stats[] = { 3699 { "tx_bytes", GM_TXO_OK_HI }, 3700 { "rx_bytes", GM_RXO_OK_HI }, 3701 { "tx_broadcast", GM_TXF_BC_OK }, 3702 { "rx_broadcast", GM_RXF_BC_OK }, 3703 { "tx_multicast", GM_TXF_MC_OK }, 3704 { "rx_multicast", GM_RXF_MC_OK }, 3705 { "tx_unicast", GM_TXF_UC_OK }, 3706 { "rx_unicast", GM_RXF_UC_OK }, 3707 { "tx_mac_pause", GM_TXF_MPAUSE }, 3708 { "rx_mac_pause", GM_RXF_MPAUSE }, 3709 { "collisions", GM_TXF_COL }, 3710 { "late_collision",GM_TXF_LAT_COL }, 3711 { "aborted", GM_TXF_ABO_COL }, 3712 { "single_collisions", GM_TXF_SNG_COL }, 3713 { "multi_collisions", GM_TXF_MUL_COL }, 3714 3715 { "rx_short", GM_RXF_SHT }, 3716 { "rx_runt", GM_RXE_FRAG }, 3717 { "rx_64_byte_packets", GM_RXF_64B }, 3718 { "rx_65_to_127_byte_packets", GM_RXF_127B }, 3719 { "rx_128_to_255_byte_packets", GM_RXF_255B }, 3720 { "rx_256_to_511_byte_packets", GM_RXF_511B }, 3721 { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, 3722 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, 3723 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, 3724 { "rx_too_long", GM_RXF_LNG_ERR }, 3725 { "rx_fifo_overflow", GM_RXE_FIFO_OV }, 3726 { "rx_jabber", GM_RXF_JAB_PKT }, 3727 { "rx_fcs_error", GM_RXF_FCS_ERR }, 3728 3729 { "tx_64_byte_packets", GM_TXF_64B }, 3730 { "tx_65_to_127_byte_packets", GM_TXF_127B }, 3731 { "tx_128_to_255_byte_packets", GM_TXF_255B }, 3732 { "tx_256_to_511_byte_packets", GM_TXF_511B }, 3733 { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, 3734 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, 3735 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, 3736 { "tx_fifo_underrun", GM_TXE_FIFO_UR }, 3737 }; 3738 3739 static u32 sky2_get_msglevel(struct net_device *netdev) 3740 { 3741 struct sky2_port *sky2 = netdev_priv(netdev); 3742 return sky2->msg_enable; 3743 } 3744 3745 static int sky2_nway_reset(struct net_device *dev) 3746 { 3747 struct sky2_port *sky2 = netdev_priv(dev); 3748 3749 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) 3750 return -EINVAL; 3751 3752 sky2_phy_reinit(sky2); 3753 sky2_set_multicast(dev); 3754 3755 return 0; 3756 } 3757 3758 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) 3759 { 3760 struct sky2_hw *hw = sky2->hw; 3761 unsigned port = sky2->port; 3762 int i; 3763 3764 data[0] = get_stats64(hw, port, GM_TXO_OK_LO); 3765 data[1] = get_stats64(hw, port, GM_RXO_OK_LO); 3766 3767 for (i = 2; i < count; i++) 3768 data[i] = get_stats32(hw, port, sky2_stats[i].offset); 3769 } 3770 3771 static void sky2_set_msglevel(struct net_device *netdev, u32 value) 3772 { 3773 struct sky2_port *sky2 = netdev_priv(netdev); 3774 sky2->msg_enable = value; 3775 } 3776 3777 static int sky2_get_sset_count(struct net_device *dev, int sset) 3778 { 3779 switch (sset) { 3780 case ETH_SS_STATS: 3781 return ARRAY_SIZE(sky2_stats); 3782 default: 3783 return -EOPNOTSUPP; 3784 } 3785 } 3786 3787 static void sky2_get_ethtool_stats(struct net_device *dev, 3788 struct ethtool_stats *stats, u64 * data) 3789 { 3790 struct sky2_port *sky2 = netdev_priv(dev); 3791 3792 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); 3793 } 3794 3795 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) 3796 { 3797 int i; 3798 3799 switch (stringset) { 3800 case ETH_SS_STATS: 3801 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) 3802 ethtool_puts(&data, sky2_stats[i].name); 3803 break; 3804 } 3805 } 3806 3807 static int sky2_set_mac_address(struct net_device *dev, void *p) 3808 { 3809 struct sky2_port *sky2 = netdev_priv(dev); 3810 struct sky2_hw *hw = sky2->hw; 3811 unsigned port = sky2->port; 3812 const struct sockaddr *addr = p; 3813 3814 if (!is_valid_ether_addr(addr->sa_data)) 3815 return -EADDRNOTAVAIL; 3816 3817 eth_hw_addr_set(dev, addr->sa_data); 3818 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, 3819 dev->dev_addr, ETH_ALEN); 3820 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, 3821 dev->dev_addr, ETH_ALEN); 3822 3823 /* virtual address for data */ 3824 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3825 3826 /* physical address: used for pause frames */ 3827 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3828 3829 return 0; 3830 } 3831 3832 static inline void sky2_add_filter(u8 filter[8], const u8 *addr) 3833 { 3834 u32 bit; 3835 3836 bit = ether_crc(ETH_ALEN, addr) & 63; 3837 filter[bit >> 3] |= 1 << (bit & 7); 3838 } 3839 3840 static void sky2_set_multicast(struct net_device *dev) 3841 { 3842 struct sky2_port *sky2 = netdev_priv(dev); 3843 struct sky2_hw *hw = sky2->hw; 3844 unsigned port = sky2->port; 3845 struct netdev_hw_addr *ha; 3846 u16 reg; 3847 u8 filter[8]; 3848 int rx_pause; 3849 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 3850 3851 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); 3852 memset(filter, 0, sizeof(filter)); 3853 3854 reg = gma_read16(hw, port, GM_RX_CTRL); 3855 reg |= GM_RXCR_UCF_ENA; 3856 3857 if (dev->flags & IFF_PROMISC) /* promiscuous */ 3858 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 3859 else if (dev->flags & IFF_ALLMULTI) 3860 memset(filter, 0xff, sizeof(filter)); 3861 else if (netdev_mc_empty(dev) && !rx_pause) 3862 reg &= ~GM_RXCR_MCF_ENA; 3863 else { 3864 reg |= GM_RXCR_MCF_ENA; 3865 3866 if (rx_pause) 3867 sky2_add_filter(filter, pause_mc_addr); 3868 3869 netdev_for_each_mc_addr(ha, dev) 3870 sky2_add_filter(filter, ha->addr); 3871 } 3872 3873 gma_write16(hw, port, GM_MC_ADDR_H1, 3874 (u16) filter[0] | ((u16) filter[1] << 8)); 3875 gma_write16(hw, port, GM_MC_ADDR_H2, 3876 (u16) filter[2] | ((u16) filter[3] << 8)); 3877 gma_write16(hw, port, GM_MC_ADDR_H3, 3878 (u16) filter[4] | ((u16) filter[5] << 8)); 3879 gma_write16(hw, port, GM_MC_ADDR_H4, 3880 (u16) filter[6] | ((u16) filter[7] << 8)); 3881 3882 gma_write16(hw, port, GM_RX_CTRL, reg); 3883 } 3884 3885 static void sky2_get_stats(struct net_device *dev, 3886 struct rtnl_link_stats64 *stats) 3887 { 3888 struct sky2_port *sky2 = netdev_priv(dev); 3889 struct sky2_hw *hw = sky2->hw; 3890 unsigned port = sky2->port; 3891 unsigned int start; 3892 u64 _bytes, _packets; 3893 3894 do { 3895 start = u64_stats_fetch_begin(&sky2->rx_stats.syncp); 3896 _bytes = sky2->rx_stats.bytes; 3897 _packets = sky2->rx_stats.packets; 3898 } while (u64_stats_fetch_retry(&sky2->rx_stats.syncp, start)); 3899 3900 stats->rx_packets = _packets; 3901 stats->rx_bytes = _bytes; 3902 3903 do { 3904 start = u64_stats_fetch_begin(&sky2->tx_stats.syncp); 3905 _bytes = sky2->tx_stats.bytes; 3906 _packets = sky2->tx_stats.packets; 3907 } while (u64_stats_fetch_retry(&sky2->tx_stats.syncp, start)); 3908 3909 stats->tx_packets = _packets; 3910 stats->tx_bytes = _bytes; 3911 3912 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) 3913 + get_stats32(hw, port, GM_RXF_BC_OK); 3914 3915 stats->collisions = get_stats32(hw, port, GM_TXF_COL); 3916 3917 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); 3918 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); 3919 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) 3920 + get_stats32(hw, port, GM_RXE_FRAG); 3921 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); 3922 3923 stats->rx_dropped = dev->stats.rx_dropped; 3924 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 3925 stats->tx_fifo_errors = dev->stats.tx_fifo_errors; 3926 } 3927 3928 /* Can have one global because blinking is controlled by 3929 * ethtool and that is always under RTNL mutex 3930 */ 3931 static void sky2_led(struct sky2_port *sky2, enum led_mode mode) 3932 { 3933 struct sky2_hw *hw = sky2->hw; 3934 unsigned port = sky2->port; 3935 3936 spin_lock_bh(&sky2->phy_lock); 3937 if (hw->chip_id == CHIP_ID_YUKON_EC_U || 3938 hw->chip_id == CHIP_ID_YUKON_EX || 3939 hw->chip_id == CHIP_ID_YUKON_SUPR) { 3940 u16 pg; 3941 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3942 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3943 3944 switch (mode) { 3945 case MO_LED_OFF: 3946 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3947 PHY_M_LEDC_LOS_CTRL(8) | 3948 PHY_M_LEDC_INIT_CTRL(8) | 3949 PHY_M_LEDC_STA1_CTRL(8) | 3950 PHY_M_LEDC_STA0_CTRL(8)); 3951 break; 3952 case MO_LED_ON: 3953 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3954 PHY_M_LEDC_LOS_CTRL(9) | 3955 PHY_M_LEDC_INIT_CTRL(9) | 3956 PHY_M_LEDC_STA1_CTRL(9) | 3957 PHY_M_LEDC_STA0_CTRL(9)); 3958 break; 3959 case MO_LED_BLINK: 3960 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3961 PHY_M_LEDC_LOS_CTRL(0xa) | 3962 PHY_M_LEDC_INIT_CTRL(0xa) | 3963 PHY_M_LEDC_STA1_CTRL(0xa) | 3964 PHY_M_LEDC_STA0_CTRL(0xa)); 3965 break; 3966 case MO_LED_NORM: 3967 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3968 PHY_M_LEDC_LOS_CTRL(1) | 3969 PHY_M_LEDC_INIT_CTRL(8) | 3970 PHY_M_LEDC_STA1_CTRL(7) | 3971 PHY_M_LEDC_STA0_CTRL(7)); 3972 } 3973 3974 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3975 } else 3976 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 3977 PHY_M_LED_MO_DUP(mode) | 3978 PHY_M_LED_MO_10(mode) | 3979 PHY_M_LED_MO_100(mode) | 3980 PHY_M_LED_MO_1000(mode) | 3981 PHY_M_LED_MO_RX(mode) | 3982 PHY_M_LED_MO_TX(mode)); 3983 3984 spin_unlock_bh(&sky2->phy_lock); 3985 } 3986 3987 /* blink LED's for finding board */ 3988 static int sky2_set_phys_id(struct net_device *dev, 3989 enum ethtool_phys_id_state state) 3990 { 3991 struct sky2_port *sky2 = netdev_priv(dev); 3992 3993 switch (state) { 3994 case ETHTOOL_ID_ACTIVE: 3995 return 1; /* cycle on/off once per second */ 3996 case ETHTOOL_ID_INACTIVE: 3997 sky2_led(sky2, MO_LED_NORM); 3998 break; 3999 case ETHTOOL_ID_ON: 4000 sky2_led(sky2, MO_LED_ON); 4001 break; 4002 case ETHTOOL_ID_OFF: 4003 sky2_led(sky2, MO_LED_OFF); 4004 break; 4005 } 4006 4007 return 0; 4008 } 4009 4010 static void sky2_get_pauseparam(struct net_device *dev, 4011 struct ethtool_pauseparam *ecmd) 4012 { 4013 struct sky2_port *sky2 = netdev_priv(dev); 4014 4015 switch (sky2->flow_mode) { 4016 case FC_NONE: 4017 ecmd->tx_pause = ecmd->rx_pause = 0; 4018 break; 4019 case FC_TX: 4020 ecmd->tx_pause = 1, ecmd->rx_pause = 0; 4021 break; 4022 case FC_RX: 4023 ecmd->tx_pause = 0, ecmd->rx_pause = 1; 4024 break; 4025 case FC_BOTH: 4026 ecmd->tx_pause = ecmd->rx_pause = 1; 4027 } 4028 4029 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) 4030 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 4031 } 4032 4033 static int sky2_set_pauseparam(struct net_device *dev, 4034 struct ethtool_pauseparam *ecmd) 4035 { 4036 struct sky2_port *sky2 = netdev_priv(dev); 4037 4038 if (ecmd->autoneg == AUTONEG_ENABLE) 4039 sky2->flags |= SKY2_FLAG_AUTO_PAUSE; 4040 else 4041 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; 4042 4043 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); 4044 4045 if (netif_running(dev)) 4046 sky2_phy_reinit(sky2); 4047 4048 return 0; 4049 } 4050 4051 static int sky2_get_coalesce(struct net_device *dev, 4052 struct ethtool_coalesce *ecmd, 4053 struct kernel_ethtool_coalesce *kernel_coal, 4054 struct netlink_ext_ack *extack) 4055 { 4056 struct sky2_port *sky2 = netdev_priv(dev); 4057 struct sky2_hw *hw = sky2->hw; 4058 4059 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) 4060 ecmd->tx_coalesce_usecs = 0; 4061 else { 4062 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); 4063 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); 4064 } 4065 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); 4066 4067 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) 4068 ecmd->rx_coalesce_usecs = 0; 4069 else { 4070 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); 4071 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); 4072 } 4073 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); 4074 4075 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) 4076 ecmd->rx_coalesce_usecs_irq = 0; 4077 else { 4078 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); 4079 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); 4080 } 4081 4082 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); 4083 4084 return 0; 4085 } 4086 4087 /* Note: this affect both ports */ 4088 static int sky2_set_coalesce(struct net_device *dev, 4089 struct ethtool_coalesce *ecmd, 4090 struct kernel_ethtool_coalesce *kernel_coal, 4091 struct netlink_ext_ack *extack) 4092 { 4093 struct sky2_port *sky2 = netdev_priv(dev); 4094 struct sky2_hw *hw = sky2->hw; 4095 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); 4096 4097 if (ecmd->tx_coalesce_usecs > tmax || 4098 ecmd->rx_coalesce_usecs > tmax || 4099 ecmd->rx_coalesce_usecs_irq > tmax) 4100 return -EINVAL; 4101 4102 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) 4103 return -EINVAL; 4104 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) 4105 return -EINVAL; 4106 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) 4107 return -EINVAL; 4108 4109 if (ecmd->tx_coalesce_usecs == 0) 4110 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 4111 else { 4112 sky2_write32(hw, STAT_TX_TIMER_INI, 4113 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); 4114 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 4115 } 4116 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); 4117 4118 if (ecmd->rx_coalesce_usecs == 0) 4119 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); 4120 else { 4121 sky2_write32(hw, STAT_LEV_TIMER_INI, 4122 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); 4123 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 4124 } 4125 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); 4126 4127 if (ecmd->rx_coalesce_usecs_irq == 0) 4128 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); 4129 else { 4130 sky2_write32(hw, STAT_ISR_TIMER_INI, 4131 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); 4132 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 4133 } 4134 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); 4135 return 0; 4136 } 4137 4138 /* 4139 * Hardware is limited to min of 128 and max of 2048 for ring size 4140 * and rounded up to next power of two 4141 * to avoid division in modulus calculation 4142 */ 4143 static unsigned long roundup_ring_size(unsigned long pending) 4144 { 4145 return max(128ul, roundup_pow_of_two(pending+1)); 4146 } 4147 4148 static void sky2_get_ringparam(struct net_device *dev, 4149 struct ethtool_ringparam *ering, 4150 struct kernel_ethtool_ringparam *kernel_ering, 4151 struct netlink_ext_ack *extack) 4152 { 4153 struct sky2_port *sky2 = netdev_priv(dev); 4154 4155 ering->rx_max_pending = RX_MAX_PENDING; 4156 ering->tx_max_pending = TX_MAX_PENDING; 4157 4158 ering->rx_pending = sky2->rx_pending; 4159 ering->tx_pending = sky2->tx_pending; 4160 } 4161 4162 static int sky2_set_ringparam(struct net_device *dev, 4163 struct ethtool_ringparam *ering, 4164 struct kernel_ethtool_ringparam *kernel_ering, 4165 struct netlink_ext_ack *extack) 4166 { 4167 struct sky2_port *sky2 = netdev_priv(dev); 4168 4169 if (ering->rx_pending > RX_MAX_PENDING || 4170 ering->rx_pending < 8 || 4171 ering->tx_pending < TX_MIN_PENDING || 4172 ering->tx_pending > TX_MAX_PENDING) 4173 return -EINVAL; 4174 4175 sky2_detach(dev); 4176 4177 sky2->rx_pending = ering->rx_pending; 4178 sky2->tx_pending = ering->tx_pending; 4179 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending); 4180 4181 return sky2_reattach(dev); 4182 } 4183 4184 static int sky2_get_regs_len(struct net_device *dev) 4185 { 4186 return 0x4000; 4187 } 4188 4189 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) 4190 { 4191 /* This complicated switch statement is to make sure and 4192 * only access regions that are unreserved. 4193 * Some blocks are only valid on dual port cards. 4194 */ 4195 switch (b) { 4196 /* second port */ 4197 case 5: /* Tx Arbiter 2 */ 4198 case 9: /* RX2 */ 4199 case 14 ... 15: /* TX2 */ 4200 case 17: case 19: /* Ram Buffer 2 */ 4201 case 22 ... 23: /* Tx Ram Buffer 2 */ 4202 case 25: /* Rx MAC Fifo 1 */ 4203 case 27: /* Tx MAC Fifo 2 */ 4204 case 31: /* GPHY 2 */ 4205 case 40 ... 47: /* Pattern Ram 2 */ 4206 case 52: case 54: /* TCP Segmentation 2 */ 4207 case 112 ... 116: /* GMAC 2 */ 4208 return hw->ports > 1; 4209 4210 case 0: /* Control */ 4211 case 2: /* Mac address */ 4212 case 4: /* Tx Arbiter 1 */ 4213 case 7: /* PCI express reg */ 4214 case 8: /* RX1 */ 4215 case 12 ... 13: /* TX1 */ 4216 case 16: case 18:/* Rx Ram Buffer 1 */ 4217 case 20 ... 21: /* Tx Ram Buffer 1 */ 4218 case 24: /* Rx MAC Fifo 1 */ 4219 case 26: /* Tx MAC Fifo 1 */ 4220 case 28 ... 29: /* Descriptor and status unit */ 4221 case 30: /* GPHY 1*/ 4222 case 32 ... 39: /* Pattern Ram 1 */ 4223 case 48: case 50: /* TCP Segmentation 1 */ 4224 case 56 ... 60: /* PCI space */ 4225 case 80 ... 84: /* GMAC 1 */ 4226 return 1; 4227 4228 default: 4229 return 0; 4230 } 4231 } 4232 4233 /* 4234 * Returns copy of control register region 4235 * Note: ethtool_get_regs always provides full size (16k) buffer 4236 */ 4237 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4238 void *p) 4239 { 4240 const struct sky2_port *sky2 = netdev_priv(dev); 4241 const void __iomem *io = sky2->hw->regs; 4242 unsigned int b; 4243 4244 regs->version = 1; 4245 4246 for (b = 0; b < 128; b++) { 4247 /* skip poisonous diagnostic ram region in block 3 */ 4248 if (b == 3) 4249 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); 4250 else if (sky2_reg_access_ok(sky2->hw, b)) 4251 memcpy_fromio(p, io, 128); 4252 else 4253 memset(p, 0, 128); 4254 4255 p += 128; 4256 io += 128; 4257 } 4258 } 4259 4260 static int sky2_get_eeprom_len(struct net_device *dev) 4261 { 4262 struct sky2_port *sky2 = netdev_priv(dev); 4263 struct sky2_hw *hw = sky2->hw; 4264 u16 reg2; 4265 4266 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4267 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4268 } 4269 4270 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4271 u8 *data) 4272 { 4273 struct sky2_port *sky2 = netdev_priv(dev); 4274 int rc; 4275 4276 eeprom->magic = SKY2_EEPROM_MAGIC; 4277 rc = pci_read_vpd_any(sky2->hw->pdev, eeprom->offset, eeprom->len, 4278 data); 4279 if (rc < 0) 4280 return rc; 4281 4282 eeprom->len = rc; 4283 4284 return 0; 4285 } 4286 4287 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4288 u8 *data) 4289 { 4290 struct sky2_port *sky2 = netdev_priv(dev); 4291 int rc; 4292 4293 if (eeprom->magic != SKY2_EEPROM_MAGIC) 4294 return -EINVAL; 4295 4296 rc = pci_write_vpd_any(sky2->hw->pdev, eeprom->offset, eeprom->len, 4297 data); 4298 4299 return rc < 0 ? rc : 0; 4300 } 4301 4302 static netdev_features_t sky2_fix_features(struct net_device *dev, 4303 netdev_features_t features) 4304 { 4305 const struct sky2_port *sky2 = netdev_priv(dev); 4306 const struct sky2_hw *hw = sky2->hw; 4307 4308 /* In order to do Jumbo packets on these chips, need to turn off the 4309 * transmit store/forward. Therefore checksum offload won't work. 4310 */ 4311 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { 4312 netdev_info(dev, "checksum offload not possible with jumbo frames\n"); 4313 features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK); 4314 } 4315 4316 /* Some hardware requires receive checksum for RSS to work. */ 4317 if ( (features & NETIF_F_RXHASH) && 4318 !(features & NETIF_F_RXCSUM) && 4319 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { 4320 netdev_info(dev, "receive hashing forces receive checksum\n"); 4321 features |= NETIF_F_RXCSUM; 4322 } 4323 4324 return features; 4325 } 4326 4327 static int sky2_set_features(struct net_device *dev, netdev_features_t features) 4328 { 4329 struct sky2_port *sky2 = netdev_priv(dev); 4330 netdev_features_t changed = dev->features ^ features; 4331 4332 if ((changed & NETIF_F_RXCSUM) && 4333 !(sky2->hw->flags & SKY2_HW_NEW_LE)) { 4334 sky2_write32(sky2->hw, 4335 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 4336 (features & NETIF_F_RXCSUM) 4337 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 4338 } 4339 4340 if (changed & NETIF_F_RXHASH) 4341 rx_set_rss(dev, features); 4342 4343 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX)) 4344 sky2_vlan_mode(dev, features); 4345 4346 return 0; 4347 } 4348 4349 static const struct ethtool_ops sky2_ethtool_ops = { 4350 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 4351 ETHTOOL_COALESCE_MAX_FRAMES | 4352 ETHTOOL_COALESCE_RX_USECS_IRQ | 4353 ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ, 4354 .get_drvinfo = sky2_get_drvinfo, 4355 .get_wol = sky2_get_wol, 4356 .set_wol = sky2_set_wol, 4357 .get_msglevel = sky2_get_msglevel, 4358 .set_msglevel = sky2_set_msglevel, 4359 .nway_reset = sky2_nway_reset, 4360 .get_regs_len = sky2_get_regs_len, 4361 .get_regs = sky2_get_regs, 4362 .get_link = ethtool_op_get_link, 4363 .get_eeprom_len = sky2_get_eeprom_len, 4364 .get_eeprom = sky2_get_eeprom, 4365 .set_eeprom = sky2_set_eeprom, 4366 .get_strings = sky2_get_strings, 4367 .get_coalesce = sky2_get_coalesce, 4368 .set_coalesce = sky2_set_coalesce, 4369 .get_ringparam = sky2_get_ringparam, 4370 .set_ringparam = sky2_set_ringparam, 4371 .get_pauseparam = sky2_get_pauseparam, 4372 .set_pauseparam = sky2_set_pauseparam, 4373 .set_phys_id = sky2_set_phys_id, 4374 .get_sset_count = sky2_get_sset_count, 4375 .get_ethtool_stats = sky2_get_ethtool_stats, 4376 .get_link_ksettings = sky2_get_link_ksettings, 4377 .set_link_ksettings = sky2_set_link_ksettings, 4378 }; 4379 4380 #ifdef CONFIG_SKY2_DEBUG 4381 4382 static struct dentry *sky2_debug; 4383 4384 static int sky2_debug_show(struct seq_file *seq, void *v) 4385 { 4386 struct net_device *dev = seq->private; 4387 const struct sky2_port *sky2 = netdev_priv(dev); 4388 struct sky2_hw *hw = sky2->hw; 4389 unsigned port = sky2->port; 4390 unsigned idx, last; 4391 int sop; 4392 4393 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n", 4394 sky2_read32(hw, B0_ISRC), 4395 sky2_read32(hw, B0_IMSK), 4396 sky2_read32(hw, B0_Y2_SP_ICR)); 4397 4398 if (!netif_running(dev)) { 4399 seq_puts(seq, "network not running\n"); 4400 return 0; 4401 } 4402 4403 napi_disable(&hw->napi); 4404 last = sky2_read16(hw, STAT_PUT_IDX); 4405 4406 seq_printf(seq, "Status ring %u\n", hw->st_size); 4407 if (hw->st_idx == last) 4408 seq_puts(seq, "Status ring (empty)\n"); 4409 else { 4410 seq_puts(seq, "Status ring\n"); 4411 for (idx = hw->st_idx; idx != last && idx < hw->st_size; 4412 idx = RING_NEXT(idx, hw->st_size)) { 4413 const struct sky2_status_le *le = hw->st_le + idx; 4414 seq_printf(seq, "[%d] %#x %d %#x\n", 4415 idx, le->opcode, le->length, le->status); 4416 } 4417 seq_puts(seq, "\n"); 4418 } 4419 4420 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", 4421 sky2->tx_cons, sky2->tx_prod, 4422 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 4423 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); 4424 4425 /* Dump contents of tx ring */ 4426 sop = 1; 4427 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; 4428 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 4429 const struct sky2_tx_le *le = sky2->tx_le + idx; 4430 u32 a = le32_to_cpu(le->addr); 4431 4432 if (sop) 4433 seq_printf(seq, "%u:", idx); 4434 sop = 0; 4435 4436 switch (le->opcode & ~HW_OWNER) { 4437 case OP_ADDR64: 4438 seq_printf(seq, " %#x:", a); 4439 break; 4440 case OP_LRGLEN: 4441 seq_printf(seq, " mtu=%d", a); 4442 break; 4443 case OP_VLAN: 4444 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); 4445 break; 4446 case OP_TCPLISW: 4447 seq_printf(seq, " csum=%#x", a); 4448 break; 4449 case OP_LARGESEND: 4450 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); 4451 break; 4452 case OP_PACKET: 4453 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); 4454 break; 4455 case OP_BUFFER: 4456 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); 4457 break; 4458 default: 4459 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, 4460 a, le16_to_cpu(le->length)); 4461 } 4462 4463 if (le->ctrl & EOP) { 4464 seq_putc(seq, '\n'); 4465 sop = 1; 4466 } 4467 } 4468 4469 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", 4470 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), 4471 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), 4472 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); 4473 4474 sky2_read32(hw, B0_Y2_SP_LISR); 4475 napi_enable(&hw->napi); 4476 return 0; 4477 } 4478 DEFINE_SHOW_ATTRIBUTE(sky2_debug); 4479 4480 /* 4481 * Use network device events to create/remove/rename 4482 * debugfs file entries 4483 */ 4484 static int sky2_device_event(struct notifier_block *unused, 4485 unsigned long event, void *ptr) 4486 { 4487 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4488 struct sky2_port *sky2 = netdev_priv(dev); 4489 4490 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug) 4491 return NOTIFY_DONE; 4492 4493 switch (event) { 4494 case NETDEV_CHANGENAME: 4495 debugfs_change_name(sky2->debugfs, "%s", dev->name); 4496 break; 4497 4498 case NETDEV_GOING_DOWN: 4499 if (sky2->debugfs) { 4500 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); 4501 debugfs_remove(sky2->debugfs); 4502 sky2->debugfs = NULL; 4503 } 4504 break; 4505 4506 case NETDEV_UP: 4507 sky2->debugfs = debugfs_create_file(dev->name, 0444, 4508 sky2_debug, dev, 4509 &sky2_debug_fops); 4510 if (IS_ERR(sky2->debugfs)) 4511 sky2->debugfs = NULL; 4512 } 4513 4514 return NOTIFY_DONE; 4515 } 4516 4517 static struct notifier_block sky2_notifier = { 4518 .notifier_call = sky2_device_event, 4519 }; 4520 4521 4522 static __init void sky2_debug_init(void) 4523 { 4524 struct dentry *ent; 4525 4526 ent = debugfs_create_dir("sky2", NULL); 4527 if (IS_ERR(ent)) 4528 return; 4529 4530 sky2_debug = ent; 4531 register_netdevice_notifier(&sky2_notifier); 4532 } 4533 4534 static __exit void sky2_debug_cleanup(void) 4535 { 4536 if (sky2_debug) { 4537 unregister_netdevice_notifier(&sky2_notifier); 4538 debugfs_remove(sky2_debug); 4539 sky2_debug = NULL; 4540 } 4541 } 4542 4543 #else 4544 #define sky2_debug_init() 4545 #define sky2_debug_cleanup() 4546 #endif 4547 4548 /* Two copies of network device operations to handle special case of 4549 * not allowing netpoll on second port 4550 */ 4551 static const struct net_device_ops sky2_netdev_ops[2] = { 4552 { 4553 .ndo_open = sky2_open, 4554 .ndo_stop = sky2_close, 4555 .ndo_start_xmit = sky2_xmit_frame, 4556 .ndo_eth_ioctl = sky2_ioctl, 4557 .ndo_validate_addr = eth_validate_addr, 4558 .ndo_set_mac_address = sky2_set_mac_address, 4559 .ndo_set_rx_mode = sky2_set_multicast, 4560 .ndo_change_mtu = sky2_change_mtu, 4561 .ndo_fix_features = sky2_fix_features, 4562 .ndo_set_features = sky2_set_features, 4563 .ndo_tx_timeout = sky2_tx_timeout, 4564 .ndo_get_stats64 = sky2_get_stats, 4565 #ifdef CONFIG_NET_POLL_CONTROLLER 4566 .ndo_poll_controller = sky2_netpoll, 4567 #endif 4568 }, 4569 { 4570 .ndo_open = sky2_open, 4571 .ndo_stop = sky2_close, 4572 .ndo_start_xmit = sky2_xmit_frame, 4573 .ndo_eth_ioctl = sky2_ioctl, 4574 .ndo_validate_addr = eth_validate_addr, 4575 .ndo_set_mac_address = sky2_set_mac_address, 4576 .ndo_set_rx_mode = sky2_set_multicast, 4577 .ndo_change_mtu = sky2_change_mtu, 4578 .ndo_fix_features = sky2_fix_features, 4579 .ndo_set_features = sky2_set_features, 4580 .ndo_tx_timeout = sky2_tx_timeout, 4581 .ndo_get_stats64 = sky2_get_stats, 4582 }, 4583 }; 4584 4585 /* Initialize network device */ 4586 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port, 4587 int highmem, int wol) 4588 { 4589 struct sky2_port *sky2; 4590 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 4591 int ret; 4592 4593 if (!dev) 4594 return NULL; 4595 4596 SET_NETDEV_DEV(dev, &hw->pdev->dev); 4597 dev->irq = hw->pdev->irq; 4598 dev->ethtool_ops = &sky2_ethtool_ops; 4599 dev->watchdog_timeo = TX_WATCHDOG; 4600 dev->netdev_ops = &sky2_netdev_ops[port]; 4601 4602 sky2 = netdev_priv(dev); 4603 sky2->netdev = dev; 4604 sky2->hw = hw; 4605 sky2->msg_enable = netif_msg_init(debug, default_msg); 4606 4607 u64_stats_init(&sky2->tx_stats.syncp); 4608 u64_stats_init(&sky2->rx_stats.syncp); 4609 4610 /* Auto speed and flow control */ 4611 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; 4612 if (hw->chip_id != CHIP_ID_YUKON_XL) 4613 dev->hw_features |= NETIF_F_RXCSUM; 4614 4615 sky2->flow_mode = FC_BOTH; 4616 4617 sky2->duplex = -1; 4618 sky2->speed = -1; 4619 sky2->advertising = sky2_supported_modes(hw); 4620 sky2->wol = wol; 4621 4622 spin_lock_init(&sky2->phy_lock); 4623 4624 sky2->tx_pending = TX_DEF_PENDING; 4625 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING); 4626 sky2->rx_pending = RX_DEF_PENDING; 4627 4628 hw->dev[port] = dev; 4629 4630 sky2->port = port; 4631 4632 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; 4633 4634 if (highmem) 4635 dev->features |= NETIF_F_HIGHDMA; 4636 4637 /* Enable receive hashing unless hardware is known broken */ 4638 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 4639 dev->hw_features |= NETIF_F_RXHASH; 4640 4641 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { 4642 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 4643 NETIF_F_HW_VLAN_CTAG_RX; 4644 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 4645 } 4646 4647 dev->features |= dev->hw_features; 4648 4649 /* MTU range: 60 - 1500 or 9000 */ 4650 dev->min_mtu = ETH_ZLEN; 4651 if (hw->chip_id == CHIP_ID_YUKON_FE || 4652 hw->chip_id == CHIP_ID_YUKON_FE_P) 4653 dev->max_mtu = ETH_DATA_LEN; 4654 else 4655 dev->max_mtu = ETH_JUMBO_MTU; 4656 4657 /* try to get mac address in the following order: 4658 * 1) from device tree data 4659 * 2) from internal registers set by bootloader 4660 */ 4661 ret = of_get_ethdev_address(hw->pdev->dev.of_node, dev); 4662 if (ret) { 4663 u8 addr[ETH_ALEN]; 4664 4665 memcpy_fromio(addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); 4666 eth_hw_addr_set(dev, addr); 4667 } 4668 4669 /* if the address is invalid, use a random value */ 4670 if (!is_valid_ether_addr(dev->dev_addr)) { 4671 struct sockaddr sa = { AF_UNSPEC }; 4672 4673 dev_warn(&hw->pdev->dev, "Invalid MAC address, defaulting to random\n"); 4674 eth_hw_addr_random(dev); 4675 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN); 4676 if (sky2_set_mac_address(dev, &sa)) 4677 dev_warn(&hw->pdev->dev, "Failed to set MAC address.\n"); 4678 } 4679 4680 return dev; 4681 } 4682 4683 static void sky2_show_addr(struct net_device *dev) 4684 { 4685 const struct sky2_port *sky2 = netdev_priv(dev); 4686 4687 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); 4688 } 4689 4690 /* Handle software interrupt used during MSI test */ 4691 static irqreturn_t sky2_test_intr(int irq, void *dev_id) 4692 { 4693 struct sky2_hw *hw = dev_id; 4694 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 4695 4696 if (status == 0) 4697 return IRQ_NONE; 4698 4699 if (status & Y2_IS_IRQ_SW) { 4700 hw->flags |= SKY2_HW_USE_MSI; 4701 wake_up(&hw->msi_wait); 4702 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4703 } 4704 sky2_write32(hw, B0_Y2_SP_ICR, 2); 4705 4706 return IRQ_HANDLED; 4707 } 4708 4709 /* Test interrupt path by forcing a software IRQ */ 4710 static int sky2_test_msi(struct sky2_hw *hw) 4711 { 4712 struct pci_dev *pdev = hw->pdev; 4713 int err; 4714 4715 init_waitqueue_head(&hw->msi_wait); 4716 4717 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); 4718 if (err) { 4719 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 4720 return err; 4721 } 4722 4723 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 4724 4725 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 4726 sky2_read8(hw, B0_CTST); 4727 4728 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); 4729 4730 if (!(hw->flags & SKY2_HW_USE_MSI)) { 4731 /* MSI test failed, go back to INTx mode */ 4732 dev_info(&pdev->dev, "No interrupt generated using MSI, " 4733 "switching to INTx mode.\n"); 4734 4735 err = -EOPNOTSUPP; 4736 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4737 } 4738 4739 sky2_write32(hw, B0_IMSK, 0); 4740 sky2_read32(hw, B0_IMSK); 4741 4742 free_irq(pdev->irq, hw); 4743 4744 return err; 4745 } 4746 4747 /* This driver supports yukon2 chipset only */ 4748 static const char *sky2_name(u8 chipid, char *buf, int sz) 4749 { 4750 static const char *const name[] = { 4751 "XL", /* 0xb3 */ 4752 "EC Ultra", /* 0xb4 */ 4753 "Extreme", /* 0xb5 */ 4754 "EC", /* 0xb6 */ 4755 "FE", /* 0xb7 */ 4756 "FE+", /* 0xb8 */ 4757 "Supreme", /* 0xb9 */ 4758 "UL 2", /* 0xba */ 4759 "Unknown", /* 0xbb */ 4760 "Optima", /* 0xbc */ 4761 "OptimaEEE", /* 0xbd */ 4762 "Optima 2", /* 0xbe */ 4763 }; 4764 4765 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2) 4766 snprintf(buf, sz, "%s", name[chipid - CHIP_ID_YUKON_XL]); 4767 else 4768 snprintf(buf, sz, "(chip %#x)", chipid); 4769 return buf; 4770 } 4771 4772 static const struct dmi_system_id msi_blacklist[] = { 4773 { 4774 .ident = "Dell Inspiron 1545", 4775 .matches = { 4776 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 4777 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 1545"), 4778 }, 4779 }, 4780 { 4781 .ident = "Gateway P-79", 4782 .matches = { 4783 DMI_MATCH(DMI_SYS_VENDOR, "Gateway"), 4784 DMI_MATCH(DMI_PRODUCT_NAME, "P-79"), 4785 }, 4786 }, 4787 { 4788 .ident = "ASUS P5W DH Deluxe", 4789 .matches = { 4790 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTEK COMPUTER INC"), 4791 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 4792 }, 4793 }, 4794 { 4795 .ident = "ASUS P6T", 4796 .matches = { 4797 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 4798 DMI_MATCH(DMI_BOARD_NAME, "P6T"), 4799 }, 4800 }, 4801 { 4802 .ident = "ASUS P6X", 4803 .matches = { 4804 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 4805 DMI_MATCH(DMI_BOARD_NAME, "P6X"), 4806 }, 4807 }, 4808 {} 4809 }; 4810 4811 static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 4812 { 4813 struct net_device *dev, *dev1; 4814 struct sky2_hw *hw; 4815 int err, using_dac = 0, wol_default; 4816 u32 reg; 4817 char buf1[16]; 4818 4819 err = pci_enable_device(pdev); 4820 if (err) { 4821 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4822 goto err_out; 4823 } 4824 4825 /* Get configuration information 4826 * Note: only regular PCI config access once to test for HW issues 4827 * other PCI access through shared memory for speed and to 4828 * avoid MMCONFIG problems. 4829 */ 4830 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 4831 if (err) { 4832 dev_err(&pdev->dev, "PCI read config failed\n"); 4833 goto err_out_disable; 4834 } 4835 4836 if (~reg == 0) { 4837 dev_err(&pdev->dev, "PCI configuration read error\n"); 4838 err = -EIO; 4839 goto err_out_disable; 4840 } 4841 4842 err = pci_request_regions(pdev, DRV_NAME); 4843 if (err) { 4844 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 4845 goto err_out_disable; 4846 } 4847 4848 pci_set_master(pdev); 4849 4850 if (sizeof(dma_addr_t) > sizeof(u32) && 4851 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 4852 using_dac = 1; 4853 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 4854 if (err < 0) { 4855 dev_err(&pdev->dev, "unable to obtain 64 bit DMA " 4856 "for consistent allocations\n"); 4857 goto err_out_free_regions; 4858 } 4859 } else { 4860 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 4861 if (err) { 4862 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4863 goto err_out_free_regions; 4864 } 4865 } 4866 4867 4868 #ifdef __BIG_ENDIAN 4869 /* The sk98lin vendor driver uses hardware byte swapping but 4870 * this driver uses software swapping. 4871 */ 4872 reg &= ~PCI_REV_DESC; 4873 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 4874 if (err) { 4875 dev_err(&pdev->dev, "PCI write config failed\n"); 4876 goto err_out_free_regions; 4877 } 4878 #endif 4879 4880 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; 4881 4882 err = -ENOMEM; 4883 4884 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 4885 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 4886 if (!hw) 4887 goto err_out_free_regions; 4888 4889 hw->pdev = pdev; 4890 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 4891 4892 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000); 4893 if (!hw->regs) { 4894 dev_err(&pdev->dev, "cannot map device registers\n"); 4895 goto err_out_free_hw; 4896 } 4897 4898 err = sky2_init(hw); 4899 if (err) 4900 goto err_out_iounmap; 4901 4902 /* ring for status responses */ 4903 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); 4904 hw->st_le = dma_alloc_coherent(&pdev->dev, 4905 hw->st_size * sizeof(struct sky2_status_le), 4906 &hw->st_dma, GFP_KERNEL); 4907 if (!hw->st_le) { 4908 err = -ENOMEM; 4909 goto err_out_reset; 4910 } 4911 4912 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", 4913 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); 4914 4915 sky2_reset(hw); 4916 4917 dev = sky2_init_netdev(hw, 0, using_dac, wol_default); 4918 if (!dev) { 4919 err = -ENOMEM; 4920 goto err_out_free_pci; 4921 } 4922 4923 if (disable_msi == -1) 4924 disable_msi = !!dmi_check_system(msi_blacklist); 4925 4926 if (!disable_msi && pci_enable_msi(pdev) == 0) { 4927 err = sky2_test_msi(hw); 4928 if (err) { 4929 pci_disable_msi(pdev); 4930 if (err != -EOPNOTSUPP) 4931 goto err_out_free_netdev; 4932 } 4933 } 4934 4935 netif_napi_add(dev, &hw->napi, sky2_poll); 4936 4937 err = register_netdev(dev); 4938 if (err) { 4939 dev_err(&pdev->dev, "cannot register net device\n"); 4940 goto err_out_free_netdev; 4941 } 4942 4943 netif_carrier_off(dev); 4944 4945 sky2_show_addr(dev); 4946 4947 if (hw->ports > 1) { 4948 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); 4949 if (!dev1) { 4950 err = -ENOMEM; 4951 goto err_out_unregister; 4952 } 4953 4954 err = register_netdev(dev1); 4955 if (err) { 4956 dev_err(&pdev->dev, "cannot register second net device\n"); 4957 goto err_out_free_dev1; 4958 } 4959 4960 err = sky2_setup_irq(hw, hw->irq_name); 4961 if (err) 4962 goto err_out_unregister_dev1; 4963 4964 sky2_show_addr(dev1); 4965 } 4966 4967 timer_setup(&hw->watchdog_timer, sky2_watchdog, 0); 4968 INIT_WORK(&hw->restart_work, sky2_restart); 4969 4970 pci_set_drvdata(pdev, hw); 4971 pdev->d3hot_delay = 300; 4972 4973 return 0; 4974 4975 err_out_unregister_dev1: 4976 unregister_netdev(dev1); 4977 err_out_free_dev1: 4978 free_netdev(dev1); 4979 err_out_unregister: 4980 unregister_netdev(dev); 4981 err_out_free_netdev: 4982 if (hw->flags & SKY2_HW_USE_MSI) 4983 pci_disable_msi(pdev); 4984 free_netdev(dev); 4985 err_out_free_pci: 4986 dma_free_coherent(&pdev->dev, 4987 hw->st_size * sizeof(struct sky2_status_le), 4988 hw->st_le, hw->st_dma); 4989 err_out_reset: 4990 sky2_write8(hw, B0_CTST, CS_RST_SET); 4991 err_out_iounmap: 4992 iounmap(hw->regs); 4993 err_out_free_hw: 4994 kfree(hw); 4995 err_out_free_regions: 4996 pci_release_regions(pdev); 4997 err_out_disable: 4998 pci_disable_device(pdev); 4999 err_out: 5000 return err; 5001 } 5002 5003 static void sky2_remove(struct pci_dev *pdev) 5004 { 5005 struct sky2_hw *hw = pci_get_drvdata(pdev); 5006 int i; 5007 5008 if (!hw) 5009 return; 5010 5011 timer_shutdown_sync(&hw->watchdog_timer); 5012 cancel_work_sync(&hw->restart_work); 5013 5014 for (i = hw->ports-1; i >= 0; --i) 5015 unregister_netdev(hw->dev[i]); 5016 5017 sky2_write32(hw, B0_IMSK, 0); 5018 sky2_read32(hw, B0_IMSK); 5019 5020 sky2_power_aux(hw); 5021 5022 sky2_write8(hw, B0_CTST, CS_RST_SET); 5023 sky2_read8(hw, B0_CTST); 5024 5025 if (hw->ports > 1) { 5026 napi_disable(&hw->napi); 5027 free_irq(pdev->irq, hw); 5028 } 5029 5030 if (hw->flags & SKY2_HW_USE_MSI) 5031 pci_disable_msi(pdev); 5032 dma_free_coherent(&pdev->dev, 5033 hw->st_size * sizeof(struct sky2_status_le), 5034 hw->st_le, hw->st_dma); 5035 pci_release_regions(pdev); 5036 pci_disable_device(pdev); 5037 5038 for (i = hw->ports-1; i >= 0; --i) 5039 free_netdev(hw->dev[i]); 5040 5041 iounmap(hw->regs); 5042 kfree(hw); 5043 } 5044 5045 static int sky2_suspend(struct device *dev) 5046 { 5047 struct sky2_hw *hw = dev_get_drvdata(dev); 5048 int i; 5049 5050 if (!hw) 5051 return 0; 5052 5053 timer_delete_sync(&hw->watchdog_timer); 5054 cancel_work_sync(&hw->restart_work); 5055 5056 rtnl_lock(); 5057 5058 sky2_all_down(hw); 5059 for (i = 0; i < hw->ports; i++) { 5060 struct net_device *dev = hw->dev[i]; 5061 struct sky2_port *sky2 = netdev_priv(dev); 5062 5063 if (sky2->wol) 5064 sky2_wol_init(sky2); 5065 } 5066 5067 sky2_power_aux(hw); 5068 rtnl_unlock(); 5069 5070 return 0; 5071 } 5072 5073 #ifdef CONFIG_PM_SLEEP 5074 static int sky2_resume(struct device *dev) 5075 { 5076 struct pci_dev *pdev = to_pci_dev(dev); 5077 struct sky2_hw *hw = pci_get_drvdata(pdev); 5078 int err; 5079 5080 if (!hw) 5081 return 0; 5082 5083 /* Re-enable all clocks */ 5084 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); 5085 if (err) { 5086 dev_err(&pdev->dev, "PCI write config failed\n"); 5087 goto out; 5088 } 5089 5090 rtnl_lock(); 5091 sky2_reset(hw); 5092 sky2_all_up(hw); 5093 rtnl_unlock(); 5094 5095 return 0; 5096 out: 5097 5098 dev_err(&pdev->dev, "resume failed (%d)\n", err); 5099 pci_disable_device(pdev); 5100 return err; 5101 } 5102 5103 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); 5104 #define SKY2_PM_OPS (&sky2_pm_ops) 5105 5106 #else 5107 5108 #define SKY2_PM_OPS NULL 5109 #endif 5110 5111 static void sky2_shutdown(struct pci_dev *pdev) 5112 { 5113 struct sky2_hw *hw = pci_get_drvdata(pdev); 5114 int port; 5115 5116 for (port = 0; port < hw->ports; port++) { 5117 struct net_device *ndev = hw->dev[port]; 5118 5119 rtnl_lock(); 5120 if (netif_running(ndev)) { 5121 dev_close(ndev); 5122 netif_device_detach(ndev); 5123 } 5124 rtnl_unlock(); 5125 } 5126 sky2_suspend(&pdev->dev); 5127 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 5128 pci_set_power_state(pdev, PCI_D3hot); 5129 } 5130 5131 static struct pci_driver sky2_driver = { 5132 .name = DRV_NAME, 5133 .id_table = sky2_id_table, 5134 .probe = sky2_probe, 5135 .remove = sky2_remove, 5136 .shutdown = sky2_shutdown, 5137 .driver.pm = SKY2_PM_OPS, 5138 }; 5139 5140 static int __init sky2_init_module(void) 5141 { 5142 pr_info("driver version " DRV_VERSION "\n"); 5143 5144 sky2_debug_init(); 5145 return pci_register_driver(&sky2_driver); 5146 } 5147 5148 static void __exit sky2_cleanup_module(void) 5149 { 5150 pci_unregister_driver(&sky2_driver); 5151 sky2_debug_cleanup(); 5152 } 5153 5154 module_init(sky2_init_module); 5155 module_exit(sky2_cleanup_module); 5156 5157 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); 5158 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 5159 MODULE_LICENSE("GPL"); 5160 MODULE_VERSION(DRV_VERSION); 5161