1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * New driver for Marvell Yukon chipset and SysKonnect Gigabit 4 * Ethernet adapters. Based on earlier sk98lin, e100 and 5 * FreeBSD if_sk drivers. 6 * 7 * This driver intentionally does not support all the features 8 * of the original driver such as link fail-over and link management because 9 * those should be done at higher levels. 10 * 11 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org> 12 */ 13 14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 15 16 #include <linux/in.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/netdevice.h> 21 #include <linux/etherdevice.h> 22 #include <linux/ethtool.h> 23 #include <linux/pci.h> 24 #include <linux/if_vlan.h> 25 #include <linux/ip.h> 26 #include <linux/delay.h> 27 #include <linux/crc32.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/debugfs.h> 30 #include <linux/sched.h> 31 #include <linux/seq_file.h> 32 #include <linux/mii.h> 33 #include <linux/slab.h> 34 #include <linux/dmi.h> 35 #include <linux/prefetch.h> 36 #include <asm/irq.h> 37 38 #include "skge.h" 39 40 #define DRV_NAME "skge" 41 #define DRV_VERSION "1.14" 42 43 #define DEFAULT_TX_RING_SIZE 128 44 #define DEFAULT_RX_RING_SIZE 512 45 #define MAX_TX_RING_SIZE 1024 46 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1) 47 #define MAX_RX_RING_SIZE 4096 48 #define RX_COPY_THRESHOLD 128 49 #define RX_BUF_SIZE 1536 50 #define PHY_RETRIES 1000 51 #define ETH_JUMBO_MTU 9000 52 #define TX_WATCHDOG (5 * HZ) 53 #define NAPI_WEIGHT 64 54 #define BLINK_MS 250 55 #define LINK_HZ HZ 56 57 #define SKGE_EEPROM_MAGIC 0x9933aabb 58 59 60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver"); 61 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 62 MODULE_LICENSE("GPL"); 63 MODULE_VERSION(DRV_VERSION); 64 65 static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 66 NETIF_MSG_LINK | NETIF_MSG_IFUP | 67 NETIF_MSG_IFDOWN); 68 69 static int debug = -1; /* defaults above */ 70 module_param(debug, int, 0); 71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 72 73 static const struct pci_device_id skge_id_table[] = { 74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */ 75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */ 76 #ifdef CONFIG_SKGE_GENESIS 77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */ 78 #endif 79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */ 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */ 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */ 82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */ 83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */ 84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */ 85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */ 86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */ 87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */ 88 { 0 } 89 }; 90 MODULE_DEVICE_TABLE(pci, skge_id_table); 91 92 static int skge_up(struct net_device *dev); 93 static int skge_down(struct net_device *dev); 94 static void skge_phy_reset(struct skge_port *skge); 95 static void skge_tx_clean(struct net_device *dev); 96 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 97 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 98 static void genesis_get_stats(struct skge_port *skge, u64 *data); 99 static void yukon_get_stats(struct skge_port *skge, u64 *data); 100 static void yukon_init(struct skge_hw *hw, int port); 101 static void genesis_mac_init(struct skge_hw *hw, int port); 102 static void genesis_link_up(struct skge_port *skge); 103 static void skge_set_multicast(struct net_device *dev); 104 static irqreturn_t skge_intr(int irq, void *dev_id); 105 106 /* Avoid conditionals by using array */ 107 static const int txqaddr[] = { Q_XA1, Q_XA2 }; 108 static const int rxqaddr[] = { Q_R1, Q_R2 }; 109 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; 110 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; 111 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F }; 112 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 }; 113 114 static inline bool is_genesis(const struct skge_hw *hw) 115 { 116 #ifdef CONFIG_SKGE_GENESIS 117 return hw->chip_id == CHIP_ID_GENESIS; 118 #else 119 return false; 120 #endif 121 } 122 123 static int skge_get_regs_len(struct net_device *dev) 124 { 125 return 0x4000; 126 } 127 128 /* 129 * Returns copy of whole control register region 130 * Note: skip RAM address register because accessing it will 131 * cause bus hangs! 132 */ 133 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs, 134 void *p) 135 { 136 const struct skge_port *skge = netdev_priv(dev); 137 const void __iomem *io = skge->hw->regs; 138 139 regs->version = 1; 140 memset(p, 0, regs->len); 141 memcpy_fromio(p, io, B3_RAM_ADDR); 142 143 if (regs->len > B3_RI_WTO_R1) { 144 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 145 regs->len - B3_RI_WTO_R1); 146 } 147 } 148 149 /* Wake on Lan only supported on Yukon chips with rev 1 or above */ 150 static u32 wol_supported(const struct skge_hw *hw) 151 { 152 if (is_genesis(hw)) 153 return 0; 154 155 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) 156 return 0; 157 158 return WAKE_MAGIC | WAKE_PHY; 159 } 160 161 static void skge_wol_init(struct skge_port *skge) 162 { 163 struct skge_hw *hw = skge->hw; 164 int port = skge->port; 165 u16 ctrl; 166 167 skge_write16(hw, B0_CTST, CS_RST_CLR); 168 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 169 170 /* Turn on Vaux */ 171 skge_write8(hw, B0_POWER_CTRL, 172 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 173 174 /* WA code for COMA mode -- clear PHY reset */ 175 if (hw->chip_id == CHIP_ID_YUKON_LITE && 176 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 177 u32 reg = skge_read32(hw, B2_GP_IO); 178 reg |= GP_DIR_9; 179 reg &= ~GP_IO_9; 180 skge_write32(hw, B2_GP_IO, reg); 181 } 182 183 skge_write32(hw, SK_REG(port, GPHY_CTRL), 184 GPC_DIS_SLEEP | 185 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 | 186 GPC_ANEG_1 | GPC_RST_SET); 187 188 skge_write32(hw, SK_REG(port, GPHY_CTRL), 189 GPC_DIS_SLEEP | 190 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 | 191 GPC_ANEG_1 | GPC_RST_CLR); 192 193 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 194 195 /* Force to 10/100 skge_reset will re-enable on resume */ 196 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, 197 (PHY_AN_100FULL | PHY_AN_100HALF | 198 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA)); 199 /* no 1000 HD/FD */ 200 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0); 201 gm_phy_write(hw, port, PHY_MARV_CTRL, 202 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE | 203 PHY_CT_RE_CFG | PHY_CT_DUP_MD); 204 205 206 /* Set GMAC to no flow control and auto update for speed/duplex */ 207 gma_write16(hw, port, GM_GP_CTRL, 208 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 209 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 210 211 /* Set WOL address */ 212 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 213 skge->netdev->dev_addr, ETH_ALEN); 214 215 /* Turn on appropriate WOL control bits */ 216 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 217 ctrl = 0; 218 if (skge->wol & WAKE_PHY) 219 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 220 else 221 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 222 223 if (skge->wol & WAKE_MAGIC) 224 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 225 else 226 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 227 228 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 229 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 230 231 /* block receiver */ 232 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 233 } 234 235 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 236 { 237 struct skge_port *skge = netdev_priv(dev); 238 239 wol->supported = wol_supported(skge->hw); 240 wol->wolopts = skge->wol; 241 } 242 243 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 244 { 245 struct skge_port *skge = netdev_priv(dev); 246 struct skge_hw *hw = skge->hw; 247 248 if ((wol->wolopts & ~wol_supported(hw)) || 249 !device_can_wakeup(&hw->pdev->dev)) 250 return -EOPNOTSUPP; 251 252 skge->wol = wol->wolopts; 253 254 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); 255 256 return 0; 257 } 258 259 /* Determine supported/advertised modes based on hardware. 260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx 261 */ 262 static u32 skge_supported_modes(const struct skge_hw *hw) 263 { 264 u32 supported; 265 266 if (hw->copper) { 267 supported = (SUPPORTED_10baseT_Half | 268 SUPPORTED_10baseT_Full | 269 SUPPORTED_100baseT_Half | 270 SUPPORTED_100baseT_Full | 271 SUPPORTED_1000baseT_Half | 272 SUPPORTED_1000baseT_Full | 273 SUPPORTED_Autoneg | 274 SUPPORTED_TP); 275 276 if (is_genesis(hw)) 277 supported &= ~(SUPPORTED_10baseT_Half | 278 SUPPORTED_10baseT_Full | 279 SUPPORTED_100baseT_Half | 280 SUPPORTED_100baseT_Full); 281 282 else if (hw->chip_id == CHIP_ID_YUKON) 283 supported &= ~SUPPORTED_1000baseT_Half; 284 } else 285 supported = (SUPPORTED_1000baseT_Full | 286 SUPPORTED_1000baseT_Half | 287 SUPPORTED_FIBRE | 288 SUPPORTED_Autoneg); 289 290 return supported; 291 } 292 293 static int skge_get_link_ksettings(struct net_device *dev, 294 struct ethtool_link_ksettings *cmd) 295 { 296 struct skge_port *skge = netdev_priv(dev); 297 struct skge_hw *hw = skge->hw; 298 u32 supported, advertising; 299 300 supported = skge_supported_modes(hw); 301 302 if (hw->copper) { 303 cmd->base.port = PORT_TP; 304 cmd->base.phy_address = hw->phy_addr; 305 } else 306 cmd->base.port = PORT_FIBRE; 307 308 advertising = skge->advertising; 309 cmd->base.autoneg = skge->autoneg; 310 cmd->base.speed = skge->speed; 311 cmd->base.duplex = skge->duplex; 312 313 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 314 supported); 315 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 316 advertising); 317 318 return 0; 319 } 320 321 static int skge_set_link_ksettings(struct net_device *dev, 322 const struct ethtool_link_ksettings *cmd) 323 { 324 struct skge_port *skge = netdev_priv(dev); 325 const struct skge_hw *hw = skge->hw; 326 u32 supported = skge_supported_modes(hw); 327 int err = 0; 328 u32 advertising; 329 330 ethtool_convert_link_mode_to_legacy_u32(&advertising, 331 cmd->link_modes.advertising); 332 333 if (cmd->base.autoneg == AUTONEG_ENABLE) { 334 advertising = supported; 335 skge->duplex = -1; 336 skge->speed = -1; 337 } else { 338 u32 setting; 339 u32 speed = cmd->base.speed; 340 341 switch (speed) { 342 case SPEED_1000: 343 if (cmd->base.duplex == DUPLEX_FULL) 344 setting = SUPPORTED_1000baseT_Full; 345 else if (cmd->base.duplex == DUPLEX_HALF) 346 setting = SUPPORTED_1000baseT_Half; 347 else 348 return -EINVAL; 349 break; 350 case SPEED_100: 351 if (cmd->base.duplex == DUPLEX_FULL) 352 setting = SUPPORTED_100baseT_Full; 353 else if (cmd->base.duplex == DUPLEX_HALF) 354 setting = SUPPORTED_100baseT_Half; 355 else 356 return -EINVAL; 357 break; 358 359 case SPEED_10: 360 if (cmd->base.duplex == DUPLEX_FULL) 361 setting = SUPPORTED_10baseT_Full; 362 else if (cmd->base.duplex == DUPLEX_HALF) 363 setting = SUPPORTED_10baseT_Half; 364 else 365 return -EINVAL; 366 break; 367 default: 368 return -EINVAL; 369 } 370 371 if ((setting & supported) == 0) 372 return -EINVAL; 373 374 skge->speed = speed; 375 skge->duplex = cmd->base.duplex; 376 } 377 378 skge->autoneg = cmd->base.autoneg; 379 skge->advertising = advertising; 380 381 if (netif_running(dev)) { 382 skge_down(dev); 383 err = skge_up(dev); 384 if (err) { 385 dev_close(dev); 386 return err; 387 } 388 } 389 390 return 0; 391 } 392 393 static void skge_get_drvinfo(struct net_device *dev, 394 struct ethtool_drvinfo *info) 395 { 396 struct skge_port *skge = netdev_priv(dev); 397 398 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 399 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 400 strlcpy(info->bus_info, pci_name(skge->hw->pdev), 401 sizeof(info->bus_info)); 402 } 403 404 static const struct skge_stat { 405 char name[ETH_GSTRING_LEN]; 406 u16 xmac_offset; 407 u16 gma_offset; 408 } skge_stats[] = { 409 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI }, 410 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI }, 411 412 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK }, 413 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK }, 414 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK }, 415 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK }, 416 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK }, 417 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK }, 418 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE }, 419 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE }, 420 421 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL }, 422 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL }, 423 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL }, 424 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL }, 425 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR }, 426 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV }, 427 428 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, 429 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT }, 430 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG }, 431 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, 432 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR }, 433 }; 434 435 static int skge_get_sset_count(struct net_device *dev, int sset) 436 { 437 switch (sset) { 438 case ETH_SS_STATS: 439 return ARRAY_SIZE(skge_stats); 440 default: 441 return -EOPNOTSUPP; 442 } 443 } 444 445 static void skge_get_ethtool_stats(struct net_device *dev, 446 struct ethtool_stats *stats, u64 *data) 447 { 448 struct skge_port *skge = netdev_priv(dev); 449 450 if (is_genesis(skge->hw)) 451 genesis_get_stats(skge, data); 452 else 453 yukon_get_stats(skge, data); 454 } 455 456 /* Use hardware MIB variables for critical path statistics and 457 * transmit feedback not reported at interrupt. 458 * Other errors are accounted for in interrupt handler. 459 */ 460 static struct net_device_stats *skge_get_stats(struct net_device *dev) 461 { 462 struct skge_port *skge = netdev_priv(dev); 463 u64 data[ARRAY_SIZE(skge_stats)]; 464 465 if (is_genesis(skge->hw)) 466 genesis_get_stats(skge, data); 467 else 468 yukon_get_stats(skge, data); 469 470 dev->stats.tx_bytes = data[0]; 471 dev->stats.rx_bytes = data[1]; 472 dev->stats.tx_packets = data[2] + data[4] + data[6]; 473 dev->stats.rx_packets = data[3] + data[5] + data[7]; 474 dev->stats.multicast = data[3] + data[5]; 475 dev->stats.collisions = data[10]; 476 dev->stats.tx_aborted_errors = data[12]; 477 478 return &dev->stats; 479 } 480 481 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data) 482 { 483 int i; 484 485 switch (stringset) { 486 case ETH_SS_STATS: 487 for (i = 0; i < ARRAY_SIZE(skge_stats); i++) 488 memcpy(data + i * ETH_GSTRING_LEN, 489 skge_stats[i].name, ETH_GSTRING_LEN); 490 break; 491 } 492 } 493 494 static void skge_get_ring_param(struct net_device *dev, 495 struct ethtool_ringparam *p) 496 { 497 struct skge_port *skge = netdev_priv(dev); 498 499 p->rx_max_pending = MAX_RX_RING_SIZE; 500 p->tx_max_pending = MAX_TX_RING_SIZE; 501 502 p->rx_pending = skge->rx_ring.count; 503 p->tx_pending = skge->tx_ring.count; 504 } 505 506 static int skge_set_ring_param(struct net_device *dev, 507 struct ethtool_ringparam *p) 508 { 509 struct skge_port *skge = netdev_priv(dev); 510 int err = 0; 511 512 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE || 513 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE) 514 return -EINVAL; 515 516 skge->rx_ring.count = p->rx_pending; 517 skge->tx_ring.count = p->tx_pending; 518 519 if (netif_running(dev)) { 520 skge_down(dev); 521 err = skge_up(dev); 522 if (err) 523 dev_close(dev); 524 } 525 526 return err; 527 } 528 529 static u32 skge_get_msglevel(struct net_device *netdev) 530 { 531 struct skge_port *skge = netdev_priv(netdev); 532 return skge->msg_enable; 533 } 534 535 static void skge_set_msglevel(struct net_device *netdev, u32 value) 536 { 537 struct skge_port *skge = netdev_priv(netdev); 538 skge->msg_enable = value; 539 } 540 541 static int skge_nway_reset(struct net_device *dev) 542 { 543 struct skge_port *skge = netdev_priv(dev); 544 545 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev)) 546 return -EINVAL; 547 548 skge_phy_reset(skge); 549 return 0; 550 } 551 552 static void skge_get_pauseparam(struct net_device *dev, 553 struct ethtool_pauseparam *ecmd) 554 { 555 struct skge_port *skge = netdev_priv(dev); 556 557 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) || 558 (skge->flow_control == FLOW_MODE_SYM_OR_REM)); 559 ecmd->tx_pause = (ecmd->rx_pause || 560 (skge->flow_control == FLOW_MODE_LOC_SEND)); 561 562 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause; 563 } 564 565 static int skge_set_pauseparam(struct net_device *dev, 566 struct ethtool_pauseparam *ecmd) 567 { 568 struct skge_port *skge = netdev_priv(dev); 569 struct ethtool_pauseparam old; 570 int err = 0; 571 572 skge_get_pauseparam(dev, &old); 573 574 if (ecmd->autoneg != old.autoneg) 575 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC; 576 else { 577 if (ecmd->rx_pause && ecmd->tx_pause) 578 skge->flow_control = FLOW_MODE_SYMMETRIC; 579 else if (ecmd->rx_pause && !ecmd->tx_pause) 580 skge->flow_control = FLOW_MODE_SYM_OR_REM; 581 else if (!ecmd->rx_pause && ecmd->tx_pause) 582 skge->flow_control = FLOW_MODE_LOC_SEND; 583 else 584 skge->flow_control = FLOW_MODE_NONE; 585 } 586 587 if (netif_running(dev)) { 588 skge_down(dev); 589 err = skge_up(dev); 590 if (err) { 591 dev_close(dev); 592 return err; 593 } 594 } 595 596 return 0; 597 } 598 599 /* Chip internal frequency for clock calculations */ 600 static inline u32 hwkhz(const struct skge_hw *hw) 601 { 602 return is_genesis(hw) ? 53125 : 78125; 603 } 604 605 /* Chip HZ to microseconds */ 606 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) 607 { 608 return (ticks * 1000) / hwkhz(hw); 609 } 610 611 /* Microseconds to chip HZ */ 612 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) 613 { 614 return hwkhz(hw) * usec / 1000; 615 } 616 617 static int skge_get_coalesce(struct net_device *dev, 618 struct ethtool_coalesce *ecmd) 619 { 620 struct skge_port *skge = netdev_priv(dev); 621 struct skge_hw *hw = skge->hw; 622 int port = skge->port; 623 624 ecmd->rx_coalesce_usecs = 0; 625 ecmd->tx_coalesce_usecs = 0; 626 627 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { 628 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); 629 u32 msk = skge_read32(hw, B2_IRQM_MSK); 630 631 if (msk & rxirqmask[port]) 632 ecmd->rx_coalesce_usecs = delay; 633 if (msk & txirqmask[port]) 634 ecmd->tx_coalesce_usecs = delay; 635 } 636 637 return 0; 638 } 639 640 /* Note: interrupt timer is per board, but can turn on/off per port */ 641 static int skge_set_coalesce(struct net_device *dev, 642 struct ethtool_coalesce *ecmd) 643 { 644 struct skge_port *skge = netdev_priv(dev); 645 struct skge_hw *hw = skge->hw; 646 int port = skge->port; 647 u32 msk = skge_read32(hw, B2_IRQM_MSK); 648 u32 delay = 25; 649 650 if (ecmd->rx_coalesce_usecs == 0) 651 msk &= ~rxirqmask[port]; 652 else if (ecmd->rx_coalesce_usecs < 25 || 653 ecmd->rx_coalesce_usecs > 33333) 654 return -EINVAL; 655 else { 656 msk |= rxirqmask[port]; 657 delay = ecmd->rx_coalesce_usecs; 658 } 659 660 if (ecmd->tx_coalesce_usecs == 0) 661 msk &= ~txirqmask[port]; 662 else if (ecmd->tx_coalesce_usecs < 25 || 663 ecmd->tx_coalesce_usecs > 33333) 664 return -EINVAL; 665 else { 666 msk |= txirqmask[port]; 667 delay = min(delay, ecmd->rx_coalesce_usecs); 668 } 669 670 skge_write32(hw, B2_IRQM_MSK, msk); 671 if (msk == 0) 672 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); 673 else { 674 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); 675 skge_write32(hw, B2_IRQM_CTRL, TIM_START); 676 } 677 return 0; 678 } 679 680 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST }; 681 static void skge_led(struct skge_port *skge, enum led_mode mode) 682 { 683 struct skge_hw *hw = skge->hw; 684 int port = skge->port; 685 686 spin_lock_bh(&hw->phy_lock); 687 if (is_genesis(hw)) { 688 switch (mode) { 689 case LED_MODE_OFF: 690 if (hw->phy_type == SK_PHY_BCOM) 691 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); 692 else { 693 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); 694 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); 695 } 696 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 697 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); 698 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); 699 break; 700 701 case LED_MODE_ON: 702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); 703 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); 704 705 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); 706 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); 707 708 break; 709 710 case LED_MODE_TST: 711 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); 712 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); 713 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); 714 715 if (hw->phy_type == SK_PHY_BCOM) 716 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); 717 else { 718 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); 719 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); 720 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); 721 } 722 723 } 724 } else { 725 switch (mode) { 726 case LED_MODE_OFF: 727 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 728 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 729 PHY_M_LED_MO_DUP(MO_LED_OFF) | 730 PHY_M_LED_MO_10(MO_LED_OFF) | 731 PHY_M_LED_MO_100(MO_LED_OFF) | 732 PHY_M_LED_MO_1000(MO_LED_OFF) | 733 PHY_M_LED_MO_RX(MO_LED_OFF)); 734 break; 735 case LED_MODE_ON: 736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 737 PHY_M_LED_PULS_DUR(PULS_170MS) | 738 PHY_M_LED_BLINK_RT(BLINK_84MS) | 739 PHY_M_LEDC_TX_CTRL | 740 PHY_M_LEDC_DP_CTRL); 741 742 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 743 PHY_M_LED_MO_RX(MO_LED_OFF) | 744 (skge->speed == SPEED_100 ? 745 PHY_M_LED_MO_100(MO_LED_ON) : 0)); 746 break; 747 case LED_MODE_TST: 748 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 749 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 750 PHY_M_LED_MO_DUP(MO_LED_ON) | 751 PHY_M_LED_MO_10(MO_LED_ON) | 752 PHY_M_LED_MO_100(MO_LED_ON) | 753 PHY_M_LED_MO_1000(MO_LED_ON) | 754 PHY_M_LED_MO_RX(MO_LED_ON)); 755 } 756 } 757 spin_unlock_bh(&hw->phy_lock); 758 } 759 760 /* blink LED's for finding board */ 761 static int skge_set_phys_id(struct net_device *dev, 762 enum ethtool_phys_id_state state) 763 { 764 struct skge_port *skge = netdev_priv(dev); 765 766 switch (state) { 767 case ETHTOOL_ID_ACTIVE: 768 return 2; /* cycle on/off twice per second */ 769 770 case ETHTOOL_ID_ON: 771 skge_led(skge, LED_MODE_TST); 772 break; 773 774 case ETHTOOL_ID_OFF: 775 skge_led(skge, LED_MODE_OFF); 776 break; 777 778 case ETHTOOL_ID_INACTIVE: 779 /* back to regular LED state */ 780 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF); 781 } 782 783 return 0; 784 } 785 786 static int skge_get_eeprom_len(struct net_device *dev) 787 { 788 struct skge_port *skge = netdev_priv(dev); 789 u32 reg2; 790 791 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2); 792 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 793 } 794 795 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset) 796 { 797 u32 val; 798 799 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset); 800 801 do { 802 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); 803 } while (!(offset & PCI_VPD_ADDR_F)); 804 805 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val); 806 return val; 807 } 808 809 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val) 810 { 811 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val); 812 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, 813 offset | PCI_VPD_ADDR_F); 814 815 do { 816 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); 817 } while (offset & PCI_VPD_ADDR_F); 818 } 819 820 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 821 u8 *data) 822 { 823 struct skge_port *skge = netdev_priv(dev); 824 struct pci_dev *pdev = skge->hw->pdev; 825 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD); 826 int length = eeprom->len; 827 u16 offset = eeprom->offset; 828 829 if (!cap) 830 return -EINVAL; 831 832 eeprom->magic = SKGE_EEPROM_MAGIC; 833 834 while (length > 0) { 835 u32 val = skge_vpd_read(pdev, cap, offset); 836 int n = min_t(int, length, sizeof(val)); 837 838 memcpy(data, &val, n); 839 length -= n; 840 data += n; 841 offset += n; 842 } 843 return 0; 844 } 845 846 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 847 u8 *data) 848 { 849 struct skge_port *skge = netdev_priv(dev); 850 struct pci_dev *pdev = skge->hw->pdev; 851 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD); 852 int length = eeprom->len; 853 u16 offset = eeprom->offset; 854 855 if (!cap) 856 return -EINVAL; 857 858 if (eeprom->magic != SKGE_EEPROM_MAGIC) 859 return -EINVAL; 860 861 while (length > 0) { 862 u32 val; 863 int n = min_t(int, length, sizeof(val)); 864 865 if (n < sizeof(val)) 866 val = skge_vpd_read(pdev, cap, offset); 867 memcpy(&val, data, n); 868 869 skge_vpd_write(pdev, cap, offset, val); 870 871 length -= n; 872 data += n; 873 offset += n; 874 } 875 return 0; 876 } 877 878 static const struct ethtool_ops skge_ethtool_ops = { 879 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 880 .get_drvinfo = skge_get_drvinfo, 881 .get_regs_len = skge_get_regs_len, 882 .get_regs = skge_get_regs, 883 .get_wol = skge_get_wol, 884 .set_wol = skge_set_wol, 885 .get_msglevel = skge_get_msglevel, 886 .set_msglevel = skge_set_msglevel, 887 .nway_reset = skge_nway_reset, 888 .get_link = ethtool_op_get_link, 889 .get_eeprom_len = skge_get_eeprom_len, 890 .get_eeprom = skge_get_eeprom, 891 .set_eeprom = skge_set_eeprom, 892 .get_ringparam = skge_get_ring_param, 893 .set_ringparam = skge_set_ring_param, 894 .get_pauseparam = skge_get_pauseparam, 895 .set_pauseparam = skge_set_pauseparam, 896 .get_coalesce = skge_get_coalesce, 897 .set_coalesce = skge_set_coalesce, 898 .get_strings = skge_get_strings, 899 .set_phys_id = skge_set_phys_id, 900 .get_sset_count = skge_get_sset_count, 901 .get_ethtool_stats = skge_get_ethtool_stats, 902 .get_link_ksettings = skge_get_link_ksettings, 903 .set_link_ksettings = skge_set_link_ksettings, 904 }; 905 906 /* 907 * Allocate ring elements and chain them together 908 * One-to-one association of board descriptors with ring elements 909 */ 910 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base) 911 { 912 struct skge_tx_desc *d; 913 struct skge_element *e; 914 int i; 915 916 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL); 917 if (!ring->start) 918 return -ENOMEM; 919 920 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { 921 e->desc = d; 922 if (i == ring->count - 1) { 923 e->next = ring->start; 924 d->next_offset = base; 925 } else { 926 e->next = e + 1; 927 d->next_offset = base + (i+1) * sizeof(*d); 928 } 929 } 930 ring->to_use = ring->to_clean = ring->start; 931 932 return 0; 933 } 934 935 /* Allocate and setup a new buffer for receiving */ 936 static int skge_rx_setup(struct skge_port *skge, struct skge_element *e, 937 struct sk_buff *skb, unsigned int bufsize) 938 { 939 struct skge_rx_desc *rd = e->desc; 940 dma_addr_t map; 941 942 map = dma_map_single(&skge->hw->pdev->dev, skb->data, bufsize, 943 DMA_FROM_DEVICE); 944 945 if (dma_mapping_error(&skge->hw->pdev->dev, map)) 946 return -1; 947 948 rd->dma_lo = lower_32_bits(map); 949 rd->dma_hi = upper_32_bits(map); 950 e->skb = skb; 951 rd->csum1_start = ETH_HLEN; 952 rd->csum2_start = ETH_HLEN; 953 rd->csum1 = 0; 954 rd->csum2 = 0; 955 956 wmb(); 957 958 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize; 959 dma_unmap_addr_set(e, mapaddr, map); 960 dma_unmap_len_set(e, maplen, bufsize); 961 return 0; 962 } 963 964 /* Resume receiving using existing skb, 965 * Note: DMA address is not changed by chip. 966 * MTU not changed while receiver active. 967 */ 968 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size) 969 { 970 struct skge_rx_desc *rd = e->desc; 971 972 rd->csum2 = 0; 973 rd->csum2_start = ETH_HLEN; 974 975 wmb(); 976 977 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size; 978 } 979 980 981 /* Free all buffers in receive ring, assumes receiver stopped */ 982 static void skge_rx_clean(struct skge_port *skge) 983 { 984 struct skge_hw *hw = skge->hw; 985 struct skge_ring *ring = &skge->rx_ring; 986 struct skge_element *e; 987 988 e = ring->start; 989 do { 990 struct skge_rx_desc *rd = e->desc; 991 rd->control = 0; 992 if (e->skb) { 993 dma_unmap_single(&hw->pdev->dev, 994 dma_unmap_addr(e, mapaddr), 995 dma_unmap_len(e, maplen), 996 DMA_FROM_DEVICE); 997 dev_kfree_skb(e->skb); 998 e->skb = NULL; 999 } 1000 } while ((e = e->next) != ring->start); 1001 } 1002 1003 1004 /* Allocate buffers for receive ring 1005 * For receive: to_clean is next received frame. 1006 */ 1007 static int skge_rx_fill(struct net_device *dev) 1008 { 1009 struct skge_port *skge = netdev_priv(dev); 1010 struct skge_ring *ring = &skge->rx_ring; 1011 struct skge_element *e; 1012 1013 e = ring->start; 1014 do { 1015 struct sk_buff *skb; 1016 1017 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN, 1018 GFP_KERNEL); 1019 if (!skb) 1020 return -ENOMEM; 1021 1022 skb_reserve(skb, NET_IP_ALIGN); 1023 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) { 1024 dev_kfree_skb(skb); 1025 return -EIO; 1026 } 1027 } while ((e = e->next) != ring->start); 1028 1029 ring->to_clean = ring->start; 1030 return 0; 1031 } 1032 1033 static const char *skge_pause(enum pause_status status) 1034 { 1035 switch (status) { 1036 case FLOW_STAT_NONE: 1037 return "none"; 1038 case FLOW_STAT_REM_SEND: 1039 return "rx only"; 1040 case FLOW_STAT_LOC_SEND: 1041 return "tx_only"; 1042 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */ 1043 return "both"; 1044 default: 1045 return "indeterminated"; 1046 } 1047 } 1048 1049 1050 static void skge_link_up(struct skge_port *skge) 1051 { 1052 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), 1053 LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON); 1054 1055 netif_carrier_on(skge->netdev); 1056 netif_wake_queue(skge->netdev); 1057 1058 netif_info(skge, link, skge->netdev, 1059 "Link is up at %d Mbps, %s duplex, flow control %s\n", 1060 skge->speed, 1061 skge->duplex == DUPLEX_FULL ? "full" : "half", 1062 skge_pause(skge->flow_status)); 1063 } 1064 1065 static void skge_link_down(struct skge_port *skge) 1066 { 1067 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF); 1068 netif_carrier_off(skge->netdev); 1069 netif_stop_queue(skge->netdev); 1070 1071 netif_info(skge, link, skge->netdev, "Link is down\n"); 1072 } 1073 1074 static void xm_link_down(struct skge_hw *hw, int port) 1075 { 1076 struct net_device *dev = hw->dev[port]; 1077 struct skge_port *skge = netdev_priv(dev); 1078 1079 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); 1080 1081 if (netif_carrier_ok(dev)) 1082 skge_link_down(skge); 1083 } 1084 1085 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) 1086 { 1087 int i; 1088 1089 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 1090 *val = xm_read16(hw, port, XM_PHY_DATA); 1091 1092 if (hw->phy_type == SK_PHY_XMAC) 1093 goto ready; 1094 1095 for (i = 0; i < PHY_RETRIES; i++) { 1096 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) 1097 goto ready; 1098 udelay(1); 1099 } 1100 1101 return -ETIMEDOUT; 1102 ready: 1103 *val = xm_read16(hw, port, XM_PHY_DATA); 1104 1105 return 0; 1106 } 1107 1108 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) 1109 { 1110 u16 v = 0; 1111 if (__xm_phy_read(hw, port, reg, &v)) 1112 pr_warn("%s: phy read timed out\n", hw->dev[port]->name); 1113 return v; 1114 } 1115 1116 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) 1117 { 1118 int i; 1119 1120 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 1121 for (i = 0; i < PHY_RETRIES; i++) { 1122 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 1123 goto ready; 1124 udelay(1); 1125 } 1126 return -EIO; 1127 1128 ready: 1129 xm_write16(hw, port, XM_PHY_DATA, val); 1130 for (i = 0; i < PHY_RETRIES; i++) { 1131 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 1132 return 0; 1133 udelay(1); 1134 } 1135 return -ETIMEDOUT; 1136 } 1137 1138 static void genesis_init(struct skge_hw *hw) 1139 { 1140 /* set blink source counter */ 1141 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); 1142 skge_write8(hw, B2_BSC_CTRL, BSC_START); 1143 1144 /* configure mac arbiter */ 1145 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); 1146 1147 /* configure mac arbiter timeout values */ 1148 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); 1149 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); 1150 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); 1151 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); 1152 1153 skge_write8(hw, B3_MA_RCINI_RX1, 0); 1154 skge_write8(hw, B3_MA_RCINI_RX2, 0); 1155 skge_write8(hw, B3_MA_RCINI_TX1, 0); 1156 skge_write8(hw, B3_MA_RCINI_TX2, 0); 1157 1158 /* configure packet arbiter timeout */ 1159 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); 1160 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); 1161 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); 1162 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); 1163 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); 1164 } 1165 1166 static void genesis_reset(struct skge_hw *hw, int port) 1167 { 1168 static const u8 zero[8] = { 0 }; 1169 u32 reg; 1170 1171 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 1172 1173 /* reset the statistics module */ 1174 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); 1175 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); 1176 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ 1177 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ 1178 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ 1179 1180 /* disable Broadcom PHY IRQ */ 1181 if (hw->phy_type == SK_PHY_BCOM) 1182 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); 1183 1184 xm_outhash(hw, port, XM_HSM, zero); 1185 1186 /* Flush TX and RX fifo */ 1187 reg = xm_read32(hw, port, XM_MODE); 1188 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF); 1189 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); 1190 } 1191 1192 /* Convert mode to MII values */ 1193 static const u16 phy_pause_map[] = { 1194 [FLOW_MODE_NONE] = 0, 1195 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM, 1196 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP, 1197 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM, 1198 }; 1199 1200 /* special defines for FIBER (88E1011S only) */ 1201 static const u16 fiber_pause_map[] = { 1202 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE, 1203 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD, 1204 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD, 1205 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD, 1206 }; 1207 1208 1209 /* Check status of Broadcom phy link */ 1210 static void bcom_check_link(struct skge_hw *hw, int port) 1211 { 1212 struct net_device *dev = hw->dev[port]; 1213 struct skge_port *skge = netdev_priv(dev); 1214 u16 status; 1215 1216 /* read twice because of latch */ 1217 xm_phy_read(hw, port, PHY_BCOM_STAT); 1218 status = xm_phy_read(hw, port, PHY_BCOM_STAT); 1219 1220 if ((status & PHY_ST_LSYNC) == 0) { 1221 xm_link_down(hw, port); 1222 return; 1223 } 1224 1225 if (skge->autoneg == AUTONEG_ENABLE) { 1226 u16 lpa, aux; 1227 1228 if (!(status & PHY_ST_AN_OVER)) 1229 return; 1230 1231 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); 1232 if (lpa & PHY_B_AN_RF) { 1233 netdev_notice(dev, "remote fault\n"); 1234 return; 1235 } 1236 1237 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); 1238 1239 /* Check Duplex mismatch */ 1240 switch (aux & PHY_B_AS_AN_RES_MSK) { 1241 case PHY_B_RES_1000FD: 1242 skge->duplex = DUPLEX_FULL; 1243 break; 1244 case PHY_B_RES_1000HD: 1245 skge->duplex = DUPLEX_HALF; 1246 break; 1247 default: 1248 netdev_notice(dev, "duplex mismatch\n"); 1249 return; 1250 } 1251 1252 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 1253 switch (aux & PHY_B_AS_PAUSE_MSK) { 1254 case PHY_B_AS_PAUSE_MSK: 1255 skge->flow_status = FLOW_STAT_SYMMETRIC; 1256 break; 1257 case PHY_B_AS_PRR: 1258 skge->flow_status = FLOW_STAT_REM_SEND; 1259 break; 1260 case PHY_B_AS_PRT: 1261 skge->flow_status = FLOW_STAT_LOC_SEND; 1262 break; 1263 default: 1264 skge->flow_status = FLOW_STAT_NONE; 1265 } 1266 skge->speed = SPEED_1000; 1267 } 1268 1269 if (!netif_carrier_ok(dev)) 1270 genesis_link_up(skge); 1271 } 1272 1273 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional 1274 * Phy on for 100 or 10Mbit operation 1275 */ 1276 static void bcom_phy_init(struct skge_port *skge) 1277 { 1278 struct skge_hw *hw = skge->hw; 1279 int port = skge->port; 1280 int i; 1281 u16 id1, r, ext, ctl; 1282 1283 /* magic workaround patterns for Broadcom */ 1284 static const struct { 1285 u16 reg; 1286 u16 val; 1287 } A1hack[] = { 1288 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, 1289 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, 1290 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, 1291 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1292 }, C0hack[] = { 1293 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, 1294 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, 1295 }; 1296 1297 /* read Id from external PHY (all have the same address) */ 1298 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); 1299 1300 /* Optimize MDIO transfer by suppressing preamble. */ 1301 r = xm_read16(hw, port, XM_MMU_CMD); 1302 r |= XM_MMU_NO_PRE; 1303 xm_write16(hw, port, XM_MMU_CMD, r); 1304 1305 switch (id1) { 1306 case PHY_BCOM_ID1_C0: 1307 /* 1308 * Workaround BCOM Errata for the C0 type. 1309 * Write magic patterns to reserved registers. 1310 */ 1311 for (i = 0; i < ARRAY_SIZE(C0hack); i++) 1312 xm_phy_write(hw, port, 1313 C0hack[i].reg, C0hack[i].val); 1314 1315 break; 1316 case PHY_BCOM_ID1_A1: 1317 /* 1318 * Workaround BCOM Errata for the A1 type. 1319 * Write magic patterns to reserved registers. 1320 */ 1321 for (i = 0; i < ARRAY_SIZE(A1hack); i++) 1322 xm_phy_write(hw, port, 1323 A1hack[i].reg, A1hack[i].val); 1324 break; 1325 } 1326 1327 /* 1328 * Workaround BCOM Errata (#10523) for all BCom PHYs. 1329 * Disable Power Management after reset. 1330 */ 1331 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); 1332 r |= PHY_B_AC_DIS_PM; 1333 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); 1334 1335 /* Dummy read */ 1336 xm_read16(hw, port, XM_ISRC); 1337 1338 ext = PHY_B_PEC_EN_LTR; /* enable tx led */ 1339 ctl = PHY_CT_SP1000; /* always 1000mbit */ 1340 1341 if (skge->autoneg == AUTONEG_ENABLE) { 1342 /* 1343 * Workaround BCOM Errata #1 for the C5 type. 1344 * 1000Base-T Link Acquisition Failure in Slave Mode 1345 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register 1346 */ 1347 u16 adv = PHY_B_1000C_RD; 1348 if (skge->advertising & ADVERTISED_1000baseT_Half) 1349 adv |= PHY_B_1000C_AHD; 1350 if (skge->advertising & ADVERTISED_1000baseT_Full) 1351 adv |= PHY_B_1000C_AFD; 1352 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); 1353 1354 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG; 1355 } else { 1356 if (skge->duplex == DUPLEX_FULL) 1357 ctl |= PHY_CT_DUP_MD; 1358 /* Force to slave */ 1359 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); 1360 } 1361 1362 /* Set autonegotiation pause parameters */ 1363 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, 1364 phy_pause_map[skge->flow_control] | PHY_AN_CSMA); 1365 1366 /* Handle Jumbo frames */ 1367 if (hw->dev[port]->mtu > ETH_DATA_LEN) { 1368 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 1369 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK); 1370 1371 ext |= PHY_B_PEC_HIGH_LA; 1372 1373 } 1374 1375 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); 1376 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); 1377 1378 /* Use link status change interrupt */ 1379 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 1380 } 1381 1382 static void xm_phy_init(struct skge_port *skge) 1383 { 1384 struct skge_hw *hw = skge->hw; 1385 int port = skge->port; 1386 u16 ctrl = 0; 1387 1388 if (skge->autoneg == AUTONEG_ENABLE) { 1389 if (skge->advertising & ADVERTISED_1000baseT_Half) 1390 ctrl |= PHY_X_AN_HD; 1391 if (skge->advertising & ADVERTISED_1000baseT_Full) 1392 ctrl |= PHY_X_AN_FD; 1393 1394 ctrl |= fiber_pause_map[skge->flow_control]; 1395 1396 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); 1397 1398 /* Restart Auto-negotiation */ 1399 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG; 1400 } else { 1401 /* Set DuplexMode in Config register */ 1402 if (skge->duplex == DUPLEX_FULL) 1403 ctrl |= PHY_CT_DUP_MD; 1404 /* 1405 * Do NOT enable Auto-negotiation here. This would hold 1406 * the link down because no IDLEs are transmitted 1407 */ 1408 } 1409 1410 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); 1411 1412 /* Poll PHY for status changes */ 1413 mod_timer(&skge->link_timer, jiffies + LINK_HZ); 1414 } 1415 1416 static int xm_check_link(struct net_device *dev) 1417 { 1418 struct skge_port *skge = netdev_priv(dev); 1419 struct skge_hw *hw = skge->hw; 1420 int port = skge->port; 1421 u16 status; 1422 1423 /* read twice because of latch */ 1424 xm_phy_read(hw, port, PHY_XMAC_STAT); 1425 status = xm_phy_read(hw, port, PHY_XMAC_STAT); 1426 1427 if ((status & PHY_ST_LSYNC) == 0) { 1428 xm_link_down(hw, port); 1429 return 0; 1430 } 1431 1432 if (skge->autoneg == AUTONEG_ENABLE) { 1433 u16 lpa, res; 1434 1435 if (!(status & PHY_ST_AN_OVER)) 1436 return 0; 1437 1438 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); 1439 if (lpa & PHY_B_AN_RF) { 1440 netdev_notice(dev, "remote fault\n"); 1441 return 0; 1442 } 1443 1444 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); 1445 1446 /* Check Duplex mismatch */ 1447 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) { 1448 case PHY_X_RS_FD: 1449 skge->duplex = DUPLEX_FULL; 1450 break; 1451 case PHY_X_RS_HD: 1452 skge->duplex = DUPLEX_HALF; 1453 break; 1454 default: 1455 netdev_notice(dev, "duplex mismatch\n"); 1456 return 0; 1457 } 1458 1459 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 1460 if ((skge->flow_control == FLOW_MODE_SYMMETRIC || 1461 skge->flow_control == FLOW_MODE_SYM_OR_REM) && 1462 (lpa & PHY_X_P_SYM_MD)) 1463 skge->flow_status = FLOW_STAT_SYMMETRIC; 1464 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM && 1465 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) 1466 /* Enable PAUSE receive, disable PAUSE transmit */ 1467 skge->flow_status = FLOW_STAT_REM_SEND; 1468 else if (skge->flow_control == FLOW_MODE_LOC_SEND && 1469 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) 1470 /* Disable PAUSE receive, enable PAUSE transmit */ 1471 skge->flow_status = FLOW_STAT_LOC_SEND; 1472 else 1473 skge->flow_status = FLOW_STAT_NONE; 1474 1475 skge->speed = SPEED_1000; 1476 } 1477 1478 if (!netif_carrier_ok(dev)) 1479 genesis_link_up(skge); 1480 return 1; 1481 } 1482 1483 /* Poll to check for link coming up. 1484 * 1485 * Since internal PHY is wired to a level triggered pin, can't 1486 * get an interrupt when carrier is detected, need to poll for 1487 * link coming up. 1488 */ 1489 static void xm_link_timer(struct timer_list *t) 1490 { 1491 struct skge_port *skge = from_timer(skge, t, link_timer); 1492 struct net_device *dev = skge->netdev; 1493 struct skge_hw *hw = skge->hw; 1494 int port = skge->port; 1495 int i; 1496 unsigned long flags; 1497 1498 if (!netif_running(dev)) 1499 return; 1500 1501 spin_lock_irqsave(&hw->phy_lock, flags); 1502 1503 /* 1504 * Verify that the link by checking GPIO register three times. 1505 * This pin has the signal from the link_sync pin connected to it. 1506 */ 1507 for (i = 0; i < 3; i++) { 1508 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) 1509 goto link_down; 1510 } 1511 1512 /* Re-enable interrupt to detect link down */ 1513 if (xm_check_link(dev)) { 1514 u16 msk = xm_read16(hw, port, XM_IMSK); 1515 msk &= ~XM_IS_INP_ASS; 1516 xm_write16(hw, port, XM_IMSK, msk); 1517 xm_read16(hw, port, XM_ISRC); 1518 } else { 1519 link_down: 1520 mod_timer(&skge->link_timer, 1521 round_jiffies(jiffies + LINK_HZ)); 1522 } 1523 spin_unlock_irqrestore(&hw->phy_lock, flags); 1524 } 1525 1526 static void genesis_mac_init(struct skge_hw *hw, int port) 1527 { 1528 struct net_device *dev = hw->dev[port]; 1529 struct skge_port *skge = netdev_priv(dev); 1530 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; 1531 int i; 1532 u32 r; 1533 static const u8 zero[6] = { 0 }; 1534 1535 for (i = 0; i < 10; i++) { 1536 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), 1537 MFF_SET_MAC_RST); 1538 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) 1539 goto reset_ok; 1540 udelay(1); 1541 } 1542 1543 netdev_warn(dev, "genesis reset failed\n"); 1544 1545 reset_ok: 1546 /* Unreset the XMAC. */ 1547 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 1548 1549 /* 1550 * Perform additional initialization for external PHYs, 1551 * namely for the 1000baseTX cards that use the XMAC's 1552 * GMII mode. 1553 */ 1554 if (hw->phy_type != SK_PHY_XMAC) { 1555 /* Take external Phy out of reset */ 1556 r = skge_read32(hw, B2_GP_IO); 1557 if (port == 0) 1558 r |= GP_DIR_0|GP_IO_0; 1559 else 1560 r |= GP_DIR_2|GP_IO_2; 1561 1562 skge_write32(hw, B2_GP_IO, r); 1563 1564 /* Enable GMII interface */ 1565 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); 1566 } 1567 1568 1569 switch (hw->phy_type) { 1570 case SK_PHY_XMAC: 1571 xm_phy_init(skge); 1572 break; 1573 case SK_PHY_BCOM: 1574 bcom_phy_init(skge); 1575 bcom_check_link(hw, port); 1576 } 1577 1578 /* Set Station Address */ 1579 xm_outaddr(hw, port, XM_SA, dev->dev_addr); 1580 1581 /* We don't use match addresses so clear */ 1582 for (i = 1; i < 16; i++) 1583 xm_outaddr(hw, port, XM_EXM(i), zero); 1584 1585 /* Clear MIB counters */ 1586 xm_write16(hw, port, XM_STAT_CMD, 1587 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 1588 /* Clear two times according to Errata #3 */ 1589 xm_write16(hw, port, XM_STAT_CMD, 1590 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 1591 1592 /* configure Rx High Water Mark (XM_RX_HI_WM) */ 1593 xm_write16(hw, port, XM_RX_HI_WM, 1450); 1594 1595 /* We don't need the FCS appended to the packet. */ 1596 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS; 1597 if (jumbo) 1598 r |= XM_RX_BIG_PK_OK; 1599 1600 if (skge->duplex == DUPLEX_HALF) { 1601 /* 1602 * If in manual half duplex mode the other side might be in 1603 * full duplex mode, so ignore if a carrier extension is not seen 1604 * on frames received 1605 */ 1606 r |= XM_RX_DIS_CEXT; 1607 } 1608 xm_write16(hw, port, XM_RX_CMD, r); 1609 1610 /* We want short frames padded to 60 bytes. */ 1611 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); 1612 1613 /* Increase threshold for jumbo frames on dual port */ 1614 if (hw->ports > 1 && jumbo) 1615 xm_write16(hw, port, XM_TX_THR, 1020); 1616 else 1617 xm_write16(hw, port, XM_TX_THR, 512); 1618 1619 /* 1620 * Enable the reception of all error frames. This is 1621 * a necessary evil due to the design of the XMAC. The 1622 * XMAC's receive FIFO is only 8K in size, however jumbo 1623 * frames can be up to 9000 bytes in length. When bad 1624 * frame filtering is enabled, the XMAC's RX FIFO operates 1625 * in 'store and forward' mode. For this to work, the 1626 * entire frame has to fit into the FIFO, but that means 1627 * that jumbo frames larger than 8192 bytes will be 1628 * truncated. Disabling all bad frame filtering causes 1629 * the RX FIFO to operate in streaming mode, in which 1630 * case the XMAC will start transferring frames out of the 1631 * RX FIFO as soon as the FIFO threshold is reached. 1632 */ 1633 xm_write32(hw, port, XM_MODE, XM_DEF_MODE); 1634 1635 1636 /* 1637 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK) 1638 * - Enable all bits excepting 'Octets Rx OK Low CntOv' 1639 * and 'Octets Rx OK Hi Cnt Ov'. 1640 */ 1641 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); 1642 1643 /* 1644 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK) 1645 * - Enable all bits excepting 'Octets Tx OK Low CntOv' 1646 * and 'Octets Tx OK Hi Cnt Ov'. 1647 */ 1648 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); 1649 1650 /* Configure MAC arbiter */ 1651 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); 1652 1653 /* configure timeout values */ 1654 skge_write8(hw, B3_MA_TOINI_RX1, 72); 1655 skge_write8(hw, B3_MA_TOINI_RX2, 72); 1656 skge_write8(hw, B3_MA_TOINI_TX1, 72); 1657 skge_write8(hw, B3_MA_TOINI_TX2, 72); 1658 1659 skge_write8(hw, B3_MA_RCINI_RX1, 0); 1660 skge_write8(hw, B3_MA_RCINI_RX2, 0); 1661 skge_write8(hw, B3_MA_RCINI_TX1, 0); 1662 skge_write8(hw, B3_MA_RCINI_TX2, 0); 1663 1664 /* Configure Rx MAC FIFO */ 1665 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); 1666 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); 1667 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); 1668 1669 /* Configure Tx MAC FIFO */ 1670 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); 1671 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); 1672 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); 1673 1674 if (jumbo) { 1675 /* Enable frame flushing if jumbo frames used */ 1676 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH); 1677 } else { 1678 /* enable timeout timers if normal frames */ 1679 skge_write16(hw, B3_PA_CTRL, 1680 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); 1681 } 1682 } 1683 1684 static void genesis_stop(struct skge_port *skge) 1685 { 1686 struct skge_hw *hw = skge->hw; 1687 int port = skge->port; 1688 unsigned retries = 1000; 1689 u16 cmd; 1690 1691 /* Disable Tx and Rx */ 1692 cmd = xm_read16(hw, port, XM_MMU_CMD); 1693 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); 1694 xm_write16(hw, port, XM_MMU_CMD, cmd); 1695 1696 genesis_reset(hw, port); 1697 1698 /* Clear Tx packet arbiter timeout IRQ */ 1699 skge_write16(hw, B3_PA_CTRL, 1700 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); 1701 1702 /* Reset the MAC */ 1703 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 1704 do { 1705 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); 1706 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)) 1707 break; 1708 } while (--retries > 0); 1709 1710 /* For external PHYs there must be special handling */ 1711 if (hw->phy_type != SK_PHY_XMAC) { 1712 u32 reg = skge_read32(hw, B2_GP_IO); 1713 if (port == 0) { 1714 reg |= GP_DIR_0; 1715 reg &= ~GP_IO_0; 1716 } else { 1717 reg |= GP_DIR_2; 1718 reg &= ~GP_IO_2; 1719 } 1720 skge_write32(hw, B2_GP_IO, reg); 1721 skge_read32(hw, B2_GP_IO); 1722 } 1723 1724 xm_write16(hw, port, XM_MMU_CMD, 1725 xm_read16(hw, port, XM_MMU_CMD) 1726 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); 1727 1728 xm_read16(hw, port, XM_MMU_CMD); 1729 } 1730 1731 1732 static void genesis_get_stats(struct skge_port *skge, u64 *data) 1733 { 1734 struct skge_hw *hw = skge->hw; 1735 int port = skge->port; 1736 int i; 1737 unsigned long timeout = jiffies + HZ; 1738 1739 xm_write16(hw, port, 1740 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); 1741 1742 /* wait for update to complete */ 1743 while (xm_read16(hw, port, XM_STAT_CMD) 1744 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) { 1745 if (time_after(jiffies, timeout)) 1746 break; 1747 udelay(10); 1748 } 1749 1750 /* special case for 64 bit octet counter */ 1751 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 1752 | xm_read32(hw, port, XM_TXO_OK_LO); 1753 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 1754 | xm_read32(hw, port, XM_RXO_OK_LO); 1755 1756 for (i = 2; i < ARRAY_SIZE(skge_stats); i++) 1757 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); 1758 } 1759 1760 static void genesis_mac_intr(struct skge_hw *hw, int port) 1761 { 1762 struct net_device *dev = hw->dev[port]; 1763 struct skge_port *skge = netdev_priv(dev); 1764 u16 status = xm_read16(hw, port, XM_ISRC); 1765 1766 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 1767 "mac interrupt status 0x%x\n", status); 1768 1769 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) { 1770 xm_link_down(hw, port); 1771 mod_timer(&skge->link_timer, jiffies + 1); 1772 } 1773 1774 if (status & XM_IS_TXF_UR) { 1775 xm_write32(hw, port, XM_MODE, XM_MD_FTF); 1776 ++dev->stats.tx_fifo_errors; 1777 } 1778 } 1779 1780 static void genesis_link_up(struct skge_port *skge) 1781 { 1782 struct skge_hw *hw = skge->hw; 1783 int port = skge->port; 1784 u16 cmd, msk; 1785 u32 mode; 1786 1787 cmd = xm_read16(hw, port, XM_MMU_CMD); 1788 1789 /* 1790 * enabling pause frame reception is required for 1000BT 1791 * because the XMAC is not reset if the link is going down 1792 */ 1793 if (skge->flow_status == FLOW_STAT_NONE || 1794 skge->flow_status == FLOW_STAT_LOC_SEND) 1795 /* Disable Pause Frame Reception */ 1796 cmd |= XM_MMU_IGN_PF; 1797 else 1798 /* Enable Pause Frame Reception */ 1799 cmd &= ~XM_MMU_IGN_PF; 1800 1801 xm_write16(hw, port, XM_MMU_CMD, cmd); 1802 1803 mode = xm_read32(hw, port, XM_MODE); 1804 if (skge->flow_status == FLOW_STAT_SYMMETRIC || 1805 skge->flow_status == FLOW_STAT_LOC_SEND) { 1806 /* 1807 * Configure Pause Frame Generation 1808 * Use internal and external Pause Frame Generation. 1809 * Sending pause frames is edge triggered. 1810 * Send a Pause frame with the maximum pause time if 1811 * internal oder external FIFO full condition occurs. 1812 * Send a zero pause time frame to re-start transmission. 1813 */ 1814 /* XM_PAUSE_DA = '010000C28001' (default) */ 1815 /* XM_MAC_PTIME = 0xffff (maximum) */ 1816 /* remember this value is defined in big endian (!) */ 1817 xm_write16(hw, port, XM_MAC_PTIME, 0xffff); 1818 1819 mode |= XM_PAUSE_MODE; 1820 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); 1821 } else { 1822 /* 1823 * disable pause frame generation is required for 1000BT 1824 * because the XMAC is not reset if the link is going down 1825 */ 1826 /* Disable Pause Mode in Mode Register */ 1827 mode &= ~XM_PAUSE_MODE; 1828 1829 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); 1830 } 1831 1832 xm_write32(hw, port, XM_MODE, mode); 1833 1834 /* Turn on detection of Tx underrun */ 1835 msk = xm_read16(hw, port, XM_IMSK); 1836 msk &= ~XM_IS_TXF_UR; 1837 xm_write16(hw, port, XM_IMSK, msk); 1838 1839 xm_read16(hw, port, XM_ISRC); 1840 1841 /* get MMU Command Reg. */ 1842 cmd = xm_read16(hw, port, XM_MMU_CMD); 1843 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) 1844 cmd |= XM_MMU_GMII_FD; 1845 1846 /* 1847 * Workaround BCOM Errata (#10523) for all BCom Phys 1848 * Enable Power Management after link up 1849 */ 1850 if (hw->phy_type == SK_PHY_BCOM) { 1851 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 1852 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) 1853 & ~PHY_B_AC_DIS_PM); 1854 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 1855 } 1856 1857 /* enable Rx/Tx */ 1858 xm_write16(hw, port, XM_MMU_CMD, 1859 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); 1860 skge_link_up(skge); 1861 } 1862 1863 1864 static inline void bcom_phy_intr(struct skge_port *skge) 1865 { 1866 struct skge_hw *hw = skge->hw; 1867 int port = skge->port; 1868 u16 isrc; 1869 1870 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); 1871 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 1872 "phy interrupt status 0x%x\n", isrc); 1873 1874 if (isrc & PHY_B_IS_PSE) 1875 pr_err("%s: uncorrectable pair swap error\n", 1876 hw->dev[port]->name); 1877 1878 /* Workaround BCom Errata: 1879 * enable and disable loopback mode if "NO HCD" occurs. 1880 */ 1881 if (isrc & PHY_B_IS_NO_HDCL) { 1882 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); 1883 xm_phy_write(hw, port, PHY_BCOM_CTRL, 1884 ctrl | PHY_CT_LOOP); 1885 xm_phy_write(hw, port, PHY_BCOM_CTRL, 1886 ctrl & ~PHY_CT_LOOP); 1887 } 1888 1889 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) 1890 bcom_check_link(hw, port); 1891 1892 } 1893 1894 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) 1895 { 1896 int i; 1897 1898 gma_write16(hw, port, GM_SMI_DATA, val); 1899 gma_write16(hw, port, GM_SMI_CTRL, 1900 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); 1901 for (i = 0; i < PHY_RETRIES; i++) { 1902 udelay(1); 1903 1904 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) 1905 return 0; 1906 } 1907 1908 pr_warn("%s: phy write timeout\n", hw->dev[port]->name); 1909 return -EIO; 1910 } 1911 1912 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) 1913 { 1914 int i; 1915 1916 gma_write16(hw, port, GM_SMI_CTRL, 1917 GM_SMI_CT_PHY_AD(hw->phy_addr) 1918 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 1919 1920 for (i = 0; i < PHY_RETRIES; i++) { 1921 udelay(1); 1922 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) 1923 goto ready; 1924 } 1925 1926 return -ETIMEDOUT; 1927 ready: 1928 *val = gma_read16(hw, port, GM_SMI_DATA); 1929 return 0; 1930 } 1931 1932 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) 1933 { 1934 u16 v = 0; 1935 if (__gm_phy_read(hw, port, reg, &v)) 1936 pr_warn("%s: phy read timeout\n", hw->dev[port]->name); 1937 return v; 1938 } 1939 1940 /* Marvell Phy Initialization */ 1941 static void yukon_init(struct skge_hw *hw, int port) 1942 { 1943 struct skge_port *skge = netdev_priv(hw->dev[port]); 1944 u16 ctrl, ct1000, adv; 1945 1946 if (skge->autoneg == AUTONEG_ENABLE) { 1947 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 1948 1949 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 1950 PHY_M_EC_MAC_S_MSK); 1951 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 1952 1953 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 1954 1955 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 1956 } 1957 1958 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 1959 if (skge->autoneg == AUTONEG_DISABLE) 1960 ctrl &= ~PHY_CT_ANE; 1961 1962 ctrl |= PHY_CT_RESET; 1963 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 1964 1965 ctrl = 0; 1966 ct1000 = 0; 1967 adv = PHY_AN_CSMA; 1968 1969 if (skge->autoneg == AUTONEG_ENABLE) { 1970 if (hw->copper) { 1971 if (skge->advertising & ADVERTISED_1000baseT_Full) 1972 ct1000 |= PHY_M_1000C_AFD; 1973 if (skge->advertising & ADVERTISED_1000baseT_Half) 1974 ct1000 |= PHY_M_1000C_AHD; 1975 if (skge->advertising & ADVERTISED_100baseT_Full) 1976 adv |= PHY_M_AN_100_FD; 1977 if (skge->advertising & ADVERTISED_100baseT_Half) 1978 adv |= PHY_M_AN_100_HD; 1979 if (skge->advertising & ADVERTISED_10baseT_Full) 1980 adv |= PHY_M_AN_10_FD; 1981 if (skge->advertising & ADVERTISED_10baseT_Half) 1982 adv |= PHY_M_AN_10_HD; 1983 1984 /* Set Flow-control capabilities */ 1985 adv |= phy_pause_map[skge->flow_control]; 1986 } else { 1987 if (skge->advertising & ADVERTISED_1000baseT_Full) 1988 adv |= PHY_M_AN_1000X_AFD; 1989 if (skge->advertising & ADVERTISED_1000baseT_Half) 1990 adv |= PHY_M_AN_1000X_AHD; 1991 1992 adv |= fiber_pause_map[skge->flow_control]; 1993 } 1994 1995 /* Restart Auto-negotiation */ 1996 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 1997 } else { 1998 /* forced speed/duplex settings */ 1999 ct1000 = PHY_M_1000C_MSE; 2000 2001 if (skge->duplex == DUPLEX_FULL) 2002 ctrl |= PHY_CT_DUP_MD; 2003 2004 switch (skge->speed) { 2005 case SPEED_1000: 2006 ctrl |= PHY_CT_SP1000; 2007 break; 2008 case SPEED_100: 2009 ctrl |= PHY_CT_SP100; 2010 break; 2011 } 2012 2013 ctrl |= PHY_CT_RESET; 2014 } 2015 2016 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 2017 2018 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 2019 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 2020 2021 /* Enable phy interrupt on autonegotiation complete (or link up) */ 2022 if (skge->autoneg == AUTONEG_ENABLE) 2023 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); 2024 else 2025 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); 2026 } 2027 2028 static void yukon_reset(struct skge_hw *hw, int port) 2029 { 2030 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ 2031 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 2032 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 2033 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 2034 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 2035 2036 gma_write16(hw, port, GM_RX_CTRL, 2037 gma_read16(hw, port, GM_RX_CTRL) 2038 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 2039 } 2040 2041 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */ 2042 static int is_yukon_lite_a0(struct skge_hw *hw) 2043 { 2044 u32 reg; 2045 int ret; 2046 2047 if (hw->chip_id != CHIP_ID_YUKON) 2048 return 0; 2049 2050 reg = skge_read32(hw, B2_FAR); 2051 skge_write8(hw, B2_FAR + 3, 0xff); 2052 ret = (skge_read8(hw, B2_FAR + 3) != 0); 2053 skge_write32(hw, B2_FAR, reg); 2054 return ret; 2055 } 2056 2057 static void yukon_mac_init(struct skge_hw *hw, int port) 2058 { 2059 struct skge_port *skge = netdev_priv(hw->dev[port]); 2060 int i; 2061 u32 reg; 2062 const u8 *addr = hw->dev[port]->dev_addr; 2063 2064 /* WA code for COMA mode -- set PHY reset */ 2065 if (hw->chip_id == CHIP_ID_YUKON_LITE && 2066 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 2067 reg = skge_read32(hw, B2_GP_IO); 2068 reg |= GP_DIR_9 | GP_IO_9; 2069 skge_write32(hw, B2_GP_IO, reg); 2070 } 2071 2072 /* hard reset */ 2073 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2074 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2075 2076 /* WA code for COMA mode -- clear PHY reset */ 2077 if (hw->chip_id == CHIP_ID_YUKON_LITE && 2078 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 2079 reg = skge_read32(hw, B2_GP_IO); 2080 reg |= GP_DIR_9; 2081 reg &= ~GP_IO_9; 2082 skge_write32(hw, B2_GP_IO, reg); 2083 } 2084 2085 /* Set hardware config mode */ 2086 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | 2087 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE; 2088 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; 2089 2090 /* Clear GMC reset */ 2091 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); 2092 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); 2093 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); 2094 2095 if (skge->autoneg == AUTONEG_DISABLE) { 2096 reg = GM_GPCR_AU_ALL_DIS; 2097 gma_write16(hw, port, GM_GP_CTRL, 2098 gma_read16(hw, port, GM_GP_CTRL) | reg); 2099 2100 switch (skge->speed) { 2101 case SPEED_1000: 2102 reg &= ~GM_GPCR_SPEED_100; 2103 reg |= GM_GPCR_SPEED_1000; 2104 break; 2105 case SPEED_100: 2106 reg &= ~GM_GPCR_SPEED_1000; 2107 reg |= GM_GPCR_SPEED_100; 2108 break; 2109 case SPEED_10: 2110 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); 2111 break; 2112 } 2113 2114 if (skge->duplex == DUPLEX_FULL) 2115 reg |= GM_GPCR_DUP_FULL; 2116 } else 2117 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; 2118 2119 switch (skge->flow_control) { 2120 case FLOW_MODE_NONE: 2121 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2122 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 2123 break; 2124 case FLOW_MODE_LOC_SEND: 2125 /* disable Rx flow-control */ 2126 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 2127 break; 2128 case FLOW_MODE_SYMMETRIC: 2129 case FLOW_MODE_SYM_OR_REM: 2130 /* enable Tx & Rx flow-control */ 2131 break; 2132 } 2133 2134 gma_write16(hw, port, GM_GP_CTRL, reg); 2135 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 2136 2137 yukon_init(hw, port); 2138 2139 /* MIB clear */ 2140 reg = gma_read16(hw, port, GM_PHY_ADDR); 2141 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 2142 2143 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 2144 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); 2145 gma_write16(hw, port, GM_PHY_ADDR, reg); 2146 2147 /* transmit control */ 2148 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 2149 2150 /* receive control reg: unicast + multicast + no FCS */ 2151 gma_write16(hw, port, GM_RX_CTRL, 2152 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 2153 2154 /* transmit flow control */ 2155 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 2156 2157 /* transmit parameter */ 2158 gma_write16(hw, port, GM_TX_PARAM, 2159 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 2160 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 2161 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); 2162 2163 /* configure the Serial Mode Register */ 2164 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) 2165 | GM_SMOD_VLAN_ENA 2166 | IPG_DATA_VAL(IPG_DATA_DEF); 2167 2168 if (hw->dev[port]->mtu > ETH_DATA_LEN) 2169 reg |= GM_SMOD_JUMBO_ENA; 2170 2171 gma_write16(hw, port, GM_SERIAL_MODE, reg); 2172 2173 /* physical address: used for pause frames */ 2174 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 2175 /* virtual address for data */ 2176 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 2177 2178 /* enable interrupt mask for counter overflows */ 2179 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 2180 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 2181 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 2182 2183 /* Initialize Mac Fifo */ 2184 2185 /* Configure Rx MAC FIFO */ 2186 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); 2187 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 2188 2189 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ 2190 if (is_yukon_lite_a0(hw)) 2191 reg &= ~GMF_RX_F_FL_ON; 2192 2193 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 2194 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); 2195 /* 2196 * because Pause Packet Truncation in GMAC is not working 2197 * we have to increase the Flush Threshold to 64 bytes 2198 * in order to flush pause packets in Rx FIFO on Yukon-1 2199 */ 2200 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); 2201 2202 /* Configure Tx MAC FIFO */ 2203 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 2204 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 2205 } 2206 2207 /* Go into power down mode */ 2208 static void yukon_suspend(struct skge_hw *hw, int port) 2209 { 2210 u16 ctrl; 2211 2212 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 2213 ctrl |= PHY_M_PC_POL_R_DIS; 2214 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 2215 2216 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 2217 ctrl |= PHY_CT_RESET; 2218 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 2219 2220 /* switch IEEE compatible power down mode on */ 2221 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 2222 ctrl |= PHY_CT_PDOWN; 2223 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 2224 } 2225 2226 static void yukon_stop(struct skge_port *skge) 2227 { 2228 struct skge_hw *hw = skge->hw; 2229 int port = skge->port; 2230 2231 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 2232 yukon_reset(hw, port); 2233 2234 gma_write16(hw, port, GM_GP_CTRL, 2235 gma_read16(hw, port, GM_GP_CTRL) 2236 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); 2237 gma_read16(hw, port, GM_GP_CTRL); 2238 2239 yukon_suspend(hw, port); 2240 2241 /* set GPHY Control reset */ 2242 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2243 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2244 } 2245 2246 static void yukon_get_stats(struct skge_port *skge, u64 *data) 2247 { 2248 struct skge_hw *hw = skge->hw; 2249 int port = skge->port; 2250 int i; 2251 2252 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 2253 | gma_read32(hw, port, GM_TXO_OK_LO); 2254 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 2255 | gma_read32(hw, port, GM_RXO_OK_LO); 2256 2257 for (i = 2; i < ARRAY_SIZE(skge_stats); i++) 2258 data[i] = gma_read32(hw, port, 2259 skge_stats[i].gma_offset); 2260 } 2261 2262 static void yukon_mac_intr(struct skge_hw *hw, int port) 2263 { 2264 struct net_device *dev = hw->dev[port]; 2265 struct skge_port *skge = netdev_priv(dev); 2266 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2267 2268 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 2269 "mac interrupt status 0x%x\n", status); 2270 2271 if (status & GM_IS_RX_FF_OR) { 2272 ++dev->stats.rx_fifo_errors; 2273 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2274 } 2275 2276 if (status & GM_IS_TX_FF_UR) { 2277 ++dev->stats.tx_fifo_errors; 2278 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2279 } 2280 2281 } 2282 2283 static u16 yukon_speed(const struct skge_hw *hw, u16 aux) 2284 { 2285 switch (aux & PHY_M_PS_SPEED_MSK) { 2286 case PHY_M_PS_SPEED_1000: 2287 return SPEED_1000; 2288 case PHY_M_PS_SPEED_100: 2289 return SPEED_100; 2290 default: 2291 return SPEED_10; 2292 } 2293 } 2294 2295 static void yukon_link_up(struct skge_port *skge) 2296 { 2297 struct skge_hw *hw = skge->hw; 2298 int port = skge->port; 2299 u16 reg; 2300 2301 /* Enable Transmit FIFO Underrun */ 2302 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 2303 2304 reg = gma_read16(hw, port, GM_GP_CTRL); 2305 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) 2306 reg |= GM_GPCR_DUP_FULL; 2307 2308 /* enable Rx/Tx */ 2309 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 2310 gma_write16(hw, port, GM_GP_CTRL, reg); 2311 2312 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); 2313 skge_link_up(skge); 2314 } 2315 2316 static void yukon_link_down(struct skge_port *skge) 2317 { 2318 struct skge_hw *hw = skge->hw; 2319 int port = skge->port; 2320 u16 ctrl; 2321 2322 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2323 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2324 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2325 2326 if (skge->flow_status == FLOW_STAT_REM_SEND) { 2327 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2328 ctrl |= PHY_M_AN_ASP; 2329 /* restore Asymmetric Pause bit */ 2330 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); 2331 } 2332 2333 skge_link_down(skge); 2334 2335 yukon_init(hw, port); 2336 } 2337 2338 static void yukon_phy_intr(struct skge_port *skge) 2339 { 2340 struct skge_hw *hw = skge->hw; 2341 int port = skge->port; 2342 const char *reason = NULL; 2343 u16 istatus, phystat; 2344 2345 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2346 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2347 2348 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 2349 "phy interrupt status 0x%x 0x%x\n", istatus, phystat); 2350 2351 if (istatus & PHY_M_IS_AN_COMPL) { 2352 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) 2353 & PHY_M_AN_RF) { 2354 reason = "remote fault"; 2355 goto failed; 2356 } 2357 2358 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { 2359 reason = "master/slave fault"; 2360 goto failed; 2361 } 2362 2363 if (!(phystat & PHY_M_PS_SPDUP_RES)) { 2364 reason = "speed/duplex"; 2365 goto failed; 2366 } 2367 2368 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) 2369 ? DUPLEX_FULL : DUPLEX_HALF; 2370 skge->speed = yukon_speed(hw, phystat); 2371 2372 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 2373 switch (phystat & PHY_M_PS_PAUSE_MSK) { 2374 case PHY_M_PS_PAUSE_MSK: 2375 skge->flow_status = FLOW_STAT_SYMMETRIC; 2376 break; 2377 case PHY_M_PS_RX_P_EN: 2378 skge->flow_status = FLOW_STAT_REM_SEND; 2379 break; 2380 case PHY_M_PS_TX_P_EN: 2381 skge->flow_status = FLOW_STAT_LOC_SEND; 2382 break; 2383 default: 2384 skge->flow_status = FLOW_STAT_NONE; 2385 } 2386 2387 if (skge->flow_status == FLOW_STAT_NONE || 2388 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) 2389 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2390 else 2391 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2392 yukon_link_up(skge); 2393 return; 2394 } 2395 2396 if (istatus & PHY_M_IS_LSP_CHANGE) 2397 skge->speed = yukon_speed(hw, phystat); 2398 2399 if (istatus & PHY_M_IS_DUP_CHANGE) 2400 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2401 if (istatus & PHY_M_IS_LST_CHANGE) { 2402 if (phystat & PHY_M_PS_LINK_UP) 2403 yukon_link_up(skge); 2404 else 2405 yukon_link_down(skge); 2406 } 2407 return; 2408 failed: 2409 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason); 2410 2411 /* XXX restart autonegotiation? */ 2412 } 2413 2414 static void skge_phy_reset(struct skge_port *skge) 2415 { 2416 struct skge_hw *hw = skge->hw; 2417 int port = skge->port; 2418 struct net_device *dev = hw->dev[port]; 2419 2420 netif_stop_queue(skge->netdev); 2421 netif_carrier_off(skge->netdev); 2422 2423 spin_lock_bh(&hw->phy_lock); 2424 if (is_genesis(hw)) { 2425 genesis_reset(hw, port); 2426 genesis_mac_init(hw, port); 2427 } else { 2428 yukon_reset(hw, port); 2429 yukon_init(hw, port); 2430 } 2431 spin_unlock_bh(&hw->phy_lock); 2432 2433 skge_set_multicast(dev); 2434 } 2435 2436 /* Basic MII support */ 2437 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2438 { 2439 struct mii_ioctl_data *data = if_mii(ifr); 2440 struct skge_port *skge = netdev_priv(dev); 2441 struct skge_hw *hw = skge->hw; 2442 int err = -EOPNOTSUPP; 2443 2444 if (!netif_running(dev)) 2445 return -ENODEV; /* Phy still in reset */ 2446 2447 switch (cmd) { 2448 case SIOCGMIIPHY: 2449 data->phy_id = hw->phy_addr; 2450 2451 fallthrough; 2452 case SIOCGMIIREG: { 2453 u16 val = 0; 2454 spin_lock_bh(&hw->phy_lock); 2455 2456 if (is_genesis(hw)) 2457 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); 2458 else 2459 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); 2460 spin_unlock_bh(&hw->phy_lock); 2461 data->val_out = val; 2462 break; 2463 } 2464 2465 case SIOCSMIIREG: 2466 spin_lock_bh(&hw->phy_lock); 2467 if (is_genesis(hw)) 2468 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, 2469 data->val_in); 2470 else 2471 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, 2472 data->val_in); 2473 spin_unlock_bh(&hw->phy_lock); 2474 break; 2475 } 2476 return err; 2477 } 2478 2479 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) 2480 { 2481 u32 end; 2482 2483 start /= 8; 2484 len /= 8; 2485 end = start + len - 1; 2486 2487 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 2488 skge_write32(hw, RB_ADDR(q, RB_START), start); 2489 skge_write32(hw, RB_ADDR(q, RB_WP), start); 2490 skge_write32(hw, RB_ADDR(q, RB_RP), start); 2491 skge_write32(hw, RB_ADDR(q, RB_END), end); 2492 2493 if (q == Q_R1 || q == Q_R2) { 2494 /* Set thresholds on receive queue's */ 2495 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), 2496 start + (2*len)/3); 2497 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), 2498 start + (len/3)); 2499 } else { 2500 /* Enable store & forward on Tx queue's because 2501 * Tx FIFO is only 4K on Genesis and 1K on Yukon 2502 */ 2503 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 2504 } 2505 2506 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 2507 } 2508 2509 /* Setup Bus Memory Interface */ 2510 static void skge_qset(struct skge_port *skge, u16 q, 2511 const struct skge_element *e) 2512 { 2513 struct skge_hw *hw = skge->hw; 2514 u32 watermark = 0x600; 2515 u64 base = skge->dma + (e->desc - skge->mem); 2516 2517 /* optimization to reduce window on 32bit/33mhz */ 2518 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) 2519 watermark /= 2; 2520 2521 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); 2522 skge_write32(hw, Q_ADDR(q, Q_F), watermark); 2523 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); 2524 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); 2525 } 2526 2527 static int skge_up(struct net_device *dev) 2528 { 2529 struct skge_port *skge = netdev_priv(dev); 2530 struct skge_hw *hw = skge->hw; 2531 int port = skge->port; 2532 u32 chunk, ram_addr; 2533 size_t rx_size, tx_size; 2534 int err; 2535 2536 if (!is_valid_ether_addr(dev->dev_addr)) 2537 return -EINVAL; 2538 2539 netif_info(skge, ifup, skge->netdev, "enabling interface\n"); 2540 2541 if (dev->mtu > RX_BUF_SIZE) 2542 skge->rx_buf_size = dev->mtu + ETH_HLEN; 2543 else 2544 skge->rx_buf_size = RX_BUF_SIZE; 2545 2546 2547 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc); 2548 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc); 2549 skge->mem_size = tx_size + rx_size; 2550 skge->mem = dma_alloc_coherent(&hw->pdev->dev, skge->mem_size, 2551 &skge->dma, GFP_KERNEL); 2552 if (!skge->mem) 2553 return -ENOMEM; 2554 2555 BUG_ON(skge->dma & 7); 2556 2557 if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) { 2558 dev_err(&hw->pdev->dev, "dma_alloc_coherent region crosses 4G boundary\n"); 2559 err = -EINVAL; 2560 goto free_pci_mem; 2561 } 2562 2563 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma); 2564 if (err) 2565 goto free_pci_mem; 2566 2567 err = skge_rx_fill(dev); 2568 if (err) 2569 goto free_rx_ring; 2570 2571 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size, 2572 skge->dma + rx_size); 2573 if (err) 2574 goto free_rx_ring; 2575 2576 if (hw->ports == 1) { 2577 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED, 2578 dev->name, hw); 2579 if (err) { 2580 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n", 2581 hw->pdev->irq, err); 2582 goto free_tx_ring; 2583 } 2584 } 2585 2586 /* Initialize MAC */ 2587 netif_carrier_off(dev); 2588 spin_lock_bh(&hw->phy_lock); 2589 if (is_genesis(hw)) 2590 genesis_mac_init(hw, port); 2591 else 2592 yukon_mac_init(hw, port); 2593 spin_unlock_bh(&hw->phy_lock); 2594 2595 /* Configure RAMbuffers - equally between ports and tx/rx */ 2596 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2); 2597 ram_addr = hw->ram_offset + 2 * chunk * port; 2598 2599 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); 2600 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); 2601 2602 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean); 2603 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); 2604 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use); 2605 2606 /* Start receiver BMU */ 2607 wmb(); 2608 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); 2609 skge_led(skge, LED_MODE_ON); 2610 2611 spin_lock_irq(&hw->hw_lock); 2612 hw->intr_mask |= portmask[port]; 2613 skge_write32(hw, B0_IMSK, hw->intr_mask); 2614 skge_read32(hw, B0_IMSK); 2615 spin_unlock_irq(&hw->hw_lock); 2616 2617 napi_enable(&skge->napi); 2618 2619 skge_set_multicast(dev); 2620 2621 return 0; 2622 2623 free_tx_ring: 2624 kfree(skge->tx_ring.start); 2625 free_rx_ring: 2626 skge_rx_clean(skge); 2627 kfree(skge->rx_ring.start); 2628 free_pci_mem: 2629 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem, 2630 skge->dma); 2631 skge->mem = NULL; 2632 2633 return err; 2634 } 2635 2636 /* stop receiver */ 2637 static void skge_rx_stop(struct skge_hw *hw, int port) 2638 { 2639 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); 2640 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), 2641 RB_RST_SET|RB_DIS_OP_MD); 2642 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); 2643 } 2644 2645 static int skge_down(struct net_device *dev) 2646 { 2647 struct skge_port *skge = netdev_priv(dev); 2648 struct skge_hw *hw = skge->hw; 2649 int port = skge->port; 2650 2651 if (!skge->mem) 2652 return 0; 2653 2654 netif_info(skge, ifdown, skge->netdev, "disabling interface\n"); 2655 2656 netif_tx_disable(dev); 2657 2658 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC) 2659 del_timer_sync(&skge->link_timer); 2660 2661 napi_disable(&skge->napi); 2662 netif_carrier_off(dev); 2663 2664 spin_lock_irq(&hw->hw_lock); 2665 hw->intr_mask &= ~portmask[port]; 2666 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask); 2667 skge_read32(hw, B0_IMSK); 2668 spin_unlock_irq(&hw->hw_lock); 2669 2670 if (hw->ports == 1) 2671 free_irq(hw->pdev->irq, hw); 2672 2673 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF); 2674 if (is_genesis(hw)) 2675 genesis_stop(skge); 2676 else 2677 yukon_stop(skge); 2678 2679 /* Stop transmitter */ 2680 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); 2681 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2682 RB_RST_SET|RB_DIS_OP_MD); 2683 2684 2685 /* Disable Force Sync bit and Enable Alloc bit */ 2686 skge_write8(hw, SK_REG(port, TXA_CTRL), 2687 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2688 2689 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2690 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2691 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2692 2693 /* Reset PCI FIFO */ 2694 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); 2695 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2696 2697 /* Reset the RAM Buffer async Tx queue */ 2698 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); 2699 2700 skge_rx_stop(hw, port); 2701 2702 if (is_genesis(hw)) { 2703 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); 2704 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); 2705 } else { 2706 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2707 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2708 } 2709 2710 skge_led(skge, LED_MODE_OFF); 2711 2712 netif_tx_lock_bh(dev); 2713 skge_tx_clean(dev); 2714 netif_tx_unlock_bh(dev); 2715 2716 skge_rx_clean(skge); 2717 2718 kfree(skge->rx_ring.start); 2719 kfree(skge->tx_ring.start); 2720 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem, 2721 skge->dma); 2722 skge->mem = NULL; 2723 return 0; 2724 } 2725 2726 static inline int skge_avail(const struct skge_ring *ring) 2727 { 2728 smp_mb(); 2729 return ((ring->to_clean > ring->to_use) ? 0 : ring->count) 2730 + (ring->to_clean - ring->to_use) - 1; 2731 } 2732 2733 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb, 2734 struct net_device *dev) 2735 { 2736 struct skge_port *skge = netdev_priv(dev); 2737 struct skge_hw *hw = skge->hw; 2738 struct skge_element *e; 2739 struct skge_tx_desc *td; 2740 int i; 2741 u32 control, len; 2742 dma_addr_t map; 2743 2744 if (skb_padto(skb, ETH_ZLEN)) 2745 return NETDEV_TX_OK; 2746 2747 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) 2748 return NETDEV_TX_BUSY; 2749 2750 e = skge->tx_ring.to_use; 2751 td = e->desc; 2752 BUG_ON(td->control & BMU_OWN); 2753 e->skb = skb; 2754 len = skb_headlen(skb); 2755 map = dma_map_single(&hw->pdev->dev, skb->data, len, DMA_TO_DEVICE); 2756 if (dma_mapping_error(&hw->pdev->dev, map)) 2757 goto mapping_error; 2758 2759 dma_unmap_addr_set(e, mapaddr, map); 2760 dma_unmap_len_set(e, maplen, len); 2761 2762 td->dma_lo = lower_32_bits(map); 2763 td->dma_hi = upper_32_bits(map); 2764 2765 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2766 const int offset = skb_checksum_start_offset(skb); 2767 2768 /* This seems backwards, but it is what the sk98lin 2769 * does. Looks like hardware is wrong? 2770 */ 2771 if (ipip_hdr(skb)->protocol == IPPROTO_UDP && 2772 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) 2773 control = BMU_TCP_CHECK; 2774 else 2775 control = BMU_UDP_CHECK; 2776 2777 td->csum_offs = 0; 2778 td->csum_start = offset; 2779 td->csum_write = offset + skb->csum_offset; 2780 } else 2781 control = BMU_CHECK; 2782 2783 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */ 2784 control |= BMU_EOF | BMU_IRQ_EOF; 2785 else { 2786 struct skge_tx_desc *tf = td; 2787 2788 control |= BMU_STFWD; 2789 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2790 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2791 2792 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0, 2793 skb_frag_size(frag), DMA_TO_DEVICE); 2794 if (dma_mapping_error(&hw->pdev->dev, map)) 2795 goto mapping_unwind; 2796 2797 e = e->next; 2798 e->skb = skb; 2799 tf = e->desc; 2800 BUG_ON(tf->control & BMU_OWN); 2801 2802 tf->dma_lo = lower_32_bits(map); 2803 tf->dma_hi = upper_32_bits(map); 2804 dma_unmap_addr_set(e, mapaddr, map); 2805 dma_unmap_len_set(e, maplen, skb_frag_size(frag)); 2806 2807 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag); 2808 } 2809 tf->control |= BMU_EOF | BMU_IRQ_EOF; 2810 } 2811 /* Make sure all the descriptors written */ 2812 wmb(); 2813 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len; 2814 wmb(); 2815 2816 netdev_sent_queue(dev, skb->len); 2817 2818 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); 2819 2820 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev, 2821 "tx queued, slot %td, len %d\n", 2822 e - skge->tx_ring.start, skb->len); 2823 2824 skge->tx_ring.to_use = e->next; 2825 smp_wmb(); 2826 2827 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) { 2828 netdev_dbg(dev, "transmit queue full\n"); 2829 netif_stop_queue(dev); 2830 } 2831 2832 return NETDEV_TX_OK; 2833 2834 mapping_unwind: 2835 e = skge->tx_ring.to_use; 2836 dma_unmap_single(&hw->pdev->dev, dma_unmap_addr(e, mapaddr), 2837 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2838 while (i-- > 0) { 2839 e = e->next; 2840 dma_unmap_page(&hw->pdev->dev, dma_unmap_addr(e, mapaddr), 2841 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2842 } 2843 2844 mapping_error: 2845 if (net_ratelimit()) 2846 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 2847 dev_kfree_skb_any(skb); 2848 return NETDEV_TX_OK; 2849 } 2850 2851 2852 /* Free resources associated with this reing element */ 2853 static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e, 2854 u32 control) 2855 { 2856 /* skb header vs. fragment */ 2857 if (control & BMU_STF) 2858 dma_unmap_single(&pdev->dev, dma_unmap_addr(e, mapaddr), 2859 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2860 else 2861 dma_unmap_page(&pdev->dev, dma_unmap_addr(e, mapaddr), 2862 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2863 } 2864 2865 /* Free all buffers in transmit ring */ 2866 static void skge_tx_clean(struct net_device *dev) 2867 { 2868 struct skge_port *skge = netdev_priv(dev); 2869 struct skge_element *e; 2870 2871 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { 2872 struct skge_tx_desc *td = e->desc; 2873 2874 skge_tx_unmap(skge->hw->pdev, e, td->control); 2875 2876 if (td->control & BMU_EOF) 2877 dev_kfree_skb(e->skb); 2878 td->control = 0; 2879 } 2880 2881 netdev_reset_queue(dev); 2882 skge->tx_ring.to_clean = e; 2883 } 2884 2885 static void skge_tx_timeout(struct net_device *dev, unsigned int txqueue) 2886 { 2887 struct skge_port *skge = netdev_priv(dev); 2888 2889 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n"); 2890 2891 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); 2892 skge_tx_clean(dev); 2893 netif_wake_queue(dev); 2894 } 2895 2896 static int skge_change_mtu(struct net_device *dev, int new_mtu) 2897 { 2898 int err; 2899 2900 if (!netif_running(dev)) { 2901 dev->mtu = new_mtu; 2902 return 0; 2903 } 2904 2905 skge_down(dev); 2906 2907 dev->mtu = new_mtu; 2908 2909 err = skge_up(dev); 2910 if (err) 2911 dev_close(dev); 2912 2913 return err; 2914 } 2915 2916 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 2917 2918 static void genesis_add_filter(u8 filter[8], const u8 *addr) 2919 { 2920 u32 crc, bit; 2921 2922 crc = ether_crc_le(ETH_ALEN, addr); 2923 bit = ~crc & 0x3f; 2924 filter[bit/8] |= 1 << (bit%8); 2925 } 2926 2927 static void genesis_set_multicast(struct net_device *dev) 2928 { 2929 struct skge_port *skge = netdev_priv(dev); 2930 struct skge_hw *hw = skge->hw; 2931 int port = skge->port; 2932 struct netdev_hw_addr *ha; 2933 u32 mode; 2934 u8 filter[8]; 2935 2936 mode = xm_read32(hw, port, XM_MODE); 2937 mode |= XM_MD_ENA_HASH; 2938 if (dev->flags & IFF_PROMISC) 2939 mode |= XM_MD_ENA_PROM; 2940 else 2941 mode &= ~XM_MD_ENA_PROM; 2942 2943 if (dev->flags & IFF_ALLMULTI) 2944 memset(filter, 0xff, sizeof(filter)); 2945 else { 2946 memset(filter, 0, sizeof(filter)); 2947 2948 if (skge->flow_status == FLOW_STAT_REM_SEND || 2949 skge->flow_status == FLOW_STAT_SYMMETRIC) 2950 genesis_add_filter(filter, pause_mc_addr); 2951 2952 netdev_for_each_mc_addr(ha, dev) 2953 genesis_add_filter(filter, ha->addr); 2954 } 2955 2956 xm_write32(hw, port, XM_MODE, mode); 2957 xm_outhash(hw, port, XM_HSM, filter); 2958 } 2959 2960 static void yukon_add_filter(u8 filter[8], const u8 *addr) 2961 { 2962 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f; 2963 2964 filter[bit / 8] |= 1 << (bit % 8); 2965 } 2966 2967 static void yukon_set_multicast(struct net_device *dev) 2968 { 2969 struct skge_port *skge = netdev_priv(dev); 2970 struct skge_hw *hw = skge->hw; 2971 int port = skge->port; 2972 struct netdev_hw_addr *ha; 2973 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND || 2974 skge->flow_status == FLOW_STAT_SYMMETRIC); 2975 u16 reg; 2976 u8 filter[8]; 2977 2978 memset(filter, 0, sizeof(filter)); 2979 2980 reg = gma_read16(hw, port, GM_RX_CTRL); 2981 reg |= GM_RXCR_UCF_ENA; 2982 2983 if (dev->flags & IFF_PROMISC) /* promiscuous */ 2984 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 2985 else if (dev->flags & IFF_ALLMULTI) /* all multicast */ 2986 memset(filter, 0xff, sizeof(filter)); 2987 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */ 2988 reg &= ~GM_RXCR_MCF_ENA; 2989 else { 2990 reg |= GM_RXCR_MCF_ENA; 2991 2992 if (rx_pause) 2993 yukon_add_filter(filter, pause_mc_addr); 2994 2995 netdev_for_each_mc_addr(ha, dev) 2996 yukon_add_filter(filter, ha->addr); 2997 } 2998 2999 3000 gma_write16(hw, port, GM_MC_ADDR_H1, 3001 (u16)filter[0] | ((u16)filter[1] << 8)); 3002 gma_write16(hw, port, GM_MC_ADDR_H2, 3003 (u16)filter[2] | ((u16)filter[3] << 8)); 3004 gma_write16(hw, port, GM_MC_ADDR_H3, 3005 (u16)filter[4] | ((u16)filter[5] << 8)); 3006 gma_write16(hw, port, GM_MC_ADDR_H4, 3007 (u16)filter[6] | ((u16)filter[7] << 8)); 3008 3009 gma_write16(hw, port, GM_RX_CTRL, reg); 3010 } 3011 3012 static inline u16 phy_length(const struct skge_hw *hw, u32 status) 3013 { 3014 if (is_genesis(hw)) 3015 return status >> XMR_FS_LEN_SHIFT; 3016 else 3017 return status >> GMR_FS_LEN_SHIFT; 3018 } 3019 3020 static inline int bad_phy_status(const struct skge_hw *hw, u32 status) 3021 { 3022 if (is_genesis(hw)) 3023 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; 3024 else 3025 return (status & GMR_FS_ANY_ERR) || 3026 (status & GMR_FS_RX_OK) == 0; 3027 } 3028 3029 static void skge_set_multicast(struct net_device *dev) 3030 { 3031 struct skge_port *skge = netdev_priv(dev); 3032 3033 if (is_genesis(skge->hw)) 3034 genesis_set_multicast(dev); 3035 else 3036 yukon_set_multicast(dev); 3037 3038 } 3039 3040 3041 /* Get receive buffer from descriptor. 3042 * Handles copy of small buffers and reallocation failures 3043 */ 3044 static struct sk_buff *skge_rx_get(struct net_device *dev, 3045 struct skge_element *e, 3046 u32 control, u32 status, u16 csum) 3047 { 3048 struct skge_port *skge = netdev_priv(dev); 3049 struct sk_buff *skb; 3050 u16 len = control & BMU_BBC; 3051 3052 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev, 3053 "rx slot %td status 0x%x len %d\n", 3054 e - skge->rx_ring.start, status, len); 3055 3056 if (len > skge->rx_buf_size) 3057 goto error; 3058 3059 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)) 3060 goto error; 3061 3062 if (bad_phy_status(skge->hw, status)) 3063 goto error; 3064 3065 if (phy_length(skge->hw, status) != len) 3066 goto error; 3067 3068 if (len < RX_COPY_THRESHOLD) { 3069 skb = netdev_alloc_skb_ip_align(dev, len); 3070 if (!skb) 3071 goto resubmit; 3072 3073 dma_sync_single_for_cpu(&skge->hw->pdev->dev, 3074 dma_unmap_addr(e, mapaddr), 3075 dma_unmap_len(e, maplen), 3076 DMA_FROM_DEVICE); 3077 skb_copy_from_linear_data(e->skb, skb->data, len); 3078 dma_sync_single_for_device(&skge->hw->pdev->dev, 3079 dma_unmap_addr(e, mapaddr), 3080 dma_unmap_len(e, maplen), 3081 DMA_FROM_DEVICE); 3082 skge_rx_reuse(e, skge->rx_buf_size); 3083 } else { 3084 struct skge_element ee; 3085 struct sk_buff *nskb; 3086 3087 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size); 3088 if (!nskb) 3089 goto resubmit; 3090 3091 ee = *e; 3092 3093 skb = ee.skb; 3094 prefetch(skb->data); 3095 3096 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) { 3097 dev_kfree_skb(nskb); 3098 goto resubmit; 3099 } 3100 3101 dma_unmap_single(&skge->hw->pdev->dev, 3102 dma_unmap_addr(&ee, mapaddr), 3103 dma_unmap_len(&ee, maplen), DMA_FROM_DEVICE); 3104 } 3105 3106 skb_put(skb, len); 3107 3108 if (dev->features & NETIF_F_RXCSUM) { 3109 skb->csum = le16_to_cpu(csum); 3110 skb->ip_summed = CHECKSUM_COMPLETE; 3111 } 3112 3113 skb->protocol = eth_type_trans(skb, dev); 3114 3115 return skb; 3116 error: 3117 3118 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev, 3119 "rx err, slot %td control 0x%x status 0x%x\n", 3120 e - skge->rx_ring.start, control, status); 3121 3122 if (is_genesis(skge->hw)) { 3123 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR)) 3124 dev->stats.rx_length_errors++; 3125 if (status & XMR_FS_FRA_ERR) 3126 dev->stats.rx_frame_errors++; 3127 if (status & XMR_FS_FCS_ERR) 3128 dev->stats.rx_crc_errors++; 3129 } else { 3130 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE)) 3131 dev->stats.rx_length_errors++; 3132 if (status & GMR_FS_FRAGMENT) 3133 dev->stats.rx_frame_errors++; 3134 if (status & GMR_FS_CRC_ERR) 3135 dev->stats.rx_crc_errors++; 3136 } 3137 3138 resubmit: 3139 skge_rx_reuse(e, skge->rx_buf_size); 3140 return NULL; 3141 } 3142 3143 /* Free all buffers in Tx ring which are no longer owned by device */ 3144 static void skge_tx_done(struct net_device *dev) 3145 { 3146 struct skge_port *skge = netdev_priv(dev); 3147 struct skge_ring *ring = &skge->tx_ring; 3148 struct skge_element *e; 3149 unsigned int bytes_compl = 0, pkts_compl = 0; 3150 3151 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); 3152 3153 for (e = ring->to_clean; e != ring->to_use; e = e->next) { 3154 u32 control = ((const struct skge_tx_desc *) e->desc)->control; 3155 3156 if (control & BMU_OWN) 3157 break; 3158 3159 skge_tx_unmap(skge->hw->pdev, e, control); 3160 3161 if (control & BMU_EOF) { 3162 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev, 3163 "tx done slot %td\n", 3164 e - skge->tx_ring.start); 3165 3166 pkts_compl++; 3167 bytes_compl += e->skb->len; 3168 3169 dev_consume_skb_any(e->skb); 3170 } 3171 } 3172 netdev_completed_queue(dev, pkts_compl, bytes_compl); 3173 skge->tx_ring.to_clean = e; 3174 3175 /* Can run lockless until we need to synchronize to restart queue. */ 3176 smp_mb(); 3177 3178 if (unlikely(netif_queue_stopped(dev) && 3179 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) { 3180 netif_tx_lock(dev); 3181 if (unlikely(netif_queue_stopped(dev) && 3182 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) { 3183 netif_wake_queue(dev); 3184 3185 } 3186 netif_tx_unlock(dev); 3187 } 3188 } 3189 3190 static int skge_poll(struct napi_struct *napi, int budget) 3191 { 3192 struct skge_port *skge = container_of(napi, struct skge_port, napi); 3193 struct net_device *dev = skge->netdev; 3194 struct skge_hw *hw = skge->hw; 3195 struct skge_ring *ring = &skge->rx_ring; 3196 struct skge_element *e; 3197 int work_done = 0; 3198 3199 skge_tx_done(dev); 3200 3201 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); 3202 3203 for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) { 3204 struct skge_rx_desc *rd = e->desc; 3205 struct sk_buff *skb; 3206 u32 control; 3207 3208 rmb(); 3209 control = rd->control; 3210 if (control & BMU_OWN) 3211 break; 3212 3213 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2); 3214 if (likely(skb)) { 3215 napi_gro_receive(napi, skb); 3216 ++work_done; 3217 } 3218 } 3219 ring->to_clean = e; 3220 3221 /* restart receiver */ 3222 wmb(); 3223 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); 3224 3225 if (work_done < budget && napi_complete_done(napi, work_done)) { 3226 unsigned long flags; 3227 3228 spin_lock_irqsave(&hw->hw_lock, flags); 3229 hw->intr_mask |= napimask[skge->port]; 3230 skge_write32(hw, B0_IMSK, hw->intr_mask); 3231 skge_read32(hw, B0_IMSK); 3232 spin_unlock_irqrestore(&hw->hw_lock, flags); 3233 } 3234 3235 return work_done; 3236 } 3237 3238 /* Parity errors seem to happen when Genesis is connected to a switch 3239 * with no other ports present. Heartbeat error?? 3240 */ 3241 static void skge_mac_parity(struct skge_hw *hw, int port) 3242 { 3243 struct net_device *dev = hw->dev[port]; 3244 3245 ++dev->stats.tx_heartbeat_errors; 3246 3247 if (is_genesis(hw)) 3248 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), 3249 MFF_CLR_PERR); 3250 else 3251 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ 3252 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), 3253 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) 3254 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); 3255 } 3256 3257 static void skge_mac_intr(struct skge_hw *hw, int port) 3258 { 3259 if (is_genesis(hw)) 3260 genesis_mac_intr(hw, port); 3261 else 3262 yukon_mac_intr(hw, port); 3263 } 3264 3265 /* Handle device specific framing and timeout interrupts */ 3266 static void skge_error_irq(struct skge_hw *hw) 3267 { 3268 struct pci_dev *pdev = hw->pdev; 3269 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); 3270 3271 if (is_genesis(hw)) { 3272 /* clear xmac errors */ 3273 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) 3274 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); 3275 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) 3276 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); 3277 } else { 3278 /* Timestamp (unused) overflow */ 3279 if (hwstatus & IS_IRQ_TIST_OV) 3280 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3281 } 3282 3283 if (hwstatus & IS_RAM_RD_PAR) { 3284 dev_err(&pdev->dev, "Ram read data parity error\n"); 3285 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); 3286 } 3287 3288 if (hwstatus & IS_RAM_WR_PAR) { 3289 dev_err(&pdev->dev, "Ram write data parity error\n"); 3290 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); 3291 } 3292 3293 if (hwstatus & IS_M1_PAR_ERR) 3294 skge_mac_parity(hw, 0); 3295 3296 if (hwstatus & IS_M2_PAR_ERR) 3297 skge_mac_parity(hw, 1); 3298 3299 if (hwstatus & IS_R1_PAR_ERR) { 3300 dev_err(&pdev->dev, "%s: receive queue parity error\n", 3301 hw->dev[0]->name); 3302 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); 3303 } 3304 3305 if (hwstatus & IS_R2_PAR_ERR) { 3306 dev_err(&pdev->dev, "%s: receive queue parity error\n", 3307 hw->dev[1]->name); 3308 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); 3309 } 3310 3311 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) { 3312 u16 pci_status, pci_cmd; 3313 3314 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 3315 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 3316 3317 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n", 3318 pci_cmd, pci_status); 3319 3320 /* Write the error bits back to clear them. */ 3321 pci_status &= PCI_STATUS_ERROR_BITS; 3322 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3323 pci_write_config_word(pdev, PCI_COMMAND, 3324 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 3325 pci_write_config_word(pdev, PCI_STATUS, pci_status); 3326 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3327 3328 /* if error still set then just ignore it */ 3329 hwstatus = skge_read32(hw, B0_HWE_ISRC); 3330 if (hwstatus & IS_IRQ_STAT) { 3331 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n"); 3332 hw->intr_mask &= ~IS_HW_ERR; 3333 } 3334 } 3335 } 3336 3337 /* 3338 * Interrupt from PHY are handled in tasklet (softirq) 3339 * because accessing phy registers requires spin wait which might 3340 * cause excess interrupt latency. 3341 */ 3342 static void skge_extirq(struct tasklet_struct *t) 3343 { 3344 struct skge_hw *hw = from_tasklet(hw, t, phy_task); 3345 int port; 3346 3347 for (port = 0; port < hw->ports; port++) { 3348 struct net_device *dev = hw->dev[port]; 3349 3350 if (netif_running(dev)) { 3351 struct skge_port *skge = netdev_priv(dev); 3352 3353 spin_lock(&hw->phy_lock); 3354 if (!is_genesis(hw)) 3355 yukon_phy_intr(skge); 3356 else if (hw->phy_type == SK_PHY_BCOM) 3357 bcom_phy_intr(skge); 3358 spin_unlock(&hw->phy_lock); 3359 } 3360 } 3361 3362 spin_lock_irq(&hw->hw_lock); 3363 hw->intr_mask |= IS_EXT_REG; 3364 skge_write32(hw, B0_IMSK, hw->intr_mask); 3365 skge_read32(hw, B0_IMSK); 3366 spin_unlock_irq(&hw->hw_lock); 3367 } 3368 3369 static irqreturn_t skge_intr(int irq, void *dev_id) 3370 { 3371 struct skge_hw *hw = dev_id; 3372 u32 status; 3373 int handled = 0; 3374 3375 spin_lock(&hw->hw_lock); 3376 /* Reading this register masks IRQ */ 3377 status = skge_read32(hw, B0_SP_ISRC); 3378 if (status == 0 || status == ~0) 3379 goto out; 3380 3381 handled = 1; 3382 status &= hw->intr_mask; 3383 if (status & IS_EXT_REG) { 3384 hw->intr_mask &= ~IS_EXT_REG; 3385 tasklet_schedule(&hw->phy_task); 3386 } 3387 3388 if (status & (IS_XA1_F|IS_R1_F)) { 3389 struct skge_port *skge = netdev_priv(hw->dev[0]); 3390 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); 3391 napi_schedule(&skge->napi); 3392 } 3393 3394 if (status & IS_PA_TO_TX1) 3395 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); 3396 3397 if (status & IS_PA_TO_RX1) { 3398 ++hw->dev[0]->stats.rx_over_errors; 3399 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); 3400 } 3401 3402 3403 if (status & IS_MAC1) 3404 skge_mac_intr(hw, 0); 3405 3406 if (hw->dev[1]) { 3407 struct skge_port *skge = netdev_priv(hw->dev[1]); 3408 3409 if (status & (IS_XA2_F|IS_R2_F)) { 3410 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); 3411 napi_schedule(&skge->napi); 3412 } 3413 3414 if (status & IS_PA_TO_RX2) { 3415 ++hw->dev[1]->stats.rx_over_errors; 3416 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); 3417 } 3418 3419 if (status & IS_PA_TO_TX2) 3420 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); 3421 3422 if (status & IS_MAC2) 3423 skge_mac_intr(hw, 1); 3424 } 3425 3426 if (status & IS_HW_ERR) 3427 skge_error_irq(hw); 3428 out: 3429 skge_write32(hw, B0_IMSK, hw->intr_mask); 3430 skge_read32(hw, B0_IMSK); 3431 spin_unlock(&hw->hw_lock); 3432 3433 return IRQ_RETVAL(handled); 3434 } 3435 3436 #ifdef CONFIG_NET_POLL_CONTROLLER 3437 static void skge_netpoll(struct net_device *dev) 3438 { 3439 struct skge_port *skge = netdev_priv(dev); 3440 3441 disable_irq(dev->irq); 3442 skge_intr(dev->irq, skge->hw); 3443 enable_irq(dev->irq); 3444 } 3445 #endif 3446 3447 static int skge_set_mac_address(struct net_device *dev, void *p) 3448 { 3449 struct skge_port *skge = netdev_priv(dev); 3450 struct skge_hw *hw = skge->hw; 3451 unsigned port = skge->port; 3452 const struct sockaddr *addr = p; 3453 u16 ctrl; 3454 3455 if (!is_valid_ether_addr(addr->sa_data)) 3456 return -EADDRNOTAVAIL; 3457 3458 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 3459 3460 if (!netif_running(dev)) { 3461 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); 3462 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); 3463 } else { 3464 /* disable Rx */ 3465 spin_lock_bh(&hw->phy_lock); 3466 ctrl = gma_read16(hw, port, GM_GP_CTRL); 3467 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA); 3468 3469 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); 3470 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); 3471 3472 if (is_genesis(hw)) 3473 xm_outaddr(hw, port, XM_SA, dev->dev_addr); 3474 else { 3475 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3476 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3477 } 3478 3479 gma_write16(hw, port, GM_GP_CTRL, ctrl); 3480 spin_unlock_bh(&hw->phy_lock); 3481 } 3482 3483 return 0; 3484 } 3485 3486 static const struct { 3487 u8 id; 3488 const char *name; 3489 } skge_chips[] = { 3490 { CHIP_ID_GENESIS, "Genesis" }, 3491 { CHIP_ID_YUKON, "Yukon" }, 3492 { CHIP_ID_YUKON_LITE, "Yukon-Lite"}, 3493 { CHIP_ID_YUKON_LP, "Yukon-LP"}, 3494 }; 3495 3496 static const char *skge_board_name(const struct skge_hw *hw) 3497 { 3498 int i; 3499 static char buf[16]; 3500 3501 for (i = 0; i < ARRAY_SIZE(skge_chips); i++) 3502 if (skge_chips[i].id == hw->chip_id) 3503 return skge_chips[i].name; 3504 3505 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id); 3506 return buf; 3507 } 3508 3509 3510 /* 3511 * Setup the board data structure, but don't bring up 3512 * the port(s) 3513 */ 3514 static int skge_reset(struct skge_hw *hw) 3515 { 3516 u32 reg; 3517 u16 ctst, pci_status; 3518 u8 t8, mac_cfg, pmd_type; 3519 int i; 3520 3521 ctst = skge_read16(hw, B0_CTST); 3522 3523 /* do a SW reset */ 3524 skge_write8(hw, B0_CTST, CS_RST_SET); 3525 skge_write8(hw, B0_CTST, CS_RST_CLR); 3526 3527 /* clear PCI errors, if any */ 3528 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3529 skge_write8(hw, B2_TST_CTRL2, 0); 3530 3531 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); 3532 pci_write_config_word(hw->pdev, PCI_STATUS, 3533 pci_status | PCI_STATUS_ERROR_BITS); 3534 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3535 skge_write8(hw, B0_CTST, CS_MRST_CLR); 3536 3537 /* restore CLK_RUN bits (for Yukon-Lite) */ 3538 skge_write16(hw, B0_CTST, 3539 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA)); 3540 3541 hw->chip_id = skge_read8(hw, B2_CHIP_ID); 3542 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; 3543 pmd_type = skge_read8(hw, B2_PMD_TYP); 3544 hw->copper = (pmd_type == 'T' || pmd_type == '1'); 3545 3546 switch (hw->chip_id) { 3547 case CHIP_ID_GENESIS: 3548 #ifdef CONFIG_SKGE_GENESIS 3549 switch (hw->phy_type) { 3550 case SK_PHY_XMAC: 3551 hw->phy_addr = PHY_ADDR_XMAC; 3552 break; 3553 case SK_PHY_BCOM: 3554 hw->phy_addr = PHY_ADDR_BCOM; 3555 break; 3556 default: 3557 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", 3558 hw->phy_type); 3559 return -EOPNOTSUPP; 3560 } 3561 break; 3562 #else 3563 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n"); 3564 return -EOPNOTSUPP; 3565 #endif 3566 3567 case CHIP_ID_YUKON: 3568 case CHIP_ID_YUKON_LITE: 3569 case CHIP_ID_YUKON_LP: 3570 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') 3571 hw->copper = 1; 3572 3573 hw->phy_addr = PHY_ADDR_MARV; 3574 break; 3575 3576 default: 3577 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3578 hw->chip_id); 3579 return -EOPNOTSUPP; 3580 } 3581 3582 mac_cfg = skge_read8(hw, B2_MAC_CFG); 3583 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; 3584 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; 3585 3586 /* read the adapters RAM size */ 3587 t8 = skge_read8(hw, B2_E_0); 3588 if (is_genesis(hw)) { 3589 if (t8 == 3) { 3590 /* special case: 4 x 64k x 36, offset = 0x80000 */ 3591 hw->ram_size = 0x100000; 3592 hw->ram_offset = 0x80000; 3593 } else 3594 hw->ram_size = t8 * 512; 3595 } else if (t8 == 0) 3596 hw->ram_size = 0x20000; 3597 else 3598 hw->ram_size = t8 * 4096; 3599 3600 hw->intr_mask = IS_HW_ERR; 3601 3602 /* Use PHY IRQ for all but fiber based Genesis board */ 3603 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)) 3604 hw->intr_mask |= IS_EXT_REG; 3605 3606 if (is_genesis(hw)) 3607 genesis_init(hw); 3608 else { 3609 /* switch power to VCC (WA for VAUX problem) */ 3610 skge_write8(hw, B0_POWER_CTRL, 3611 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 3612 3613 /* avoid boards with stuck Hardware error bits */ 3614 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && 3615 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { 3616 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n"); 3617 hw->intr_mask &= ~IS_HW_ERR; 3618 } 3619 3620 /* Clear PHY COMA */ 3621 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3622 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); 3623 reg &= ~PCI_PHY_COMA; 3624 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); 3625 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3626 3627 3628 for (i = 0; i < hw->ports; i++) { 3629 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3630 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3631 } 3632 } 3633 3634 /* turn off hardware timer (unused) */ 3635 skge_write8(hw, B2_TI_CTRL, TIM_STOP); 3636 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3637 skge_write8(hw, B0_LED, LED_STAT_ON); 3638 3639 /* enable the Tx Arbiters */ 3640 for (i = 0; i < hw->ports; i++) 3641 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3642 3643 /* Initialize ram interface */ 3644 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); 3645 3646 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); 3647 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); 3648 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); 3649 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); 3650 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); 3651 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); 3652 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); 3653 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); 3654 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); 3655 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); 3656 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); 3657 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); 3658 3659 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); 3660 3661 /* Set interrupt moderation for Transmit only 3662 * Receive interrupts avoided by NAPI 3663 */ 3664 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); 3665 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); 3666 skge_write32(hw, B2_IRQM_CTRL, TIM_START); 3667 3668 /* Leave irq disabled until first port is brought up. */ 3669 skge_write32(hw, B0_IMSK, 0); 3670 3671 for (i = 0; i < hw->ports; i++) { 3672 if (is_genesis(hw)) 3673 genesis_reset(hw, i); 3674 else 3675 yukon_reset(hw, i); 3676 } 3677 3678 return 0; 3679 } 3680 3681 3682 #ifdef CONFIG_SKGE_DEBUG 3683 3684 static struct dentry *skge_debug; 3685 3686 static int skge_debug_show(struct seq_file *seq, void *v) 3687 { 3688 struct net_device *dev = seq->private; 3689 const struct skge_port *skge = netdev_priv(dev); 3690 const struct skge_hw *hw = skge->hw; 3691 const struct skge_element *e; 3692 3693 if (!netif_running(dev)) 3694 return -ENETDOWN; 3695 3696 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC), 3697 skge_read32(hw, B0_IMSK)); 3698 3699 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring)); 3700 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { 3701 const struct skge_tx_desc *t = e->desc; 3702 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n", 3703 t->control, t->dma_hi, t->dma_lo, t->status, 3704 t->csum_offs, t->csum_write, t->csum_start); 3705 } 3706 3707 seq_puts(seq, "\nRx Ring:\n"); 3708 for (e = skge->rx_ring.to_clean; ; e = e->next) { 3709 const struct skge_rx_desc *r = e->desc; 3710 3711 if (r->control & BMU_OWN) 3712 break; 3713 3714 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n", 3715 r->control, r->dma_hi, r->dma_lo, r->status, 3716 r->timestamp, r->csum1, r->csum1_start); 3717 } 3718 3719 return 0; 3720 } 3721 DEFINE_SHOW_ATTRIBUTE(skge_debug); 3722 3723 /* 3724 * Use network device events to create/remove/rename 3725 * debugfs file entries 3726 */ 3727 static int skge_device_event(struct notifier_block *unused, 3728 unsigned long event, void *ptr) 3729 { 3730 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3731 struct skge_port *skge; 3732 3733 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug) 3734 goto done; 3735 3736 skge = netdev_priv(dev); 3737 switch (event) { 3738 case NETDEV_CHANGENAME: 3739 if (skge->debugfs) 3740 skge->debugfs = debugfs_rename(skge_debug, 3741 skge->debugfs, 3742 skge_debug, dev->name); 3743 break; 3744 3745 case NETDEV_GOING_DOWN: 3746 debugfs_remove(skge->debugfs); 3747 skge->debugfs = NULL; 3748 break; 3749 3750 case NETDEV_UP: 3751 skge->debugfs = debugfs_create_file(dev->name, 0444, skge_debug, 3752 dev, &skge_debug_fops); 3753 break; 3754 } 3755 3756 done: 3757 return NOTIFY_DONE; 3758 } 3759 3760 static struct notifier_block skge_notifier = { 3761 .notifier_call = skge_device_event, 3762 }; 3763 3764 3765 static __init void skge_debug_init(void) 3766 { 3767 skge_debug = debugfs_create_dir("skge", NULL); 3768 3769 register_netdevice_notifier(&skge_notifier); 3770 } 3771 3772 static __exit void skge_debug_cleanup(void) 3773 { 3774 if (skge_debug) { 3775 unregister_netdevice_notifier(&skge_notifier); 3776 debugfs_remove(skge_debug); 3777 skge_debug = NULL; 3778 } 3779 } 3780 3781 #else 3782 #define skge_debug_init() 3783 #define skge_debug_cleanup() 3784 #endif 3785 3786 static const struct net_device_ops skge_netdev_ops = { 3787 .ndo_open = skge_up, 3788 .ndo_stop = skge_down, 3789 .ndo_start_xmit = skge_xmit_frame, 3790 .ndo_do_ioctl = skge_ioctl, 3791 .ndo_get_stats = skge_get_stats, 3792 .ndo_tx_timeout = skge_tx_timeout, 3793 .ndo_change_mtu = skge_change_mtu, 3794 .ndo_validate_addr = eth_validate_addr, 3795 .ndo_set_rx_mode = skge_set_multicast, 3796 .ndo_set_mac_address = skge_set_mac_address, 3797 #ifdef CONFIG_NET_POLL_CONTROLLER 3798 .ndo_poll_controller = skge_netpoll, 3799 #endif 3800 }; 3801 3802 3803 /* Initialize network device */ 3804 static struct net_device *skge_devinit(struct skge_hw *hw, int port, 3805 int highmem) 3806 { 3807 struct skge_port *skge; 3808 struct net_device *dev = alloc_etherdev(sizeof(*skge)); 3809 3810 if (!dev) 3811 return NULL; 3812 3813 SET_NETDEV_DEV(dev, &hw->pdev->dev); 3814 dev->netdev_ops = &skge_netdev_ops; 3815 dev->ethtool_ops = &skge_ethtool_ops; 3816 dev->watchdog_timeo = TX_WATCHDOG; 3817 dev->irq = hw->pdev->irq; 3818 3819 /* MTU range: 60 - 9000 */ 3820 dev->min_mtu = ETH_ZLEN; 3821 dev->max_mtu = ETH_JUMBO_MTU; 3822 3823 if (highmem) 3824 dev->features |= NETIF_F_HIGHDMA; 3825 3826 skge = netdev_priv(dev); 3827 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT); 3828 skge->netdev = dev; 3829 skge->hw = hw; 3830 skge->msg_enable = netif_msg_init(debug, default_msg); 3831 3832 skge->tx_ring.count = DEFAULT_TX_RING_SIZE; 3833 skge->rx_ring.count = DEFAULT_RX_RING_SIZE; 3834 3835 /* Auto speed and flow control */ 3836 skge->autoneg = AUTONEG_ENABLE; 3837 skge->flow_control = FLOW_MODE_SYM_OR_REM; 3838 skge->duplex = -1; 3839 skge->speed = -1; 3840 skge->advertising = skge_supported_modes(hw); 3841 3842 if (device_can_wakeup(&hw->pdev->dev)) { 3843 skge->wol = wol_supported(hw) & WAKE_MAGIC; 3844 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); 3845 } 3846 3847 hw->dev[port] = dev; 3848 3849 skge->port = port; 3850 3851 /* Only used for Genesis XMAC */ 3852 if (is_genesis(hw)) 3853 timer_setup(&skge->link_timer, xm_link_timer, 0); 3854 else { 3855 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 3856 NETIF_F_RXCSUM; 3857 dev->features |= dev->hw_features; 3858 } 3859 3860 /* read the mac address */ 3861 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); 3862 3863 return dev; 3864 } 3865 3866 static void skge_show_addr(struct net_device *dev) 3867 { 3868 const struct skge_port *skge = netdev_priv(dev); 3869 3870 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr); 3871 } 3872 3873 static int only_32bit_dma; 3874 3875 static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3876 { 3877 struct net_device *dev, *dev1; 3878 struct skge_hw *hw; 3879 int err, using_dac = 0; 3880 3881 err = pci_enable_device(pdev); 3882 if (err) { 3883 dev_err(&pdev->dev, "cannot enable PCI device\n"); 3884 goto err_out; 3885 } 3886 3887 err = pci_request_regions(pdev, DRV_NAME); 3888 if (err) { 3889 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 3890 goto err_out_disable_pdev; 3891 } 3892 3893 pci_set_master(pdev); 3894 3895 if (!only_32bit_dma && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 3896 using_dac = 1; 3897 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 3898 } else if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) { 3899 using_dac = 0; 3900 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 3901 } 3902 3903 if (err) { 3904 dev_err(&pdev->dev, "no usable DMA configuration\n"); 3905 goto err_out_free_regions; 3906 } 3907 3908 #ifdef __BIG_ENDIAN 3909 /* byte swap descriptors in hardware */ 3910 { 3911 u32 reg; 3912 3913 pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 3914 reg |= PCI_REV_DESC; 3915 pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 3916 } 3917 #endif 3918 3919 err = -ENOMEM; 3920 /* space for skge@pci:0000:04:00.0 */ 3921 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 3922 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 3923 if (!hw) 3924 goto err_out_free_regions; 3925 3926 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 3927 3928 hw->pdev = pdev; 3929 spin_lock_init(&hw->hw_lock); 3930 spin_lock_init(&hw->phy_lock); 3931 tasklet_setup(&hw->phy_task, skge_extirq); 3932 3933 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000); 3934 if (!hw->regs) { 3935 dev_err(&pdev->dev, "cannot map device registers\n"); 3936 goto err_out_free_hw; 3937 } 3938 3939 err = skge_reset(hw); 3940 if (err) 3941 goto err_out_iounmap; 3942 3943 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n", 3944 DRV_VERSION, 3945 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq, 3946 skge_board_name(hw), hw->chip_rev); 3947 3948 dev = skge_devinit(hw, 0, using_dac); 3949 if (!dev) { 3950 err = -ENOMEM; 3951 goto err_out_led_off; 3952 } 3953 3954 /* Some motherboards are broken and has zero in ROM. */ 3955 if (!is_valid_ether_addr(dev->dev_addr)) 3956 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n"); 3957 3958 err = register_netdev(dev); 3959 if (err) { 3960 dev_err(&pdev->dev, "cannot register net device\n"); 3961 goto err_out_free_netdev; 3962 } 3963 3964 skge_show_addr(dev); 3965 3966 if (hw->ports > 1) { 3967 dev1 = skge_devinit(hw, 1, using_dac); 3968 if (!dev1) { 3969 err = -ENOMEM; 3970 goto err_out_unregister; 3971 } 3972 3973 err = register_netdev(dev1); 3974 if (err) { 3975 dev_err(&pdev->dev, "cannot register second net device\n"); 3976 goto err_out_free_dev1; 3977 } 3978 3979 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, 3980 hw->irq_name, hw); 3981 if (err) { 3982 dev_err(&pdev->dev, "cannot assign irq %d\n", 3983 pdev->irq); 3984 goto err_out_unregister_dev1; 3985 } 3986 3987 skge_show_addr(dev1); 3988 } 3989 pci_set_drvdata(pdev, hw); 3990 3991 return 0; 3992 3993 err_out_unregister_dev1: 3994 unregister_netdev(dev1); 3995 err_out_free_dev1: 3996 free_netdev(dev1); 3997 err_out_unregister: 3998 unregister_netdev(dev); 3999 err_out_free_netdev: 4000 free_netdev(dev); 4001 err_out_led_off: 4002 skge_write16(hw, B0_LED, LED_STAT_OFF); 4003 err_out_iounmap: 4004 iounmap(hw->regs); 4005 err_out_free_hw: 4006 kfree(hw); 4007 err_out_free_regions: 4008 pci_release_regions(pdev); 4009 err_out_disable_pdev: 4010 pci_disable_device(pdev); 4011 err_out: 4012 return err; 4013 } 4014 4015 static void skge_remove(struct pci_dev *pdev) 4016 { 4017 struct skge_hw *hw = pci_get_drvdata(pdev); 4018 struct net_device *dev0, *dev1; 4019 4020 if (!hw) 4021 return; 4022 4023 dev1 = hw->dev[1]; 4024 if (dev1) 4025 unregister_netdev(dev1); 4026 dev0 = hw->dev[0]; 4027 unregister_netdev(dev0); 4028 4029 tasklet_kill(&hw->phy_task); 4030 4031 spin_lock_irq(&hw->hw_lock); 4032 hw->intr_mask = 0; 4033 4034 if (hw->ports > 1) { 4035 skge_write32(hw, B0_IMSK, 0); 4036 skge_read32(hw, B0_IMSK); 4037 } 4038 spin_unlock_irq(&hw->hw_lock); 4039 4040 skge_write16(hw, B0_LED, LED_STAT_OFF); 4041 skge_write8(hw, B0_CTST, CS_RST_SET); 4042 4043 if (hw->ports > 1) 4044 free_irq(pdev->irq, hw); 4045 pci_release_regions(pdev); 4046 pci_disable_device(pdev); 4047 if (dev1) 4048 free_netdev(dev1); 4049 free_netdev(dev0); 4050 4051 iounmap(hw->regs); 4052 kfree(hw); 4053 } 4054 4055 #ifdef CONFIG_PM_SLEEP 4056 static int skge_suspend(struct device *dev) 4057 { 4058 struct skge_hw *hw = dev_get_drvdata(dev); 4059 int i; 4060 4061 if (!hw) 4062 return 0; 4063 4064 for (i = 0; i < hw->ports; i++) { 4065 struct net_device *dev = hw->dev[i]; 4066 struct skge_port *skge = netdev_priv(dev); 4067 4068 if (netif_running(dev)) 4069 skge_down(dev); 4070 4071 if (skge->wol) 4072 skge_wol_init(skge); 4073 } 4074 4075 skge_write32(hw, B0_IMSK, 0); 4076 4077 return 0; 4078 } 4079 4080 static int skge_resume(struct device *dev) 4081 { 4082 struct skge_hw *hw = dev_get_drvdata(dev); 4083 int i, err; 4084 4085 if (!hw) 4086 return 0; 4087 4088 err = skge_reset(hw); 4089 if (err) 4090 goto out; 4091 4092 for (i = 0; i < hw->ports; i++) { 4093 struct net_device *dev = hw->dev[i]; 4094 4095 if (netif_running(dev)) { 4096 err = skge_up(dev); 4097 4098 if (err) { 4099 netdev_err(dev, "could not up: %d\n", err); 4100 dev_close(dev); 4101 goto out; 4102 } 4103 } 4104 } 4105 out: 4106 return err; 4107 } 4108 4109 static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume); 4110 #define SKGE_PM_OPS (&skge_pm_ops) 4111 4112 #else 4113 4114 #define SKGE_PM_OPS NULL 4115 #endif /* CONFIG_PM_SLEEP */ 4116 4117 static void skge_shutdown(struct pci_dev *pdev) 4118 { 4119 struct skge_hw *hw = pci_get_drvdata(pdev); 4120 int i; 4121 4122 if (!hw) 4123 return; 4124 4125 for (i = 0; i < hw->ports; i++) { 4126 struct net_device *dev = hw->dev[i]; 4127 struct skge_port *skge = netdev_priv(dev); 4128 4129 if (skge->wol) 4130 skge_wol_init(skge); 4131 } 4132 4133 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 4134 pci_set_power_state(pdev, PCI_D3hot); 4135 } 4136 4137 static struct pci_driver skge_driver = { 4138 .name = DRV_NAME, 4139 .id_table = skge_id_table, 4140 .probe = skge_probe, 4141 .remove = skge_remove, 4142 .shutdown = skge_shutdown, 4143 .driver.pm = SKGE_PM_OPS, 4144 }; 4145 4146 static const struct dmi_system_id skge_32bit_dma_boards[] = { 4147 { 4148 .ident = "Gigabyte nForce boards", 4149 .matches = { 4150 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"), 4151 DMI_MATCH(DMI_BOARD_NAME, "nForce"), 4152 }, 4153 }, 4154 { 4155 .ident = "ASUS P5NSLI", 4156 .matches = { 4157 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 4158 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI") 4159 }, 4160 }, 4161 { 4162 .ident = "FUJITSU SIEMENS A8NE-FM", 4163 .matches = { 4164 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."), 4165 DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM") 4166 }, 4167 }, 4168 {} 4169 }; 4170 4171 static int __init skge_init_module(void) 4172 { 4173 if (dmi_check_system(skge_32bit_dma_boards)) 4174 only_32bit_dma = 1; 4175 skge_debug_init(); 4176 return pci_register_driver(&skge_driver); 4177 } 4178 4179 static void __exit skge_cleanup_module(void) 4180 { 4181 pci_unregister_driver(&skge_driver); 4182 skge_debug_cleanup(); 4183 } 4184 4185 module_init(skge_init_module); 4186 module_exit(skge_cleanup_module); 4187