1 /* 2 * PXA168 ethernet driver. 3 * Most of the code is derived from mv643xx ethernet driver. 4 * 5 * Copyright (C) 2010 Marvell International Ltd. 6 * Sachin Sanap <ssanap@marvell.com> 7 * Zhangfei Gao <zgao6@marvell.com> 8 * Philip Rakity <prakity@marvell.com> 9 * Mark Brown <markb@marvell.com> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 2 14 * of the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 */ 25 26 #include <linux/init.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/in.h> 29 #include <linux/ip.h> 30 #include <linux/tcp.h> 31 #include <linux/udp.h> 32 #include <linux/etherdevice.h> 33 #include <linux/bitops.h> 34 #include <linux/delay.h> 35 #include <linux/ethtool.h> 36 #include <linux/platform_device.h> 37 #include <linux/module.h> 38 #include <linux/kernel.h> 39 #include <linux/workqueue.h> 40 #include <linux/clk.h> 41 #include <linux/phy.h> 42 #include <linux/io.h> 43 #include <linux/interrupt.h> 44 #include <linux/types.h> 45 #include <asm/pgtable.h> 46 #include <asm/system.h> 47 #include <asm/cacheflush.h> 48 #include <linux/pxa168_eth.h> 49 50 #define DRIVER_NAME "pxa168-eth" 51 #define DRIVER_VERSION "0.3" 52 53 /* 54 * Registers 55 */ 56 57 #define PHY_ADDRESS 0x0000 58 #define SMI 0x0010 59 #define PORT_CONFIG 0x0400 60 #define PORT_CONFIG_EXT 0x0408 61 #define PORT_COMMAND 0x0410 62 #define PORT_STATUS 0x0418 63 #define HTPR 0x0428 64 #define SDMA_CONFIG 0x0440 65 #define SDMA_CMD 0x0448 66 #define INT_CAUSE 0x0450 67 #define INT_W_CLEAR 0x0454 68 #define INT_MASK 0x0458 69 #define ETH_F_RX_DESC_0 0x0480 70 #define ETH_C_RX_DESC_0 0x04A0 71 #define ETH_C_TX_DESC_1 0x04E4 72 73 /* smi register */ 74 #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */ 75 #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */ 76 #define SMI_OP_W (0 << 26) /* Write operation */ 77 #define SMI_OP_R (1 << 26) /* Read operation */ 78 79 #define PHY_WAIT_ITERATIONS 10 80 81 #define PXA168_ETH_PHY_ADDR_DEFAULT 0 82 /* RX & TX descriptor command */ 83 #define BUF_OWNED_BY_DMA (1 << 31) 84 85 /* RX descriptor status */ 86 #define RX_EN_INT (1 << 23) 87 #define RX_FIRST_DESC (1 << 17) 88 #define RX_LAST_DESC (1 << 16) 89 #define RX_ERROR (1 << 15) 90 91 /* TX descriptor command */ 92 #define TX_EN_INT (1 << 23) 93 #define TX_GEN_CRC (1 << 22) 94 #define TX_ZERO_PADDING (1 << 18) 95 #define TX_FIRST_DESC (1 << 17) 96 #define TX_LAST_DESC (1 << 16) 97 #define TX_ERROR (1 << 15) 98 99 /* SDMA_CMD */ 100 #define SDMA_CMD_AT (1 << 31) 101 #define SDMA_CMD_TXDL (1 << 24) 102 #define SDMA_CMD_TXDH (1 << 23) 103 #define SDMA_CMD_AR (1 << 15) 104 #define SDMA_CMD_ERD (1 << 7) 105 106 /* Bit definitions of the Port Config Reg */ 107 #define PCR_HS (1 << 12) 108 #define PCR_EN (1 << 7) 109 #define PCR_PM (1 << 0) 110 111 /* Bit definitions of the Port Config Extend Reg */ 112 #define PCXR_2BSM (1 << 28) 113 #define PCXR_DSCP_EN (1 << 21) 114 #define PCXR_MFL_1518 (0 << 14) 115 #define PCXR_MFL_1536 (1 << 14) 116 #define PCXR_MFL_2048 (2 << 14) 117 #define PCXR_MFL_64K (3 << 14) 118 #define PCXR_FLP (1 << 11) 119 #define PCXR_PRIO_TX_OFF 3 120 #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF) 121 122 /* Bit definitions of the SDMA Config Reg */ 123 #define SDCR_BSZ_OFF 12 124 #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF) 125 #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF) 126 #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF) 127 #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF) 128 #define SDCR_BLMR (1 << 6) 129 #define SDCR_BLMT (1 << 7) 130 #define SDCR_RIFB (1 << 9) 131 #define SDCR_RC_OFF 2 132 #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) 133 134 /* 135 * Bit definitions of the Interrupt Cause Reg 136 * and Interrupt MASK Reg is the same 137 */ 138 #define ICR_RXBUF (1 << 0) 139 #define ICR_TXBUF_H (1 << 2) 140 #define ICR_TXBUF_L (1 << 3) 141 #define ICR_TXEND_H (1 << 6) 142 #define ICR_TXEND_L (1 << 7) 143 #define ICR_RXERR (1 << 8) 144 #define ICR_TXERR_H (1 << 10) 145 #define ICR_TXERR_L (1 << 11) 146 #define ICR_TX_UDR (1 << 13) 147 #define ICR_MII_CH (1 << 28) 148 149 #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ 150 ICR_TXERR_H | ICR_TXERR_L |\ 151 ICR_TXEND_H | ICR_TXEND_L |\ 152 ICR_RXBUF | ICR_RXERR | ICR_MII_CH) 153 154 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ 155 156 #define NUM_RX_DESCS 64 157 #define NUM_TX_DESCS 64 158 159 #define HASH_ADD 0 160 #define HASH_DELETE 1 161 #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ 162 #define HOP_NUMBER 12 163 164 /* Bit definitions for Port status */ 165 #define PORT_SPEED_100 (1 << 0) 166 #define FULL_DUPLEX (1 << 1) 167 #define FLOW_CONTROL_ENABLED (1 << 2) 168 #define LINK_UP (1 << 3) 169 170 /* Bit definitions for work to be done */ 171 #define WORK_LINK (1 << 0) 172 #define WORK_TX_DONE (1 << 1) 173 174 /* 175 * Misc definitions. 176 */ 177 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 178 179 struct rx_desc { 180 u32 cmd_sts; /* Descriptor command status */ 181 u16 byte_cnt; /* Descriptor buffer byte count */ 182 u16 buf_size; /* Buffer size */ 183 u32 buf_ptr; /* Descriptor buffer pointer */ 184 u32 next_desc_ptr; /* Next descriptor pointer */ 185 }; 186 187 struct tx_desc { 188 u32 cmd_sts; /* Command/status field */ 189 u16 reserved; 190 u16 byte_cnt; /* buffer byte count */ 191 u32 buf_ptr; /* pointer to buffer for this descriptor */ 192 u32 next_desc_ptr; /* Pointer to next descriptor */ 193 }; 194 195 struct pxa168_eth_private { 196 int port_num; /* User Ethernet port number */ 197 198 int rx_resource_err; /* Rx ring resource error flag */ 199 200 /* Next available and first returning Rx resource */ 201 int rx_curr_desc_q, rx_used_desc_q; 202 203 /* Next available and first returning Tx resource */ 204 int tx_curr_desc_q, tx_used_desc_q; 205 206 struct rx_desc *p_rx_desc_area; 207 dma_addr_t rx_desc_dma; 208 int rx_desc_area_size; 209 struct sk_buff **rx_skb; 210 211 struct tx_desc *p_tx_desc_area; 212 dma_addr_t tx_desc_dma; 213 int tx_desc_area_size; 214 struct sk_buff **tx_skb; 215 216 struct work_struct tx_timeout_task; 217 218 struct net_device *dev; 219 struct napi_struct napi; 220 u8 work_todo; 221 int skb_size; 222 223 struct net_device_stats stats; 224 /* Size of Tx Ring per queue */ 225 int tx_ring_size; 226 /* Number of tx descriptors in use */ 227 int tx_desc_count; 228 /* Size of Rx Ring per queue */ 229 int rx_ring_size; 230 /* Number of rx descriptors in use */ 231 int rx_desc_count; 232 233 /* 234 * Used in case RX Ring is empty, which can occur when 235 * system does not have resources (skb's) 236 */ 237 struct timer_list timeout; 238 struct mii_bus *smi_bus; 239 struct phy_device *phy; 240 241 /* clock */ 242 struct clk *clk; 243 struct pxa168_eth_platform_data *pd; 244 /* 245 * Ethernet controller base address. 246 */ 247 void __iomem *base; 248 249 /* Pointer to the hardware address filter table */ 250 void *htpr; 251 dma_addr_t htpr_dma; 252 }; 253 254 struct addr_table_entry { 255 __le32 lo; 256 __le32 hi; 257 }; 258 259 /* Bit fields of a Hash Table Entry */ 260 enum hash_table_entry { 261 HASH_ENTRY_VALID = 1, 262 SKIP = 2, 263 HASH_ENTRY_RECEIVE_DISCARD = 4, 264 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2 265 }; 266 267 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd); 268 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd); 269 static int pxa168_init_hw(struct pxa168_eth_private *pep); 270 static void eth_port_reset(struct net_device *dev); 271 static void eth_port_start(struct net_device *dev); 272 static int pxa168_eth_open(struct net_device *dev); 273 static int pxa168_eth_stop(struct net_device *dev); 274 static int ethernet_phy_setup(struct net_device *dev); 275 276 static inline u32 rdl(struct pxa168_eth_private *pep, int offset) 277 { 278 return readl(pep->base + offset); 279 } 280 281 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data) 282 { 283 writel(data, pep->base + offset); 284 } 285 286 static void abort_dma(struct pxa168_eth_private *pep) 287 { 288 int delay; 289 int max_retries = 40; 290 291 do { 292 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT); 293 udelay(100); 294 295 delay = 10; 296 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT)) 297 && delay-- > 0) { 298 udelay(10); 299 } 300 } while (max_retries-- > 0 && delay <= 0); 301 302 if (max_retries <= 0) 303 printk(KERN_ERR "%s : DMA Stuck\n", __func__); 304 } 305 306 static int ethernet_phy_get(struct pxa168_eth_private *pep) 307 { 308 unsigned int reg_data; 309 310 reg_data = rdl(pep, PHY_ADDRESS); 311 312 return (reg_data >> (5 * pep->port_num)) & 0x1f; 313 } 314 315 static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr) 316 { 317 u32 reg_data; 318 int addr_shift = 5 * pep->port_num; 319 320 reg_data = rdl(pep, PHY_ADDRESS); 321 reg_data &= ~(0x1f << addr_shift); 322 reg_data |= (phy_addr & 0x1f) << addr_shift; 323 wrl(pep, PHY_ADDRESS, reg_data); 324 } 325 326 static void ethernet_phy_reset(struct pxa168_eth_private *pep) 327 { 328 int data; 329 330 data = phy_read(pep->phy, MII_BMCR); 331 if (data < 0) 332 return; 333 334 data |= BMCR_RESET; 335 if (phy_write(pep->phy, MII_BMCR, data) < 0) 336 return; 337 338 do { 339 data = phy_read(pep->phy, MII_BMCR); 340 } while (data >= 0 && data & BMCR_RESET); 341 } 342 343 static void rxq_refill(struct net_device *dev) 344 { 345 struct pxa168_eth_private *pep = netdev_priv(dev); 346 struct sk_buff *skb; 347 struct rx_desc *p_used_rx_desc; 348 int used_rx_desc; 349 350 while (pep->rx_desc_count < pep->rx_ring_size) { 351 int size; 352 353 skb = dev_alloc_skb(pep->skb_size); 354 if (!skb) 355 break; 356 if (SKB_DMA_REALIGN) 357 skb_reserve(skb, SKB_DMA_REALIGN); 358 pep->rx_desc_count++; 359 /* Get 'used' Rx descriptor */ 360 used_rx_desc = pep->rx_used_desc_q; 361 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc]; 362 size = skb->end - skb->data; 363 p_used_rx_desc->buf_ptr = dma_map_single(NULL, 364 skb->data, 365 size, 366 DMA_FROM_DEVICE); 367 p_used_rx_desc->buf_size = size; 368 pep->rx_skb[used_rx_desc] = skb; 369 370 /* Return the descriptor to DMA ownership */ 371 wmb(); 372 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; 373 wmb(); 374 375 /* Move the used descriptor pointer to the next descriptor */ 376 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size; 377 378 /* Any Rx return cancels the Rx resource error status */ 379 pep->rx_resource_err = 0; 380 381 skb_reserve(skb, ETH_HW_IP_ALIGN); 382 } 383 384 /* 385 * If RX ring is empty of SKB, set a timer to try allocating 386 * again at a later time. 387 */ 388 if (pep->rx_desc_count == 0) { 389 pep->timeout.expires = jiffies + (HZ / 10); 390 add_timer(&pep->timeout); 391 } 392 } 393 394 static inline void rxq_refill_timer_wrapper(unsigned long data) 395 { 396 struct pxa168_eth_private *pep = (void *)data; 397 napi_schedule(&pep->napi); 398 } 399 400 static inline u8 flip_8_bits(u8 x) 401 { 402 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1) 403 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3) 404 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1) 405 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3); 406 } 407 408 static void nibble_swap_every_byte(unsigned char *mac_addr) 409 { 410 int i; 411 for (i = 0; i < ETH_ALEN; i++) { 412 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) | 413 ((mac_addr[i] & 0xf0) >> 4); 414 } 415 } 416 417 static void inverse_every_nibble(unsigned char *mac_addr) 418 { 419 int i; 420 for (i = 0; i < ETH_ALEN; i++) 421 mac_addr[i] = flip_8_bits(mac_addr[i]); 422 } 423 424 /* 425 * ---------------------------------------------------------------------------- 426 * This function will calculate the hash function of the address. 427 * Inputs 428 * mac_addr_orig - MAC address. 429 * Outputs 430 * return the calculated entry. 431 */ 432 static u32 hash_function(unsigned char *mac_addr_orig) 433 { 434 u32 hash_result; 435 u32 addr0; 436 u32 addr1; 437 u32 addr2; 438 u32 addr3; 439 unsigned char mac_addr[ETH_ALEN]; 440 441 /* Make a copy of MAC address since we are going to performe bit 442 * operations on it 443 */ 444 memcpy(mac_addr, mac_addr_orig, ETH_ALEN); 445 446 nibble_swap_every_byte(mac_addr); 447 inverse_every_nibble(mac_addr); 448 449 addr0 = (mac_addr[5] >> 2) & 0x3f; 450 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2); 451 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1; 452 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8); 453 454 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); 455 hash_result = hash_result & 0x07ff; 456 return hash_result; 457 } 458 459 /* 460 * ---------------------------------------------------------------------------- 461 * This function will add/del an entry to the address table. 462 * Inputs 463 * pep - ETHERNET . 464 * mac_addr - MAC address. 465 * skip - if 1, skip this address.Used in case of deleting an entry which is a 466 * part of chain in the hash table.We can't just delete the entry since 467 * that will break the chain.We need to defragment the tables time to 468 * time. 469 * rd - 0 Discard packet upon match. 470 * - 1 Receive packet upon match. 471 * Outputs 472 * address table entry is added/deleted. 473 * 0 if success. 474 * -ENOSPC if table full 475 */ 476 static int add_del_hash_entry(struct pxa168_eth_private *pep, 477 unsigned char *mac_addr, 478 u32 rd, u32 skip, int del) 479 { 480 struct addr_table_entry *entry, *start; 481 u32 new_high; 482 u32 new_low; 483 u32 i; 484 485 new_low = (((mac_addr[1] >> 4) & 0xf) << 15) 486 | (((mac_addr[1] >> 0) & 0xf) << 11) 487 | (((mac_addr[0] >> 4) & 0xf) << 7) 488 | (((mac_addr[0] >> 0) & 0xf) << 3) 489 | (((mac_addr[3] >> 4) & 0x1) << 31) 490 | (((mac_addr[3] >> 0) & 0xf) << 27) 491 | (((mac_addr[2] >> 4) & 0xf) << 23) 492 | (((mac_addr[2] >> 0) & 0xf) << 19) 493 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT) 494 | HASH_ENTRY_VALID; 495 496 new_high = (((mac_addr[5] >> 4) & 0xf) << 15) 497 | (((mac_addr[5] >> 0) & 0xf) << 11) 498 | (((mac_addr[4] >> 4) & 0xf) << 7) 499 | (((mac_addr[4] >> 0) & 0xf) << 3) 500 | (((mac_addr[3] >> 5) & 0x7) << 0); 501 502 /* 503 * Pick the appropriate table, start scanning for free/reusable 504 * entries at the index obtained by hashing the specified MAC address 505 */ 506 start = pep->htpr; 507 entry = start + hash_function(mac_addr); 508 for (i = 0; i < HOP_NUMBER; i++) { 509 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) { 510 break; 511 } else { 512 /* if same address put in same position */ 513 if (((le32_to_cpu(entry->lo) & 0xfffffff8) == 514 (new_low & 0xfffffff8)) && 515 (le32_to_cpu(entry->hi) == new_high)) { 516 break; 517 } 518 } 519 if (entry == start + 0x7ff) 520 entry = start; 521 else 522 entry++; 523 } 524 525 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) && 526 (le32_to_cpu(entry->hi) != new_high) && del) 527 return 0; 528 529 if (i == HOP_NUMBER) { 530 if (!del) { 531 printk(KERN_INFO "%s: table section is full, need to " 532 "move to 16kB implementation?\n", 533 __FILE__); 534 return -ENOSPC; 535 } else 536 return 0; 537 } 538 539 /* 540 * Update the selected entry 541 */ 542 if (del) { 543 entry->hi = 0; 544 entry->lo = 0; 545 } else { 546 entry->hi = cpu_to_le32(new_high); 547 entry->lo = cpu_to_le32(new_low); 548 } 549 550 return 0; 551 } 552 553 /* 554 * ---------------------------------------------------------------------------- 555 * Create an addressTable entry from MAC address info 556 * found in the specifed net_device struct 557 * 558 * Input : pointer to ethernet interface network device structure 559 * Output : N/A 560 */ 561 static void update_hash_table_mac_address(struct pxa168_eth_private *pep, 562 unsigned char *oaddr, 563 unsigned char *addr) 564 { 565 /* Delete old entry */ 566 if (oaddr) 567 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE); 568 /* Add new entry */ 569 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD); 570 } 571 572 static int init_hash_table(struct pxa168_eth_private *pep) 573 { 574 /* 575 * Hardware expects CPU to build a hash table based on a predefined 576 * hash function and populate it based on hardware address. The 577 * location of the hash table is identified by 32-bit pointer stored 578 * in HTPR internal register. Two possible sizes exists for the hash 579 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB 580 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support 581 * 1/2kB. 582 */ 583 /* TODO: Add support for 8kB hash table and alternative hash 584 * function.Driver can dynamically switch to them if the 1/2kB hash 585 * table is full. 586 */ 587 if (pep->htpr == NULL) { 588 pep->htpr = dma_alloc_coherent(pep->dev->dev.parent, 589 HASH_ADDR_TABLE_SIZE, 590 &pep->htpr_dma, GFP_KERNEL); 591 if (pep->htpr == NULL) 592 return -ENOMEM; 593 } 594 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); 595 wrl(pep, HTPR, pep->htpr_dma); 596 return 0; 597 } 598 599 static void pxa168_eth_set_rx_mode(struct net_device *dev) 600 { 601 struct pxa168_eth_private *pep = netdev_priv(dev); 602 struct netdev_hw_addr *ha; 603 u32 val; 604 605 val = rdl(pep, PORT_CONFIG); 606 if (dev->flags & IFF_PROMISC) 607 val |= PCR_PM; 608 else 609 val &= ~PCR_PM; 610 wrl(pep, PORT_CONFIG, val); 611 612 /* 613 * Remove the old list of MAC address and add dev->addr 614 * and multicast address. 615 */ 616 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); 617 update_hash_table_mac_address(pep, NULL, dev->dev_addr); 618 619 netdev_for_each_mc_addr(ha, dev) 620 update_hash_table_mac_address(pep, NULL, ha->addr); 621 } 622 623 static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr) 624 { 625 struct sockaddr *sa = addr; 626 struct pxa168_eth_private *pep = netdev_priv(dev); 627 unsigned char oldMac[ETH_ALEN]; 628 629 if (!is_valid_ether_addr(sa->sa_data)) 630 return -EINVAL; 631 memcpy(oldMac, dev->dev_addr, ETH_ALEN); 632 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); 633 netif_addr_lock_bh(dev); 634 update_hash_table_mac_address(pep, oldMac, dev->dev_addr); 635 netif_addr_unlock_bh(dev); 636 return 0; 637 } 638 639 static void eth_port_start(struct net_device *dev) 640 { 641 unsigned int val = 0; 642 struct pxa168_eth_private *pep = netdev_priv(dev); 643 int tx_curr_desc, rx_curr_desc; 644 645 /* Perform PHY reset, if there is a PHY. */ 646 if (pep->phy != NULL) { 647 struct ethtool_cmd cmd; 648 649 pxa168_get_settings(pep->dev, &cmd); 650 ethernet_phy_reset(pep); 651 pxa168_set_settings(pep->dev, &cmd); 652 } 653 654 /* Assignment of Tx CTRP of given queue */ 655 tx_curr_desc = pep->tx_curr_desc_q; 656 wrl(pep, ETH_C_TX_DESC_1, 657 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc))); 658 659 /* Assignment of Rx CRDP of given queue */ 660 rx_curr_desc = pep->rx_curr_desc_q; 661 wrl(pep, ETH_C_RX_DESC_0, 662 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); 663 664 wrl(pep, ETH_F_RX_DESC_0, 665 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); 666 667 /* Clear all interrupts */ 668 wrl(pep, INT_CAUSE, 0); 669 670 /* Enable all interrupts for receive, transmit and error. */ 671 wrl(pep, INT_MASK, ALL_INTS); 672 673 val = rdl(pep, PORT_CONFIG); 674 val |= PCR_EN; 675 wrl(pep, PORT_CONFIG, val); 676 677 /* Start RX DMA engine */ 678 val = rdl(pep, SDMA_CMD); 679 val |= SDMA_CMD_ERD; 680 wrl(pep, SDMA_CMD, val); 681 } 682 683 static void eth_port_reset(struct net_device *dev) 684 { 685 struct pxa168_eth_private *pep = netdev_priv(dev); 686 unsigned int val = 0; 687 688 /* Stop all interrupts for receive, transmit and error. */ 689 wrl(pep, INT_MASK, 0); 690 691 /* Clear all interrupts */ 692 wrl(pep, INT_CAUSE, 0); 693 694 /* Stop RX DMA */ 695 val = rdl(pep, SDMA_CMD); 696 val &= ~SDMA_CMD_ERD; /* abort dma command */ 697 698 /* Abort any transmit and receive operations and put DMA 699 * in idle state. 700 */ 701 abort_dma(pep); 702 703 /* Disable port */ 704 val = rdl(pep, PORT_CONFIG); 705 val &= ~PCR_EN; 706 wrl(pep, PORT_CONFIG, val); 707 } 708 709 /* 710 * txq_reclaim - Free the tx desc data for completed descriptors 711 * If force is non-zero, frees uncompleted descriptors as well 712 */ 713 static int txq_reclaim(struct net_device *dev, int force) 714 { 715 struct pxa168_eth_private *pep = netdev_priv(dev); 716 struct tx_desc *desc; 717 u32 cmd_sts; 718 struct sk_buff *skb; 719 int tx_index; 720 dma_addr_t addr; 721 int count; 722 int released = 0; 723 724 netif_tx_lock(dev); 725 726 pep->work_todo &= ~WORK_TX_DONE; 727 while (pep->tx_desc_count > 0) { 728 tx_index = pep->tx_used_desc_q; 729 desc = &pep->p_tx_desc_area[tx_index]; 730 cmd_sts = desc->cmd_sts; 731 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) { 732 if (released > 0) { 733 goto txq_reclaim_end; 734 } else { 735 released = -1; 736 goto txq_reclaim_end; 737 } 738 } 739 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size; 740 pep->tx_desc_count--; 741 addr = desc->buf_ptr; 742 count = desc->byte_cnt; 743 skb = pep->tx_skb[tx_index]; 744 if (skb) 745 pep->tx_skb[tx_index] = NULL; 746 747 if (cmd_sts & TX_ERROR) { 748 if (net_ratelimit()) 749 printk(KERN_ERR "%s: Error in TX\n", dev->name); 750 dev->stats.tx_errors++; 751 } 752 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); 753 if (skb) 754 dev_kfree_skb_irq(skb); 755 released++; 756 } 757 txq_reclaim_end: 758 netif_tx_unlock(dev); 759 return released; 760 } 761 762 static void pxa168_eth_tx_timeout(struct net_device *dev) 763 { 764 struct pxa168_eth_private *pep = netdev_priv(dev); 765 766 printk(KERN_INFO "%s: TX timeout desc_count %d\n", 767 dev->name, pep->tx_desc_count); 768 769 schedule_work(&pep->tx_timeout_task); 770 } 771 772 static void pxa168_eth_tx_timeout_task(struct work_struct *work) 773 { 774 struct pxa168_eth_private *pep = container_of(work, 775 struct pxa168_eth_private, 776 tx_timeout_task); 777 struct net_device *dev = pep->dev; 778 pxa168_eth_stop(dev); 779 pxa168_eth_open(dev); 780 } 781 782 static int rxq_process(struct net_device *dev, int budget) 783 { 784 struct pxa168_eth_private *pep = netdev_priv(dev); 785 struct net_device_stats *stats = &dev->stats; 786 unsigned int received_packets = 0; 787 struct sk_buff *skb; 788 789 while (budget-- > 0) { 790 int rx_next_curr_desc, rx_curr_desc, rx_used_desc; 791 struct rx_desc *rx_desc; 792 unsigned int cmd_sts; 793 794 /* Do not process Rx ring in case of Rx ring resource error */ 795 if (pep->rx_resource_err) 796 break; 797 rx_curr_desc = pep->rx_curr_desc_q; 798 rx_used_desc = pep->rx_used_desc_q; 799 rx_desc = &pep->p_rx_desc_area[rx_curr_desc]; 800 cmd_sts = rx_desc->cmd_sts; 801 rmb(); 802 if (cmd_sts & (BUF_OWNED_BY_DMA)) 803 break; 804 skb = pep->rx_skb[rx_curr_desc]; 805 pep->rx_skb[rx_curr_desc] = NULL; 806 807 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size; 808 pep->rx_curr_desc_q = rx_next_curr_desc; 809 810 /* Rx descriptors exhausted. */ 811 /* Set the Rx ring resource error flag */ 812 if (rx_next_curr_desc == rx_used_desc) 813 pep->rx_resource_err = 1; 814 pep->rx_desc_count--; 815 dma_unmap_single(NULL, rx_desc->buf_ptr, 816 rx_desc->buf_size, 817 DMA_FROM_DEVICE); 818 received_packets++; 819 /* 820 * Update statistics. 821 * Note byte count includes 4 byte CRC count 822 */ 823 stats->rx_packets++; 824 stats->rx_bytes += rx_desc->byte_cnt; 825 /* 826 * In case received a packet without first / last bits on OR 827 * the error summary bit is on, the packets needs to be droped. 828 */ 829 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 830 (RX_FIRST_DESC | RX_LAST_DESC)) 831 || (cmd_sts & RX_ERROR)) { 832 833 stats->rx_dropped++; 834 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 835 (RX_FIRST_DESC | RX_LAST_DESC)) { 836 if (net_ratelimit()) 837 printk(KERN_ERR 838 "%s: Rx pkt on multiple desc\n", 839 dev->name); 840 } 841 if (cmd_sts & RX_ERROR) 842 stats->rx_errors++; 843 dev_kfree_skb_irq(skb); 844 } else { 845 /* 846 * The -4 is for the CRC in the trailer of the 847 * received packet 848 */ 849 skb_put(skb, rx_desc->byte_cnt - 4); 850 skb->protocol = eth_type_trans(skb, dev); 851 netif_receive_skb(skb); 852 } 853 } 854 /* Fill RX ring with skb's */ 855 rxq_refill(dev); 856 return received_packets; 857 } 858 859 static int pxa168_eth_collect_events(struct pxa168_eth_private *pep, 860 struct net_device *dev) 861 { 862 u32 icr; 863 int ret = 0; 864 865 icr = rdl(pep, INT_CAUSE); 866 if (icr == 0) 867 return IRQ_NONE; 868 869 wrl(pep, INT_CAUSE, ~icr); 870 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) { 871 pep->work_todo |= WORK_TX_DONE; 872 ret = 1; 873 } 874 if (icr & ICR_RXBUF) 875 ret = 1; 876 if (icr & ICR_MII_CH) { 877 pep->work_todo |= WORK_LINK; 878 ret = 1; 879 } 880 return ret; 881 } 882 883 static void handle_link_event(struct pxa168_eth_private *pep) 884 { 885 struct net_device *dev = pep->dev; 886 u32 port_status; 887 int speed; 888 int duplex; 889 int fc; 890 891 port_status = rdl(pep, PORT_STATUS); 892 if (!(port_status & LINK_UP)) { 893 if (netif_carrier_ok(dev)) { 894 printk(KERN_INFO "%s: link down\n", dev->name); 895 netif_carrier_off(dev); 896 txq_reclaim(dev, 1); 897 } 898 return; 899 } 900 if (port_status & PORT_SPEED_100) 901 speed = 100; 902 else 903 speed = 10; 904 905 duplex = (port_status & FULL_DUPLEX) ? 1 : 0; 906 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; 907 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " 908 "flow control %sabled\n", dev->name, 909 speed, duplex ? "full" : "half", fc ? "en" : "dis"); 910 if (!netif_carrier_ok(dev)) 911 netif_carrier_on(dev); 912 } 913 914 static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id) 915 { 916 struct net_device *dev = (struct net_device *)dev_id; 917 struct pxa168_eth_private *pep = netdev_priv(dev); 918 919 if (unlikely(!pxa168_eth_collect_events(pep, dev))) 920 return IRQ_NONE; 921 /* Disable interrupts */ 922 wrl(pep, INT_MASK, 0); 923 napi_schedule(&pep->napi); 924 return IRQ_HANDLED; 925 } 926 927 static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep) 928 { 929 int skb_size; 930 931 /* 932 * Reserve 2+14 bytes for an ethernet header (the hardware 933 * automatically prepends 2 bytes of dummy data to each 934 * received packet), 16 bytes for up to four VLAN tags, and 935 * 4 bytes for the trailing FCS -- 36 bytes total. 936 */ 937 skb_size = pep->dev->mtu + 36; 938 939 /* 940 * Make sure that the skb size is a multiple of 8 bytes, as 941 * the lower three bits of the receive descriptor's buffer 942 * size field are ignored by the hardware. 943 */ 944 pep->skb_size = (skb_size + 7) & ~7; 945 946 /* 947 * If NET_SKB_PAD is smaller than a cache line, 948 * netdev_alloc_skb() will cause skb->data to be misaligned 949 * to a cache line boundary. If this is the case, include 950 * some extra space to allow re-aligning the data area. 951 */ 952 pep->skb_size += SKB_DMA_REALIGN; 953 954 } 955 956 static int set_port_config_ext(struct pxa168_eth_private *pep) 957 { 958 int skb_size; 959 960 pxa168_eth_recalc_skb_size(pep); 961 if (pep->skb_size <= 1518) 962 skb_size = PCXR_MFL_1518; 963 else if (pep->skb_size <= 1536) 964 skb_size = PCXR_MFL_1536; 965 else if (pep->skb_size <= 2048) 966 skb_size = PCXR_MFL_2048; 967 else 968 skb_size = PCXR_MFL_64K; 969 970 /* Extended Port Configuration */ 971 wrl(pep, 972 PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */ 973 PCXR_DSCP_EN | /* Enable DSCP in IP */ 974 skb_size | PCXR_FLP | /* do not force link pass */ 975 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */ 976 977 return 0; 978 } 979 980 static int pxa168_init_hw(struct pxa168_eth_private *pep) 981 { 982 int err = 0; 983 984 /* Disable interrupts */ 985 wrl(pep, INT_MASK, 0); 986 wrl(pep, INT_CAUSE, 0); 987 /* Write to ICR to clear interrupts. */ 988 wrl(pep, INT_W_CLEAR, 0); 989 /* Abort any transmit and receive operations and put DMA 990 * in idle state. 991 */ 992 abort_dma(pep); 993 /* Initialize address hash table */ 994 err = init_hash_table(pep); 995 if (err) 996 return err; 997 /* SDMA configuration */ 998 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */ 999 SDCR_RIFB | /* Rx interrupt on frame */ 1000 SDCR_BLMT | /* Little endian transmit */ 1001 SDCR_BLMR | /* Little endian receive */ 1002 SDCR_RC_MAX_RETRANS); /* Max retransmit count */ 1003 /* Port Configuration */ 1004 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */ 1005 set_port_config_ext(pep); 1006 1007 return err; 1008 } 1009 1010 static int rxq_init(struct net_device *dev) 1011 { 1012 struct pxa168_eth_private *pep = netdev_priv(dev); 1013 struct rx_desc *p_rx_desc; 1014 int size = 0, i = 0; 1015 int rx_desc_num = pep->rx_ring_size; 1016 1017 /* Allocate RX skb rings */ 1018 pep->rx_skb = kmalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size, 1019 GFP_KERNEL); 1020 if (!pep->rx_skb) { 1021 printk(KERN_ERR "%s: Cannot alloc RX skb ring\n", dev->name); 1022 return -ENOMEM; 1023 } 1024 /* Allocate RX ring */ 1025 pep->rx_desc_count = 0; 1026 size = pep->rx_ring_size * sizeof(struct rx_desc); 1027 pep->rx_desc_area_size = size; 1028 pep->p_rx_desc_area = dma_alloc_coherent(pep->dev->dev.parent, size, 1029 &pep->rx_desc_dma, GFP_KERNEL); 1030 if (!pep->p_rx_desc_area) { 1031 printk(KERN_ERR "%s: Cannot alloc RX ring (size %d bytes)\n", 1032 dev->name, size); 1033 goto out; 1034 } 1035 memset((void *)pep->p_rx_desc_area, 0, size); 1036 /* initialize the next_desc_ptr links in the Rx descriptors ring */ 1037 p_rx_desc = (struct rx_desc *)pep->p_rx_desc_area; 1038 for (i = 0; i < rx_desc_num; i++) { 1039 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma + 1040 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc); 1041 } 1042 /* Save Rx desc pointer to driver struct. */ 1043 pep->rx_curr_desc_q = 0; 1044 pep->rx_used_desc_q = 0; 1045 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc); 1046 return 0; 1047 out: 1048 kfree(pep->rx_skb); 1049 return -ENOMEM; 1050 } 1051 1052 static void rxq_deinit(struct net_device *dev) 1053 { 1054 struct pxa168_eth_private *pep = netdev_priv(dev); 1055 int curr; 1056 1057 /* Free preallocated skb's on RX rings */ 1058 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) { 1059 if (pep->rx_skb[curr]) { 1060 dev_kfree_skb(pep->rx_skb[curr]); 1061 pep->rx_desc_count--; 1062 } 1063 } 1064 if (pep->rx_desc_count) 1065 printk(KERN_ERR 1066 "Error in freeing Rx Ring. %d skb's still\n", 1067 pep->rx_desc_count); 1068 /* Free RX ring */ 1069 if (pep->p_rx_desc_area) 1070 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size, 1071 pep->p_rx_desc_area, pep->rx_desc_dma); 1072 kfree(pep->rx_skb); 1073 } 1074 1075 static int txq_init(struct net_device *dev) 1076 { 1077 struct pxa168_eth_private *pep = netdev_priv(dev); 1078 struct tx_desc *p_tx_desc; 1079 int size = 0, i = 0; 1080 int tx_desc_num = pep->tx_ring_size; 1081 1082 pep->tx_skb = kmalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size, 1083 GFP_KERNEL); 1084 if (!pep->tx_skb) { 1085 printk(KERN_ERR "%s: Cannot alloc TX skb ring\n", dev->name); 1086 return -ENOMEM; 1087 } 1088 /* Allocate TX ring */ 1089 pep->tx_desc_count = 0; 1090 size = pep->tx_ring_size * sizeof(struct tx_desc); 1091 pep->tx_desc_area_size = size; 1092 pep->p_tx_desc_area = dma_alloc_coherent(pep->dev->dev.parent, size, 1093 &pep->tx_desc_dma, GFP_KERNEL); 1094 if (!pep->p_tx_desc_area) { 1095 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", 1096 dev->name, size); 1097 goto out; 1098 } 1099 memset((void *)pep->p_tx_desc_area, 0, pep->tx_desc_area_size); 1100 /* Initialize the next_desc_ptr links in the Tx descriptors ring */ 1101 p_tx_desc = (struct tx_desc *)pep->p_tx_desc_area; 1102 for (i = 0; i < tx_desc_num; i++) { 1103 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma + 1104 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc); 1105 } 1106 pep->tx_curr_desc_q = 0; 1107 pep->tx_used_desc_q = 0; 1108 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc); 1109 return 0; 1110 out: 1111 kfree(pep->tx_skb); 1112 return -ENOMEM; 1113 } 1114 1115 static void txq_deinit(struct net_device *dev) 1116 { 1117 struct pxa168_eth_private *pep = netdev_priv(dev); 1118 1119 /* Free outstanding skb's on TX ring */ 1120 txq_reclaim(dev, 1); 1121 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q); 1122 /* Free TX ring */ 1123 if (pep->p_tx_desc_area) 1124 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size, 1125 pep->p_tx_desc_area, pep->tx_desc_dma); 1126 kfree(pep->tx_skb); 1127 } 1128 1129 static int pxa168_eth_open(struct net_device *dev) 1130 { 1131 struct pxa168_eth_private *pep = netdev_priv(dev); 1132 int err; 1133 1134 err = request_irq(dev->irq, pxa168_eth_int_handler, 1135 IRQF_DISABLED, dev->name, dev); 1136 if (err) { 1137 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); 1138 return -EAGAIN; 1139 } 1140 pep->rx_resource_err = 0; 1141 err = rxq_init(dev); 1142 if (err != 0) 1143 goto out_free_irq; 1144 err = txq_init(dev); 1145 if (err != 0) 1146 goto out_free_rx_skb; 1147 pep->rx_used_desc_q = 0; 1148 pep->rx_curr_desc_q = 0; 1149 1150 /* Fill RX ring with skb's */ 1151 rxq_refill(dev); 1152 pep->rx_used_desc_q = 0; 1153 pep->rx_curr_desc_q = 0; 1154 netif_carrier_off(dev); 1155 eth_port_start(dev); 1156 napi_enable(&pep->napi); 1157 return 0; 1158 out_free_rx_skb: 1159 rxq_deinit(dev); 1160 out_free_irq: 1161 free_irq(dev->irq, dev); 1162 return err; 1163 } 1164 1165 static int pxa168_eth_stop(struct net_device *dev) 1166 { 1167 struct pxa168_eth_private *pep = netdev_priv(dev); 1168 eth_port_reset(dev); 1169 1170 /* Disable interrupts */ 1171 wrl(pep, INT_MASK, 0); 1172 wrl(pep, INT_CAUSE, 0); 1173 /* Write to ICR to clear interrupts. */ 1174 wrl(pep, INT_W_CLEAR, 0); 1175 napi_disable(&pep->napi); 1176 del_timer_sync(&pep->timeout); 1177 netif_carrier_off(dev); 1178 free_irq(dev->irq, dev); 1179 rxq_deinit(dev); 1180 txq_deinit(dev); 1181 1182 return 0; 1183 } 1184 1185 static int pxa168_eth_change_mtu(struct net_device *dev, int mtu) 1186 { 1187 int retval; 1188 struct pxa168_eth_private *pep = netdev_priv(dev); 1189 1190 if ((mtu > 9500) || (mtu < 68)) 1191 return -EINVAL; 1192 1193 dev->mtu = mtu; 1194 retval = set_port_config_ext(pep); 1195 1196 if (!netif_running(dev)) 1197 return 0; 1198 1199 /* 1200 * Stop and then re-open the interface. This will allocate RX 1201 * skbs of the new MTU. 1202 * There is a possible danger that the open will not succeed, 1203 * due to memory being full. 1204 */ 1205 pxa168_eth_stop(dev); 1206 if (pxa168_eth_open(dev)) { 1207 dev_printk(KERN_ERR, &dev->dev, 1208 "fatal error on re-opening device after " 1209 "MTU change\n"); 1210 } 1211 1212 return 0; 1213 } 1214 1215 static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep) 1216 { 1217 int tx_desc_curr; 1218 1219 tx_desc_curr = pep->tx_curr_desc_q; 1220 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size; 1221 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q); 1222 pep->tx_desc_count++; 1223 1224 return tx_desc_curr; 1225 } 1226 1227 static int pxa168_rx_poll(struct napi_struct *napi, int budget) 1228 { 1229 struct pxa168_eth_private *pep = 1230 container_of(napi, struct pxa168_eth_private, napi); 1231 struct net_device *dev = pep->dev; 1232 int work_done = 0; 1233 1234 if (unlikely(pep->work_todo & WORK_LINK)) { 1235 pep->work_todo &= ~(WORK_LINK); 1236 handle_link_event(pep); 1237 } 1238 /* 1239 * We call txq_reclaim every time since in NAPI interupts are disabled 1240 * and due to this we miss the TX_DONE interrupt,which is not updated in 1241 * interrupt status register. 1242 */ 1243 txq_reclaim(dev, 0); 1244 if (netif_queue_stopped(dev) 1245 && pep->tx_ring_size - pep->tx_desc_count > 1) { 1246 netif_wake_queue(dev); 1247 } 1248 work_done = rxq_process(dev, budget); 1249 if (work_done < budget) { 1250 napi_complete(napi); 1251 wrl(pep, INT_MASK, ALL_INTS); 1252 } 1253 1254 return work_done; 1255 } 1256 1257 static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) 1258 { 1259 struct pxa168_eth_private *pep = netdev_priv(dev); 1260 struct net_device_stats *stats = &dev->stats; 1261 struct tx_desc *desc; 1262 int tx_index; 1263 int length; 1264 1265 tx_index = eth_alloc_tx_desc_index(pep); 1266 desc = &pep->p_tx_desc_area[tx_index]; 1267 length = skb->len; 1268 pep->tx_skb[tx_index] = skb; 1269 desc->byte_cnt = length; 1270 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); 1271 1272 skb_tx_timestamp(skb); 1273 1274 wmb(); 1275 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC | 1276 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT; 1277 wmb(); 1278 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD); 1279 1280 stats->tx_bytes += length; 1281 stats->tx_packets++; 1282 dev->trans_start = jiffies; 1283 if (pep->tx_ring_size - pep->tx_desc_count <= 1) { 1284 /* We handled the current skb, but now we are out of space.*/ 1285 netif_stop_queue(dev); 1286 } 1287 1288 return NETDEV_TX_OK; 1289 } 1290 1291 static int smi_wait_ready(struct pxa168_eth_private *pep) 1292 { 1293 int i = 0; 1294 1295 /* wait for the SMI register to become available */ 1296 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) { 1297 if (i == PHY_WAIT_ITERATIONS) 1298 return -ETIMEDOUT; 1299 msleep(10); 1300 } 1301 1302 return 0; 1303 } 1304 1305 static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum) 1306 { 1307 struct pxa168_eth_private *pep = bus->priv; 1308 int i = 0; 1309 int val; 1310 1311 if (smi_wait_ready(pep)) { 1312 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n"); 1313 return -ETIMEDOUT; 1314 } 1315 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R); 1316 /* now wait for the data to be valid */ 1317 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) { 1318 if (i == PHY_WAIT_ITERATIONS) { 1319 printk(KERN_WARNING 1320 "pxa168_eth: SMI bus read not valid\n"); 1321 return -ENODEV; 1322 } 1323 msleep(10); 1324 } 1325 1326 return val & 0xffff; 1327 } 1328 1329 static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum, 1330 u16 value) 1331 { 1332 struct pxa168_eth_private *pep = bus->priv; 1333 1334 if (smi_wait_ready(pep)) { 1335 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n"); 1336 return -ETIMEDOUT; 1337 } 1338 1339 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | 1340 SMI_OP_W | (value & 0xffff)); 1341 1342 if (smi_wait_ready(pep)) { 1343 printk(KERN_ERR "pxa168_eth: SMI bus busy timeout\n"); 1344 return -ETIMEDOUT; 1345 } 1346 1347 return 0; 1348 } 1349 1350 static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, 1351 int cmd) 1352 { 1353 struct pxa168_eth_private *pep = netdev_priv(dev); 1354 if (pep->phy != NULL) 1355 return phy_mii_ioctl(pep->phy, ifr, cmd); 1356 1357 return -EOPNOTSUPP; 1358 } 1359 1360 static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr) 1361 { 1362 struct mii_bus *bus = pep->smi_bus; 1363 struct phy_device *phydev; 1364 int start; 1365 int num; 1366 int i; 1367 1368 if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) { 1369 /* Scan entire range */ 1370 start = ethernet_phy_get(pep); 1371 num = 32; 1372 } else { 1373 /* Use phy addr specific to platform */ 1374 start = phy_addr & 0x1f; 1375 num = 1; 1376 } 1377 phydev = NULL; 1378 for (i = 0; i < num; i++) { 1379 int addr = (start + i) & 0x1f; 1380 if (bus->phy_map[addr] == NULL) 1381 mdiobus_scan(bus, addr); 1382 1383 if (phydev == NULL) { 1384 phydev = bus->phy_map[addr]; 1385 if (phydev != NULL) 1386 ethernet_phy_set_addr(pep, addr); 1387 } 1388 } 1389 1390 return phydev; 1391 } 1392 1393 static void phy_init(struct pxa168_eth_private *pep, int speed, int duplex) 1394 { 1395 struct phy_device *phy = pep->phy; 1396 ethernet_phy_reset(pep); 1397 1398 phy_attach(pep->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_MII); 1399 1400 if (speed == 0) { 1401 phy->autoneg = AUTONEG_ENABLE; 1402 phy->speed = 0; 1403 phy->duplex = 0; 1404 phy->supported &= PHY_BASIC_FEATURES; 1405 phy->advertising = phy->supported | ADVERTISED_Autoneg; 1406 } else { 1407 phy->autoneg = AUTONEG_DISABLE; 1408 phy->advertising = 0; 1409 phy->speed = speed; 1410 phy->duplex = duplex; 1411 } 1412 phy_start_aneg(phy); 1413 } 1414 1415 static int ethernet_phy_setup(struct net_device *dev) 1416 { 1417 struct pxa168_eth_private *pep = netdev_priv(dev); 1418 1419 if (pep->pd->init) 1420 pep->pd->init(); 1421 pep->phy = phy_scan(pep, pep->pd->phy_addr & 0x1f); 1422 if (pep->phy != NULL) 1423 phy_init(pep, pep->pd->speed, pep->pd->duplex); 1424 update_hash_table_mac_address(pep, NULL, dev->dev_addr); 1425 1426 return 0; 1427 } 1428 1429 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1430 { 1431 struct pxa168_eth_private *pep = netdev_priv(dev); 1432 int err; 1433 1434 err = phy_read_status(pep->phy); 1435 if (err == 0) 1436 err = phy_ethtool_gset(pep->phy, cmd); 1437 1438 return err; 1439 } 1440 1441 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1442 { 1443 struct pxa168_eth_private *pep = netdev_priv(dev); 1444 1445 return phy_ethtool_sset(pep->phy, cmd); 1446 } 1447 1448 static void pxa168_get_drvinfo(struct net_device *dev, 1449 struct ethtool_drvinfo *info) 1450 { 1451 strncpy(info->driver, DRIVER_NAME, 32); 1452 strncpy(info->version, DRIVER_VERSION, 32); 1453 strncpy(info->fw_version, "N/A", 32); 1454 strncpy(info->bus_info, "N/A", 32); 1455 } 1456 1457 static const struct ethtool_ops pxa168_ethtool_ops = { 1458 .get_settings = pxa168_get_settings, 1459 .set_settings = pxa168_set_settings, 1460 .get_drvinfo = pxa168_get_drvinfo, 1461 .get_link = ethtool_op_get_link, 1462 }; 1463 1464 static const struct net_device_ops pxa168_eth_netdev_ops = { 1465 .ndo_open = pxa168_eth_open, 1466 .ndo_stop = pxa168_eth_stop, 1467 .ndo_start_xmit = pxa168_eth_start_xmit, 1468 .ndo_set_rx_mode = pxa168_eth_set_rx_mode, 1469 .ndo_set_mac_address = pxa168_eth_set_mac_address, 1470 .ndo_validate_addr = eth_validate_addr, 1471 .ndo_do_ioctl = pxa168_eth_do_ioctl, 1472 .ndo_change_mtu = pxa168_eth_change_mtu, 1473 .ndo_tx_timeout = pxa168_eth_tx_timeout, 1474 }; 1475 1476 static int pxa168_eth_probe(struct platform_device *pdev) 1477 { 1478 struct pxa168_eth_private *pep = NULL; 1479 struct net_device *dev = NULL; 1480 struct resource *res; 1481 struct clk *clk; 1482 int err; 1483 1484 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n"); 1485 1486 clk = clk_get(&pdev->dev, "MFUCLK"); 1487 if (IS_ERR(clk)) { 1488 printk(KERN_ERR "%s: Fast Ethernet failed to get clock\n", 1489 DRIVER_NAME); 1490 return -ENODEV; 1491 } 1492 clk_enable(clk); 1493 1494 dev = alloc_etherdev(sizeof(struct pxa168_eth_private)); 1495 if (!dev) { 1496 err = -ENOMEM; 1497 goto err_clk; 1498 } 1499 1500 platform_set_drvdata(pdev, dev); 1501 pep = netdev_priv(dev); 1502 pep->dev = dev; 1503 pep->clk = clk; 1504 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1505 if (res == NULL) { 1506 err = -ENODEV; 1507 goto err_netdev; 1508 } 1509 pep->base = ioremap(res->start, resource_size(res)); 1510 if (pep->base == NULL) { 1511 err = -ENOMEM; 1512 goto err_netdev; 1513 } 1514 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1515 BUG_ON(!res); 1516 dev->irq = res->start; 1517 dev->netdev_ops = &pxa168_eth_netdev_ops; 1518 dev->watchdog_timeo = 2 * HZ; 1519 dev->base_addr = 0; 1520 SET_ETHTOOL_OPS(dev, &pxa168_ethtool_ops); 1521 1522 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task); 1523 1524 printk(KERN_INFO "%s:Using random mac address\n", DRIVER_NAME); 1525 random_ether_addr(dev->dev_addr); 1526 1527 pep->pd = pdev->dev.platform_data; 1528 pep->rx_ring_size = NUM_RX_DESCS; 1529 if (pep->pd->rx_queue_size) 1530 pep->rx_ring_size = pep->pd->rx_queue_size; 1531 1532 pep->tx_ring_size = NUM_TX_DESCS; 1533 if (pep->pd->tx_queue_size) 1534 pep->tx_ring_size = pep->pd->tx_queue_size; 1535 1536 pep->port_num = pep->pd->port_number; 1537 /* Hardware supports only 3 ports */ 1538 BUG_ON(pep->port_num > 2); 1539 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size); 1540 1541 memset(&pep->timeout, 0, sizeof(struct timer_list)); 1542 init_timer(&pep->timeout); 1543 pep->timeout.function = rxq_refill_timer_wrapper; 1544 pep->timeout.data = (unsigned long)pep; 1545 1546 pep->smi_bus = mdiobus_alloc(); 1547 if (pep->smi_bus == NULL) { 1548 err = -ENOMEM; 1549 goto err_base; 1550 } 1551 pep->smi_bus->priv = pep; 1552 pep->smi_bus->name = "pxa168_eth smi"; 1553 pep->smi_bus->read = pxa168_smi_read; 1554 pep->smi_bus->write = pxa168_smi_write; 1555 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); 1556 pep->smi_bus->parent = &pdev->dev; 1557 pep->smi_bus->phy_mask = 0xffffffff; 1558 err = mdiobus_register(pep->smi_bus); 1559 if (err) 1560 goto err_free_mdio; 1561 1562 pxa168_init_hw(pep); 1563 err = ethernet_phy_setup(dev); 1564 if (err) 1565 goto err_mdiobus; 1566 SET_NETDEV_DEV(dev, &pdev->dev); 1567 err = register_netdev(dev); 1568 if (err) 1569 goto err_mdiobus; 1570 return 0; 1571 1572 err_mdiobus: 1573 mdiobus_unregister(pep->smi_bus); 1574 err_free_mdio: 1575 mdiobus_free(pep->smi_bus); 1576 err_base: 1577 iounmap(pep->base); 1578 err_netdev: 1579 free_netdev(dev); 1580 err_clk: 1581 clk_disable(clk); 1582 clk_put(clk); 1583 return err; 1584 } 1585 1586 static int pxa168_eth_remove(struct platform_device *pdev) 1587 { 1588 struct net_device *dev = platform_get_drvdata(pdev); 1589 struct pxa168_eth_private *pep = netdev_priv(dev); 1590 1591 if (pep->htpr) { 1592 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE, 1593 pep->htpr, pep->htpr_dma); 1594 pep->htpr = NULL; 1595 } 1596 if (pep->clk) { 1597 clk_disable(pep->clk); 1598 clk_put(pep->clk); 1599 pep->clk = NULL; 1600 } 1601 if (pep->phy != NULL) 1602 phy_detach(pep->phy); 1603 1604 iounmap(pep->base); 1605 pep->base = NULL; 1606 mdiobus_unregister(pep->smi_bus); 1607 mdiobus_free(pep->smi_bus); 1608 unregister_netdev(dev); 1609 cancel_work_sync(&pep->tx_timeout_task); 1610 free_netdev(dev); 1611 platform_set_drvdata(pdev, NULL); 1612 return 0; 1613 } 1614 1615 static void pxa168_eth_shutdown(struct platform_device *pdev) 1616 { 1617 struct net_device *dev = platform_get_drvdata(pdev); 1618 eth_port_reset(dev); 1619 } 1620 1621 #ifdef CONFIG_PM 1622 static int pxa168_eth_resume(struct platform_device *pdev) 1623 { 1624 return -ENOSYS; 1625 } 1626 1627 static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state) 1628 { 1629 return -ENOSYS; 1630 } 1631 1632 #else 1633 #define pxa168_eth_resume NULL 1634 #define pxa168_eth_suspend NULL 1635 #endif 1636 1637 static struct platform_driver pxa168_eth_driver = { 1638 .probe = pxa168_eth_probe, 1639 .remove = pxa168_eth_remove, 1640 .shutdown = pxa168_eth_shutdown, 1641 .resume = pxa168_eth_resume, 1642 .suspend = pxa168_eth_suspend, 1643 .driver = { 1644 .name = DRIVER_NAME, 1645 }, 1646 }; 1647 1648 static int __init pxa168_init_module(void) 1649 { 1650 return platform_driver_register(&pxa168_eth_driver); 1651 } 1652 1653 static void __exit pxa168_cleanup_module(void) 1654 { 1655 platform_driver_unregister(&pxa168_eth_driver); 1656 } 1657 1658 module_init(pxa168_init_module); 1659 module_exit(pxa168_cleanup_module); 1660 1661 MODULE_LICENSE("GPL"); 1662 MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168"); 1663 MODULE_ALIAS("platform:pxa168_eth"); 1664