1 /* 2 * PXA168 ethernet driver. 3 * Most of the code is derived from mv643xx ethernet driver. 4 * 5 * Copyright (C) 2010 Marvell International Ltd. 6 * Sachin Sanap <ssanap@marvell.com> 7 * Zhangfei Gao <zgao6@marvell.com> 8 * Philip Rakity <prakity@marvell.com> 9 * Mark Brown <markb@marvell.com> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 2 14 * of the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include <linux/bitops.h> 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/etherdevice.h> 30 #include <linux/ethtool.h> 31 #include <linux/in.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/ip.h> 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/of.h> 38 #include <linux/of_net.h> 39 #include <linux/phy.h> 40 #include <linux/platform_device.h> 41 #include <linux/pxa168_eth.h> 42 #include <linux/tcp.h> 43 #include <linux/types.h> 44 #include <linux/udp.h> 45 #include <linux/workqueue.h> 46 47 #include <asm/pgtable.h> 48 #include <asm/cacheflush.h> 49 50 #define DRIVER_NAME "pxa168-eth" 51 #define DRIVER_VERSION "0.3" 52 53 /* 54 * Registers 55 */ 56 57 #define PHY_ADDRESS 0x0000 58 #define SMI 0x0010 59 #define PORT_CONFIG 0x0400 60 #define PORT_CONFIG_EXT 0x0408 61 #define PORT_COMMAND 0x0410 62 #define PORT_STATUS 0x0418 63 #define HTPR 0x0428 64 #define MAC_ADDR_LOW 0x0430 65 #define MAC_ADDR_HIGH 0x0438 66 #define SDMA_CONFIG 0x0440 67 #define SDMA_CMD 0x0448 68 #define INT_CAUSE 0x0450 69 #define INT_W_CLEAR 0x0454 70 #define INT_MASK 0x0458 71 #define ETH_F_RX_DESC_0 0x0480 72 #define ETH_C_RX_DESC_0 0x04A0 73 #define ETH_C_TX_DESC_1 0x04E4 74 75 /* smi register */ 76 #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */ 77 #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */ 78 #define SMI_OP_W (0 << 26) /* Write operation */ 79 #define SMI_OP_R (1 << 26) /* Read operation */ 80 81 #define PHY_WAIT_ITERATIONS 10 82 83 #define PXA168_ETH_PHY_ADDR_DEFAULT 0 84 /* RX & TX descriptor command */ 85 #define BUF_OWNED_BY_DMA (1 << 31) 86 87 /* RX descriptor status */ 88 #define RX_EN_INT (1 << 23) 89 #define RX_FIRST_DESC (1 << 17) 90 #define RX_LAST_DESC (1 << 16) 91 #define RX_ERROR (1 << 15) 92 93 /* TX descriptor command */ 94 #define TX_EN_INT (1 << 23) 95 #define TX_GEN_CRC (1 << 22) 96 #define TX_ZERO_PADDING (1 << 18) 97 #define TX_FIRST_DESC (1 << 17) 98 #define TX_LAST_DESC (1 << 16) 99 #define TX_ERROR (1 << 15) 100 101 /* SDMA_CMD */ 102 #define SDMA_CMD_AT (1 << 31) 103 #define SDMA_CMD_TXDL (1 << 24) 104 #define SDMA_CMD_TXDH (1 << 23) 105 #define SDMA_CMD_AR (1 << 15) 106 #define SDMA_CMD_ERD (1 << 7) 107 108 /* Bit definitions of the Port Config Reg */ 109 #define PCR_DUPLEX_FULL (1 << 15) 110 #define PCR_HS (1 << 12) 111 #define PCR_EN (1 << 7) 112 #define PCR_PM (1 << 0) 113 114 /* Bit definitions of the Port Config Extend Reg */ 115 #define PCXR_2BSM (1 << 28) 116 #define PCXR_DSCP_EN (1 << 21) 117 #define PCXR_RMII_EN (1 << 20) 118 #define PCXR_AN_SPEED_DIS (1 << 19) 119 #define PCXR_SPEED_100 (1 << 18) 120 #define PCXR_MFL_1518 (0 << 14) 121 #define PCXR_MFL_1536 (1 << 14) 122 #define PCXR_MFL_2048 (2 << 14) 123 #define PCXR_MFL_64K (3 << 14) 124 #define PCXR_FLOWCTL_DIS (1 << 12) 125 #define PCXR_FLP (1 << 11) 126 #define PCXR_AN_FLOWCTL_DIS (1 << 10) 127 #define PCXR_AN_DUPLEX_DIS (1 << 9) 128 #define PCXR_PRIO_TX_OFF 3 129 #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF) 130 131 /* Bit definitions of the SDMA Config Reg */ 132 #define SDCR_BSZ_OFF 12 133 #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF) 134 #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF) 135 #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF) 136 #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF) 137 #define SDCR_BLMR (1 << 6) 138 #define SDCR_BLMT (1 << 7) 139 #define SDCR_RIFB (1 << 9) 140 #define SDCR_RC_OFF 2 141 #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) 142 143 /* 144 * Bit definitions of the Interrupt Cause Reg 145 * and Interrupt MASK Reg is the same 146 */ 147 #define ICR_RXBUF (1 << 0) 148 #define ICR_TXBUF_H (1 << 2) 149 #define ICR_TXBUF_L (1 << 3) 150 #define ICR_TXEND_H (1 << 6) 151 #define ICR_TXEND_L (1 << 7) 152 #define ICR_RXERR (1 << 8) 153 #define ICR_TXERR_H (1 << 10) 154 #define ICR_TXERR_L (1 << 11) 155 #define ICR_TX_UDR (1 << 13) 156 #define ICR_MII_CH (1 << 28) 157 158 #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ 159 ICR_TXERR_H | ICR_TXERR_L |\ 160 ICR_TXEND_H | ICR_TXEND_L |\ 161 ICR_RXBUF | ICR_RXERR | ICR_MII_CH) 162 163 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ 164 165 #define NUM_RX_DESCS 64 166 #define NUM_TX_DESCS 64 167 168 #define HASH_ADD 0 169 #define HASH_DELETE 1 170 #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ 171 #define HOP_NUMBER 12 172 173 /* Bit definitions for Port status */ 174 #define PORT_SPEED_100 (1 << 0) 175 #define FULL_DUPLEX (1 << 1) 176 #define FLOW_CONTROL_DISABLED (1 << 2) 177 #define LINK_UP (1 << 3) 178 179 /* Bit definitions for work to be done */ 180 #define WORK_TX_DONE (1 << 1) 181 182 /* 183 * Misc definitions. 184 */ 185 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 186 187 struct rx_desc { 188 u32 cmd_sts; /* Descriptor command status */ 189 u16 byte_cnt; /* Descriptor buffer byte count */ 190 u16 buf_size; /* Buffer size */ 191 u32 buf_ptr; /* Descriptor buffer pointer */ 192 u32 next_desc_ptr; /* Next descriptor pointer */ 193 }; 194 195 struct tx_desc { 196 u32 cmd_sts; /* Command/status field */ 197 u16 reserved; 198 u16 byte_cnt; /* buffer byte count */ 199 u32 buf_ptr; /* pointer to buffer for this descriptor */ 200 u32 next_desc_ptr; /* Pointer to next descriptor */ 201 }; 202 203 struct pxa168_eth_private { 204 int port_num; /* User Ethernet port number */ 205 int phy_addr; 206 int phy_speed; 207 int phy_duplex; 208 phy_interface_t phy_intf; 209 210 int rx_resource_err; /* Rx ring resource error flag */ 211 212 /* Next available and first returning Rx resource */ 213 int rx_curr_desc_q, rx_used_desc_q; 214 215 /* Next available and first returning Tx resource */ 216 int tx_curr_desc_q, tx_used_desc_q; 217 218 struct rx_desc *p_rx_desc_area; 219 dma_addr_t rx_desc_dma; 220 int rx_desc_area_size; 221 struct sk_buff **rx_skb; 222 223 struct tx_desc *p_tx_desc_area; 224 dma_addr_t tx_desc_dma; 225 int tx_desc_area_size; 226 struct sk_buff **tx_skb; 227 228 struct work_struct tx_timeout_task; 229 230 struct net_device *dev; 231 struct napi_struct napi; 232 u8 work_todo; 233 int skb_size; 234 235 /* Size of Tx Ring per queue */ 236 int tx_ring_size; 237 /* Number of tx descriptors in use */ 238 int tx_desc_count; 239 /* Size of Rx Ring per queue */ 240 int rx_ring_size; 241 /* Number of rx descriptors in use */ 242 int rx_desc_count; 243 244 /* 245 * Used in case RX Ring is empty, which can occur when 246 * system does not have resources (skb's) 247 */ 248 struct timer_list timeout; 249 struct mii_bus *smi_bus; 250 251 /* clock */ 252 struct clk *clk; 253 struct pxa168_eth_platform_data *pd; 254 /* 255 * Ethernet controller base address. 256 */ 257 void __iomem *base; 258 259 /* Pointer to the hardware address filter table */ 260 void *htpr; 261 dma_addr_t htpr_dma; 262 }; 263 264 struct addr_table_entry { 265 __le32 lo; 266 __le32 hi; 267 }; 268 269 /* Bit fields of a Hash Table Entry */ 270 enum hash_table_entry { 271 HASH_ENTRY_VALID = 1, 272 SKIP = 2, 273 HASH_ENTRY_RECEIVE_DISCARD = 4, 274 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2 275 }; 276 277 static int pxa168_init_hw(struct pxa168_eth_private *pep); 278 static int pxa168_init_phy(struct net_device *dev); 279 static void eth_port_reset(struct net_device *dev); 280 static void eth_port_start(struct net_device *dev); 281 static int pxa168_eth_open(struct net_device *dev); 282 static int pxa168_eth_stop(struct net_device *dev); 283 284 static inline u32 rdl(struct pxa168_eth_private *pep, int offset) 285 { 286 return readl_relaxed(pep->base + offset); 287 } 288 289 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data) 290 { 291 writel_relaxed(data, pep->base + offset); 292 } 293 294 static void abort_dma(struct pxa168_eth_private *pep) 295 { 296 int delay; 297 int max_retries = 40; 298 299 do { 300 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT); 301 udelay(100); 302 303 delay = 10; 304 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT)) 305 && delay-- > 0) { 306 udelay(10); 307 } 308 } while (max_retries-- > 0 && delay <= 0); 309 310 if (max_retries <= 0) 311 netdev_err(pep->dev, "%s : DMA Stuck\n", __func__); 312 } 313 314 static void rxq_refill(struct net_device *dev) 315 { 316 struct pxa168_eth_private *pep = netdev_priv(dev); 317 struct sk_buff *skb; 318 struct rx_desc *p_used_rx_desc; 319 int used_rx_desc; 320 321 while (pep->rx_desc_count < pep->rx_ring_size) { 322 int size; 323 324 skb = netdev_alloc_skb(dev, pep->skb_size); 325 if (!skb) 326 break; 327 if (SKB_DMA_REALIGN) 328 skb_reserve(skb, SKB_DMA_REALIGN); 329 pep->rx_desc_count++; 330 /* Get 'used' Rx descriptor */ 331 used_rx_desc = pep->rx_used_desc_q; 332 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc]; 333 size = skb_end_pointer(skb) - skb->data; 334 p_used_rx_desc->buf_ptr = dma_map_single(NULL, 335 skb->data, 336 size, 337 DMA_FROM_DEVICE); 338 p_used_rx_desc->buf_size = size; 339 pep->rx_skb[used_rx_desc] = skb; 340 341 /* Return the descriptor to DMA ownership */ 342 dma_wmb(); 343 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; 344 dma_wmb(); 345 346 /* Move the used descriptor pointer to the next descriptor */ 347 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size; 348 349 /* Any Rx return cancels the Rx resource error status */ 350 pep->rx_resource_err = 0; 351 352 skb_reserve(skb, ETH_HW_IP_ALIGN); 353 } 354 355 /* 356 * If RX ring is empty of SKB, set a timer to try allocating 357 * again at a later time. 358 */ 359 if (pep->rx_desc_count == 0) { 360 pep->timeout.expires = jiffies + (HZ / 10); 361 add_timer(&pep->timeout); 362 } 363 } 364 365 static inline void rxq_refill_timer_wrapper(struct timer_list *t) 366 { 367 struct pxa168_eth_private *pep = from_timer(pep, t, timeout); 368 napi_schedule(&pep->napi); 369 } 370 371 static inline u8 flip_8_bits(u8 x) 372 { 373 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1) 374 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3) 375 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1) 376 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3); 377 } 378 379 static void nibble_swap_every_byte(unsigned char *mac_addr) 380 { 381 int i; 382 for (i = 0; i < ETH_ALEN; i++) { 383 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) | 384 ((mac_addr[i] & 0xf0) >> 4); 385 } 386 } 387 388 static void inverse_every_nibble(unsigned char *mac_addr) 389 { 390 int i; 391 for (i = 0; i < ETH_ALEN; i++) 392 mac_addr[i] = flip_8_bits(mac_addr[i]); 393 } 394 395 /* 396 * ---------------------------------------------------------------------------- 397 * This function will calculate the hash function of the address. 398 * Inputs 399 * mac_addr_orig - MAC address. 400 * Outputs 401 * return the calculated entry. 402 */ 403 static u32 hash_function(unsigned char *mac_addr_orig) 404 { 405 u32 hash_result; 406 u32 addr0; 407 u32 addr1; 408 u32 addr2; 409 u32 addr3; 410 unsigned char mac_addr[ETH_ALEN]; 411 412 /* Make a copy of MAC address since we are going to performe bit 413 * operations on it 414 */ 415 memcpy(mac_addr, mac_addr_orig, ETH_ALEN); 416 417 nibble_swap_every_byte(mac_addr); 418 inverse_every_nibble(mac_addr); 419 420 addr0 = (mac_addr[5] >> 2) & 0x3f; 421 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2); 422 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1; 423 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8); 424 425 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); 426 hash_result = hash_result & 0x07ff; 427 return hash_result; 428 } 429 430 /* 431 * ---------------------------------------------------------------------------- 432 * This function will add/del an entry to the address table. 433 * Inputs 434 * pep - ETHERNET . 435 * mac_addr - MAC address. 436 * skip - if 1, skip this address.Used in case of deleting an entry which is a 437 * part of chain in the hash table.We can't just delete the entry since 438 * that will break the chain.We need to defragment the tables time to 439 * time. 440 * rd - 0 Discard packet upon match. 441 * - 1 Receive packet upon match. 442 * Outputs 443 * address table entry is added/deleted. 444 * 0 if success. 445 * -ENOSPC if table full 446 */ 447 static int add_del_hash_entry(struct pxa168_eth_private *pep, 448 unsigned char *mac_addr, 449 u32 rd, u32 skip, int del) 450 { 451 struct addr_table_entry *entry, *start; 452 u32 new_high; 453 u32 new_low; 454 u32 i; 455 456 new_low = (((mac_addr[1] >> 4) & 0xf) << 15) 457 | (((mac_addr[1] >> 0) & 0xf) << 11) 458 | (((mac_addr[0] >> 4) & 0xf) << 7) 459 | (((mac_addr[0] >> 0) & 0xf) << 3) 460 | (((mac_addr[3] >> 4) & 0x1) << 31) 461 | (((mac_addr[3] >> 0) & 0xf) << 27) 462 | (((mac_addr[2] >> 4) & 0xf) << 23) 463 | (((mac_addr[2] >> 0) & 0xf) << 19) 464 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT) 465 | HASH_ENTRY_VALID; 466 467 new_high = (((mac_addr[5] >> 4) & 0xf) << 15) 468 | (((mac_addr[5] >> 0) & 0xf) << 11) 469 | (((mac_addr[4] >> 4) & 0xf) << 7) 470 | (((mac_addr[4] >> 0) & 0xf) << 3) 471 | (((mac_addr[3] >> 5) & 0x7) << 0); 472 473 /* 474 * Pick the appropriate table, start scanning for free/reusable 475 * entries at the index obtained by hashing the specified MAC address 476 */ 477 start = pep->htpr; 478 entry = start + hash_function(mac_addr); 479 for (i = 0; i < HOP_NUMBER; i++) { 480 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) { 481 break; 482 } else { 483 /* if same address put in same position */ 484 if (((le32_to_cpu(entry->lo) & 0xfffffff8) == 485 (new_low & 0xfffffff8)) && 486 (le32_to_cpu(entry->hi) == new_high)) { 487 break; 488 } 489 } 490 if (entry == start + 0x7ff) 491 entry = start; 492 else 493 entry++; 494 } 495 496 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) && 497 (le32_to_cpu(entry->hi) != new_high) && del) 498 return 0; 499 500 if (i == HOP_NUMBER) { 501 if (!del) { 502 netdev_info(pep->dev, 503 "%s: table section is full, need to " 504 "move to 16kB implementation?\n", 505 __FILE__); 506 return -ENOSPC; 507 } else 508 return 0; 509 } 510 511 /* 512 * Update the selected entry 513 */ 514 if (del) { 515 entry->hi = 0; 516 entry->lo = 0; 517 } else { 518 entry->hi = cpu_to_le32(new_high); 519 entry->lo = cpu_to_le32(new_low); 520 } 521 522 return 0; 523 } 524 525 /* 526 * ---------------------------------------------------------------------------- 527 * Create an addressTable entry from MAC address info 528 * found in the specifed net_device struct 529 * 530 * Input : pointer to ethernet interface network device structure 531 * Output : N/A 532 */ 533 static void update_hash_table_mac_address(struct pxa168_eth_private *pep, 534 unsigned char *oaddr, 535 unsigned char *addr) 536 { 537 /* Delete old entry */ 538 if (oaddr) 539 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE); 540 /* Add new entry */ 541 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD); 542 } 543 544 static int init_hash_table(struct pxa168_eth_private *pep) 545 { 546 /* 547 * Hardware expects CPU to build a hash table based on a predefined 548 * hash function and populate it based on hardware address. The 549 * location of the hash table is identified by 32-bit pointer stored 550 * in HTPR internal register. Two possible sizes exists for the hash 551 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB 552 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support 553 * 1/2kB. 554 */ 555 /* TODO: Add support for 8kB hash table and alternative hash 556 * function.Driver can dynamically switch to them if the 1/2kB hash 557 * table is full. 558 */ 559 if (!pep->htpr) { 560 pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent, 561 HASH_ADDR_TABLE_SIZE, 562 &pep->htpr_dma, GFP_KERNEL); 563 if (!pep->htpr) 564 return -ENOMEM; 565 } else { 566 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); 567 } 568 wrl(pep, HTPR, pep->htpr_dma); 569 return 0; 570 } 571 572 static void pxa168_eth_set_rx_mode(struct net_device *dev) 573 { 574 struct pxa168_eth_private *pep = netdev_priv(dev); 575 struct netdev_hw_addr *ha; 576 u32 val; 577 578 val = rdl(pep, PORT_CONFIG); 579 if (dev->flags & IFF_PROMISC) 580 val |= PCR_PM; 581 else 582 val &= ~PCR_PM; 583 wrl(pep, PORT_CONFIG, val); 584 585 /* 586 * Remove the old list of MAC address and add dev->addr 587 * and multicast address. 588 */ 589 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); 590 update_hash_table_mac_address(pep, NULL, dev->dev_addr); 591 592 netdev_for_each_mc_addr(ha, dev) 593 update_hash_table_mac_address(pep, NULL, ha->addr); 594 } 595 596 static void pxa168_eth_get_mac_address(struct net_device *dev, 597 unsigned char *addr) 598 { 599 struct pxa168_eth_private *pep = netdev_priv(dev); 600 unsigned int mac_h = rdl(pep, MAC_ADDR_HIGH); 601 unsigned int mac_l = rdl(pep, MAC_ADDR_LOW); 602 603 addr[0] = (mac_h >> 24) & 0xff; 604 addr[1] = (mac_h >> 16) & 0xff; 605 addr[2] = (mac_h >> 8) & 0xff; 606 addr[3] = mac_h & 0xff; 607 addr[4] = (mac_l >> 8) & 0xff; 608 addr[5] = mac_l & 0xff; 609 } 610 611 static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr) 612 { 613 struct sockaddr *sa = addr; 614 struct pxa168_eth_private *pep = netdev_priv(dev); 615 unsigned char oldMac[ETH_ALEN]; 616 u32 mac_h, mac_l; 617 618 if (!is_valid_ether_addr(sa->sa_data)) 619 return -EADDRNOTAVAIL; 620 memcpy(oldMac, dev->dev_addr, ETH_ALEN); 621 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); 622 623 mac_h = dev->dev_addr[0] << 24; 624 mac_h |= dev->dev_addr[1] << 16; 625 mac_h |= dev->dev_addr[2] << 8; 626 mac_h |= dev->dev_addr[3]; 627 mac_l = dev->dev_addr[4] << 8; 628 mac_l |= dev->dev_addr[5]; 629 wrl(pep, MAC_ADDR_HIGH, mac_h); 630 wrl(pep, MAC_ADDR_LOW, mac_l); 631 632 netif_addr_lock_bh(dev); 633 update_hash_table_mac_address(pep, oldMac, dev->dev_addr); 634 netif_addr_unlock_bh(dev); 635 return 0; 636 } 637 638 static void eth_port_start(struct net_device *dev) 639 { 640 unsigned int val = 0; 641 struct pxa168_eth_private *pep = netdev_priv(dev); 642 int tx_curr_desc, rx_curr_desc; 643 644 phy_start(dev->phydev); 645 646 /* Assignment of Tx CTRP of given queue */ 647 tx_curr_desc = pep->tx_curr_desc_q; 648 wrl(pep, ETH_C_TX_DESC_1, 649 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc))); 650 651 /* Assignment of Rx CRDP of given queue */ 652 rx_curr_desc = pep->rx_curr_desc_q; 653 wrl(pep, ETH_C_RX_DESC_0, 654 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); 655 656 wrl(pep, ETH_F_RX_DESC_0, 657 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); 658 659 /* Clear all interrupts */ 660 wrl(pep, INT_CAUSE, 0); 661 662 /* Enable all interrupts for receive, transmit and error. */ 663 wrl(pep, INT_MASK, ALL_INTS); 664 665 val = rdl(pep, PORT_CONFIG); 666 val |= PCR_EN; 667 wrl(pep, PORT_CONFIG, val); 668 669 /* Start RX DMA engine */ 670 val = rdl(pep, SDMA_CMD); 671 val |= SDMA_CMD_ERD; 672 wrl(pep, SDMA_CMD, val); 673 } 674 675 static void eth_port_reset(struct net_device *dev) 676 { 677 struct pxa168_eth_private *pep = netdev_priv(dev); 678 unsigned int val = 0; 679 680 /* Stop all interrupts for receive, transmit and error. */ 681 wrl(pep, INT_MASK, 0); 682 683 /* Clear all interrupts */ 684 wrl(pep, INT_CAUSE, 0); 685 686 /* Stop RX DMA */ 687 val = rdl(pep, SDMA_CMD); 688 val &= ~SDMA_CMD_ERD; /* abort dma command */ 689 690 /* Abort any transmit and receive operations and put DMA 691 * in idle state. 692 */ 693 abort_dma(pep); 694 695 /* Disable port */ 696 val = rdl(pep, PORT_CONFIG); 697 val &= ~PCR_EN; 698 wrl(pep, PORT_CONFIG, val); 699 700 phy_stop(dev->phydev); 701 } 702 703 /* 704 * txq_reclaim - Free the tx desc data for completed descriptors 705 * If force is non-zero, frees uncompleted descriptors as well 706 */ 707 static int txq_reclaim(struct net_device *dev, int force) 708 { 709 struct pxa168_eth_private *pep = netdev_priv(dev); 710 struct tx_desc *desc; 711 u32 cmd_sts; 712 struct sk_buff *skb; 713 int tx_index; 714 dma_addr_t addr; 715 int count; 716 int released = 0; 717 718 netif_tx_lock(dev); 719 720 pep->work_todo &= ~WORK_TX_DONE; 721 while (pep->tx_desc_count > 0) { 722 tx_index = pep->tx_used_desc_q; 723 desc = &pep->p_tx_desc_area[tx_index]; 724 cmd_sts = desc->cmd_sts; 725 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) { 726 if (released > 0) { 727 goto txq_reclaim_end; 728 } else { 729 released = -1; 730 goto txq_reclaim_end; 731 } 732 } 733 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size; 734 pep->tx_desc_count--; 735 addr = desc->buf_ptr; 736 count = desc->byte_cnt; 737 skb = pep->tx_skb[tx_index]; 738 if (skb) 739 pep->tx_skb[tx_index] = NULL; 740 741 if (cmd_sts & TX_ERROR) { 742 if (net_ratelimit()) 743 netdev_err(dev, "Error in TX\n"); 744 dev->stats.tx_errors++; 745 } 746 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); 747 if (skb) 748 dev_kfree_skb_irq(skb); 749 released++; 750 } 751 txq_reclaim_end: 752 netif_tx_unlock(dev); 753 return released; 754 } 755 756 static void pxa168_eth_tx_timeout(struct net_device *dev) 757 { 758 struct pxa168_eth_private *pep = netdev_priv(dev); 759 760 netdev_info(dev, "TX timeout desc_count %d\n", pep->tx_desc_count); 761 762 schedule_work(&pep->tx_timeout_task); 763 } 764 765 static void pxa168_eth_tx_timeout_task(struct work_struct *work) 766 { 767 struct pxa168_eth_private *pep = container_of(work, 768 struct pxa168_eth_private, 769 tx_timeout_task); 770 struct net_device *dev = pep->dev; 771 pxa168_eth_stop(dev); 772 pxa168_eth_open(dev); 773 } 774 775 static int rxq_process(struct net_device *dev, int budget) 776 { 777 struct pxa168_eth_private *pep = netdev_priv(dev); 778 struct net_device_stats *stats = &dev->stats; 779 unsigned int received_packets = 0; 780 struct sk_buff *skb; 781 782 while (budget-- > 0) { 783 int rx_next_curr_desc, rx_curr_desc, rx_used_desc; 784 struct rx_desc *rx_desc; 785 unsigned int cmd_sts; 786 787 /* Do not process Rx ring in case of Rx ring resource error */ 788 if (pep->rx_resource_err) 789 break; 790 rx_curr_desc = pep->rx_curr_desc_q; 791 rx_used_desc = pep->rx_used_desc_q; 792 rx_desc = &pep->p_rx_desc_area[rx_curr_desc]; 793 cmd_sts = rx_desc->cmd_sts; 794 dma_rmb(); 795 if (cmd_sts & (BUF_OWNED_BY_DMA)) 796 break; 797 skb = pep->rx_skb[rx_curr_desc]; 798 pep->rx_skb[rx_curr_desc] = NULL; 799 800 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size; 801 pep->rx_curr_desc_q = rx_next_curr_desc; 802 803 /* Rx descriptors exhausted. */ 804 /* Set the Rx ring resource error flag */ 805 if (rx_next_curr_desc == rx_used_desc) 806 pep->rx_resource_err = 1; 807 pep->rx_desc_count--; 808 dma_unmap_single(NULL, rx_desc->buf_ptr, 809 rx_desc->buf_size, 810 DMA_FROM_DEVICE); 811 received_packets++; 812 /* 813 * Update statistics. 814 * Note byte count includes 4 byte CRC count 815 */ 816 stats->rx_packets++; 817 stats->rx_bytes += rx_desc->byte_cnt; 818 /* 819 * In case received a packet without first / last bits on OR 820 * the error summary bit is on, the packets needs to be droped. 821 */ 822 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 823 (RX_FIRST_DESC | RX_LAST_DESC)) 824 || (cmd_sts & RX_ERROR)) { 825 826 stats->rx_dropped++; 827 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 828 (RX_FIRST_DESC | RX_LAST_DESC)) { 829 if (net_ratelimit()) 830 netdev_err(dev, 831 "Rx pkt on multiple desc\n"); 832 } 833 if (cmd_sts & RX_ERROR) 834 stats->rx_errors++; 835 dev_kfree_skb_irq(skb); 836 } else { 837 /* 838 * The -4 is for the CRC in the trailer of the 839 * received packet 840 */ 841 skb_put(skb, rx_desc->byte_cnt - 4); 842 skb->protocol = eth_type_trans(skb, dev); 843 netif_receive_skb(skb); 844 } 845 } 846 /* Fill RX ring with skb's */ 847 rxq_refill(dev); 848 return received_packets; 849 } 850 851 static int pxa168_eth_collect_events(struct pxa168_eth_private *pep, 852 struct net_device *dev) 853 { 854 u32 icr; 855 int ret = 0; 856 857 icr = rdl(pep, INT_CAUSE); 858 if (icr == 0) 859 return IRQ_NONE; 860 861 wrl(pep, INT_CAUSE, ~icr); 862 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) { 863 pep->work_todo |= WORK_TX_DONE; 864 ret = 1; 865 } 866 if (icr & ICR_RXBUF) 867 ret = 1; 868 return ret; 869 } 870 871 static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id) 872 { 873 struct net_device *dev = (struct net_device *)dev_id; 874 struct pxa168_eth_private *pep = netdev_priv(dev); 875 876 if (unlikely(!pxa168_eth_collect_events(pep, dev))) 877 return IRQ_NONE; 878 /* Disable interrupts */ 879 wrl(pep, INT_MASK, 0); 880 napi_schedule(&pep->napi); 881 return IRQ_HANDLED; 882 } 883 884 static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep) 885 { 886 int skb_size; 887 888 /* 889 * Reserve 2+14 bytes for an ethernet header (the hardware 890 * automatically prepends 2 bytes of dummy data to each 891 * received packet), 16 bytes for up to four VLAN tags, and 892 * 4 bytes for the trailing FCS -- 36 bytes total. 893 */ 894 skb_size = pep->dev->mtu + 36; 895 896 /* 897 * Make sure that the skb size is a multiple of 8 bytes, as 898 * the lower three bits of the receive descriptor's buffer 899 * size field are ignored by the hardware. 900 */ 901 pep->skb_size = (skb_size + 7) & ~7; 902 903 /* 904 * If NET_SKB_PAD is smaller than a cache line, 905 * netdev_alloc_skb() will cause skb->data to be misaligned 906 * to a cache line boundary. If this is the case, include 907 * some extra space to allow re-aligning the data area. 908 */ 909 pep->skb_size += SKB_DMA_REALIGN; 910 911 } 912 913 static int set_port_config_ext(struct pxa168_eth_private *pep) 914 { 915 int skb_size; 916 917 pxa168_eth_recalc_skb_size(pep); 918 if (pep->skb_size <= 1518) 919 skb_size = PCXR_MFL_1518; 920 else if (pep->skb_size <= 1536) 921 skb_size = PCXR_MFL_1536; 922 else if (pep->skb_size <= 2048) 923 skb_size = PCXR_MFL_2048; 924 else 925 skb_size = PCXR_MFL_64K; 926 927 /* Extended Port Configuration */ 928 wrl(pep, PORT_CONFIG_EXT, 929 PCXR_AN_SPEED_DIS | /* Disable HW AN */ 930 PCXR_AN_DUPLEX_DIS | 931 PCXR_AN_FLOWCTL_DIS | 932 PCXR_2BSM | /* Two byte prefix aligns IP hdr */ 933 PCXR_DSCP_EN | /* Enable DSCP in IP */ 934 skb_size | PCXR_FLP | /* do not force link pass */ 935 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */ 936 937 return 0; 938 } 939 940 static void pxa168_eth_adjust_link(struct net_device *dev) 941 { 942 struct pxa168_eth_private *pep = netdev_priv(dev); 943 struct phy_device *phy = dev->phydev; 944 u32 cfg, cfg_o = rdl(pep, PORT_CONFIG); 945 u32 cfgext, cfgext_o = rdl(pep, PORT_CONFIG_EXT); 946 947 cfg = cfg_o & ~PCR_DUPLEX_FULL; 948 cfgext = cfgext_o & ~(PCXR_SPEED_100 | PCXR_FLOWCTL_DIS | PCXR_RMII_EN); 949 950 if (phy->interface == PHY_INTERFACE_MODE_RMII) 951 cfgext |= PCXR_RMII_EN; 952 if (phy->speed == SPEED_100) 953 cfgext |= PCXR_SPEED_100; 954 if (phy->duplex) 955 cfg |= PCR_DUPLEX_FULL; 956 if (!phy->pause) 957 cfgext |= PCXR_FLOWCTL_DIS; 958 959 /* Bail out if there has nothing changed */ 960 if (cfg == cfg_o && cfgext == cfgext_o) 961 return; 962 963 wrl(pep, PORT_CONFIG, cfg); 964 wrl(pep, PORT_CONFIG_EXT, cfgext); 965 966 phy_print_status(phy); 967 } 968 969 static int pxa168_init_phy(struct net_device *dev) 970 { 971 struct pxa168_eth_private *pep = netdev_priv(dev); 972 struct ethtool_link_ksettings cmd; 973 struct phy_device *phy = NULL; 974 int err; 975 976 if (dev->phydev) 977 return 0; 978 979 phy = mdiobus_scan(pep->smi_bus, pep->phy_addr); 980 if (IS_ERR(phy)) 981 return PTR_ERR(phy); 982 983 err = phy_connect_direct(dev, phy, pxa168_eth_adjust_link, 984 pep->phy_intf); 985 if (err) 986 return err; 987 988 cmd.base.phy_address = pep->phy_addr; 989 cmd.base.speed = pep->phy_speed; 990 cmd.base.duplex = pep->phy_duplex; 991 ethtool_convert_legacy_u32_to_link_mode(cmd.link_modes.advertising, 992 PHY_BASIC_FEATURES); 993 cmd.base.autoneg = AUTONEG_ENABLE; 994 995 if (cmd.base.speed != 0) 996 cmd.base.autoneg = AUTONEG_DISABLE; 997 998 return phy_ethtool_set_link_ksettings(dev, &cmd); 999 } 1000 1001 static int pxa168_init_hw(struct pxa168_eth_private *pep) 1002 { 1003 int err = 0; 1004 1005 /* Disable interrupts */ 1006 wrl(pep, INT_MASK, 0); 1007 wrl(pep, INT_CAUSE, 0); 1008 /* Write to ICR to clear interrupts. */ 1009 wrl(pep, INT_W_CLEAR, 0); 1010 /* Abort any transmit and receive operations and put DMA 1011 * in idle state. 1012 */ 1013 abort_dma(pep); 1014 /* Initialize address hash table */ 1015 err = init_hash_table(pep); 1016 if (err) 1017 return err; 1018 /* SDMA configuration */ 1019 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */ 1020 SDCR_RIFB | /* Rx interrupt on frame */ 1021 SDCR_BLMT | /* Little endian transmit */ 1022 SDCR_BLMR | /* Little endian receive */ 1023 SDCR_RC_MAX_RETRANS); /* Max retransmit count */ 1024 /* Port Configuration */ 1025 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */ 1026 set_port_config_ext(pep); 1027 1028 return err; 1029 } 1030 1031 static int rxq_init(struct net_device *dev) 1032 { 1033 struct pxa168_eth_private *pep = netdev_priv(dev); 1034 struct rx_desc *p_rx_desc; 1035 int size = 0, i = 0; 1036 int rx_desc_num = pep->rx_ring_size; 1037 1038 /* Allocate RX skb rings */ 1039 pep->rx_skb = kcalloc(rx_desc_num, sizeof(*pep->rx_skb), GFP_KERNEL); 1040 if (!pep->rx_skb) 1041 return -ENOMEM; 1042 1043 /* Allocate RX ring */ 1044 pep->rx_desc_count = 0; 1045 size = pep->rx_ring_size * sizeof(struct rx_desc); 1046 pep->rx_desc_area_size = size; 1047 pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size, 1048 &pep->rx_desc_dma, 1049 GFP_KERNEL); 1050 if (!pep->p_rx_desc_area) 1051 goto out; 1052 1053 /* initialize the next_desc_ptr links in the Rx descriptors ring */ 1054 p_rx_desc = pep->p_rx_desc_area; 1055 for (i = 0; i < rx_desc_num; i++) { 1056 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma + 1057 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc); 1058 } 1059 /* Save Rx desc pointer to driver struct. */ 1060 pep->rx_curr_desc_q = 0; 1061 pep->rx_used_desc_q = 0; 1062 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc); 1063 return 0; 1064 out: 1065 kfree(pep->rx_skb); 1066 return -ENOMEM; 1067 } 1068 1069 static void rxq_deinit(struct net_device *dev) 1070 { 1071 struct pxa168_eth_private *pep = netdev_priv(dev); 1072 int curr; 1073 1074 /* Free preallocated skb's on RX rings */ 1075 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) { 1076 if (pep->rx_skb[curr]) { 1077 dev_kfree_skb(pep->rx_skb[curr]); 1078 pep->rx_desc_count--; 1079 } 1080 } 1081 if (pep->rx_desc_count) 1082 netdev_err(dev, "Error in freeing Rx Ring. %d skb's still\n", 1083 pep->rx_desc_count); 1084 /* Free RX ring */ 1085 if (pep->p_rx_desc_area) 1086 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size, 1087 pep->p_rx_desc_area, pep->rx_desc_dma); 1088 kfree(pep->rx_skb); 1089 } 1090 1091 static int txq_init(struct net_device *dev) 1092 { 1093 struct pxa168_eth_private *pep = netdev_priv(dev); 1094 struct tx_desc *p_tx_desc; 1095 int size = 0, i = 0; 1096 int tx_desc_num = pep->tx_ring_size; 1097 1098 pep->tx_skb = kcalloc(tx_desc_num, sizeof(*pep->tx_skb), GFP_KERNEL); 1099 if (!pep->tx_skb) 1100 return -ENOMEM; 1101 1102 /* Allocate TX ring */ 1103 pep->tx_desc_count = 0; 1104 size = pep->tx_ring_size * sizeof(struct tx_desc); 1105 pep->tx_desc_area_size = size; 1106 pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size, 1107 &pep->tx_desc_dma, 1108 GFP_KERNEL); 1109 if (!pep->p_tx_desc_area) 1110 goto out; 1111 /* Initialize the next_desc_ptr links in the Tx descriptors ring */ 1112 p_tx_desc = pep->p_tx_desc_area; 1113 for (i = 0; i < tx_desc_num; i++) { 1114 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma + 1115 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc); 1116 } 1117 pep->tx_curr_desc_q = 0; 1118 pep->tx_used_desc_q = 0; 1119 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc); 1120 return 0; 1121 out: 1122 kfree(pep->tx_skb); 1123 return -ENOMEM; 1124 } 1125 1126 static void txq_deinit(struct net_device *dev) 1127 { 1128 struct pxa168_eth_private *pep = netdev_priv(dev); 1129 1130 /* Free outstanding skb's on TX ring */ 1131 txq_reclaim(dev, 1); 1132 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q); 1133 /* Free TX ring */ 1134 if (pep->p_tx_desc_area) 1135 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size, 1136 pep->p_tx_desc_area, pep->tx_desc_dma); 1137 kfree(pep->tx_skb); 1138 } 1139 1140 static int pxa168_eth_open(struct net_device *dev) 1141 { 1142 struct pxa168_eth_private *pep = netdev_priv(dev); 1143 int err; 1144 1145 err = pxa168_init_phy(dev); 1146 if (err) 1147 return err; 1148 1149 err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev); 1150 if (err) { 1151 dev_err(&dev->dev, "can't assign irq\n"); 1152 return -EAGAIN; 1153 } 1154 pep->rx_resource_err = 0; 1155 err = rxq_init(dev); 1156 if (err != 0) 1157 goto out_free_irq; 1158 err = txq_init(dev); 1159 if (err != 0) 1160 goto out_free_rx_skb; 1161 pep->rx_used_desc_q = 0; 1162 pep->rx_curr_desc_q = 0; 1163 1164 /* Fill RX ring with skb's */ 1165 rxq_refill(dev); 1166 pep->rx_used_desc_q = 0; 1167 pep->rx_curr_desc_q = 0; 1168 netif_carrier_off(dev); 1169 napi_enable(&pep->napi); 1170 eth_port_start(dev); 1171 return 0; 1172 out_free_rx_skb: 1173 rxq_deinit(dev); 1174 out_free_irq: 1175 free_irq(dev->irq, dev); 1176 return err; 1177 } 1178 1179 static int pxa168_eth_stop(struct net_device *dev) 1180 { 1181 struct pxa168_eth_private *pep = netdev_priv(dev); 1182 eth_port_reset(dev); 1183 1184 /* Disable interrupts */ 1185 wrl(pep, INT_MASK, 0); 1186 wrl(pep, INT_CAUSE, 0); 1187 /* Write to ICR to clear interrupts. */ 1188 wrl(pep, INT_W_CLEAR, 0); 1189 napi_disable(&pep->napi); 1190 del_timer_sync(&pep->timeout); 1191 netif_carrier_off(dev); 1192 free_irq(dev->irq, dev); 1193 rxq_deinit(dev); 1194 txq_deinit(dev); 1195 1196 return 0; 1197 } 1198 1199 static int pxa168_eth_change_mtu(struct net_device *dev, int mtu) 1200 { 1201 int retval; 1202 struct pxa168_eth_private *pep = netdev_priv(dev); 1203 1204 dev->mtu = mtu; 1205 retval = set_port_config_ext(pep); 1206 1207 if (!netif_running(dev)) 1208 return 0; 1209 1210 /* 1211 * Stop and then re-open the interface. This will allocate RX 1212 * skbs of the new MTU. 1213 * There is a possible danger that the open will not succeed, 1214 * due to memory being full. 1215 */ 1216 pxa168_eth_stop(dev); 1217 if (pxa168_eth_open(dev)) { 1218 dev_err(&dev->dev, 1219 "fatal error on re-opening device after MTU change\n"); 1220 } 1221 1222 return 0; 1223 } 1224 1225 static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep) 1226 { 1227 int tx_desc_curr; 1228 1229 tx_desc_curr = pep->tx_curr_desc_q; 1230 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size; 1231 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q); 1232 pep->tx_desc_count++; 1233 1234 return tx_desc_curr; 1235 } 1236 1237 static int pxa168_rx_poll(struct napi_struct *napi, int budget) 1238 { 1239 struct pxa168_eth_private *pep = 1240 container_of(napi, struct pxa168_eth_private, napi); 1241 struct net_device *dev = pep->dev; 1242 int work_done = 0; 1243 1244 /* 1245 * We call txq_reclaim every time since in NAPI interupts are disabled 1246 * and due to this we miss the TX_DONE interrupt,which is not updated in 1247 * interrupt status register. 1248 */ 1249 txq_reclaim(dev, 0); 1250 if (netif_queue_stopped(dev) 1251 && pep->tx_ring_size - pep->tx_desc_count > 1) { 1252 netif_wake_queue(dev); 1253 } 1254 work_done = rxq_process(dev, budget); 1255 if (work_done < budget) { 1256 napi_complete_done(napi, work_done); 1257 wrl(pep, INT_MASK, ALL_INTS); 1258 } 1259 1260 return work_done; 1261 } 1262 1263 static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) 1264 { 1265 struct pxa168_eth_private *pep = netdev_priv(dev); 1266 struct net_device_stats *stats = &dev->stats; 1267 struct tx_desc *desc; 1268 int tx_index; 1269 int length; 1270 1271 tx_index = eth_alloc_tx_desc_index(pep); 1272 desc = &pep->p_tx_desc_area[tx_index]; 1273 length = skb->len; 1274 pep->tx_skb[tx_index] = skb; 1275 desc->byte_cnt = length; 1276 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); 1277 1278 skb_tx_timestamp(skb); 1279 1280 dma_wmb(); 1281 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC | 1282 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT; 1283 wmb(); 1284 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD); 1285 1286 stats->tx_bytes += length; 1287 stats->tx_packets++; 1288 netif_trans_update(dev); 1289 if (pep->tx_ring_size - pep->tx_desc_count <= 1) { 1290 /* We handled the current skb, but now we are out of space.*/ 1291 netif_stop_queue(dev); 1292 } 1293 1294 return NETDEV_TX_OK; 1295 } 1296 1297 static int smi_wait_ready(struct pxa168_eth_private *pep) 1298 { 1299 int i = 0; 1300 1301 /* wait for the SMI register to become available */ 1302 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) { 1303 if (i == PHY_WAIT_ITERATIONS) 1304 return -ETIMEDOUT; 1305 msleep(10); 1306 } 1307 1308 return 0; 1309 } 1310 1311 static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum) 1312 { 1313 struct pxa168_eth_private *pep = bus->priv; 1314 int i = 0; 1315 int val; 1316 1317 if (smi_wait_ready(pep)) { 1318 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); 1319 return -ETIMEDOUT; 1320 } 1321 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R); 1322 /* now wait for the data to be valid */ 1323 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) { 1324 if (i == PHY_WAIT_ITERATIONS) { 1325 netdev_warn(pep->dev, 1326 "pxa168_eth: SMI bus read not valid\n"); 1327 return -ENODEV; 1328 } 1329 msleep(10); 1330 } 1331 1332 return val & 0xffff; 1333 } 1334 1335 static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum, 1336 u16 value) 1337 { 1338 struct pxa168_eth_private *pep = bus->priv; 1339 1340 if (smi_wait_ready(pep)) { 1341 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); 1342 return -ETIMEDOUT; 1343 } 1344 1345 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | 1346 SMI_OP_W | (value & 0xffff)); 1347 1348 if (smi_wait_ready(pep)) { 1349 netdev_err(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); 1350 return -ETIMEDOUT; 1351 } 1352 1353 return 0; 1354 } 1355 1356 static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, 1357 int cmd) 1358 { 1359 if (dev->phydev) 1360 return phy_mii_ioctl(dev->phydev, ifr, cmd); 1361 1362 return -EOPNOTSUPP; 1363 } 1364 1365 #ifdef CONFIG_NET_POLL_CONTROLLER 1366 static void pxa168_eth_netpoll(struct net_device *dev) 1367 { 1368 disable_irq(dev->irq); 1369 pxa168_eth_int_handler(dev->irq, dev); 1370 enable_irq(dev->irq); 1371 } 1372 #endif 1373 1374 static void pxa168_get_drvinfo(struct net_device *dev, 1375 struct ethtool_drvinfo *info) 1376 { 1377 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver)); 1378 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 1379 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); 1380 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info)); 1381 } 1382 1383 static const struct ethtool_ops pxa168_ethtool_ops = { 1384 .get_drvinfo = pxa168_get_drvinfo, 1385 .nway_reset = phy_ethtool_nway_reset, 1386 .get_link = ethtool_op_get_link, 1387 .get_ts_info = ethtool_op_get_ts_info, 1388 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1389 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1390 }; 1391 1392 static const struct net_device_ops pxa168_eth_netdev_ops = { 1393 .ndo_open = pxa168_eth_open, 1394 .ndo_stop = pxa168_eth_stop, 1395 .ndo_start_xmit = pxa168_eth_start_xmit, 1396 .ndo_set_rx_mode = pxa168_eth_set_rx_mode, 1397 .ndo_set_mac_address = pxa168_eth_set_mac_address, 1398 .ndo_validate_addr = eth_validate_addr, 1399 .ndo_do_ioctl = pxa168_eth_do_ioctl, 1400 .ndo_change_mtu = pxa168_eth_change_mtu, 1401 .ndo_tx_timeout = pxa168_eth_tx_timeout, 1402 #ifdef CONFIG_NET_POLL_CONTROLLER 1403 .ndo_poll_controller = pxa168_eth_netpoll, 1404 #endif 1405 }; 1406 1407 static int pxa168_eth_probe(struct platform_device *pdev) 1408 { 1409 struct pxa168_eth_private *pep = NULL; 1410 struct net_device *dev = NULL; 1411 struct resource *res; 1412 struct clk *clk; 1413 struct device_node *np; 1414 const unsigned char *mac_addr = NULL; 1415 int err; 1416 1417 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n"); 1418 1419 clk = devm_clk_get(&pdev->dev, NULL); 1420 if (IS_ERR(clk)) { 1421 dev_err(&pdev->dev, "Fast Ethernet failed to get clock\n"); 1422 return -ENODEV; 1423 } 1424 clk_prepare_enable(clk); 1425 1426 dev = alloc_etherdev(sizeof(struct pxa168_eth_private)); 1427 if (!dev) { 1428 err = -ENOMEM; 1429 goto err_clk; 1430 } 1431 1432 platform_set_drvdata(pdev, dev); 1433 pep = netdev_priv(dev); 1434 pep->dev = dev; 1435 pep->clk = clk; 1436 1437 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1438 pep->base = devm_ioremap_resource(&pdev->dev, res); 1439 if (IS_ERR(pep->base)) { 1440 err = -ENOMEM; 1441 goto err_netdev; 1442 } 1443 1444 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1445 BUG_ON(!res); 1446 dev->irq = res->start; 1447 dev->netdev_ops = &pxa168_eth_netdev_ops; 1448 dev->watchdog_timeo = 2 * HZ; 1449 dev->base_addr = 0; 1450 dev->ethtool_ops = &pxa168_ethtool_ops; 1451 1452 /* MTU range: 68 - 9500 */ 1453 dev->min_mtu = ETH_MIN_MTU; 1454 dev->max_mtu = 9500; 1455 1456 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task); 1457 1458 if (pdev->dev.of_node) 1459 mac_addr = of_get_mac_address(pdev->dev.of_node); 1460 1461 if (mac_addr && is_valid_ether_addr(mac_addr)) { 1462 ether_addr_copy(dev->dev_addr, mac_addr); 1463 } else { 1464 /* try reading the mac address, if set by the bootloader */ 1465 pxa168_eth_get_mac_address(dev, dev->dev_addr); 1466 if (!is_valid_ether_addr(dev->dev_addr)) { 1467 dev_info(&pdev->dev, "Using random mac address\n"); 1468 eth_hw_addr_random(dev); 1469 } 1470 } 1471 1472 pep->rx_ring_size = NUM_RX_DESCS; 1473 pep->tx_ring_size = NUM_TX_DESCS; 1474 1475 pep->pd = dev_get_platdata(&pdev->dev); 1476 if (pep->pd) { 1477 if (pep->pd->rx_queue_size) 1478 pep->rx_ring_size = pep->pd->rx_queue_size; 1479 1480 if (pep->pd->tx_queue_size) 1481 pep->tx_ring_size = pep->pd->tx_queue_size; 1482 1483 pep->port_num = pep->pd->port_number; 1484 pep->phy_addr = pep->pd->phy_addr; 1485 pep->phy_speed = pep->pd->speed; 1486 pep->phy_duplex = pep->pd->duplex; 1487 pep->phy_intf = pep->pd->intf; 1488 1489 if (pep->pd->init) 1490 pep->pd->init(); 1491 } else if (pdev->dev.of_node) { 1492 of_property_read_u32(pdev->dev.of_node, "port-id", 1493 &pep->port_num); 1494 1495 np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1496 if (!np) { 1497 dev_err(&pdev->dev, "missing phy-handle\n"); 1498 err = -EINVAL; 1499 goto err_netdev; 1500 } 1501 of_property_read_u32(np, "reg", &pep->phy_addr); 1502 pep->phy_intf = of_get_phy_mode(pdev->dev.of_node); 1503 of_node_put(np); 1504 } 1505 1506 /* Hardware supports only 3 ports */ 1507 BUG_ON(pep->port_num > 2); 1508 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size); 1509 1510 memset(&pep->timeout, 0, sizeof(struct timer_list)); 1511 timer_setup(&pep->timeout, rxq_refill_timer_wrapper, 0); 1512 1513 pep->smi_bus = mdiobus_alloc(); 1514 if (!pep->smi_bus) { 1515 err = -ENOMEM; 1516 goto err_netdev; 1517 } 1518 pep->smi_bus->priv = pep; 1519 pep->smi_bus->name = "pxa168_eth smi"; 1520 pep->smi_bus->read = pxa168_smi_read; 1521 pep->smi_bus->write = pxa168_smi_write; 1522 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1523 pdev->name, pdev->id); 1524 pep->smi_bus->parent = &pdev->dev; 1525 pep->smi_bus->phy_mask = 0xffffffff; 1526 err = mdiobus_register(pep->smi_bus); 1527 if (err) 1528 goto err_free_mdio; 1529 1530 SET_NETDEV_DEV(dev, &pdev->dev); 1531 pxa168_init_hw(pep); 1532 err = register_netdev(dev); 1533 if (err) 1534 goto err_mdiobus; 1535 return 0; 1536 1537 err_mdiobus: 1538 mdiobus_unregister(pep->smi_bus); 1539 err_free_mdio: 1540 mdiobus_free(pep->smi_bus); 1541 err_netdev: 1542 free_netdev(dev); 1543 err_clk: 1544 clk_disable_unprepare(clk); 1545 return err; 1546 } 1547 1548 static int pxa168_eth_remove(struct platform_device *pdev) 1549 { 1550 struct net_device *dev = platform_get_drvdata(pdev); 1551 struct pxa168_eth_private *pep = netdev_priv(dev); 1552 1553 if (pep->htpr) { 1554 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE, 1555 pep->htpr, pep->htpr_dma); 1556 pep->htpr = NULL; 1557 } 1558 if (dev->phydev) 1559 phy_disconnect(dev->phydev); 1560 if (pep->clk) { 1561 clk_disable_unprepare(pep->clk); 1562 } 1563 1564 mdiobus_unregister(pep->smi_bus); 1565 mdiobus_free(pep->smi_bus); 1566 unregister_netdev(dev); 1567 cancel_work_sync(&pep->tx_timeout_task); 1568 free_netdev(dev); 1569 return 0; 1570 } 1571 1572 static void pxa168_eth_shutdown(struct platform_device *pdev) 1573 { 1574 struct net_device *dev = platform_get_drvdata(pdev); 1575 eth_port_reset(dev); 1576 } 1577 1578 #ifdef CONFIG_PM 1579 static int pxa168_eth_resume(struct platform_device *pdev) 1580 { 1581 return -ENOSYS; 1582 } 1583 1584 static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state) 1585 { 1586 return -ENOSYS; 1587 } 1588 1589 #else 1590 #define pxa168_eth_resume NULL 1591 #define pxa168_eth_suspend NULL 1592 #endif 1593 1594 static const struct of_device_id pxa168_eth_of_match[] = { 1595 { .compatible = "marvell,pxa168-eth" }, 1596 { }, 1597 }; 1598 MODULE_DEVICE_TABLE(of, pxa168_eth_of_match); 1599 1600 static struct platform_driver pxa168_eth_driver = { 1601 .probe = pxa168_eth_probe, 1602 .remove = pxa168_eth_remove, 1603 .shutdown = pxa168_eth_shutdown, 1604 .resume = pxa168_eth_resume, 1605 .suspend = pxa168_eth_suspend, 1606 .driver = { 1607 .name = DRIVER_NAME, 1608 .of_match_table = of_match_ptr(pxa168_eth_of_match), 1609 }, 1610 }; 1611 1612 module_platform_driver(pxa168_eth_driver); 1613 1614 MODULE_LICENSE("GPL"); 1615 MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168"); 1616 MODULE_ALIAS("platform:pxa168_eth"); 1617