1 /* 2 * PXA168 ethernet driver. 3 * Most of the code is derived from mv643xx ethernet driver. 4 * 5 * Copyright (C) 2010 Marvell International Ltd. 6 * Sachin Sanap <ssanap@marvell.com> 7 * Zhangfei Gao <zgao6@marvell.com> 8 * Philip Rakity <prakity@marvell.com> 9 * Mark Brown <markb@marvell.com> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 2 14 * of the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include <linux/dma-mapping.h> 26 #include <linux/in.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/udp.h> 30 #include <linux/etherdevice.h> 31 #include <linux/bitops.h> 32 #include <linux/delay.h> 33 #include <linux/ethtool.h> 34 #include <linux/platform_device.h> 35 #include <linux/module.h> 36 #include <linux/kernel.h> 37 #include <linux/workqueue.h> 38 #include <linux/clk.h> 39 #include <linux/phy.h> 40 #include <linux/io.h> 41 #include <linux/interrupt.h> 42 #include <linux/types.h> 43 #include <asm/pgtable.h> 44 #include <asm/cacheflush.h> 45 #include <linux/pxa168_eth.h> 46 47 #define DRIVER_NAME "pxa168-eth" 48 #define DRIVER_VERSION "0.3" 49 50 /* 51 * Registers 52 */ 53 54 #define PHY_ADDRESS 0x0000 55 #define SMI 0x0010 56 #define PORT_CONFIG 0x0400 57 #define PORT_CONFIG_EXT 0x0408 58 #define PORT_COMMAND 0x0410 59 #define PORT_STATUS 0x0418 60 #define HTPR 0x0428 61 #define SDMA_CONFIG 0x0440 62 #define SDMA_CMD 0x0448 63 #define INT_CAUSE 0x0450 64 #define INT_W_CLEAR 0x0454 65 #define INT_MASK 0x0458 66 #define ETH_F_RX_DESC_0 0x0480 67 #define ETH_C_RX_DESC_0 0x04A0 68 #define ETH_C_TX_DESC_1 0x04E4 69 70 /* smi register */ 71 #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */ 72 #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */ 73 #define SMI_OP_W (0 << 26) /* Write operation */ 74 #define SMI_OP_R (1 << 26) /* Read operation */ 75 76 #define PHY_WAIT_ITERATIONS 10 77 78 #define PXA168_ETH_PHY_ADDR_DEFAULT 0 79 /* RX & TX descriptor command */ 80 #define BUF_OWNED_BY_DMA (1 << 31) 81 82 /* RX descriptor status */ 83 #define RX_EN_INT (1 << 23) 84 #define RX_FIRST_DESC (1 << 17) 85 #define RX_LAST_DESC (1 << 16) 86 #define RX_ERROR (1 << 15) 87 88 /* TX descriptor command */ 89 #define TX_EN_INT (1 << 23) 90 #define TX_GEN_CRC (1 << 22) 91 #define TX_ZERO_PADDING (1 << 18) 92 #define TX_FIRST_DESC (1 << 17) 93 #define TX_LAST_DESC (1 << 16) 94 #define TX_ERROR (1 << 15) 95 96 /* SDMA_CMD */ 97 #define SDMA_CMD_AT (1 << 31) 98 #define SDMA_CMD_TXDL (1 << 24) 99 #define SDMA_CMD_TXDH (1 << 23) 100 #define SDMA_CMD_AR (1 << 15) 101 #define SDMA_CMD_ERD (1 << 7) 102 103 /* Bit definitions of the Port Config Reg */ 104 #define PCR_HS (1 << 12) 105 #define PCR_EN (1 << 7) 106 #define PCR_PM (1 << 0) 107 108 /* Bit definitions of the Port Config Extend Reg */ 109 #define PCXR_2BSM (1 << 28) 110 #define PCXR_DSCP_EN (1 << 21) 111 #define PCXR_MFL_1518 (0 << 14) 112 #define PCXR_MFL_1536 (1 << 14) 113 #define PCXR_MFL_2048 (2 << 14) 114 #define PCXR_MFL_64K (3 << 14) 115 #define PCXR_FLP (1 << 11) 116 #define PCXR_PRIO_TX_OFF 3 117 #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF) 118 119 /* Bit definitions of the SDMA Config Reg */ 120 #define SDCR_BSZ_OFF 12 121 #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF) 122 #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF) 123 #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF) 124 #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF) 125 #define SDCR_BLMR (1 << 6) 126 #define SDCR_BLMT (1 << 7) 127 #define SDCR_RIFB (1 << 9) 128 #define SDCR_RC_OFF 2 129 #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) 130 131 /* 132 * Bit definitions of the Interrupt Cause Reg 133 * and Interrupt MASK Reg is the same 134 */ 135 #define ICR_RXBUF (1 << 0) 136 #define ICR_TXBUF_H (1 << 2) 137 #define ICR_TXBUF_L (1 << 3) 138 #define ICR_TXEND_H (1 << 6) 139 #define ICR_TXEND_L (1 << 7) 140 #define ICR_RXERR (1 << 8) 141 #define ICR_TXERR_H (1 << 10) 142 #define ICR_TXERR_L (1 << 11) 143 #define ICR_TX_UDR (1 << 13) 144 #define ICR_MII_CH (1 << 28) 145 146 #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ 147 ICR_TXERR_H | ICR_TXERR_L |\ 148 ICR_TXEND_H | ICR_TXEND_L |\ 149 ICR_RXBUF | ICR_RXERR | ICR_MII_CH) 150 151 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ 152 153 #define NUM_RX_DESCS 64 154 #define NUM_TX_DESCS 64 155 156 #define HASH_ADD 0 157 #define HASH_DELETE 1 158 #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ 159 #define HOP_NUMBER 12 160 161 /* Bit definitions for Port status */ 162 #define PORT_SPEED_100 (1 << 0) 163 #define FULL_DUPLEX (1 << 1) 164 #define FLOW_CONTROL_ENABLED (1 << 2) 165 #define LINK_UP (1 << 3) 166 167 /* Bit definitions for work to be done */ 168 #define WORK_LINK (1 << 0) 169 #define WORK_TX_DONE (1 << 1) 170 171 /* 172 * Misc definitions. 173 */ 174 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 175 176 struct rx_desc { 177 u32 cmd_sts; /* Descriptor command status */ 178 u16 byte_cnt; /* Descriptor buffer byte count */ 179 u16 buf_size; /* Buffer size */ 180 u32 buf_ptr; /* Descriptor buffer pointer */ 181 u32 next_desc_ptr; /* Next descriptor pointer */ 182 }; 183 184 struct tx_desc { 185 u32 cmd_sts; /* Command/status field */ 186 u16 reserved; 187 u16 byte_cnt; /* buffer byte count */ 188 u32 buf_ptr; /* pointer to buffer for this descriptor */ 189 u32 next_desc_ptr; /* Pointer to next descriptor */ 190 }; 191 192 struct pxa168_eth_private { 193 int port_num; /* User Ethernet port number */ 194 195 int rx_resource_err; /* Rx ring resource error flag */ 196 197 /* Next available and first returning Rx resource */ 198 int rx_curr_desc_q, rx_used_desc_q; 199 200 /* Next available and first returning Tx resource */ 201 int tx_curr_desc_q, tx_used_desc_q; 202 203 struct rx_desc *p_rx_desc_area; 204 dma_addr_t rx_desc_dma; 205 int rx_desc_area_size; 206 struct sk_buff **rx_skb; 207 208 struct tx_desc *p_tx_desc_area; 209 dma_addr_t tx_desc_dma; 210 int tx_desc_area_size; 211 struct sk_buff **tx_skb; 212 213 struct work_struct tx_timeout_task; 214 215 struct net_device *dev; 216 struct napi_struct napi; 217 u8 work_todo; 218 int skb_size; 219 220 /* Size of Tx Ring per queue */ 221 int tx_ring_size; 222 /* Number of tx descriptors in use */ 223 int tx_desc_count; 224 /* Size of Rx Ring per queue */ 225 int rx_ring_size; 226 /* Number of rx descriptors in use */ 227 int rx_desc_count; 228 229 /* 230 * Used in case RX Ring is empty, which can occur when 231 * system does not have resources (skb's) 232 */ 233 struct timer_list timeout; 234 struct mii_bus *smi_bus; 235 struct phy_device *phy; 236 237 /* clock */ 238 struct clk *clk; 239 struct pxa168_eth_platform_data *pd; 240 /* 241 * Ethernet controller base address. 242 */ 243 void __iomem *base; 244 245 /* Pointer to the hardware address filter table */ 246 void *htpr; 247 dma_addr_t htpr_dma; 248 }; 249 250 struct addr_table_entry { 251 __le32 lo; 252 __le32 hi; 253 }; 254 255 /* Bit fields of a Hash Table Entry */ 256 enum hash_table_entry { 257 HASH_ENTRY_VALID = 1, 258 SKIP = 2, 259 HASH_ENTRY_RECEIVE_DISCARD = 4, 260 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2 261 }; 262 263 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd); 264 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd); 265 static int pxa168_init_hw(struct pxa168_eth_private *pep); 266 static void eth_port_reset(struct net_device *dev); 267 static void eth_port_start(struct net_device *dev); 268 static int pxa168_eth_open(struct net_device *dev); 269 static int pxa168_eth_stop(struct net_device *dev); 270 static int ethernet_phy_setup(struct net_device *dev); 271 272 static inline u32 rdl(struct pxa168_eth_private *pep, int offset) 273 { 274 return readl(pep->base + offset); 275 } 276 277 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data) 278 { 279 writel(data, pep->base + offset); 280 } 281 282 static void abort_dma(struct pxa168_eth_private *pep) 283 { 284 int delay; 285 int max_retries = 40; 286 287 do { 288 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT); 289 udelay(100); 290 291 delay = 10; 292 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT)) 293 && delay-- > 0) { 294 udelay(10); 295 } 296 } while (max_retries-- > 0 && delay <= 0); 297 298 if (max_retries <= 0) 299 printk(KERN_ERR "%s : DMA Stuck\n", __func__); 300 } 301 302 static int ethernet_phy_get(struct pxa168_eth_private *pep) 303 { 304 unsigned int reg_data; 305 306 reg_data = rdl(pep, PHY_ADDRESS); 307 308 return (reg_data >> (5 * pep->port_num)) & 0x1f; 309 } 310 311 static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr) 312 { 313 u32 reg_data; 314 int addr_shift = 5 * pep->port_num; 315 316 reg_data = rdl(pep, PHY_ADDRESS); 317 reg_data &= ~(0x1f << addr_shift); 318 reg_data |= (phy_addr & 0x1f) << addr_shift; 319 wrl(pep, PHY_ADDRESS, reg_data); 320 } 321 322 static void rxq_refill(struct net_device *dev) 323 { 324 struct pxa168_eth_private *pep = netdev_priv(dev); 325 struct sk_buff *skb; 326 struct rx_desc *p_used_rx_desc; 327 int used_rx_desc; 328 329 while (pep->rx_desc_count < pep->rx_ring_size) { 330 int size; 331 332 skb = netdev_alloc_skb(dev, pep->skb_size); 333 if (!skb) 334 break; 335 if (SKB_DMA_REALIGN) 336 skb_reserve(skb, SKB_DMA_REALIGN); 337 pep->rx_desc_count++; 338 /* Get 'used' Rx descriptor */ 339 used_rx_desc = pep->rx_used_desc_q; 340 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc]; 341 size = skb_end_pointer(skb) - skb->data; 342 p_used_rx_desc->buf_ptr = dma_map_single(NULL, 343 skb->data, 344 size, 345 DMA_FROM_DEVICE); 346 p_used_rx_desc->buf_size = size; 347 pep->rx_skb[used_rx_desc] = skb; 348 349 /* Return the descriptor to DMA ownership */ 350 wmb(); 351 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; 352 wmb(); 353 354 /* Move the used descriptor pointer to the next descriptor */ 355 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size; 356 357 /* Any Rx return cancels the Rx resource error status */ 358 pep->rx_resource_err = 0; 359 360 skb_reserve(skb, ETH_HW_IP_ALIGN); 361 } 362 363 /* 364 * If RX ring is empty of SKB, set a timer to try allocating 365 * again at a later time. 366 */ 367 if (pep->rx_desc_count == 0) { 368 pep->timeout.expires = jiffies + (HZ / 10); 369 add_timer(&pep->timeout); 370 } 371 } 372 373 static inline void rxq_refill_timer_wrapper(unsigned long data) 374 { 375 struct pxa168_eth_private *pep = (void *)data; 376 napi_schedule(&pep->napi); 377 } 378 379 static inline u8 flip_8_bits(u8 x) 380 { 381 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1) 382 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3) 383 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1) 384 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3); 385 } 386 387 static void nibble_swap_every_byte(unsigned char *mac_addr) 388 { 389 int i; 390 for (i = 0; i < ETH_ALEN; i++) { 391 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) | 392 ((mac_addr[i] & 0xf0) >> 4); 393 } 394 } 395 396 static void inverse_every_nibble(unsigned char *mac_addr) 397 { 398 int i; 399 for (i = 0; i < ETH_ALEN; i++) 400 mac_addr[i] = flip_8_bits(mac_addr[i]); 401 } 402 403 /* 404 * ---------------------------------------------------------------------------- 405 * This function will calculate the hash function of the address. 406 * Inputs 407 * mac_addr_orig - MAC address. 408 * Outputs 409 * return the calculated entry. 410 */ 411 static u32 hash_function(unsigned char *mac_addr_orig) 412 { 413 u32 hash_result; 414 u32 addr0; 415 u32 addr1; 416 u32 addr2; 417 u32 addr3; 418 unsigned char mac_addr[ETH_ALEN]; 419 420 /* Make a copy of MAC address since we are going to performe bit 421 * operations on it 422 */ 423 memcpy(mac_addr, mac_addr_orig, ETH_ALEN); 424 425 nibble_swap_every_byte(mac_addr); 426 inverse_every_nibble(mac_addr); 427 428 addr0 = (mac_addr[5] >> 2) & 0x3f; 429 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2); 430 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1; 431 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8); 432 433 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); 434 hash_result = hash_result & 0x07ff; 435 return hash_result; 436 } 437 438 /* 439 * ---------------------------------------------------------------------------- 440 * This function will add/del an entry to the address table. 441 * Inputs 442 * pep - ETHERNET . 443 * mac_addr - MAC address. 444 * skip - if 1, skip this address.Used in case of deleting an entry which is a 445 * part of chain in the hash table.We can't just delete the entry since 446 * that will break the chain.We need to defragment the tables time to 447 * time. 448 * rd - 0 Discard packet upon match. 449 * - 1 Receive packet upon match. 450 * Outputs 451 * address table entry is added/deleted. 452 * 0 if success. 453 * -ENOSPC if table full 454 */ 455 static int add_del_hash_entry(struct pxa168_eth_private *pep, 456 unsigned char *mac_addr, 457 u32 rd, u32 skip, int del) 458 { 459 struct addr_table_entry *entry, *start; 460 u32 new_high; 461 u32 new_low; 462 u32 i; 463 464 new_low = (((mac_addr[1] >> 4) & 0xf) << 15) 465 | (((mac_addr[1] >> 0) & 0xf) << 11) 466 | (((mac_addr[0] >> 4) & 0xf) << 7) 467 | (((mac_addr[0] >> 0) & 0xf) << 3) 468 | (((mac_addr[3] >> 4) & 0x1) << 31) 469 | (((mac_addr[3] >> 0) & 0xf) << 27) 470 | (((mac_addr[2] >> 4) & 0xf) << 23) 471 | (((mac_addr[2] >> 0) & 0xf) << 19) 472 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT) 473 | HASH_ENTRY_VALID; 474 475 new_high = (((mac_addr[5] >> 4) & 0xf) << 15) 476 | (((mac_addr[5] >> 0) & 0xf) << 11) 477 | (((mac_addr[4] >> 4) & 0xf) << 7) 478 | (((mac_addr[4] >> 0) & 0xf) << 3) 479 | (((mac_addr[3] >> 5) & 0x7) << 0); 480 481 /* 482 * Pick the appropriate table, start scanning for free/reusable 483 * entries at the index obtained by hashing the specified MAC address 484 */ 485 start = pep->htpr; 486 entry = start + hash_function(mac_addr); 487 for (i = 0; i < HOP_NUMBER; i++) { 488 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) { 489 break; 490 } else { 491 /* if same address put in same position */ 492 if (((le32_to_cpu(entry->lo) & 0xfffffff8) == 493 (new_low & 0xfffffff8)) && 494 (le32_to_cpu(entry->hi) == new_high)) { 495 break; 496 } 497 } 498 if (entry == start + 0x7ff) 499 entry = start; 500 else 501 entry++; 502 } 503 504 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) && 505 (le32_to_cpu(entry->hi) != new_high) && del) 506 return 0; 507 508 if (i == HOP_NUMBER) { 509 if (!del) { 510 printk(KERN_INFO "%s: table section is full, need to " 511 "move to 16kB implementation?\n", 512 __FILE__); 513 return -ENOSPC; 514 } else 515 return 0; 516 } 517 518 /* 519 * Update the selected entry 520 */ 521 if (del) { 522 entry->hi = 0; 523 entry->lo = 0; 524 } else { 525 entry->hi = cpu_to_le32(new_high); 526 entry->lo = cpu_to_le32(new_low); 527 } 528 529 return 0; 530 } 531 532 /* 533 * ---------------------------------------------------------------------------- 534 * Create an addressTable entry from MAC address info 535 * found in the specifed net_device struct 536 * 537 * Input : pointer to ethernet interface network device structure 538 * Output : N/A 539 */ 540 static void update_hash_table_mac_address(struct pxa168_eth_private *pep, 541 unsigned char *oaddr, 542 unsigned char *addr) 543 { 544 /* Delete old entry */ 545 if (oaddr) 546 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE); 547 /* Add new entry */ 548 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD); 549 } 550 551 static int init_hash_table(struct pxa168_eth_private *pep) 552 { 553 /* 554 * Hardware expects CPU to build a hash table based on a predefined 555 * hash function and populate it based on hardware address. The 556 * location of the hash table is identified by 32-bit pointer stored 557 * in HTPR internal register. Two possible sizes exists for the hash 558 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB 559 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support 560 * 1/2kB. 561 */ 562 /* TODO: Add support for 8kB hash table and alternative hash 563 * function.Driver can dynamically switch to them if the 1/2kB hash 564 * table is full. 565 */ 566 if (pep->htpr == NULL) { 567 pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent, 568 HASH_ADDR_TABLE_SIZE, 569 &pep->htpr_dma, GFP_KERNEL); 570 if (pep->htpr == NULL) 571 return -ENOMEM; 572 } else { 573 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); 574 } 575 wrl(pep, HTPR, pep->htpr_dma); 576 return 0; 577 } 578 579 static void pxa168_eth_set_rx_mode(struct net_device *dev) 580 { 581 struct pxa168_eth_private *pep = netdev_priv(dev); 582 struct netdev_hw_addr *ha; 583 u32 val; 584 585 val = rdl(pep, PORT_CONFIG); 586 if (dev->flags & IFF_PROMISC) 587 val |= PCR_PM; 588 else 589 val &= ~PCR_PM; 590 wrl(pep, PORT_CONFIG, val); 591 592 /* 593 * Remove the old list of MAC address and add dev->addr 594 * and multicast address. 595 */ 596 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); 597 update_hash_table_mac_address(pep, NULL, dev->dev_addr); 598 599 netdev_for_each_mc_addr(ha, dev) 600 update_hash_table_mac_address(pep, NULL, ha->addr); 601 } 602 603 static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr) 604 { 605 struct sockaddr *sa = addr; 606 struct pxa168_eth_private *pep = netdev_priv(dev); 607 unsigned char oldMac[ETH_ALEN]; 608 609 if (!is_valid_ether_addr(sa->sa_data)) 610 return -EADDRNOTAVAIL; 611 memcpy(oldMac, dev->dev_addr, ETH_ALEN); 612 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); 613 netif_addr_lock_bh(dev); 614 update_hash_table_mac_address(pep, oldMac, dev->dev_addr); 615 netif_addr_unlock_bh(dev); 616 return 0; 617 } 618 619 static void eth_port_start(struct net_device *dev) 620 { 621 unsigned int val = 0; 622 struct pxa168_eth_private *pep = netdev_priv(dev); 623 int tx_curr_desc, rx_curr_desc; 624 625 /* Perform PHY reset, if there is a PHY. */ 626 if (pep->phy != NULL) { 627 struct ethtool_cmd cmd; 628 629 pxa168_get_settings(pep->dev, &cmd); 630 phy_init_hw(pep->phy); 631 pxa168_set_settings(pep->dev, &cmd); 632 } 633 634 /* Assignment of Tx CTRP of given queue */ 635 tx_curr_desc = pep->tx_curr_desc_q; 636 wrl(pep, ETH_C_TX_DESC_1, 637 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc))); 638 639 /* Assignment of Rx CRDP of given queue */ 640 rx_curr_desc = pep->rx_curr_desc_q; 641 wrl(pep, ETH_C_RX_DESC_0, 642 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); 643 644 wrl(pep, ETH_F_RX_DESC_0, 645 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); 646 647 /* Clear all interrupts */ 648 wrl(pep, INT_CAUSE, 0); 649 650 /* Enable all interrupts for receive, transmit and error. */ 651 wrl(pep, INT_MASK, ALL_INTS); 652 653 val = rdl(pep, PORT_CONFIG); 654 val |= PCR_EN; 655 wrl(pep, PORT_CONFIG, val); 656 657 /* Start RX DMA engine */ 658 val = rdl(pep, SDMA_CMD); 659 val |= SDMA_CMD_ERD; 660 wrl(pep, SDMA_CMD, val); 661 } 662 663 static void eth_port_reset(struct net_device *dev) 664 { 665 struct pxa168_eth_private *pep = netdev_priv(dev); 666 unsigned int val = 0; 667 668 /* Stop all interrupts for receive, transmit and error. */ 669 wrl(pep, INT_MASK, 0); 670 671 /* Clear all interrupts */ 672 wrl(pep, INT_CAUSE, 0); 673 674 /* Stop RX DMA */ 675 val = rdl(pep, SDMA_CMD); 676 val &= ~SDMA_CMD_ERD; /* abort dma command */ 677 678 /* Abort any transmit and receive operations and put DMA 679 * in idle state. 680 */ 681 abort_dma(pep); 682 683 /* Disable port */ 684 val = rdl(pep, PORT_CONFIG); 685 val &= ~PCR_EN; 686 wrl(pep, PORT_CONFIG, val); 687 } 688 689 /* 690 * txq_reclaim - Free the tx desc data for completed descriptors 691 * If force is non-zero, frees uncompleted descriptors as well 692 */ 693 static int txq_reclaim(struct net_device *dev, int force) 694 { 695 struct pxa168_eth_private *pep = netdev_priv(dev); 696 struct tx_desc *desc; 697 u32 cmd_sts; 698 struct sk_buff *skb; 699 int tx_index; 700 dma_addr_t addr; 701 int count; 702 int released = 0; 703 704 netif_tx_lock(dev); 705 706 pep->work_todo &= ~WORK_TX_DONE; 707 while (pep->tx_desc_count > 0) { 708 tx_index = pep->tx_used_desc_q; 709 desc = &pep->p_tx_desc_area[tx_index]; 710 cmd_sts = desc->cmd_sts; 711 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) { 712 if (released > 0) { 713 goto txq_reclaim_end; 714 } else { 715 released = -1; 716 goto txq_reclaim_end; 717 } 718 } 719 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size; 720 pep->tx_desc_count--; 721 addr = desc->buf_ptr; 722 count = desc->byte_cnt; 723 skb = pep->tx_skb[tx_index]; 724 if (skb) 725 pep->tx_skb[tx_index] = NULL; 726 727 if (cmd_sts & TX_ERROR) { 728 if (net_ratelimit()) 729 printk(KERN_ERR "%s: Error in TX\n", dev->name); 730 dev->stats.tx_errors++; 731 } 732 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); 733 if (skb) 734 dev_kfree_skb_irq(skb); 735 released++; 736 } 737 txq_reclaim_end: 738 netif_tx_unlock(dev); 739 return released; 740 } 741 742 static void pxa168_eth_tx_timeout(struct net_device *dev) 743 { 744 struct pxa168_eth_private *pep = netdev_priv(dev); 745 746 printk(KERN_INFO "%s: TX timeout desc_count %d\n", 747 dev->name, pep->tx_desc_count); 748 749 schedule_work(&pep->tx_timeout_task); 750 } 751 752 static void pxa168_eth_tx_timeout_task(struct work_struct *work) 753 { 754 struct pxa168_eth_private *pep = container_of(work, 755 struct pxa168_eth_private, 756 tx_timeout_task); 757 struct net_device *dev = pep->dev; 758 pxa168_eth_stop(dev); 759 pxa168_eth_open(dev); 760 } 761 762 static int rxq_process(struct net_device *dev, int budget) 763 { 764 struct pxa168_eth_private *pep = netdev_priv(dev); 765 struct net_device_stats *stats = &dev->stats; 766 unsigned int received_packets = 0; 767 struct sk_buff *skb; 768 769 while (budget-- > 0) { 770 int rx_next_curr_desc, rx_curr_desc, rx_used_desc; 771 struct rx_desc *rx_desc; 772 unsigned int cmd_sts; 773 774 /* Do not process Rx ring in case of Rx ring resource error */ 775 if (pep->rx_resource_err) 776 break; 777 rx_curr_desc = pep->rx_curr_desc_q; 778 rx_used_desc = pep->rx_used_desc_q; 779 rx_desc = &pep->p_rx_desc_area[rx_curr_desc]; 780 cmd_sts = rx_desc->cmd_sts; 781 rmb(); 782 if (cmd_sts & (BUF_OWNED_BY_DMA)) 783 break; 784 skb = pep->rx_skb[rx_curr_desc]; 785 pep->rx_skb[rx_curr_desc] = NULL; 786 787 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size; 788 pep->rx_curr_desc_q = rx_next_curr_desc; 789 790 /* Rx descriptors exhausted. */ 791 /* Set the Rx ring resource error flag */ 792 if (rx_next_curr_desc == rx_used_desc) 793 pep->rx_resource_err = 1; 794 pep->rx_desc_count--; 795 dma_unmap_single(NULL, rx_desc->buf_ptr, 796 rx_desc->buf_size, 797 DMA_FROM_DEVICE); 798 received_packets++; 799 /* 800 * Update statistics. 801 * Note byte count includes 4 byte CRC count 802 */ 803 stats->rx_packets++; 804 stats->rx_bytes += rx_desc->byte_cnt; 805 /* 806 * In case received a packet without first / last bits on OR 807 * the error summary bit is on, the packets needs to be droped. 808 */ 809 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 810 (RX_FIRST_DESC | RX_LAST_DESC)) 811 || (cmd_sts & RX_ERROR)) { 812 813 stats->rx_dropped++; 814 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 815 (RX_FIRST_DESC | RX_LAST_DESC)) { 816 if (net_ratelimit()) 817 printk(KERN_ERR 818 "%s: Rx pkt on multiple desc\n", 819 dev->name); 820 } 821 if (cmd_sts & RX_ERROR) 822 stats->rx_errors++; 823 dev_kfree_skb_irq(skb); 824 } else { 825 /* 826 * The -4 is for the CRC in the trailer of the 827 * received packet 828 */ 829 skb_put(skb, rx_desc->byte_cnt - 4); 830 skb->protocol = eth_type_trans(skb, dev); 831 netif_receive_skb(skb); 832 } 833 } 834 /* Fill RX ring with skb's */ 835 rxq_refill(dev); 836 return received_packets; 837 } 838 839 static int pxa168_eth_collect_events(struct pxa168_eth_private *pep, 840 struct net_device *dev) 841 { 842 u32 icr; 843 int ret = 0; 844 845 icr = rdl(pep, INT_CAUSE); 846 if (icr == 0) 847 return IRQ_NONE; 848 849 wrl(pep, INT_CAUSE, ~icr); 850 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) { 851 pep->work_todo |= WORK_TX_DONE; 852 ret = 1; 853 } 854 if (icr & ICR_RXBUF) 855 ret = 1; 856 if (icr & ICR_MII_CH) { 857 pep->work_todo |= WORK_LINK; 858 ret = 1; 859 } 860 return ret; 861 } 862 863 static void handle_link_event(struct pxa168_eth_private *pep) 864 { 865 struct net_device *dev = pep->dev; 866 u32 port_status; 867 int speed; 868 int duplex; 869 int fc; 870 871 port_status = rdl(pep, PORT_STATUS); 872 if (!(port_status & LINK_UP)) { 873 if (netif_carrier_ok(dev)) { 874 printk(KERN_INFO "%s: link down\n", dev->name); 875 netif_carrier_off(dev); 876 txq_reclaim(dev, 1); 877 } 878 return; 879 } 880 if (port_status & PORT_SPEED_100) 881 speed = 100; 882 else 883 speed = 10; 884 885 duplex = (port_status & FULL_DUPLEX) ? 1 : 0; 886 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; 887 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " 888 "flow control %sabled\n", dev->name, 889 speed, duplex ? "full" : "half", fc ? "en" : "dis"); 890 if (!netif_carrier_ok(dev)) 891 netif_carrier_on(dev); 892 } 893 894 static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id) 895 { 896 struct net_device *dev = (struct net_device *)dev_id; 897 struct pxa168_eth_private *pep = netdev_priv(dev); 898 899 if (unlikely(!pxa168_eth_collect_events(pep, dev))) 900 return IRQ_NONE; 901 /* Disable interrupts */ 902 wrl(pep, INT_MASK, 0); 903 napi_schedule(&pep->napi); 904 return IRQ_HANDLED; 905 } 906 907 static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep) 908 { 909 int skb_size; 910 911 /* 912 * Reserve 2+14 bytes for an ethernet header (the hardware 913 * automatically prepends 2 bytes of dummy data to each 914 * received packet), 16 bytes for up to four VLAN tags, and 915 * 4 bytes for the trailing FCS -- 36 bytes total. 916 */ 917 skb_size = pep->dev->mtu + 36; 918 919 /* 920 * Make sure that the skb size is a multiple of 8 bytes, as 921 * the lower three bits of the receive descriptor's buffer 922 * size field are ignored by the hardware. 923 */ 924 pep->skb_size = (skb_size + 7) & ~7; 925 926 /* 927 * If NET_SKB_PAD is smaller than a cache line, 928 * netdev_alloc_skb() will cause skb->data to be misaligned 929 * to a cache line boundary. If this is the case, include 930 * some extra space to allow re-aligning the data area. 931 */ 932 pep->skb_size += SKB_DMA_REALIGN; 933 934 } 935 936 static int set_port_config_ext(struct pxa168_eth_private *pep) 937 { 938 int skb_size; 939 940 pxa168_eth_recalc_skb_size(pep); 941 if (pep->skb_size <= 1518) 942 skb_size = PCXR_MFL_1518; 943 else if (pep->skb_size <= 1536) 944 skb_size = PCXR_MFL_1536; 945 else if (pep->skb_size <= 2048) 946 skb_size = PCXR_MFL_2048; 947 else 948 skb_size = PCXR_MFL_64K; 949 950 /* Extended Port Configuration */ 951 wrl(pep, 952 PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */ 953 PCXR_DSCP_EN | /* Enable DSCP in IP */ 954 skb_size | PCXR_FLP | /* do not force link pass */ 955 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */ 956 957 return 0; 958 } 959 960 static int pxa168_init_hw(struct pxa168_eth_private *pep) 961 { 962 int err = 0; 963 964 /* Disable interrupts */ 965 wrl(pep, INT_MASK, 0); 966 wrl(pep, INT_CAUSE, 0); 967 /* Write to ICR to clear interrupts. */ 968 wrl(pep, INT_W_CLEAR, 0); 969 /* Abort any transmit and receive operations and put DMA 970 * in idle state. 971 */ 972 abort_dma(pep); 973 /* Initialize address hash table */ 974 err = init_hash_table(pep); 975 if (err) 976 return err; 977 /* SDMA configuration */ 978 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */ 979 SDCR_RIFB | /* Rx interrupt on frame */ 980 SDCR_BLMT | /* Little endian transmit */ 981 SDCR_BLMR | /* Little endian receive */ 982 SDCR_RC_MAX_RETRANS); /* Max retransmit count */ 983 /* Port Configuration */ 984 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */ 985 set_port_config_ext(pep); 986 987 return err; 988 } 989 990 static int rxq_init(struct net_device *dev) 991 { 992 struct pxa168_eth_private *pep = netdev_priv(dev); 993 struct rx_desc *p_rx_desc; 994 int size = 0, i = 0; 995 int rx_desc_num = pep->rx_ring_size; 996 997 /* Allocate RX skb rings */ 998 pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size, 999 GFP_KERNEL); 1000 if (!pep->rx_skb) 1001 return -ENOMEM; 1002 1003 /* Allocate RX ring */ 1004 pep->rx_desc_count = 0; 1005 size = pep->rx_ring_size * sizeof(struct rx_desc); 1006 pep->rx_desc_area_size = size; 1007 pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size, 1008 &pep->rx_desc_dma, 1009 GFP_KERNEL); 1010 if (!pep->p_rx_desc_area) 1011 goto out; 1012 1013 /* initialize the next_desc_ptr links in the Rx descriptors ring */ 1014 p_rx_desc = pep->p_rx_desc_area; 1015 for (i = 0; i < rx_desc_num; i++) { 1016 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma + 1017 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc); 1018 } 1019 /* Save Rx desc pointer to driver struct. */ 1020 pep->rx_curr_desc_q = 0; 1021 pep->rx_used_desc_q = 0; 1022 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc); 1023 return 0; 1024 out: 1025 kfree(pep->rx_skb); 1026 return -ENOMEM; 1027 } 1028 1029 static void rxq_deinit(struct net_device *dev) 1030 { 1031 struct pxa168_eth_private *pep = netdev_priv(dev); 1032 int curr; 1033 1034 /* Free preallocated skb's on RX rings */ 1035 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) { 1036 if (pep->rx_skb[curr]) { 1037 dev_kfree_skb(pep->rx_skb[curr]); 1038 pep->rx_desc_count--; 1039 } 1040 } 1041 if (pep->rx_desc_count) 1042 printk(KERN_ERR 1043 "Error in freeing Rx Ring. %d skb's still\n", 1044 pep->rx_desc_count); 1045 /* Free RX ring */ 1046 if (pep->p_rx_desc_area) 1047 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size, 1048 pep->p_rx_desc_area, pep->rx_desc_dma); 1049 kfree(pep->rx_skb); 1050 } 1051 1052 static int txq_init(struct net_device *dev) 1053 { 1054 struct pxa168_eth_private *pep = netdev_priv(dev); 1055 struct tx_desc *p_tx_desc; 1056 int size = 0, i = 0; 1057 int tx_desc_num = pep->tx_ring_size; 1058 1059 pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size, 1060 GFP_KERNEL); 1061 if (!pep->tx_skb) 1062 return -ENOMEM; 1063 1064 /* Allocate TX ring */ 1065 pep->tx_desc_count = 0; 1066 size = pep->tx_ring_size * sizeof(struct tx_desc); 1067 pep->tx_desc_area_size = size; 1068 pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size, 1069 &pep->tx_desc_dma, 1070 GFP_KERNEL); 1071 if (!pep->p_tx_desc_area) 1072 goto out; 1073 /* Initialize the next_desc_ptr links in the Tx descriptors ring */ 1074 p_tx_desc = pep->p_tx_desc_area; 1075 for (i = 0; i < tx_desc_num; i++) { 1076 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma + 1077 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc); 1078 } 1079 pep->tx_curr_desc_q = 0; 1080 pep->tx_used_desc_q = 0; 1081 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc); 1082 return 0; 1083 out: 1084 kfree(pep->tx_skb); 1085 return -ENOMEM; 1086 } 1087 1088 static void txq_deinit(struct net_device *dev) 1089 { 1090 struct pxa168_eth_private *pep = netdev_priv(dev); 1091 1092 /* Free outstanding skb's on TX ring */ 1093 txq_reclaim(dev, 1); 1094 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q); 1095 /* Free TX ring */ 1096 if (pep->p_tx_desc_area) 1097 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size, 1098 pep->p_tx_desc_area, pep->tx_desc_dma); 1099 kfree(pep->tx_skb); 1100 } 1101 1102 static int pxa168_eth_open(struct net_device *dev) 1103 { 1104 struct pxa168_eth_private *pep = netdev_priv(dev); 1105 int err; 1106 1107 err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev); 1108 if (err) { 1109 dev_err(&dev->dev, "can't assign irq\n"); 1110 return -EAGAIN; 1111 } 1112 pep->rx_resource_err = 0; 1113 err = rxq_init(dev); 1114 if (err != 0) 1115 goto out_free_irq; 1116 err = txq_init(dev); 1117 if (err != 0) 1118 goto out_free_rx_skb; 1119 pep->rx_used_desc_q = 0; 1120 pep->rx_curr_desc_q = 0; 1121 1122 /* Fill RX ring with skb's */ 1123 rxq_refill(dev); 1124 pep->rx_used_desc_q = 0; 1125 pep->rx_curr_desc_q = 0; 1126 netif_carrier_off(dev); 1127 eth_port_start(dev); 1128 napi_enable(&pep->napi); 1129 return 0; 1130 out_free_rx_skb: 1131 rxq_deinit(dev); 1132 out_free_irq: 1133 free_irq(dev->irq, dev); 1134 return err; 1135 } 1136 1137 static int pxa168_eth_stop(struct net_device *dev) 1138 { 1139 struct pxa168_eth_private *pep = netdev_priv(dev); 1140 eth_port_reset(dev); 1141 1142 /* Disable interrupts */ 1143 wrl(pep, INT_MASK, 0); 1144 wrl(pep, INT_CAUSE, 0); 1145 /* Write to ICR to clear interrupts. */ 1146 wrl(pep, INT_W_CLEAR, 0); 1147 napi_disable(&pep->napi); 1148 del_timer_sync(&pep->timeout); 1149 netif_carrier_off(dev); 1150 free_irq(dev->irq, dev); 1151 rxq_deinit(dev); 1152 txq_deinit(dev); 1153 1154 return 0; 1155 } 1156 1157 static int pxa168_eth_change_mtu(struct net_device *dev, int mtu) 1158 { 1159 int retval; 1160 struct pxa168_eth_private *pep = netdev_priv(dev); 1161 1162 if ((mtu > 9500) || (mtu < 68)) 1163 return -EINVAL; 1164 1165 dev->mtu = mtu; 1166 retval = set_port_config_ext(pep); 1167 1168 if (!netif_running(dev)) 1169 return 0; 1170 1171 /* 1172 * Stop and then re-open the interface. This will allocate RX 1173 * skbs of the new MTU. 1174 * There is a possible danger that the open will not succeed, 1175 * due to memory being full. 1176 */ 1177 pxa168_eth_stop(dev); 1178 if (pxa168_eth_open(dev)) { 1179 dev_err(&dev->dev, 1180 "fatal error on re-opening device after MTU change\n"); 1181 } 1182 1183 return 0; 1184 } 1185 1186 static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep) 1187 { 1188 int tx_desc_curr; 1189 1190 tx_desc_curr = pep->tx_curr_desc_q; 1191 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size; 1192 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q); 1193 pep->tx_desc_count++; 1194 1195 return tx_desc_curr; 1196 } 1197 1198 static int pxa168_rx_poll(struct napi_struct *napi, int budget) 1199 { 1200 struct pxa168_eth_private *pep = 1201 container_of(napi, struct pxa168_eth_private, napi); 1202 struct net_device *dev = pep->dev; 1203 int work_done = 0; 1204 1205 if (unlikely(pep->work_todo & WORK_LINK)) { 1206 pep->work_todo &= ~(WORK_LINK); 1207 handle_link_event(pep); 1208 } 1209 /* 1210 * We call txq_reclaim every time since in NAPI interupts are disabled 1211 * and due to this we miss the TX_DONE interrupt,which is not updated in 1212 * interrupt status register. 1213 */ 1214 txq_reclaim(dev, 0); 1215 if (netif_queue_stopped(dev) 1216 && pep->tx_ring_size - pep->tx_desc_count > 1) { 1217 netif_wake_queue(dev); 1218 } 1219 work_done = rxq_process(dev, budget); 1220 if (work_done < budget) { 1221 napi_complete(napi); 1222 wrl(pep, INT_MASK, ALL_INTS); 1223 } 1224 1225 return work_done; 1226 } 1227 1228 static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) 1229 { 1230 struct pxa168_eth_private *pep = netdev_priv(dev); 1231 struct net_device_stats *stats = &dev->stats; 1232 struct tx_desc *desc; 1233 int tx_index; 1234 int length; 1235 1236 tx_index = eth_alloc_tx_desc_index(pep); 1237 desc = &pep->p_tx_desc_area[tx_index]; 1238 length = skb->len; 1239 pep->tx_skb[tx_index] = skb; 1240 desc->byte_cnt = length; 1241 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); 1242 1243 skb_tx_timestamp(skb); 1244 1245 wmb(); 1246 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC | 1247 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT; 1248 wmb(); 1249 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD); 1250 1251 stats->tx_bytes += length; 1252 stats->tx_packets++; 1253 dev->trans_start = jiffies; 1254 if (pep->tx_ring_size - pep->tx_desc_count <= 1) { 1255 /* We handled the current skb, but now we are out of space.*/ 1256 netif_stop_queue(dev); 1257 } 1258 1259 return NETDEV_TX_OK; 1260 } 1261 1262 static int smi_wait_ready(struct pxa168_eth_private *pep) 1263 { 1264 int i = 0; 1265 1266 /* wait for the SMI register to become available */ 1267 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) { 1268 if (i == PHY_WAIT_ITERATIONS) 1269 return -ETIMEDOUT; 1270 msleep(10); 1271 } 1272 1273 return 0; 1274 } 1275 1276 static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum) 1277 { 1278 struct pxa168_eth_private *pep = bus->priv; 1279 int i = 0; 1280 int val; 1281 1282 if (smi_wait_ready(pep)) { 1283 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n"); 1284 return -ETIMEDOUT; 1285 } 1286 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R); 1287 /* now wait for the data to be valid */ 1288 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) { 1289 if (i == PHY_WAIT_ITERATIONS) { 1290 printk(KERN_WARNING 1291 "pxa168_eth: SMI bus read not valid\n"); 1292 return -ENODEV; 1293 } 1294 msleep(10); 1295 } 1296 1297 return val & 0xffff; 1298 } 1299 1300 static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum, 1301 u16 value) 1302 { 1303 struct pxa168_eth_private *pep = bus->priv; 1304 1305 if (smi_wait_ready(pep)) { 1306 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n"); 1307 return -ETIMEDOUT; 1308 } 1309 1310 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | 1311 SMI_OP_W | (value & 0xffff)); 1312 1313 if (smi_wait_ready(pep)) { 1314 printk(KERN_ERR "pxa168_eth: SMI bus busy timeout\n"); 1315 return -ETIMEDOUT; 1316 } 1317 1318 return 0; 1319 } 1320 1321 static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, 1322 int cmd) 1323 { 1324 struct pxa168_eth_private *pep = netdev_priv(dev); 1325 if (pep->phy != NULL) 1326 return phy_mii_ioctl(pep->phy, ifr, cmd); 1327 1328 return -EOPNOTSUPP; 1329 } 1330 1331 static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr) 1332 { 1333 struct mii_bus *bus = pep->smi_bus; 1334 struct phy_device *phydev; 1335 int start; 1336 int num; 1337 int i; 1338 1339 if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) { 1340 /* Scan entire range */ 1341 start = ethernet_phy_get(pep); 1342 num = 32; 1343 } else { 1344 /* Use phy addr specific to platform */ 1345 start = phy_addr & 0x1f; 1346 num = 1; 1347 } 1348 phydev = NULL; 1349 for (i = 0; i < num; i++) { 1350 int addr = (start + i) & 0x1f; 1351 if (bus->phy_map[addr] == NULL) 1352 mdiobus_scan(bus, addr); 1353 1354 if (phydev == NULL) { 1355 phydev = bus->phy_map[addr]; 1356 if (phydev != NULL) 1357 ethernet_phy_set_addr(pep, addr); 1358 } 1359 } 1360 1361 return phydev; 1362 } 1363 1364 static void phy_init(struct pxa168_eth_private *pep, int speed, int duplex) 1365 { 1366 struct phy_device *phy = pep->phy; 1367 1368 phy_attach(pep->dev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII); 1369 1370 if (speed == 0) { 1371 phy->autoneg = AUTONEG_ENABLE; 1372 phy->speed = 0; 1373 phy->duplex = 0; 1374 phy->supported &= PHY_BASIC_FEATURES; 1375 phy->advertising = phy->supported | ADVERTISED_Autoneg; 1376 } else { 1377 phy->autoneg = AUTONEG_DISABLE; 1378 phy->advertising = 0; 1379 phy->speed = speed; 1380 phy->duplex = duplex; 1381 } 1382 phy_start_aneg(phy); 1383 } 1384 1385 static int ethernet_phy_setup(struct net_device *dev) 1386 { 1387 struct pxa168_eth_private *pep = netdev_priv(dev); 1388 1389 if (pep->pd->init) 1390 pep->pd->init(); 1391 pep->phy = phy_scan(pep, pep->pd->phy_addr & 0x1f); 1392 if (pep->phy != NULL) 1393 phy_init(pep, pep->pd->speed, pep->pd->duplex); 1394 update_hash_table_mac_address(pep, NULL, dev->dev_addr); 1395 1396 return 0; 1397 } 1398 1399 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1400 { 1401 struct pxa168_eth_private *pep = netdev_priv(dev); 1402 int err; 1403 1404 err = phy_read_status(pep->phy); 1405 if (err == 0) 1406 err = phy_ethtool_gset(pep->phy, cmd); 1407 1408 return err; 1409 } 1410 1411 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1412 { 1413 struct pxa168_eth_private *pep = netdev_priv(dev); 1414 1415 return phy_ethtool_sset(pep->phy, cmd); 1416 } 1417 1418 static void pxa168_get_drvinfo(struct net_device *dev, 1419 struct ethtool_drvinfo *info) 1420 { 1421 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver)); 1422 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 1423 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); 1424 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info)); 1425 } 1426 1427 static const struct ethtool_ops pxa168_ethtool_ops = { 1428 .get_settings = pxa168_get_settings, 1429 .set_settings = pxa168_set_settings, 1430 .get_drvinfo = pxa168_get_drvinfo, 1431 .get_link = ethtool_op_get_link, 1432 .get_ts_info = ethtool_op_get_ts_info, 1433 }; 1434 1435 static const struct net_device_ops pxa168_eth_netdev_ops = { 1436 .ndo_open = pxa168_eth_open, 1437 .ndo_stop = pxa168_eth_stop, 1438 .ndo_start_xmit = pxa168_eth_start_xmit, 1439 .ndo_set_rx_mode = pxa168_eth_set_rx_mode, 1440 .ndo_set_mac_address = pxa168_eth_set_mac_address, 1441 .ndo_validate_addr = eth_validate_addr, 1442 .ndo_do_ioctl = pxa168_eth_do_ioctl, 1443 .ndo_change_mtu = pxa168_eth_change_mtu, 1444 .ndo_tx_timeout = pxa168_eth_tx_timeout, 1445 }; 1446 1447 static int pxa168_eth_probe(struct platform_device *pdev) 1448 { 1449 struct pxa168_eth_private *pep = NULL; 1450 struct net_device *dev = NULL; 1451 struct resource *res; 1452 struct clk *clk; 1453 int err; 1454 1455 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n"); 1456 1457 clk = clk_get(&pdev->dev, "MFUCLK"); 1458 if (IS_ERR(clk)) { 1459 printk(KERN_ERR "%s: Fast Ethernet failed to get clock\n", 1460 DRIVER_NAME); 1461 return -ENODEV; 1462 } 1463 clk_enable(clk); 1464 1465 dev = alloc_etherdev(sizeof(struct pxa168_eth_private)); 1466 if (!dev) { 1467 err = -ENOMEM; 1468 goto err_clk; 1469 } 1470 1471 platform_set_drvdata(pdev, dev); 1472 pep = netdev_priv(dev); 1473 pep->dev = dev; 1474 pep->clk = clk; 1475 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1476 if (res == NULL) { 1477 err = -ENODEV; 1478 goto err_netdev; 1479 } 1480 pep->base = ioremap(res->start, resource_size(res)); 1481 if (pep->base == NULL) { 1482 err = -ENOMEM; 1483 goto err_netdev; 1484 } 1485 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1486 BUG_ON(!res); 1487 dev->irq = res->start; 1488 dev->netdev_ops = &pxa168_eth_netdev_ops; 1489 dev->watchdog_timeo = 2 * HZ; 1490 dev->base_addr = 0; 1491 dev->ethtool_ops = &pxa168_ethtool_ops; 1492 1493 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task); 1494 1495 printk(KERN_INFO "%s:Using random mac address\n", DRIVER_NAME); 1496 eth_hw_addr_random(dev); 1497 1498 pep->pd = dev_get_platdata(&pdev->dev); 1499 pep->rx_ring_size = NUM_RX_DESCS; 1500 if (pep->pd->rx_queue_size) 1501 pep->rx_ring_size = pep->pd->rx_queue_size; 1502 1503 pep->tx_ring_size = NUM_TX_DESCS; 1504 if (pep->pd->tx_queue_size) 1505 pep->tx_ring_size = pep->pd->tx_queue_size; 1506 1507 pep->port_num = pep->pd->port_number; 1508 /* Hardware supports only 3 ports */ 1509 BUG_ON(pep->port_num > 2); 1510 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size); 1511 1512 memset(&pep->timeout, 0, sizeof(struct timer_list)); 1513 init_timer(&pep->timeout); 1514 pep->timeout.function = rxq_refill_timer_wrapper; 1515 pep->timeout.data = (unsigned long)pep; 1516 1517 pep->smi_bus = mdiobus_alloc(); 1518 if (pep->smi_bus == NULL) { 1519 err = -ENOMEM; 1520 goto err_base; 1521 } 1522 pep->smi_bus->priv = pep; 1523 pep->smi_bus->name = "pxa168_eth smi"; 1524 pep->smi_bus->read = pxa168_smi_read; 1525 pep->smi_bus->write = pxa168_smi_write; 1526 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1527 pdev->name, pdev->id); 1528 pep->smi_bus->parent = &pdev->dev; 1529 pep->smi_bus->phy_mask = 0xffffffff; 1530 err = mdiobus_register(pep->smi_bus); 1531 if (err) 1532 goto err_free_mdio; 1533 1534 pxa168_init_hw(pep); 1535 err = ethernet_phy_setup(dev); 1536 if (err) 1537 goto err_mdiobus; 1538 SET_NETDEV_DEV(dev, &pdev->dev); 1539 err = register_netdev(dev); 1540 if (err) 1541 goto err_mdiobus; 1542 return 0; 1543 1544 err_mdiobus: 1545 mdiobus_unregister(pep->smi_bus); 1546 err_free_mdio: 1547 mdiobus_free(pep->smi_bus); 1548 err_base: 1549 iounmap(pep->base); 1550 err_netdev: 1551 free_netdev(dev); 1552 err_clk: 1553 clk_disable(clk); 1554 clk_put(clk); 1555 return err; 1556 } 1557 1558 static int pxa168_eth_remove(struct platform_device *pdev) 1559 { 1560 struct net_device *dev = platform_get_drvdata(pdev); 1561 struct pxa168_eth_private *pep = netdev_priv(dev); 1562 1563 if (pep->htpr) { 1564 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE, 1565 pep->htpr, pep->htpr_dma); 1566 pep->htpr = NULL; 1567 } 1568 if (pep->clk) { 1569 clk_disable(pep->clk); 1570 clk_put(pep->clk); 1571 pep->clk = NULL; 1572 } 1573 if (pep->phy != NULL) 1574 phy_detach(pep->phy); 1575 1576 iounmap(pep->base); 1577 pep->base = NULL; 1578 mdiobus_unregister(pep->smi_bus); 1579 mdiobus_free(pep->smi_bus); 1580 unregister_netdev(dev); 1581 cancel_work_sync(&pep->tx_timeout_task); 1582 free_netdev(dev); 1583 return 0; 1584 } 1585 1586 static void pxa168_eth_shutdown(struct platform_device *pdev) 1587 { 1588 struct net_device *dev = platform_get_drvdata(pdev); 1589 eth_port_reset(dev); 1590 } 1591 1592 #ifdef CONFIG_PM 1593 static int pxa168_eth_resume(struct platform_device *pdev) 1594 { 1595 return -ENOSYS; 1596 } 1597 1598 static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state) 1599 { 1600 return -ENOSYS; 1601 } 1602 1603 #else 1604 #define pxa168_eth_resume NULL 1605 #define pxa168_eth_suspend NULL 1606 #endif 1607 1608 static struct platform_driver pxa168_eth_driver = { 1609 .probe = pxa168_eth_probe, 1610 .remove = pxa168_eth_remove, 1611 .shutdown = pxa168_eth_shutdown, 1612 .resume = pxa168_eth_resume, 1613 .suspend = pxa168_eth_suspend, 1614 .driver = { 1615 .name = DRIVER_NAME, 1616 }, 1617 }; 1618 1619 module_platform_driver(pxa168_eth_driver); 1620 1621 MODULE_LICENSE("GPL"); 1622 MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168"); 1623 MODULE_ALIAS("platform:pxa168_eth"); 1624