xref: /linux/drivers/net/ethernet/marvell/octeontx2/nic/qos.h (revision 9f771739a04919226081a107167596de75108fbb)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
3  *
4  * Copyright (C) 2023 Marvell.
5  *
6  */
7 #ifndef OTX2_QOS_H
8 #define OTX2_QOS_H
9 
10 #include <linux/types.h>
11 #include <linux/netdevice.h>
12 #include <linux/rhashtable.h>
13 
14 #define OTX2_QOS_MAX_LVL		4
15 #define OTX2_QOS_MAX_PRIO		7
16 #define OTX2_QOS_MAX_LEAF_NODES                16
17 
18 enum qos_smq_operations {
19 	QOS_CFG_SQ,
20 	QOS_SMQ_FLUSH,
21 };
22 
23 u64 otx2_get_txschq_rate_regval(struct otx2_nic *nic, u64 maxrate, u32 burst);
24 
25 int otx2_setup_tc_htb(struct net_device *ndev, struct tc_htb_qopt_offload *htb);
26 int otx2_qos_get_qid(struct otx2_nic *pfvf);
27 void otx2_qos_free_qid(struct otx2_nic *pfvf, int qidx);
28 int otx2_qos_enable_sq(struct otx2_nic *pfvf, int qidx);
29 void otx2_qos_disable_sq(struct otx2_nic *pfvf, int qidx);
30 
31 struct otx2_qos_cfg {
32 	u16 schq[NIX_TXSCH_LVL_CNT];
33 	u16 schq_contig[NIX_TXSCH_LVL_CNT];
34 	int static_node_pos[NIX_TXSCH_LVL_CNT];
35 	int dwrr_node_pos[NIX_TXSCH_LVL_CNT];
36 	u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
37 	u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
38 };
39 
40 struct otx2_qos {
41 	DECLARE_HASHTABLE(qos_hlist, order_base_2(OTX2_QOS_MAX_LEAF_NODES));
42 	struct mutex qos_lock; /* child list lock */
43 	u16 qid_to_sqmap[OTX2_QOS_MAX_LEAF_NODES];
44 	struct list_head qos_tree;
45 	DECLARE_BITMAP(qos_sq_bmap, OTX2_QOS_MAX_LEAF_NODES);
46 	u16 maj_id;
47 	u16 defcls;
48 	u8  link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
49 };
50 
51 struct otx2_qos_node {
52 	struct list_head list; /* list management */
53 	struct list_head child_list;
54 	struct list_head child_schq_list;
55 	struct hlist_node hlist;
56 	DECLARE_BITMAP(prio_bmap, OTX2_QOS_MAX_PRIO + 1);
57 	struct otx2_qos_node *parent;	/* parent qos node */
58 	u64 rate; /* htb params */
59 	u64 ceil;
60 	u32 classid;
61 	u32 prio;
62 	u16 schq; /* hw txschq */
63 	u16 qid;
64 	u16 prio_anchor;
65 	u8 level;
66 };
67 
68 
69 #endif
70