1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Virtual Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/net_tstamp.h> 12 13 #include "otx2_common.h" 14 #include "otx2_reg.h" 15 #include "otx2_ptp.h" 16 #include "cn10k.h" 17 18 #define DRV_NAME "rvu_nicvf" 19 #define DRV_STRING "Marvell RVU NIC Virtual Function Driver" 20 21 static const struct pci_device_id otx2_vf_id_table[] = { 22 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) }, 23 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) }, 24 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_SDP_REP) }, 25 { } 26 }; 27 28 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 29 MODULE_DESCRIPTION(DRV_STRING); 30 MODULE_LICENSE("GPL v2"); 31 MODULE_DEVICE_TABLE(pci, otx2_vf_id_table); 32 33 /* RVU VF Interrupt Vector Enumeration */ 34 enum { 35 RVU_VF_INT_VEC_MBOX = 0x0, 36 }; 37 38 static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf, 39 struct mbox_msghdr *msg) 40 { 41 if (msg->id >= MBOX_MSG_MAX) { 42 dev_err(vf->dev, 43 "Mbox msg with unknown ID %d\n", msg->id); 44 return; 45 } 46 47 if (msg->sig != OTX2_MBOX_RSP_SIG) { 48 dev_err(vf->dev, 49 "Mbox msg with wrong signature %x, ID %d\n", 50 msg->sig, msg->id); 51 return; 52 } 53 54 if (msg->rc == MBOX_MSG_INVALID) { 55 dev_err(vf->dev, 56 "PF/AF says the sent msg(s) %d were invalid\n", 57 msg->id); 58 return; 59 } 60 61 switch (msg->id) { 62 case MBOX_MSG_READY: 63 vf->pcifunc = msg->pcifunc; 64 break; 65 case MBOX_MSG_MSIX_OFFSET: 66 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg); 67 break; 68 case MBOX_MSG_NPA_LF_ALLOC: 69 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg); 70 break; 71 case MBOX_MSG_NIX_LF_ALLOC: 72 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg); 73 break; 74 case MBOX_MSG_NIX_BP_ENABLE: 75 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg); 76 break; 77 default: 78 if (msg->rc) 79 dev_err(vf->dev, 80 "Mbox msg response has err %d, ID %d\n", 81 msg->rc, msg->id); 82 } 83 } 84 85 static void otx2vf_vfaf_mbox_handler(struct work_struct *work) 86 { 87 struct otx2_mbox_dev *mdev; 88 struct mbox_hdr *rsp_hdr; 89 struct mbox_msghdr *msg; 90 struct otx2_mbox *mbox; 91 struct mbox *af_mbox; 92 int offset, id; 93 u16 num_msgs; 94 95 af_mbox = container_of(work, struct mbox, mbox_wrk); 96 mbox = &af_mbox->mbox; 97 mdev = &mbox->dev[0]; 98 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 99 num_msgs = rsp_hdr->num_msgs; 100 101 if (num_msgs == 0) 102 return; 103 104 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 105 106 for (id = 0; id < num_msgs; id++) { 107 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 108 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg); 109 offset = mbox->rx_start + msg->next_msgoff; 110 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 111 __otx2_mbox_reset(mbox, 0); 112 mdev->msgs_acked++; 113 } 114 } 115 116 static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf, 117 struct mbox_msghdr *req) 118 { 119 struct msg_rsp *rsp; 120 int err; 121 122 /* Check if valid, if not reply with a invalid msg */ 123 if (req->sig != OTX2_MBOX_REQ_SIG) { 124 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 125 return -ENODEV; 126 } 127 128 switch (req->id) { 129 case MBOX_MSG_CGX_LINK_EVENT: 130 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg( 131 &vf->mbox.mbox_up, 0, 132 sizeof(struct msg_rsp)); 133 if (!rsp) 134 return -ENOMEM; 135 136 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 137 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 138 rsp->hdr.pcifunc = 0; 139 rsp->hdr.rc = 0; 140 err = otx2_mbox_up_handler_cgx_link_event( 141 vf, (struct cgx_link_info_msg *)req, rsp); 142 return err; 143 default: 144 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 145 return -ENODEV; 146 } 147 return 0; 148 } 149 150 static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work) 151 { 152 struct otx2_mbox_dev *mdev; 153 struct mbox_hdr *rsp_hdr; 154 struct mbox_msghdr *msg; 155 struct otx2_mbox *mbox; 156 struct mbox *vf_mbox; 157 struct otx2_nic *vf; 158 int offset, id; 159 u16 num_msgs; 160 161 vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 162 vf = vf_mbox->pfvf; 163 mbox = &vf_mbox->mbox_up; 164 mdev = &mbox->dev[0]; 165 166 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 167 num_msgs = rsp_hdr->num_msgs; 168 169 if (num_msgs == 0) 170 return; 171 172 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 173 174 for (id = 0; id < num_msgs; id++) { 175 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 176 otx2vf_process_mbox_msg_up(vf, msg); 177 offset = mbox->rx_start + msg->next_msgoff; 178 } 179 180 otx2_mbox_msg_send(mbox, 0); 181 } 182 183 static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq) 184 { 185 struct otx2_nic *vf = (struct otx2_nic *)vf_irq; 186 struct otx2_mbox_dev *mdev; 187 struct otx2_mbox *mbox; 188 struct mbox_hdr *hdr; 189 u64 mbox_data; 190 191 /* Clear the IRQ */ 192 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 193 194 mbox_data = otx2_read64(vf, RVU_VF_VFPF_MBOX0); 195 196 /* Read latest mbox data */ 197 smp_rmb(); 198 199 if (mbox_data & MBOX_DOWN_MSG) { 200 mbox_data &= ~MBOX_DOWN_MSG; 201 otx2_write64(vf, RVU_VF_VFPF_MBOX0, mbox_data); 202 203 /* Check for PF => VF response messages */ 204 mbox = &vf->mbox.mbox; 205 mdev = &mbox->dev[0]; 206 otx2_sync_mbox_bbuf(mbox, 0); 207 208 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 209 if (hdr->num_msgs) 210 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk); 211 212 trace_otx2_msg_interrupt(mbox->pdev, "DOWN reply from PF to VF", 213 BIT_ULL(0)); 214 } 215 216 if (mbox_data & MBOX_UP_MSG) { 217 mbox_data &= ~MBOX_UP_MSG; 218 otx2_write64(vf, RVU_VF_VFPF_MBOX0, mbox_data); 219 220 /* Check for PF => VF notification messages */ 221 mbox = &vf->mbox.mbox_up; 222 mdev = &mbox->dev[0]; 223 otx2_sync_mbox_bbuf(mbox, 0); 224 225 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 226 if (hdr->num_msgs) 227 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk); 228 229 trace_otx2_msg_interrupt(mbox->pdev, "UP message from PF to VF", 230 BIT_ULL(0)); 231 } 232 233 return IRQ_HANDLED; 234 } 235 236 static void otx2vf_disable_mbox_intr(struct otx2_nic *vf) 237 { 238 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX); 239 240 /* Disable VF => PF mailbox IRQ */ 241 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0)); 242 free_irq(vector, vf); 243 } 244 245 static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf) 246 { 247 struct otx2_hw *hw = &vf->hw; 248 struct msg_req *req; 249 char *irq_name; 250 int err; 251 252 /* Register mailbox interrupt handler */ 253 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE]; 254 snprintf(irq_name, NAME_SIZE, "RVUVFAF Mbox"); 255 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX), 256 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf); 257 if (err) { 258 dev_err(vf->dev, 259 "RVUPF: IRQ registration failed for VFAF mbox irq\n"); 260 return err; 261 } 262 263 /* Enable mailbox interrupt for msgs coming from PF. 264 * First clear to avoid spurious interrupts, if any. 265 */ 266 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 267 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0)); 268 269 if (!probe_pf) 270 return 0; 271 272 /* Check mailbox communication with PF */ 273 req = otx2_mbox_alloc_msg_ready(&vf->mbox); 274 if (!req) { 275 otx2vf_disable_mbox_intr(vf); 276 return -ENOMEM; 277 } 278 279 err = otx2_sync_mbox_msg(&vf->mbox); 280 if (err) { 281 dev_warn(vf->dev, 282 "AF not responding to mailbox, deferring probe\n"); 283 otx2vf_disable_mbox_intr(vf); 284 return -EPROBE_DEFER; 285 } 286 return 0; 287 } 288 289 static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf) 290 { 291 struct mbox *mbox = &vf->mbox; 292 293 if (vf->mbox_wq) { 294 destroy_workqueue(vf->mbox_wq); 295 vf->mbox_wq = NULL; 296 } 297 298 if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 299 iounmap((void __iomem *)mbox->mbox.hwbase); 300 301 otx2_mbox_destroy(&mbox->mbox); 302 otx2_mbox_destroy(&mbox->mbox_up); 303 } 304 305 static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf) 306 { 307 struct mbox *mbox = &vf->mbox; 308 void __iomem *hwbase; 309 int err; 310 311 mbox->pfvf = vf; 312 vf->mbox_wq = alloc_ordered_workqueue("otx2_vfaf_mailbox", 313 WQ_HIGHPRI | WQ_MEM_RECLAIM); 314 if (!vf->mbox_wq) 315 return -ENOMEM; 316 317 if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) { 318 /* For cn10k platform, VF mailbox region is in its BAR2 319 * register space 320 */ 321 hwbase = vf->reg_base + RVU_VF_MBOX_REGION; 322 } else { 323 /* Mailbox is a reserved memory (in RAM) region shared between 324 * admin function (i.e PF0) and this VF, shouldn't be mapped as 325 * device memory to allow unaligned accesses. 326 */ 327 hwbase = ioremap_wc(pci_resource_start(vf->pdev, 328 PCI_MBOX_BAR_NUM), 329 pci_resource_len(vf->pdev, 330 PCI_MBOX_BAR_NUM)); 331 if (!hwbase) { 332 dev_err(vf->dev, "Unable to map VFAF mailbox region\n"); 333 err = -ENOMEM; 334 goto exit; 335 } 336 } 337 338 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base, 339 MBOX_DIR_VFPF, 1); 340 if (err) 341 goto exit; 342 343 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base, 344 MBOX_DIR_VFPF_UP, 1); 345 if (err) 346 goto exit; 347 348 err = otx2_mbox_bbuf_init(mbox, vf->pdev); 349 if (err) 350 goto exit; 351 352 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler); 353 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler); 354 mutex_init(&mbox->lock); 355 356 return 0; 357 exit: 358 if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 359 iounmap(hwbase); 360 destroy_workqueue(vf->mbox_wq); 361 return err; 362 } 363 364 static int otx2vf_open(struct net_device *netdev) 365 { 366 struct otx2_nic *vf; 367 int err; 368 369 err = otx2_open(netdev); 370 if (err) 371 return err; 372 373 /* LBKs do not receive link events so tell everyone we are up here */ 374 vf = netdev_priv(netdev); 375 if (is_otx2_lbkvf(vf->pdev) || is_otx2_sdp_rep(vf->pdev)) { 376 pr_info("%s NIC Link is UP\n", netdev->name); 377 netif_carrier_on(netdev); 378 netif_tx_start_all_queues(netdev); 379 } 380 381 return 0; 382 } 383 384 static int otx2vf_stop(struct net_device *netdev) 385 { 386 return otx2_stop(netdev); 387 } 388 389 static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev) 390 { 391 struct otx2_nic *vf = netdev_priv(netdev); 392 int qidx = skb_get_queue_mapping(skb); 393 struct otx2_snd_queue *sq; 394 struct netdev_queue *txq; 395 396 sq = &vf->qset.sq[qidx]; 397 txq = netdev_get_tx_queue(netdev, qidx); 398 399 if (!otx2_sq_append_skb(vf, txq, sq, skb, qidx)) { 400 netif_tx_stop_queue(txq); 401 402 /* Check again, incase SQBs got freed up */ 403 smp_mb(); 404 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 405 > sq->sqe_thresh) 406 netif_tx_wake_queue(txq); 407 408 return NETDEV_TX_BUSY; 409 } 410 411 return NETDEV_TX_OK; 412 } 413 414 static void otx2vf_set_rx_mode(struct net_device *netdev) 415 { 416 struct otx2_nic *vf = netdev_priv(netdev); 417 418 queue_work(vf->otx2_wq, &vf->rx_mode_work); 419 } 420 421 static void otx2vf_do_set_rx_mode(struct work_struct *work) 422 { 423 struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work); 424 struct net_device *netdev = vf->netdev; 425 unsigned int flags = netdev->flags; 426 struct nix_rx_mode *req; 427 428 mutex_lock(&vf->mbox.lock); 429 430 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox); 431 if (!req) { 432 mutex_unlock(&vf->mbox.lock); 433 return; 434 } 435 436 req->mode = NIX_RX_MODE_UCAST; 437 438 if (flags & IFF_PROMISC) 439 req->mode |= NIX_RX_MODE_PROMISC; 440 if (flags & (IFF_ALLMULTI | IFF_MULTICAST)) 441 req->mode |= NIX_RX_MODE_ALLMULTI; 442 443 req->mode |= NIX_RX_MODE_USE_MCE; 444 445 otx2_sync_mbox_msg(&vf->mbox); 446 447 mutex_unlock(&vf->mbox.lock); 448 } 449 450 static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu) 451 { 452 bool if_up = netif_running(netdev); 453 int err = 0; 454 455 if (if_up) 456 otx2vf_stop(netdev); 457 458 netdev_info(netdev, "Changing MTU from %d to %d\n", 459 netdev->mtu, new_mtu); 460 WRITE_ONCE(netdev->mtu, new_mtu); 461 462 if (if_up) 463 err = otx2vf_open(netdev); 464 465 return err; 466 } 467 468 static void otx2vf_reset_task(struct work_struct *work) 469 { 470 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task); 471 472 rtnl_lock(); 473 474 if (netif_running(vf->netdev)) { 475 otx2vf_stop(vf->netdev); 476 vf->reset_count++; 477 otx2vf_open(vf->netdev); 478 } 479 480 rtnl_unlock(); 481 } 482 483 static int otx2vf_set_features(struct net_device *netdev, 484 netdev_features_t features) 485 { 486 return otx2_handle_ntuple_tc_features(netdev, features); 487 } 488 489 static const struct net_device_ops otx2vf_netdev_ops = { 490 .ndo_open = otx2vf_open, 491 .ndo_stop = otx2vf_stop, 492 .ndo_start_xmit = otx2vf_xmit, 493 .ndo_select_queue = otx2_select_queue, 494 .ndo_set_rx_mode = otx2vf_set_rx_mode, 495 .ndo_set_mac_address = otx2_set_mac_address, 496 .ndo_change_mtu = otx2vf_change_mtu, 497 .ndo_set_features = otx2vf_set_features, 498 .ndo_get_stats64 = otx2_get_stats64, 499 .ndo_tx_timeout = otx2_tx_timeout, 500 .ndo_eth_ioctl = otx2_ioctl, 501 .ndo_setup_tc = otx2_setup_tc, 502 }; 503 504 static int otx2_vf_wq_init(struct otx2_nic *vf) 505 { 506 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq"); 507 if (!vf->otx2_wq) 508 return -ENOMEM; 509 510 INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode); 511 INIT_WORK(&vf->reset_task, otx2vf_reset_task); 512 return 0; 513 } 514 515 static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf) 516 { 517 struct otx2_hw *hw = &vf->hw; 518 int num_vec, err; 519 520 num_vec = hw->nix_msixoff; 521 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 522 523 otx2vf_disable_mbox_intr(vf); 524 pci_free_irq_vectors(hw->pdev); 525 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 526 if (err < 0) { 527 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n", 528 __func__, num_vec); 529 return err; 530 } 531 532 return otx2vf_register_mbox_intr(vf, false); 533 } 534 535 static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id) 536 { 537 int num_vec = pci_msix_vec_count(pdev); 538 struct device *dev = &pdev->dev; 539 int err, qcount, qos_txqs; 540 struct net_device *netdev; 541 struct otx2_nic *vf; 542 struct otx2_hw *hw; 543 544 err = pcim_enable_device(pdev); 545 if (err) { 546 dev_err(dev, "Failed to enable PCI device\n"); 547 return err; 548 } 549 550 err = pci_request_regions(pdev, DRV_NAME); 551 if (err) { 552 dev_err(dev, "PCI request regions failed 0x%x\n", err); 553 return err; 554 } 555 556 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 557 if (err) { 558 dev_err(dev, "DMA mask config failed, abort\n"); 559 goto err_release_regions; 560 } 561 562 pci_set_master(pdev); 563 564 qcount = num_online_cpus(); 565 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 566 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount + qos_txqs, qcount); 567 if (!netdev) { 568 err = -ENOMEM; 569 goto err_release_regions; 570 } 571 572 pci_set_drvdata(pdev, netdev); 573 SET_NETDEV_DEV(netdev, &pdev->dev); 574 vf = netdev_priv(netdev); 575 vf->netdev = netdev; 576 vf->pdev = pdev; 577 vf->dev = dev; 578 vf->iommu_domain = iommu_get_domain_for_dev(dev); 579 580 vf->flags |= OTX2_FLAG_INTF_DOWN; 581 hw = &vf->hw; 582 hw->pdev = vf->pdev; 583 hw->rx_queues = qcount; 584 hw->tx_queues = qcount; 585 hw->max_queues = qcount; 586 hw->non_qos_queues = qcount; 587 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 588 /* Use CQE of 128 byte descriptor size by default */ 589 hw->xqe_size = 128; 590 591 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 592 GFP_KERNEL); 593 if (!hw->irq_name) { 594 err = -ENOMEM; 595 goto err_free_netdev; 596 } 597 598 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 599 sizeof(cpumask_var_t), GFP_KERNEL); 600 if (!hw->affinity_mask) { 601 err = -ENOMEM; 602 goto err_free_netdev; 603 } 604 605 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 606 if (err < 0) { 607 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 608 __func__, num_vec); 609 goto err_free_netdev; 610 } 611 612 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 613 if (!vf->reg_base) { 614 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 615 err = -ENOMEM; 616 goto err_free_irq_vectors; 617 } 618 619 otx2_setup_dev_hw_settings(vf); 620 /* Init VF <=> PF mailbox stuff */ 621 err = otx2vf_vfaf_mbox_init(vf); 622 if (err) 623 goto err_free_irq_vectors; 624 625 /* Register mailbox interrupt */ 626 err = otx2vf_register_mbox_intr(vf, true); 627 if (err) 628 goto err_mbox_destroy; 629 630 /* Request AF to attach NPA and LIX LFs to this AF */ 631 err = otx2_attach_npa_nix(vf); 632 if (err) 633 goto err_disable_mbox_intr; 634 635 err = otx2vf_realloc_msix_vectors(vf); 636 if (err) 637 goto err_detach_rsrc; 638 639 err = otx2_set_real_num_queues(netdev, qcount, qcount); 640 if (err) 641 goto err_detach_rsrc; 642 643 err = cn10k_lmtst_init(vf); 644 if (err) 645 goto err_detach_rsrc; 646 647 /* Don't check for error. Proceed without ptp */ 648 otx2_ptp_init(vf); 649 650 /* Assign default mac address */ 651 otx2_get_mac_from_af(netdev); 652 653 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 654 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 655 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 656 NETIF_F_GSO_UDP_L4; 657 netdev->features = netdev->hw_features; 658 /* Support TSO on tag interface */ 659 netdev->vlan_features |= netdev->features; 660 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 661 NETIF_F_HW_VLAN_STAG_TX; 662 netdev->features |= netdev->hw_features; 663 664 netdev->hw_features |= NETIF_F_NTUPLE; 665 netdev->hw_features |= NETIF_F_RXALL; 666 netdev->hw_features |= NETIF_F_HW_TC; 667 668 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 669 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 670 671 netdev->netdev_ops = &otx2vf_netdev_ops; 672 673 netdev->min_mtu = OTX2_MIN_MTU; 674 netdev->max_mtu = otx2_get_max_mtu(vf); 675 hw->max_mtu = netdev->max_mtu; 676 677 /* To distinguish, for LBK VFs set netdev name explicitly */ 678 if (is_otx2_lbkvf(vf->pdev)) { 679 int n; 680 681 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK; 682 /* Need to subtract 1 to get proper VF number */ 683 n -= 1; 684 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n); 685 } 686 687 if (is_otx2_sdp_rep(vf->pdev)) { 688 int n; 689 690 n = vf->pcifunc & RVU_PFVF_FUNC_MASK; 691 n -= 1; 692 snprintf(netdev->name, sizeof(netdev->name), "sdp%d-%d", 693 pdev->bus->number, n); 694 } 695 696 err = register_netdev(netdev); 697 if (err) { 698 dev_err(dev, "Failed to register netdevice\n"); 699 goto err_ptp_destroy; 700 } 701 702 err = otx2_vf_wq_init(vf); 703 if (err) 704 goto err_unreg_netdev; 705 706 otx2vf_set_ethtool_ops(netdev); 707 708 err = otx2vf_mcam_flow_init(vf); 709 if (err) 710 goto err_unreg_netdev; 711 712 err = otx2_init_tc(vf); 713 if (err) 714 goto err_unreg_netdev; 715 716 err = otx2_register_dl(vf); 717 if (err) 718 goto err_shutdown_tc; 719 720 #ifdef CONFIG_DCB 721 err = otx2_dcbnl_set_ops(netdev); 722 if (err) 723 goto err_shutdown_tc; 724 #endif 725 otx2_qos_init(vf, qos_txqs); 726 727 return 0; 728 729 err_shutdown_tc: 730 otx2_shutdown_tc(vf); 731 err_unreg_netdev: 732 unregister_netdev(netdev); 733 err_ptp_destroy: 734 otx2_ptp_destroy(vf); 735 err_detach_rsrc: 736 free_percpu(vf->hw.lmt_info); 737 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag)) 738 qmem_free(vf->dev, vf->dync_lmt); 739 otx2_detach_resources(&vf->mbox); 740 err_disable_mbox_intr: 741 otx2vf_disable_mbox_intr(vf); 742 err_mbox_destroy: 743 otx2vf_vfaf_mbox_destroy(vf); 744 err_free_irq_vectors: 745 pci_free_irq_vectors(hw->pdev); 746 err_free_netdev: 747 pci_set_drvdata(pdev, NULL); 748 free_netdev(netdev); 749 err_release_regions: 750 pci_release_regions(pdev); 751 return err; 752 } 753 754 static void otx2vf_remove(struct pci_dev *pdev) 755 { 756 struct net_device *netdev = pci_get_drvdata(pdev); 757 struct otx2_nic *vf; 758 759 if (!netdev) 760 return; 761 762 vf = netdev_priv(netdev); 763 764 /* Disable 802.3x pause frames */ 765 if (vf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 766 (vf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 767 vf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 768 vf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 769 otx2_config_pause_frm(vf); 770 } 771 772 #ifdef CONFIG_DCB 773 /* Disable PFC config */ 774 if (vf->pfc_en) { 775 vf->pfc_en = 0; 776 otx2_config_priority_flow_ctrl(vf); 777 } 778 #endif 779 780 cancel_work_sync(&vf->reset_task); 781 otx2_unregister_dl(vf); 782 unregister_netdev(netdev); 783 if (vf->otx2_wq) 784 destroy_workqueue(vf->otx2_wq); 785 otx2_ptp_destroy(vf); 786 otx2_mcam_flow_del(vf); 787 otx2_shutdown_tc(vf); 788 otx2_shutdown_qos(vf); 789 otx2_detach_resources(&vf->mbox); 790 otx2vf_disable_mbox_intr(vf); 791 free_percpu(vf->hw.lmt_info); 792 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag)) 793 qmem_free(vf->dev, vf->dync_lmt); 794 otx2vf_vfaf_mbox_destroy(vf); 795 pci_free_irq_vectors(vf->pdev); 796 pci_set_drvdata(pdev, NULL); 797 free_netdev(netdev); 798 799 pci_release_regions(pdev); 800 } 801 802 static struct pci_driver otx2vf_driver = { 803 .name = DRV_NAME, 804 .id_table = otx2_vf_id_table, 805 .probe = otx2vf_probe, 806 .remove = otx2vf_remove, 807 .shutdown = otx2vf_remove, 808 }; 809 810 static int __init otx2vf_init_module(void) 811 { 812 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 813 814 return pci_register_driver(&otx2vf_driver); 815 } 816 817 static void __exit otx2vf_cleanup_module(void) 818 { 819 pci_unregister_driver(&otx2vf_driver); 820 } 821 822 module_init(otx2vf_init_module); 823 module_exit(otx2vf_cleanup_module); 824