1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Virtual Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/net_tstamp.h> 12 13 #include "otx2_common.h" 14 #include "otx2_reg.h" 15 #include "otx2_ptp.h" 16 #include "cn10k.h" 17 #include "cn10k_ipsec.h" 18 19 #define DRV_NAME "rvu_nicvf" 20 #define DRV_STRING "Marvell RVU NIC Virtual Function Driver" 21 22 static const struct pci_device_id otx2_vf_id_table[] = { 23 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) }, 24 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) }, 25 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_SDP_REP) }, 26 { } 27 }; 28 29 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 30 MODULE_DESCRIPTION(DRV_STRING); 31 MODULE_LICENSE("GPL v2"); 32 MODULE_DEVICE_TABLE(pci, otx2_vf_id_table); 33 34 /* RVU VF Interrupt Vector Enumeration */ 35 enum { 36 RVU_VF_INT_VEC_MBOX = 0x0, 37 }; 38 39 static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf, 40 struct mbox_msghdr *msg) 41 { 42 if (msg->id >= MBOX_MSG_MAX) { 43 dev_err(vf->dev, 44 "Mbox msg with unknown ID %d\n", msg->id); 45 return; 46 } 47 48 if (msg->sig != OTX2_MBOX_RSP_SIG) { 49 dev_err(vf->dev, 50 "Mbox msg with wrong signature %x, ID %d\n", 51 msg->sig, msg->id); 52 return; 53 } 54 55 if (msg->rc == MBOX_MSG_INVALID) { 56 dev_err(vf->dev, 57 "PF/AF says the sent msg(s) %d were invalid\n", 58 msg->id); 59 return; 60 } 61 62 switch (msg->id) { 63 case MBOX_MSG_READY: 64 vf->pcifunc = msg->pcifunc; 65 break; 66 case MBOX_MSG_MSIX_OFFSET: 67 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg); 68 break; 69 case MBOX_MSG_NPA_LF_ALLOC: 70 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg); 71 break; 72 case MBOX_MSG_NIX_LF_ALLOC: 73 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg); 74 break; 75 case MBOX_MSG_NIX_BP_ENABLE: 76 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg); 77 break; 78 default: 79 if (msg->rc) 80 dev_err(vf->dev, 81 "Mbox msg response has err %d, ID %d\n", 82 msg->rc, msg->id); 83 } 84 } 85 86 static void otx2vf_vfaf_mbox_handler(struct work_struct *work) 87 { 88 struct otx2_mbox_dev *mdev; 89 struct mbox_hdr *rsp_hdr; 90 struct mbox_msghdr *msg; 91 struct otx2_mbox *mbox; 92 struct mbox *af_mbox; 93 int offset, id; 94 u16 num_msgs; 95 96 af_mbox = container_of(work, struct mbox, mbox_wrk); 97 mbox = &af_mbox->mbox; 98 mdev = &mbox->dev[0]; 99 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 100 num_msgs = rsp_hdr->num_msgs; 101 102 if (num_msgs == 0) 103 return; 104 105 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 106 107 for (id = 0; id < num_msgs; id++) { 108 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 109 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg); 110 offset = mbox->rx_start + msg->next_msgoff; 111 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 112 __otx2_mbox_reset(mbox, 0); 113 mdev->msgs_acked++; 114 } 115 } 116 117 static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf, 118 struct mbox_msghdr *req) 119 { 120 struct msg_rsp *rsp; 121 int err; 122 123 /* Check if valid, if not reply with a invalid msg */ 124 if (req->sig != OTX2_MBOX_REQ_SIG) { 125 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 126 return -ENODEV; 127 } 128 129 switch (req->id) { 130 case MBOX_MSG_CGX_LINK_EVENT: 131 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg( 132 &vf->mbox.mbox_up, 0, 133 sizeof(struct msg_rsp)); 134 if (!rsp) 135 return -ENOMEM; 136 137 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 138 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 139 rsp->hdr.pcifunc = req->pcifunc; 140 rsp->hdr.rc = 0; 141 err = otx2_mbox_up_handler_cgx_link_event( 142 vf, (struct cgx_link_info_msg *)req, rsp); 143 return err; 144 default: 145 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 146 return -ENODEV; 147 } 148 return 0; 149 } 150 151 static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work) 152 { 153 struct otx2_mbox_dev *mdev; 154 struct mbox_hdr *rsp_hdr; 155 struct mbox_msghdr *msg; 156 struct otx2_mbox *mbox; 157 struct mbox *vf_mbox; 158 struct otx2_nic *vf; 159 int offset, id; 160 u16 num_msgs; 161 162 vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 163 vf = vf_mbox->pfvf; 164 mbox = &vf_mbox->mbox_up; 165 mdev = &mbox->dev[0]; 166 167 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 168 num_msgs = rsp_hdr->num_msgs; 169 170 if (num_msgs == 0) 171 return; 172 173 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 174 175 for (id = 0; id < num_msgs; id++) { 176 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 177 otx2vf_process_mbox_msg_up(vf, msg); 178 offset = mbox->rx_start + msg->next_msgoff; 179 } 180 181 otx2_mbox_msg_send(mbox, 0); 182 } 183 184 static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq) 185 { 186 struct otx2_nic *vf = (struct otx2_nic *)vf_irq; 187 struct otx2_mbox_dev *mdev; 188 struct otx2_mbox *mbox; 189 struct mbox_hdr *hdr; 190 u64 mbox_data; 191 192 /* Clear the IRQ */ 193 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 194 195 mbox_data = otx2_read64(vf, RVU_VF_VFPF_MBOX0); 196 197 /* Read latest mbox data */ 198 smp_rmb(); 199 200 if (mbox_data & MBOX_DOWN_MSG) { 201 mbox_data &= ~MBOX_DOWN_MSG; 202 otx2_write64(vf, RVU_VF_VFPF_MBOX0, mbox_data); 203 204 /* Check for PF => VF response messages */ 205 mbox = &vf->mbox.mbox; 206 mdev = &mbox->dev[0]; 207 otx2_sync_mbox_bbuf(mbox, 0); 208 209 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 210 if (hdr->num_msgs) 211 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk); 212 213 trace_otx2_msg_interrupt(mbox->pdev, "DOWN reply from PF to VF", 214 BIT_ULL(0)); 215 } 216 217 if (mbox_data & MBOX_UP_MSG) { 218 mbox_data &= ~MBOX_UP_MSG; 219 otx2_write64(vf, RVU_VF_VFPF_MBOX0, mbox_data); 220 221 /* Check for PF => VF notification messages */ 222 mbox = &vf->mbox.mbox_up; 223 mdev = &mbox->dev[0]; 224 otx2_sync_mbox_bbuf(mbox, 0); 225 226 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 227 if (hdr->num_msgs) 228 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk); 229 230 trace_otx2_msg_interrupt(mbox->pdev, "UP message from PF to VF", 231 BIT_ULL(0)); 232 } 233 234 return IRQ_HANDLED; 235 } 236 237 static void otx2vf_disable_mbox_intr(struct otx2_nic *vf) 238 { 239 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX); 240 241 /* Disable VF => PF mailbox IRQ */ 242 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0)); 243 244 if (is_cn20k(vf->pdev)) 245 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0) | BIT_ULL(1)); 246 247 free_irq(vector, vf); 248 } 249 250 static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf) 251 { 252 struct otx2_hw *hw = &vf->hw; 253 struct msg_req *req; 254 char *irq_name; 255 int err; 256 257 /* Register mailbox interrupt handler */ 258 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE]; 259 snprintf(irq_name, NAME_SIZE, "RVUVF%d AFVF Mbox", ((vf->pcifunc & 260 RVU_PFVF_FUNC_MASK) - 1)); 261 262 if (!is_cn20k(vf->pdev)) { 263 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX), 264 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf); 265 } else { 266 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX), 267 vf->hw_ops->vfaf_mbox_intr_handler, 0, irq_name, 268 vf); 269 } 270 271 if (err) { 272 dev_err(vf->dev, 273 "RVUPF: IRQ registration failed for VFAF mbox irq\n"); 274 return err; 275 } 276 277 /* Enable mailbox interrupt for msgs coming from PF. 278 * First clear to avoid spurious interrupts, if any. 279 */ 280 if (!is_cn20k(vf->pdev)) { 281 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 282 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0)); 283 } else { 284 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0) | BIT_ULL(1) | 285 BIT_ULL(2) | BIT_ULL(3)); 286 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0) | 287 BIT_ULL(1) | BIT_ULL(2) | BIT_ULL(3)); 288 } 289 290 if (!probe_pf) 291 return 0; 292 293 /* Check mailbox communication with PF */ 294 req = otx2_mbox_alloc_msg_ready(&vf->mbox); 295 if (!req) { 296 otx2vf_disable_mbox_intr(vf); 297 return -ENOMEM; 298 } 299 300 err = otx2_sync_mbox_msg(&vf->mbox); 301 if (err) { 302 dev_warn(vf->dev, 303 "AF not responding to mailbox, deferring probe\n"); 304 otx2vf_disable_mbox_intr(vf); 305 return -EPROBE_DEFER; 306 } 307 return 0; 308 } 309 310 static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf) 311 { 312 struct mbox *mbox = &vf->mbox; 313 314 if (vf->mbox_wq) { 315 destroy_workqueue(vf->mbox_wq); 316 vf->mbox_wq = NULL; 317 } 318 319 if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 320 iounmap((void __iomem *)mbox->mbox.hwbase); 321 322 otx2_mbox_destroy(&mbox->mbox); 323 otx2_mbox_destroy(&mbox->mbox_up); 324 } 325 326 static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf) 327 { 328 struct mbox *mbox = &vf->mbox; 329 void __iomem *hwbase; 330 int err; 331 332 mbox->pfvf = vf; 333 vf->mbox_wq = alloc_ordered_workqueue("otx2_vfaf_mailbox", 334 WQ_HIGHPRI | WQ_MEM_RECLAIM); 335 if (!vf->mbox_wq) 336 return -ENOMEM; 337 338 /* For cn20k platform, VF mailbox region is in dram aliased from AF 339 * VF MBOX ADDR, MBOX is a separate RVU block. 340 */ 341 if (is_cn20k(vf->pdev)) { 342 hwbase = vf->reg_base + RVU_VF_MBOX_REGION + ((u64)BLKADDR_MBOX << 343 RVU_FUNC_BLKADDR_SHIFT); 344 } else if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) { 345 /* For cn10k platform, VF mailbox region is in its BAR2 346 * register space 347 */ 348 hwbase = vf->reg_base + RVU_VF_MBOX_REGION; 349 } else { 350 /* Mailbox is a reserved memory (in RAM) region shared between 351 * admin function (i.e PF0) and this VF, shouldn't be mapped as 352 * device memory to allow unaligned accesses. 353 */ 354 hwbase = ioremap_wc(pci_resource_start(vf->pdev, 355 PCI_MBOX_BAR_NUM), 356 pci_resource_len(vf->pdev, 357 PCI_MBOX_BAR_NUM)); 358 if (!hwbase) { 359 dev_err(vf->dev, "Unable to map VFAF mailbox region\n"); 360 err = -ENOMEM; 361 goto exit; 362 } 363 } 364 365 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base, 366 MBOX_DIR_VFPF, 1); 367 if (err) 368 goto exit; 369 370 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base, 371 MBOX_DIR_VFPF_UP, 1); 372 if (err) 373 goto exit; 374 375 err = otx2_mbox_bbuf_init(mbox, vf->pdev); 376 if (err) 377 goto exit; 378 379 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler); 380 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler); 381 mutex_init(&mbox->lock); 382 383 return 0; 384 exit: 385 if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 386 iounmap(hwbase); 387 destroy_workqueue(vf->mbox_wq); 388 return err; 389 } 390 391 static int otx2vf_open(struct net_device *netdev) 392 { 393 struct otx2_nic *vf; 394 int err; 395 396 err = otx2_open(netdev); 397 if (err) 398 return err; 399 400 /* LBKs do not receive link events so tell everyone we are up here */ 401 vf = netdev_priv(netdev); 402 if (is_otx2_lbkvf(vf->pdev) || is_otx2_sdp_rep(vf->pdev)) { 403 pr_info("%s NIC Link is UP\n", netdev->name); 404 netif_carrier_on(netdev); 405 netif_tx_start_all_queues(netdev); 406 } 407 408 return 0; 409 } 410 411 static int otx2vf_stop(struct net_device *netdev) 412 { 413 return otx2_stop(netdev); 414 } 415 416 static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev) 417 { 418 struct otx2_nic *vf = netdev_priv(netdev); 419 int qidx = skb_get_queue_mapping(skb); 420 struct otx2_snd_queue *sq; 421 struct netdev_queue *txq; 422 423 sq = &vf->qset.sq[qidx]; 424 txq = netdev_get_tx_queue(netdev, qidx); 425 426 if (!otx2_sq_append_skb(vf, txq, sq, skb, qidx)) { 427 netif_tx_stop_queue(txq); 428 429 /* Check again, incase SQBs got freed up */ 430 smp_mb(); 431 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 432 > sq->sqe_thresh) 433 netif_tx_wake_queue(txq); 434 435 return NETDEV_TX_BUSY; 436 } 437 438 return NETDEV_TX_OK; 439 } 440 441 static void otx2vf_set_rx_mode(struct net_device *netdev) 442 { 443 struct otx2_nic *vf = netdev_priv(netdev); 444 445 queue_work(vf->otx2_wq, &vf->rx_mode_work); 446 } 447 448 static void otx2vf_do_set_rx_mode(struct work_struct *work) 449 { 450 struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work); 451 struct net_device *netdev = vf->netdev; 452 unsigned int flags = netdev->flags; 453 struct nix_rx_mode *req; 454 455 mutex_lock(&vf->mbox.lock); 456 457 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox); 458 if (!req) { 459 mutex_unlock(&vf->mbox.lock); 460 return; 461 } 462 463 req->mode = NIX_RX_MODE_UCAST; 464 465 if (flags & IFF_PROMISC) 466 req->mode |= NIX_RX_MODE_PROMISC; 467 if (flags & (IFF_ALLMULTI | IFF_MULTICAST)) 468 req->mode |= NIX_RX_MODE_ALLMULTI; 469 470 req->mode |= NIX_RX_MODE_USE_MCE; 471 472 otx2_sync_mbox_msg(&vf->mbox); 473 474 mutex_unlock(&vf->mbox.lock); 475 } 476 477 static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu) 478 { 479 bool if_up = netif_running(netdev); 480 int err = 0; 481 482 if (if_up) 483 otx2vf_stop(netdev); 484 485 netdev_info(netdev, "Changing MTU from %d to %d\n", 486 netdev->mtu, new_mtu); 487 WRITE_ONCE(netdev->mtu, new_mtu); 488 489 if (if_up) 490 err = otx2vf_open(netdev); 491 492 return err; 493 } 494 495 static void otx2vf_reset_task(struct work_struct *work) 496 { 497 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task); 498 499 rtnl_lock(); 500 501 if (netif_running(vf->netdev)) { 502 otx2vf_stop(vf->netdev); 503 vf->reset_count++; 504 otx2vf_open(vf->netdev); 505 } 506 507 rtnl_unlock(); 508 } 509 510 static int otx2vf_set_features(struct net_device *netdev, 511 netdev_features_t features) 512 { 513 return otx2_handle_ntuple_tc_features(netdev, features); 514 } 515 516 static const struct net_device_ops otx2vf_netdev_ops = { 517 .ndo_open = otx2vf_open, 518 .ndo_stop = otx2vf_stop, 519 .ndo_start_xmit = otx2vf_xmit, 520 .ndo_select_queue = otx2_select_queue, 521 .ndo_set_rx_mode = otx2vf_set_rx_mode, 522 .ndo_set_mac_address = otx2_set_mac_address, 523 .ndo_change_mtu = otx2vf_change_mtu, 524 .ndo_set_features = otx2vf_set_features, 525 .ndo_get_stats64 = otx2_get_stats64, 526 .ndo_tx_timeout = otx2_tx_timeout, 527 .ndo_eth_ioctl = otx2_ioctl, 528 .ndo_setup_tc = otx2_setup_tc, 529 }; 530 531 static int otx2_vf_wq_init(struct otx2_nic *vf) 532 { 533 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq"); 534 if (!vf->otx2_wq) 535 return -ENOMEM; 536 537 INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode); 538 INIT_WORK(&vf->reset_task, otx2vf_reset_task); 539 return 0; 540 } 541 542 static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf) 543 { 544 struct otx2_hw *hw = &vf->hw; 545 int num_vec, err; 546 547 num_vec = hw->nix_msixoff; 548 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 549 550 otx2vf_disable_mbox_intr(vf); 551 pci_free_irq_vectors(hw->pdev); 552 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 553 if (err < 0) { 554 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n", 555 __func__, num_vec); 556 return err; 557 } 558 559 return otx2vf_register_mbox_intr(vf, false); 560 } 561 562 static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id) 563 { 564 int num_vec = pci_msix_vec_count(pdev); 565 struct device *dev = &pdev->dev; 566 int err, qcount, qos_txqs; 567 struct net_device *netdev; 568 struct otx2_nic *vf; 569 struct otx2_hw *hw; 570 571 err = pcim_enable_device(pdev); 572 if (err) { 573 dev_err(dev, "Failed to enable PCI device\n"); 574 return err; 575 } 576 577 err = pcim_request_all_regions(pdev, DRV_NAME); 578 if (err) { 579 dev_err(dev, "PCI request regions failed 0x%x\n", err); 580 return err; 581 } 582 583 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 584 if (err) { 585 dev_err(dev, "DMA mask config failed, abort\n"); 586 return err; 587 } 588 589 pci_set_master(pdev); 590 591 qcount = num_online_cpus(); 592 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 593 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount + qos_txqs, qcount); 594 if (!netdev) 595 return -ENOMEM; 596 597 pci_set_drvdata(pdev, netdev); 598 SET_NETDEV_DEV(netdev, &pdev->dev); 599 vf = netdev_priv(netdev); 600 vf->netdev = netdev; 601 vf->pdev = pdev; 602 vf->dev = dev; 603 vf->iommu_domain = iommu_get_domain_for_dev(dev); 604 605 vf->flags |= OTX2_FLAG_INTF_DOWN; 606 hw = &vf->hw; 607 hw->pdev = vf->pdev; 608 hw->rx_queues = qcount; 609 hw->tx_queues = qcount; 610 hw->max_queues = qcount; 611 hw->non_qos_queues = qcount; 612 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 613 /* Use CQE of 128 byte descriptor size by default */ 614 hw->xqe_size = 128; 615 616 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 617 GFP_KERNEL); 618 if (!hw->irq_name) { 619 err = -ENOMEM; 620 goto err_free_netdev; 621 } 622 623 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 624 sizeof(cpumask_var_t), GFP_KERNEL); 625 if (!hw->affinity_mask) { 626 err = -ENOMEM; 627 goto err_free_netdev; 628 } 629 630 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 631 if (err < 0) { 632 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 633 __func__, num_vec); 634 goto err_free_netdev; 635 } 636 637 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 638 if (!vf->reg_base) { 639 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 640 err = -ENOMEM; 641 goto err_free_irq_vectors; 642 } 643 644 otx2_setup_dev_hw_settings(vf); 645 646 if (is_cn20k(vf->pdev)) 647 cn20k_init(vf); 648 else 649 otx2_init_hw_ops(vf); 650 651 /* Init VF <=> PF mailbox stuff */ 652 err = otx2vf_vfaf_mbox_init(vf); 653 if (err) 654 goto err_free_irq_vectors; 655 656 /* Register mailbox interrupt */ 657 err = otx2vf_register_mbox_intr(vf, true); 658 if (err) 659 goto err_mbox_destroy; 660 661 /* Request AF to attach NPA and LIX LFs to this AF */ 662 err = otx2_attach_npa_nix(vf); 663 if (err) 664 goto err_disable_mbox_intr; 665 666 err = otx2vf_realloc_msix_vectors(vf); 667 if (err) 668 goto err_detach_rsrc; 669 670 err = otx2_set_real_num_queues(netdev, qcount, qcount); 671 if (err) 672 goto err_detach_rsrc; 673 674 err = cn10k_lmtst_init(vf); 675 if (err) 676 goto err_detach_rsrc; 677 678 /* Don't check for error. Proceed without ptp */ 679 otx2_ptp_init(vf); 680 681 /* Assign default mac address */ 682 otx2_get_mac_from_af(netdev); 683 684 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 685 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 686 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 687 NETIF_F_GSO_UDP_L4; 688 netdev->features = netdev->hw_features; 689 /* Support TSO on tag interface */ 690 netdev->vlan_features |= netdev->features; 691 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 692 NETIF_F_HW_VLAN_STAG_TX; 693 netdev->features |= netdev->hw_features; 694 695 netdev->hw_features |= NETIF_F_NTUPLE; 696 netdev->hw_features |= NETIF_F_RXALL; 697 netdev->hw_features |= NETIF_F_HW_TC; 698 699 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 700 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 701 702 netdev->netdev_ops = &otx2vf_netdev_ops; 703 704 netdev->min_mtu = OTX2_MIN_MTU; 705 netdev->max_mtu = otx2_get_max_mtu(vf); 706 hw->max_mtu = netdev->max_mtu; 707 708 /* To distinguish, for LBK VFs set netdev name explicitly */ 709 if (is_otx2_lbkvf(vf->pdev)) { 710 int n; 711 712 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK; 713 /* Need to subtract 1 to get proper VF number */ 714 n -= 1; 715 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n); 716 } 717 718 if (is_otx2_sdp_rep(vf->pdev)) { 719 int n; 720 721 n = vf->pcifunc & RVU_PFVF_FUNC_MASK; 722 n -= 1; 723 snprintf(netdev->name, sizeof(netdev->name), "sdp%d-%d", 724 pdev->bus->number, n); 725 } 726 727 err = cn10k_ipsec_init(netdev); 728 if (err) 729 goto err_ptp_destroy; 730 731 err = register_netdev(netdev); 732 if (err) { 733 dev_err(dev, "Failed to register netdevice\n"); 734 goto err_ipsec_clean; 735 } 736 737 err = otx2_vf_wq_init(vf); 738 if (err) 739 goto err_unreg_netdev; 740 741 otx2vf_set_ethtool_ops(netdev); 742 743 err = otx2vf_mcam_flow_init(vf); 744 if (err) 745 goto err_unreg_netdev; 746 747 err = otx2_init_tc(vf); 748 if (err) 749 goto err_unreg_netdev; 750 751 err = otx2_register_dl(vf); 752 if (err) 753 goto err_shutdown_tc; 754 755 vf->af_xdp_zc_qidx = bitmap_zalloc(qcount, GFP_KERNEL); 756 if (!vf->af_xdp_zc_qidx) { 757 err = -ENOMEM; 758 goto err_unreg_devlink; 759 } 760 761 #ifdef CONFIG_DCB 762 /* Priority flow control is not supported for LBK and SDP vf(s) */ 763 if (!(is_otx2_lbkvf(vf->pdev) || is_otx2_sdp_rep(vf->pdev))) { 764 err = otx2_dcbnl_set_ops(netdev); 765 if (err) 766 goto err_free_zc_bmap; 767 } 768 #endif 769 otx2_qos_init(vf, qos_txqs); 770 771 return 0; 772 773 #ifdef CONFIG_DCB 774 err_free_zc_bmap: 775 bitmap_free(vf->af_xdp_zc_qidx); 776 #endif 777 err_unreg_devlink: 778 otx2_unregister_dl(vf); 779 err_shutdown_tc: 780 otx2_shutdown_tc(vf); 781 err_unreg_netdev: 782 unregister_netdev(netdev); 783 err_ipsec_clean: 784 cn10k_ipsec_clean(vf); 785 err_ptp_destroy: 786 otx2_ptp_destroy(vf); 787 err_detach_rsrc: 788 free_percpu(vf->hw.lmt_info); 789 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag)) 790 qmem_free(vf->dev, vf->dync_lmt); 791 otx2_detach_resources(&vf->mbox); 792 err_disable_mbox_intr: 793 otx2vf_disable_mbox_intr(vf); 794 err_mbox_destroy: 795 otx2vf_vfaf_mbox_destroy(vf); 796 err_free_irq_vectors: 797 pci_free_irq_vectors(hw->pdev); 798 err_free_netdev: 799 pci_set_drvdata(pdev, NULL); 800 free_netdev(netdev); 801 return err; 802 } 803 804 static void otx2vf_remove(struct pci_dev *pdev) 805 { 806 struct net_device *netdev = pci_get_drvdata(pdev); 807 struct otx2_nic *vf; 808 809 if (!netdev) 810 return; 811 812 vf = netdev_priv(netdev); 813 814 /* Disable 802.3x pause frames */ 815 if (vf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 816 (vf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 817 vf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 818 vf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 819 otx2_config_pause_frm(vf); 820 } 821 822 #ifdef CONFIG_DCB 823 /* Disable PFC config */ 824 if (vf->pfc_en) { 825 vf->pfc_en = 0; 826 otx2_config_priority_flow_ctrl(vf); 827 } 828 #endif 829 830 cancel_work_sync(&vf->reset_task); 831 otx2_unregister_dl(vf); 832 unregister_netdev(netdev); 833 if (vf->otx2_wq) 834 destroy_workqueue(vf->otx2_wq); 835 cn10k_ipsec_clean(vf); 836 otx2_ptp_destroy(vf); 837 otx2_mcam_flow_del(vf); 838 otx2_shutdown_tc(vf); 839 otx2_shutdown_qos(vf); 840 otx2_detach_resources(&vf->mbox); 841 otx2vf_disable_mbox_intr(vf); 842 free_percpu(vf->hw.lmt_info); 843 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag)) 844 qmem_free(vf->dev, vf->dync_lmt); 845 otx2vf_vfaf_mbox_destroy(vf); 846 pci_free_irq_vectors(vf->pdev); 847 pci_set_drvdata(pdev, NULL); 848 free_netdev(netdev); 849 } 850 851 static struct pci_driver otx2vf_driver = { 852 .name = DRV_NAME, 853 .id_table = otx2_vf_id_table, 854 .probe = otx2vf_probe, 855 .remove = otx2vf_remove, 856 .shutdown = otx2vf_remove, 857 }; 858 859 static int __init otx2vf_init_module(void) 860 { 861 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 862 863 return pci_register_driver(&otx2vf_driver); 864 } 865 866 static void __exit otx2vf_cleanup_module(void) 867 { 868 pci_unregister_driver(&otx2vf_driver); 869 } 870 871 module_init(otx2vf_init_module); 872 module_exit(otx2vf_cleanup_module); 873