1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 #include <linux/bitfield.h> 19 #include <net/page_pool/types.h> 20 21 #include "otx2_reg.h" 22 #include "otx2_common.h" 23 #include "otx2_txrx.h" 24 #include "otx2_struct.h" 25 #include "otx2_ptp.h" 26 #include "cn10k.h" 27 #include "qos.h" 28 #include <rvu_trace.h> 29 30 #define DRV_NAME "rvu_nicpf" 31 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 32 33 /* Supported devices */ 34 static const struct pci_device_id otx2_pf_id_table[] = { 35 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 36 { 0, } /* end of table */ 37 }; 38 39 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 40 MODULE_DESCRIPTION(DRV_STRING); 41 MODULE_LICENSE("GPL v2"); 42 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 43 44 static void otx2_vf_link_event_task(struct work_struct *work); 45 46 enum { 47 TYPE_PFAF, 48 TYPE_PFVF, 49 }; 50 51 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 52 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 53 54 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 55 { 56 struct otx2_nic *pf = netdev_priv(netdev); 57 bool if_up = netif_running(netdev); 58 int err = 0; 59 60 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 61 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 62 netdev->mtu); 63 return -EINVAL; 64 } 65 if (if_up) 66 otx2_stop(netdev); 67 68 netdev_info(netdev, "Changing MTU from %d to %d\n", 69 netdev->mtu, new_mtu); 70 WRITE_ONCE(netdev->mtu, new_mtu); 71 72 if (if_up) 73 err = otx2_open(netdev); 74 75 return err; 76 } 77 78 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 79 { 80 int irq, vfs = pf->total_vfs; 81 82 /* Disable VFs ME interrupts */ 83 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 84 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 85 free_irq(irq, pf); 86 87 /* Disable VFs FLR interrupts */ 88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 90 free_irq(irq, pf); 91 92 if (vfs <= 64) 93 return; 94 95 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 96 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 97 free_irq(irq, pf); 98 99 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 100 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 101 free_irq(irq, pf); 102 } 103 104 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 105 { 106 if (!pf->flr_wq) 107 return; 108 destroy_workqueue(pf->flr_wq); 109 pf->flr_wq = NULL; 110 devm_kfree(pf->dev, pf->flr_wrk); 111 } 112 113 static void otx2_flr_handler(struct work_struct *work) 114 { 115 struct flr_work *flrwork = container_of(work, struct flr_work, work); 116 struct otx2_nic *pf = flrwork->pf; 117 struct mbox *mbox = &pf->mbox; 118 struct msg_req *req; 119 int vf, reg = 0; 120 121 vf = flrwork - pf->flr_wrk; 122 123 mutex_lock(&mbox->lock); 124 req = otx2_mbox_alloc_msg_vf_flr(mbox); 125 if (!req) { 126 mutex_unlock(&mbox->lock); 127 return; 128 } 129 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 130 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 131 132 if (!otx2_sync_mbox_msg(&pf->mbox)) { 133 if (vf >= 64) { 134 reg = 1; 135 vf = vf - 64; 136 } 137 /* clear transcation pending bit */ 138 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 139 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 140 } 141 142 mutex_unlock(&mbox->lock); 143 } 144 145 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 146 { 147 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 148 int reg, dev, vf, start_vf, num_reg = 1; 149 u64 intr; 150 151 if (pf->total_vfs > 64) 152 num_reg = 2; 153 154 for (reg = 0; reg < num_reg; reg++) { 155 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 156 if (!intr) 157 continue; 158 start_vf = 64 * reg; 159 for (vf = 0; vf < 64; vf++) { 160 if (!(intr & BIT_ULL(vf))) 161 continue; 162 dev = vf + start_vf; 163 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 164 /* Clear interrupt */ 165 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 166 /* Disable the interrupt */ 167 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 168 BIT_ULL(vf)); 169 } 170 } 171 return IRQ_HANDLED; 172 } 173 174 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 175 { 176 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 177 int vf, reg, num_reg = 1; 178 u64 intr; 179 180 if (pf->total_vfs > 64) 181 num_reg = 2; 182 183 for (reg = 0; reg < num_reg; reg++) { 184 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 185 if (!intr) 186 continue; 187 for (vf = 0; vf < 64; vf++) { 188 if (!(intr & BIT_ULL(vf))) 189 continue; 190 /* clear trpend bit */ 191 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 192 /* clear interrupt */ 193 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 194 } 195 } 196 return IRQ_HANDLED; 197 } 198 199 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 200 { 201 struct otx2_hw *hw = &pf->hw; 202 char *irq_name; 203 int ret; 204 205 /* Register ME interrupt handler*/ 206 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 207 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 208 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 209 otx2_pf_me_intr_handler, 0, irq_name, pf); 210 if (ret) { 211 dev_err(pf->dev, 212 "RVUPF: IRQ registration failed for ME0\n"); 213 } 214 215 /* Register FLR interrupt handler */ 216 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 218 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 219 otx2_pf_flr_intr_handler, 0, irq_name, pf); 220 if (ret) { 221 dev_err(pf->dev, 222 "RVUPF: IRQ registration failed for FLR0\n"); 223 return ret; 224 } 225 226 if (numvfs > 64) { 227 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 228 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 229 rvu_get_pf(pf->pcifunc)); 230 ret = request_irq(pci_irq_vector 231 (pf->pdev, RVU_PF_INT_VEC_VFME1), 232 otx2_pf_me_intr_handler, 0, irq_name, pf); 233 if (ret) { 234 dev_err(pf->dev, 235 "RVUPF: IRQ registration failed for ME1\n"); 236 } 237 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 238 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 239 rvu_get_pf(pf->pcifunc)); 240 ret = request_irq(pci_irq_vector 241 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 242 otx2_pf_flr_intr_handler, 0, irq_name, pf); 243 if (ret) { 244 dev_err(pf->dev, 245 "RVUPF: IRQ registration failed for FLR1\n"); 246 return ret; 247 } 248 } 249 250 /* Enable ME interrupt for all VFs*/ 251 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 252 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 253 254 /* Enable FLR interrupt for all VFs*/ 255 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 256 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 257 258 if (numvfs > 64) { 259 numvfs -= 64; 260 261 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 262 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 263 INTR_MASK(numvfs)); 264 265 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 266 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 267 INTR_MASK(numvfs)); 268 } 269 return 0; 270 } 271 272 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 273 { 274 int vf; 275 276 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI); 277 if (!pf->flr_wq) 278 return -ENOMEM; 279 280 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 281 sizeof(struct flr_work), GFP_KERNEL); 282 if (!pf->flr_wrk) { 283 destroy_workqueue(pf->flr_wq); 284 return -ENOMEM; 285 } 286 287 for (vf = 0; vf < num_vfs; vf++) { 288 pf->flr_wrk[vf].pf = pf; 289 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 290 } 291 292 return 0; 293 } 294 295 static void otx2_queue_vf_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 296 int first, int mdevs, u64 intr) 297 { 298 struct otx2_mbox_dev *mdev; 299 struct otx2_mbox *mbox; 300 struct mbox_hdr *hdr; 301 int i; 302 303 for (i = first; i < mdevs; i++) { 304 /* start from 0 */ 305 if (!(intr & BIT_ULL(i - first))) 306 continue; 307 308 mbox = &mw->mbox; 309 mdev = &mbox->dev[i]; 310 hdr = mdev->mbase + mbox->rx_start; 311 /* The hdr->num_msgs is set to zero immediately in the interrupt 312 * handler to ensure that it holds a correct value next time 313 * when the interrupt handler is called. pf->mw[i].num_msgs 314 * holds the data for use in otx2_pfvf_mbox_handler and 315 * pf->mw[i].up_num_msgs holds the data for use in 316 * otx2_pfvf_mbox_up_handler. 317 */ 318 if (hdr->num_msgs) { 319 mw[i].num_msgs = hdr->num_msgs; 320 hdr->num_msgs = 0; 321 queue_work(mbox_wq, &mw[i].mbox_wrk); 322 } 323 324 mbox = &mw->mbox_up; 325 mdev = &mbox->dev[i]; 326 hdr = mdev->mbase + mbox->rx_start; 327 if (hdr->num_msgs) { 328 mw[i].up_num_msgs = hdr->num_msgs; 329 hdr->num_msgs = 0; 330 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 331 } 332 } 333 } 334 335 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 336 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 337 int devid) 338 { 339 struct otx2_mbox_dev *src_mdev = mdev; 340 int offset; 341 342 /* Msgs are already copied, trigger VF's mbox irq */ 343 smp_wmb(); 344 345 otx2_mbox_wait_for_zero(pfvf_mbox, devid); 346 347 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 348 writeq(MBOX_DOWN_MSG, (void __iomem *)pfvf_mbox->reg_base + offset); 349 350 /* Restore VF's mbox bounce buffer region address */ 351 src_mdev->mbase = bbuf_base; 352 } 353 354 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 355 struct otx2_mbox *src_mbox, 356 int dir, int vf, int num_msgs) 357 { 358 struct otx2_mbox_dev *src_mdev, *dst_mdev; 359 struct mbox_hdr *mbox_hdr; 360 struct mbox_hdr *req_hdr; 361 struct mbox *dst_mbox; 362 int dst_size, err; 363 364 if (dir == MBOX_DIR_PFAF) { 365 /* Set VF's mailbox memory as PF's bounce buffer memory, so 366 * that explicit copying of VF's msgs to PF=>AF mbox region 367 * and AF=>PF responses to VF's mbox region can be avoided. 368 */ 369 src_mdev = &src_mbox->dev[vf]; 370 mbox_hdr = src_mbox->hwbase + 371 src_mbox->rx_start + (vf * MBOX_SIZE); 372 373 dst_mbox = &pf->mbox; 374 dst_size = dst_mbox->mbox.tx_size - 375 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 376 /* Check if msgs fit into destination area and has valid size */ 377 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 378 return -EINVAL; 379 380 dst_mdev = &dst_mbox->mbox.dev[0]; 381 382 mutex_lock(&pf->mbox.lock); 383 dst_mdev->mbase = src_mdev->mbase; 384 dst_mdev->msg_size = mbox_hdr->msg_size; 385 dst_mdev->num_msgs = num_msgs; 386 err = otx2_sync_mbox_msg(dst_mbox); 387 /* Error code -EIO indicate there is a communication failure 388 * to the AF. Rest of the error codes indicate that AF processed 389 * VF messages and set the error codes in response messages 390 * (if any) so simply forward responses to VF. 391 */ 392 if (err == -EIO) { 393 dev_warn(pf->dev, 394 "AF not responding to VF%d messages\n", vf); 395 /* restore PF mbase and exit */ 396 dst_mdev->mbase = pf->mbox.bbuf_base; 397 mutex_unlock(&pf->mbox.lock); 398 return err; 399 } 400 /* At this point, all the VF messages sent to AF are acked 401 * with proper responses and responses are copied to VF 402 * mailbox hence raise interrupt to VF. 403 */ 404 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 405 dst_mbox->mbox.rx_start); 406 req_hdr->num_msgs = num_msgs; 407 408 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 409 pf->mbox.bbuf_base, vf); 410 mutex_unlock(&pf->mbox.lock); 411 } else if (dir == MBOX_DIR_PFVF_UP) { 412 src_mdev = &src_mbox->dev[0]; 413 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 414 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 415 src_mbox->rx_start); 416 req_hdr->num_msgs = num_msgs; 417 418 dst_mbox = &pf->mbox_pfvf[0]; 419 dst_size = dst_mbox->mbox_up.tx_size - 420 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 421 /* Check if msgs fit into destination area */ 422 if (mbox_hdr->msg_size > dst_size) 423 return -EINVAL; 424 425 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 426 dst_mdev->mbase = src_mdev->mbase; 427 dst_mdev->msg_size = mbox_hdr->msg_size; 428 dst_mdev->num_msgs = mbox_hdr->num_msgs; 429 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 430 if (err) { 431 dev_warn(pf->dev, 432 "VF%d is not responding to mailbox\n", vf); 433 return err; 434 } 435 } else if (dir == MBOX_DIR_VFPF_UP) { 436 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 437 src_mbox->rx_start); 438 req_hdr->num_msgs = num_msgs; 439 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 440 &pf->mbox.mbox_up, 441 pf->mbox_pfvf[vf].bbuf_base, 442 0); 443 } 444 445 return 0; 446 } 447 448 static void otx2_pfvf_mbox_handler(struct work_struct *work) 449 { 450 struct mbox_msghdr *msg = NULL; 451 int offset, vf_idx, id, err; 452 struct otx2_mbox_dev *mdev; 453 struct otx2_mbox *mbox; 454 struct mbox *vf_mbox; 455 struct otx2_nic *pf; 456 457 vf_mbox = container_of(work, struct mbox, mbox_wrk); 458 pf = vf_mbox->pfvf; 459 vf_idx = vf_mbox - pf->mbox_pfvf; 460 461 mbox = &pf->mbox_pfvf[0].mbox; 462 mdev = &mbox->dev[vf_idx]; 463 464 offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 465 466 for (id = 0; id < vf_mbox->num_msgs; id++) { 467 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 468 offset); 469 470 if (msg->sig != OTX2_MBOX_REQ_SIG) 471 goto inval_msg; 472 473 /* Set VF's number in each of the msg */ 474 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 475 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 476 offset = msg->next_msgoff; 477 } 478 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 479 vf_mbox->num_msgs); 480 if (err) 481 goto inval_msg; 482 return; 483 484 inval_msg: 485 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 486 otx2_mbox_msg_send(mbox, vf_idx); 487 } 488 489 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 490 { 491 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 492 struct otx2_nic *pf = vf_mbox->pfvf; 493 struct otx2_mbox_dev *mdev; 494 int offset, id, vf_idx = 0; 495 struct mbox_msghdr *msg; 496 struct otx2_mbox *mbox; 497 498 vf_idx = vf_mbox - pf->mbox_pfvf; 499 mbox = &pf->mbox_pfvf[0].mbox_up; 500 mdev = &mbox->dev[vf_idx]; 501 502 offset = mbox->rx_start + ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 503 504 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 505 msg = mdev->mbase + offset; 506 507 if (msg->id >= MBOX_MSG_MAX) { 508 dev_err(pf->dev, 509 "Mbox msg with unknown ID 0x%x\n", msg->id); 510 goto end; 511 } 512 513 if (msg->sig != OTX2_MBOX_RSP_SIG) { 514 dev_err(pf->dev, 515 "Mbox msg with wrong signature %x, ID 0x%x\n", 516 msg->sig, msg->id); 517 goto end; 518 } 519 520 switch (msg->id) { 521 case MBOX_MSG_CGX_LINK_EVENT: 522 break; 523 default: 524 if (msg->rc) 525 dev_err(pf->dev, 526 "Mbox msg response has err %d, ID 0x%x\n", 527 msg->rc, msg->id); 528 break; 529 } 530 531 end: 532 offset = mbox->rx_start + msg->next_msgoff; 533 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 534 __otx2_mbox_reset(mbox, vf_idx); 535 mdev->msgs_acked++; 536 } 537 } 538 539 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 540 { 541 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 542 int vfs = pf->total_vfs; 543 struct mbox *mbox; 544 u64 intr; 545 546 mbox = pf->mbox_pfvf; 547 /* Handle VF interrupts */ 548 if (vfs > 64) { 549 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 550 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 551 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr); 552 if (intr) 553 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 554 vfs = 64; 555 } 556 557 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 558 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 559 560 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr); 561 562 if (intr) 563 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 564 565 return IRQ_HANDLED; 566 } 567 568 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 569 { 570 void __iomem *hwbase; 571 struct mbox *mbox; 572 int err, vf; 573 u64 base; 574 575 if (!numvfs) 576 return -EINVAL; 577 578 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 579 sizeof(struct mbox), GFP_KERNEL); 580 if (!pf->mbox_pfvf) 581 return -ENOMEM; 582 583 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 584 WQ_UNBOUND | WQ_HIGHPRI | 585 WQ_MEM_RECLAIM, 0); 586 if (!pf->mbox_pfvf_wq) 587 return -ENOMEM; 588 589 /* On CN10K platform, PF <-> VF mailbox region follows after 590 * PF <-> AF mailbox region. 591 */ 592 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 593 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 594 MBOX_SIZE; 595 else 596 base = readq((void __iomem *)((u64)pf->reg_base + 597 RVU_PF_VF_BAR4_ADDR)); 598 599 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 600 if (!hwbase) { 601 err = -ENOMEM; 602 goto free_wq; 603 } 604 605 mbox = &pf->mbox_pfvf[0]; 606 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 607 MBOX_DIR_PFVF, numvfs); 608 if (err) 609 goto free_iomem; 610 611 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 612 MBOX_DIR_PFVF_UP, numvfs); 613 if (err) 614 goto free_iomem; 615 616 for (vf = 0; vf < numvfs; vf++) { 617 mbox->pfvf = pf; 618 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 619 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 620 mbox++; 621 } 622 623 return 0; 624 625 free_iomem: 626 if (hwbase) 627 iounmap(hwbase); 628 free_wq: 629 destroy_workqueue(pf->mbox_pfvf_wq); 630 return err; 631 } 632 633 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 634 { 635 struct mbox *mbox = &pf->mbox_pfvf[0]; 636 637 if (!mbox) 638 return; 639 640 if (pf->mbox_pfvf_wq) { 641 destroy_workqueue(pf->mbox_pfvf_wq); 642 pf->mbox_pfvf_wq = NULL; 643 } 644 645 if (mbox->mbox.hwbase) 646 iounmap(mbox->mbox.hwbase); 647 648 otx2_mbox_destroy(&mbox->mbox); 649 } 650 651 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 652 { 653 /* Clear PF <=> VF mailbox IRQ */ 654 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 655 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 656 657 /* Enable PF <=> VF mailbox IRQ */ 658 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 659 if (numvfs > 64) { 660 numvfs -= 64; 661 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 662 INTR_MASK(numvfs)); 663 } 664 } 665 666 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 667 { 668 int vector; 669 670 /* Disable PF <=> VF mailbox IRQ */ 671 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 672 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 673 674 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 675 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 676 free_irq(vector, pf); 677 678 if (numvfs > 64) { 679 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 680 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 681 free_irq(vector, pf); 682 } 683 } 684 685 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 686 { 687 struct otx2_hw *hw = &pf->hw; 688 char *irq_name; 689 int err; 690 691 /* Register MBOX0 interrupt handler */ 692 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 693 if (pf->pcifunc) 694 snprintf(irq_name, NAME_SIZE, 695 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 696 else 697 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 698 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 699 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 700 if (err) { 701 dev_err(pf->dev, 702 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 703 return err; 704 } 705 706 if (numvfs > 64) { 707 /* Register MBOX1 interrupt handler */ 708 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 709 if (pf->pcifunc) 710 snprintf(irq_name, NAME_SIZE, 711 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 712 else 713 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 714 err = request_irq(pci_irq_vector(pf->pdev, 715 RVU_PF_INT_VEC_VFPF_MBOX1), 716 otx2_pfvf_mbox_intr_handler, 717 0, irq_name, pf); 718 if (err) { 719 dev_err(pf->dev, 720 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 721 return err; 722 } 723 } 724 725 otx2_enable_pfvf_mbox_intr(pf, numvfs); 726 727 return 0; 728 } 729 730 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 731 struct mbox_msghdr *msg) 732 { 733 int devid; 734 735 if (msg->id >= MBOX_MSG_MAX) { 736 dev_err(pf->dev, 737 "Mbox msg with unknown ID 0x%x\n", msg->id); 738 return; 739 } 740 741 if (msg->sig != OTX2_MBOX_RSP_SIG) { 742 dev_err(pf->dev, 743 "Mbox msg with wrong signature %x, ID 0x%x\n", 744 msg->sig, msg->id); 745 return; 746 } 747 748 /* message response heading VF */ 749 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 750 if (devid) { 751 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 752 struct delayed_work *dwork; 753 754 switch (msg->id) { 755 case MBOX_MSG_NIX_LF_START_RX: 756 config->intf_down = false; 757 dwork = &config->link_event_work; 758 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 759 break; 760 case MBOX_MSG_NIX_LF_STOP_RX: 761 config->intf_down = true; 762 break; 763 } 764 765 return; 766 } 767 768 switch (msg->id) { 769 case MBOX_MSG_READY: 770 pf->pcifunc = msg->pcifunc; 771 break; 772 case MBOX_MSG_MSIX_OFFSET: 773 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 774 break; 775 case MBOX_MSG_NPA_LF_ALLOC: 776 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 777 break; 778 case MBOX_MSG_NIX_LF_ALLOC: 779 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 780 break; 781 case MBOX_MSG_NIX_BP_ENABLE: 782 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 783 break; 784 case MBOX_MSG_CGX_STATS: 785 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 786 break; 787 case MBOX_MSG_CGX_FEC_STATS: 788 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 789 break; 790 default: 791 if (msg->rc) 792 dev_err(pf->dev, 793 "Mbox msg response has err %d, ID 0x%x\n", 794 msg->rc, msg->id); 795 break; 796 } 797 } 798 799 static void otx2_pfaf_mbox_handler(struct work_struct *work) 800 { 801 struct otx2_mbox_dev *mdev; 802 struct mbox_hdr *rsp_hdr; 803 struct mbox_msghdr *msg; 804 struct otx2_mbox *mbox; 805 struct mbox *af_mbox; 806 struct otx2_nic *pf; 807 int offset, id; 808 u16 num_msgs; 809 810 af_mbox = container_of(work, struct mbox, mbox_wrk); 811 mbox = &af_mbox->mbox; 812 mdev = &mbox->dev[0]; 813 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 814 num_msgs = rsp_hdr->num_msgs; 815 816 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 817 pf = af_mbox->pfvf; 818 819 for (id = 0; id < num_msgs; id++) { 820 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 821 otx2_process_pfaf_mbox_msg(pf, msg); 822 offset = mbox->rx_start + msg->next_msgoff; 823 if (mdev->msgs_acked == (num_msgs - 1)) 824 __otx2_mbox_reset(mbox, 0); 825 mdev->msgs_acked++; 826 } 827 828 } 829 830 static void otx2_handle_link_event(struct otx2_nic *pf) 831 { 832 struct cgx_link_user_info *linfo = &pf->linfo; 833 struct net_device *netdev = pf->netdev; 834 835 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 836 linfo->link_up ? "UP" : "DOWN", linfo->speed, 837 linfo->full_duplex ? "Full" : "Half"); 838 if (linfo->link_up) { 839 netif_carrier_on(netdev); 840 netif_tx_start_all_queues(netdev); 841 } else { 842 netif_tx_stop_all_queues(netdev); 843 netif_carrier_off(netdev); 844 } 845 } 846 847 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 848 struct mcs_intr_info *event, 849 struct msg_rsp *rsp) 850 { 851 cn10k_handle_mcs_event(pf, event); 852 853 return 0; 854 } 855 856 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 857 struct cgx_link_info_msg *msg, 858 struct msg_rsp *rsp) 859 { 860 int i; 861 862 /* Copy the link info sent by AF */ 863 pf->linfo = msg->link_info; 864 865 /* notify VFs about link event */ 866 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 867 struct otx2_vf_config *config = &pf->vf_configs[i]; 868 struct delayed_work *dwork = &config->link_event_work; 869 870 if (config->intf_down) 871 continue; 872 873 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 874 } 875 876 /* interface has not been fully configured yet */ 877 if (pf->flags & OTX2_FLAG_INTF_DOWN) 878 return 0; 879 880 otx2_handle_link_event(pf); 881 return 0; 882 } 883 884 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 885 struct mbox_msghdr *req) 886 { 887 /* Check if valid, if not reply with a invalid msg */ 888 if (req->sig != OTX2_MBOX_REQ_SIG) { 889 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 890 return -ENODEV; 891 } 892 893 switch (req->id) { 894 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 895 case _id: { \ 896 struct _rsp_type *rsp; \ 897 int err; \ 898 \ 899 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 900 &pf->mbox.mbox_up, 0, \ 901 sizeof(struct _rsp_type)); \ 902 if (!rsp) \ 903 return -ENOMEM; \ 904 \ 905 rsp->hdr.id = _id; \ 906 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 907 rsp->hdr.pcifunc = 0; \ 908 rsp->hdr.rc = 0; \ 909 \ 910 err = otx2_mbox_up_handler_ ## _fn_name( \ 911 pf, (struct _req_type *)req, rsp); \ 912 return err; \ 913 } 914 MBOX_UP_CGX_MESSAGES 915 MBOX_UP_MCS_MESSAGES 916 #undef M 917 break; 918 default: 919 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 920 return -ENODEV; 921 } 922 return 0; 923 } 924 925 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 926 { 927 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 928 struct otx2_mbox *mbox = &af_mbox->mbox_up; 929 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 930 struct otx2_nic *pf = af_mbox->pfvf; 931 int offset, id, devid = 0; 932 struct mbox_hdr *rsp_hdr; 933 struct mbox_msghdr *msg; 934 u16 num_msgs; 935 936 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 937 num_msgs = rsp_hdr->num_msgs; 938 939 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 940 941 for (id = 0; id < num_msgs; id++) { 942 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 943 944 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 945 /* Skip processing VF's messages */ 946 if (!devid) 947 otx2_process_mbox_msg_up(pf, msg); 948 offset = mbox->rx_start + msg->next_msgoff; 949 } 950 /* Forward to VF iff VFs are really present */ 951 if (devid && pci_num_vf(pf->pdev)) { 952 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 953 MBOX_DIR_PFVF_UP, devid - 1, 954 num_msgs); 955 return; 956 } 957 958 otx2_mbox_msg_send(mbox, 0); 959 } 960 961 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 962 { 963 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 964 struct mbox *mw = &pf->mbox; 965 struct otx2_mbox_dev *mdev; 966 struct otx2_mbox *mbox; 967 struct mbox_hdr *hdr; 968 u64 mbox_data; 969 970 /* Clear the IRQ */ 971 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 972 973 974 mbox_data = otx2_read64(pf, RVU_PF_PFAF_MBOX0); 975 976 if (mbox_data & MBOX_UP_MSG) { 977 mbox_data &= ~MBOX_UP_MSG; 978 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); 979 980 mbox = &mw->mbox_up; 981 mdev = &mbox->dev[0]; 982 otx2_sync_mbox_bbuf(mbox, 0); 983 984 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 985 if (hdr->num_msgs) 986 queue_work(pf->mbox_wq, &mw->mbox_up_wrk); 987 988 trace_otx2_msg_interrupt(pf->pdev, "UP message from AF to PF", 989 BIT_ULL(0)); 990 } 991 992 if (mbox_data & MBOX_DOWN_MSG) { 993 mbox_data &= ~MBOX_DOWN_MSG; 994 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); 995 996 mbox = &mw->mbox; 997 mdev = &mbox->dev[0]; 998 otx2_sync_mbox_bbuf(mbox, 0); 999 1000 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 1001 if (hdr->num_msgs) 1002 queue_work(pf->mbox_wq, &mw->mbox_wrk); 1003 1004 trace_otx2_msg_interrupt(pf->pdev, "DOWN reply from AF to PF", 1005 BIT_ULL(0)); 1006 } 1007 1008 return IRQ_HANDLED; 1009 } 1010 1011 void otx2_disable_mbox_intr(struct otx2_nic *pf) 1012 { 1013 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 1014 1015 /* Disable AF => PF mailbox IRQ */ 1016 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 1017 free_irq(vector, pf); 1018 } 1019 1020 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 1021 { 1022 struct otx2_hw *hw = &pf->hw; 1023 struct msg_req *req; 1024 char *irq_name; 1025 int err; 1026 1027 /* Register mailbox interrupt handler */ 1028 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1029 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 1030 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1031 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1032 if (err) { 1033 dev_err(pf->dev, 1034 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1035 return err; 1036 } 1037 1038 /* Enable mailbox interrupt for msgs coming from AF. 1039 * First clear to avoid spurious interrupts, if any. 1040 */ 1041 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1042 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1043 1044 if (!probe_af) 1045 return 0; 1046 1047 /* Check mailbox communication with AF */ 1048 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1049 if (!req) { 1050 otx2_disable_mbox_intr(pf); 1051 return -ENOMEM; 1052 } 1053 err = otx2_sync_mbox_msg(&pf->mbox); 1054 if (err) { 1055 dev_warn(pf->dev, 1056 "AF not responding to mailbox, deferring probe\n"); 1057 otx2_disable_mbox_intr(pf); 1058 return -EPROBE_DEFER; 1059 } 1060 1061 return 0; 1062 } 1063 1064 void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1065 { 1066 struct mbox *mbox = &pf->mbox; 1067 1068 if (pf->mbox_wq) { 1069 destroy_workqueue(pf->mbox_wq); 1070 pf->mbox_wq = NULL; 1071 } 1072 1073 if (mbox->mbox.hwbase) 1074 iounmap((void __iomem *)mbox->mbox.hwbase); 1075 1076 otx2_mbox_destroy(&mbox->mbox); 1077 otx2_mbox_destroy(&mbox->mbox_up); 1078 } 1079 1080 int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1081 { 1082 struct mbox *mbox = &pf->mbox; 1083 void __iomem *hwbase; 1084 int err; 1085 1086 mbox->pfvf = pf; 1087 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox", 1088 WQ_HIGHPRI | WQ_MEM_RECLAIM); 1089 if (!pf->mbox_wq) 1090 return -ENOMEM; 1091 1092 /* Mailbox is a reserved memory (in RAM) region shared between 1093 * admin function (i.e AF) and this PF, shouldn't be mapped as 1094 * device memory to allow unaligned accesses. 1095 */ 1096 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1097 MBOX_SIZE); 1098 if (!hwbase) { 1099 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1100 err = -ENOMEM; 1101 goto exit; 1102 } 1103 1104 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1105 MBOX_DIR_PFAF, 1); 1106 if (err) 1107 goto exit; 1108 1109 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1110 MBOX_DIR_PFAF_UP, 1); 1111 if (err) 1112 goto exit; 1113 1114 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1115 if (err) 1116 goto exit; 1117 1118 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1119 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1120 mutex_init(&mbox->lock); 1121 1122 return 0; 1123 exit: 1124 otx2_pfaf_mbox_destroy(pf); 1125 return err; 1126 } 1127 1128 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1129 { 1130 struct msg_req *msg; 1131 int err; 1132 1133 mutex_lock(&pf->mbox.lock); 1134 if (enable) 1135 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1136 else 1137 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1138 1139 if (!msg) { 1140 mutex_unlock(&pf->mbox.lock); 1141 return -ENOMEM; 1142 } 1143 1144 err = otx2_sync_mbox_msg(&pf->mbox); 1145 mutex_unlock(&pf->mbox.lock); 1146 return err; 1147 } 1148 1149 int otx2_reset_mac_stats(struct otx2_nic *pfvf) 1150 { 1151 struct msg_req *req; 1152 int err; 1153 1154 mutex_lock(&pfvf->mbox.lock); 1155 req = otx2_mbox_alloc_msg_cgx_stats_rst(&pfvf->mbox); 1156 if (!req) { 1157 mutex_unlock(&pfvf->mbox.lock); 1158 return -ENOMEM; 1159 } 1160 1161 err = otx2_sync_mbox_msg(&pfvf->mbox); 1162 mutex_unlock(&pfvf->mbox.lock); 1163 return err; 1164 } 1165 1166 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1167 { 1168 struct msg_req *msg; 1169 int err; 1170 1171 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1172 pf->flow_cfg->dmacflt_max_flows)) 1173 netdev_warn(pf->netdev, 1174 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1175 1176 mutex_lock(&pf->mbox.lock); 1177 if (enable) 1178 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1179 else 1180 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1181 1182 if (!msg) { 1183 mutex_unlock(&pf->mbox.lock); 1184 return -ENOMEM; 1185 } 1186 1187 err = otx2_sync_mbox_msg(&pf->mbox); 1188 mutex_unlock(&pf->mbox.lock); 1189 return err; 1190 } 1191 1192 int otx2_set_real_num_queues(struct net_device *netdev, 1193 int tx_queues, int rx_queues) 1194 { 1195 int err; 1196 1197 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1198 if (err) { 1199 netdev_err(netdev, 1200 "Failed to set no of Tx queues: %d\n", tx_queues); 1201 return err; 1202 } 1203 1204 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1205 if (err) 1206 netdev_err(netdev, 1207 "Failed to set no of Rx queues: %d\n", rx_queues); 1208 return err; 1209 } 1210 EXPORT_SYMBOL(otx2_set_real_num_queues); 1211 1212 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = { 1213 "NIX_SQOPERR_OOR", 1214 "NIX_SQOPERR_CTX_FAULT", 1215 "NIX_SQOPERR_CTX_POISON", 1216 "NIX_SQOPERR_DISABLED", 1217 "NIX_SQOPERR_SIZE_ERR", 1218 "NIX_SQOPERR_OFLOW", 1219 "NIX_SQOPERR_SQB_NULL", 1220 "NIX_SQOPERR_SQB_FAULT", 1221 "NIX_SQOPERR_SQE_SZ_ZERO", 1222 }; 1223 1224 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = { 1225 "NIX_MNQERR_SQ_CTX_FAULT", 1226 "NIX_MNQERR_SQ_CTX_POISON", 1227 "NIX_MNQERR_SQB_FAULT", 1228 "NIX_MNQERR_SQB_POISON", 1229 "NIX_MNQERR_TOTAL_ERR", 1230 "NIX_MNQERR_LSO_ERR", 1231 "NIX_MNQERR_CQ_QUERY_ERR", 1232 "NIX_MNQERR_MAX_SQE_SIZE_ERR", 1233 "NIX_MNQERR_MAXLEN_ERR", 1234 "NIX_MNQERR_SQE_SIZEM1_ZERO", 1235 }; 1236 1237 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = { 1238 [NIX_SND_STATUS_GOOD] = "NIX_SND_STATUS_GOOD", 1239 [NIX_SND_STATUS_SQ_CTX_FAULT] = "NIX_SND_STATUS_SQ_CTX_FAULT", 1240 [NIX_SND_STATUS_SQ_CTX_POISON] = "NIX_SND_STATUS_SQ_CTX_POISON", 1241 [NIX_SND_STATUS_SQB_FAULT] = "NIX_SND_STATUS_SQB_FAULT", 1242 [NIX_SND_STATUS_SQB_POISON] = "NIX_SND_STATUS_SQB_POISON", 1243 [NIX_SND_STATUS_HDR_ERR] = "NIX_SND_STATUS_HDR_ERR", 1244 [NIX_SND_STATUS_EXT_ERR] = "NIX_SND_STATUS_EXT_ERR", 1245 [NIX_SND_STATUS_JUMP_FAULT] = "NIX_SND_STATUS_JUMP_FAULT", 1246 [NIX_SND_STATUS_JUMP_POISON] = "NIX_SND_STATUS_JUMP_POISON", 1247 [NIX_SND_STATUS_CRC_ERR] = "NIX_SND_STATUS_CRC_ERR", 1248 [NIX_SND_STATUS_IMM_ERR] = "NIX_SND_STATUS_IMM_ERR", 1249 [NIX_SND_STATUS_SG_ERR] = "NIX_SND_STATUS_SG_ERR", 1250 [NIX_SND_STATUS_MEM_ERR] = "NIX_SND_STATUS_MEM_ERR", 1251 [NIX_SND_STATUS_INVALID_SUBDC] = "NIX_SND_STATUS_INVALID_SUBDC", 1252 [NIX_SND_STATUS_SUBDC_ORDER_ERR] = "NIX_SND_STATUS_SUBDC_ORDER_ERR", 1253 [NIX_SND_STATUS_DATA_FAULT] = "NIX_SND_STATUS_DATA_FAULT", 1254 [NIX_SND_STATUS_DATA_POISON] = "NIX_SND_STATUS_DATA_POISON", 1255 [NIX_SND_STATUS_NPC_DROP_ACTION] = "NIX_SND_STATUS_NPC_DROP_ACTION", 1256 [NIX_SND_STATUS_LOCK_VIOL] = "NIX_SND_STATUS_LOCK_VIOL", 1257 [NIX_SND_STATUS_NPC_UCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_UCAST_CHAN_ERR", 1258 [NIX_SND_STATUS_NPC_MCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_MCAST_CHAN_ERR", 1259 [NIX_SND_STATUS_NPC_MCAST_ABORT] = "NIX_SND_STATUS_NPC_MCAST_ABORT", 1260 [NIX_SND_STATUS_NPC_VTAG_PTR_ERR] = "NIX_SND_STATUS_NPC_VTAG_PTR_ERR", 1261 [NIX_SND_STATUS_NPC_VTAG_SIZE_ERR] = "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR", 1262 [NIX_SND_STATUS_SEND_MEM_FAULT] = "NIX_SND_STATUS_SEND_MEM_FAULT", 1263 [NIX_SND_STATUS_SEND_STATS_ERR] = "NIX_SND_STATUS_SEND_STATS_ERR", 1264 }; 1265 1266 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1267 { 1268 struct otx2_nic *pf = data; 1269 struct otx2_snd_queue *sq; 1270 u64 val, *ptr; 1271 u64 qidx = 0; 1272 1273 /* CQ */ 1274 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1275 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1276 val = otx2_atomic64_add((qidx << 44), ptr); 1277 1278 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1279 (val & NIX_CQERRINT_BITS)); 1280 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1281 continue; 1282 1283 if (val & BIT_ULL(42)) { 1284 netdev_err(pf->netdev, 1285 "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1286 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1287 } else { 1288 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1289 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1290 qidx); 1291 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1292 netdev_err(pf->netdev, 1293 "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1294 qidx); 1295 } 1296 1297 schedule_work(&pf->reset_task); 1298 } 1299 1300 /* SQ */ 1301 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1302 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg; 1303 u8 sq_op_err_code, mnq_err_code, snd_err_code; 1304 1305 sq = &pf->qset.sq[qidx]; 1306 if (!sq->sqb_ptrs) 1307 continue; 1308 1309 /* Below debug registers captures first errors corresponding to 1310 * those registers. We don't have to check against SQ qid as 1311 * these are fatal errors. 1312 */ 1313 1314 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1315 val = otx2_atomic64_add((qidx << 44), ptr); 1316 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1317 (val & NIX_SQINT_BITS)); 1318 1319 if (val & BIT_ULL(42)) { 1320 netdev_err(pf->netdev, 1321 "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1322 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1323 goto done; 1324 } 1325 1326 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG); 1327 if (!(sq_op_err_dbg & BIT(44))) 1328 goto chk_mnq_err_dbg; 1329 1330 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg); 1331 netdev_err(pf->netdev, 1332 "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(0x%llx) err=%s(%#x)\n", 1333 qidx, sq_op_err_dbg, 1334 nix_sqoperr_e_str[sq_op_err_code], 1335 sq_op_err_code); 1336 1337 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44)); 1338 1339 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL) 1340 goto chk_mnq_err_dbg; 1341 1342 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure. 1343 * TODO: But we are in irq context. How to call mbox functions which does sleep 1344 */ 1345 1346 chk_mnq_err_dbg: 1347 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG); 1348 if (!(mnq_err_dbg & BIT(44))) 1349 goto chk_snd_err_dbg; 1350 1351 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg); 1352 netdev_err(pf->netdev, 1353 "SQ%lld: NIX_LF_MNQ_ERR_DBG(0x%llx) err=%s(%#x)\n", 1354 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code], 1355 mnq_err_code); 1356 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44)); 1357 1358 chk_snd_err_dbg: 1359 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG); 1360 if (snd_err_dbg & BIT(44)) { 1361 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg); 1362 netdev_err(pf->netdev, 1363 "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s(%#x)\n", 1364 qidx, snd_err_dbg, 1365 nix_snd_status_e_str[snd_err_code], 1366 snd_err_code); 1367 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44)); 1368 } 1369 1370 done: 1371 /* Print values and reset */ 1372 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1373 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1374 qidx); 1375 1376 schedule_work(&pf->reset_task); 1377 } 1378 1379 return IRQ_HANDLED; 1380 } 1381 1382 irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1383 { 1384 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1385 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1386 int qidx = cq_poll->cint_idx; 1387 1388 /* Disable interrupts. 1389 * 1390 * Completion interrupts behave in a level-triggered interrupt 1391 * fashion, and hence have to be cleared only after it is serviced. 1392 */ 1393 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1394 1395 /* Schedule NAPI */ 1396 pf->napi_events++; 1397 napi_schedule_irqoff(&cq_poll->napi); 1398 1399 return IRQ_HANDLED; 1400 } 1401 1402 void otx2_disable_napi(struct otx2_nic *pf) 1403 { 1404 struct otx2_qset *qset = &pf->qset; 1405 struct otx2_cq_poll *cq_poll; 1406 struct work_struct *work; 1407 int qidx; 1408 1409 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1410 cq_poll = &qset->napi[qidx]; 1411 work = &cq_poll->dim.work; 1412 if (work->func) 1413 cancel_work_sync(work); 1414 napi_disable(&cq_poll->napi); 1415 netif_napi_del(&cq_poll->napi); 1416 } 1417 } 1418 1419 static void otx2_free_cq_res(struct otx2_nic *pf) 1420 { 1421 struct otx2_qset *qset = &pf->qset; 1422 struct otx2_cq_queue *cq; 1423 int qidx; 1424 1425 /* Disable CQs */ 1426 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1427 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1428 cq = &qset->cq[qidx]; 1429 qmem_free(pf->dev, cq->cqe); 1430 } 1431 } 1432 1433 static void otx2_free_sq_res(struct otx2_nic *pf) 1434 { 1435 struct otx2_qset *qset = &pf->qset; 1436 struct otx2_snd_queue *sq; 1437 int qidx; 1438 1439 /* Disable SQs */ 1440 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1441 /* Free SQB pointers */ 1442 otx2_sq_free_sqbs(pf); 1443 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1444 sq = &qset->sq[qidx]; 1445 /* Skip freeing Qos queues if they are not initialized */ 1446 if (!sq->sqe) 1447 continue; 1448 qmem_free(pf->dev, sq->sqe); 1449 qmem_free(pf->dev, sq->tso_hdrs); 1450 kfree(sq->sg); 1451 kfree(sq->sqb_ptrs); 1452 } 1453 } 1454 1455 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1456 { 1457 int frame_size; 1458 int total_size; 1459 int rbuf_size; 1460 1461 if (pf->hw.rbuf_len) 1462 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1463 1464 /* The data transferred by NIX to memory consists of actual packet 1465 * plus additional data which has timestamp and/or EDSA/HIGIG2 1466 * headers if interface is configured in corresponding modes. 1467 * NIX transfers entire data using 6 segments/buffers and writes 1468 * a CQE_RX descriptor with those segment addresses. First segment 1469 * has additional data prepended to packet. Also software omits a 1470 * headroom of 128 bytes in each segment. Hence the total size of 1471 * memory needed to receive a packet with 'mtu' is: 1472 * frame size = mtu + additional data; 1473 * memory = frame_size + headroom * 6; 1474 * each receive buffer size = memory / 6; 1475 */ 1476 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1477 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1478 rbuf_size = total_size / 6; 1479 1480 return ALIGN(rbuf_size, 2048); 1481 } 1482 1483 int otx2_init_hw_resources(struct otx2_nic *pf) 1484 { 1485 struct nix_lf_free_req *free_req; 1486 struct mbox *mbox = &pf->mbox; 1487 struct otx2_hw *hw = &pf->hw; 1488 struct msg_req *req; 1489 int err = 0, lvl; 1490 1491 /* Set required NPA LF's pool counts 1492 * Auras and Pools are used in a 1:1 mapping, 1493 * so, aura count = pool count. 1494 */ 1495 hw->rqpool_cnt = hw->rx_queues; 1496 hw->sqpool_cnt = otx2_get_total_tx_queues(pf); 1497 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1498 1499 /* Maximum hardware supported transmit length */ 1500 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1501 1502 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1503 1504 mutex_lock(&mbox->lock); 1505 /* NPA init */ 1506 err = otx2_config_npa(pf); 1507 if (err) 1508 goto exit; 1509 1510 /* NIX init */ 1511 err = otx2_config_nix(pf); 1512 if (err) 1513 goto err_free_npa_lf; 1514 1515 /* Enable backpressure for CGX mapped PF/VFs */ 1516 if (!is_otx2_lbkvf(pf->pdev)) 1517 otx2_nix_config_bp(pf, true); 1518 1519 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1520 err = otx2_rq_aura_pool_init(pf); 1521 if (err) { 1522 mutex_unlock(&mbox->lock); 1523 goto err_free_nix_lf; 1524 } 1525 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1526 err = otx2_sq_aura_pool_init(pf); 1527 if (err) { 1528 mutex_unlock(&mbox->lock); 1529 goto err_free_rq_ptrs; 1530 } 1531 1532 err = otx2_txsch_alloc(pf); 1533 if (err) { 1534 mutex_unlock(&mbox->lock); 1535 goto err_free_sq_ptrs; 1536 } 1537 1538 #ifdef CONFIG_DCB 1539 if (pf->pfc_en) { 1540 err = otx2_pfc_txschq_alloc(pf); 1541 if (err) { 1542 mutex_unlock(&mbox->lock); 1543 goto err_free_sq_ptrs; 1544 } 1545 } 1546 #endif 1547 1548 err = otx2_config_nix_queues(pf); 1549 if (err) { 1550 mutex_unlock(&mbox->lock); 1551 goto err_free_txsch; 1552 } 1553 1554 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1555 err = otx2_txschq_config(pf, lvl, 0, false); 1556 if (err) { 1557 mutex_unlock(&mbox->lock); 1558 goto err_free_nix_queues; 1559 } 1560 } 1561 1562 #ifdef CONFIG_DCB 1563 if (pf->pfc_en) { 1564 err = otx2_pfc_txschq_config(pf); 1565 if (err) { 1566 mutex_unlock(&mbox->lock); 1567 goto err_free_nix_queues; 1568 } 1569 } 1570 #endif 1571 1572 mutex_unlock(&mbox->lock); 1573 return err; 1574 1575 err_free_nix_queues: 1576 otx2_free_sq_res(pf); 1577 otx2_free_cq_res(pf); 1578 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1579 err_free_txsch: 1580 otx2_txschq_stop(pf); 1581 err_free_sq_ptrs: 1582 otx2_sq_free_sqbs(pf); 1583 err_free_rq_ptrs: 1584 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1585 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1586 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1587 otx2_aura_pool_free(pf); 1588 err_free_nix_lf: 1589 mutex_lock(&mbox->lock); 1590 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1591 if (free_req) { 1592 free_req->flags = NIX_LF_DISABLE_FLOWS; 1593 if (otx2_sync_mbox_msg(mbox)) 1594 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1595 } 1596 err_free_npa_lf: 1597 /* Reset NPA LF */ 1598 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1599 if (req) { 1600 if (otx2_sync_mbox_msg(mbox)) 1601 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1602 } 1603 exit: 1604 mutex_unlock(&mbox->lock); 1605 return err; 1606 } 1607 1608 void otx2_free_hw_resources(struct otx2_nic *pf) 1609 { 1610 struct otx2_qset *qset = &pf->qset; 1611 struct nix_lf_free_req *free_req; 1612 struct mbox *mbox = &pf->mbox; 1613 struct otx2_cq_queue *cq; 1614 struct otx2_pool *pool; 1615 struct msg_req *req; 1616 int pool_id; 1617 int qidx; 1618 1619 /* Ensure all SQE are processed */ 1620 otx2_sqb_flush(pf); 1621 1622 /* Stop transmission */ 1623 otx2_txschq_stop(pf); 1624 1625 #ifdef CONFIG_DCB 1626 if (pf->pfc_en) 1627 otx2_pfc_txschq_stop(pf); 1628 #endif 1629 1630 otx2_clean_qos_queues(pf); 1631 1632 mutex_lock(&mbox->lock); 1633 /* Disable backpressure */ 1634 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1635 otx2_nix_config_bp(pf, false); 1636 mutex_unlock(&mbox->lock); 1637 1638 /* Disable RQs */ 1639 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1640 1641 /*Dequeue all CQEs */ 1642 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1643 cq = &qset->cq[qidx]; 1644 if (cq->cq_type == CQ_RX) 1645 otx2_cleanup_rx_cqes(pf, cq, qidx); 1646 else 1647 otx2_cleanup_tx_cqes(pf, cq); 1648 } 1649 otx2_free_pending_sqe(pf); 1650 1651 otx2_free_sq_res(pf); 1652 1653 /* Free RQ buffer pointers*/ 1654 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1655 1656 for (qidx = 0; qidx < pf->hw.rx_queues; qidx++) { 1657 pool_id = otx2_get_pool_idx(pf, AURA_NIX_RQ, qidx); 1658 pool = &pf->qset.pool[pool_id]; 1659 page_pool_destroy(pool->page_pool); 1660 pool->page_pool = NULL; 1661 } 1662 1663 otx2_free_cq_res(pf); 1664 1665 /* Free all ingress bandwidth profiles allocated */ 1666 cn10k_free_all_ipolicers(pf); 1667 1668 mutex_lock(&mbox->lock); 1669 /* Reset NIX LF */ 1670 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1671 if (free_req) { 1672 free_req->flags = NIX_LF_DISABLE_FLOWS; 1673 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1674 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1675 if (otx2_sync_mbox_msg(mbox)) 1676 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1677 } 1678 mutex_unlock(&mbox->lock); 1679 1680 /* Disable NPA Pool and Aura hw context */ 1681 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1682 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1683 otx2_aura_pool_free(pf); 1684 1685 mutex_lock(&mbox->lock); 1686 /* Reset NPA LF */ 1687 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1688 if (req) { 1689 if (otx2_sync_mbox_msg(mbox)) 1690 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1691 } 1692 mutex_unlock(&mbox->lock); 1693 } 1694 1695 static bool otx2_promisc_use_mce_list(struct otx2_nic *pfvf) 1696 { 1697 int vf; 1698 1699 /* The AF driver will determine whether to allow the VF netdev or not */ 1700 if (is_otx2_vf(pfvf->pcifunc)) 1701 return true; 1702 1703 /* check if there are any trusted VFs associated with the PF netdev */ 1704 for (vf = 0; vf < pci_num_vf(pfvf->pdev); vf++) 1705 if (pfvf->vf_configs[vf].trusted) 1706 return true; 1707 return false; 1708 } 1709 1710 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1711 { 1712 struct net_device *netdev = pf->netdev; 1713 struct nix_rx_mode *req; 1714 bool promisc = false; 1715 1716 if (!(netdev->flags & IFF_UP)) 1717 return; 1718 1719 if ((netdev->flags & IFF_PROMISC) || 1720 (netdev_uc_count(netdev) > pf->flow_cfg->ucast_flt_cnt)) { 1721 promisc = true; 1722 } 1723 1724 /* Write unicast address to mcam entries or del from mcam */ 1725 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1726 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1727 1728 mutex_lock(&pf->mbox.lock); 1729 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1730 if (!req) { 1731 mutex_unlock(&pf->mbox.lock); 1732 return; 1733 } 1734 1735 req->mode = NIX_RX_MODE_UCAST; 1736 1737 if (promisc) 1738 req->mode |= NIX_RX_MODE_PROMISC; 1739 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1740 req->mode |= NIX_RX_MODE_ALLMULTI; 1741 1742 if (otx2_promisc_use_mce_list(pf)) 1743 req->mode |= NIX_RX_MODE_USE_MCE; 1744 1745 otx2_sync_mbox_msg(&pf->mbox); 1746 mutex_unlock(&pf->mbox.lock); 1747 } 1748 1749 static void otx2_set_irq_coalesce(struct otx2_nic *pfvf) 1750 { 1751 int cint; 1752 1753 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++) 1754 otx2_config_irq_coalescing(pfvf, cint); 1755 } 1756 1757 static void otx2_dim_work(struct work_struct *w) 1758 { 1759 struct dim_cq_moder cur_moder; 1760 struct otx2_cq_poll *cq_poll; 1761 struct otx2_nic *pfvf; 1762 struct dim *dim; 1763 1764 dim = container_of(w, struct dim, work); 1765 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1766 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1767 pfvf = (struct otx2_nic *)cq_poll->dev; 1768 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1769 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1770 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1771 NAPI_POLL_WEIGHT : cur_moder.pkts; 1772 otx2_set_irq_coalesce(pfvf); 1773 dim->state = DIM_START_MEASURE; 1774 } 1775 1776 void otx2_free_queue_mem(struct otx2_qset *qset) 1777 { 1778 kfree(qset->sq); 1779 qset->sq = NULL; 1780 kfree(qset->cq); 1781 qset->cq = NULL; 1782 kfree(qset->rq); 1783 qset->rq = NULL; 1784 kfree(qset->napi); 1785 qset->napi = NULL; 1786 } 1787 1788 int otx2_alloc_queue_mem(struct otx2_nic *pf) 1789 { 1790 struct otx2_qset *qset = &pf->qset; 1791 struct otx2_cq_poll *cq_poll; 1792 1793 1794 /* RQ and SQs are mapped to different CQs, 1795 * so find out max CQ IRQs (i.e CINTs) needed. 1796 */ 1797 pf->hw.non_qos_queues = pf->hw.tx_queues + pf->hw.xdp_queues; 1798 pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues, 1799 pf->hw.tc_tx_queues); 1800 1801 pf->qset.cq_cnt = pf->hw.rx_queues + otx2_get_total_tx_queues(pf); 1802 1803 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1804 if (!qset->napi) 1805 return -ENOMEM; 1806 1807 /* CQ size of RQ */ 1808 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1809 /* CQ size of SQ */ 1810 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1811 1812 qset->cq = kcalloc(pf->qset.cq_cnt, 1813 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1814 if (!qset->cq) 1815 goto err_free_mem; 1816 1817 qset->sq = kcalloc(otx2_get_total_tx_queues(pf), 1818 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1819 if (!qset->sq) 1820 goto err_free_mem; 1821 1822 qset->rq = kcalloc(pf->hw.rx_queues, 1823 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1824 if (!qset->rq) 1825 goto err_free_mem; 1826 1827 return 0; 1828 1829 err_free_mem: 1830 otx2_free_queue_mem(qset); 1831 return -ENOMEM; 1832 } 1833 1834 int otx2_open(struct net_device *netdev) 1835 { 1836 struct otx2_nic *pf = netdev_priv(netdev); 1837 struct otx2_cq_poll *cq_poll = NULL; 1838 struct otx2_qset *qset = &pf->qset; 1839 int err = 0, qidx, vec; 1840 char *irq_name; 1841 1842 netif_carrier_off(netdev); 1843 1844 err = otx2_alloc_queue_mem(pf); 1845 if (err) 1846 return err; 1847 1848 err = otx2_init_hw_resources(pf); 1849 if (err) 1850 goto err_free_mem; 1851 1852 /* Register NAPI handler */ 1853 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1854 cq_poll = &qset->napi[qidx]; 1855 cq_poll->cint_idx = qidx; 1856 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1857 * 'cq_ids[0]' points to RQ's CQ and 1858 * 'cq_ids[1]' points to SQ's CQ and 1859 * 'cq_ids[2]' points to XDP's CQ and 1860 */ 1861 cq_poll->cq_ids[CQ_RX] = 1862 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1863 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1864 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1865 if (pf->xdp_prog) 1866 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1867 (qidx + pf->hw.rx_queues + 1868 pf->hw.tx_queues) : 1869 CINT_INVALID_CQ; 1870 else 1871 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1872 1873 cq_poll->cq_ids[CQ_QOS] = (qidx < pf->hw.tc_tx_queues) ? 1874 (qidx + pf->hw.rx_queues + 1875 pf->hw.non_qos_queues) : 1876 CINT_INVALID_CQ; 1877 1878 cq_poll->dev = (void *)pf; 1879 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1880 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1881 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1882 napi_enable(&cq_poll->napi); 1883 } 1884 1885 /* Set maximum frame size allowed in HW */ 1886 err = otx2_hw_set_mtu(pf, netdev->mtu); 1887 if (err) 1888 goto err_disable_napi; 1889 1890 /* Setup segmentation algorithms, if failed, clear offload capability */ 1891 otx2_setup_segmentation(pf); 1892 1893 /* Initialize RSS */ 1894 err = otx2_rss_init(pf); 1895 if (err) 1896 goto err_disable_napi; 1897 1898 /* Register Queue IRQ handlers */ 1899 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1900 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1901 1902 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1903 1904 err = request_irq(pci_irq_vector(pf->pdev, vec), 1905 otx2_q_intr_handler, 0, irq_name, pf); 1906 if (err) { 1907 dev_err(pf->dev, 1908 "RVUPF%d: IRQ registration failed for QERR\n", 1909 rvu_get_pf(pf->pcifunc)); 1910 goto err_disable_napi; 1911 } 1912 1913 /* Enable QINT IRQ */ 1914 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1915 1916 /* Register CQ IRQ handlers */ 1917 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1918 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1919 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1920 int name_len; 1921 1922 name_len = snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", 1923 pf->netdev->name, qidx); 1924 if (name_len >= NAME_SIZE) { 1925 dev_err(pf->dev, 1926 "RVUPF%d: IRQ registration failed for CQ%d, irq name is too long\n", 1927 rvu_get_pf(pf->pcifunc), qidx); 1928 err = -EINVAL; 1929 goto err_free_cints; 1930 } 1931 1932 err = request_irq(pci_irq_vector(pf->pdev, vec), 1933 otx2_cq_intr_handler, 0, irq_name, 1934 &qset->napi[qidx]); 1935 if (err) { 1936 dev_err(pf->dev, 1937 "RVUPF%d: IRQ registration failed for CQ%d\n", 1938 rvu_get_pf(pf->pcifunc), qidx); 1939 goto err_free_cints; 1940 } 1941 vec++; 1942 1943 otx2_config_irq_coalescing(pf, qidx); 1944 1945 /* Enable CQ IRQ */ 1946 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1947 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1948 } 1949 1950 otx2_set_cints_affinity(pf); 1951 1952 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1953 otx2_enable_rxvlan(pf, true); 1954 1955 /* When reinitializing enable time stamping if it is enabled before */ 1956 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1957 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1958 otx2_config_hw_tx_tstamp(pf, true); 1959 } 1960 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1961 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1962 otx2_config_hw_rx_tstamp(pf, true); 1963 } 1964 1965 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1966 /* 'intf_down' may be checked on any cpu */ 1967 smp_wmb(); 1968 1969 /* Enable QoS configuration before starting tx queues */ 1970 otx2_qos_config_txschq(pf); 1971 1972 /* we have already received link status notification */ 1973 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1974 otx2_handle_link_event(pf); 1975 1976 /* Install DMAC Filters */ 1977 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1978 otx2_dmacflt_reinstall_flows(pf); 1979 1980 otx2_tc_apply_ingress_police_rules(pf); 1981 1982 err = otx2_rxtx_enable(pf, true); 1983 /* If a mbox communication error happens at this point then interface 1984 * will end up in a state such that it is in down state but hardware 1985 * mcam entries are enabled to receive the packets. Hence disable the 1986 * packet I/O. 1987 */ 1988 if (err == -EIO) 1989 goto err_disable_rxtx; 1990 else if (err) 1991 goto err_tx_stop_queues; 1992 1993 otx2_do_set_rx_mode(pf); 1994 1995 return 0; 1996 1997 err_disable_rxtx: 1998 otx2_rxtx_enable(pf, false); 1999 err_tx_stop_queues: 2000 netif_tx_stop_all_queues(netdev); 2001 netif_carrier_off(netdev); 2002 pf->flags |= OTX2_FLAG_INTF_DOWN; 2003 err_free_cints: 2004 otx2_free_cints(pf, qidx); 2005 vec = pci_irq_vector(pf->pdev, 2006 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 2007 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 2008 free_irq(vec, pf); 2009 err_disable_napi: 2010 otx2_disable_napi(pf); 2011 otx2_free_hw_resources(pf); 2012 err_free_mem: 2013 otx2_free_queue_mem(qset); 2014 return err; 2015 } 2016 EXPORT_SYMBOL(otx2_open); 2017 2018 int otx2_stop(struct net_device *netdev) 2019 { 2020 struct otx2_nic *pf = netdev_priv(netdev); 2021 struct otx2_cq_poll *cq_poll = NULL; 2022 struct otx2_qset *qset = &pf->qset; 2023 struct otx2_rss_info *rss; 2024 int qidx, vec, wrk; 2025 2026 /* If the DOWN flag is set resources are already freed */ 2027 if (pf->flags & OTX2_FLAG_INTF_DOWN) 2028 return 0; 2029 2030 netif_carrier_off(netdev); 2031 netif_tx_stop_all_queues(netdev); 2032 2033 pf->flags |= OTX2_FLAG_INTF_DOWN; 2034 /* 'intf_down' may be checked on any cpu */ 2035 smp_wmb(); 2036 2037 /* First stop packet Rx/Tx */ 2038 otx2_rxtx_enable(pf, false); 2039 2040 /* Clear RSS enable flag */ 2041 rss = &pf->hw.rss_info; 2042 rss->enable = false; 2043 if (!netif_is_rxfh_configured(netdev)) 2044 kfree(rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 2045 2046 /* Cleanup Queue IRQ */ 2047 vec = pci_irq_vector(pf->pdev, 2048 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 2049 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 2050 free_irq(vec, pf); 2051 2052 /* Cleanup CQ NAPI and IRQ */ 2053 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 2054 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 2055 /* Disable interrupt */ 2056 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 2057 2058 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 2059 2060 cq_poll = &qset->napi[qidx]; 2061 napi_synchronize(&cq_poll->napi); 2062 vec++; 2063 } 2064 2065 netif_tx_disable(netdev); 2066 2067 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 2068 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 2069 devm_kfree(pf->dev, pf->refill_wrk); 2070 2071 otx2_free_hw_resources(pf); 2072 otx2_free_cints(pf, pf->hw.cint_cnt); 2073 otx2_disable_napi(pf); 2074 2075 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 2076 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 2077 2078 otx2_free_queue_mem(qset); 2079 /* Do not clear RQ/SQ ringsize settings */ 2080 memset_startat(qset, 0, sqe_cnt); 2081 return 0; 2082 } 2083 EXPORT_SYMBOL(otx2_stop); 2084 2085 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 2086 { 2087 struct otx2_nic *pf = netdev_priv(netdev); 2088 int qidx = skb_get_queue_mapping(skb); 2089 struct otx2_snd_queue *sq; 2090 struct netdev_queue *txq; 2091 int sq_idx; 2092 2093 /* XDP SQs are not mapped with TXQs 2094 * advance qid to derive correct sq mapped with QOS 2095 */ 2096 sq_idx = (qidx >= pf->hw.tx_queues) ? (qidx + pf->hw.xdp_queues) : qidx; 2097 2098 /* Check for minimum and maximum packet length */ 2099 if (skb->len <= ETH_HLEN || 2100 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 2101 dev_kfree_skb(skb); 2102 return NETDEV_TX_OK; 2103 } 2104 2105 sq = &pf->qset.sq[sq_idx]; 2106 txq = netdev_get_tx_queue(netdev, qidx); 2107 2108 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 2109 netif_tx_stop_queue(txq); 2110 2111 /* Check again, incase SQBs got freed up */ 2112 smp_mb(); 2113 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 2114 > sq->sqe_thresh) 2115 netif_tx_wake_queue(txq); 2116 2117 return NETDEV_TX_BUSY; 2118 } 2119 2120 return NETDEV_TX_OK; 2121 } 2122 2123 static int otx2_qos_select_htb_queue(struct otx2_nic *pf, struct sk_buff *skb, 2124 u16 htb_maj_id) 2125 { 2126 u16 classid; 2127 2128 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id) 2129 classid = TC_H_MIN(skb->priority); 2130 else 2131 classid = READ_ONCE(pf->qos.defcls); 2132 2133 if (!classid) 2134 return 0; 2135 2136 return otx2_get_txq_by_classid(pf, classid); 2137 } 2138 2139 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 2140 struct net_device *sb_dev) 2141 { 2142 struct otx2_nic *pf = netdev_priv(netdev); 2143 bool qos_enabled; 2144 #ifdef CONFIG_DCB 2145 u8 vlan_prio; 2146 #endif 2147 int txq; 2148 2149 qos_enabled = netdev->real_num_tx_queues > pf->hw.tx_queues; 2150 if (unlikely(qos_enabled)) { 2151 /* This smp_load_acquire() pairs with smp_store_release() in 2152 * otx2_qos_root_add() called from htb offload root creation 2153 */ 2154 u16 htb_maj_id = smp_load_acquire(&pf->qos.maj_id); 2155 2156 if (unlikely(htb_maj_id)) { 2157 txq = otx2_qos_select_htb_queue(pf, skb, htb_maj_id); 2158 if (txq > 0) 2159 return txq; 2160 goto process_pfc; 2161 } 2162 } 2163 2164 process_pfc: 2165 #ifdef CONFIG_DCB 2166 if (!skb_vlan_tag_present(skb)) 2167 goto pick_tx; 2168 2169 vlan_prio = skb->vlan_tci >> 13; 2170 if ((vlan_prio > pf->hw.tx_queues - 1) || 2171 !pf->pfc_alloc_status[vlan_prio]) 2172 goto pick_tx; 2173 2174 return vlan_prio; 2175 2176 pick_tx: 2177 #endif 2178 txq = netdev_pick_tx(netdev, skb, NULL); 2179 if (unlikely(qos_enabled)) 2180 return txq % pf->hw.tx_queues; 2181 2182 return txq; 2183 } 2184 EXPORT_SYMBOL(otx2_select_queue); 2185 2186 static netdev_features_t otx2_fix_features(struct net_device *dev, 2187 netdev_features_t features) 2188 { 2189 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2190 features |= NETIF_F_HW_VLAN_STAG_RX; 2191 else 2192 features &= ~NETIF_F_HW_VLAN_STAG_RX; 2193 2194 return features; 2195 } 2196 2197 static void otx2_set_rx_mode(struct net_device *netdev) 2198 { 2199 struct otx2_nic *pf = netdev_priv(netdev); 2200 2201 queue_work(pf->otx2_wq, &pf->rx_mode_work); 2202 } 2203 2204 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 2205 { 2206 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 2207 2208 otx2_do_set_rx_mode(pf); 2209 } 2210 2211 static int otx2_set_features(struct net_device *netdev, 2212 netdev_features_t features) 2213 { 2214 netdev_features_t changed = features ^ netdev->features; 2215 struct otx2_nic *pf = netdev_priv(netdev); 2216 2217 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 2218 return otx2_cgx_config_loopback(pf, 2219 features & NETIF_F_LOOPBACK); 2220 2221 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 2222 return otx2_enable_rxvlan(pf, 2223 features & NETIF_F_HW_VLAN_CTAG_RX); 2224 2225 return otx2_handle_ntuple_tc_features(netdev, features); 2226 } 2227 2228 static void otx2_reset_task(struct work_struct *work) 2229 { 2230 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 2231 2232 if (!netif_running(pf->netdev)) 2233 return; 2234 2235 rtnl_lock(); 2236 otx2_stop(pf->netdev); 2237 pf->reset_count++; 2238 otx2_open(pf->netdev); 2239 netif_trans_update(pf->netdev); 2240 rtnl_unlock(); 2241 } 2242 2243 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 2244 { 2245 struct msg_req *req; 2246 int err; 2247 2248 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 2249 return 0; 2250 2251 mutex_lock(&pfvf->mbox.lock); 2252 if (enable) 2253 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 2254 else 2255 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 2256 if (!req) { 2257 mutex_unlock(&pfvf->mbox.lock); 2258 return -ENOMEM; 2259 } 2260 2261 err = otx2_sync_mbox_msg(&pfvf->mbox); 2262 if (err) { 2263 mutex_unlock(&pfvf->mbox.lock); 2264 return err; 2265 } 2266 2267 mutex_unlock(&pfvf->mbox.lock); 2268 if (enable) 2269 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2270 else 2271 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2272 return 0; 2273 } 2274 2275 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2276 { 2277 struct msg_req *req; 2278 int err; 2279 2280 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2281 return 0; 2282 2283 mutex_lock(&pfvf->mbox.lock); 2284 if (enable) 2285 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2286 else 2287 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2288 if (!req) { 2289 mutex_unlock(&pfvf->mbox.lock); 2290 return -ENOMEM; 2291 } 2292 2293 err = otx2_sync_mbox_msg(&pfvf->mbox); 2294 if (err) { 2295 mutex_unlock(&pfvf->mbox.lock); 2296 return err; 2297 } 2298 2299 mutex_unlock(&pfvf->mbox.lock); 2300 if (enable) 2301 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2302 else 2303 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2304 return 0; 2305 } 2306 2307 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2308 { 2309 struct otx2_nic *pfvf = netdev_priv(netdev); 2310 struct hwtstamp_config config; 2311 2312 if (!pfvf->ptp) 2313 return -ENODEV; 2314 2315 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2316 return -EFAULT; 2317 2318 switch (config.tx_type) { 2319 case HWTSTAMP_TX_OFF: 2320 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2321 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2322 2323 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2324 otx2_config_hw_tx_tstamp(pfvf, false); 2325 break; 2326 case HWTSTAMP_TX_ONESTEP_SYNC: 2327 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2328 return -ERANGE; 2329 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2330 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2331 msecs_to_jiffies(500)); 2332 fallthrough; 2333 case HWTSTAMP_TX_ON: 2334 otx2_config_hw_tx_tstamp(pfvf, true); 2335 break; 2336 default: 2337 return -ERANGE; 2338 } 2339 2340 switch (config.rx_filter) { 2341 case HWTSTAMP_FILTER_NONE: 2342 otx2_config_hw_rx_tstamp(pfvf, false); 2343 break; 2344 case HWTSTAMP_FILTER_ALL: 2345 case HWTSTAMP_FILTER_SOME: 2346 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2347 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2348 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2349 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2350 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2351 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2352 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2353 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2354 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2355 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2356 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2357 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2358 otx2_config_hw_rx_tstamp(pfvf, true); 2359 config.rx_filter = HWTSTAMP_FILTER_ALL; 2360 break; 2361 default: 2362 return -ERANGE; 2363 } 2364 2365 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2366 2367 return copy_to_user(ifr->ifr_data, &config, 2368 sizeof(config)) ? -EFAULT : 0; 2369 } 2370 EXPORT_SYMBOL(otx2_config_hwtstamp); 2371 2372 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2373 { 2374 struct otx2_nic *pfvf = netdev_priv(netdev); 2375 struct hwtstamp_config *cfg = &pfvf->tstamp; 2376 2377 switch (cmd) { 2378 case SIOCSHWTSTAMP: 2379 return otx2_config_hwtstamp(netdev, req); 2380 case SIOCGHWTSTAMP: 2381 return copy_to_user(req->ifr_data, cfg, 2382 sizeof(*cfg)) ? -EFAULT : 0; 2383 default: 2384 return -EOPNOTSUPP; 2385 } 2386 } 2387 EXPORT_SYMBOL(otx2_ioctl); 2388 2389 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2390 { 2391 struct npc_install_flow_req *req; 2392 int err; 2393 2394 mutex_lock(&pf->mbox.lock); 2395 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2396 if (!req) { 2397 err = -ENOMEM; 2398 goto out; 2399 } 2400 2401 ether_addr_copy(req->packet.dmac, mac); 2402 eth_broadcast_addr((u8 *)&req->mask.dmac); 2403 req->features = BIT_ULL(NPC_DMAC); 2404 req->channel = pf->hw.rx_chan_base; 2405 req->intf = NIX_INTF_RX; 2406 req->default_rule = 1; 2407 req->append = 1; 2408 req->vf = vf + 1; 2409 req->op = NIX_RX_ACTION_DEFAULT; 2410 2411 err = otx2_sync_mbox_msg(&pf->mbox); 2412 out: 2413 mutex_unlock(&pf->mbox.lock); 2414 return err; 2415 } 2416 2417 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2418 { 2419 struct otx2_nic *pf = netdev_priv(netdev); 2420 struct pci_dev *pdev = pf->pdev; 2421 struct otx2_vf_config *config; 2422 int ret; 2423 2424 if (!netif_running(netdev)) 2425 return -EAGAIN; 2426 2427 if (vf >= pf->total_vfs) 2428 return -EINVAL; 2429 2430 if (!is_valid_ether_addr(mac)) 2431 return -EINVAL; 2432 2433 config = &pf->vf_configs[vf]; 2434 ether_addr_copy(config->mac, mac); 2435 2436 ret = otx2_do_set_vf_mac(pf, vf, mac); 2437 if (ret == 0) 2438 dev_info(&pdev->dev, 2439 "Load/Reload VF driver\n"); 2440 2441 return ret; 2442 } 2443 2444 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2445 __be16 proto) 2446 { 2447 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2448 struct nix_vtag_config_rsp *vtag_rsp; 2449 struct npc_delete_flow_req *del_req; 2450 struct nix_vtag_config *vtag_req; 2451 struct npc_install_flow_req *req; 2452 struct otx2_vf_config *config; 2453 int err = 0; 2454 u32 idx; 2455 2456 config = &pf->vf_configs[vf]; 2457 2458 if (!vlan && !config->vlan) 2459 goto out; 2460 2461 mutex_lock(&pf->mbox.lock); 2462 2463 /* free old tx vtag entry */ 2464 if (config->vlan) { 2465 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2466 if (!vtag_req) { 2467 err = -ENOMEM; 2468 goto out; 2469 } 2470 vtag_req->cfg_type = 0; 2471 vtag_req->tx.free_vtag0 = 1; 2472 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2473 2474 err = otx2_sync_mbox_msg(&pf->mbox); 2475 if (err) 2476 goto out; 2477 } 2478 2479 if (!vlan && config->vlan) { 2480 /* rx */ 2481 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2482 if (!del_req) { 2483 err = -ENOMEM; 2484 goto out; 2485 } 2486 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2487 del_req->entry = 2488 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2489 err = otx2_sync_mbox_msg(&pf->mbox); 2490 if (err) 2491 goto out; 2492 2493 /* tx */ 2494 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2495 if (!del_req) { 2496 err = -ENOMEM; 2497 goto out; 2498 } 2499 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2500 del_req->entry = 2501 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2502 err = otx2_sync_mbox_msg(&pf->mbox); 2503 2504 goto out; 2505 } 2506 2507 /* rx */ 2508 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2509 if (!req) { 2510 err = -ENOMEM; 2511 goto out; 2512 } 2513 2514 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2515 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2516 req->packet.vlan_tci = htons(vlan); 2517 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2518 /* af fills the destination mac addr */ 2519 eth_broadcast_addr((u8 *)&req->mask.dmac); 2520 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2521 req->channel = pf->hw.rx_chan_base; 2522 req->intf = NIX_INTF_RX; 2523 req->vf = vf + 1; 2524 req->op = NIX_RX_ACTION_DEFAULT; 2525 req->vtag0_valid = true; 2526 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2527 req->set_cntr = 1; 2528 2529 err = otx2_sync_mbox_msg(&pf->mbox); 2530 if (err) 2531 goto out; 2532 2533 /* tx */ 2534 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2535 if (!vtag_req) { 2536 err = -ENOMEM; 2537 goto out; 2538 } 2539 2540 /* configure tx vtag params */ 2541 vtag_req->vtag_size = VTAGSIZE_T4; 2542 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2543 vtag_req->tx.cfg_vtag0 = 1; 2544 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2545 2546 err = otx2_sync_mbox_msg(&pf->mbox); 2547 if (err) 2548 goto out; 2549 2550 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2551 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2552 if (IS_ERR(vtag_rsp)) { 2553 err = PTR_ERR(vtag_rsp); 2554 goto out; 2555 } 2556 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2557 2558 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2559 if (!req) { 2560 err = -ENOMEM; 2561 goto out; 2562 } 2563 2564 eth_zero_addr((u8 *)&req->mask.dmac); 2565 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2566 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2567 req->features = BIT_ULL(NPC_DMAC); 2568 req->channel = pf->hw.tx_chan_base; 2569 req->intf = NIX_INTF_TX; 2570 req->vf = vf + 1; 2571 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2572 req->vtag0_def = vtag_rsp->vtag0_idx; 2573 req->vtag0_op = VTAG_INSERT; 2574 req->set_cntr = 1; 2575 2576 err = otx2_sync_mbox_msg(&pf->mbox); 2577 out: 2578 config->vlan = vlan; 2579 mutex_unlock(&pf->mbox.lock); 2580 return err; 2581 } 2582 2583 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2584 __be16 proto) 2585 { 2586 struct otx2_nic *pf = netdev_priv(netdev); 2587 struct pci_dev *pdev = pf->pdev; 2588 2589 if (!netif_running(netdev)) 2590 return -EAGAIN; 2591 2592 if (vf >= pci_num_vf(pdev)) 2593 return -EINVAL; 2594 2595 /* qos is currently unsupported */ 2596 if (vlan >= VLAN_N_VID || qos) 2597 return -EINVAL; 2598 2599 if (proto != htons(ETH_P_8021Q)) 2600 return -EPROTONOSUPPORT; 2601 2602 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2603 return -EOPNOTSUPP; 2604 2605 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2606 } 2607 2608 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2609 struct ifla_vf_info *ivi) 2610 { 2611 struct otx2_nic *pf = netdev_priv(netdev); 2612 struct pci_dev *pdev = pf->pdev; 2613 struct otx2_vf_config *config; 2614 2615 if (!netif_running(netdev)) 2616 return -EAGAIN; 2617 2618 if (vf >= pci_num_vf(pdev)) 2619 return -EINVAL; 2620 2621 config = &pf->vf_configs[vf]; 2622 ivi->vf = vf; 2623 ether_addr_copy(ivi->mac, config->mac); 2624 ivi->vlan = config->vlan; 2625 ivi->trusted = config->trusted; 2626 2627 return 0; 2628 } 2629 2630 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2631 int qidx) 2632 { 2633 struct page *page; 2634 u64 dma_addr; 2635 int err = 0; 2636 2637 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2638 offset_in_page(xdpf->data), xdpf->len, 2639 DMA_TO_DEVICE); 2640 if (dma_mapping_error(pf->dev, dma_addr)) 2641 return -ENOMEM; 2642 2643 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2644 if (!err) { 2645 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2646 page = virt_to_page(xdpf->data); 2647 put_page(page); 2648 return -ENOMEM; 2649 } 2650 return 0; 2651 } 2652 2653 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2654 struct xdp_frame **frames, u32 flags) 2655 { 2656 struct otx2_nic *pf = netdev_priv(netdev); 2657 int qidx = smp_processor_id(); 2658 struct otx2_snd_queue *sq; 2659 int drops = 0, i; 2660 2661 if (!netif_running(netdev)) 2662 return -ENETDOWN; 2663 2664 qidx += pf->hw.tx_queues; 2665 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2666 2667 /* Abort xmit if xdp queue is not */ 2668 if (unlikely(!sq)) 2669 return -ENXIO; 2670 2671 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2672 return -EINVAL; 2673 2674 for (i = 0; i < n; i++) { 2675 struct xdp_frame *xdpf = frames[i]; 2676 int err; 2677 2678 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2679 if (err) 2680 drops++; 2681 } 2682 return n - drops; 2683 } 2684 2685 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2686 { 2687 struct net_device *dev = pf->netdev; 2688 bool if_up = netif_running(pf->netdev); 2689 struct bpf_prog *old_prog; 2690 2691 if (prog && dev->mtu > MAX_XDP_MTU) { 2692 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2693 return -EOPNOTSUPP; 2694 } 2695 2696 if (if_up) 2697 otx2_stop(pf->netdev); 2698 2699 old_prog = xchg(&pf->xdp_prog, prog); 2700 2701 if (old_prog) 2702 bpf_prog_put(old_prog); 2703 2704 if (pf->xdp_prog) 2705 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2706 2707 /* Network stack and XDP shared same rx queues. 2708 * Use separate tx queues for XDP and network stack. 2709 */ 2710 if (pf->xdp_prog) { 2711 pf->hw.xdp_queues = pf->hw.rx_queues; 2712 xdp_features_set_redirect_target(dev, false); 2713 } else { 2714 pf->hw.xdp_queues = 0; 2715 xdp_features_clear_redirect_target(dev); 2716 } 2717 2718 if (if_up) 2719 otx2_open(pf->netdev); 2720 2721 return 0; 2722 } 2723 2724 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2725 { 2726 struct otx2_nic *pf = netdev_priv(netdev); 2727 2728 switch (xdp->command) { 2729 case XDP_SETUP_PROG: 2730 return otx2_xdp_setup(pf, xdp->prog); 2731 default: 2732 return -EINVAL; 2733 } 2734 } 2735 2736 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2737 int req_perm) 2738 { 2739 struct set_vf_perm *req; 2740 int rc; 2741 2742 mutex_lock(&pf->mbox.lock); 2743 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2744 if (!req) { 2745 rc = -ENOMEM; 2746 goto out; 2747 } 2748 2749 /* Let AF reset VF permissions as sriov is disabled */ 2750 if (req_perm == OTX2_RESET_VF_PERM) { 2751 req->flags |= RESET_VF_PERM; 2752 } else if (req_perm == OTX2_TRUSTED_VF) { 2753 if (pf->vf_configs[vf].trusted) 2754 req->flags |= VF_TRUSTED; 2755 } 2756 2757 req->vf = vf; 2758 rc = otx2_sync_mbox_msg(&pf->mbox); 2759 out: 2760 mutex_unlock(&pf->mbox.lock); 2761 return rc; 2762 } 2763 2764 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2765 bool enable) 2766 { 2767 struct otx2_nic *pf = netdev_priv(netdev); 2768 struct pci_dev *pdev = pf->pdev; 2769 int rc; 2770 2771 if (vf >= pci_num_vf(pdev)) 2772 return -EINVAL; 2773 2774 if (pf->vf_configs[vf].trusted == enable) 2775 return 0; 2776 2777 pf->vf_configs[vf].trusted = enable; 2778 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2779 2780 if (rc) { 2781 pf->vf_configs[vf].trusted = !enable; 2782 } else { 2783 netdev_info(pf->netdev, "VF %d is %strusted\n", 2784 vf, enable ? "" : "not "); 2785 otx2_set_rx_mode(netdev); 2786 } 2787 2788 return rc; 2789 } 2790 2791 static const struct net_device_ops otx2_netdev_ops = { 2792 .ndo_open = otx2_open, 2793 .ndo_stop = otx2_stop, 2794 .ndo_start_xmit = otx2_xmit, 2795 .ndo_select_queue = otx2_select_queue, 2796 .ndo_fix_features = otx2_fix_features, 2797 .ndo_set_mac_address = otx2_set_mac_address, 2798 .ndo_change_mtu = otx2_change_mtu, 2799 .ndo_set_rx_mode = otx2_set_rx_mode, 2800 .ndo_set_features = otx2_set_features, 2801 .ndo_tx_timeout = otx2_tx_timeout, 2802 .ndo_get_stats64 = otx2_get_stats64, 2803 .ndo_eth_ioctl = otx2_ioctl, 2804 .ndo_set_vf_mac = otx2_set_vf_mac, 2805 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2806 .ndo_get_vf_config = otx2_get_vf_config, 2807 .ndo_bpf = otx2_xdp, 2808 .ndo_xdp_xmit = otx2_xdp_xmit, 2809 .ndo_setup_tc = otx2_setup_tc, 2810 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2811 }; 2812 2813 int otx2_wq_init(struct otx2_nic *pf) 2814 { 2815 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2816 if (!pf->otx2_wq) 2817 return -ENOMEM; 2818 2819 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2820 INIT_WORK(&pf->reset_task, otx2_reset_task); 2821 return 0; 2822 } 2823 2824 int otx2_check_pf_usable(struct otx2_nic *nic) 2825 { 2826 u64 rev; 2827 2828 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2829 rev = (rev >> 12) & 0xFF; 2830 /* Check if AF has setup revision for RVUM block, 2831 * otherwise this driver probe should be deferred 2832 * until AF driver comes up. 2833 */ 2834 if (!rev) { 2835 dev_warn(nic->dev, 2836 "AF is not initialized, deferring probe\n"); 2837 return -EPROBE_DEFER; 2838 } 2839 return 0; 2840 } 2841 2842 int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2843 { 2844 struct otx2_hw *hw = &pf->hw; 2845 int num_vec, err; 2846 2847 /* NPA interrupts are inot registered, so alloc only 2848 * upto NIX vector offset. 2849 */ 2850 num_vec = hw->nix_msixoff; 2851 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2852 2853 otx2_disable_mbox_intr(pf); 2854 pci_free_irq_vectors(hw->pdev); 2855 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2856 if (err < 0) { 2857 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2858 __func__, num_vec); 2859 return err; 2860 } 2861 2862 return otx2_register_mbox_intr(pf, false); 2863 } 2864 2865 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2866 { 2867 int i; 2868 2869 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2870 sizeof(struct otx2_vf_config), 2871 GFP_KERNEL); 2872 if (!pf->vf_configs) 2873 return -ENOMEM; 2874 2875 for (i = 0; i < pf->total_vfs; i++) { 2876 pf->vf_configs[i].pf = pf; 2877 pf->vf_configs[i].intf_down = true; 2878 pf->vf_configs[i].trusted = false; 2879 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2880 otx2_vf_link_event_task); 2881 } 2882 2883 return 0; 2884 } 2885 2886 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2887 { 2888 int i; 2889 2890 if (!pf->vf_configs) 2891 return; 2892 2893 for (i = 0; i < pf->total_vfs; i++) { 2894 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2895 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2896 } 2897 } 2898 2899 int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf) 2900 { 2901 struct device *dev = &pdev->dev; 2902 struct otx2_hw *hw = &pf->hw; 2903 int num_vec, err; 2904 2905 num_vec = pci_msix_vec_count(pdev); 2906 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2907 GFP_KERNEL); 2908 if (!hw->irq_name) 2909 return -ENOMEM; 2910 2911 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2912 sizeof(cpumask_var_t), GFP_KERNEL); 2913 if (!hw->affinity_mask) 2914 return -ENOMEM; 2915 2916 /* Map CSRs */ 2917 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2918 if (!pf->reg_base) { 2919 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2920 return -ENOMEM; 2921 } 2922 2923 err = otx2_check_pf_usable(pf); 2924 if (err) 2925 return err; 2926 2927 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2928 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2929 if (err < 0) { 2930 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2931 __func__, num_vec); 2932 return err; 2933 } 2934 2935 otx2_setup_dev_hw_settings(pf); 2936 2937 /* Init PF <=> AF mailbox stuff */ 2938 err = otx2_pfaf_mbox_init(pf); 2939 if (err) 2940 goto err_free_irq_vectors; 2941 2942 /* Register mailbox interrupt */ 2943 err = otx2_register_mbox_intr(pf, true); 2944 if (err) 2945 goto err_mbox_destroy; 2946 2947 /* Request AF to attach NPA and NIX LFs to this PF. 2948 * NIX and NPA LFs are needed for this PF to function as a NIC. 2949 */ 2950 err = otx2_attach_npa_nix(pf); 2951 if (err) 2952 goto err_disable_mbox_intr; 2953 2954 err = otx2_realloc_msix_vectors(pf); 2955 if (err) 2956 goto err_detach_rsrc; 2957 2958 err = cn10k_lmtst_init(pf); 2959 if (err) 2960 goto err_detach_rsrc; 2961 2962 return 0; 2963 2964 err_detach_rsrc: 2965 if (pf->hw.lmt_info) 2966 free_percpu(pf->hw.lmt_info); 2967 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2968 qmem_free(pf->dev, pf->dync_lmt); 2969 otx2_detach_resources(&pf->mbox); 2970 err_disable_mbox_intr: 2971 otx2_disable_mbox_intr(pf); 2972 err_mbox_destroy: 2973 otx2_pfaf_mbox_destroy(pf); 2974 err_free_irq_vectors: 2975 pci_free_irq_vectors(hw->pdev); 2976 2977 return err; 2978 } 2979 2980 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2981 { 2982 struct device *dev = &pdev->dev; 2983 int err, qcount, qos_txqs; 2984 struct net_device *netdev; 2985 struct otx2_nic *pf; 2986 struct otx2_hw *hw; 2987 2988 err = pcim_enable_device(pdev); 2989 if (err) { 2990 dev_err(dev, "Failed to enable PCI device\n"); 2991 return err; 2992 } 2993 2994 err = pci_request_regions(pdev, DRV_NAME); 2995 if (err) { 2996 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2997 return err; 2998 } 2999 3000 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3001 if (err) { 3002 dev_err(dev, "DMA mask config failed, abort\n"); 3003 goto err_release_regions; 3004 } 3005 3006 pci_set_master(pdev); 3007 3008 /* Set number of queues */ 3009 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 3010 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 3011 3012 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount + qos_txqs, qcount); 3013 if (!netdev) { 3014 err = -ENOMEM; 3015 goto err_release_regions; 3016 } 3017 3018 pci_set_drvdata(pdev, netdev); 3019 SET_NETDEV_DEV(netdev, &pdev->dev); 3020 pf = netdev_priv(netdev); 3021 pf->netdev = netdev; 3022 pf->pdev = pdev; 3023 pf->dev = dev; 3024 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 3025 pf->flags |= OTX2_FLAG_INTF_DOWN; 3026 3027 hw = &pf->hw; 3028 hw->pdev = pdev; 3029 hw->rx_queues = qcount; 3030 hw->tx_queues = qcount; 3031 hw->non_qos_queues = qcount; 3032 hw->max_queues = qcount; 3033 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 3034 /* Use CQE of 128 byte descriptor size by default */ 3035 hw->xqe_size = 128; 3036 3037 err = otx2_init_rsrc(pdev, pf); 3038 if (err) 3039 goto err_free_netdev; 3040 3041 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 3042 if (err) 3043 goto err_detach_rsrc; 3044 3045 /* Assign default mac address */ 3046 otx2_get_mac_from_af(netdev); 3047 3048 /* Don't check for error. Proceed without ptp */ 3049 otx2_ptp_init(pf); 3050 3051 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 3052 * HW allocates buffer pointer from stack and uses it for DMA'ing 3053 * ingress packet. In some scenarios HW can free back allocated buffer 3054 * pointers to pool. This makes it impossible for SW to maintain a 3055 * parallel list where physical addresses of buffer pointers (IOVAs) 3056 * given to HW can be saved for later reference. 3057 * 3058 * So the only way to convert Rx packet's buffer address is to use 3059 * IOMMU's iova_to_phys() handler which translates the address by 3060 * walking through the translation tables. 3061 */ 3062 pf->iommu_domain = iommu_get_domain_for_dev(dev); 3063 3064 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 3065 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 3066 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 3067 NETIF_F_GSO_UDP_L4); 3068 netdev->features |= netdev->hw_features; 3069 3070 err = otx2_mcam_flow_init(pf); 3071 if (err) 3072 goto err_ptp_destroy; 3073 3074 err = cn10k_mcs_init(pf); 3075 if (err) 3076 goto err_del_mcam_entries; 3077 3078 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 3079 netdev->hw_features |= NETIF_F_NTUPLE; 3080 3081 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 3082 netdev->priv_flags |= IFF_UNICAST_FLT; 3083 3084 /* Support TSO on tag interface */ 3085 netdev->vlan_features |= netdev->features; 3086 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 3087 NETIF_F_HW_VLAN_STAG_TX; 3088 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 3089 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 3090 NETIF_F_HW_VLAN_STAG_RX; 3091 netdev->features |= netdev->hw_features; 3092 3093 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 3094 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 3095 netdev->hw_features |= NETIF_F_HW_TC; 3096 3097 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 3098 3099 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 3100 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 3101 3102 netdev->netdev_ops = &otx2_netdev_ops; 3103 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3104 3105 netdev->min_mtu = OTX2_MIN_MTU; 3106 netdev->max_mtu = otx2_get_max_mtu(pf); 3107 hw->max_mtu = netdev->max_mtu; 3108 3109 /* reset CGX/RPM MAC stats */ 3110 otx2_reset_mac_stats(pf); 3111 3112 err = register_netdev(netdev); 3113 if (err) { 3114 dev_err(dev, "Failed to register netdevice\n"); 3115 goto err_mcs_free; 3116 } 3117 3118 err = otx2_wq_init(pf); 3119 if (err) 3120 goto err_unreg_netdev; 3121 3122 otx2_set_ethtool_ops(netdev); 3123 3124 err = otx2_init_tc(pf); 3125 if (err) 3126 goto err_mcam_flow_del; 3127 3128 err = otx2_register_dl(pf); 3129 if (err) 3130 goto err_mcam_flow_del; 3131 3132 /* Initialize SR-IOV resources */ 3133 err = otx2_sriov_vfcfg_init(pf); 3134 if (err) 3135 goto err_pf_sriov_init; 3136 3137 /* Enable link notifications */ 3138 otx2_cgx_config_linkevents(pf, true); 3139 3140 #ifdef CONFIG_DCB 3141 err = otx2_dcbnl_set_ops(netdev); 3142 if (err) 3143 goto err_pf_sriov_init; 3144 #endif 3145 3146 otx2_qos_init(pf, qos_txqs); 3147 3148 return 0; 3149 3150 err_pf_sriov_init: 3151 otx2_shutdown_tc(pf); 3152 err_mcam_flow_del: 3153 otx2_mcam_flow_del(pf); 3154 err_unreg_netdev: 3155 unregister_netdev(netdev); 3156 err_mcs_free: 3157 cn10k_mcs_free(pf); 3158 err_del_mcam_entries: 3159 otx2_mcam_flow_del(pf); 3160 err_ptp_destroy: 3161 otx2_ptp_destroy(pf); 3162 err_detach_rsrc: 3163 if (pf->hw.lmt_info) 3164 free_percpu(pf->hw.lmt_info); 3165 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3166 qmem_free(pf->dev, pf->dync_lmt); 3167 otx2_detach_resources(&pf->mbox); 3168 otx2_disable_mbox_intr(pf); 3169 otx2_pfaf_mbox_destroy(pf); 3170 pci_free_irq_vectors(hw->pdev); 3171 err_free_netdev: 3172 pci_set_drvdata(pdev, NULL); 3173 free_netdev(netdev); 3174 err_release_regions: 3175 pci_release_regions(pdev); 3176 return err; 3177 } 3178 3179 static void otx2_vf_link_event_task(struct work_struct *work) 3180 { 3181 struct otx2_vf_config *config; 3182 struct cgx_link_info_msg *req; 3183 struct mbox_msghdr *msghdr; 3184 struct delayed_work *dwork; 3185 struct otx2_nic *pf; 3186 int vf_idx; 3187 3188 config = container_of(work, struct otx2_vf_config, 3189 link_event_work.work); 3190 vf_idx = config - config->pf->vf_configs; 3191 pf = config->pf; 3192 3193 if (config->intf_down) 3194 return; 3195 3196 mutex_lock(&pf->mbox.lock); 3197 3198 dwork = &config->link_event_work; 3199 3200 if (!otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx)) { 3201 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 3202 mutex_unlock(&pf->mbox.lock); 3203 return; 3204 } 3205 3206 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 3207 sizeof(*req), sizeof(struct msg_rsp)); 3208 if (!msghdr) { 3209 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 3210 mutex_unlock(&pf->mbox.lock); 3211 return; 3212 } 3213 3214 req = (struct cgx_link_info_msg *)msghdr; 3215 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 3216 req->hdr.sig = OTX2_MBOX_REQ_SIG; 3217 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 3218 3219 otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx); 3220 3221 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 3222 3223 mutex_unlock(&pf->mbox.lock); 3224 } 3225 3226 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 3227 { 3228 struct net_device *netdev = pci_get_drvdata(pdev); 3229 struct otx2_nic *pf = netdev_priv(netdev); 3230 int ret; 3231 3232 /* Init PF <=> VF mailbox stuff */ 3233 ret = otx2_pfvf_mbox_init(pf, numvfs); 3234 if (ret) 3235 return ret; 3236 3237 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 3238 if (ret) 3239 goto free_mbox; 3240 3241 ret = otx2_pf_flr_init(pf, numvfs); 3242 if (ret) 3243 goto free_intr; 3244 3245 ret = otx2_register_flr_me_intr(pf, numvfs); 3246 if (ret) 3247 goto free_flr; 3248 3249 ret = pci_enable_sriov(pdev, numvfs); 3250 if (ret) 3251 goto free_flr_intr; 3252 3253 return numvfs; 3254 free_flr_intr: 3255 otx2_disable_flr_me_intr(pf); 3256 free_flr: 3257 otx2_flr_wq_destroy(pf); 3258 free_intr: 3259 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3260 free_mbox: 3261 otx2_pfvf_mbox_destroy(pf); 3262 return ret; 3263 } 3264 3265 static int otx2_sriov_disable(struct pci_dev *pdev) 3266 { 3267 struct net_device *netdev = pci_get_drvdata(pdev); 3268 struct otx2_nic *pf = netdev_priv(netdev); 3269 int numvfs = pci_num_vf(pdev); 3270 3271 if (!numvfs) 3272 return 0; 3273 3274 pci_disable_sriov(pdev); 3275 3276 otx2_disable_flr_me_intr(pf); 3277 otx2_flr_wq_destroy(pf); 3278 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3279 otx2_pfvf_mbox_destroy(pf); 3280 3281 return 0; 3282 } 3283 3284 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 3285 { 3286 if (numvfs == 0) 3287 return otx2_sriov_disable(pdev); 3288 else 3289 return otx2_sriov_enable(pdev, numvfs); 3290 } 3291 3292 static void otx2_ndc_sync(struct otx2_nic *pf) 3293 { 3294 struct mbox *mbox = &pf->mbox; 3295 struct ndc_sync_op *req; 3296 3297 mutex_lock(&mbox->lock); 3298 3299 req = otx2_mbox_alloc_msg_ndc_sync_op(mbox); 3300 if (!req) { 3301 mutex_unlock(&mbox->lock); 3302 return; 3303 } 3304 3305 req->nix_lf_tx_sync = 1; 3306 req->nix_lf_rx_sync = 1; 3307 req->npa_lf_sync = 1; 3308 3309 if (!otx2_sync_mbox_msg(mbox)) 3310 dev_err(pf->dev, "NDC sync operation failed\n"); 3311 3312 mutex_unlock(&mbox->lock); 3313 } 3314 3315 static void otx2_remove(struct pci_dev *pdev) 3316 { 3317 struct net_device *netdev = pci_get_drvdata(pdev); 3318 struct otx2_nic *pf; 3319 3320 if (!netdev) 3321 return; 3322 3323 pf = netdev_priv(netdev); 3324 3325 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 3326 3327 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 3328 otx2_config_hw_tx_tstamp(pf, false); 3329 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 3330 otx2_config_hw_rx_tstamp(pf, false); 3331 3332 /* Disable 802.3x pause frames */ 3333 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 3334 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 3335 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 3336 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 3337 otx2_config_pause_frm(pf); 3338 } 3339 3340 #ifdef CONFIG_DCB 3341 /* Disable PFC config */ 3342 if (pf->pfc_en) { 3343 pf->pfc_en = 0; 3344 otx2_config_priority_flow_ctrl(pf); 3345 } 3346 #endif 3347 cancel_work_sync(&pf->reset_task); 3348 /* Disable link notifications */ 3349 otx2_cgx_config_linkevents(pf, false); 3350 3351 otx2_unregister_dl(pf); 3352 unregister_netdev(netdev); 3353 cn10k_mcs_free(pf); 3354 otx2_sriov_disable(pf->pdev); 3355 otx2_sriov_vfcfg_cleanup(pf); 3356 if (pf->otx2_wq) 3357 destroy_workqueue(pf->otx2_wq); 3358 3359 otx2_ptp_destroy(pf); 3360 otx2_mcam_flow_del(pf); 3361 otx2_shutdown_tc(pf); 3362 otx2_shutdown_qos(pf); 3363 otx2_ndc_sync(pf); 3364 otx2_detach_resources(&pf->mbox); 3365 if (pf->hw.lmt_info) 3366 free_percpu(pf->hw.lmt_info); 3367 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3368 qmem_free(pf->dev, pf->dync_lmt); 3369 otx2_disable_mbox_intr(pf); 3370 otx2_pfaf_mbox_destroy(pf); 3371 pci_free_irq_vectors(pf->pdev); 3372 pci_set_drvdata(pdev, NULL); 3373 free_netdev(netdev); 3374 3375 pci_release_regions(pdev); 3376 } 3377 3378 static struct pci_driver otx2_pf_driver = { 3379 .name = DRV_NAME, 3380 .id_table = otx2_pf_id_table, 3381 .probe = otx2_probe, 3382 .shutdown = otx2_remove, 3383 .remove = otx2_remove, 3384 .sriov_configure = otx2_sriov_configure 3385 }; 3386 3387 static int __init otx2_rvupf_init_module(void) 3388 { 3389 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3390 3391 return pci_register_driver(&otx2_pf_driver); 3392 } 3393 3394 static void __exit otx2_rvupf_cleanup_module(void) 3395 { 3396 pci_unregister_driver(&otx2_pf_driver); 3397 } 3398 3399 module_init(otx2_rvupf_init_module); 3400 module_exit(otx2_rvupf_cleanup_module); 3401