1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Physcial Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/pci.h> 14 #include <linux/etherdevice.h> 15 #include <linux/of.h> 16 #include <linux/if_vlan.h> 17 #include <linux/iommu.h> 18 #include <net/ip.h> 19 20 #include "otx2_reg.h" 21 #include "otx2_common.h" 22 #include "otx2_txrx.h" 23 #include "otx2_struct.h" 24 #include "otx2_ptp.h" 25 26 #define DRV_NAME "octeontx2-nicpf" 27 #define DRV_STRING "Marvell OcteonTX2 NIC Physical Function Driver" 28 29 /* Supported devices */ 30 static const struct pci_device_id otx2_pf_id_table[] = { 31 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 32 { 0, } /* end of table */ 33 }; 34 35 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 36 MODULE_DESCRIPTION(DRV_STRING); 37 MODULE_LICENSE("GPL v2"); 38 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 39 40 enum { 41 TYPE_PFAF, 42 TYPE_PFVF, 43 }; 44 45 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 46 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 47 48 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 49 { 50 bool if_up = netif_running(netdev); 51 int err = 0; 52 53 if (if_up) 54 otx2_stop(netdev); 55 56 netdev_info(netdev, "Changing MTU from %d to %d\n", 57 netdev->mtu, new_mtu); 58 netdev->mtu = new_mtu; 59 60 if (if_up) 61 err = otx2_open(netdev); 62 63 return err; 64 } 65 66 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 67 { 68 int irq, vfs = pf->total_vfs; 69 70 /* Disable VFs ME interrupts */ 71 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 72 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 73 free_irq(irq, pf); 74 75 /* Disable VFs FLR interrupts */ 76 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 77 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 78 free_irq(irq, pf); 79 80 if (vfs <= 64) 81 return; 82 83 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 84 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 85 free_irq(irq, pf); 86 87 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 88 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 89 free_irq(irq, pf); 90 } 91 92 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 93 { 94 if (!pf->flr_wq) 95 return; 96 destroy_workqueue(pf->flr_wq); 97 pf->flr_wq = NULL; 98 devm_kfree(pf->dev, pf->flr_wrk); 99 } 100 101 static void otx2_flr_handler(struct work_struct *work) 102 { 103 struct flr_work *flrwork = container_of(work, struct flr_work, work); 104 struct otx2_nic *pf = flrwork->pf; 105 struct mbox *mbox = &pf->mbox; 106 struct msg_req *req; 107 int vf, reg = 0; 108 109 vf = flrwork - pf->flr_wrk; 110 111 mutex_lock(&mbox->lock); 112 req = otx2_mbox_alloc_msg_vf_flr(mbox); 113 if (!req) { 114 mutex_unlock(&mbox->lock); 115 return; 116 } 117 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 118 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 119 120 if (!otx2_sync_mbox_msg(&pf->mbox)) { 121 if (vf >= 64) { 122 reg = 1; 123 vf = vf - 64; 124 } 125 /* clear transcation pending bit */ 126 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 127 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 128 } 129 130 mutex_unlock(&mbox->lock); 131 } 132 133 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 134 { 135 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 136 int reg, dev, vf, start_vf, num_reg = 1; 137 u64 intr; 138 139 if (pf->total_vfs > 64) 140 num_reg = 2; 141 142 for (reg = 0; reg < num_reg; reg++) { 143 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 144 if (!intr) 145 continue; 146 start_vf = 64 * reg; 147 for (vf = 0; vf < 64; vf++) { 148 if (!(intr & BIT_ULL(vf))) 149 continue; 150 dev = vf + start_vf; 151 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 152 /* Clear interrupt */ 153 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 154 /* Disable the interrupt */ 155 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 156 BIT_ULL(vf)); 157 } 158 } 159 return IRQ_HANDLED; 160 } 161 162 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 163 { 164 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 165 int vf, reg, num_reg = 1; 166 u64 intr; 167 168 if (pf->total_vfs > 64) 169 num_reg = 2; 170 171 for (reg = 0; reg < num_reg; reg++) { 172 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 173 if (!intr) 174 continue; 175 for (vf = 0; vf < 64; vf++) { 176 if (!(intr & BIT_ULL(vf))) 177 continue; 178 /* clear trpend bit */ 179 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 180 /* clear interrupt */ 181 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 182 } 183 } 184 return IRQ_HANDLED; 185 } 186 187 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 188 { 189 struct otx2_hw *hw = &pf->hw; 190 char *irq_name; 191 int ret; 192 193 /* Register ME interrupt handler*/ 194 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 195 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 196 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 197 otx2_pf_me_intr_handler, 0, irq_name, pf); 198 if (ret) { 199 dev_err(pf->dev, 200 "RVUPF: IRQ registration failed for ME0\n"); 201 } 202 203 /* Register FLR interrupt handler */ 204 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 205 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 206 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 207 otx2_pf_flr_intr_handler, 0, irq_name, pf); 208 if (ret) { 209 dev_err(pf->dev, 210 "RVUPF: IRQ registration failed for FLR0\n"); 211 return ret; 212 } 213 214 if (numvfs > 64) { 215 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 216 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 217 rvu_get_pf(pf->pcifunc)); 218 ret = request_irq(pci_irq_vector 219 (pf->pdev, RVU_PF_INT_VEC_VFME1), 220 otx2_pf_me_intr_handler, 0, irq_name, pf); 221 if (ret) { 222 dev_err(pf->dev, 223 "RVUPF: IRQ registration failed for ME1\n"); 224 } 225 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 226 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 227 rvu_get_pf(pf->pcifunc)); 228 ret = request_irq(pci_irq_vector 229 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 230 otx2_pf_flr_intr_handler, 0, irq_name, pf); 231 if (ret) { 232 dev_err(pf->dev, 233 "RVUPF: IRQ registration failed for FLR1\n"); 234 return ret; 235 } 236 } 237 238 /* Enable ME interrupt for all VFs*/ 239 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 240 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 241 242 /* Enable FLR interrupt for all VFs*/ 243 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 244 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 245 246 if (numvfs > 64) { 247 numvfs -= 64; 248 249 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 250 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 251 INTR_MASK(numvfs)); 252 253 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 254 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 255 INTR_MASK(numvfs)); 256 } 257 return 0; 258 } 259 260 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 261 { 262 int vf; 263 264 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 265 WQ_UNBOUND | WQ_HIGHPRI, 1); 266 if (!pf->flr_wq) 267 return -ENOMEM; 268 269 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 270 sizeof(struct flr_work), GFP_KERNEL); 271 if (!pf->flr_wrk) { 272 destroy_workqueue(pf->flr_wq); 273 return -ENOMEM; 274 } 275 276 for (vf = 0; vf < num_vfs; vf++) { 277 pf->flr_wrk[vf].pf = pf; 278 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 279 } 280 281 return 0; 282 } 283 284 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 285 int first, int mdevs, u64 intr, int type) 286 { 287 struct otx2_mbox_dev *mdev; 288 struct otx2_mbox *mbox; 289 struct mbox_hdr *hdr; 290 int i; 291 292 for (i = first; i < mdevs; i++) { 293 /* start from 0 */ 294 if (!(intr & BIT_ULL(i - first))) 295 continue; 296 297 mbox = &mw->mbox; 298 mdev = &mbox->dev[i]; 299 if (type == TYPE_PFAF) 300 otx2_sync_mbox_bbuf(mbox, i); 301 hdr = mdev->mbase + mbox->rx_start; 302 /* The hdr->num_msgs is set to zero immediately in the interrupt 303 * handler to ensure that it holds a correct value next time 304 * when the interrupt handler is called. 305 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 306 * pf>mbox.up_num_msgs holds the data for use in 307 * pfaf_mbox_up_handler. 308 */ 309 if (hdr->num_msgs) { 310 mw[i].num_msgs = hdr->num_msgs; 311 hdr->num_msgs = 0; 312 if (type == TYPE_PFAF) 313 memset(mbox->hwbase + mbox->rx_start, 0, 314 ALIGN(sizeof(struct mbox_hdr), 315 sizeof(u64))); 316 317 queue_work(mbox_wq, &mw[i].mbox_wrk); 318 } 319 320 mbox = &mw->mbox_up; 321 mdev = &mbox->dev[i]; 322 if (type == TYPE_PFAF) 323 otx2_sync_mbox_bbuf(mbox, i); 324 hdr = mdev->mbase + mbox->rx_start; 325 if (hdr->num_msgs) { 326 mw[i].up_num_msgs = hdr->num_msgs; 327 hdr->num_msgs = 0; 328 if (type == TYPE_PFAF) 329 memset(mbox->hwbase + mbox->rx_start, 0, 330 ALIGN(sizeof(struct mbox_hdr), 331 sizeof(u64))); 332 333 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 334 } 335 } 336 } 337 338 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 339 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 340 int devid) 341 { 342 struct otx2_mbox_dev *src_mdev = mdev; 343 int offset; 344 345 /* Msgs are already copied, trigger VF's mbox irq */ 346 smp_wmb(); 347 348 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 349 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 350 351 /* Restore VF's mbox bounce buffer region address */ 352 src_mdev->mbase = bbuf_base; 353 } 354 355 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 356 struct otx2_mbox *src_mbox, 357 int dir, int vf, int num_msgs) 358 { 359 struct otx2_mbox_dev *src_mdev, *dst_mdev; 360 struct mbox_hdr *mbox_hdr; 361 struct mbox_hdr *req_hdr; 362 struct mbox *dst_mbox; 363 int dst_size, err; 364 365 if (dir == MBOX_DIR_PFAF) { 366 /* Set VF's mailbox memory as PF's bounce buffer memory, so 367 * that explicit copying of VF's msgs to PF=>AF mbox region 368 * and AF=>PF responses to VF's mbox region can be avoided. 369 */ 370 src_mdev = &src_mbox->dev[vf]; 371 mbox_hdr = src_mbox->hwbase + 372 src_mbox->rx_start + (vf * MBOX_SIZE); 373 374 dst_mbox = &pf->mbox; 375 dst_size = dst_mbox->mbox.tx_size - 376 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 377 /* Check if msgs fit into destination area */ 378 if (mbox_hdr->msg_size > dst_size) 379 return -EINVAL; 380 381 dst_mdev = &dst_mbox->mbox.dev[0]; 382 383 mutex_lock(&pf->mbox.lock); 384 dst_mdev->mbase = src_mdev->mbase; 385 dst_mdev->msg_size = mbox_hdr->msg_size; 386 dst_mdev->num_msgs = num_msgs; 387 err = otx2_sync_mbox_msg(dst_mbox); 388 if (err) { 389 dev_warn(pf->dev, 390 "AF not responding to VF%d messages\n", vf); 391 /* restore PF mbase and exit */ 392 dst_mdev->mbase = pf->mbox.bbuf_base; 393 mutex_unlock(&pf->mbox.lock); 394 return err; 395 } 396 /* At this point, all the VF messages sent to AF are acked 397 * with proper responses and responses are copied to VF 398 * mailbox hence raise interrupt to VF. 399 */ 400 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 401 dst_mbox->mbox.rx_start); 402 req_hdr->num_msgs = num_msgs; 403 404 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 405 pf->mbox.bbuf_base, vf); 406 mutex_unlock(&pf->mbox.lock); 407 } else if (dir == MBOX_DIR_PFVF_UP) { 408 src_mdev = &src_mbox->dev[0]; 409 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 410 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 411 src_mbox->rx_start); 412 req_hdr->num_msgs = num_msgs; 413 414 dst_mbox = &pf->mbox_pfvf[0]; 415 dst_size = dst_mbox->mbox_up.tx_size - 416 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 417 /* Check if msgs fit into destination area */ 418 if (mbox_hdr->msg_size > dst_size) 419 return -EINVAL; 420 421 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 422 dst_mdev->mbase = src_mdev->mbase; 423 dst_mdev->msg_size = mbox_hdr->msg_size; 424 dst_mdev->num_msgs = mbox_hdr->num_msgs; 425 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 426 if (err) { 427 dev_warn(pf->dev, 428 "VF%d is not responding to mailbox\n", vf); 429 return err; 430 } 431 } else if (dir == MBOX_DIR_VFPF_UP) { 432 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 433 src_mbox->rx_start); 434 req_hdr->num_msgs = num_msgs; 435 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 436 &pf->mbox.mbox_up, 437 pf->mbox_pfvf[vf].bbuf_base, 438 0); 439 } 440 441 return 0; 442 } 443 444 static void otx2_pfvf_mbox_handler(struct work_struct *work) 445 { 446 struct mbox_msghdr *msg = NULL; 447 int offset, vf_idx, id, err; 448 struct otx2_mbox_dev *mdev; 449 struct mbox_hdr *req_hdr; 450 struct otx2_mbox *mbox; 451 struct mbox *vf_mbox; 452 struct otx2_nic *pf; 453 454 vf_mbox = container_of(work, struct mbox, mbox_wrk); 455 pf = vf_mbox->pfvf; 456 vf_idx = vf_mbox - pf->mbox_pfvf; 457 458 mbox = &pf->mbox_pfvf[0].mbox; 459 mdev = &mbox->dev[vf_idx]; 460 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 461 462 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 463 464 for (id = 0; id < vf_mbox->num_msgs; id++) { 465 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 466 offset); 467 468 if (msg->sig != OTX2_MBOX_REQ_SIG) 469 goto inval_msg; 470 471 /* Set VF's number in each of the msg */ 472 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 473 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 474 offset = msg->next_msgoff; 475 } 476 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 477 vf_mbox->num_msgs); 478 if (err) 479 goto inval_msg; 480 return; 481 482 inval_msg: 483 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 484 otx2_mbox_msg_send(mbox, vf_idx); 485 } 486 487 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 488 { 489 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 490 struct otx2_nic *pf = vf_mbox->pfvf; 491 struct otx2_mbox_dev *mdev; 492 int offset, id, vf_idx = 0; 493 struct mbox_hdr *rsp_hdr; 494 struct mbox_msghdr *msg; 495 struct otx2_mbox *mbox; 496 497 vf_idx = vf_mbox - pf->mbox_pfvf; 498 mbox = &pf->mbox_pfvf[0].mbox_up; 499 mdev = &mbox->dev[vf_idx]; 500 501 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 502 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 503 504 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 505 msg = mdev->mbase + offset; 506 507 if (msg->id >= MBOX_MSG_MAX) { 508 dev_err(pf->dev, 509 "Mbox msg with unknown ID 0x%x\n", msg->id); 510 goto end; 511 } 512 513 if (msg->sig != OTX2_MBOX_RSP_SIG) { 514 dev_err(pf->dev, 515 "Mbox msg with wrong signature %x, ID 0x%x\n", 516 msg->sig, msg->id); 517 goto end; 518 } 519 520 switch (msg->id) { 521 case MBOX_MSG_CGX_LINK_EVENT: 522 break; 523 default: 524 if (msg->rc) 525 dev_err(pf->dev, 526 "Mbox msg response has err %d, ID 0x%x\n", 527 msg->rc, msg->id); 528 break; 529 } 530 531 end: 532 offset = mbox->rx_start + msg->next_msgoff; 533 mdev->msgs_acked++; 534 } 535 536 otx2_mbox_reset(mbox, vf_idx); 537 } 538 539 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 540 { 541 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 542 int vfs = pf->total_vfs; 543 struct mbox *mbox; 544 u64 intr; 545 546 mbox = pf->mbox_pfvf; 547 /* Handle VF interrupts */ 548 if (vfs > 64) { 549 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 550 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 551 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 552 TYPE_PFVF); 553 vfs -= 64; 554 } 555 556 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 557 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 558 559 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 560 561 return IRQ_HANDLED; 562 } 563 564 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 565 { 566 void __iomem *hwbase; 567 struct mbox *mbox; 568 int err, vf; 569 u64 base; 570 571 if (!numvfs) 572 return -EINVAL; 573 574 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 575 sizeof(struct mbox), GFP_KERNEL); 576 if (!pf->mbox_pfvf) 577 return -ENOMEM; 578 579 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 580 WQ_UNBOUND | WQ_HIGHPRI | 581 WQ_MEM_RECLAIM, 1); 582 if (!pf->mbox_pfvf_wq) 583 return -ENOMEM; 584 585 base = readq((void __iomem *)((u64)pf->reg_base + RVU_PF_VF_BAR4_ADDR)); 586 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 587 588 if (!hwbase) { 589 err = -ENOMEM; 590 goto free_wq; 591 } 592 593 mbox = &pf->mbox_pfvf[0]; 594 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 595 MBOX_DIR_PFVF, numvfs); 596 if (err) 597 goto free_iomem; 598 599 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 600 MBOX_DIR_PFVF_UP, numvfs); 601 if (err) 602 goto free_iomem; 603 604 for (vf = 0; vf < numvfs; vf++) { 605 mbox->pfvf = pf; 606 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 607 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 608 mbox++; 609 } 610 611 return 0; 612 613 free_iomem: 614 if (hwbase) 615 iounmap(hwbase); 616 free_wq: 617 destroy_workqueue(pf->mbox_pfvf_wq); 618 return err; 619 } 620 621 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 622 { 623 struct mbox *mbox = &pf->mbox_pfvf[0]; 624 625 if (!mbox) 626 return; 627 628 if (pf->mbox_pfvf_wq) { 629 destroy_workqueue(pf->mbox_pfvf_wq); 630 pf->mbox_pfvf_wq = NULL; 631 } 632 633 if (mbox->mbox.hwbase) 634 iounmap(mbox->mbox.hwbase); 635 636 otx2_mbox_destroy(&mbox->mbox); 637 } 638 639 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 640 { 641 /* Clear PF <=> VF mailbox IRQ */ 642 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 643 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 644 645 /* Enable PF <=> VF mailbox IRQ */ 646 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 647 if (numvfs > 64) { 648 numvfs -= 64; 649 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 650 INTR_MASK(numvfs)); 651 } 652 } 653 654 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 655 { 656 int vector; 657 658 /* Disable PF <=> VF mailbox IRQ */ 659 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 660 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 661 662 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 663 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 664 free_irq(vector, pf); 665 666 if (numvfs > 64) { 667 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 668 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 669 free_irq(vector, pf); 670 } 671 } 672 673 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 674 { 675 struct otx2_hw *hw = &pf->hw; 676 char *irq_name; 677 int err; 678 679 /* Register MBOX0 interrupt handler */ 680 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 681 if (pf->pcifunc) 682 snprintf(irq_name, NAME_SIZE, 683 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 684 else 685 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 686 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 687 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 688 if (err) { 689 dev_err(pf->dev, 690 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 691 return err; 692 } 693 694 if (numvfs > 64) { 695 /* Register MBOX1 interrupt handler */ 696 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 697 if (pf->pcifunc) 698 snprintf(irq_name, NAME_SIZE, 699 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 700 else 701 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 702 err = request_irq(pci_irq_vector(pf->pdev, 703 RVU_PF_INT_VEC_VFPF_MBOX1), 704 otx2_pfvf_mbox_intr_handler, 705 0, irq_name, pf); 706 if (err) { 707 dev_err(pf->dev, 708 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 709 return err; 710 } 711 } 712 713 otx2_enable_pfvf_mbox_intr(pf, numvfs); 714 715 return 0; 716 } 717 718 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 719 struct mbox_msghdr *msg) 720 { 721 int devid; 722 723 if (msg->id >= MBOX_MSG_MAX) { 724 dev_err(pf->dev, 725 "Mbox msg with unknown ID 0x%x\n", msg->id); 726 return; 727 } 728 729 if (msg->sig != OTX2_MBOX_RSP_SIG) { 730 dev_err(pf->dev, 731 "Mbox msg with wrong signature %x, ID 0x%x\n", 732 msg->sig, msg->id); 733 return; 734 } 735 736 /* message response heading VF */ 737 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 738 if (devid) { 739 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 740 struct delayed_work *dwork; 741 742 switch (msg->id) { 743 case MBOX_MSG_NIX_LF_START_RX: 744 config->intf_down = false; 745 dwork = &config->link_event_work; 746 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 747 break; 748 case MBOX_MSG_NIX_LF_STOP_RX: 749 config->intf_down = true; 750 break; 751 } 752 753 return; 754 } 755 756 switch (msg->id) { 757 case MBOX_MSG_READY: 758 pf->pcifunc = msg->pcifunc; 759 break; 760 case MBOX_MSG_MSIX_OFFSET: 761 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 762 break; 763 case MBOX_MSG_NPA_LF_ALLOC: 764 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 765 break; 766 case MBOX_MSG_NIX_LF_ALLOC: 767 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 768 break; 769 case MBOX_MSG_NIX_TXSCH_ALLOC: 770 mbox_handler_nix_txsch_alloc(pf, 771 (struct nix_txsch_alloc_rsp *)msg); 772 break; 773 case MBOX_MSG_NIX_BP_ENABLE: 774 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 775 break; 776 case MBOX_MSG_CGX_STATS: 777 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 778 break; 779 default: 780 if (msg->rc) 781 dev_err(pf->dev, 782 "Mbox msg response has err %d, ID 0x%x\n", 783 msg->rc, msg->id); 784 break; 785 } 786 } 787 788 static void otx2_pfaf_mbox_handler(struct work_struct *work) 789 { 790 struct otx2_mbox_dev *mdev; 791 struct mbox_hdr *rsp_hdr; 792 struct mbox_msghdr *msg; 793 struct otx2_mbox *mbox; 794 struct mbox *af_mbox; 795 struct otx2_nic *pf; 796 int offset, id; 797 798 af_mbox = container_of(work, struct mbox, mbox_wrk); 799 mbox = &af_mbox->mbox; 800 mdev = &mbox->dev[0]; 801 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 802 803 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 804 pf = af_mbox->pfvf; 805 806 for (id = 0; id < af_mbox->num_msgs; id++) { 807 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 808 otx2_process_pfaf_mbox_msg(pf, msg); 809 offset = mbox->rx_start + msg->next_msgoff; 810 mdev->msgs_acked++; 811 } 812 813 otx2_mbox_reset(mbox, 0); 814 } 815 816 static void otx2_handle_link_event(struct otx2_nic *pf) 817 { 818 struct cgx_link_user_info *linfo = &pf->linfo; 819 struct net_device *netdev = pf->netdev; 820 821 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 822 linfo->link_up ? "UP" : "DOWN", linfo->speed, 823 linfo->full_duplex ? "Full" : "Half"); 824 if (linfo->link_up) { 825 netif_carrier_on(netdev); 826 netif_tx_start_all_queues(netdev); 827 } else { 828 netif_tx_stop_all_queues(netdev); 829 netif_carrier_off(netdev); 830 } 831 } 832 833 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 834 struct cgx_link_info_msg *msg, 835 struct msg_rsp *rsp) 836 { 837 int i; 838 839 /* Copy the link info sent by AF */ 840 pf->linfo = msg->link_info; 841 842 /* notify VFs about link event */ 843 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 844 struct otx2_vf_config *config = &pf->vf_configs[i]; 845 struct delayed_work *dwork = &config->link_event_work; 846 847 if (config->intf_down) 848 continue; 849 850 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 851 } 852 853 /* interface has not been fully configured yet */ 854 if (pf->flags & OTX2_FLAG_INTF_DOWN) 855 return 0; 856 857 otx2_handle_link_event(pf); 858 return 0; 859 } 860 861 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 862 struct mbox_msghdr *req) 863 { 864 /* Check if valid, if not reply with a invalid msg */ 865 if (req->sig != OTX2_MBOX_REQ_SIG) { 866 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 867 return -ENODEV; 868 } 869 870 switch (req->id) { 871 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 872 case _id: { \ 873 struct _rsp_type *rsp; \ 874 int err; \ 875 \ 876 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 877 &pf->mbox.mbox_up, 0, \ 878 sizeof(struct _rsp_type)); \ 879 if (!rsp) \ 880 return -ENOMEM; \ 881 \ 882 rsp->hdr.id = _id; \ 883 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 884 rsp->hdr.pcifunc = 0; \ 885 rsp->hdr.rc = 0; \ 886 \ 887 err = otx2_mbox_up_handler_ ## _fn_name( \ 888 pf, (struct _req_type *)req, rsp); \ 889 return err; \ 890 } 891 MBOX_UP_CGX_MESSAGES 892 #undef M 893 break; 894 default: 895 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 896 return -ENODEV; 897 } 898 return 0; 899 } 900 901 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 902 { 903 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 904 struct otx2_mbox *mbox = &af_mbox->mbox_up; 905 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 906 struct otx2_nic *pf = af_mbox->pfvf; 907 int offset, id, devid = 0; 908 struct mbox_hdr *rsp_hdr; 909 struct mbox_msghdr *msg; 910 911 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 912 913 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 914 915 for (id = 0; id < af_mbox->up_num_msgs; id++) { 916 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 917 918 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 919 /* Skip processing VF's messages */ 920 if (!devid) 921 otx2_process_mbox_msg_up(pf, msg); 922 offset = mbox->rx_start + msg->next_msgoff; 923 } 924 if (devid) { 925 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 926 MBOX_DIR_PFVF_UP, devid - 1, 927 af_mbox->up_num_msgs); 928 return; 929 } 930 931 otx2_mbox_msg_send(mbox, 0); 932 } 933 934 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 935 { 936 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 937 struct mbox *mbox; 938 939 /* Clear the IRQ */ 940 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 941 942 mbox = &pf->mbox; 943 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 944 945 return IRQ_HANDLED; 946 } 947 948 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 949 { 950 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 951 952 /* Disable AF => PF mailbox IRQ */ 953 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 954 free_irq(vector, pf); 955 } 956 957 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 958 { 959 struct otx2_hw *hw = &pf->hw; 960 struct msg_req *req; 961 char *irq_name; 962 int err; 963 964 /* Register mailbox interrupt handler */ 965 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 966 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 967 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 968 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 969 if (err) { 970 dev_err(pf->dev, 971 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 972 return err; 973 } 974 975 /* Enable mailbox interrupt for msgs coming from AF. 976 * First clear to avoid spurious interrupts, if any. 977 */ 978 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 979 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 980 981 if (!probe_af) 982 return 0; 983 984 /* Check mailbox communication with AF */ 985 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 986 if (!req) { 987 otx2_disable_mbox_intr(pf); 988 return -ENOMEM; 989 } 990 err = otx2_sync_mbox_msg(&pf->mbox); 991 if (err) { 992 dev_warn(pf->dev, 993 "AF not responding to mailbox, deferring probe\n"); 994 otx2_disable_mbox_intr(pf); 995 return -EPROBE_DEFER; 996 } 997 998 return 0; 999 } 1000 1001 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1002 { 1003 struct mbox *mbox = &pf->mbox; 1004 1005 if (pf->mbox_wq) { 1006 destroy_workqueue(pf->mbox_wq); 1007 pf->mbox_wq = NULL; 1008 } 1009 1010 if (mbox->mbox.hwbase) 1011 iounmap((void __iomem *)mbox->mbox.hwbase); 1012 1013 otx2_mbox_destroy(&mbox->mbox); 1014 otx2_mbox_destroy(&mbox->mbox_up); 1015 } 1016 1017 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1018 { 1019 struct mbox *mbox = &pf->mbox; 1020 void __iomem *hwbase; 1021 int err; 1022 1023 mbox->pfvf = pf; 1024 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1025 WQ_UNBOUND | WQ_HIGHPRI | 1026 WQ_MEM_RECLAIM, 1); 1027 if (!pf->mbox_wq) 1028 return -ENOMEM; 1029 1030 /* Mailbox is a reserved memory (in RAM) region shared between 1031 * admin function (i.e AF) and this PF, shouldn't be mapped as 1032 * device memory to allow unaligned accesses. 1033 */ 1034 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1035 pci_resource_len(pf->pdev, PCI_MBOX_BAR_NUM)); 1036 if (!hwbase) { 1037 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1038 err = -ENOMEM; 1039 goto exit; 1040 } 1041 1042 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1043 MBOX_DIR_PFAF, 1); 1044 if (err) 1045 goto exit; 1046 1047 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1048 MBOX_DIR_PFAF_UP, 1); 1049 if (err) 1050 goto exit; 1051 1052 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1053 if (err) 1054 goto exit; 1055 1056 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1057 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1058 mutex_init(&mbox->lock); 1059 1060 return 0; 1061 exit: 1062 otx2_pfaf_mbox_destroy(pf); 1063 return err; 1064 } 1065 1066 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1067 { 1068 struct msg_req *msg; 1069 int err; 1070 1071 mutex_lock(&pf->mbox.lock); 1072 if (enable) 1073 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1074 else 1075 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1076 1077 if (!msg) { 1078 mutex_unlock(&pf->mbox.lock); 1079 return -ENOMEM; 1080 } 1081 1082 err = otx2_sync_mbox_msg(&pf->mbox); 1083 mutex_unlock(&pf->mbox.lock); 1084 return err; 1085 } 1086 1087 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1088 { 1089 struct msg_req *msg; 1090 int err; 1091 1092 mutex_lock(&pf->mbox.lock); 1093 if (enable) 1094 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1095 else 1096 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1097 1098 if (!msg) { 1099 mutex_unlock(&pf->mbox.lock); 1100 return -ENOMEM; 1101 } 1102 1103 err = otx2_sync_mbox_msg(&pf->mbox); 1104 mutex_unlock(&pf->mbox.lock); 1105 return err; 1106 } 1107 1108 int otx2_set_real_num_queues(struct net_device *netdev, 1109 int tx_queues, int rx_queues) 1110 { 1111 int err; 1112 1113 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1114 if (err) { 1115 netdev_err(netdev, 1116 "Failed to set no of Tx queues: %d\n", tx_queues); 1117 return err; 1118 } 1119 1120 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1121 if (err) 1122 netdev_err(netdev, 1123 "Failed to set no of Rx queues: %d\n", rx_queues); 1124 return err; 1125 } 1126 EXPORT_SYMBOL(otx2_set_real_num_queues); 1127 1128 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1129 { 1130 struct otx2_nic *pf = data; 1131 u64 val, *ptr; 1132 u64 qidx = 0; 1133 1134 /* CQ */ 1135 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1136 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1137 val = otx2_atomic64_add((qidx << 44), ptr); 1138 1139 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1140 (val & NIX_CQERRINT_BITS)); 1141 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1142 continue; 1143 1144 if (val & BIT_ULL(42)) { 1145 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1146 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1147 } else { 1148 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1149 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1150 qidx); 1151 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1152 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1153 qidx); 1154 } 1155 1156 schedule_work(&pf->reset_task); 1157 } 1158 1159 /* SQ */ 1160 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) { 1161 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1162 val = otx2_atomic64_add((qidx << 44), ptr); 1163 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1164 (val & NIX_SQINT_BITS)); 1165 1166 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42)))) 1167 continue; 1168 1169 if (val & BIT_ULL(42)) { 1170 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1171 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1172 } else { 1173 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) { 1174 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx", 1175 qidx, 1176 otx2_read64(pf, 1177 NIX_LF_SQ_OP_ERR_DBG)); 1178 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, 1179 BIT_ULL(44)); 1180 } 1181 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) { 1182 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n", 1183 qidx, 1184 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG)); 1185 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, 1186 BIT_ULL(44)); 1187 } 1188 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) { 1189 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx", 1190 qidx, 1191 otx2_read64(pf, 1192 NIX_LF_SEND_ERR_DBG)); 1193 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, 1194 BIT_ULL(44)); 1195 } 1196 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1197 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1198 qidx); 1199 } 1200 1201 schedule_work(&pf->reset_task); 1202 } 1203 1204 return IRQ_HANDLED; 1205 } 1206 1207 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1208 { 1209 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1210 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1211 int qidx = cq_poll->cint_idx; 1212 1213 /* Disable interrupts. 1214 * 1215 * Completion interrupts behave in a level-triggered interrupt 1216 * fashion, and hence have to be cleared only after it is serviced. 1217 */ 1218 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1219 1220 /* Schedule NAPI */ 1221 napi_schedule_irqoff(&cq_poll->napi); 1222 1223 return IRQ_HANDLED; 1224 } 1225 1226 static void otx2_disable_napi(struct otx2_nic *pf) 1227 { 1228 struct otx2_qset *qset = &pf->qset; 1229 struct otx2_cq_poll *cq_poll; 1230 int qidx; 1231 1232 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1233 cq_poll = &qset->napi[qidx]; 1234 napi_disable(&cq_poll->napi); 1235 netif_napi_del(&cq_poll->napi); 1236 } 1237 } 1238 1239 static void otx2_free_cq_res(struct otx2_nic *pf) 1240 { 1241 struct otx2_qset *qset = &pf->qset; 1242 struct otx2_cq_queue *cq; 1243 int qidx; 1244 1245 /* Disable CQs */ 1246 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1247 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1248 cq = &qset->cq[qidx]; 1249 qmem_free(pf->dev, cq->cqe); 1250 } 1251 } 1252 1253 static void otx2_free_sq_res(struct otx2_nic *pf) 1254 { 1255 struct otx2_qset *qset = &pf->qset; 1256 struct otx2_snd_queue *sq; 1257 int qidx; 1258 1259 /* Disable SQs */ 1260 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1261 /* Free SQB pointers */ 1262 otx2_sq_free_sqbs(pf); 1263 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) { 1264 sq = &qset->sq[qidx]; 1265 qmem_free(pf->dev, sq->sqe); 1266 qmem_free(pf->dev, sq->tso_hdrs); 1267 kfree(sq->sg); 1268 kfree(sq->sqb_ptrs); 1269 } 1270 } 1271 1272 static int otx2_init_hw_resources(struct otx2_nic *pf) 1273 { 1274 struct mbox *mbox = &pf->mbox; 1275 struct otx2_hw *hw = &pf->hw; 1276 struct msg_req *req; 1277 int err = 0, lvl; 1278 1279 /* Set required NPA LF's pool counts 1280 * Auras and Pools are used in a 1:1 mapping, 1281 * so, aura count = pool count. 1282 */ 1283 hw->rqpool_cnt = hw->rx_queues; 1284 hw->sqpool_cnt = hw->tx_queues; 1285 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1286 1287 /* Get the size of receive buffers to allocate */ 1288 pf->rbsize = RCV_FRAG_LEN(OTX2_HW_TIMESTAMP_LEN + pf->netdev->mtu + 1289 OTX2_ETH_HLEN); 1290 1291 mutex_lock(&mbox->lock); 1292 /* NPA init */ 1293 err = otx2_config_npa(pf); 1294 if (err) 1295 goto exit; 1296 1297 /* NIX init */ 1298 err = otx2_config_nix(pf); 1299 if (err) 1300 goto err_free_npa_lf; 1301 1302 /* Enable backpressure */ 1303 otx2_nix_config_bp(pf, true); 1304 1305 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1306 err = otx2_rq_aura_pool_init(pf); 1307 if (err) { 1308 mutex_unlock(&mbox->lock); 1309 goto err_free_nix_lf; 1310 } 1311 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1312 err = otx2_sq_aura_pool_init(pf); 1313 if (err) { 1314 mutex_unlock(&mbox->lock); 1315 goto err_free_rq_ptrs; 1316 } 1317 1318 err = otx2_txsch_alloc(pf); 1319 if (err) { 1320 mutex_unlock(&mbox->lock); 1321 goto err_free_sq_ptrs; 1322 } 1323 1324 err = otx2_config_nix_queues(pf); 1325 if (err) { 1326 mutex_unlock(&mbox->lock); 1327 goto err_free_txsch; 1328 } 1329 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1330 err = otx2_txschq_config(pf, lvl); 1331 if (err) { 1332 mutex_unlock(&mbox->lock); 1333 goto err_free_nix_queues; 1334 } 1335 } 1336 mutex_unlock(&mbox->lock); 1337 return err; 1338 1339 err_free_nix_queues: 1340 otx2_free_sq_res(pf); 1341 otx2_free_cq_res(pf); 1342 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1343 err_free_txsch: 1344 if (otx2_txschq_stop(pf)) 1345 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1346 err_free_sq_ptrs: 1347 otx2_sq_free_sqbs(pf); 1348 err_free_rq_ptrs: 1349 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1350 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1351 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1352 otx2_aura_pool_free(pf); 1353 err_free_nix_lf: 1354 mutex_lock(&mbox->lock); 1355 req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1356 if (req) { 1357 if (otx2_sync_mbox_msg(mbox)) 1358 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1359 } 1360 err_free_npa_lf: 1361 /* Reset NPA LF */ 1362 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1363 if (req) { 1364 if (otx2_sync_mbox_msg(mbox)) 1365 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1366 } 1367 exit: 1368 mutex_unlock(&mbox->lock); 1369 return err; 1370 } 1371 1372 static void otx2_free_hw_resources(struct otx2_nic *pf) 1373 { 1374 struct otx2_qset *qset = &pf->qset; 1375 struct mbox *mbox = &pf->mbox; 1376 struct otx2_cq_queue *cq; 1377 struct msg_req *req; 1378 int qidx, err; 1379 1380 /* Ensure all SQE are processed */ 1381 otx2_sqb_flush(pf); 1382 1383 /* Stop transmission */ 1384 err = otx2_txschq_stop(pf); 1385 if (err) 1386 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1387 1388 mutex_lock(&mbox->lock); 1389 /* Disable backpressure */ 1390 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1391 otx2_nix_config_bp(pf, false); 1392 mutex_unlock(&mbox->lock); 1393 1394 /* Disable RQs */ 1395 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1396 1397 /*Dequeue all CQEs */ 1398 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1399 cq = &qset->cq[qidx]; 1400 if (cq->cq_type == CQ_RX) 1401 otx2_cleanup_rx_cqes(pf, cq); 1402 else 1403 otx2_cleanup_tx_cqes(pf, cq); 1404 } 1405 1406 otx2_free_sq_res(pf); 1407 1408 /* Free RQ buffer pointers*/ 1409 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1410 1411 otx2_free_cq_res(pf); 1412 1413 mutex_lock(&mbox->lock); 1414 /* Reset NIX LF */ 1415 req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1416 if (req) { 1417 if (otx2_sync_mbox_msg(mbox)) 1418 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1419 } 1420 mutex_unlock(&mbox->lock); 1421 1422 /* Disable NPA Pool and Aura hw context */ 1423 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1424 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1425 otx2_aura_pool_free(pf); 1426 1427 mutex_lock(&mbox->lock); 1428 /* Reset NPA LF */ 1429 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1430 if (req) { 1431 if (otx2_sync_mbox_msg(mbox)) 1432 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1433 } 1434 mutex_unlock(&mbox->lock); 1435 } 1436 1437 int otx2_open(struct net_device *netdev) 1438 { 1439 struct otx2_nic *pf = netdev_priv(netdev); 1440 struct otx2_cq_poll *cq_poll = NULL; 1441 struct otx2_qset *qset = &pf->qset; 1442 int err = 0, qidx, vec; 1443 char *irq_name; 1444 1445 netif_carrier_off(netdev); 1446 1447 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tx_queues; 1448 /* RQ and SQs are mapped to different CQs, 1449 * so find out max CQ IRQs (i.e CINTs) needed. 1450 */ 1451 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1452 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1453 if (!qset->napi) 1454 return -ENOMEM; 1455 1456 /* CQ size of RQ */ 1457 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1458 /* CQ size of SQ */ 1459 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1460 1461 err = -ENOMEM; 1462 qset->cq = kcalloc(pf->qset.cq_cnt, 1463 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1464 if (!qset->cq) 1465 goto err_free_mem; 1466 1467 qset->sq = kcalloc(pf->hw.tx_queues, 1468 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1469 if (!qset->sq) 1470 goto err_free_mem; 1471 1472 qset->rq = kcalloc(pf->hw.rx_queues, 1473 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1474 if (!qset->rq) 1475 goto err_free_mem; 1476 1477 err = otx2_init_hw_resources(pf); 1478 if (err) 1479 goto err_free_mem; 1480 1481 /* Register NAPI handler */ 1482 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1483 cq_poll = &qset->napi[qidx]; 1484 cq_poll->cint_idx = qidx; 1485 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1486 * 'cq_ids[0]' points to RQ's CQ and 1487 * 'cq_ids[1]' points to SQ's CQ and 1488 */ 1489 cq_poll->cq_ids[CQ_RX] = 1490 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1491 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1492 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1493 cq_poll->dev = (void *)pf; 1494 netif_napi_add(netdev, &cq_poll->napi, 1495 otx2_napi_handler, NAPI_POLL_WEIGHT); 1496 napi_enable(&cq_poll->napi); 1497 } 1498 1499 /* Set maximum frame size allowed in HW */ 1500 err = otx2_hw_set_mtu(pf, netdev->mtu); 1501 if (err) 1502 goto err_disable_napi; 1503 1504 /* Initialize RSS */ 1505 err = otx2_rss_init(pf); 1506 if (err) 1507 goto err_disable_napi; 1508 1509 /* Register Queue IRQ handlers */ 1510 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1511 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1512 1513 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1514 1515 err = request_irq(pci_irq_vector(pf->pdev, vec), 1516 otx2_q_intr_handler, 0, irq_name, pf); 1517 if (err) { 1518 dev_err(pf->dev, 1519 "RVUPF%d: IRQ registration failed for QERR\n", 1520 rvu_get_pf(pf->pcifunc)); 1521 goto err_disable_napi; 1522 } 1523 1524 /* Enable QINT IRQ */ 1525 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1526 1527 /* Register CQ IRQ handlers */ 1528 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1529 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1530 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1531 1532 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1533 qidx); 1534 1535 err = request_irq(pci_irq_vector(pf->pdev, vec), 1536 otx2_cq_intr_handler, 0, irq_name, 1537 &qset->napi[qidx]); 1538 if (err) { 1539 dev_err(pf->dev, 1540 "RVUPF%d: IRQ registration failed for CQ%d\n", 1541 rvu_get_pf(pf->pcifunc), qidx); 1542 goto err_free_cints; 1543 } 1544 vec++; 1545 1546 otx2_config_irq_coalescing(pf, qidx); 1547 1548 /* Enable CQ IRQ */ 1549 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1550 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1551 } 1552 1553 otx2_set_cints_affinity(pf); 1554 1555 /* When reinitializing enable time stamping if it is enabled before */ 1556 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1557 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1558 otx2_config_hw_tx_tstamp(pf, true); 1559 } 1560 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1561 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1562 otx2_config_hw_rx_tstamp(pf, true); 1563 } 1564 1565 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1566 /* 'intf_down' may be checked on any cpu */ 1567 smp_wmb(); 1568 1569 /* we have already received link status notification */ 1570 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1571 otx2_handle_link_event(pf); 1572 1573 /* Restore pause frame settings */ 1574 otx2_config_pause_frm(pf); 1575 1576 err = otx2_rxtx_enable(pf, true); 1577 if (err) 1578 goto err_free_cints; 1579 1580 return 0; 1581 1582 err_free_cints: 1583 otx2_free_cints(pf, qidx); 1584 vec = pci_irq_vector(pf->pdev, 1585 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1586 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1587 synchronize_irq(vec); 1588 free_irq(vec, pf); 1589 err_disable_napi: 1590 otx2_disable_napi(pf); 1591 otx2_free_hw_resources(pf); 1592 err_free_mem: 1593 kfree(qset->sq); 1594 kfree(qset->cq); 1595 kfree(qset->rq); 1596 kfree(qset->napi); 1597 return err; 1598 } 1599 EXPORT_SYMBOL(otx2_open); 1600 1601 int otx2_stop(struct net_device *netdev) 1602 { 1603 struct otx2_nic *pf = netdev_priv(netdev); 1604 struct otx2_cq_poll *cq_poll = NULL; 1605 struct otx2_qset *qset = &pf->qset; 1606 int qidx, vec, wrk; 1607 1608 netif_carrier_off(netdev); 1609 netif_tx_stop_all_queues(netdev); 1610 1611 pf->flags |= OTX2_FLAG_INTF_DOWN; 1612 /* 'intf_down' may be checked on any cpu */ 1613 smp_wmb(); 1614 1615 /* First stop packet Rx/Tx */ 1616 otx2_rxtx_enable(pf, false); 1617 1618 /* Cleanup Queue IRQ */ 1619 vec = pci_irq_vector(pf->pdev, 1620 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1621 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1622 synchronize_irq(vec); 1623 free_irq(vec, pf); 1624 1625 /* Cleanup CQ NAPI and IRQ */ 1626 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1627 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1628 /* Disable interrupt */ 1629 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1630 1631 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1632 1633 cq_poll = &qset->napi[qidx]; 1634 napi_synchronize(&cq_poll->napi); 1635 vec++; 1636 } 1637 1638 netif_tx_disable(netdev); 1639 1640 otx2_free_hw_resources(pf); 1641 otx2_free_cints(pf, pf->hw.cint_cnt); 1642 otx2_disable_napi(pf); 1643 1644 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1645 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1646 1647 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1648 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1649 devm_kfree(pf->dev, pf->refill_wrk); 1650 1651 kfree(qset->sq); 1652 kfree(qset->cq); 1653 kfree(qset->rq); 1654 kfree(qset->napi); 1655 /* Do not clear RQ/SQ ringsize settings */ 1656 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0, 1657 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt)); 1658 return 0; 1659 } 1660 EXPORT_SYMBOL(otx2_stop); 1661 1662 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1663 { 1664 struct otx2_nic *pf = netdev_priv(netdev); 1665 int qidx = skb_get_queue_mapping(skb); 1666 struct otx2_snd_queue *sq; 1667 struct netdev_queue *txq; 1668 1669 /* Check for minimum and maximum packet length */ 1670 if (skb->len <= ETH_HLEN || 1671 (!skb_shinfo(skb)->gso_size && skb->len > pf->max_frs)) { 1672 dev_kfree_skb(skb); 1673 return NETDEV_TX_OK; 1674 } 1675 1676 sq = &pf->qset.sq[qidx]; 1677 txq = netdev_get_tx_queue(netdev, qidx); 1678 1679 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1680 netif_tx_stop_queue(txq); 1681 1682 /* Check again, incase SQBs got freed up */ 1683 smp_mb(); 1684 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1685 > sq->sqe_thresh) 1686 netif_tx_wake_queue(txq); 1687 1688 return NETDEV_TX_BUSY; 1689 } 1690 1691 return NETDEV_TX_OK; 1692 } 1693 1694 static void otx2_set_rx_mode(struct net_device *netdev) 1695 { 1696 struct otx2_nic *pf = netdev_priv(netdev); 1697 1698 queue_work(pf->otx2_wq, &pf->rx_mode_work); 1699 } 1700 1701 static void otx2_do_set_rx_mode(struct work_struct *work) 1702 { 1703 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 1704 struct net_device *netdev = pf->netdev; 1705 struct nix_rx_mode *req; 1706 1707 if (!(netdev->flags & IFF_UP)) 1708 return; 1709 1710 mutex_lock(&pf->mbox.lock); 1711 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1712 if (!req) { 1713 mutex_unlock(&pf->mbox.lock); 1714 return; 1715 } 1716 1717 req->mode = NIX_RX_MODE_UCAST; 1718 1719 /* We don't support MAC address filtering yet */ 1720 if (netdev->flags & IFF_PROMISC) 1721 req->mode |= NIX_RX_MODE_PROMISC; 1722 else if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1723 req->mode |= NIX_RX_MODE_ALLMULTI; 1724 1725 otx2_sync_mbox_msg(&pf->mbox); 1726 mutex_unlock(&pf->mbox.lock); 1727 } 1728 1729 static int otx2_set_features(struct net_device *netdev, 1730 netdev_features_t features) 1731 { 1732 netdev_features_t changed = features ^ netdev->features; 1733 struct otx2_nic *pf = netdev_priv(netdev); 1734 1735 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1736 return otx2_cgx_config_loopback(pf, 1737 features & NETIF_F_LOOPBACK); 1738 return 0; 1739 } 1740 1741 static void otx2_reset_task(struct work_struct *work) 1742 { 1743 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 1744 1745 if (!netif_running(pf->netdev)) 1746 return; 1747 1748 rtnl_lock(); 1749 otx2_stop(pf->netdev); 1750 pf->reset_count++; 1751 otx2_open(pf->netdev); 1752 netif_trans_update(pf->netdev); 1753 rtnl_unlock(); 1754 } 1755 1756 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 1757 { 1758 struct msg_req *req; 1759 int err; 1760 1761 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 1762 return 0; 1763 1764 mutex_lock(&pfvf->mbox.lock); 1765 if (enable) 1766 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 1767 else 1768 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 1769 if (!req) { 1770 mutex_unlock(&pfvf->mbox.lock); 1771 return -ENOMEM; 1772 } 1773 1774 err = otx2_sync_mbox_msg(&pfvf->mbox); 1775 if (err) { 1776 mutex_unlock(&pfvf->mbox.lock); 1777 return err; 1778 } 1779 1780 mutex_unlock(&pfvf->mbox.lock); 1781 if (enable) 1782 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 1783 else 1784 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1785 return 0; 1786 } 1787 1788 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 1789 { 1790 struct msg_req *req; 1791 int err; 1792 1793 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 1794 return 0; 1795 1796 mutex_lock(&pfvf->mbox.lock); 1797 if (enable) 1798 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 1799 else 1800 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 1801 if (!req) { 1802 mutex_unlock(&pfvf->mbox.lock); 1803 return -ENOMEM; 1804 } 1805 1806 err = otx2_sync_mbox_msg(&pfvf->mbox); 1807 if (err) { 1808 mutex_unlock(&pfvf->mbox.lock); 1809 return err; 1810 } 1811 1812 mutex_unlock(&pfvf->mbox.lock); 1813 if (enable) 1814 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 1815 else 1816 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1817 return 0; 1818 } 1819 1820 static int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 1821 { 1822 struct otx2_nic *pfvf = netdev_priv(netdev); 1823 struct hwtstamp_config config; 1824 1825 if (!pfvf->ptp) 1826 return -ENODEV; 1827 1828 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1829 return -EFAULT; 1830 1831 /* reserved for future extensions */ 1832 if (config.flags) 1833 return -EINVAL; 1834 1835 switch (config.tx_type) { 1836 case HWTSTAMP_TX_OFF: 1837 otx2_config_hw_tx_tstamp(pfvf, false); 1838 break; 1839 case HWTSTAMP_TX_ON: 1840 otx2_config_hw_tx_tstamp(pfvf, true); 1841 break; 1842 default: 1843 return -ERANGE; 1844 } 1845 1846 switch (config.rx_filter) { 1847 case HWTSTAMP_FILTER_NONE: 1848 otx2_config_hw_rx_tstamp(pfvf, false); 1849 break; 1850 case HWTSTAMP_FILTER_ALL: 1851 case HWTSTAMP_FILTER_SOME: 1852 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1853 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1854 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1855 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1856 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1857 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1858 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1859 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1860 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1861 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1862 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1863 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1864 otx2_config_hw_rx_tstamp(pfvf, true); 1865 config.rx_filter = HWTSTAMP_FILTER_ALL; 1866 break; 1867 default: 1868 return -ERANGE; 1869 } 1870 1871 memcpy(&pfvf->tstamp, &config, sizeof(config)); 1872 1873 return copy_to_user(ifr->ifr_data, &config, 1874 sizeof(config)) ? -EFAULT : 0; 1875 } 1876 1877 static int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 1878 { 1879 struct otx2_nic *pfvf = netdev_priv(netdev); 1880 struct hwtstamp_config *cfg = &pfvf->tstamp; 1881 1882 switch (cmd) { 1883 case SIOCSHWTSTAMP: 1884 return otx2_config_hwtstamp(netdev, req); 1885 case SIOCGHWTSTAMP: 1886 return copy_to_user(req->ifr_data, cfg, 1887 sizeof(*cfg)) ? -EFAULT : 0; 1888 default: 1889 return -EOPNOTSUPP; 1890 } 1891 } 1892 1893 static const struct net_device_ops otx2_netdev_ops = { 1894 .ndo_open = otx2_open, 1895 .ndo_stop = otx2_stop, 1896 .ndo_start_xmit = otx2_xmit, 1897 .ndo_set_mac_address = otx2_set_mac_address, 1898 .ndo_change_mtu = otx2_change_mtu, 1899 .ndo_set_rx_mode = otx2_set_rx_mode, 1900 .ndo_set_features = otx2_set_features, 1901 .ndo_tx_timeout = otx2_tx_timeout, 1902 .ndo_get_stats64 = otx2_get_stats64, 1903 .ndo_do_ioctl = otx2_ioctl, 1904 }; 1905 1906 static int otx2_wq_init(struct otx2_nic *pf) 1907 { 1908 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 1909 if (!pf->otx2_wq) 1910 return -ENOMEM; 1911 1912 INIT_WORK(&pf->rx_mode_work, otx2_do_set_rx_mode); 1913 INIT_WORK(&pf->reset_task, otx2_reset_task); 1914 return 0; 1915 } 1916 1917 static int otx2_check_pf_usable(struct otx2_nic *nic) 1918 { 1919 u64 rev; 1920 1921 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 1922 rev = (rev >> 12) & 0xFF; 1923 /* Check if AF has setup revision for RVUM block, 1924 * otherwise this driver probe should be deferred 1925 * until AF driver comes up. 1926 */ 1927 if (!rev) { 1928 dev_warn(nic->dev, 1929 "AF is not initialized, deferring probe\n"); 1930 return -EPROBE_DEFER; 1931 } 1932 return 0; 1933 } 1934 1935 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 1936 { 1937 struct otx2_hw *hw = &pf->hw; 1938 int num_vec, err; 1939 1940 /* NPA interrupts are inot registered, so alloc only 1941 * upto NIX vector offset. 1942 */ 1943 num_vec = hw->nix_msixoff; 1944 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 1945 1946 otx2_disable_mbox_intr(pf); 1947 pci_free_irq_vectors(hw->pdev); 1948 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 1949 if (err < 0) { 1950 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 1951 __func__, num_vec); 1952 return err; 1953 } 1954 1955 return otx2_register_mbox_intr(pf, false); 1956 } 1957 1958 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1959 { 1960 struct device *dev = &pdev->dev; 1961 struct net_device *netdev; 1962 struct otx2_nic *pf; 1963 struct otx2_hw *hw; 1964 int err, qcount; 1965 int num_vec; 1966 1967 err = pcim_enable_device(pdev); 1968 if (err) { 1969 dev_err(dev, "Failed to enable PCI device\n"); 1970 return err; 1971 } 1972 1973 err = pci_request_regions(pdev, DRV_NAME); 1974 if (err) { 1975 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1976 return err; 1977 } 1978 1979 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 1980 if (err) { 1981 dev_err(dev, "DMA mask config failed, abort\n"); 1982 goto err_release_regions; 1983 } 1984 1985 pci_set_master(pdev); 1986 1987 /* Set number of queues */ 1988 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 1989 1990 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 1991 if (!netdev) { 1992 err = -ENOMEM; 1993 goto err_release_regions; 1994 } 1995 1996 pci_set_drvdata(pdev, netdev); 1997 SET_NETDEV_DEV(netdev, &pdev->dev); 1998 pf = netdev_priv(netdev); 1999 pf->netdev = netdev; 2000 pf->pdev = pdev; 2001 pf->dev = dev; 2002 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2003 pf->flags |= OTX2_FLAG_INTF_DOWN; 2004 2005 hw = &pf->hw; 2006 hw->pdev = pdev; 2007 hw->rx_queues = qcount; 2008 hw->tx_queues = qcount; 2009 hw->max_queues = qcount; 2010 2011 num_vec = pci_msix_vec_count(pdev); 2012 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2013 GFP_KERNEL); 2014 if (!hw->irq_name) { 2015 err = -ENOMEM; 2016 goto err_free_netdev; 2017 } 2018 2019 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2020 sizeof(cpumask_var_t), GFP_KERNEL); 2021 if (!hw->affinity_mask) { 2022 err = -ENOMEM; 2023 goto err_free_netdev; 2024 } 2025 2026 /* Map CSRs */ 2027 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2028 if (!pf->reg_base) { 2029 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2030 err = -ENOMEM; 2031 goto err_free_netdev; 2032 } 2033 2034 err = otx2_check_pf_usable(pf); 2035 if (err) 2036 goto err_free_netdev; 2037 2038 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2039 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2040 if (err < 0) { 2041 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2042 __func__, num_vec); 2043 goto err_free_netdev; 2044 } 2045 2046 /* Init PF <=> AF mailbox stuff */ 2047 err = otx2_pfaf_mbox_init(pf); 2048 if (err) 2049 goto err_free_irq_vectors; 2050 2051 /* Register mailbox interrupt */ 2052 err = otx2_register_mbox_intr(pf, true); 2053 if (err) 2054 goto err_mbox_destroy; 2055 2056 /* Request AF to attach NPA and NIX LFs to this PF. 2057 * NIX and NPA LFs are needed for this PF to function as a NIC. 2058 */ 2059 err = otx2_attach_npa_nix(pf); 2060 if (err) 2061 goto err_disable_mbox_intr; 2062 2063 err = otx2_realloc_msix_vectors(pf); 2064 if (err) 2065 goto err_detach_rsrc; 2066 2067 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2068 if (err) 2069 goto err_detach_rsrc; 2070 2071 otx2_setup_dev_hw_settings(pf); 2072 2073 /* Assign default mac address */ 2074 otx2_get_mac_from_af(netdev); 2075 2076 /* Don't check for error. Proceed without ptp */ 2077 otx2_ptp_init(pf); 2078 2079 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2080 * HW allocates buffer pointer from stack and uses it for DMA'ing 2081 * ingress packet. In some scenarios HW can free back allocated buffer 2082 * pointers to pool. This makes it impossible for SW to maintain a 2083 * parallel list where physical addresses of buffer pointers (IOVAs) 2084 * given to HW can be saved for later reference. 2085 * 2086 * So the only way to convert Rx packet's buffer address is to use 2087 * IOMMU's iova_to_phys() handler which translates the address by 2088 * walking through the translation tables. 2089 */ 2090 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2091 2092 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2093 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2094 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6); 2095 netdev->features |= netdev->hw_features; 2096 2097 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2098 2099 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS; 2100 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2101 2102 netdev->netdev_ops = &otx2_netdev_ops; 2103 2104 /* MTU range: 64 - 9190 */ 2105 netdev->min_mtu = OTX2_MIN_MTU; 2106 netdev->max_mtu = OTX2_MAX_MTU; 2107 2108 err = register_netdev(netdev); 2109 if (err) { 2110 dev_err(dev, "Failed to register netdevice\n"); 2111 goto err_ptp_destroy; 2112 } 2113 2114 err = otx2_wq_init(pf); 2115 if (err) 2116 goto err_unreg_netdev; 2117 2118 otx2_set_ethtool_ops(netdev); 2119 2120 /* Enable link notifications */ 2121 otx2_cgx_config_linkevents(pf, true); 2122 2123 /* Enable pause frames by default */ 2124 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 2125 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 2126 2127 return 0; 2128 2129 err_unreg_netdev: 2130 unregister_netdev(netdev); 2131 err_ptp_destroy: 2132 otx2_ptp_destroy(pf); 2133 err_detach_rsrc: 2134 otx2_detach_resources(&pf->mbox); 2135 err_disable_mbox_intr: 2136 otx2_disable_mbox_intr(pf); 2137 err_mbox_destroy: 2138 otx2_pfaf_mbox_destroy(pf); 2139 err_free_irq_vectors: 2140 pci_free_irq_vectors(hw->pdev); 2141 err_free_netdev: 2142 pci_set_drvdata(pdev, NULL); 2143 free_netdev(netdev); 2144 err_release_regions: 2145 pci_release_regions(pdev); 2146 return err; 2147 } 2148 2149 static void otx2_vf_link_event_task(struct work_struct *work) 2150 { 2151 struct otx2_vf_config *config; 2152 struct cgx_link_info_msg *req; 2153 struct mbox_msghdr *msghdr; 2154 struct otx2_nic *pf; 2155 int vf_idx; 2156 2157 config = container_of(work, struct otx2_vf_config, 2158 link_event_work.work); 2159 vf_idx = config - config->pf->vf_configs; 2160 pf = config->pf; 2161 2162 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2163 sizeof(*req), sizeof(struct msg_rsp)); 2164 if (!msghdr) { 2165 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2166 return; 2167 } 2168 2169 req = (struct cgx_link_info_msg *)msghdr; 2170 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2171 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2172 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2173 2174 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2175 } 2176 2177 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2178 { 2179 struct net_device *netdev = pci_get_drvdata(pdev); 2180 struct otx2_nic *pf = netdev_priv(netdev); 2181 int ret, i; 2182 2183 /* Init PF <=> VF mailbox stuff */ 2184 ret = otx2_pfvf_mbox_init(pf, numvfs); 2185 if (ret) 2186 return ret; 2187 2188 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 2189 if (ret) 2190 goto free_mbox; 2191 2192 pf->vf_configs = kcalloc(numvfs, sizeof(struct otx2_vf_config), 2193 GFP_KERNEL); 2194 if (!pf->vf_configs) { 2195 ret = -ENOMEM; 2196 goto free_intr; 2197 } 2198 2199 for (i = 0; i < numvfs; i++) { 2200 pf->vf_configs[i].pf = pf; 2201 pf->vf_configs[i].intf_down = true; 2202 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2203 otx2_vf_link_event_task); 2204 } 2205 2206 ret = otx2_pf_flr_init(pf, numvfs); 2207 if (ret) 2208 goto free_configs; 2209 2210 ret = otx2_register_flr_me_intr(pf, numvfs); 2211 if (ret) 2212 goto free_flr; 2213 2214 ret = pci_enable_sriov(pdev, numvfs); 2215 if (ret) 2216 goto free_flr_intr; 2217 2218 return numvfs; 2219 free_flr_intr: 2220 otx2_disable_flr_me_intr(pf); 2221 free_flr: 2222 otx2_flr_wq_destroy(pf); 2223 free_configs: 2224 kfree(pf->vf_configs); 2225 free_intr: 2226 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2227 free_mbox: 2228 otx2_pfvf_mbox_destroy(pf); 2229 return ret; 2230 } 2231 2232 static int otx2_sriov_disable(struct pci_dev *pdev) 2233 { 2234 struct net_device *netdev = pci_get_drvdata(pdev); 2235 struct otx2_nic *pf = netdev_priv(netdev); 2236 int numvfs = pci_num_vf(pdev); 2237 int i; 2238 2239 if (!numvfs) 2240 return 0; 2241 2242 pci_disable_sriov(pdev); 2243 2244 for (i = 0; i < pci_num_vf(pdev); i++) 2245 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2246 kfree(pf->vf_configs); 2247 2248 otx2_disable_flr_me_intr(pf); 2249 otx2_flr_wq_destroy(pf); 2250 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2251 otx2_pfvf_mbox_destroy(pf); 2252 2253 return 0; 2254 } 2255 2256 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 2257 { 2258 if (numvfs == 0) 2259 return otx2_sriov_disable(pdev); 2260 else 2261 return otx2_sriov_enable(pdev, numvfs); 2262 } 2263 2264 static void otx2_remove(struct pci_dev *pdev) 2265 { 2266 struct net_device *netdev = pci_get_drvdata(pdev); 2267 struct otx2_nic *pf; 2268 2269 if (!netdev) 2270 return; 2271 2272 pf = netdev_priv(netdev); 2273 2274 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 2275 otx2_config_hw_tx_tstamp(pf, false); 2276 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 2277 otx2_config_hw_rx_tstamp(pf, false); 2278 2279 cancel_work_sync(&pf->reset_task); 2280 /* Disable link notifications */ 2281 otx2_cgx_config_linkevents(pf, false); 2282 2283 unregister_netdev(netdev); 2284 otx2_sriov_disable(pf->pdev); 2285 if (pf->otx2_wq) 2286 destroy_workqueue(pf->otx2_wq); 2287 2288 otx2_ptp_destroy(pf); 2289 otx2_detach_resources(&pf->mbox); 2290 otx2_disable_mbox_intr(pf); 2291 otx2_pfaf_mbox_destroy(pf); 2292 pci_free_irq_vectors(pf->pdev); 2293 pci_set_drvdata(pdev, NULL); 2294 free_netdev(netdev); 2295 2296 pci_release_regions(pdev); 2297 } 2298 2299 static struct pci_driver otx2_pf_driver = { 2300 .name = DRV_NAME, 2301 .id_table = otx2_pf_id_table, 2302 .probe = otx2_probe, 2303 .shutdown = otx2_remove, 2304 .remove = otx2_remove, 2305 .sriov_configure = otx2_sriov_configure 2306 }; 2307 2308 static int __init otx2_rvupf_init_module(void) 2309 { 2310 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2311 2312 return pci_register_driver(&otx2_pf_driver); 2313 } 2314 2315 static void __exit otx2_rvupf_cleanup_module(void) 2316 { 2317 pci_unregister_driver(&otx2_pf_driver); 2318 } 2319 2320 module_init(otx2_rvupf_init_module); 2321 module_exit(otx2_rvupf_cleanup_module); 2322