1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 #include <linux/bitfield.h> 19 #include <net/page_pool/types.h> 20 21 #include "otx2_reg.h" 22 #include "otx2_common.h" 23 #include "otx2_txrx.h" 24 #include "otx2_struct.h" 25 #include "otx2_ptp.h" 26 #include "cn10k.h" 27 #include "qos.h" 28 #include <rvu_trace.h> 29 #include "cn10k_ipsec.h" 30 31 #define DRV_NAME "rvu_nicpf" 32 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 33 34 /* Supported devices */ 35 static const struct pci_device_id otx2_pf_id_table[] = { 36 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 37 { 0, } /* end of table */ 38 }; 39 40 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 41 MODULE_DESCRIPTION(DRV_STRING); 42 MODULE_LICENSE("GPL v2"); 43 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 44 45 static void otx2_vf_link_event_task(struct work_struct *work); 46 47 enum { 48 TYPE_PFAF, 49 TYPE_PFVF, 50 }; 51 52 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 53 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 54 55 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 56 { 57 struct otx2_nic *pf = netdev_priv(netdev); 58 bool if_up = netif_running(netdev); 59 int err = 0; 60 61 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 62 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 63 netdev->mtu); 64 return -EINVAL; 65 } 66 if (if_up) 67 otx2_stop(netdev); 68 69 netdev_info(netdev, "Changing MTU from %d to %d\n", 70 netdev->mtu, new_mtu); 71 WRITE_ONCE(netdev->mtu, new_mtu); 72 73 if (if_up) 74 err = otx2_open(netdev); 75 76 return err; 77 } 78 79 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 80 { 81 int irq, vfs = pf->total_vfs; 82 83 /* Disable VFs ME interrupts */ 84 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 85 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 86 free_irq(irq, pf); 87 88 /* Disable VFs FLR interrupts */ 89 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 90 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 91 free_irq(irq, pf); 92 93 if (vfs <= 64) 94 return; 95 96 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 97 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 98 free_irq(irq, pf); 99 100 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 101 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 102 free_irq(irq, pf); 103 } 104 105 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 106 { 107 if (!pf->flr_wq) 108 return; 109 destroy_workqueue(pf->flr_wq); 110 pf->flr_wq = NULL; 111 devm_kfree(pf->dev, pf->flr_wrk); 112 } 113 114 static void otx2_flr_handler(struct work_struct *work) 115 { 116 struct flr_work *flrwork = container_of(work, struct flr_work, work); 117 struct otx2_nic *pf = flrwork->pf; 118 struct mbox *mbox = &pf->mbox; 119 struct msg_req *req; 120 int vf, reg = 0; 121 122 vf = flrwork - pf->flr_wrk; 123 124 mutex_lock(&mbox->lock); 125 req = otx2_mbox_alloc_msg_vf_flr(mbox); 126 if (!req) { 127 mutex_unlock(&mbox->lock); 128 return; 129 } 130 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 131 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 132 133 if (!otx2_sync_mbox_msg(&pf->mbox)) { 134 if (vf >= 64) { 135 reg = 1; 136 vf = vf - 64; 137 } 138 /* clear transcation pending bit */ 139 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 140 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 141 } 142 143 mutex_unlock(&mbox->lock); 144 } 145 146 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 147 { 148 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 149 int reg, dev, vf, start_vf, num_reg = 1; 150 u64 intr; 151 152 if (pf->total_vfs > 64) 153 num_reg = 2; 154 155 for (reg = 0; reg < num_reg; reg++) { 156 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 157 if (!intr) 158 continue; 159 start_vf = 64 * reg; 160 for (vf = 0; vf < 64; vf++) { 161 if (!(intr & BIT_ULL(vf))) 162 continue; 163 dev = vf + start_vf; 164 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 165 /* Clear interrupt */ 166 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 167 /* Disable the interrupt */ 168 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 169 BIT_ULL(vf)); 170 } 171 } 172 return IRQ_HANDLED; 173 } 174 175 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 176 { 177 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 178 int vf, reg, num_reg = 1; 179 u64 intr; 180 181 if (pf->total_vfs > 64) 182 num_reg = 2; 183 184 for (reg = 0; reg < num_reg; reg++) { 185 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 186 if (!intr) 187 continue; 188 for (vf = 0; vf < 64; vf++) { 189 if (!(intr & BIT_ULL(vf))) 190 continue; 191 /* clear trpend bit */ 192 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 193 /* clear interrupt */ 194 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 195 } 196 } 197 return IRQ_HANDLED; 198 } 199 200 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 201 { 202 struct otx2_hw *hw = &pf->hw; 203 char *irq_name; 204 int ret; 205 206 /* Register ME interrupt handler*/ 207 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 208 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 209 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 210 otx2_pf_me_intr_handler, 0, irq_name, pf); 211 if (ret) { 212 dev_err(pf->dev, 213 "RVUPF: IRQ registration failed for ME0\n"); 214 } 215 216 /* Register FLR interrupt handler */ 217 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 218 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 219 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 220 otx2_pf_flr_intr_handler, 0, irq_name, pf); 221 if (ret) { 222 dev_err(pf->dev, 223 "RVUPF: IRQ registration failed for FLR0\n"); 224 return ret; 225 } 226 227 if (numvfs > 64) { 228 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 229 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 230 rvu_get_pf(pf->pcifunc)); 231 ret = request_irq(pci_irq_vector 232 (pf->pdev, RVU_PF_INT_VEC_VFME1), 233 otx2_pf_me_intr_handler, 0, irq_name, pf); 234 if (ret) { 235 dev_err(pf->dev, 236 "RVUPF: IRQ registration failed for ME1\n"); 237 } 238 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 239 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 240 rvu_get_pf(pf->pcifunc)); 241 ret = request_irq(pci_irq_vector 242 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 243 otx2_pf_flr_intr_handler, 0, irq_name, pf); 244 if (ret) { 245 dev_err(pf->dev, 246 "RVUPF: IRQ registration failed for FLR1\n"); 247 return ret; 248 } 249 } 250 251 /* Enable ME interrupt for all VFs*/ 252 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 253 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 254 255 /* Enable FLR interrupt for all VFs*/ 256 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 257 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 258 259 if (numvfs > 64) { 260 numvfs -= 64; 261 262 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 263 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 264 INTR_MASK(numvfs)); 265 266 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 267 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 268 INTR_MASK(numvfs)); 269 } 270 return 0; 271 } 272 273 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 274 { 275 int vf; 276 277 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI); 278 if (!pf->flr_wq) 279 return -ENOMEM; 280 281 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 282 sizeof(struct flr_work), GFP_KERNEL); 283 if (!pf->flr_wrk) { 284 destroy_workqueue(pf->flr_wq); 285 return -ENOMEM; 286 } 287 288 for (vf = 0; vf < num_vfs; vf++) { 289 pf->flr_wrk[vf].pf = pf; 290 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 291 } 292 293 return 0; 294 } 295 296 static void otx2_queue_vf_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 297 int first, int mdevs, u64 intr) 298 { 299 struct otx2_mbox_dev *mdev; 300 struct otx2_mbox *mbox; 301 struct mbox_hdr *hdr; 302 int i; 303 304 for (i = first; i < mdevs; i++) { 305 /* start from 0 */ 306 if (!(intr & BIT_ULL(i - first))) 307 continue; 308 309 mbox = &mw->mbox; 310 mdev = &mbox->dev[i]; 311 hdr = mdev->mbase + mbox->rx_start; 312 /* The hdr->num_msgs is set to zero immediately in the interrupt 313 * handler to ensure that it holds a correct value next time 314 * when the interrupt handler is called. pf->mw[i].num_msgs 315 * holds the data for use in otx2_pfvf_mbox_handler and 316 * pf->mw[i].up_num_msgs holds the data for use in 317 * otx2_pfvf_mbox_up_handler. 318 */ 319 if (hdr->num_msgs) { 320 mw[i].num_msgs = hdr->num_msgs; 321 hdr->num_msgs = 0; 322 queue_work(mbox_wq, &mw[i].mbox_wrk); 323 } 324 325 mbox = &mw->mbox_up; 326 mdev = &mbox->dev[i]; 327 hdr = mdev->mbase + mbox->rx_start; 328 if (hdr->num_msgs) { 329 mw[i].up_num_msgs = hdr->num_msgs; 330 hdr->num_msgs = 0; 331 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 332 } 333 } 334 } 335 336 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 337 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 338 int devid) 339 { 340 struct otx2_mbox_dev *src_mdev = mdev; 341 int offset; 342 343 /* Msgs are already copied, trigger VF's mbox irq */ 344 smp_wmb(); 345 346 otx2_mbox_wait_for_zero(pfvf_mbox, devid); 347 348 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 349 writeq(MBOX_DOWN_MSG, (void __iomem *)pfvf_mbox->reg_base + offset); 350 351 /* Restore VF's mbox bounce buffer region address */ 352 src_mdev->mbase = bbuf_base; 353 } 354 355 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 356 struct otx2_mbox *src_mbox, 357 int dir, int vf, int num_msgs) 358 { 359 struct otx2_mbox_dev *src_mdev, *dst_mdev; 360 struct mbox_hdr *mbox_hdr; 361 struct mbox_hdr *req_hdr; 362 struct mbox *dst_mbox; 363 int dst_size, err; 364 365 if (dir == MBOX_DIR_PFAF) { 366 /* Set VF's mailbox memory as PF's bounce buffer memory, so 367 * that explicit copying of VF's msgs to PF=>AF mbox region 368 * and AF=>PF responses to VF's mbox region can be avoided. 369 */ 370 src_mdev = &src_mbox->dev[vf]; 371 mbox_hdr = src_mbox->hwbase + 372 src_mbox->rx_start + (vf * MBOX_SIZE); 373 374 dst_mbox = &pf->mbox; 375 dst_size = dst_mbox->mbox.tx_size - 376 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 377 /* Check if msgs fit into destination area and has valid size */ 378 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 379 return -EINVAL; 380 381 dst_mdev = &dst_mbox->mbox.dev[0]; 382 383 mutex_lock(&pf->mbox.lock); 384 dst_mdev->mbase = src_mdev->mbase; 385 dst_mdev->msg_size = mbox_hdr->msg_size; 386 dst_mdev->num_msgs = num_msgs; 387 err = otx2_sync_mbox_msg(dst_mbox); 388 /* Error code -EIO indicate there is a communication failure 389 * to the AF. Rest of the error codes indicate that AF processed 390 * VF messages and set the error codes in response messages 391 * (if any) so simply forward responses to VF. 392 */ 393 if (err == -EIO) { 394 dev_warn(pf->dev, 395 "AF not responding to VF%d messages\n", vf); 396 /* restore PF mbase and exit */ 397 dst_mdev->mbase = pf->mbox.bbuf_base; 398 mutex_unlock(&pf->mbox.lock); 399 return err; 400 } 401 /* At this point, all the VF messages sent to AF are acked 402 * with proper responses and responses are copied to VF 403 * mailbox hence raise interrupt to VF. 404 */ 405 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 406 dst_mbox->mbox.rx_start); 407 req_hdr->num_msgs = num_msgs; 408 409 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 410 pf->mbox.bbuf_base, vf); 411 mutex_unlock(&pf->mbox.lock); 412 } else if (dir == MBOX_DIR_PFVF_UP) { 413 src_mdev = &src_mbox->dev[0]; 414 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 415 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 416 src_mbox->rx_start); 417 req_hdr->num_msgs = num_msgs; 418 419 dst_mbox = &pf->mbox_pfvf[0]; 420 dst_size = dst_mbox->mbox_up.tx_size - 421 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 422 /* Check if msgs fit into destination area */ 423 if (mbox_hdr->msg_size > dst_size) 424 return -EINVAL; 425 426 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 427 dst_mdev->mbase = src_mdev->mbase; 428 dst_mdev->msg_size = mbox_hdr->msg_size; 429 dst_mdev->num_msgs = mbox_hdr->num_msgs; 430 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 431 if (err) { 432 dev_warn(pf->dev, 433 "VF%d is not responding to mailbox\n", vf); 434 return err; 435 } 436 } else if (dir == MBOX_DIR_VFPF_UP) { 437 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 438 src_mbox->rx_start); 439 req_hdr->num_msgs = num_msgs; 440 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 441 &pf->mbox.mbox_up, 442 pf->mbox_pfvf[vf].bbuf_base, 443 0); 444 } 445 446 return 0; 447 } 448 449 static void otx2_pfvf_mbox_handler(struct work_struct *work) 450 { 451 struct mbox_msghdr *msg = NULL; 452 int offset, vf_idx, id, err; 453 struct otx2_mbox_dev *mdev; 454 struct otx2_mbox *mbox; 455 struct mbox *vf_mbox; 456 struct otx2_nic *pf; 457 458 vf_mbox = container_of(work, struct mbox, mbox_wrk); 459 pf = vf_mbox->pfvf; 460 vf_idx = vf_mbox - pf->mbox_pfvf; 461 462 mbox = &pf->mbox_pfvf[0].mbox; 463 mdev = &mbox->dev[vf_idx]; 464 465 offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 466 467 for (id = 0; id < vf_mbox->num_msgs; id++) { 468 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 469 offset); 470 471 if (msg->sig != OTX2_MBOX_REQ_SIG) 472 goto inval_msg; 473 474 /* Set VF's number in each of the msg */ 475 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 476 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 477 offset = msg->next_msgoff; 478 } 479 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 480 vf_mbox->num_msgs); 481 if (err) 482 goto inval_msg; 483 return; 484 485 inval_msg: 486 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 487 otx2_mbox_msg_send(mbox, vf_idx); 488 } 489 490 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 491 { 492 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 493 struct otx2_nic *pf = vf_mbox->pfvf; 494 struct otx2_mbox_dev *mdev; 495 int offset, id, vf_idx = 0; 496 struct mbox_msghdr *msg; 497 struct otx2_mbox *mbox; 498 499 vf_idx = vf_mbox - pf->mbox_pfvf; 500 mbox = &pf->mbox_pfvf[0].mbox_up; 501 mdev = &mbox->dev[vf_idx]; 502 503 offset = mbox->rx_start + ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 504 505 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 506 msg = mdev->mbase + offset; 507 508 if (msg->id >= MBOX_MSG_MAX) { 509 dev_err(pf->dev, 510 "Mbox msg with unknown ID 0x%x\n", msg->id); 511 goto end; 512 } 513 514 if (msg->sig != OTX2_MBOX_RSP_SIG) { 515 dev_err(pf->dev, 516 "Mbox msg with wrong signature %x, ID 0x%x\n", 517 msg->sig, msg->id); 518 goto end; 519 } 520 521 switch (msg->id) { 522 case MBOX_MSG_CGX_LINK_EVENT: 523 case MBOX_MSG_REP_EVENT_UP_NOTIFY: 524 break; 525 default: 526 if (msg->rc) 527 dev_err(pf->dev, 528 "Mbox msg response has err %d, ID 0x%x\n", 529 msg->rc, msg->id); 530 break; 531 } 532 533 end: 534 offset = mbox->rx_start + msg->next_msgoff; 535 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 536 __otx2_mbox_reset(mbox, vf_idx); 537 mdev->msgs_acked++; 538 } 539 } 540 541 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 542 { 543 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 544 int vfs = pf->total_vfs; 545 struct mbox *mbox; 546 u64 intr; 547 548 mbox = pf->mbox_pfvf; 549 /* Handle VF interrupts */ 550 if (vfs > 64) { 551 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 552 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 553 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr); 554 if (intr) 555 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 556 vfs = 64; 557 } 558 559 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 560 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 561 562 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr); 563 564 if (intr) 565 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 566 567 return IRQ_HANDLED; 568 } 569 570 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 571 { 572 void __iomem *hwbase; 573 struct mbox *mbox; 574 int err, vf; 575 u64 base; 576 577 if (!numvfs) 578 return -EINVAL; 579 580 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 581 sizeof(struct mbox), GFP_KERNEL); 582 if (!pf->mbox_pfvf) 583 return -ENOMEM; 584 585 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 586 WQ_UNBOUND | WQ_HIGHPRI | 587 WQ_MEM_RECLAIM, 0); 588 if (!pf->mbox_pfvf_wq) 589 return -ENOMEM; 590 591 /* On CN10K platform, PF <-> VF mailbox region follows after 592 * PF <-> AF mailbox region. 593 */ 594 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 595 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 596 MBOX_SIZE; 597 else 598 base = readq((void __iomem *)((u64)pf->reg_base + 599 RVU_PF_VF_BAR4_ADDR)); 600 601 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 602 if (!hwbase) { 603 err = -ENOMEM; 604 goto free_wq; 605 } 606 607 mbox = &pf->mbox_pfvf[0]; 608 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 609 MBOX_DIR_PFVF, numvfs); 610 if (err) 611 goto free_iomem; 612 613 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 614 MBOX_DIR_PFVF_UP, numvfs); 615 if (err) 616 goto free_iomem; 617 618 for (vf = 0; vf < numvfs; vf++) { 619 mbox->pfvf = pf; 620 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 621 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 622 mbox++; 623 } 624 625 return 0; 626 627 free_iomem: 628 if (hwbase) 629 iounmap(hwbase); 630 free_wq: 631 destroy_workqueue(pf->mbox_pfvf_wq); 632 return err; 633 } 634 635 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 636 { 637 struct mbox *mbox = &pf->mbox_pfvf[0]; 638 639 if (!mbox) 640 return; 641 642 if (pf->mbox_pfvf_wq) { 643 destroy_workqueue(pf->mbox_pfvf_wq); 644 pf->mbox_pfvf_wq = NULL; 645 } 646 647 if (mbox->mbox.hwbase) 648 iounmap(mbox->mbox.hwbase); 649 650 otx2_mbox_destroy(&mbox->mbox); 651 } 652 653 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 654 { 655 /* Clear PF <=> VF mailbox IRQ */ 656 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 657 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 658 659 /* Enable PF <=> VF mailbox IRQ */ 660 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 661 if (numvfs > 64) { 662 numvfs -= 64; 663 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 664 INTR_MASK(numvfs)); 665 } 666 } 667 668 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 669 { 670 int vector; 671 672 /* Disable PF <=> VF mailbox IRQ */ 673 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 674 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 675 676 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 677 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 678 free_irq(vector, pf); 679 680 if (numvfs > 64) { 681 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 682 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 683 free_irq(vector, pf); 684 } 685 } 686 687 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 688 { 689 struct otx2_hw *hw = &pf->hw; 690 char *irq_name; 691 int err; 692 693 /* Register MBOX0 interrupt handler */ 694 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 695 if (pf->pcifunc) 696 snprintf(irq_name, NAME_SIZE, 697 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 698 else 699 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 700 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 701 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 702 if (err) { 703 dev_err(pf->dev, 704 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 705 return err; 706 } 707 708 if (numvfs > 64) { 709 /* Register MBOX1 interrupt handler */ 710 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 711 if (pf->pcifunc) 712 snprintf(irq_name, NAME_SIZE, 713 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 714 else 715 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 716 err = request_irq(pci_irq_vector(pf->pdev, 717 RVU_PF_INT_VEC_VFPF_MBOX1), 718 otx2_pfvf_mbox_intr_handler, 719 0, irq_name, pf); 720 if (err) { 721 dev_err(pf->dev, 722 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 723 return err; 724 } 725 } 726 727 otx2_enable_pfvf_mbox_intr(pf, numvfs); 728 729 return 0; 730 } 731 732 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 733 struct mbox_msghdr *msg) 734 { 735 int devid; 736 737 if (msg->id >= MBOX_MSG_MAX) { 738 dev_err(pf->dev, 739 "Mbox msg with unknown ID 0x%x\n", msg->id); 740 return; 741 } 742 743 if (msg->sig != OTX2_MBOX_RSP_SIG) { 744 dev_err(pf->dev, 745 "Mbox msg with wrong signature %x, ID 0x%x\n", 746 msg->sig, msg->id); 747 return; 748 } 749 750 /* message response heading VF */ 751 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 752 if (devid) { 753 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 754 struct delayed_work *dwork; 755 756 switch (msg->id) { 757 case MBOX_MSG_NIX_LF_START_RX: 758 config->intf_down = false; 759 dwork = &config->link_event_work; 760 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 761 break; 762 case MBOX_MSG_NIX_LF_STOP_RX: 763 config->intf_down = true; 764 break; 765 } 766 767 return; 768 } 769 770 switch (msg->id) { 771 case MBOX_MSG_READY: 772 pf->pcifunc = msg->pcifunc; 773 break; 774 case MBOX_MSG_MSIX_OFFSET: 775 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 776 break; 777 case MBOX_MSG_NPA_LF_ALLOC: 778 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 779 break; 780 case MBOX_MSG_NIX_LF_ALLOC: 781 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 782 break; 783 case MBOX_MSG_NIX_BP_ENABLE: 784 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 785 break; 786 case MBOX_MSG_CGX_STATS: 787 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 788 break; 789 case MBOX_MSG_CGX_FEC_STATS: 790 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 791 break; 792 default: 793 if (msg->rc) 794 dev_err(pf->dev, 795 "Mbox msg response has err %d, ID 0x%x\n", 796 msg->rc, msg->id); 797 break; 798 } 799 } 800 801 static void otx2_pfaf_mbox_handler(struct work_struct *work) 802 { 803 struct otx2_mbox_dev *mdev; 804 struct mbox_hdr *rsp_hdr; 805 struct mbox_msghdr *msg; 806 struct otx2_mbox *mbox; 807 struct mbox *af_mbox; 808 struct otx2_nic *pf; 809 int offset, id; 810 u16 num_msgs; 811 812 af_mbox = container_of(work, struct mbox, mbox_wrk); 813 mbox = &af_mbox->mbox; 814 mdev = &mbox->dev[0]; 815 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 816 num_msgs = rsp_hdr->num_msgs; 817 818 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 819 pf = af_mbox->pfvf; 820 821 for (id = 0; id < num_msgs; id++) { 822 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 823 otx2_process_pfaf_mbox_msg(pf, msg); 824 offset = mbox->rx_start + msg->next_msgoff; 825 if (mdev->msgs_acked == (num_msgs - 1)) 826 __otx2_mbox_reset(mbox, 0); 827 mdev->msgs_acked++; 828 } 829 830 } 831 832 static void otx2_handle_link_event(struct otx2_nic *pf) 833 { 834 struct cgx_link_user_info *linfo = &pf->linfo; 835 struct net_device *netdev = pf->netdev; 836 837 if (pf->flags & OTX2_FLAG_PORT_UP) 838 return; 839 840 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 841 linfo->link_up ? "UP" : "DOWN", linfo->speed, 842 linfo->full_duplex ? "Full" : "Half"); 843 if (linfo->link_up) { 844 netif_carrier_on(netdev); 845 netif_tx_start_all_queues(netdev); 846 } else { 847 netif_tx_stop_all_queues(netdev); 848 netif_carrier_off(netdev); 849 } 850 } 851 852 static int otx2_mbox_up_handler_rep_event_up_notify(struct otx2_nic *pf, 853 struct rep_event *info, 854 struct msg_rsp *rsp) 855 { 856 struct net_device *netdev = pf->netdev; 857 858 if (info->event == RVU_EVENT_MTU_CHANGE) { 859 netdev->mtu = info->evt_data.mtu; 860 return 0; 861 } 862 863 if (info->event == RVU_EVENT_PORT_STATE) { 864 if (info->evt_data.port_state) { 865 pf->flags |= OTX2_FLAG_PORT_UP; 866 netif_carrier_on(netdev); 867 netif_tx_start_all_queues(netdev); 868 } else { 869 pf->flags &= ~OTX2_FLAG_PORT_UP; 870 netif_tx_stop_all_queues(netdev); 871 netif_carrier_off(netdev); 872 } 873 return 0; 874 } 875 #ifdef CONFIG_RVU_ESWITCH 876 rvu_event_up_notify(pf, info); 877 #endif 878 return 0; 879 } 880 881 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 882 struct mcs_intr_info *event, 883 struct msg_rsp *rsp) 884 { 885 cn10k_handle_mcs_event(pf, event); 886 887 return 0; 888 } 889 890 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 891 struct cgx_link_info_msg *msg, 892 struct msg_rsp *rsp) 893 { 894 int i; 895 896 /* Copy the link info sent by AF */ 897 pf->linfo = msg->link_info; 898 899 /* notify VFs about link event */ 900 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 901 struct otx2_vf_config *config = &pf->vf_configs[i]; 902 struct delayed_work *dwork = &config->link_event_work; 903 904 if (config->intf_down) 905 continue; 906 907 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 908 } 909 910 /* interface has not been fully configured yet */ 911 if (pf->flags & OTX2_FLAG_INTF_DOWN) 912 return 0; 913 914 otx2_handle_link_event(pf); 915 return 0; 916 } 917 918 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 919 struct mbox_msghdr *req) 920 { 921 /* Check if valid, if not reply with a invalid msg */ 922 if (req->sig != OTX2_MBOX_REQ_SIG) { 923 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 924 return -ENODEV; 925 } 926 927 switch (req->id) { 928 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 929 case _id: { \ 930 struct _rsp_type *rsp; \ 931 int err; \ 932 \ 933 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 934 &pf->mbox.mbox_up, 0, \ 935 sizeof(struct _rsp_type)); \ 936 if (!rsp) \ 937 return -ENOMEM; \ 938 \ 939 rsp->hdr.id = _id; \ 940 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 941 rsp->hdr.pcifunc = 0; \ 942 rsp->hdr.rc = 0; \ 943 \ 944 err = otx2_mbox_up_handler_ ## _fn_name( \ 945 pf, (struct _req_type *)req, rsp); \ 946 return err; \ 947 } 948 MBOX_UP_CGX_MESSAGES 949 MBOX_UP_MCS_MESSAGES 950 MBOX_UP_REP_MESSAGES 951 #undef M 952 break; 953 default: 954 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 955 return -ENODEV; 956 } 957 return 0; 958 } 959 960 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 961 { 962 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 963 struct otx2_mbox *mbox = &af_mbox->mbox_up; 964 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 965 struct otx2_nic *pf = af_mbox->pfvf; 966 int offset, id, devid = 0; 967 struct mbox_hdr *rsp_hdr; 968 struct mbox_msghdr *msg; 969 u16 num_msgs; 970 971 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 972 num_msgs = rsp_hdr->num_msgs; 973 974 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 975 976 for (id = 0; id < num_msgs; id++) { 977 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 978 979 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 980 /* Skip processing VF's messages */ 981 if (!devid) 982 otx2_process_mbox_msg_up(pf, msg); 983 offset = mbox->rx_start + msg->next_msgoff; 984 } 985 /* Forward to VF iff VFs are really present */ 986 if (devid && pci_num_vf(pf->pdev)) { 987 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 988 MBOX_DIR_PFVF_UP, devid - 1, 989 num_msgs); 990 return; 991 } 992 993 otx2_mbox_msg_send(mbox, 0); 994 } 995 996 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 997 { 998 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 999 struct mbox *mw = &pf->mbox; 1000 struct otx2_mbox_dev *mdev; 1001 struct otx2_mbox *mbox; 1002 struct mbox_hdr *hdr; 1003 u64 mbox_data; 1004 1005 /* Clear the IRQ */ 1006 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1007 1008 1009 mbox_data = otx2_read64(pf, RVU_PF_PFAF_MBOX0); 1010 1011 if (mbox_data & MBOX_UP_MSG) { 1012 mbox_data &= ~MBOX_UP_MSG; 1013 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); 1014 1015 mbox = &mw->mbox_up; 1016 mdev = &mbox->dev[0]; 1017 otx2_sync_mbox_bbuf(mbox, 0); 1018 1019 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 1020 if (hdr->num_msgs) 1021 queue_work(pf->mbox_wq, &mw->mbox_up_wrk); 1022 1023 trace_otx2_msg_interrupt(pf->pdev, "UP message from AF to PF", 1024 BIT_ULL(0)); 1025 } 1026 1027 if (mbox_data & MBOX_DOWN_MSG) { 1028 mbox_data &= ~MBOX_DOWN_MSG; 1029 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); 1030 1031 mbox = &mw->mbox; 1032 mdev = &mbox->dev[0]; 1033 otx2_sync_mbox_bbuf(mbox, 0); 1034 1035 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 1036 if (hdr->num_msgs) 1037 queue_work(pf->mbox_wq, &mw->mbox_wrk); 1038 1039 trace_otx2_msg_interrupt(pf->pdev, "DOWN reply from AF to PF", 1040 BIT_ULL(0)); 1041 } 1042 1043 return IRQ_HANDLED; 1044 } 1045 1046 void otx2_disable_mbox_intr(struct otx2_nic *pf) 1047 { 1048 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 1049 1050 /* Disable AF => PF mailbox IRQ */ 1051 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 1052 free_irq(vector, pf); 1053 } 1054 EXPORT_SYMBOL(otx2_disable_mbox_intr); 1055 1056 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 1057 { 1058 struct otx2_hw *hw = &pf->hw; 1059 struct msg_req *req; 1060 char *irq_name; 1061 int err; 1062 1063 /* Register mailbox interrupt handler */ 1064 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1065 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 1066 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1067 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1068 if (err) { 1069 dev_err(pf->dev, 1070 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1071 return err; 1072 } 1073 1074 /* Enable mailbox interrupt for msgs coming from AF. 1075 * First clear to avoid spurious interrupts, if any. 1076 */ 1077 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1078 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1079 1080 if (!probe_af) 1081 return 0; 1082 1083 /* Check mailbox communication with AF */ 1084 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1085 if (!req) { 1086 otx2_disable_mbox_intr(pf); 1087 return -ENOMEM; 1088 } 1089 err = otx2_sync_mbox_msg(&pf->mbox); 1090 if (err) { 1091 dev_warn(pf->dev, 1092 "AF not responding to mailbox, deferring probe\n"); 1093 otx2_disable_mbox_intr(pf); 1094 return -EPROBE_DEFER; 1095 } 1096 1097 return 0; 1098 } 1099 1100 void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1101 { 1102 struct mbox *mbox = &pf->mbox; 1103 1104 if (pf->mbox_wq) { 1105 destroy_workqueue(pf->mbox_wq); 1106 pf->mbox_wq = NULL; 1107 } 1108 1109 if (mbox->mbox.hwbase) 1110 iounmap((void __iomem *)mbox->mbox.hwbase); 1111 1112 otx2_mbox_destroy(&mbox->mbox); 1113 otx2_mbox_destroy(&mbox->mbox_up); 1114 } 1115 EXPORT_SYMBOL(otx2_pfaf_mbox_destroy); 1116 1117 int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1118 { 1119 struct mbox *mbox = &pf->mbox; 1120 void __iomem *hwbase; 1121 int err; 1122 1123 mbox->pfvf = pf; 1124 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox", 1125 WQ_HIGHPRI | WQ_MEM_RECLAIM); 1126 if (!pf->mbox_wq) 1127 return -ENOMEM; 1128 1129 /* Mailbox is a reserved memory (in RAM) region shared between 1130 * admin function (i.e AF) and this PF, shouldn't be mapped as 1131 * device memory to allow unaligned accesses. 1132 */ 1133 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1134 MBOX_SIZE); 1135 if (!hwbase) { 1136 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1137 err = -ENOMEM; 1138 goto exit; 1139 } 1140 1141 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1142 MBOX_DIR_PFAF, 1); 1143 if (err) 1144 goto exit; 1145 1146 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1147 MBOX_DIR_PFAF_UP, 1); 1148 if (err) 1149 goto exit; 1150 1151 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1152 if (err) 1153 goto exit; 1154 1155 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1156 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1157 mutex_init(&mbox->lock); 1158 1159 return 0; 1160 exit: 1161 otx2_pfaf_mbox_destroy(pf); 1162 return err; 1163 } 1164 1165 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1166 { 1167 struct msg_req *msg; 1168 int err; 1169 1170 mutex_lock(&pf->mbox.lock); 1171 if (enable) 1172 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1173 else 1174 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1175 1176 if (!msg) { 1177 mutex_unlock(&pf->mbox.lock); 1178 return -ENOMEM; 1179 } 1180 1181 err = otx2_sync_mbox_msg(&pf->mbox); 1182 mutex_unlock(&pf->mbox.lock); 1183 return err; 1184 } 1185 1186 int otx2_reset_mac_stats(struct otx2_nic *pfvf) 1187 { 1188 struct msg_req *req; 1189 int err; 1190 1191 mutex_lock(&pfvf->mbox.lock); 1192 req = otx2_mbox_alloc_msg_cgx_stats_rst(&pfvf->mbox); 1193 if (!req) { 1194 mutex_unlock(&pfvf->mbox.lock); 1195 return -ENOMEM; 1196 } 1197 1198 err = otx2_sync_mbox_msg(&pfvf->mbox); 1199 mutex_unlock(&pfvf->mbox.lock); 1200 return err; 1201 } 1202 1203 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1204 { 1205 struct msg_req *msg; 1206 int err; 1207 1208 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1209 pf->flow_cfg->dmacflt_max_flows)) 1210 netdev_warn(pf->netdev, 1211 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1212 1213 mutex_lock(&pf->mbox.lock); 1214 if (enable) 1215 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1216 else 1217 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1218 1219 if (!msg) { 1220 mutex_unlock(&pf->mbox.lock); 1221 return -ENOMEM; 1222 } 1223 1224 err = otx2_sync_mbox_msg(&pf->mbox); 1225 mutex_unlock(&pf->mbox.lock); 1226 return err; 1227 } 1228 1229 int otx2_set_real_num_queues(struct net_device *netdev, 1230 int tx_queues, int rx_queues) 1231 { 1232 int err; 1233 1234 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1235 if (err) { 1236 netdev_err(netdev, 1237 "Failed to set no of Tx queues: %d\n", tx_queues); 1238 return err; 1239 } 1240 1241 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1242 if (err) 1243 netdev_err(netdev, 1244 "Failed to set no of Rx queues: %d\n", rx_queues); 1245 return err; 1246 } 1247 EXPORT_SYMBOL(otx2_set_real_num_queues); 1248 1249 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = { 1250 "NIX_SQOPERR_OOR", 1251 "NIX_SQOPERR_CTX_FAULT", 1252 "NIX_SQOPERR_CTX_POISON", 1253 "NIX_SQOPERR_DISABLED", 1254 "NIX_SQOPERR_SIZE_ERR", 1255 "NIX_SQOPERR_OFLOW", 1256 "NIX_SQOPERR_SQB_NULL", 1257 "NIX_SQOPERR_SQB_FAULT", 1258 "NIX_SQOPERR_SQE_SZ_ZERO", 1259 }; 1260 1261 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = { 1262 "NIX_MNQERR_SQ_CTX_FAULT", 1263 "NIX_MNQERR_SQ_CTX_POISON", 1264 "NIX_MNQERR_SQB_FAULT", 1265 "NIX_MNQERR_SQB_POISON", 1266 "NIX_MNQERR_TOTAL_ERR", 1267 "NIX_MNQERR_LSO_ERR", 1268 "NIX_MNQERR_CQ_QUERY_ERR", 1269 "NIX_MNQERR_MAX_SQE_SIZE_ERR", 1270 "NIX_MNQERR_MAXLEN_ERR", 1271 "NIX_MNQERR_SQE_SIZEM1_ZERO", 1272 }; 1273 1274 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = { 1275 [NIX_SND_STATUS_GOOD] = "NIX_SND_STATUS_GOOD", 1276 [NIX_SND_STATUS_SQ_CTX_FAULT] = "NIX_SND_STATUS_SQ_CTX_FAULT", 1277 [NIX_SND_STATUS_SQ_CTX_POISON] = "NIX_SND_STATUS_SQ_CTX_POISON", 1278 [NIX_SND_STATUS_SQB_FAULT] = "NIX_SND_STATUS_SQB_FAULT", 1279 [NIX_SND_STATUS_SQB_POISON] = "NIX_SND_STATUS_SQB_POISON", 1280 [NIX_SND_STATUS_HDR_ERR] = "NIX_SND_STATUS_HDR_ERR", 1281 [NIX_SND_STATUS_EXT_ERR] = "NIX_SND_STATUS_EXT_ERR", 1282 [NIX_SND_STATUS_JUMP_FAULT] = "NIX_SND_STATUS_JUMP_FAULT", 1283 [NIX_SND_STATUS_JUMP_POISON] = "NIX_SND_STATUS_JUMP_POISON", 1284 [NIX_SND_STATUS_CRC_ERR] = "NIX_SND_STATUS_CRC_ERR", 1285 [NIX_SND_STATUS_IMM_ERR] = "NIX_SND_STATUS_IMM_ERR", 1286 [NIX_SND_STATUS_SG_ERR] = "NIX_SND_STATUS_SG_ERR", 1287 [NIX_SND_STATUS_MEM_ERR] = "NIX_SND_STATUS_MEM_ERR", 1288 [NIX_SND_STATUS_INVALID_SUBDC] = "NIX_SND_STATUS_INVALID_SUBDC", 1289 [NIX_SND_STATUS_SUBDC_ORDER_ERR] = "NIX_SND_STATUS_SUBDC_ORDER_ERR", 1290 [NIX_SND_STATUS_DATA_FAULT] = "NIX_SND_STATUS_DATA_FAULT", 1291 [NIX_SND_STATUS_DATA_POISON] = "NIX_SND_STATUS_DATA_POISON", 1292 [NIX_SND_STATUS_NPC_DROP_ACTION] = "NIX_SND_STATUS_NPC_DROP_ACTION", 1293 [NIX_SND_STATUS_LOCK_VIOL] = "NIX_SND_STATUS_LOCK_VIOL", 1294 [NIX_SND_STATUS_NPC_UCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_UCAST_CHAN_ERR", 1295 [NIX_SND_STATUS_NPC_MCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_MCAST_CHAN_ERR", 1296 [NIX_SND_STATUS_NPC_MCAST_ABORT] = "NIX_SND_STATUS_NPC_MCAST_ABORT", 1297 [NIX_SND_STATUS_NPC_VTAG_PTR_ERR] = "NIX_SND_STATUS_NPC_VTAG_PTR_ERR", 1298 [NIX_SND_STATUS_NPC_VTAG_SIZE_ERR] = "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR", 1299 [NIX_SND_STATUS_SEND_MEM_FAULT] = "NIX_SND_STATUS_SEND_MEM_FAULT", 1300 [NIX_SND_STATUS_SEND_STATS_ERR] = "NIX_SND_STATUS_SEND_STATS_ERR", 1301 }; 1302 1303 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1304 { 1305 struct otx2_nic *pf = data; 1306 struct otx2_snd_queue *sq; 1307 u64 val, *ptr; 1308 u64 qidx = 0; 1309 1310 /* CQ */ 1311 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1312 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1313 val = otx2_atomic64_add((qidx << 44), ptr); 1314 1315 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1316 (val & NIX_CQERRINT_BITS)); 1317 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1318 continue; 1319 1320 if (val & BIT_ULL(42)) { 1321 netdev_err(pf->netdev, 1322 "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1323 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1324 } else { 1325 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1326 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1327 qidx); 1328 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1329 netdev_err(pf->netdev, 1330 "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1331 qidx); 1332 } 1333 1334 schedule_work(&pf->reset_task); 1335 } 1336 1337 /* SQ */ 1338 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1339 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg; 1340 u8 sq_op_err_code, mnq_err_code, snd_err_code; 1341 1342 sq = &pf->qset.sq[qidx]; 1343 if (!sq->sqb_ptrs) 1344 continue; 1345 1346 /* Below debug registers captures first errors corresponding to 1347 * those registers. We don't have to check against SQ qid as 1348 * these are fatal errors. 1349 */ 1350 1351 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1352 val = otx2_atomic64_add((qidx << 44), ptr); 1353 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1354 (val & NIX_SQINT_BITS)); 1355 1356 if (val & BIT_ULL(42)) { 1357 netdev_err(pf->netdev, 1358 "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1359 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1360 goto done; 1361 } 1362 1363 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG); 1364 if (!(sq_op_err_dbg & BIT(44))) 1365 goto chk_mnq_err_dbg; 1366 1367 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg); 1368 netdev_err(pf->netdev, 1369 "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(0x%llx) err=%s(%#x)\n", 1370 qidx, sq_op_err_dbg, 1371 nix_sqoperr_e_str[sq_op_err_code], 1372 sq_op_err_code); 1373 1374 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44)); 1375 1376 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL) 1377 goto chk_mnq_err_dbg; 1378 1379 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure. 1380 * TODO: But we are in irq context. How to call mbox functions which does sleep 1381 */ 1382 1383 chk_mnq_err_dbg: 1384 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG); 1385 if (!(mnq_err_dbg & BIT(44))) 1386 goto chk_snd_err_dbg; 1387 1388 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg); 1389 netdev_err(pf->netdev, 1390 "SQ%lld: NIX_LF_MNQ_ERR_DBG(0x%llx) err=%s(%#x)\n", 1391 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code], 1392 mnq_err_code); 1393 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44)); 1394 1395 chk_snd_err_dbg: 1396 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG); 1397 if (snd_err_dbg & BIT(44)) { 1398 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg); 1399 netdev_err(pf->netdev, 1400 "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s(%#x)\n", 1401 qidx, snd_err_dbg, 1402 nix_snd_status_e_str[snd_err_code], 1403 snd_err_code); 1404 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44)); 1405 } 1406 1407 done: 1408 /* Print values and reset */ 1409 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1410 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1411 qidx); 1412 1413 schedule_work(&pf->reset_task); 1414 } 1415 1416 return IRQ_HANDLED; 1417 } 1418 1419 irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1420 { 1421 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1422 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1423 int qidx = cq_poll->cint_idx; 1424 1425 /* Disable interrupts. 1426 * 1427 * Completion interrupts behave in a level-triggered interrupt 1428 * fashion, and hence have to be cleared only after it is serviced. 1429 */ 1430 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1431 1432 /* Schedule NAPI */ 1433 pf->napi_events++; 1434 napi_schedule_irqoff(&cq_poll->napi); 1435 1436 return IRQ_HANDLED; 1437 } 1438 EXPORT_SYMBOL(otx2_cq_intr_handler); 1439 1440 void otx2_disable_napi(struct otx2_nic *pf) 1441 { 1442 struct otx2_qset *qset = &pf->qset; 1443 struct otx2_cq_poll *cq_poll; 1444 struct work_struct *work; 1445 int qidx; 1446 1447 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1448 cq_poll = &qset->napi[qidx]; 1449 work = &cq_poll->dim.work; 1450 if (work->func) 1451 cancel_work_sync(work); 1452 napi_disable(&cq_poll->napi); 1453 netif_napi_del(&cq_poll->napi); 1454 } 1455 } 1456 EXPORT_SYMBOL(otx2_disable_napi); 1457 1458 static void otx2_free_cq_res(struct otx2_nic *pf) 1459 { 1460 struct otx2_qset *qset = &pf->qset; 1461 struct otx2_cq_queue *cq; 1462 int qidx; 1463 1464 /* Disable CQs */ 1465 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1466 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1467 cq = &qset->cq[qidx]; 1468 qmem_free(pf->dev, cq->cqe); 1469 } 1470 } 1471 1472 static void otx2_free_sq_res(struct otx2_nic *pf) 1473 { 1474 struct otx2_qset *qset = &pf->qset; 1475 struct otx2_snd_queue *sq; 1476 int qidx; 1477 1478 /* Disable SQs */ 1479 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1480 /* Free SQB pointers */ 1481 otx2_sq_free_sqbs(pf); 1482 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1483 sq = &qset->sq[qidx]; 1484 /* Skip freeing Qos queues if they are not initialized */ 1485 if (!sq->sqe) 1486 continue; 1487 qmem_free(pf->dev, sq->sqe); 1488 qmem_free(pf->dev, sq->sqe_ring); 1489 qmem_free(pf->dev, sq->cpt_resp); 1490 qmem_free(pf->dev, sq->tso_hdrs); 1491 kfree(sq->sg); 1492 kfree(sq->sqb_ptrs); 1493 } 1494 } 1495 1496 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1497 { 1498 int frame_size; 1499 int total_size; 1500 int rbuf_size; 1501 1502 if (pf->hw.rbuf_len) 1503 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1504 1505 /* The data transferred by NIX to memory consists of actual packet 1506 * plus additional data which has timestamp and/or EDSA/HIGIG2 1507 * headers if interface is configured in corresponding modes. 1508 * NIX transfers entire data using 6 segments/buffers and writes 1509 * a CQE_RX descriptor with those segment addresses. First segment 1510 * has additional data prepended to packet. Also software omits a 1511 * headroom of 128 bytes in each segment. Hence the total size of 1512 * memory needed to receive a packet with 'mtu' is: 1513 * frame size = mtu + additional data; 1514 * memory = frame_size + headroom * 6; 1515 * each receive buffer size = memory / 6; 1516 */ 1517 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1518 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1519 rbuf_size = total_size / 6; 1520 1521 return ALIGN(rbuf_size, 2048); 1522 } 1523 1524 int otx2_init_hw_resources(struct otx2_nic *pf) 1525 { 1526 struct nix_lf_free_req *free_req; 1527 struct mbox *mbox = &pf->mbox; 1528 struct otx2_hw *hw = &pf->hw; 1529 struct msg_req *req; 1530 int err = 0, lvl; 1531 1532 /* Set required NPA LF's pool counts 1533 * Auras and Pools are used in a 1:1 mapping, 1534 * so, aura count = pool count. 1535 */ 1536 hw->rqpool_cnt = hw->rx_queues; 1537 hw->sqpool_cnt = otx2_get_total_tx_queues(pf); 1538 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1539 1540 if (!otx2_rep_dev(pf->pdev)) { 1541 /* Maximum hardware supported transmit length */ 1542 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1543 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1544 } 1545 1546 mutex_lock(&mbox->lock); 1547 /* NPA init */ 1548 err = otx2_config_npa(pf); 1549 if (err) 1550 goto exit; 1551 1552 /* NIX init */ 1553 err = otx2_config_nix(pf); 1554 if (err) 1555 goto err_free_npa_lf; 1556 1557 /* Default disable backpressure on NIX-CPT */ 1558 otx2_nix_cpt_config_bp(pf, false); 1559 1560 /* Enable backpressure for CGX mapped PF/VFs */ 1561 if (!is_otx2_lbkvf(pf->pdev)) 1562 otx2_nix_config_bp(pf, true); 1563 1564 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1565 err = otx2_rq_aura_pool_init(pf); 1566 if (err) { 1567 mutex_unlock(&mbox->lock); 1568 goto err_free_nix_lf; 1569 } 1570 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1571 err = otx2_sq_aura_pool_init(pf); 1572 if (err) { 1573 mutex_unlock(&mbox->lock); 1574 goto err_free_rq_ptrs; 1575 } 1576 1577 err = otx2_txsch_alloc(pf); 1578 if (err) { 1579 mutex_unlock(&mbox->lock); 1580 goto err_free_sq_ptrs; 1581 } 1582 1583 #ifdef CONFIG_DCB 1584 if (pf->pfc_en) { 1585 err = otx2_pfc_txschq_alloc(pf); 1586 if (err) { 1587 mutex_unlock(&mbox->lock); 1588 goto err_free_sq_ptrs; 1589 } 1590 } 1591 #endif 1592 1593 err = otx2_config_nix_queues(pf); 1594 if (err) { 1595 mutex_unlock(&mbox->lock); 1596 goto err_free_txsch; 1597 } 1598 1599 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1600 int idx; 1601 1602 for (idx = 0; idx < pf->hw.txschq_cnt[lvl]; idx++) { 1603 err = otx2_txschq_config(pf, lvl, idx, false); 1604 if (err) { 1605 dev_err(pf->dev, "Failed to config TXSCH\n"); 1606 mutex_unlock(&mbox->lock); 1607 goto err_free_nix_queues; 1608 } 1609 } 1610 } 1611 1612 #ifdef CONFIG_DCB 1613 if (pf->pfc_en) { 1614 err = otx2_pfc_txschq_config(pf); 1615 if (err) { 1616 mutex_unlock(&mbox->lock); 1617 goto err_free_nix_queues; 1618 } 1619 } 1620 #endif 1621 1622 mutex_unlock(&mbox->lock); 1623 return err; 1624 1625 err_free_nix_queues: 1626 otx2_free_sq_res(pf); 1627 otx2_free_cq_res(pf); 1628 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1629 err_free_txsch: 1630 otx2_txschq_stop(pf); 1631 err_free_sq_ptrs: 1632 otx2_sq_free_sqbs(pf); 1633 err_free_rq_ptrs: 1634 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1635 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1636 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1637 otx2_aura_pool_free(pf); 1638 err_free_nix_lf: 1639 mutex_lock(&mbox->lock); 1640 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1641 if (free_req) { 1642 free_req->flags = NIX_LF_DISABLE_FLOWS; 1643 if (otx2_sync_mbox_msg(mbox)) 1644 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1645 } 1646 err_free_npa_lf: 1647 /* Reset NPA LF */ 1648 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1649 if (req) { 1650 if (otx2_sync_mbox_msg(mbox)) 1651 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1652 } 1653 exit: 1654 mutex_unlock(&mbox->lock); 1655 return err; 1656 } 1657 EXPORT_SYMBOL(otx2_init_hw_resources); 1658 1659 void otx2_free_hw_resources(struct otx2_nic *pf) 1660 { 1661 struct otx2_qset *qset = &pf->qset; 1662 struct nix_lf_free_req *free_req; 1663 struct mbox *mbox = &pf->mbox; 1664 struct otx2_cq_queue *cq; 1665 struct otx2_pool *pool; 1666 struct msg_req *req; 1667 int pool_id; 1668 int qidx; 1669 1670 /* Ensure all SQE are processed */ 1671 otx2_sqb_flush(pf); 1672 1673 /* Stop transmission */ 1674 otx2_txschq_stop(pf); 1675 1676 #ifdef CONFIG_DCB 1677 if (pf->pfc_en) 1678 otx2_pfc_txschq_stop(pf); 1679 #endif 1680 1681 if (!otx2_rep_dev(pf->pdev)) 1682 otx2_clean_qos_queues(pf); 1683 1684 mutex_lock(&mbox->lock); 1685 /* Disable backpressure */ 1686 if (!is_otx2_lbkvf(pf->pdev)) 1687 otx2_nix_config_bp(pf, false); 1688 mutex_unlock(&mbox->lock); 1689 1690 /* Disable RQs */ 1691 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1692 1693 /*Dequeue all CQEs */ 1694 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1695 cq = &qset->cq[qidx]; 1696 if (cq->cq_type == CQ_RX) 1697 otx2_cleanup_rx_cqes(pf, cq, qidx); 1698 else 1699 otx2_cleanup_tx_cqes(pf, cq); 1700 } 1701 otx2_free_pending_sqe(pf); 1702 1703 otx2_free_sq_res(pf); 1704 1705 /* Free RQ buffer pointers*/ 1706 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1707 1708 for (qidx = 0; qidx < pf->hw.rx_queues; qidx++) { 1709 pool_id = otx2_get_pool_idx(pf, AURA_NIX_RQ, qidx); 1710 pool = &pf->qset.pool[pool_id]; 1711 page_pool_destroy(pool->page_pool); 1712 pool->page_pool = NULL; 1713 } 1714 1715 otx2_free_cq_res(pf); 1716 1717 /* Free all ingress bandwidth profiles allocated */ 1718 if (!otx2_rep_dev(pf->pdev)) 1719 cn10k_free_all_ipolicers(pf); 1720 1721 mutex_lock(&mbox->lock); 1722 /* Reset NIX LF */ 1723 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1724 if (free_req) { 1725 free_req->flags = NIX_LF_DISABLE_FLOWS; 1726 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1727 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1728 if (otx2_sync_mbox_msg(mbox)) 1729 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1730 } 1731 mutex_unlock(&mbox->lock); 1732 1733 /* Disable NPA Pool and Aura hw context */ 1734 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1735 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1736 otx2_aura_pool_free(pf); 1737 1738 mutex_lock(&mbox->lock); 1739 /* Reset NPA LF */ 1740 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1741 if (req) { 1742 if (otx2_sync_mbox_msg(mbox)) 1743 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1744 } 1745 mutex_unlock(&mbox->lock); 1746 } 1747 EXPORT_SYMBOL(otx2_free_hw_resources); 1748 1749 static bool otx2_promisc_use_mce_list(struct otx2_nic *pfvf) 1750 { 1751 int vf; 1752 1753 /* The AF driver will determine whether to allow the VF netdev or not */ 1754 if (is_otx2_vf(pfvf->pcifunc)) 1755 return true; 1756 1757 /* check if there are any trusted VFs associated with the PF netdev */ 1758 for (vf = 0; vf < pci_num_vf(pfvf->pdev); vf++) 1759 if (pfvf->vf_configs[vf].trusted) 1760 return true; 1761 return false; 1762 } 1763 1764 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1765 { 1766 struct net_device *netdev = pf->netdev; 1767 struct nix_rx_mode *req; 1768 bool promisc = false; 1769 1770 if (!(netdev->flags & IFF_UP)) 1771 return; 1772 1773 if ((netdev->flags & IFF_PROMISC) || 1774 (netdev_uc_count(netdev) > pf->flow_cfg->ucast_flt_cnt)) { 1775 promisc = true; 1776 } 1777 1778 /* Write unicast address to mcam entries or del from mcam */ 1779 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1780 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1781 1782 mutex_lock(&pf->mbox.lock); 1783 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1784 if (!req) { 1785 mutex_unlock(&pf->mbox.lock); 1786 return; 1787 } 1788 1789 req->mode = NIX_RX_MODE_UCAST; 1790 1791 if (promisc) 1792 req->mode |= NIX_RX_MODE_PROMISC; 1793 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1794 req->mode |= NIX_RX_MODE_ALLMULTI; 1795 1796 if (otx2_promisc_use_mce_list(pf)) 1797 req->mode |= NIX_RX_MODE_USE_MCE; 1798 1799 otx2_sync_mbox_msg(&pf->mbox); 1800 mutex_unlock(&pf->mbox.lock); 1801 } 1802 1803 static void otx2_set_irq_coalesce(struct otx2_nic *pfvf) 1804 { 1805 int cint; 1806 1807 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++) 1808 otx2_config_irq_coalescing(pfvf, cint); 1809 } 1810 1811 static void otx2_dim_work(struct work_struct *w) 1812 { 1813 struct dim_cq_moder cur_moder; 1814 struct otx2_cq_poll *cq_poll; 1815 struct otx2_nic *pfvf; 1816 struct dim *dim; 1817 1818 dim = container_of(w, struct dim, work); 1819 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1820 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1821 pfvf = (struct otx2_nic *)cq_poll->dev; 1822 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1823 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1824 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1825 NAPI_POLL_WEIGHT : cur_moder.pkts; 1826 otx2_set_irq_coalesce(pfvf); 1827 dim->state = DIM_START_MEASURE; 1828 } 1829 1830 void otx2_free_queue_mem(struct otx2_qset *qset) 1831 { 1832 kfree(qset->sq); 1833 qset->sq = NULL; 1834 kfree(qset->cq); 1835 qset->cq = NULL; 1836 kfree(qset->rq); 1837 qset->rq = NULL; 1838 kfree(qset->napi); 1839 qset->napi = NULL; 1840 } 1841 EXPORT_SYMBOL(otx2_free_queue_mem); 1842 1843 int otx2_alloc_queue_mem(struct otx2_nic *pf) 1844 { 1845 struct otx2_qset *qset = &pf->qset; 1846 struct otx2_cq_poll *cq_poll; 1847 1848 1849 /* RQ and SQs are mapped to different CQs, 1850 * so find out max CQ IRQs (i.e CINTs) needed. 1851 */ 1852 pf->hw.non_qos_queues = pf->hw.tx_queues + pf->hw.xdp_queues; 1853 pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues, 1854 pf->hw.tc_tx_queues); 1855 1856 pf->qset.cq_cnt = pf->hw.rx_queues + otx2_get_total_tx_queues(pf); 1857 1858 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1859 if (!qset->napi) 1860 return -ENOMEM; 1861 1862 /* CQ size of RQ */ 1863 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1864 /* CQ size of SQ */ 1865 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1866 1867 qset->cq = kcalloc(pf->qset.cq_cnt, 1868 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1869 if (!qset->cq) 1870 goto err_free_mem; 1871 1872 qset->sq = kcalloc(otx2_get_total_tx_queues(pf), 1873 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1874 if (!qset->sq) 1875 goto err_free_mem; 1876 1877 qset->rq = kcalloc(pf->hw.rx_queues, 1878 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1879 if (!qset->rq) 1880 goto err_free_mem; 1881 1882 return 0; 1883 1884 err_free_mem: 1885 otx2_free_queue_mem(qset); 1886 return -ENOMEM; 1887 } 1888 EXPORT_SYMBOL(otx2_alloc_queue_mem); 1889 1890 int otx2_open(struct net_device *netdev) 1891 { 1892 struct otx2_nic *pf = netdev_priv(netdev); 1893 struct otx2_cq_poll *cq_poll = NULL; 1894 struct otx2_qset *qset = &pf->qset; 1895 int err = 0, qidx, vec; 1896 char *irq_name; 1897 1898 netif_carrier_off(netdev); 1899 1900 err = otx2_alloc_queue_mem(pf); 1901 if (err) 1902 return err; 1903 1904 err = otx2_init_hw_resources(pf); 1905 if (err) 1906 goto err_free_mem; 1907 1908 /* Register NAPI handler */ 1909 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1910 cq_poll = &qset->napi[qidx]; 1911 cq_poll->cint_idx = qidx; 1912 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1913 * 'cq_ids[0]' points to RQ's CQ and 1914 * 'cq_ids[1]' points to SQ's CQ and 1915 * 'cq_ids[2]' points to XDP's CQ and 1916 */ 1917 cq_poll->cq_ids[CQ_RX] = 1918 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1919 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1920 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1921 if (pf->xdp_prog) 1922 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1923 (qidx + pf->hw.rx_queues + 1924 pf->hw.tx_queues) : 1925 CINT_INVALID_CQ; 1926 else 1927 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1928 1929 cq_poll->cq_ids[CQ_QOS] = (qidx < pf->hw.tc_tx_queues) ? 1930 (qidx + pf->hw.rx_queues + 1931 pf->hw.non_qos_queues) : 1932 CINT_INVALID_CQ; 1933 1934 cq_poll->dev = (void *)pf; 1935 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1936 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1937 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1938 napi_enable(&cq_poll->napi); 1939 } 1940 1941 /* Set maximum frame size allowed in HW */ 1942 err = otx2_hw_set_mtu(pf, netdev->mtu); 1943 if (err) 1944 goto err_disable_napi; 1945 1946 /* Setup segmentation algorithms, if failed, clear offload capability */ 1947 otx2_setup_segmentation(pf); 1948 1949 /* Initialize RSS */ 1950 err = otx2_rss_init(pf); 1951 if (err) 1952 goto err_disable_napi; 1953 1954 /* Register Queue IRQ handlers */ 1955 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1956 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1957 1958 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1959 1960 err = request_irq(pci_irq_vector(pf->pdev, vec), 1961 otx2_q_intr_handler, 0, irq_name, pf); 1962 if (err) { 1963 dev_err(pf->dev, 1964 "RVUPF%d: IRQ registration failed for QERR\n", 1965 rvu_get_pf(pf->pcifunc)); 1966 goto err_disable_napi; 1967 } 1968 1969 /* Enable QINT IRQ */ 1970 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1971 1972 /* Register CQ IRQ handlers */ 1973 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1974 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1975 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1976 int name_len; 1977 1978 name_len = snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", 1979 pf->netdev->name, qidx); 1980 if (name_len >= NAME_SIZE) { 1981 dev_err(pf->dev, 1982 "RVUPF%d: IRQ registration failed for CQ%d, irq name is too long\n", 1983 rvu_get_pf(pf->pcifunc), qidx); 1984 err = -EINVAL; 1985 goto err_free_cints; 1986 } 1987 1988 err = request_irq(pci_irq_vector(pf->pdev, vec), 1989 otx2_cq_intr_handler, 0, irq_name, 1990 &qset->napi[qidx]); 1991 if (err) { 1992 dev_err(pf->dev, 1993 "RVUPF%d: IRQ registration failed for CQ%d\n", 1994 rvu_get_pf(pf->pcifunc), qidx); 1995 goto err_free_cints; 1996 } 1997 vec++; 1998 1999 otx2_config_irq_coalescing(pf, qidx); 2000 2001 /* Enable CQ IRQ */ 2002 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 2003 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 2004 } 2005 2006 otx2_set_cints_affinity(pf); 2007 2008 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2009 otx2_enable_rxvlan(pf, true); 2010 2011 /* When reinitializing enable time stamping if it is enabled before */ 2012 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 2013 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2014 otx2_config_hw_tx_tstamp(pf, true); 2015 } 2016 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 2017 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2018 otx2_config_hw_rx_tstamp(pf, true); 2019 } 2020 2021 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 2022 pf->flags &= ~OTX2_FLAG_PORT_UP; 2023 /* 'intf_down' may be checked on any cpu */ 2024 smp_wmb(); 2025 2026 /* Enable QoS configuration before starting tx queues */ 2027 otx2_qos_config_txschq(pf); 2028 2029 /* we have already received link status notification */ 2030 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 2031 otx2_handle_link_event(pf); 2032 2033 /* Install DMAC Filters */ 2034 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 2035 otx2_dmacflt_reinstall_flows(pf); 2036 2037 otx2_tc_apply_ingress_police_rules(pf); 2038 2039 err = otx2_rxtx_enable(pf, true); 2040 /* If a mbox communication error happens at this point then interface 2041 * will end up in a state such that it is in down state but hardware 2042 * mcam entries are enabled to receive the packets. Hence disable the 2043 * packet I/O. 2044 */ 2045 if (err == -EIO) 2046 goto err_disable_rxtx; 2047 else if (err) 2048 goto err_tx_stop_queues; 2049 2050 otx2_do_set_rx_mode(pf); 2051 2052 return 0; 2053 2054 err_disable_rxtx: 2055 otx2_rxtx_enable(pf, false); 2056 err_tx_stop_queues: 2057 netif_tx_stop_all_queues(netdev); 2058 netif_carrier_off(netdev); 2059 pf->flags |= OTX2_FLAG_INTF_DOWN; 2060 err_free_cints: 2061 otx2_free_cints(pf, qidx); 2062 vec = pci_irq_vector(pf->pdev, 2063 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 2064 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 2065 free_irq(vec, pf); 2066 err_disable_napi: 2067 otx2_disable_napi(pf); 2068 otx2_free_hw_resources(pf); 2069 err_free_mem: 2070 otx2_free_queue_mem(qset); 2071 return err; 2072 } 2073 EXPORT_SYMBOL(otx2_open); 2074 2075 int otx2_stop(struct net_device *netdev) 2076 { 2077 struct otx2_nic *pf = netdev_priv(netdev); 2078 struct otx2_cq_poll *cq_poll = NULL; 2079 struct otx2_qset *qset = &pf->qset; 2080 struct otx2_rss_info *rss; 2081 int qidx, vec, wrk; 2082 2083 /* If the DOWN flag is set resources are already freed */ 2084 if (pf->flags & OTX2_FLAG_INTF_DOWN) 2085 return 0; 2086 2087 netif_carrier_off(netdev); 2088 netif_tx_stop_all_queues(netdev); 2089 2090 pf->flags |= OTX2_FLAG_INTF_DOWN; 2091 /* 'intf_down' may be checked on any cpu */ 2092 smp_wmb(); 2093 2094 /* First stop packet Rx/Tx */ 2095 otx2_rxtx_enable(pf, false); 2096 2097 /* Clear RSS enable flag */ 2098 rss = &pf->hw.rss_info; 2099 rss->enable = false; 2100 if (!netif_is_rxfh_configured(netdev)) 2101 kfree(rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 2102 2103 /* Cleanup Queue IRQ */ 2104 vec = pci_irq_vector(pf->pdev, 2105 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 2106 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 2107 free_irq(vec, pf); 2108 2109 /* Cleanup CQ NAPI and IRQ */ 2110 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 2111 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 2112 /* Disable interrupt */ 2113 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 2114 2115 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 2116 2117 cq_poll = &qset->napi[qidx]; 2118 napi_synchronize(&cq_poll->napi); 2119 vec++; 2120 } 2121 2122 netif_tx_disable(netdev); 2123 2124 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 2125 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 2126 devm_kfree(pf->dev, pf->refill_wrk); 2127 2128 otx2_free_hw_resources(pf); 2129 otx2_free_cints(pf, pf->hw.cint_cnt); 2130 otx2_disable_napi(pf); 2131 2132 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 2133 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 2134 2135 otx2_free_queue_mem(qset); 2136 /* Do not clear RQ/SQ ringsize settings */ 2137 memset_startat(qset, 0, sqe_cnt); 2138 return 0; 2139 } 2140 EXPORT_SYMBOL(otx2_stop); 2141 2142 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 2143 { 2144 struct otx2_nic *pf = netdev_priv(netdev); 2145 int qidx = skb_get_queue_mapping(skb); 2146 struct otx2_snd_queue *sq; 2147 struct netdev_queue *txq; 2148 int sq_idx; 2149 2150 /* XDP SQs are not mapped with TXQs 2151 * advance qid to derive correct sq mapped with QOS 2152 */ 2153 sq_idx = (qidx >= pf->hw.tx_queues) ? (qidx + pf->hw.xdp_queues) : qidx; 2154 2155 /* Check for minimum and maximum packet length */ 2156 if (skb->len <= ETH_HLEN || 2157 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 2158 dev_kfree_skb(skb); 2159 return NETDEV_TX_OK; 2160 } 2161 2162 sq = &pf->qset.sq[sq_idx]; 2163 txq = netdev_get_tx_queue(netdev, qidx); 2164 2165 if (!otx2_sq_append_skb(pf, txq, sq, skb, qidx)) { 2166 netif_tx_stop_queue(txq); 2167 2168 /* Check again, incase SQBs got freed up */ 2169 smp_mb(); 2170 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 2171 > sq->sqe_thresh) 2172 netif_tx_wake_queue(txq); 2173 2174 return NETDEV_TX_BUSY; 2175 } 2176 2177 return NETDEV_TX_OK; 2178 } 2179 2180 static int otx2_qos_select_htb_queue(struct otx2_nic *pf, struct sk_buff *skb, 2181 u16 htb_maj_id) 2182 { 2183 u16 classid; 2184 2185 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id) 2186 classid = TC_H_MIN(skb->priority); 2187 else 2188 classid = READ_ONCE(pf->qos.defcls); 2189 2190 if (!classid) 2191 return 0; 2192 2193 return otx2_get_txq_by_classid(pf, classid); 2194 } 2195 2196 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 2197 struct net_device *sb_dev) 2198 { 2199 struct otx2_nic *pf = netdev_priv(netdev); 2200 bool qos_enabled; 2201 #ifdef CONFIG_DCB 2202 u8 vlan_prio; 2203 #endif 2204 int txq; 2205 2206 qos_enabled = netdev->real_num_tx_queues > pf->hw.tx_queues; 2207 if (unlikely(qos_enabled)) { 2208 /* This smp_load_acquire() pairs with smp_store_release() in 2209 * otx2_qos_root_add() called from htb offload root creation 2210 */ 2211 u16 htb_maj_id = smp_load_acquire(&pf->qos.maj_id); 2212 2213 if (unlikely(htb_maj_id)) { 2214 txq = otx2_qos_select_htb_queue(pf, skb, htb_maj_id); 2215 if (txq > 0) 2216 return txq; 2217 goto process_pfc; 2218 } 2219 } 2220 2221 process_pfc: 2222 #ifdef CONFIG_DCB 2223 if (!skb_vlan_tag_present(skb)) 2224 goto pick_tx; 2225 2226 vlan_prio = skb->vlan_tci >> 13; 2227 if ((vlan_prio > pf->hw.tx_queues - 1) || 2228 !pf->pfc_alloc_status[vlan_prio]) 2229 goto pick_tx; 2230 2231 return vlan_prio; 2232 2233 pick_tx: 2234 #endif 2235 txq = netdev_pick_tx(netdev, skb, NULL); 2236 if (unlikely(qos_enabled)) 2237 return txq % pf->hw.tx_queues; 2238 2239 return txq; 2240 } 2241 EXPORT_SYMBOL(otx2_select_queue); 2242 2243 static netdev_features_t otx2_fix_features(struct net_device *dev, 2244 netdev_features_t features) 2245 { 2246 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2247 features |= NETIF_F_HW_VLAN_STAG_RX; 2248 else 2249 features &= ~NETIF_F_HW_VLAN_STAG_RX; 2250 2251 return features; 2252 } 2253 2254 static void otx2_set_rx_mode(struct net_device *netdev) 2255 { 2256 struct otx2_nic *pf = netdev_priv(netdev); 2257 2258 queue_work(pf->otx2_wq, &pf->rx_mode_work); 2259 } 2260 2261 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 2262 { 2263 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 2264 2265 otx2_do_set_rx_mode(pf); 2266 } 2267 2268 static int otx2_set_features(struct net_device *netdev, 2269 netdev_features_t features) 2270 { 2271 netdev_features_t changed = features ^ netdev->features; 2272 struct otx2_nic *pf = netdev_priv(netdev); 2273 2274 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 2275 return otx2_cgx_config_loopback(pf, 2276 features & NETIF_F_LOOPBACK); 2277 2278 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 2279 return otx2_enable_rxvlan(pf, 2280 features & NETIF_F_HW_VLAN_CTAG_RX); 2281 2282 if (changed & NETIF_F_HW_ESP) 2283 return cn10k_ipsec_ethtool_init(netdev, 2284 features & NETIF_F_HW_ESP); 2285 2286 return otx2_handle_ntuple_tc_features(netdev, features); 2287 } 2288 2289 static void otx2_reset_task(struct work_struct *work) 2290 { 2291 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 2292 2293 if (!netif_running(pf->netdev)) 2294 return; 2295 2296 rtnl_lock(); 2297 otx2_stop(pf->netdev); 2298 pf->reset_count++; 2299 otx2_open(pf->netdev); 2300 netif_trans_update(pf->netdev); 2301 rtnl_unlock(); 2302 } 2303 2304 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 2305 { 2306 struct msg_req *req; 2307 int err; 2308 2309 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 2310 return 0; 2311 2312 mutex_lock(&pfvf->mbox.lock); 2313 if (enable) 2314 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 2315 else 2316 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 2317 if (!req) { 2318 mutex_unlock(&pfvf->mbox.lock); 2319 return -ENOMEM; 2320 } 2321 2322 err = otx2_sync_mbox_msg(&pfvf->mbox); 2323 if (err) { 2324 mutex_unlock(&pfvf->mbox.lock); 2325 return err; 2326 } 2327 2328 mutex_unlock(&pfvf->mbox.lock); 2329 if (enable) 2330 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2331 else 2332 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2333 return 0; 2334 } 2335 2336 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2337 { 2338 struct msg_req *req; 2339 int err; 2340 2341 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2342 return 0; 2343 2344 mutex_lock(&pfvf->mbox.lock); 2345 if (enable) 2346 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2347 else 2348 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2349 if (!req) { 2350 mutex_unlock(&pfvf->mbox.lock); 2351 return -ENOMEM; 2352 } 2353 2354 err = otx2_sync_mbox_msg(&pfvf->mbox); 2355 if (err) { 2356 mutex_unlock(&pfvf->mbox.lock); 2357 return err; 2358 } 2359 2360 mutex_unlock(&pfvf->mbox.lock); 2361 if (enable) 2362 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2363 else 2364 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2365 return 0; 2366 } 2367 2368 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2369 { 2370 struct otx2_nic *pfvf = netdev_priv(netdev); 2371 struct hwtstamp_config config; 2372 2373 if (!pfvf->ptp) 2374 return -ENODEV; 2375 2376 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2377 return -EFAULT; 2378 2379 switch (config.tx_type) { 2380 case HWTSTAMP_TX_OFF: 2381 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2382 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2383 2384 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2385 otx2_config_hw_tx_tstamp(pfvf, false); 2386 break; 2387 case HWTSTAMP_TX_ONESTEP_SYNC: 2388 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2389 return -ERANGE; 2390 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2391 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2392 msecs_to_jiffies(500)); 2393 fallthrough; 2394 case HWTSTAMP_TX_ON: 2395 otx2_config_hw_tx_tstamp(pfvf, true); 2396 break; 2397 default: 2398 return -ERANGE; 2399 } 2400 2401 switch (config.rx_filter) { 2402 case HWTSTAMP_FILTER_NONE: 2403 otx2_config_hw_rx_tstamp(pfvf, false); 2404 break; 2405 case HWTSTAMP_FILTER_ALL: 2406 case HWTSTAMP_FILTER_SOME: 2407 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2408 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2409 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2410 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2411 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2412 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2413 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2414 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2415 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2416 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2417 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2418 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2419 otx2_config_hw_rx_tstamp(pfvf, true); 2420 config.rx_filter = HWTSTAMP_FILTER_ALL; 2421 break; 2422 default: 2423 return -ERANGE; 2424 } 2425 2426 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2427 2428 return copy_to_user(ifr->ifr_data, &config, 2429 sizeof(config)) ? -EFAULT : 0; 2430 } 2431 EXPORT_SYMBOL(otx2_config_hwtstamp); 2432 2433 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2434 { 2435 struct otx2_nic *pfvf = netdev_priv(netdev); 2436 struct hwtstamp_config *cfg = &pfvf->tstamp; 2437 2438 switch (cmd) { 2439 case SIOCSHWTSTAMP: 2440 return otx2_config_hwtstamp(netdev, req); 2441 case SIOCGHWTSTAMP: 2442 return copy_to_user(req->ifr_data, cfg, 2443 sizeof(*cfg)) ? -EFAULT : 0; 2444 default: 2445 return -EOPNOTSUPP; 2446 } 2447 } 2448 EXPORT_SYMBOL(otx2_ioctl); 2449 2450 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2451 { 2452 struct npc_install_flow_req *req; 2453 int err; 2454 2455 mutex_lock(&pf->mbox.lock); 2456 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2457 if (!req) { 2458 err = -ENOMEM; 2459 goto out; 2460 } 2461 2462 ether_addr_copy(req->packet.dmac, mac); 2463 eth_broadcast_addr((u8 *)&req->mask.dmac); 2464 req->features = BIT_ULL(NPC_DMAC); 2465 req->channel = pf->hw.rx_chan_base; 2466 req->intf = NIX_INTF_RX; 2467 req->default_rule = 1; 2468 req->append = 1; 2469 req->vf = vf + 1; 2470 req->op = NIX_RX_ACTION_DEFAULT; 2471 2472 err = otx2_sync_mbox_msg(&pf->mbox); 2473 out: 2474 mutex_unlock(&pf->mbox.lock); 2475 return err; 2476 } 2477 2478 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2479 { 2480 struct otx2_nic *pf = netdev_priv(netdev); 2481 struct pci_dev *pdev = pf->pdev; 2482 struct otx2_vf_config *config; 2483 int ret; 2484 2485 if (!netif_running(netdev)) 2486 return -EAGAIN; 2487 2488 if (vf >= pf->total_vfs) 2489 return -EINVAL; 2490 2491 if (!is_valid_ether_addr(mac)) 2492 return -EINVAL; 2493 2494 config = &pf->vf_configs[vf]; 2495 ether_addr_copy(config->mac, mac); 2496 2497 ret = otx2_do_set_vf_mac(pf, vf, mac); 2498 if (ret == 0) 2499 dev_info(&pdev->dev, 2500 "Load/Reload VF driver\n"); 2501 2502 return ret; 2503 } 2504 2505 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2506 __be16 proto) 2507 { 2508 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2509 struct nix_vtag_config_rsp *vtag_rsp; 2510 struct npc_delete_flow_req *del_req; 2511 struct nix_vtag_config *vtag_req; 2512 struct npc_install_flow_req *req; 2513 struct otx2_vf_config *config; 2514 int err = 0; 2515 u32 idx; 2516 2517 config = &pf->vf_configs[vf]; 2518 2519 if (!vlan && !config->vlan) 2520 goto out; 2521 2522 mutex_lock(&pf->mbox.lock); 2523 2524 /* free old tx vtag entry */ 2525 if (config->vlan) { 2526 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2527 if (!vtag_req) { 2528 err = -ENOMEM; 2529 goto out; 2530 } 2531 vtag_req->cfg_type = 0; 2532 vtag_req->tx.free_vtag0 = 1; 2533 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2534 2535 err = otx2_sync_mbox_msg(&pf->mbox); 2536 if (err) 2537 goto out; 2538 } 2539 2540 if (!vlan && config->vlan) { 2541 /* rx */ 2542 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2543 if (!del_req) { 2544 err = -ENOMEM; 2545 goto out; 2546 } 2547 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2548 del_req->entry = 2549 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2550 err = otx2_sync_mbox_msg(&pf->mbox); 2551 if (err) 2552 goto out; 2553 2554 /* tx */ 2555 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2556 if (!del_req) { 2557 err = -ENOMEM; 2558 goto out; 2559 } 2560 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2561 del_req->entry = 2562 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2563 err = otx2_sync_mbox_msg(&pf->mbox); 2564 2565 goto out; 2566 } 2567 2568 /* rx */ 2569 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2570 if (!req) { 2571 err = -ENOMEM; 2572 goto out; 2573 } 2574 2575 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2576 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2577 req->packet.vlan_tci = htons(vlan); 2578 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2579 /* af fills the destination mac addr */ 2580 eth_broadcast_addr((u8 *)&req->mask.dmac); 2581 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2582 req->channel = pf->hw.rx_chan_base; 2583 req->intf = NIX_INTF_RX; 2584 req->vf = vf + 1; 2585 req->op = NIX_RX_ACTION_DEFAULT; 2586 req->vtag0_valid = true; 2587 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2588 req->set_cntr = 1; 2589 2590 err = otx2_sync_mbox_msg(&pf->mbox); 2591 if (err) 2592 goto out; 2593 2594 /* tx */ 2595 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2596 if (!vtag_req) { 2597 err = -ENOMEM; 2598 goto out; 2599 } 2600 2601 /* configure tx vtag params */ 2602 vtag_req->vtag_size = VTAGSIZE_T4; 2603 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2604 vtag_req->tx.cfg_vtag0 = 1; 2605 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2606 2607 err = otx2_sync_mbox_msg(&pf->mbox); 2608 if (err) 2609 goto out; 2610 2611 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2612 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2613 if (IS_ERR(vtag_rsp)) { 2614 err = PTR_ERR(vtag_rsp); 2615 goto out; 2616 } 2617 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2618 2619 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2620 if (!req) { 2621 err = -ENOMEM; 2622 goto out; 2623 } 2624 2625 eth_zero_addr((u8 *)&req->mask.dmac); 2626 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2627 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2628 req->features = BIT_ULL(NPC_DMAC); 2629 req->channel = pf->hw.tx_chan_base; 2630 req->intf = NIX_INTF_TX; 2631 req->vf = vf + 1; 2632 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2633 req->vtag0_def = vtag_rsp->vtag0_idx; 2634 req->vtag0_op = VTAG_INSERT; 2635 req->set_cntr = 1; 2636 2637 err = otx2_sync_mbox_msg(&pf->mbox); 2638 out: 2639 config->vlan = vlan; 2640 mutex_unlock(&pf->mbox.lock); 2641 return err; 2642 } 2643 2644 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2645 __be16 proto) 2646 { 2647 struct otx2_nic *pf = netdev_priv(netdev); 2648 struct pci_dev *pdev = pf->pdev; 2649 2650 if (!netif_running(netdev)) 2651 return -EAGAIN; 2652 2653 if (vf >= pci_num_vf(pdev)) 2654 return -EINVAL; 2655 2656 /* qos is currently unsupported */ 2657 if (vlan >= VLAN_N_VID || qos) 2658 return -EINVAL; 2659 2660 if (proto != htons(ETH_P_8021Q)) 2661 return -EPROTONOSUPPORT; 2662 2663 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2664 return -EOPNOTSUPP; 2665 2666 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2667 } 2668 2669 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2670 struct ifla_vf_info *ivi) 2671 { 2672 struct otx2_nic *pf = netdev_priv(netdev); 2673 struct pci_dev *pdev = pf->pdev; 2674 struct otx2_vf_config *config; 2675 2676 if (!netif_running(netdev)) 2677 return -EAGAIN; 2678 2679 if (vf >= pci_num_vf(pdev)) 2680 return -EINVAL; 2681 2682 config = &pf->vf_configs[vf]; 2683 ivi->vf = vf; 2684 ether_addr_copy(ivi->mac, config->mac); 2685 ivi->vlan = config->vlan; 2686 ivi->trusted = config->trusted; 2687 2688 return 0; 2689 } 2690 2691 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2692 int qidx) 2693 { 2694 struct page *page; 2695 u64 dma_addr; 2696 int err = 0; 2697 2698 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2699 offset_in_page(xdpf->data), xdpf->len, 2700 DMA_TO_DEVICE); 2701 if (dma_mapping_error(pf->dev, dma_addr)) 2702 return -ENOMEM; 2703 2704 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2705 if (!err) { 2706 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2707 page = virt_to_page(xdpf->data); 2708 put_page(page); 2709 return -ENOMEM; 2710 } 2711 return 0; 2712 } 2713 2714 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2715 struct xdp_frame **frames, u32 flags) 2716 { 2717 struct otx2_nic *pf = netdev_priv(netdev); 2718 int qidx = smp_processor_id(); 2719 struct otx2_snd_queue *sq; 2720 int drops = 0, i; 2721 2722 if (!netif_running(netdev)) 2723 return -ENETDOWN; 2724 2725 qidx += pf->hw.tx_queues; 2726 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2727 2728 /* Abort xmit if xdp queue is not */ 2729 if (unlikely(!sq)) 2730 return -ENXIO; 2731 2732 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2733 return -EINVAL; 2734 2735 for (i = 0; i < n; i++) { 2736 struct xdp_frame *xdpf = frames[i]; 2737 int err; 2738 2739 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2740 if (err) 2741 drops++; 2742 } 2743 return n - drops; 2744 } 2745 2746 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2747 { 2748 struct net_device *dev = pf->netdev; 2749 bool if_up = netif_running(pf->netdev); 2750 struct bpf_prog *old_prog; 2751 2752 if (prog && dev->mtu > MAX_XDP_MTU) { 2753 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2754 return -EOPNOTSUPP; 2755 } 2756 2757 if (if_up) 2758 otx2_stop(pf->netdev); 2759 2760 old_prog = xchg(&pf->xdp_prog, prog); 2761 2762 if (old_prog) 2763 bpf_prog_put(old_prog); 2764 2765 if (pf->xdp_prog) 2766 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2767 2768 /* Network stack and XDP shared same rx queues. 2769 * Use separate tx queues for XDP and network stack. 2770 */ 2771 if (pf->xdp_prog) { 2772 pf->hw.xdp_queues = pf->hw.rx_queues; 2773 xdp_features_set_redirect_target(dev, false); 2774 } else { 2775 pf->hw.xdp_queues = 0; 2776 xdp_features_clear_redirect_target(dev); 2777 } 2778 2779 if (if_up) 2780 otx2_open(pf->netdev); 2781 2782 return 0; 2783 } 2784 2785 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2786 { 2787 struct otx2_nic *pf = netdev_priv(netdev); 2788 2789 switch (xdp->command) { 2790 case XDP_SETUP_PROG: 2791 return otx2_xdp_setup(pf, xdp->prog); 2792 default: 2793 return -EINVAL; 2794 } 2795 } 2796 2797 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2798 int req_perm) 2799 { 2800 struct set_vf_perm *req; 2801 int rc; 2802 2803 mutex_lock(&pf->mbox.lock); 2804 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2805 if (!req) { 2806 rc = -ENOMEM; 2807 goto out; 2808 } 2809 2810 /* Let AF reset VF permissions as sriov is disabled */ 2811 if (req_perm == OTX2_RESET_VF_PERM) { 2812 req->flags |= RESET_VF_PERM; 2813 } else if (req_perm == OTX2_TRUSTED_VF) { 2814 if (pf->vf_configs[vf].trusted) 2815 req->flags |= VF_TRUSTED; 2816 } 2817 2818 req->vf = vf; 2819 rc = otx2_sync_mbox_msg(&pf->mbox); 2820 out: 2821 mutex_unlock(&pf->mbox.lock); 2822 return rc; 2823 } 2824 2825 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2826 bool enable) 2827 { 2828 struct otx2_nic *pf = netdev_priv(netdev); 2829 struct pci_dev *pdev = pf->pdev; 2830 int rc; 2831 2832 if (vf >= pci_num_vf(pdev)) 2833 return -EINVAL; 2834 2835 if (pf->vf_configs[vf].trusted == enable) 2836 return 0; 2837 2838 pf->vf_configs[vf].trusted = enable; 2839 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2840 2841 if (rc) { 2842 pf->vf_configs[vf].trusted = !enable; 2843 } else { 2844 netdev_info(pf->netdev, "VF %d is %strusted\n", 2845 vf, enable ? "" : "not "); 2846 otx2_set_rx_mode(netdev); 2847 } 2848 2849 return rc; 2850 } 2851 2852 static const struct net_device_ops otx2_netdev_ops = { 2853 .ndo_open = otx2_open, 2854 .ndo_stop = otx2_stop, 2855 .ndo_start_xmit = otx2_xmit, 2856 .ndo_select_queue = otx2_select_queue, 2857 .ndo_fix_features = otx2_fix_features, 2858 .ndo_set_mac_address = otx2_set_mac_address, 2859 .ndo_change_mtu = otx2_change_mtu, 2860 .ndo_set_rx_mode = otx2_set_rx_mode, 2861 .ndo_set_features = otx2_set_features, 2862 .ndo_tx_timeout = otx2_tx_timeout, 2863 .ndo_get_stats64 = otx2_get_stats64, 2864 .ndo_eth_ioctl = otx2_ioctl, 2865 .ndo_set_vf_mac = otx2_set_vf_mac, 2866 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2867 .ndo_get_vf_config = otx2_get_vf_config, 2868 .ndo_bpf = otx2_xdp, 2869 .ndo_xdp_xmit = otx2_xdp_xmit, 2870 .ndo_setup_tc = otx2_setup_tc, 2871 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2872 }; 2873 2874 int otx2_wq_init(struct otx2_nic *pf) 2875 { 2876 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2877 if (!pf->otx2_wq) 2878 return -ENOMEM; 2879 2880 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2881 INIT_WORK(&pf->reset_task, otx2_reset_task); 2882 return 0; 2883 } 2884 2885 int otx2_check_pf_usable(struct otx2_nic *nic) 2886 { 2887 u64 rev; 2888 2889 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2890 rev = (rev >> 12) & 0xFF; 2891 /* Check if AF has setup revision for RVUM block, 2892 * otherwise this driver probe should be deferred 2893 * until AF driver comes up. 2894 */ 2895 if (!rev) { 2896 dev_warn(nic->dev, 2897 "AF is not initialized, deferring probe\n"); 2898 return -EPROBE_DEFER; 2899 } 2900 return 0; 2901 } 2902 2903 int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2904 { 2905 struct otx2_hw *hw = &pf->hw; 2906 int num_vec, err; 2907 2908 /* NPA interrupts are inot registered, so alloc only 2909 * upto NIX vector offset. 2910 */ 2911 num_vec = hw->nix_msixoff; 2912 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2913 2914 otx2_disable_mbox_intr(pf); 2915 pci_free_irq_vectors(hw->pdev); 2916 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2917 if (err < 0) { 2918 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2919 __func__, num_vec); 2920 return err; 2921 } 2922 2923 return otx2_register_mbox_intr(pf, false); 2924 } 2925 EXPORT_SYMBOL(otx2_realloc_msix_vectors); 2926 2927 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2928 { 2929 int i; 2930 2931 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2932 sizeof(struct otx2_vf_config), 2933 GFP_KERNEL); 2934 if (!pf->vf_configs) 2935 return -ENOMEM; 2936 2937 for (i = 0; i < pf->total_vfs; i++) { 2938 pf->vf_configs[i].pf = pf; 2939 pf->vf_configs[i].intf_down = true; 2940 pf->vf_configs[i].trusted = false; 2941 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2942 otx2_vf_link_event_task); 2943 } 2944 2945 return 0; 2946 } 2947 2948 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2949 { 2950 int i; 2951 2952 if (!pf->vf_configs) 2953 return; 2954 2955 for (i = 0; i < pf->total_vfs; i++) { 2956 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2957 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2958 } 2959 } 2960 2961 int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf) 2962 { 2963 struct device *dev = &pdev->dev; 2964 struct otx2_hw *hw = &pf->hw; 2965 int num_vec, err; 2966 2967 num_vec = pci_msix_vec_count(pdev); 2968 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2969 GFP_KERNEL); 2970 if (!hw->irq_name) 2971 return -ENOMEM; 2972 2973 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2974 sizeof(cpumask_var_t), GFP_KERNEL); 2975 if (!hw->affinity_mask) 2976 return -ENOMEM; 2977 2978 /* Map CSRs */ 2979 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2980 if (!pf->reg_base) { 2981 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2982 return -ENOMEM; 2983 } 2984 2985 err = otx2_check_pf_usable(pf); 2986 if (err) 2987 return err; 2988 2989 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2990 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2991 if (err < 0) { 2992 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2993 __func__, num_vec); 2994 return err; 2995 } 2996 2997 otx2_setup_dev_hw_settings(pf); 2998 2999 /* Init PF <=> AF mailbox stuff */ 3000 err = otx2_pfaf_mbox_init(pf); 3001 if (err) 3002 goto err_free_irq_vectors; 3003 3004 /* Register mailbox interrupt */ 3005 err = otx2_register_mbox_intr(pf, true); 3006 if (err) 3007 goto err_mbox_destroy; 3008 3009 /* Request AF to attach NPA and NIX LFs to this PF. 3010 * NIX and NPA LFs are needed for this PF to function as a NIC. 3011 */ 3012 err = otx2_attach_npa_nix(pf); 3013 if (err) 3014 goto err_disable_mbox_intr; 3015 3016 err = otx2_realloc_msix_vectors(pf); 3017 if (err) 3018 goto err_detach_rsrc; 3019 3020 err = cn10k_lmtst_init(pf); 3021 if (err) 3022 goto err_detach_rsrc; 3023 3024 return 0; 3025 3026 err_detach_rsrc: 3027 if (pf->hw.lmt_info) 3028 free_percpu(pf->hw.lmt_info); 3029 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3030 qmem_free(pf->dev, pf->dync_lmt); 3031 otx2_detach_resources(&pf->mbox); 3032 err_disable_mbox_intr: 3033 otx2_disable_mbox_intr(pf); 3034 err_mbox_destroy: 3035 otx2_pfaf_mbox_destroy(pf); 3036 err_free_irq_vectors: 3037 pci_free_irq_vectors(hw->pdev); 3038 3039 return err; 3040 } 3041 EXPORT_SYMBOL(otx2_init_rsrc); 3042 3043 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3044 { 3045 struct device *dev = &pdev->dev; 3046 int err, qcount, qos_txqs; 3047 struct net_device *netdev; 3048 struct otx2_nic *pf; 3049 struct otx2_hw *hw; 3050 3051 err = pcim_enable_device(pdev); 3052 if (err) { 3053 dev_err(dev, "Failed to enable PCI device\n"); 3054 return err; 3055 } 3056 3057 err = pci_request_regions(pdev, DRV_NAME); 3058 if (err) { 3059 dev_err(dev, "PCI request regions failed 0x%x\n", err); 3060 return err; 3061 } 3062 3063 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3064 if (err) { 3065 dev_err(dev, "DMA mask config failed, abort\n"); 3066 goto err_release_regions; 3067 } 3068 3069 pci_set_master(pdev); 3070 3071 /* Set number of queues */ 3072 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 3073 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 3074 3075 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount + qos_txqs, qcount); 3076 if (!netdev) { 3077 err = -ENOMEM; 3078 goto err_release_regions; 3079 } 3080 3081 pci_set_drvdata(pdev, netdev); 3082 SET_NETDEV_DEV(netdev, &pdev->dev); 3083 pf = netdev_priv(netdev); 3084 pf->netdev = netdev; 3085 pf->pdev = pdev; 3086 pf->dev = dev; 3087 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 3088 pf->flags |= OTX2_FLAG_INTF_DOWN; 3089 3090 hw = &pf->hw; 3091 hw->pdev = pdev; 3092 hw->rx_queues = qcount; 3093 hw->tx_queues = qcount; 3094 hw->non_qos_queues = qcount; 3095 hw->max_queues = qcount; 3096 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 3097 /* Use CQE of 128 byte descriptor size by default */ 3098 hw->xqe_size = 128; 3099 3100 err = otx2_init_rsrc(pdev, pf); 3101 if (err) 3102 goto err_free_netdev; 3103 3104 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 3105 if (err) 3106 goto err_detach_rsrc; 3107 3108 /* Assign default mac address */ 3109 otx2_get_mac_from_af(netdev); 3110 3111 /* Don't check for error. Proceed without ptp */ 3112 otx2_ptp_init(pf); 3113 3114 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 3115 * HW allocates buffer pointer from stack and uses it for DMA'ing 3116 * ingress packet. In some scenarios HW can free back allocated buffer 3117 * pointers to pool. This makes it impossible for SW to maintain a 3118 * parallel list where physical addresses of buffer pointers (IOVAs) 3119 * given to HW can be saved for later reference. 3120 * 3121 * So the only way to convert Rx packet's buffer address is to use 3122 * IOMMU's iova_to_phys() handler which translates the address by 3123 * walking through the translation tables. 3124 */ 3125 pf->iommu_domain = iommu_get_domain_for_dev(dev); 3126 3127 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 3128 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 3129 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 3130 NETIF_F_GSO_UDP_L4); 3131 netdev->features |= netdev->hw_features; 3132 3133 err = otx2_mcam_flow_init(pf); 3134 if (err) 3135 goto err_ptp_destroy; 3136 3137 err = cn10k_mcs_init(pf); 3138 if (err) 3139 goto err_del_mcam_entries; 3140 3141 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 3142 netdev->hw_features |= NETIF_F_NTUPLE; 3143 3144 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 3145 netdev->priv_flags |= IFF_UNICAST_FLT; 3146 3147 /* Support TSO on tag interface */ 3148 netdev->vlan_features |= netdev->features; 3149 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 3150 NETIF_F_HW_VLAN_STAG_TX; 3151 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 3152 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 3153 NETIF_F_HW_VLAN_STAG_RX; 3154 netdev->features |= netdev->hw_features; 3155 3156 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 3157 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 3158 netdev->hw_features |= NETIF_F_HW_TC; 3159 3160 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 3161 3162 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 3163 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 3164 3165 netdev->netdev_ops = &otx2_netdev_ops; 3166 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3167 3168 netdev->min_mtu = OTX2_MIN_MTU; 3169 netdev->max_mtu = otx2_get_max_mtu(pf); 3170 hw->max_mtu = netdev->max_mtu; 3171 3172 /* reset CGX/RPM MAC stats */ 3173 otx2_reset_mac_stats(pf); 3174 3175 err = cn10k_ipsec_init(netdev); 3176 if (err) 3177 goto err_mcs_free; 3178 3179 err = register_netdev(netdev); 3180 if (err) { 3181 dev_err(dev, "Failed to register netdevice\n"); 3182 goto err_ipsec_clean; 3183 } 3184 3185 err = otx2_wq_init(pf); 3186 if (err) 3187 goto err_unreg_netdev; 3188 3189 otx2_set_ethtool_ops(netdev); 3190 3191 err = otx2_init_tc(pf); 3192 if (err) 3193 goto err_mcam_flow_del; 3194 3195 err = otx2_register_dl(pf); 3196 if (err) 3197 goto err_mcam_flow_del; 3198 3199 /* Initialize SR-IOV resources */ 3200 err = otx2_sriov_vfcfg_init(pf); 3201 if (err) 3202 goto err_pf_sriov_init; 3203 3204 /* Enable link notifications */ 3205 otx2_cgx_config_linkevents(pf, true); 3206 3207 #ifdef CONFIG_DCB 3208 err = otx2_dcbnl_set_ops(netdev); 3209 if (err) 3210 goto err_pf_sriov_init; 3211 #endif 3212 3213 otx2_qos_init(pf, qos_txqs); 3214 3215 return 0; 3216 3217 err_pf_sriov_init: 3218 otx2_shutdown_tc(pf); 3219 err_mcam_flow_del: 3220 otx2_mcam_flow_del(pf); 3221 err_unreg_netdev: 3222 unregister_netdev(netdev); 3223 err_ipsec_clean: 3224 cn10k_ipsec_clean(pf); 3225 err_mcs_free: 3226 cn10k_mcs_free(pf); 3227 err_del_mcam_entries: 3228 otx2_mcam_flow_del(pf); 3229 err_ptp_destroy: 3230 otx2_ptp_destroy(pf); 3231 err_detach_rsrc: 3232 if (pf->hw.lmt_info) 3233 free_percpu(pf->hw.lmt_info); 3234 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3235 qmem_free(pf->dev, pf->dync_lmt); 3236 otx2_detach_resources(&pf->mbox); 3237 otx2_disable_mbox_intr(pf); 3238 otx2_pfaf_mbox_destroy(pf); 3239 pci_free_irq_vectors(hw->pdev); 3240 err_free_netdev: 3241 pci_set_drvdata(pdev, NULL); 3242 free_netdev(netdev); 3243 err_release_regions: 3244 pci_release_regions(pdev); 3245 return err; 3246 } 3247 3248 static void otx2_vf_link_event_task(struct work_struct *work) 3249 { 3250 struct otx2_vf_config *config; 3251 struct cgx_link_info_msg *req; 3252 struct mbox_msghdr *msghdr; 3253 struct delayed_work *dwork; 3254 struct otx2_nic *pf; 3255 int vf_idx; 3256 3257 config = container_of(work, struct otx2_vf_config, 3258 link_event_work.work); 3259 vf_idx = config - config->pf->vf_configs; 3260 pf = config->pf; 3261 3262 if (config->intf_down) 3263 return; 3264 3265 mutex_lock(&pf->mbox.lock); 3266 3267 dwork = &config->link_event_work; 3268 3269 if (!otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx)) { 3270 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 3271 mutex_unlock(&pf->mbox.lock); 3272 return; 3273 } 3274 3275 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 3276 sizeof(*req), sizeof(struct msg_rsp)); 3277 if (!msghdr) { 3278 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 3279 mutex_unlock(&pf->mbox.lock); 3280 return; 3281 } 3282 3283 req = (struct cgx_link_info_msg *)msghdr; 3284 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 3285 req->hdr.sig = OTX2_MBOX_REQ_SIG; 3286 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 3287 3288 otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx); 3289 3290 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 3291 3292 mutex_unlock(&pf->mbox.lock); 3293 } 3294 3295 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 3296 { 3297 struct net_device *netdev = pci_get_drvdata(pdev); 3298 struct otx2_nic *pf = netdev_priv(netdev); 3299 int ret; 3300 3301 /* Init PF <=> VF mailbox stuff */ 3302 ret = otx2_pfvf_mbox_init(pf, numvfs); 3303 if (ret) 3304 return ret; 3305 3306 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 3307 if (ret) 3308 goto free_mbox; 3309 3310 ret = otx2_pf_flr_init(pf, numvfs); 3311 if (ret) 3312 goto free_intr; 3313 3314 ret = otx2_register_flr_me_intr(pf, numvfs); 3315 if (ret) 3316 goto free_flr; 3317 3318 ret = pci_enable_sriov(pdev, numvfs); 3319 if (ret) 3320 goto free_flr_intr; 3321 3322 return numvfs; 3323 free_flr_intr: 3324 otx2_disable_flr_me_intr(pf); 3325 free_flr: 3326 otx2_flr_wq_destroy(pf); 3327 free_intr: 3328 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3329 free_mbox: 3330 otx2_pfvf_mbox_destroy(pf); 3331 return ret; 3332 } 3333 3334 static int otx2_sriov_disable(struct pci_dev *pdev) 3335 { 3336 struct net_device *netdev = pci_get_drvdata(pdev); 3337 struct otx2_nic *pf = netdev_priv(netdev); 3338 int numvfs = pci_num_vf(pdev); 3339 3340 if (!numvfs) 3341 return 0; 3342 3343 pci_disable_sriov(pdev); 3344 3345 otx2_disable_flr_me_intr(pf); 3346 otx2_flr_wq_destroy(pf); 3347 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3348 otx2_pfvf_mbox_destroy(pf); 3349 3350 return 0; 3351 } 3352 3353 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 3354 { 3355 if (numvfs == 0) 3356 return otx2_sriov_disable(pdev); 3357 else 3358 return otx2_sriov_enable(pdev, numvfs); 3359 } 3360 3361 static void otx2_ndc_sync(struct otx2_nic *pf) 3362 { 3363 struct mbox *mbox = &pf->mbox; 3364 struct ndc_sync_op *req; 3365 3366 mutex_lock(&mbox->lock); 3367 3368 req = otx2_mbox_alloc_msg_ndc_sync_op(mbox); 3369 if (!req) { 3370 mutex_unlock(&mbox->lock); 3371 return; 3372 } 3373 3374 req->nix_lf_tx_sync = 1; 3375 req->nix_lf_rx_sync = 1; 3376 req->npa_lf_sync = 1; 3377 3378 if (!otx2_sync_mbox_msg(mbox)) 3379 dev_err(pf->dev, "NDC sync operation failed\n"); 3380 3381 mutex_unlock(&mbox->lock); 3382 } 3383 3384 static void otx2_remove(struct pci_dev *pdev) 3385 { 3386 struct net_device *netdev = pci_get_drvdata(pdev); 3387 struct otx2_nic *pf; 3388 3389 if (!netdev) 3390 return; 3391 3392 pf = netdev_priv(netdev); 3393 3394 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 3395 3396 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 3397 otx2_config_hw_tx_tstamp(pf, false); 3398 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 3399 otx2_config_hw_rx_tstamp(pf, false); 3400 3401 /* Disable 802.3x pause frames */ 3402 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 3403 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 3404 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 3405 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 3406 otx2_config_pause_frm(pf); 3407 } 3408 3409 #ifdef CONFIG_DCB 3410 /* Disable PFC config */ 3411 if (pf->pfc_en) { 3412 pf->pfc_en = 0; 3413 otx2_config_priority_flow_ctrl(pf); 3414 } 3415 #endif 3416 cancel_work_sync(&pf->reset_task); 3417 /* Disable link notifications */ 3418 otx2_cgx_config_linkevents(pf, false); 3419 3420 otx2_unregister_dl(pf); 3421 unregister_netdev(netdev); 3422 cn10k_ipsec_clean(pf); 3423 cn10k_mcs_free(pf); 3424 otx2_sriov_disable(pf->pdev); 3425 otx2_sriov_vfcfg_cleanup(pf); 3426 if (pf->otx2_wq) 3427 destroy_workqueue(pf->otx2_wq); 3428 3429 otx2_ptp_destroy(pf); 3430 otx2_mcam_flow_del(pf); 3431 otx2_shutdown_tc(pf); 3432 otx2_shutdown_qos(pf); 3433 otx2_ndc_sync(pf); 3434 otx2_detach_resources(&pf->mbox); 3435 if (pf->hw.lmt_info) 3436 free_percpu(pf->hw.lmt_info); 3437 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3438 qmem_free(pf->dev, pf->dync_lmt); 3439 otx2_disable_mbox_intr(pf); 3440 otx2_pfaf_mbox_destroy(pf); 3441 pci_free_irq_vectors(pf->pdev); 3442 pci_set_drvdata(pdev, NULL); 3443 free_netdev(netdev); 3444 3445 pci_release_regions(pdev); 3446 } 3447 3448 static struct pci_driver otx2_pf_driver = { 3449 .name = DRV_NAME, 3450 .id_table = otx2_pf_id_table, 3451 .probe = otx2_probe, 3452 .shutdown = otx2_remove, 3453 .remove = otx2_remove, 3454 .sriov_configure = otx2_sriov_configure 3455 }; 3456 3457 static int __init otx2_rvupf_init_module(void) 3458 { 3459 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3460 3461 return pci_register_driver(&otx2_pf_driver); 3462 } 3463 3464 static void __exit otx2_rvupf_cleanup_module(void) 3465 { 3466 pci_unregister_driver(&otx2_pf_driver); 3467 } 3468 3469 module_init(otx2_rvupf_init_module); 3470 module_exit(otx2_rvupf_cleanup_module); 3471