1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 #include <linux/bitfield.h> 19 #include <net/page_pool/types.h> 20 21 #include "otx2_reg.h" 22 #include "otx2_common.h" 23 #include "otx2_txrx.h" 24 #include "otx2_struct.h" 25 #include "otx2_ptp.h" 26 #include "cn10k.h" 27 #include "qos.h" 28 #include <rvu_trace.h> 29 30 #define DRV_NAME "rvu_nicpf" 31 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 32 33 /* Supported devices */ 34 static const struct pci_device_id otx2_pf_id_table[] = { 35 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 36 { 0, } /* end of table */ 37 }; 38 39 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 40 MODULE_DESCRIPTION(DRV_STRING); 41 MODULE_LICENSE("GPL v2"); 42 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 43 44 static void otx2_vf_link_event_task(struct work_struct *work); 45 46 enum { 47 TYPE_PFAF, 48 TYPE_PFVF, 49 }; 50 51 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 52 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 53 54 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 55 { 56 struct otx2_nic *pf = netdev_priv(netdev); 57 bool if_up = netif_running(netdev); 58 int err = 0; 59 60 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 61 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 62 netdev->mtu); 63 return -EINVAL; 64 } 65 if (if_up) 66 otx2_stop(netdev); 67 68 netdev_info(netdev, "Changing MTU from %d to %d\n", 69 netdev->mtu, new_mtu); 70 netdev->mtu = new_mtu; 71 72 if (if_up) 73 err = otx2_open(netdev); 74 75 return err; 76 } 77 78 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 79 { 80 int irq, vfs = pf->total_vfs; 81 82 /* Disable VFs ME interrupts */ 83 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 84 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 85 free_irq(irq, pf); 86 87 /* Disable VFs FLR interrupts */ 88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 90 free_irq(irq, pf); 91 92 if (vfs <= 64) 93 return; 94 95 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 96 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 97 free_irq(irq, pf); 98 99 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 100 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 101 free_irq(irq, pf); 102 } 103 104 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 105 { 106 if (!pf->flr_wq) 107 return; 108 destroy_workqueue(pf->flr_wq); 109 pf->flr_wq = NULL; 110 devm_kfree(pf->dev, pf->flr_wrk); 111 } 112 113 static void otx2_flr_handler(struct work_struct *work) 114 { 115 struct flr_work *flrwork = container_of(work, struct flr_work, work); 116 struct otx2_nic *pf = flrwork->pf; 117 struct mbox *mbox = &pf->mbox; 118 struct msg_req *req; 119 int vf, reg = 0; 120 121 vf = flrwork - pf->flr_wrk; 122 123 mutex_lock(&mbox->lock); 124 req = otx2_mbox_alloc_msg_vf_flr(mbox); 125 if (!req) { 126 mutex_unlock(&mbox->lock); 127 return; 128 } 129 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 130 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 131 132 if (!otx2_sync_mbox_msg(&pf->mbox)) { 133 if (vf >= 64) { 134 reg = 1; 135 vf = vf - 64; 136 } 137 /* clear transcation pending bit */ 138 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 139 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 140 } 141 142 mutex_unlock(&mbox->lock); 143 } 144 145 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 146 { 147 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 148 int reg, dev, vf, start_vf, num_reg = 1; 149 u64 intr; 150 151 if (pf->total_vfs > 64) 152 num_reg = 2; 153 154 for (reg = 0; reg < num_reg; reg++) { 155 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 156 if (!intr) 157 continue; 158 start_vf = 64 * reg; 159 for (vf = 0; vf < 64; vf++) { 160 if (!(intr & BIT_ULL(vf))) 161 continue; 162 dev = vf + start_vf; 163 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 164 /* Clear interrupt */ 165 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 166 /* Disable the interrupt */ 167 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 168 BIT_ULL(vf)); 169 } 170 } 171 return IRQ_HANDLED; 172 } 173 174 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 175 { 176 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 177 int vf, reg, num_reg = 1; 178 u64 intr; 179 180 if (pf->total_vfs > 64) 181 num_reg = 2; 182 183 for (reg = 0; reg < num_reg; reg++) { 184 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 185 if (!intr) 186 continue; 187 for (vf = 0; vf < 64; vf++) { 188 if (!(intr & BIT_ULL(vf))) 189 continue; 190 /* clear trpend bit */ 191 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 192 /* clear interrupt */ 193 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 194 } 195 } 196 return IRQ_HANDLED; 197 } 198 199 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 200 { 201 struct otx2_hw *hw = &pf->hw; 202 char *irq_name; 203 int ret; 204 205 /* Register ME interrupt handler*/ 206 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 207 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 208 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 209 otx2_pf_me_intr_handler, 0, irq_name, pf); 210 if (ret) { 211 dev_err(pf->dev, 212 "RVUPF: IRQ registration failed for ME0\n"); 213 } 214 215 /* Register FLR interrupt handler */ 216 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 218 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 219 otx2_pf_flr_intr_handler, 0, irq_name, pf); 220 if (ret) { 221 dev_err(pf->dev, 222 "RVUPF: IRQ registration failed for FLR0\n"); 223 return ret; 224 } 225 226 if (numvfs > 64) { 227 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 228 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 229 rvu_get_pf(pf->pcifunc)); 230 ret = request_irq(pci_irq_vector 231 (pf->pdev, RVU_PF_INT_VEC_VFME1), 232 otx2_pf_me_intr_handler, 0, irq_name, pf); 233 if (ret) { 234 dev_err(pf->dev, 235 "RVUPF: IRQ registration failed for ME1\n"); 236 } 237 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 238 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 239 rvu_get_pf(pf->pcifunc)); 240 ret = request_irq(pci_irq_vector 241 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 242 otx2_pf_flr_intr_handler, 0, irq_name, pf); 243 if (ret) { 244 dev_err(pf->dev, 245 "RVUPF: IRQ registration failed for FLR1\n"); 246 return ret; 247 } 248 } 249 250 /* Enable ME interrupt for all VFs*/ 251 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 252 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 253 254 /* Enable FLR interrupt for all VFs*/ 255 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 256 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 257 258 if (numvfs > 64) { 259 numvfs -= 64; 260 261 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 262 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 263 INTR_MASK(numvfs)); 264 265 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 266 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 267 INTR_MASK(numvfs)); 268 } 269 return 0; 270 } 271 272 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 273 { 274 int vf; 275 276 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI); 277 if (!pf->flr_wq) 278 return -ENOMEM; 279 280 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 281 sizeof(struct flr_work), GFP_KERNEL); 282 if (!pf->flr_wrk) { 283 destroy_workqueue(pf->flr_wq); 284 return -ENOMEM; 285 } 286 287 for (vf = 0; vf < num_vfs; vf++) { 288 pf->flr_wrk[vf].pf = pf; 289 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 290 } 291 292 return 0; 293 } 294 295 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 296 int first, int mdevs, u64 intr, int type) 297 { 298 struct otx2_mbox_dev *mdev; 299 struct otx2_mbox *mbox; 300 struct mbox_hdr *hdr; 301 int i; 302 303 for (i = first; i < mdevs; i++) { 304 /* start from 0 */ 305 if (!(intr & BIT_ULL(i - first))) 306 continue; 307 308 mbox = &mw->mbox; 309 mdev = &mbox->dev[i]; 310 if (type == TYPE_PFAF) 311 otx2_sync_mbox_bbuf(mbox, i); 312 hdr = mdev->mbase + mbox->rx_start; 313 /* The hdr->num_msgs is set to zero immediately in the interrupt 314 * handler to ensure that it holds a correct value next time 315 * when the interrupt handler is called. 316 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 317 * pf>mbox.up_num_msgs holds the data for use in 318 * pfaf_mbox_up_handler. 319 */ 320 if (hdr->num_msgs) { 321 mw[i].num_msgs = hdr->num_msgs; 322 hdr->num_msgs = 0; 323 if (type == TYPE_PFAF) 324 memset(mbox->hwbase + mbox->rx_start, 0, 325 ALIGN(sizeof(struct mbox_hdr), 326 sizeof(u64))); 327 328 queue_work(mbox_wq, &mw[i].mbox_wrk); 329 } 330 331 mbox = &mw->mbox_up; 332 mdev = &mbox->dev[i]; 333 if (type == TYPE_PFAF) 334 otx2_sync_mbox_bbuf(mbox, i); 335 hdr = mdev->mbase + mbox->rx_start; 336 if (hdr->num_msgs) { 337 mw[i].up_num_msgs = hdr->num_msgs; 338 hdr->num_msgs = 0; 339 if (type == TYPE_PFAF) 340 memset(mbox->hwbase + mbox->rx_start, 0, 341 ALIGN(sizeof(struct mbox_hdr), 342 sizeof(u64))); 343 344 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 345 } 346 } 347 } 348 349 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 350 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 351 int devid) 352 { 353 struct otx2_mbox_dev *src_mdev = mdev; 354 int offset; 355 356 /* Msgs are already copied, trigger VF's mbox irq */ 357 smp_wmb(); 358 359 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 360 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 361 362 /* Restore VF's mbox bounce buffer region address */ 363 src_mdev->mbase = bbuf_base; 364 } 365 366 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 367 struct otx2_mbox *src_mbox, 368 int dir, int vf, int num_msgs) 369 { 370 struct otx2_mbox_dev *src_mdev, *dst_mdev; 371 struct mbox_hdr *mbox_hdr; 372 struct mbox_hdr *req_hdr; 373 struct mbox *dst_mbox; 374 int dst_size, err; 375 376 if (dir == MBOX_DIR_PFAF) { 377 /* Set VF's mailbox memory as PF's bounce buffer memory, so 378 * that explicit copying of VF's msgs to PF=>AF mbox region 379 * and AF=>PF responses to VF's mbox region can be avoided. 380 */ 381 src_mdev = &src_mbox->dev[vf]; 382 mbox_hdr = src_mbox->hwbase + 383 src_mbox->rx_start + (vf * MBOX_SIZE); 384 385 dst_mbox = &pf->mbox; 386 dst_size = dst_mbox->mbox.tx_size - 387 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 388 /* Check if msgs fit into destination area and has valid size */ 389 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 390 return -EINVAL; 391 392 dst_mdev = &dst_mbox->mbox.dev[0]; 393 394 mutex_lock(&pf->mbox.lock); 395 dst_mdev->mbase = src_mdev->mbase; 396 dst_mdev->msg_size = mbox_hdr->msg_size; 397 dst_mdev->num_msgs = num_msgs; 398 err = otx2_sync_mbox_msg(dst_mbox); 399 /* Error code -EIO indicate there is a communication failure 400 * to the AF. Rest of the error codes indicate that AF processed 401 * VF messages and set the error codes in response messages 402 * (if any) so simply forward responses to VF. 403 */ 404 if (err == -EIO) { 405 dev_warn(pf->dev, 406 "AF not responding to VF%d messages\n", vf); 407 /* restore PF mbase and exit */ 408 dst_mdev->mbase = pf->mbox.bbuf_base; 409 mutex_unlock(&pf->mbox.lock); 410 return err; 411 } 412 /* At this point, all the VF messages sent to AF are acked 413 * with proper responses and responses are copied to VF 414 * mailbox hence raise interrupt to VF. 415 */ 416 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 417 dst_mbox->mbox.rx_start); 418 req_hdr->num_msgs = num_msgs; 419 420 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 421 pf->mbox.bbuf_base, vf); 422 mutex_unlock(&pf->mbox.lock); 423 } else if (dir == MBOX_DIR_PFVF_UP) { 424 src_mdev = &src_mbox->dev[0]; 425 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 426 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 427 src_mbox->rx_start); 428 req_hdr->num_msgs = num_msgs; 429 430 dst_mbox = &pf->mbox_pfvf[0]; 431 dst_size = dst_mbox->mbox_up.tx_size - 432 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 433 /* Check if msgs fit into destination area */ 434 if (mbox_hdr->msg_size > dst_size) 435 return -EINVAL; 436 437 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 438 dst_mdev->mbase = src_mdev->mbase; 439 dst_mdev->msg_size = mbox_hdr->msg_size; 440 dst_mdev->num_msgs = mbox_hdr->num_msgs; 441 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 442 if (err) { 443 dev_warn(pf->dev, 444 "VF%d is not responding to mailbox\n", vf); 445 return err; 446 } 447 } else if (dir == MBOX_DIR_VFPF_UP) { 448 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 449 src_mbox->rx_start); 450 req_hdr->num_msgs = num_msgs; 451 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 452 &pf->mbox.mbox_up, 453 pf->mbox_pfvf[vf].bbuf_base, 454 0); 455 } 456 457 return 0; 458 } 459 460 static void otx2_pfvf_mbox_handler(struct work_struct *work) 461 { 462 struct mbox_msghdr *msg = NULL; 463 int offset, vf_idx, id, err; 464 struct otx2_mbox_dev *mdev; 465 struct mbox_hdr *req_hdr; 466 struct otx2_mbox *mbox; 467 struct mbox *vf_mbox; 468 struct otx2_nic *pf; 469 470 vf_mbox = container_of(work, struct mbox, mbox_wrk); 471 pf = vf_mbox->pfvf; 472 vf_idx = vf_mbox - pf->mbox_pfvf; 473 474 mbox = &pf->mbox_pfvf[0].mbox; 475 mdev = &mbox->dev[vf_idx]; 476 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 477 478 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 479 480 for (id = 0; id < vf_mbox->num_msgs; id++) { 481 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 482 offset); 483 484 if (msg->sig != OTX2_MBOX_REQ_SIG) 485 goto inval_msg; 486 487 /* Set VF's number in each of the msg */ 488 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 489 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 490 offset = msg->next_msgoff; 491 } 492 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 493 vf_mbox->num_msgs); 494 if (err) 495 goto inval_msg; 496 return; 497 498 inval_msg: 499 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 500 otx2_mbox_msg_send(mbox, vf_idx); 501 } 502 503 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 504 { 505 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 506 struct otx2_nic *pf = vf_mbox->pfvf; 507 struct otx2_mbox_dev *mdev; 508 int offset, id, vf_idx = 0; 509 struct mbox_hdr *rsp_hdr; 510 struct mbox_msghdr *msg; 511 struct otx2_mbox *mbox; 512 513 vf_idx = vf_mbox - pf->mbox_pfvf; 514 mbox = &pf->mbox_pfvf[0].mbox_up; 515 mdev = &mbox->dev[vf_idx]; 516 517 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 518 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 519 520 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 521 msg = mdev->mbase + offset; 522 523 if (msg->id >= MBOX_MSG_MAX) { 524 dev_err(pf->dev, 525 "Mbox msg with unknown ID 0x%x\n", msg->id); 526 goto end; 527 } 528 529 if (msg->sig != OTX2_MBOX_RSP_SIG) { 530 dev_err(pf->dev, 531 "Mbox msg with wrong signature %x, ID 0x%x\n", 532 msg->sig, msg->id); 533 goto end; 534 } 535 536 switch (msg->id) { 537 case MBOX_MSG_CGX_LINK_EVENT: 538 break; 539 default: 540 if (msg->rc) 541 dev_err(pf->dev, 542 "Mbox msg response has err %d, ID 0x%x\n", 543 msg->rc, msg->id); 544 break; 545 } 546 547 end: 548 offset = mbox->rx_start + msg->next_msgoff; 549 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 550 __otx2_mbox_reset(mbox, 0); 551 mdev->msgs_acked++; 552 } 553 } 554 555 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 556 { 557 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 558 int vfs = pf->total_vfs; 559 struct mbox *mbox; 560 u64 intr; 561 562 mbox = pf->mbox_pfvf; 563 /* Handle VF interrupts */ 564 if (vfs > 64) { 565 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 566 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 567 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 568 TYPE_PFVF); 569 vfs -= 64; 570 } 571 572 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 573 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 574 575 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 576 577 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 578 579 return IRQ_HANDLED; 580 } 581 582 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 583 { 584 void __iomem *hwbase; 585 struct mbox *mbox; 586 int err, vf; 587 u64 base; 588 589 if (!numvfs) 590 return -EINVAL; 591 592 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 593 sizeof(struct mbox), GFP_KERNEL); 594 if (!pf->mbox_pfvf) 595 return -ENOMEM; 596 597 pf->mbox_pfvf_wq = alloc_ordered_workqueue("otx2_pfvf_mailbox", 598 WQ_HIGHPRI | WQ_MEM_RECLAIM); 599 if (!pf->mbox_pfvf_wq) 600 return -ENOMEM; 601 602 /* On CN10K platform, PF <-> VF mailbox region follows after 603 * PF <-> AF mailbox region. 604 */ 605 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 606 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 607 MBOX_SIZE; 608 else 609 base = readq((void __iomem *)((u64)pf->reg_base + 610 RVU_PF_VF_BAR4_ADDR)); 611 612 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 613 if (!hwbase) { 614 err = -ENOMEM; 615 goto free_wq; 616 } 617 618 mbox = &pf->mbox_pfvf[0]; 619 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 620 MBOX_DIR_PFVF, numvfs); 621 if (err) 622 goto free_iomem; 623 624 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 625 MBOX_DIR_PFVF_UP, numvfs); 626 if (err) 627 goto free_iomem; 628 629 for (vf = 0; vf < numvfs; vf++) { 630 mbox->pfvf = pf; 631 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 632 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 633 mbox++; 634 } 635 636 return 0; 637 638 free_iomem: 639 if (hwbase) 640 iounmap(hwbase); 641 free_wq: 642 destroy_workqueue(pf->mbox_pfvf_wq); 643 return err; 644 } 645 646 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 647 { 648 struct mbox *mbox = &pf->mbox_pfvf[0]; 649 650 if (!mbox) 651 return; 652 653 if (pf->mbox_pfvf_wq) { 654 destroy_workqueue(pf->mbox_pfvf_wq); 655 pf->mbox_pfvf_wq = NULL; 656 } 657 658 if (mbox->mbox.hwbase) 659 iounmap(mbox->mbox.hwbase); 660 661 otx2_mbox_destroy(&mbox->mbox); 662 } 663 664 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 665 { 666 /* Clear PF <=> VF mailbox IRQ */ 667 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 668 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 669 670 /* Enable PF <=> VF mailbox IRQ */ 671 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 672 if (numvfs > 64) { 673 numvfs -= 64; 674 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 675 INTR_MASK(numvfs)); 676 } 677 } 678 679 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 680 { 681 int vector; 682 683 /* Disable PF <=> VF mailbox IRQ */ 684 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 685 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 686 687 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 688 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 689 free_irq(vector, pf); 690 691 if (numvfs > 64) { 692 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 693 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 694 free_irq(vector, pf); 695 } 696 } 697 698 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 699 { 700 struct otx2_hw *hw = &pf->hw; 701 char *irq_name; 702 int err; 703 704 /* Register MBOX0 interrupt handler */ 705 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 706 if (pf->pcifunc) 707 snprintf(irq_name, NAME_SIZE, 708 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 709 else 710 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 711 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 712 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 713 if (err) { 714 dev_err(pf->dev, 715 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 716 return err; 717 } 718 719 if (numvfs > 64) { 720 /* Register MBOX1 interrupt handler */ 721 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 722 if (pf->pcifunc) 723 snprintf(irq_name, NAME_SIZE, 724 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 725 else 726 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 727 err = request_irq(pci_irq_vector(pf->pdev, 728 RVU_PF_INT_VEC_VFPF_MBOX1), 729 otx2_pfvf_mbox_intr_handler, 730 0, irq_name, pf); 731 if (err) { 732 dev_err(pf->dev, 733 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 734 return err; 735 } 736 } 737 738 otx2_enable_pfvf_mbox_intr(pf, numvfs); 739 740 return 0; 741 } 742 743 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 744 struct mbox_msghdr *msg) 745 { 746 int devid; 747 748 if (msg->id >= MBOX_MSG_MAX) { 749 dev_err(pf->dev, 750 "Mbox msg with unknown ID 0x%x\n", msg->id); 751 return; 752 } 753 754 if (msg->sig != OTX2_MBOX_RSP_SIG) { 755 dev_err(pf->dev, 756 "Mbox msg with wrong signature %x, ID 0x%x\n", 757 msg->sig, msg->id); 758 return; 759 } 760 761 /* message response heading VF */ 762 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 763 if (devid) { 764 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 765 struct delayed_work *dwork; 766 767 switch (msg->id) { 768 case MBOX_MSG_NIX_LF_START_RX: 769 config->intf_down = false; 770 dwork = &config->link_event_work; 771 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 772 break; 773 case MBOX_MSG_NIX_LF_STOP_RX: 774 config->intf_down = true; 775 break; 776 } 777 778 return; 779 } 780 781 switch (msg->id) { 782 case MBOX_MSG_READY: 783 pf->pcifunc = msg->pcifunc; 784 break; 785 case MBOX_MSG_MSIX_OFFSET: 786 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 787 break; 788 case MBOX_MSG_NPA_LF_ALLOC: 789 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 790 break; 791 case MBOX_MSG_NIX_LF_ALLOC: 792 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 793 break; 794 case MBOX_MSG_NIX_BP_ENABLE: 795 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 796 break; 797 case MBOX_MSG_CGX_STATS: 798 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 799 break; 800 case MBOX_MSG_CGX_FEC_STATS: 801 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 802 break; 803 default: 804 if (msg->rc) 805 dev_err(pf->dev, 806 "Mbox msg response has err %d, ID 0x%x\n", 807 msg->rc, msg->id); 808 break; 809 } 810 } 811 812 static void otx2_pfaf_mbox_handler(struct work_struct *work) 813 { 814 struct otx2_mbox_dev *mdev; 815 struct mbox_hdr *rsp_hdr; 816 struct mbox_msghdr *msg; 817 struct otx2_mbox *mbox; 818 struct mbox *af_mbox; 819 struct otx2_nic *pf; 820 int offset, id; 821 822 af_mbox = container_of(work, struct mbox, mbox_wrk); 823 mbox = &af_mbox->mbox; 824 mdev = &mbox->dev[0]; 825 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 826 827 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 828 pf = af_mbox->pfvf; 829 830 for (id = 0; id < af_mbox->num_msgs; id++) { 831 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 832 otx2_process_pfaf_mbox_msg(pf, msg); 833 offset = mbox->rx_start + msg->next_msgoff; 834 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 835 __otx2_mbox_reset(mbox, 0); 836 mdev->msgs_acked++; 837 } 838 839 } 840 841 static void otx2_handle_link_event(struct otx2_nic *pf) 842 { 843 struct cgx_link_user_info *linfo = &pf->linfo; 844 struct net_device *netdev = pf->netdev; 845 846 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 847 linfo->link_up ? "UP" : "DOWN", linfo->speed, 848 linfo->full_duplex ? "Full" : "Half"); 849 if (linfo->link_up) { 850 netif_carrier_on(netdev); 851 netif_tx_start_all_queues(netdev); 852 } else { 853 netif_tx_stop_all_queues(netdev); 854 netif_carrier_off(netdev); 855 } 856 } 857 858 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 859 struct mcs_intr_info *event, 860 struct msg_rsp *rsp) 861 { 862 cn10k_handle_mcs_event(pf, event); 863 864 return 0; 865 } 866 867 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 868 struct cgx_link_info_msg *msg, 869 struct msg_rsp *rsp) 870 { 871 int i; 872 873 /* Copy the link info sent by AF */ 874 pf->linfo = msg->link_info; 875 876 /* notify VFs about link event */ 877 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 878 struct otx2_vf_config *config = &pf->vf_configs[i]; 879 struct delayed_work *dwork = &config->link_event_work; 880 881 if (config->intf_down) 882 continue; 883 884 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 885 } 886 887 /* interface has not been fully configured yet */ 888 if (pf->flags & OTX2_FLAG_INTF_DOWN) 889 return 0; 890 891 otx2_handle_link_event(pf); 892 return 0; 893 } 894 895 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 896 struct mbox_msghdr *req) 897 { 898 /* Check if valid, if not reply with a invalid msg */ 899 if (req->sig != OTX2_MBOX_REQ_SIG) { 900 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 901 return -ENODEV; 902 } 903 904 switch (req->id) { 905 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 906 case _id: { \ 907 struct _rsp_type *rsp; \ 908 int err; \ 909 \ 910 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 911 &pf->mbox.mbox_up, 0, \ 912 sizeof(struct _rsp_type)); \ 913 if (!rsp) \ 914 return -ENOMEM; \ 915 \ 916 rsp->hdr.id = _id; \ 917 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 918 rsp->hdr.pcifunc = 0; \ 919 rsp->hdr.rc = 0; \ 920 \ 921 err = otx2_mbox_up_handler_ ## _fn_name( \ 922 pf, (struct _req_type *)req, rsp); \ 923 return err; \ 924 } 925 MBOX_UP_CGX_MESSAGES 926 MBOX_UP_MCS_MESSAGES 927 #undef M 928 break; 929 default: 930 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 931 return -ENODEV; 932 } 933 return 0; 934 } 935 936 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 937 { 938 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 939 struct otx2_mbox *mbox = &af_mbox->mbox_up; 940 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 941 struct otx2_nic *pf = af_mbox->pfvf; 942 int offset, id, devid = 0; 943 struct mbox_hdr *rsp_hdr; 944 struct mbox_msghdr *msg; 945 946 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 947 948 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 949 950 for (id = 0; id < af_mbox->up_num_msgs; id++) { 951 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 952 953 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 954 /* Skip processing VF's messages */ 955 if (!devid) 956 otx2_process_mbox_msg_up(pf, msg); 957 offset = mbox->rx_start + msg->next_msgoff; 958 } 959 if (devid) { 960 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 961 MBOX_DIR_PFVF_UP, devid - 1, 962 af_mbox->up_num_msgs); 963 return; 964 } 965 966 otx2_mbox_msg_send(mbox, 0); 967 } 968 969 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 970 { 971 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 972 struct mbox *mbox; 973 974 /* Clear the IRQ */ 975 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 976 977 mbox = &pf->mbox; 978 979 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 980 981 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 982 983 return IRQ_HANDLED; 984 } 985 986 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 987 { 988 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 989 990 /* Disable AF => PF mailbox IRQ */ 991 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 992 free_irq(vector, pf); 993 } 994 995 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 996 { 997 struct otx2_hw *hw = &pf->hw; 998 struct msg_req *req; 999 char *irq_name; 1000 int err; 1001 1002 /* Register mailbox interrupt handler */ 1003 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1004 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 1005 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1006 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1007 if (err) { 1008 dev_err(pf->dev, 1009 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1010 return err; 1011 } 1012 1013 /* Enable mailbox interrupt for msgs coming from AF. 1014 * First clear to avoid spurious interrupts, if any. 1015 */ 1016 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1017 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1018 1019 if (!probe_af) 1020 return 0; 1021 1022 /* Check mailbox communication with AF */ 1023 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1024 if (!req) { 1025 otx2_disable_mbox_intr(pf); 1026 return -ENOMEM; 1027 } 1028 err = otx2_sync_mbox_msg(&pf->mbox); 1029 if (err) { 1030 dev_warn(pf->dev, 1031 "AF not responding to mailbox, deferring probe\n"); 1032 otx2_disable_mbox_intr(pf); 1033 return -EPROBE_DEFER; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1040 { 1041 struct mbox *mbox = &pf->mbox; 1042 1043 if (pf->mbox_wq) { 1044 destroy_workqueue(pf->mbox_wq); 1045 pf->mbox_wq = NULL; 1046 } 1047 1048 if (mbox->mbox.hwbase) 1049 iounmap((void __iomem *)mbox->mbox.hwbase); 1050 1051 otx2_mbox_destroy(&mbox->mbox); 1052 otx2_mbox_destroy(&mbox->mbox_up); 1053 } 1054 1055 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1056 { 1057 struct mbox *mbox = &pf->mbox; 1058 void __iomem *hwbase; 1059 int err; 1060 1061 mbox->pfvf = pf; 1062 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox", 1063 WQ_HIGHPRI | WQ_MEM_RECLAIM); 1064 if (!pf->mbox_wq) 1065 return -ENOMEM; 1066 1067 /* Mailbox is a reserved memory (in RAM) region shared between 1068 * admin function (i.e AF) and this PF, shouldn't be mapped as 1069 * device memory to allow unaligned accesses. 1070 */ 1071 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1072 MBOX_SIZE); 1073 if (!hwbase) { 1074 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1075 err = -ENOMEM; 1076 goto exit; 1077 } 1078 1079 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1080 MBOX_DIR_PFAF, 1); 1081 if (err) 1082 goto exit; 1083 1084 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1085 MBOX_DIR_PFAF_UP, 1); 1086 if (err) 1087 goto exit; 1088 1089 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1090 if (err) 1091 goto exit; 1092 1093 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1094 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1095 mutex_init(&mbox->lock); 1096 1097 return 0; 1098 exit: 1099 otx2_pfaf_mbox_destroy(pf); 1100 return err; 1101 } 1102 1103 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1104 { 1105 struct msg_req *msg; 1106 int err; 1107 1108 mutex_lock(&pf->mbox.lock); 1109 if (enable) 1110 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1111 else 1112 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1113 1114 if (!msg) { 1115 mutex_unlock(&pf->mbox.lock); 1116 return -ENOMEM; 1117 } 1118 1119 err = otx2_sync_mbox_msg(&pf->mbox); 1120 mutex_unlock(&pf->mbox.lock); 1121 return err; 1122 } 1123 1124 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1125 { 1126 struct msg_req *msg; 1127 int err; 1128 1129 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1130 pf->flow_cfg->dmacflt_max_flows)) 1131 netdev_warn(pf->netdev, 1132 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1133 1134 mutex_lock(&pf->mbox.lock); 1135 if (enable) 1136 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1137 else 1138 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1139 1140 if (!msg) { 1141 mutex_unlock(&pf->mbox.lock); 1142 return -ENOMEM; 1143 } 1144 1145 err = otx2_sync_mbox_msg(&pf->mbox); 1146 mutex_unlock(&pf->mbox.lock); 1147 return err; 1148 } 1149 1150 int otx2_set_real_num_queues(struct net_device *netdev, 1151 int tx_queues, int rx_queues) 1152 { 1153 int err; 1154 1155 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1156 if (err) { 1157 netdev_err(netdev, 1158 "Failed to set no of Tx queues: %d\n", tx_queues); 1159 return err; 1160 } 1161 1162 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1163 if (err) 1164 netdev_err(netdev, 1165 "Failed to set no of Rx queues: %d\n", rx_queues); 1166 return err; 1167 } 1168 EXPORT_SYMBOL(otx2_set_real_num_queues); 1169 1170 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = { 1171 "NIX_SQOPERR_OOR", 1172 "NIX_SQOPERR_CTX_FAULT", 1173 "NIX_SQOPERR_CTX_POISON", 1174 "NIX_SQOPERR_DISABLED", 1175 "NIX_SQOPERR_SIZE_ERR", 1176 "NIX_SQOPERR_OFLOW", 1177 "NIX_SQOPERR_SQB_NULL", 1178 "NIX_SQOPERR_SQB_FAULT", 1179 "NIX_SQOPERR_SQE_SZ_ZERO", 1180 }; 1181 1182 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = { 1183 "NIX_MNQERR_SQ_CTX_FAULT", 1184 "NIX_MNQERR_SQ_CTX_POISON", 1185 "NIX_MNQERR_SQB_FAULT", 1186 "NIX_MNQERR_SQB_POISON", 1187 "NIX_MNQERR_TOTAL_ERR", 1188 "NIX_MNQERR_LSO_ERR", 1189 "NIX_MNQERR_CQ_QUERY_ERR", 1190 "NIX_MNQERR_MAX_SQE_SIZE_ERR", 1191 "NIX_MNQERR_MAXLEN_ERR", 1192 "NIX_MNQERR_SQE_SIZEM1_ZERO", 1193 }; 1194 1195 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = { 1196 [NIX_SND_STATUS_GOOD] = "NIX_SND_STATUS_GOOD", 1197 [NIX_SND_STATUS_SQ_CTX_FAULT] = "NIX_SND_STATUS_SQ_CTX_FAULT", 1198 [NIX_SND_STATUS_SQ_CTX_POISON] = "NIX_SND_STATUS_SQ_CTX_POISON", 1199 [NIX_SND_STATUS_SQB_FAULT] = "NIX_SND_STATUS_SQB_FAULT", 1200 [NIX_SND_STATUS_SQB_POISON] = "NIX_SND_STATUS_SQB_POISON", 1201 [NIX_SND_STATUS_HDR_ERR] = "NIX_SND_STATUS_HDR_ERR", 1202 [NIX_SND_STATUS_EXT_ERR] = "NIX_SND_STATUS_EXT_ERR", 1203 [NIX_SND_STATUS_JUMP_FAULT] = "NIX_SND_STATUS_JUMP_FAULT", 1204 [NIX_SND_STATUS_JUMP_POISON] = "NIX_SND_STATUS_JUMP_POISON", 1205 [NIX_SND_STATUS_CRC_ERR] = "NIX_SND_STATUS_CRC_ERR", 1206 [NIX_SND_STATUS_IMM_ERR] = "NIX_SND_STATUS_IMM_ERR", 1207 [NIX_SND_STATUS_SG_ERR] = "NIX_SND_STATUS_SG_ERR", 1208 [NIX_SND_STATUS_MEM_ERR] = "NIX_SND_STATUS_MEM_ERR", 1209 [NIX_SND_STATUS_INVALID_SUBDC] = "NIX_SND_STATUS_INVALID_SUBDC", 1210 [NIX_SND_STATUS_SUBDC_ORDER_ERR] = "NIX_SND_STATUS_SUBDC_ORDER_ERR", 1211 [NIX_SND_STATUS_DATA_FAULT] = "NIX_SND_STATUS_DATA_FAULT", 1212 [NIX_SND_STATUS_DATA_POISON] = "NIX_SND_STATUS_DATA_POISON", 1213 [NIX_SND_STATUS_NPC_DROP_ACTION] = "NIX_SND_STATUS_NPC_DROP_ACTION", 1214 [NIX_SND_STATUS_LOCK_VIOL] = "NIX_SND_STATUS_LOCK_VIOL", 1215 [NIX_SND_STATUS_NPC_UCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_UCAST_CHAN_ERR", 1216 [NIX_SND_STATUS_NPC_MCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_MCAST_CHAN_ERR", 1217 [NIX_SND_STATUS_NPC_MCAST_ABORT] = "NIX_SND_STATUS_NPC_MCAST_ABORT", 1218 [NIX_SND_STATUS_NPC_VTAG_PTR_ERR] = "NIX_SND_STATUS_NPC_VTAG_PTR_ERR", 1219 [NIX_SND_STATUS_NPC_VTAG_SIZE_ERR] = "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR", 1220 [NIX_SND_STATUS_SEND_MEM_FAULT] = "NIX_SND_STATUS_SEND_MEM_FAULT", 1221 [NIX_SND_STATUS_SEND_STATS_ERR] = "NIX_SND_STATUS_SEND_STATS_ERR", 1222 }; 1223 1224 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1225 { 1226 struct otx2_nic *pf = data; 1227 struct otx2_snd_queue *sq; 1228 u64 val, *ptr; 1229 u64 qidx = 0; 1230 1231 /* CQ */ 1232 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1233 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1234 val = otx2_atomic64_add((qidx << 44), ptr); 1235 1236 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1237 (val & NIX_CQERRINT_BITS)); 1238 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1239 continue; 1240 1241 if (val & BIT_ULL(42)) { 1242 netdev_err(pf->netdev, 1243 "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1244 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1245 } else { 1246 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1247 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1248 qidx); 1249 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1250 netdev_err(pf->netdev, 1251 "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1252 qidx); 1253 } 1254 1255 schedule_work(&pf->reset_task); 1256 } 1257 1258 /* SQ */ 1259 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1260 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg; 1261 u8 sq_op_err_code, mnq_err_code, snd_err_code; 1262 1263 sq = &pf->qset.sq[qidx]; 1264 if (!sq->sqb_ptrs) 1265 continue; 1266 1267 /* Below debug registers captures first errors corresponding to 1268 * those registers. We don't have to check against SQ qid as 1269 * these are fatal errors. 1270 */ 1271 1272 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1273 val = otx2_atomic64_add((qidx << 44), ptr); 1274 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1275 (val & NIX_SQINT_BITS)); 1276 1277 if (val & BIT_ULL(42)) { 1278 netdev_err(pf->netdev, 1279 "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1280 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1281 goto done; 1282 } 1283 1284 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG); 1285 if (!(sq_op_err_dbg & BIT(44))) 1286 goto chk_mnq_err_dbg; 1287 1288 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg); 1289 netdev_err(pf->netdev, 1290 "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(0x%llx) err=%s(%#x)\n", 1291 qidx, sq_op_err_dbg, 1292 nix_sqoperr_e_str[sq_op_err_code], 1293 sq_op_err_code); 1294 1295 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44)); 1296 1297 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL) 1298 goto chk_mnq_err_dbg; 1299 1300 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure. 1301 * TODO: But we are in irq context. How to call mbox functions which does sleep 1302 */ 1303 1304 chk_mnq_err_dbg: 1305 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG); 1306 if (!(mnq_err_dbg & BIT(44))) 1307 goto chk_snd_err_dbg; 1308 1309 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg); 1310 netdev_err(pf->netdev, 1311 "SQ%lld: NIX_LF_MNQ_ERR_DBG(0x%llx) err=%s(%#x)\n", 1312 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code], 1313 mnq_err_code); 1314 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44)); 1315 1316 chk_snd_err_dbg: 1317 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG); 1318 if (snd_err_dbg & BIT(44)) { 1319 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg); 1320 netdev_err(pf->netdev, 1321 "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s(%#x)\n", 1322 qidx, snd_err_dbg, 1323 nix_snd_status_e_str[snd_err_code], 1324 snd_err_code); 1325 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44)); 1326 } 1327 1328 done: 1329 /* Print values and reset */ 1330 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1331 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1332 qidx); 1333 1334 schedule_work(&pf->reset_task); 1335 } 1336 1337 return IRQ_HANDLED; 1338 } 1339 1340 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1341 { 1342 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1343 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1344 int qidx = cq_poll->cint_idx; 1345 1346 /* Disable interrupts. 1347 * 1348 * Completion interrupts behave in a level-triggered interrupt 1349 * fashion, and hence have to be cleared only after it is serviced. 1350 */ 1351 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1352 1353 /* Schedule NAPI */ 1354 pf->napi_events++; 1355 napi_schedule_irqoff(&cq_poll->napi); 1356 1357 return IRQ_HANDLED; 1358 } 1359 1360 static void otx2_disable_napi(struct otx2_nic *pf) 1361 { 1362 struct otx2_qset *qset = &pf->qset; 1363 struct otx2_cq_poll *cq_poll; 1364 int qidx; 1365 1366 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1367 cq_poll = &qset->napi[qidx]; 1368 cancel_work_sync(&cq_poll->dim.work); 1369 napi_disable(&cq_poll->napi); 1370 netif_napi_del(&cq_poll->napi); 1371 } 1372 } 1373 1374 static void otx2_free_cq_res(struct otx2_nic *pf) 1375 { 1376 struct otx2_qset *qset = &pf->qset; 1377 struct otx2_cq_queue *cq; 1378 int qidx; 1379 1380 /* Disable CQs */ 1381 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1382 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1383 cq = &qset->cq[qidx]; 1384 qmem_free(pf->dev, cq->cqe); 1385 } 1386 } 1387 1388 static void otx2_free_sq_res(struct otx2_nic *pf) 1389 { 1390 struct otx2_qset *qset = &pf->qset; 1391 struct otx2_snd_queue *sq; 1392 int qidx; 1393 1394 /* Disable SQs */ 1395 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1396 /* Free SQB pointers */ 1397 otx2_sq_free_sqbs(pf); 1398 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1399 sq = &qset->sq[qidx]; 1400 /* Skip freeing Qos queues if they are not initialized */ 1401 if (!sq->sqe) 1402 continue; 1403 qmem_free(pf->dev, sq->sqe); 1404 qmem_free(pf->dev, sq->tso_hdrs); 1405 kfree(sq->sg); 1406 kfree(sq->sqb_ptrs); 1407 } 1408 } 1409 1410 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1411 { 1412 int frame_size; 1413 int total_size; 1414 int rbuf_size; 1415 1416 if (pf->hw.rbuf_len) 1417 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1418 1419 /* The data transferred by NIX to memory consists of actual packet 1420 * plus additional data which has timestamp and/or EDSA/HIGIG2 1421 * headers if interface is configured in corresponding modes. 1422 * NIX transfers entire data using 6 segments/buffers and writes 1423 * a CQE_RX descriptor with those segment addresses. First segment 1424 * has additional data prepended to packet. Also software omits a 1425 * headroom of 128 bytes in each segment. Hence the total size of 1426 * memory needed to receive a packet with 'mtu' is: 1427 * frame size = mtu + additional data; 1428 * memory = frame_size + headroom * 6; 1429 * each receive buffer size = memory / 6; 1430 */ 1431 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1432 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1433 rbuf_size = total_size / 6; 1434 1435 return ALIGN(rbuf_size, 2048); 1436 } 1437 1438 static int otx2_init_hw_resources(struct otx2_nic *pf) 1439 { 1440 struct nix_lf_free_req *free_req; 1441 struct mbox *mbox = &pf->mbox; 1442 struct otx2_hw *hw = &pf->hw; 1443 struct msg_req *req; 1444 int err = 0, lvl; 1445 1446 /* Set required NPA LF's pool counts 1447 * Auras and Pools are used in a 1:1 mapping, 1448 * so, aura count = pool count. 1449 */ 1450 hw->rqpool_cnt = hw->rx_queues; 1451 hw->sqpool_cnt = otx2_get_total_tx_queues(pf); 1452 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1453 1454 /* Maximum hardware supported transmit length */ 1455 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1456 1457 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1458 1459 mutex_lock(&mbox->lock); 1460 /* NPA init */ 1461 err = otx2_config_npa(pf); 1462 if (err) 1463 goto exit; 1464 1465 /* NIX init */ 1466 err = otx2_config_nix(pf); 1467 if (err) 1468 goto err_free_npa_lf; 1469 1470 /* Enable backpressure for CGX mapped PF/VFs */ 1471 if (!is_otx2_lbkvf(pf->pdev)) 1472 otx2_nix_config_bp(pf, true); 1473 1474 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1475 err = otx2_rq_aura_pool_init(pf); 1476 if (err) { 1477 mutex_unlock(&mbox->lock); 1478 goto err_free_nix_lf; 1479 } 1480 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1481 err = otx2_sq_aura_pool_init(pf); 1482 if (err) { 1483 mutex_unlock(&mbox->lock); 1484 goto err_free_rq_ptrs; 1485 } 1486 1487 err = otx2_txsch_alloc(pf); 1488 if (err) { 1489 mutex_unlock(&mbox->lock); 1490 goto err_free_sq_ptrs; 1491 } 1492 1493 #ifdef CONFIG_DCB 1494 if (pf->pfc_en) { 1495 err = otx2_pfc_txschq_alloc(pf); 1496 if (err) { 1497 mutex_unlock(&mbox->lock); 1498 goto err_free_sq_ptrs; 1499 } 1500 } 1501 #endif 1502 1503 err = otx2_config_nix_queues(pf); 1504 if (err) { 1505 mutex_unlock(&mbox->lock); 1506 goto err_free_txsch; 1507 } 1508 1509 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1510 err = otx2_txschq_config(pf, lvl, 0, false); 1511 if (err) { 1512 mutex_unlock(&mbox->lock); 1513 goto err_free_nix_queues; 1514 } 1515 } 1516 1517 #ifdef CONFIG_DCB 1518 if (pf->pfc_en) { 1519 err = otx2_pfc_txschq_config(pf); 1520 if (err) { 1521 mutex_unlock(&mbox->lock); 1522 goto err_free_nix_queues; 1523 } 1524 } 1525 #endif 1526 1527 mutex_unlock(&mbox->lock); 1528 return err; 1529 1530 err_free_nix_queues: 1531 otx2_free_sq_res(pf); 1532 otx2_free_cq_res(pf); 1533 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1534 err_free_txsch: 1535 otx2_txschq_stop(pf); 1536 err_free_sq_ptrs: 1537 otx2_sq_free_sqbs(pf); 1538 err_free_rq_ptrs: 1539 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1540 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1541 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1542 otx2_aura_pool_free(pf); 1543 err_free_nix_lf: 1544 mutex_lock(&mbox->lock); 1545 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1546 if (free_req) { 1547 free_req->flags = NIX_LF_DISABLE_FLOWS; 1548 if (otx2_sync_mbox_msg(mbox)) 1549 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1550 } 1551 err_free_npa_lf: 1552 /* Reset NPA LF */ 1553 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1554 if (req) { 1555 if (otx2_sync_mbox_msg(mbox)) 1556 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1557 } 1558 exit: 1559 mutex_unlock(&mbox->lock); 1560 return err; 1561 } 1562 1563 static void otx2_free_hw_resources(struct otx2_nic *pf) 1564 { 1565 struct otx2_qset *qset = &pf->qset; 1566 struct nix_lf_free_req *free_req; 1567 struct mbox *mbox = &pf->mbox; 1568 struct otx2_cq_queue *cq; 1569 struct otx2_pool *pool; 1570 struct msg_req *req; 1571 int pool_id; 1572 int qidx; 1573 1574 /* Ensure all SQE are processed */ 1575 otx2_sqb_flush(pf); 1576 1577 /* Stop transmission */ 1578 otx2_txschq_stop(pf); 1579 1580 #ifdef CONFIG_DCB 1581 if (pf->pfc_en) 1582 otx2_pfc_txschq_stop(pf); 1583 #endif 1584 1585 otx2_clean_qos_queues(pf); 1586 1587 mutex_lock(&mbox->lock); 1588 /* Disable backpressure */ 1589 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1590 otx2_nix_config_bp(pf, false); 1591 mutex_unlock(&mbox->lock); 1592 1593 /* Disable RQs */ 1594 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1595 1596 /*Dequeue all CQEs */ 1597 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1598 cq = &qset->cq[qidx]; 1599 if (cq->cq_type == CQ_RX) 1600 otx2_cleanup_rx_cqes(pf, cq, qidx); 1601 else 1602 otx2_cleanup_tx_cqes(pf, cq); 1603 } 1604 otx2_free_pending_sqe(pf); 1605 1606 otx2_free_sq_res(pf); 1607 1608 /* Free RQ buffer pointers*/ 1609 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1610 1611 for (qidx = 0; qidx < pf->hw.rx_queues; qidx++) { 1612 pool_id = otx2_get_pool_idx(pf, AURA_NIX_RQ, qidx); 1613 pool = &pf->qset.pool[pool_id]; 1614 page_pool_destroy(pool->page_pool); 1615 pool->page_pool = NULL; 1616 } 1617 1618 otx2_free_cq_res(pf); 1619 1620 /* Free all ingress bandwidth profiles allocated */ 1621 cn10k_free_all_ipolicers(pf); 1622 1623 mutex_lock(&mbox->lock); 1624 /* Reset NIX LF */ 1625 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1626 if (free_req) { 1627 free_req->flags = NIX_LF_DISABLE_FLOWS; 1628 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1629 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1630 if (otx2_sync_mbox_msg(mbox)) 1631 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1632 } 1633 mutex_unlock(&mbox->lock); 1634 1635 /* Disable NPA Pool and Aura hw context */ 1636 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1637 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1638 otx2_aura_pool_free(pf); 1639 1640 mutex_lock(&mbox->lock); 1641 /* Reset NPA LF */ 1642 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1643 if (req) { 1644 if (otx2_sync_mbox_msg(mbox)) 1645 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1646 } 1647 mutex_unlock(&mbox->lock); 1648 } 1649 1650 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1651 { 1652 struct net_device *netdev = pf->netdev; 1653 struct nix_rx_mode *req; 1654 bool promisc = false; 1655 1656 if (!(netdev->flags & IFF_UP)) 1657 return; 1658 1659 if ((netdev->flags & IFF_PROMISC) || 1660 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1661 promisc = true; 1662 } 1663 1664 /* Write unicast address to mcam entries or del from mcam */ 1665 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1666 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1667 1668 mutex_lock(&pf->mbox.lock); 1669 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1670 if (!req) { 1671 mutex_unlock(&pf->mbox.lock); 1672 return; 1673 } 1674 1675 req->mode = NIX_RX_MODE_UCAST; 1676 1677 if (promisc) 1678 req->mode |= NIX_RX_MODE_PROMISC; 1679 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1680 req->mode |= NIX_RX_MODE_ALLMULTI; 1681 1682 req->mode |= NIX_RX_MODE_USE_MCE; 1683 1684 otx2_sync_mbox_msg(&pf->mbox); 1685 mutex_unlock(&pf->mbox.lock); 1686 } 1687 1688 static void otx2_dim_work(struct work_struct *w) 1689 { 1690 struct dim_cq_moder cur_moder; 1691 struct otx2_cq_poll *cq_poll; 1692 struct otx2_nic *pfvf; 1693 struct dim *dim; 1694 1695 dim = container_of(w, struct dim, work); 1696 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1697 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1698 pfvf = (struct otx2_nic *)cq_poll->dev; 1699 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1700 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1701 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1702 NAPI_POLL_WEIGHT : cur_moder.pkts; 1703 dim->state = DIM_START_MEASURE; 1704 } 1705 1706 int otx2_open(struct net_device *netdev) 1707 { 1708 struct otx2_nic *pf = netdev_priv(netdev); 1709 struct otx2_cq_poll *cq_poll = NULL; 1710 struct otx2_qset *qset = &pf->qset; 1711 int err = 0, qidx, vec; 1712 char *irq_name; 1713 1714 netif_carrier_off(netdev); 1715 1716 /* RQ and SQs are mapped to different CQs, 1717 * so find out max CQ IRQs (i.e CINTs) needed. 1718 */ 1719 pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues, 1720 pf->hw.tc_tx_queues); 1721 1722 pf->qset.cq_cnt = pf->hw.rx_queues + otx2_get_total_tx_queues(pf); 1723 1724 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1725 if (!qset->napi) 1726 return -ENOMEM; 1727 1728 /* CQ size of RQ */ 1729 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1730 /* CQ size of SQ */ 1731 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1732 1733 err = -ENOMEM; 1734 qset->cq = kcalloc(pf->qset.cq_cnt, 1735 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1736 if (!qset->cq) 1737 goto err_free_mem; 1738 1739 qset->sq = kcalloc(otx2_get_total_tx_queues(pf), 1740 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1741 if (!qset->sq) 1742 goto err_free_mem; 1743 1744 qset->rq = kcalloc(pf->hw.rx_queues, 1745 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1746 if (!qset->rq) 1747 goto err_free_mem; 1748 1749 err = otx2_init_hw_resources(pf); 1750 if (err) 1751 goto err_free_mem; 1752 1753 /* Register NAPI handler */ 1754 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1755 cq_poll = &qset->napi[qidx]; 1756 cq_poll->cint_idx = qidx; 1757 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1758 * 'cq_ids[0]' points to RQ's CQ and 1759 * 'cq_ids[1]' points to SQ's CQ and 1760 * 'cq_ids[2]' points to XDP's CQ and 1761 */ 1762 cq_poll->cq_ids[CQ_RX] = 1763 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1764 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1765 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1766 if (pf->xdp_prog) 1767 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1768 (qidx + pf->hw.rx_queues + 1769 pf->hw.tx_queues) : 1770 CINT_INVALID_CQ; 1771 else 1772 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1773 1774 cq_poll->cq_ids[CQ_QOS] = (qidx < pf->hw.tc_tx_queues) ? 1775 (qidx + pf->hw.rx_queues + 1776 pf->hw.non_qos_queues) : 1777 CINT_INVALID_CQ; 1778 1779 cq_poll->dev = (void *)pf; 1780 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1781 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1782 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1783 napi_enable(&cq_poll->napi); 1784 } 1785 1786 /* Set maximum frame size allowed in HW */ 1787 err = otx2_hw_set_mtu(pf, netdev->mtu); 1788 if (err) 1789 goto err_disable_napi; 1790 1791 /* Setup segmentation algorithms, if failed, clear offload capability */ 1792 otx2_setup_segmentation(pf); 1793 1794 /* Initialize RSS */ 1795 err = otx2_rss_init(pf); 1796 if (err) 1797 goto err_disable_napi; 1798 1799 /* Register Queue IRQ handlers */ 1800 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1801 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1802 1803 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1804 1805 err = request_irq(pci_irq_vector(pf->pdev, vec), 1806 otx2_q_intr_handler, 0, irq_name, pf); 1807 if (err) { 1808 dev_err(pf->dev, 1809 "RVUPF%d: IRQ registration failed for QERR\n", 1810 rvu_get_pf(pf->pcifunc)); 1811 goto err_disable_napi; 1812 } 1813 1814 /* Enable QINT IRQ */ 1815 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1816 1817 /* Register CQ IRQ handlers */ 1818 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1819 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1820 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1821 1822 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1823 qidx); 1824 1825 err = request_irq(pci_irq_vector(pf->pdev, vec), 1826 otx2_cq_intr_handler, 0, irq_name, 1827 &qset->napi[qidx]); 1828 if (err) { 1829 dev_err(pf->dev, 1830 "RVUPF%d: IRQ registration failed for CQ%d\n", 1831 rvu_get_pf(pf->pcifunc), qidx); 1832 goto err_free_cints; 1833 } 1834 vec++; 1835 1836 otx2_config_irq_coalescing(pf, qidx); 1837 1838 /* Enable CQ IRQ */ 1839 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1840 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1841 } 1842 1843 otx2_set_cints_affinity(pf); 1844 1845 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1846 otx2_enable_rxvlan(pf, true); 1847 1848 /* When reinitializing enable time stamping if it is enabled before */ 1849 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1850 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1851 otx2_config_hw_tx_tstamp(pf, true); 1852 } 1853 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1854 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1855 otx2_config_hw_rx_tstamp(pf, true); 1856 } 1857 1858 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1859 /* 'intf_down' may be checked on any cpu */ 1860 smp_wmb(); 1861 1862 /* Enable QoS configuration before starting tx queues */ 1863 otx2_qos_config_txschq(pf); 1864 1865 /* we have already received link status notification */ 1866 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1867 otx2_handle_link_event(pf); 1868 1869 /* Install DMAC Filters */ 1870 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1871 otx2_dmacflt_reinstall_flows(pf); 1872 1873 err = otx2_rxtx_enable(pf, true); 1874 /* If a mbox communication error happens at this point then interface 1875 * will end up in a state such that it is in down state but hardware 1876 * mcam entries are enabled to receive the packets. Hence disable the 1877 * packet I/O. 1878 */ 1879 if (err == EIO) 1880 goto err_disable_rxtx; 1881 else if (err) 1882 goto err_tx_stop_queues; 1883 1884 otx2_do_set_rx_mode(pf); 1885 1886 return 0; 1887 1888 err_disable_rxtx: 1889 otx2_rxtx_enable(pf, false); 1890 err_tx_stop_queues: 1891 netif_tx_stop_all_queues(netdev); 1892 netif_carrier_off(netdev); 1893 pf->flags |= OTX2_FLAG_INTF_DOWN; 1894 err_free_cints: 1895 otx2_free_cints(pf, qidx); 1896 vec = pci_irq_vector(pf->pdev, 1897 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1898 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1899 free_irq(vec, pf); 1900 err_disable_napi: 1901 otx2_disable_napi(pf); 1902 otx2_free_hw_resources(pf); 1903 err_free_mem: 1904 kfree(qset->sq); 1905 kfree(qset->cq); 1906 kfree(qset->rq); 1907 kfree(qset->napi); 1908 return err; 1909 } 1910 EXPORT_SYMBOL(otx2_open); 1911 1912 int otx2_stop(struct net_device *netdev) 1913 { 1914 struct otx2_nic *pf = netdev_priv(netdev); 1915 struct otx2_cq_poll *cq_poll = NULL; 1916 struct otx2_qset *qset = &pf->qset; 1917 struct otx2_rss_info *rss; 1918 int qidx, vec, wrk; 1919 1920 /* If the DOWN flag is set resources are already freed */ 1921 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1922 return 0; 1923 1924 netif_carrier_off(netdev); 1925 netif_tx_stop_all_queues(netdev); 1926 1927 pf->flags |= OTX2_FLAG_INTF_DOWN; 1928 /* 'intf_down' may be checked on any cpu */ 1929 smp_wmb(); 1930 1931 /* First stop packet Rx/Tx */ 1932 otx2_rxtx_enable(pf, false); 1933 1934 /* Clear RSS enable flag */ 1935 rss = &pf->hw.rss_info; 1936 rss->enable = false; 1937 1938 /* Cleanup Queue IRQ */ 1939 vec = pci_irq_vector(pf->pdev, 1940 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1941 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1942 free_irq(vec, pf); 1943 1944 /* Cleanup CQ NAPI and IRQ */ 1945 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1946 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1947 /* Disable interrupt */ 1948 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1949 1950 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1951 1952 cq_poll = &qset->napi[qidx]; 1953 napi_synchronize(&cq_poll->napi); 1954 vec++; 1955 } 1956 1957 netif_tx_disable(netdev); 1958 1959 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1960 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1961 devm_kfree(pf->dev, pf->refill_wrk); 1962 1963 otx2_free_hw_resources(pf); 1964 otx2_free_cints(pf, pf->hw.cint_cnt); 1965 otx2_disable_napi(pf); 1966 1967 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1968 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1969 1970 1971 kfree(qset->sq); 1972 kfree(qset->cq); 1973 kfree(qset->rq); 1974 kfree(qset->napi); 1975 /* Do not clear RQ/SQ ringsize settings */ 1976 memset_startat(qset, 0, sqe_cnt); 1977 return 0; 1978 } 1979 EXPORT_SYMBOL(otx2_stop); 1980 1981 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1982 { 1983 struct otx2_nic *pf = netdev_priv(netdev); 1984 int qidx = skb_get_queue_mapping(skb); 1985 struct otx2_snd_queue *sq; 1986 struct netdev_queue *txq; 1987 int sq_idx; 1988 1989 /* XDP SQs are not mapped with TXQs 1990 * advance qid to derive correct sq mapped with QOS 1991 */ 1992 sq_idx = (qidx >= pf->hw.tx_queues) ? (qidx + pf->hw.xdp_queues) : qidx; 1993 1994 /* Check for minimum and maximum packet length */ 1995 if (skb->len <= ETH_HLEN || 1996 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 1997 dev_kfree_skb(skb); 1998 return NETDEV_TX_OK; 1999 } 2000 2001 sq = &pf->qset.sq[sq_idx]; 2002 txq = netdev_get_tx_queue(netdev, qidx); 2003 2004 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 2005 netif_tx_stop_queue(txq); 2006 2007 /* Check again, incase SQBs got freed up */ 2008 smp_mb(); 2009 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 2010 > sq->sqe_thresh) 2011 netif_tx_wake_queue(txq); 2012 2013 return NETDEV_TX_BUSY; 2014 } 2015 2016 return NETDEV_TX_OK; 2017 } 2018 2019 static int otx2_qos_select_htb_queue(struct otx2_nic *pf, struct sk_buff *skb, 2020 u16 htb_maj_id) 2021 { 2022 u16 classid; 2023 2024 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id) 2025 classid = TC_H_MIN(skb->priority); 2026 else 2027 classid = READ_ONCE(pf->qos.defcls); 2028 2029 if (!classid) 2030 return 0; 2031 2032 return otx2_get_txq_by_classid(pf, classid); 2033 } 2034 2035 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 2036 struct net_device *sb_dev) 2037 { 2038 struct otx2_nic *pf = netdev_priv(netdev); 2039 bool qos_enabled; 2040 #ifdef CONFIG_DCB 2041 u8 vlan_prio; 2042 #endif 2043 int txq; 2044 2045 qos_enabled = netdev->real_num_tx_queues > pf->hw.tx_queues; 2046 if (unlikely(qos_enabled)) { 2047 /* This smp_load_acquire() pairs with smp_store_release() in 2048 * otx2_qos_root_add() called from htb offload root creation 2049 */ 2050 u16 htb_maj_id = smp_load_acquire(&pf->qos.maj_id); 2051 2052 if (unlikely(htb_maj_id)) { 2053 txq = otx2_qos_select_htb_queue(pf, skb, htb_maj_id); 2054 if (txq > 0) 2055 return txq; 2056 goto process_pfc; 2057 } 2058 } 2059 2060 process_pfc: 2061 #ifdef CONFIG_DCB 2062 if (!skb_vlan_tag_present(skb)) 2063 goto pick_tx; 2064 2065 vlan_prio = skb->vlan_tci >> 13; 2066 if ((vlan_prio > pf->hw.tx_queues - 1) || 2067 !pf->pfc_alloc_status[vlan_prio]) 2068 goto pick_tx; 2069 2070 return vlan_prio; 2071 2072 pick_tx: 2073 #endif 2074 txq = netdev_pick_tx(netdev, skb, NULL); 2075 if (unlikely(qos_enabled)) 2076 return txq % pf->hw.tx_queues; 2077 2078 return txq; 2079 } 2080 EXPORT_SYMBOL(otx2_select_queue); 2081 2082 static netdev_features_t otx2_fix_features(struct net_device *dev, 2083 netdev_features_t features) 2084 { 2085 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2086 features |= NETIF_F_HW_VLAN_STAG_RX; 2087 else 2088 features &= ~NETIF_F_HW_VLAN_STAG_RX; 2089 2090 return features; 2091 } 2092 2093 static void otx2_set_rx_mode(struct net_device *netdev) 2094 { 2095 struct otx2_nic *pf = netdev_priv(netdev); 2096 2097 queue_work(pf->otx2_wq, &pf->rx_mode_work); 2098 } 2099 2100 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 2101 { 2102 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 2103 2104 otx2_do_set_rx_mode(pf); 2105 } 2106 2107 static int otx2_set_features(struct net_device *netdev, 2108 netdev_features_t features) 2109 { 2110 netdev_features_t changed = features ^ netdev->features; 2111 struct otx2_nic *pf = netdev_priv(netdev); 2112 2113 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 2114 return otx2_cgx_config_loopback(pf, 2115 features & NETIF_F_LOOPBACK); 2116 2117 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 2118 return otx2_enable_rxvlan(pf, 2119 features & NETIF_F_HW_VLAN_CTAG_RX); 2120 2121 return otx2_handle_ntuple_tc_features(netdev, features); 2122 } 2123 2124 static void otx2_reset_task(struct work_struct *work) 2125 { 2126 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 2127 2128 if (!netif_running(pf->netdev)) 2129 return; 2130 2131 rtnl_lock(); 2132 otx2_stop(pf->netdev); 2133 pf->reset_count++; 2134 otx2_open(pf->netdev); 2135 netif_trans_update(pf->netdev); 2136 rtnl_unlock(); 2137 } 2138 2139 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 2140 { 2141 struct msg_req *req; 2142 int err; 2143 2144 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 2145 return 0; 2146 2147 mutex_lock(&pfvf->mbox.lock); 2148 if (enable) 2149 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 2150 else 2151 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 2152 if (!req) { 2153 mutex_unlock(&pfvf->mbox.lock); 2154 return -ENOMEM; 2155 } 2156 2157 err = otx2_sync_mbox_msg(&pfvf->mbox); 2158 if (err) { 2159 mutex_unlock(&pfvf->mbox.lock); 2160 return err; 2161 } 2162 2163 mutex_unlock(&pfvf->mbox.lock); 2164 if (enable) 2165 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2166 else 2167 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2168 return 0; 2169 } 2170 2171 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2172 { 2173 struct msg_req *req; 2174 int err; 2175 2176 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2177 return 0; 2178 2179 mutex_lock(&pfvf->mbox.lock); 2180 if (enable) 2181 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2182 else 2183 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2184 if (!req) { 2185 mutex_unlock(&pfvf->mbox.lock); 2186 return -ENOMEM; 2187 } 2188 2189 err = otx2_sync_mbox_msg(&pfvf->mbox); 2190 if (err) { 2191 mutex_unlock(&pfvf->mbox.lock); 2192 return err; 2193 } 2194 2195 mutex_unlock(&pfvf->mbox.lock); 2196 if (enable) 2197 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2198 else 2199 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2200 return 0; 2201 } 2202 2203 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2204 { 2205 struct otx2_nic *pfvf = netdev_priv(netdev); 2206 struct hwtstamp_config config; 2207 2208 if (!pfvf->ptp) 2209 return -ENODEV; 2210 2211 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2212 return -EFAULT; 2213 2214 switch (config.tx_type) { 2215 case HWTSTAMP_TX_OFF: 2216 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2217 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2218 2219 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2220 otx2_config_hw_tx_tstamp(pfvf, false); 2221 break; 2222 case HWTSTAMP_TX_ONESTEP_SYNC: 2223 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2224 return -ERANGE; 2225 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2226 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2227 msecs_to_jiffies(500)); 2228 fallthrough; 2229 case HWTSTAMP_TX_ON: 2230 otx2_config_hw_tx_tstamp(pfvf, true); 2231 break; 2232 default: 2233 return -ERANGE; 2234 } 2235 2236 switch (config.rx_filter) { 2237 case HWTSTAMP_FILTER_NONE: 2238 otx2_config_hw_rx_tstamp(pfvf, false); 2239 break; 2240 case HWTSTAMP_FILTER_ALL: 2241 case HWTSTAMP_FILTER_SOME: 2242 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2243 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2244 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2245 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2246 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2247 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2248 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2249 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2250 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2251 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2252 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2253 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2254 otx2_config_hw_rx_tstamp(pfvf, true); 2255 config.rx_filter = HWTSTAMP_FILTER_ALL; 2256 break; 2257 default: 2258 return -ERANGE; 2259 } 2260 2261 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2262 2263 return copy_to_user(ifr->ifr_data, &config, 2264 sizeof(config)) ? -EFAULT : 0; 2265 } 2266 EXPORT_SYMBOL(otx2_config_hwtstamp); 2267 2268 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2269 { 2270 struct otx2_nic *pfvf = netdev_priv(netdev); 2271 struct hwtstamp_config *cfg = &pfvf->tstamp; 2272 2273 switch (cmd) { 2274 case SIOCSHWTSTAMP: 2275 return otx2_config_hwtstamp(netdev, req); 2276 case SIOCGHWTSTAMP: 2277 return copy_to_user(req->ifr_data, cfg, 2278 sizeof(*cfg)) ? -EFAULT : 0; 2279 default: 2280 return -EOPNOTSUPP; 2281 } 2282 } 2283 EXPORT_SYMBOL(otx2_ioctl); 2284 2285 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2286 { 2287 struct npc_install_flow_req *req; 2288 int err; 2289 2290 mutex_lock(&pf->mbox.lock); 2291 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2292 if (!req) { 2293 err = -ENOMEM; 2294 goto out; 2295 } 2296 2297 ether_addr_copy(req->packet.dmac, mac); 2298 eth_broadcast_addr((u8 *)&req->mask.dmac); 2299 req->features = BIT_ULL(NPC_DMAC); 2300 req->channel = pf->hw.rx_chan_base; 2301 req->intf = NIX_INTF_RX; 2302 req->default_rule = 1; 2303 req->append = 1; 2304 req->vf = vf + 1; 2305 req->op = NIX_RX_ACTION_DEFAULT; 2306 2307 err = otx2_sync_mbox_msg(&pf->mbox); 2308 out: 2309 mutex_unlock(&pf->mbox.lock); 2310 return err; 2311 } 2312 2313 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2314 { 2315 struct otx2_nic *pf = netdev_priv(netdev); 2316 struct pci_dev *pdev = pf->pdev; 2317 struct otx2_vf_config *config; 2318 int ret; 2319 2320 if (!netif_running(netdev)) 2321 return -EAGAIN; 2322 2323 if (vf >= pf->total_vfs) 2324 return -EINVAL; 2325 2326 if (!is_valid_ether_addr(mac)) 2327 return -EINVAL; 2328 2329 config = &pf->vf_configs[vf]; 2330 ether_addr_copy(config->mac, mac); 2331 2332 ret = otx2_do_set_vf_mac(pf, vf, mac); 2333 if (ret == 0) 2334 dev_info(&pdev->dev, 2335 "Load/Reload VF driver\n"); 2336 2337 return ret; 2338 } 2339 2340 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2341 __be16 proto) 2342 { 2343 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2344 struct nix_vtag_config_rsp *vtag_rsp; 2345 struct npc_delete_flow_req *del_req; 2346 struct nix_vtag_config *vtag_req; 2347 struct npc_install_flow_req *req; 2348 struct otx2_vf_config *config; 2349 int err = 0; 2350 u32 idx; 2351 2352 config = &pf->vf_configs[vf]; 2353 2354 if (!vlan && !config->vlan) 2355 goto out; 2356 2357 mutex_lock(&pf->mbox.lock); 2358 2359 /* free old tx vtag entry */ 2360 if (config->vlan) { 2361 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2362 if (!vtag_req) { 2363 err = -ENOMEM; 2364 goto out; 2365 } 2366 vtag_req->cfg_type = 0; 2367 vtag_req->tx.free_vtag0 = 1; 2368 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2369 2370 err = otx2_sync_mbox_msg(&pf->mbox); 2371 if (err) 2372 goto out; 2373 } 2374 2375 if (!vlan && config->vlan) { 2376 /* rx */ 2377 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2378 if (!del_req) { 2379 err = -ENOMEM; 2380 goto out; 2381 } 2382 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2383 del_req->entry = 2384 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2385 err = otx2_sync_mbox_msg(&pf->mbox); 2386 if (err) 2387 goto out; 2388 2389 /* tx */ 2390 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2391 if (!del_req) { 2392 err = -ENOMEM; 2393 goto out; 2394 } 2395 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2396 del_req->entry = 2397 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2398 err = otx2_sync_mbox_msg(&pf->mbox); 2399 2400 goto out; 2401 } 2402 2403 /* rx */ 2404 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2405 if (!req) { 2406 err = -ENOMEM; 2407 goto out; 2408 } 2409 2410 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2411 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2412 req->packet.vlan_tci = htons(vlan); 2413 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2414 /* af fills the destination mac addr */ 2415 eth_broadcast_addr((u8 *)&req->mask.dmac); 2416 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2417 req->channel = pf->hw.rx_chan_base; 2418 req->intf = NIX_INTF_RX; 2419 req->vf = vf + 1; 2420 req->op = NIX_RX_ACTION_DEFAULT; 2421 req->vtag0_valid = true; 2422 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2423 req->set_cntr = 1; 2424 2425 err = otx2_sync_mbox_msg(&pf->mbox); 2426 if (err) 2427 goto out; 2428 2429 /* tx */ 2430 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2431 if (!vtag_req) { 2432 err = -ENOMEM; 2433 goto out; 2434 } 2435 2436 /* configure tx vtag params */ 2437 vtag_req->vtag_size = VTAGSIZE_T4; 2438 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2439 vtag_req->tx.cfg_vtag0 = 1; 2440 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2441 2442 err = otx2_sync_mbox_msg(&pf->mbox); 2443 if (err) 2444 goto out; 2445 2446 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2447 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2448 if (IS_ERR(vtag_rsp)) { 2449 err = PTR_ERR(vtag_rsp); 2450 goto out; 2451 } 2452 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2453 2454 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2455 if (!req) { 2456 err = -ENOMEM; 2457 goto out; 2458 } 2459 2460 eth_zero_addr((u8 *)&req->mask.dmac); 2461 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2462 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2463 req->features = BIT_ULL(NPC_DMAC); 2464 req->channel = pf->hw.tx_chan_base; 2465 req->intf = NIX_INTF_TX; 2466 req->vf = vf + 1; 2467 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2468 req->vtag0_def = vtag_rsp->vtag0_idx; 2469 req->vtag0_op = VTAG_INSERT; 2470 req->set_cntr = 1; 2471 2472 err = otx2_sync_mbox_msg(&pf->mbox); 2473 out: 2474 config->vlan = vlan; 2475 mutex_unlock(&pf->mbox.lock); 2476 return err; 2477 } 2478 2479 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2480 __be16 proto) 2481 { 2482 struct otx2_nic *pf = netdev_priv(netdev); 2483 struct pci_dev *pdev = pf->pdev; 2484 2485 if (!netif_running(netdev)) 2486 return -EAGAIN; 2487 2488 if (vf >= pci_num_vf(pdev)) 2489 return -EINVAL; 2490 2491 /* qos is currently unsupported */ 2492 if (vlan >= VLAN_N_VID || qos) 2493 return -EINVAL; 2494 2495 if (proto != htons(ETH_P_8021Q)) 2496 return -EPROTONOSUPPORT; 2497 2498 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2499 return -EOPNOTSUPP; 2500 2501 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2502 } 2503 2504 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2505 struct ifla_vf_info *ivi) 2506 { 2507 struct otx2_nic *pf = netdev_priv(netdev); 2508 struct pci_dev *pdev = pf->pdev; 2509 struct otx2_vf_config *config; 2510 2511 if (!netif_running(netdev)) 2512 return -EAGAIN; 2513 2514 if (vf >= pci_num_vf(pdev)) 2515 return -EINVAL; 2516 2517 config = &pf->vf_configs[vf]; 2518 ivi->vf = vf; 2519 ether_addr_copy(ivi->mac, config->mac); 2520 ivi->vlan = config->vlan; 2521 ivi->trusted = config->trusted; 2522 2523 return 0; 2524 } 2525 2526 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2527 int qidx) 2528 { 2529 struct page *page; 2530 u64 dma_addr; 2531 int err = 0; 2532 2533 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2534 offset_in_page(xdpf->data), xdpf->len, 2535 DMA_TO_DEVICE); 2536 if (dma_mapping_error(pf->dev, dma_addr)) 2537 return -ENOMEM; 2538 2539 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2540 if (!err) { 2541 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2542 page = virt_to_page(xdpf->data); 2543 put_page(page); 2544 return -ENOMEM; 2545 } 2546 return 0; 2547 } 2548 2549 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2550 struct xdp_frame **frames, u32 flags) 2551 { 2552 struct otx2_nic *pf = netdev_priv(netdev); 2553 int qidx = smp_processor_id(); 2554 struct otx2_snd_queue *sq; 2555 int drops = 0, i; 2556 2557 if (!netif_running(netdev)) 2558 return -ENETDOWN; 2559 2560 qidx += pf->hw.tx_queues; 2561 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2562 2563 /* Abort xmit if xdp queue is not */ 2564 if (unlikely(!sq)) 2565 return -ENXIO; 2566 2567 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2568 return -EINVAL; 2569 2570 for (i = 0; i < n; i++) { 2571 struct xdp_frame *xdpf = frames[i]; 2572 int err; 2573 2574 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2575 if (err) 2576 drops++; 2577 } 2578 return n - drops; 2579 } 2580 2581 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2582 { 2583 struct net_device *dev = pf->netdev; 2584 bool if_up = netif_running(pf->netdev); 2585 struct bpf_prog *old_prog; 2586 2587 if (prog && dev->mtu > MAX_XDP_MTU) { 2588 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2589 return -EOPNOTSUPP; 2590 } 2591 2592 if (if_up) 2593 otx2_stop(pf->netdev); 2594 2595 old_prog = xchg(&pf->xdp_prog, prog); 2596 2597 if (old_prog) 2598 bpf_prog_put(old_prog); 2599 2600 if (pf->xdp_prog) 2601 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2602 2603 /* Network stack and XDP shared same rx queues. 2604 * Use separate tx queues for XDP and network stack. 2605 */ 2606 if (pf->xdp_prog) { 2607 pf->hw.xdp_queues = pf->hw.rx_queues; 2608 xdp_features_set_redirect_target(dev, false); 2609 } else { 2610 pf->hw.xdp_queues = 0; 2611 xdp_features_clear_redirect_target(dev); 2612 } 2613 2614 pf->hw.non_qos_queues += pf->hw.xdp_queues; 2615 2616 if (if_up) 2617 otx2_open(pf->netdev); 2618 2619 return 0; 2620 } 2621 2622 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2623 { 2624 struct otx2_nic *pf = netdev_priv(netdev); 2625 2626 switch (xdp->command) { 2627 case XDP_SETUP_PROG: 2628 return otx2_xdp_setup(pf, xdp->prog); 2629 default: 2630 return -EINVAL; 2631 } 2632 } 2633 2634 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2635 int req_perm) 2636 { 2637 struct set_vf_perm *req; 2638 int rc; 2639 2640 mutex_lock(&pf->mbox.lock); 2641 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2642 if (!req) { 2643 rc = -ENOMEM; 2644 goto out; 2645 } 2646 2647 /* Let AF reset VF permissions as sriov is disabled */ 2648 if (req_perm == OTX2_RESET_VF_PERM) { 2649 req->flags |= RESET_VF_PERM; 2650 } else if (req_perm == OTX2_TRUSTED_VF) { 2651 if (pf->vf_configs[vf].trusted) 2652 req->flags |= VF_TRUSTED; 2653 } 2654 2655 req->vf = vf; 2656 rc = otx2_sync_mbox_msg(&pf->mbox); 2657 out: 2658 mutex_unlock(&pf->mbox.lock); 2659 return rc; 2660 } 2661 2662 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2663 bool enable) 2664 { 2665 struct otx2_nic *pf = netdev_priv(netdev); 2666 struct pci_dev *pdev = pf->pdev; 2667 int rc; 2668 2669 if (vf >= pci_num_vf(pdev)) 2670 return -EINVAL; 2671 2672 if (pf->vf_configs[vf].trusted == enable) 2673 return 0; 2674 2675 pf->vf_configs[vf].trusted = enable; 2676 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2677 2678 if (rc) 2679 pf->vf_configs[vf].trusted = !enable; 2680 else 2681 netdev_info(pf->netdev, "VF %d is %strusted\n", 2682 vf, enable ? "" : "not "); 2683 return rc; 2684 } 2685 2686 static const struct net_device_ops otx2_netdev_ops = { 2687 .ndo_open = otx2_open, 2688 .ndo_stop = otx2_stop, 2689 .ndo_start_xmit = otx2_xmit, 2690 .ndo_select_queue = otx2_select_queue, 2691 .ndo_fix_features = otx2_fix_features, 2692 .ndo_set_mac_address = otx2_set_mac_address, 2693 .ndo_change_mtu = otx2_change_mtu, 2694 .ndo_set_rx_mode = otx2_set_rx_mode, 2695 .ndo_set_features = otx2_set_features, 2696 .ndo_tx_timeout = otx2_tx_timeout, 2697 .ndo_get_stats64 = otx2_get_stats64, 2698 .ndo_eth_ioctl = otx2_ioctl, 2699 .ndo_set_vf_mac = otx2_set_vf_mac, 2700 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2701 .ndo_get_vf_config = otx2_get_vf_config, 2702 .ndo_bpf = otx2_xdp, 2703 .ndo_xdp_xmit = otx2_xdp_xmit, 2704 .ndo_setup_tc = otx2_setup_tc, 2705 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2706 }; 2707 2708 static int otx2_wq_init(struct otx2_nic *pf) 2709 { 2710 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2711 if (!pf->otx2_wq) 2712 return -ENOMEM; 2713 2714 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2715 INIT_WORK(&pf->reset_task, otx2_reset_task); 2716 return 0; 2717 } 2718 2719 static int otx2_check_pf_usable(struct otx2_nic *nic) 2720 { 2721 u64 rev; 2722 2723 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2724 rev = (rev >> 12) & 0xFF; 2725 /* Check if AF has setup revision for RVUM block, 2726 * otherwise this driver probe should be deferred 2727 * until AF driver comes up. 2728 */ 2729 if (!rev) { 2730 dev_warn(nic->dev, 2731 "AF is not initialized, deferring probe\n"); 2732 return -EPROBE_DEFER; 2733 } 2734 return 0; 2735 } 2736 2737 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2738 { 2739 struct otx2_hw *hw = &pf->hw; 2740 int num_vec, err; 2741 2742 /* NPA interrupts are inot registered, so alloc only 2743 * upto NIX vector offset. 2744 */ 2745 num_vec = hw->nix_msixoff; 2746 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2747 2748 otx2_disable_mbox_intr(pf); 2749 pci_free_irq_vectors(hw->pdev); 2750 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2751 if (err < 0) { 2752 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2753 __func__, num_vec); 2754 return err; 2755 } 2756 2757 return otx2_register_mbox_intr(pf, false); 2758 } 2759 2760 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2761 { 2762 int i; 2763 2764 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2765 sizeof(struct otx2_vf_config), 2766 GFP_KERNEL); 2767 if (!pf->vf_configs) 2768 return -ENOMEM; 2769 2770 for (i = 0; i < pf->total_vfs; i++) { 2771 pf->vf_configs[i].pf = pf; 2772 pf->vf_configs[i].intf_down = true; 2773 pf->vf_configs[i].trusted = false; 2774 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2775 otx2_vf_link_event_task); 2776 } 2777 2778 return 0; 2779 } 2780 2781 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2782 { 2783 int i; 2784 2785 if (!pf->vf_configs) 2786 return; 2787 2788 for (i = 0; i < pf->total_vfs; i++) { 2789 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2790 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2791 } 2792 } 2793 2794 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2795 { 2796 struct device *dev = &pdev->dev; 2797 int err, qcount, qos_txqs; 2798 struct net_device *netdev; 2799 struct otx2_nic *pf; 2800 struct otx2_hw *hw; 2801 int num_vec; 2802 2803 err = pcim_enable_device(pdev); 2804 if (err) { 2805 dev_err(dev, "Failed to enable PCI device\n"); 2806 return err; 2807 } 2808 2809 err = pci_request_regions(pdev, DRV_NAME); 2810 if (err) { 2811 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2812 return err; 2813 } 2814 2815 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2816 if (err) { 2817 dev_err(dev, "DMA mask config failed, abort\n"); 2818 goto err_release_regions; 2819 } 2820 2821 pci_set_master(pdev); 2822 2823 /* Set number of queues */ 2824 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2825 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 2826 2827 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount + qos_txqs, qcount); 2828 if (!netdev) { 2829 err = -ENOMEM; 2830 goto err_release_regions; 2831 } 2832 2833 pci_set_drvdata(pdev, netdev); 2834 SET_NETDEV_DEV(netdev, &pdev->dev); 2835 pf = netdev_priv(netdev); 2836 pf->netdev = netdev; 2837 pf->pdev = pdev; 2838 pf->dev = dev; 2839 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2840 pf->flags |= OTX2_FLAG_INTF_DOWN; 2841 2842 hw = &pf->hw; 2843 hw->pdev = pdev; 2844 hw->rx_queues = qcount; 2845 hw->tx_queues = qcount; 2846 hw->non_qos_queues = qcount; 2847 hw->max_queues = qcount; 2848 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 2849 /* Use CQE of 128 byte descriptor size by default */ 2850 hw->xqe_size = 128; 2851 2852 num_vec = pci_msix_vec_count(pdev); 2853 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2854 GFP_KERNEL); 2855 if (!hw->irq_name) { 2856 err = -ENOMEM; 2857 goto err_free_netdev; 2858 } 2859 2860 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2861 sizeof(cpumask_var_t), GFP_KERNEL); 2862 if (!hw->affinity_mask) { 2863 err = -ENOMEM; 2864 goto err_free_netdev; 2865 } 2866 2867 /* Map CSRs */ 2868 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2869 if (!pf->reg_base) { 2870 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2871 err = -ENOMEM; 2872 goto err_free_netdev; 2873 } 2874 2875 err = otx2_check_pf_usable(pf); 2876 if (err) 2877 goto err_free_netdev; 2878 2879 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2880 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2881 if (err < 0) { 2882 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2883 __func__, num_vec); 2884 goto err_free_netdev; 2885 } 2886 2887 otx2_setup_dev_hw_settings(pf); 2888 2889 /* Init PF <=> AF mailbox stuff */ 2890 err = otx2_pfaf_mbox_init(pf); 2891 if (err) 2892 goto err_free_irq_vectors; 2893 2894 /* Register mailbox interrupt */ 2895 err = otx2_register_mbox_intr(pf, true); 2896 if (err) 2897 goto err_mbox_destroy; 2898 2899 /* Request AF to attach NPA and NIX LFs to this PF. 2900 * NIX and NPA LFs are needed for this PF to function as a NIC. 2901 */ 2902 err = otx2_attach_npa_nix(pf); 2903 if (err) 2904 goto err_disable_mbox_intr; 2905 2906 err = otx2_realloc_msix_vectors(pf); 2907 if (err) 2908 goto err_detach_rsrc; 2909 2910 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2911 if (err) 2912 goto err_detach_rsrc; 2913 2914 err = cn10k_lmtst_init(pf); 2915 if (err) 2916 goto err_detach_rsrc; 2917 2918 /* Assign default mac address */ 2919 otx2_get_mac_from_af(netdev); 2920 2921 /* Don't check for error. Proceed without ptp */ 2922 otx2_ptp_init(pf); 2923 2924 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2925 * HW allocates buffer pointer from stack and uses it for DMA'ing 2926 * ingress packet. In some scenarios HW can free back allocated buffer 2927 * pointers to pool. This makes it impossible for SW to maintain a 2928 * parallel list where physical addresses of buffer pointers (IOVAs) 2929 * given to HW can be saved for later reference. 2930 * 2931 * So the only way to convert Rx packet's buffer address is to use 2932 * IOMMU's iova_to_phys() handler which translates the address by 2933 * walking through the translation tables. 2934 */ 2935 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2936 2937 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2938 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2939 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2940 NETIF_F_GSO_UDP_L4); 2941 netdev->features |= netdev->hw_features; 2942 2943 err = otx2_mcam_flow_init(pf); 2944 if (err) 2945 goto err_ptp_destroy; 2946 2947 err = cn10k_mcs_init(pf); 2948 if (err) 2949 goto err_del_mcam_entries; 2950 2951 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2952 netdev->hw_features |= NETIF_F_NTUPLE; 2953 2954 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2955 netdev->priv_flags |= IFF_UNICAST_FLT; 2956 2957 /* Support TSO on tag interface */ 2958 netdev->vlan_features |= netdev->features; 2959 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2960 NETIF_F_HW_VLAN_STAG_TX; 2961 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2962 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2963 NETIF_F_HW_VLAN_STAG_RX; 2964 netdev->features |= netdev->hw_features; 2965 2966 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2967 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2968 netdev->hw_features |= NETIF_F_HW_TC; 2969 2970 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2971 2972 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 2973 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2974 2975 netdev->netdev_ops = &otx2_netdev_ops; 2976 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 2977 2978 netdev->min_mtu = OTX2_MIN_MTU; 2979 netdev->max_mtu = otx2_get_max_mtu(pf); 2980 2981 err = register_netdev(netdev); 2982 if (err) { 2983 dev_err(dev, "Failed to register netdevice\n"); 2984 goto err_mcs_free; 2985 } 2986 2987 err = otx2_wq_init(pf); 2988 if (err) 2989 goto err_unreg_netdev; 2990 2991 otx2_set_ethtool_ops(netdev); 2992 2993 err = otx2_init_tc(pf); 2994 if (err) 2995 goto err_mcam_flow_del; 2996 2997 err = otx2_register_dl(pf); 2998 if (err) 2999 goto err_mcam_flow_del; 3000 3001 /* Initialize SR-IOV resources */ 3002 err = otx2_sriov_vfcfg_init(pf); 3003 if (err) 3004 goto err_pf_sriov_init; 3005 3006 /* Enable link notifications */ 3007 otx2_cgx_config_linkevents(pf, true); 3008 3009 #ifdef CONFIG_DCB 3010 err = otx2_dcbnl_set_ops(netdev); 3011 if (err) 3012 goto err_pf_sriov_init; 3013 #endif 3014 3015 otx2_qos_init(pf, qos_txqs); 3016 3017 return 0; 3018 3019 err_pf_sriov_init: 3020 otx2_shutdown_tc(pf); 3021 err_mcam_flow_del: 3022 otx2_mcam_flow_del(pf); 3023 err_unreg_netdev: 3024 unregister_netdev(netdev); 3025 err_mcs_free: 3026 cn10k_mcs_free(pf); 3027 err_del_mcam_entries: 3028 otx2_mcam_flow_del(pf); 3029 err_ptp_destroy: 3030 otx2_ptp_destroy(pf); 3031 err_detach_rsrc: 3032 if (pf->hw.lmt_info) 3033 free_percpu(pf->hw.lmt_info); 3034 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3035 qmem_free(pf->dev, pf->dync_lmt); 3036 otx2_detach_resources(&pf->mbox); 3037 err_disable_mbox_intr: 3038 otx2_disable_mbox_intr(pf); 3039 err_mbox_destroy: 3040 otx2_pfaf_mbox_destroy(pf); 3041 err_free_irq_vectors: 3042 pci_free_irq_vectors(hw->pdev); 3043 err_free_netdev: 3044 pci_set_drvdata(pdev, NULL); 3045 free_netdev(netdev); 3046 err_release_regions: 3047 pci_release_regions(pdev); 3048 return err; 3049 } 3050 3051 static void otx2_vf_link_event_task(struct work_struct *work) 3052 { 3053 struct otx2_vf_config *config; 3054 struct cgx_link_info_msg *req; 3055 struct mbox_msghdr *msghdr; 3056 struct otx2_nic *pf; 3057 int vf_idx; 3058 3059 config = container_of(work, struct otx2_vf_config, 3060 link_event_work.work); 3061 vf_idx = config - config->pf->vf_configs; 3062 pf = config->pf; 3063 3064 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 3065 sizeof(*req), sizeof(struct msg_rsp)); 3066 if (!msghdr) { 3067 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 3068 return; 3069 } 3070 3071 req = (struct cgx_link_info_msg *)msghdr; 3072 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 3073 req->hdr.sig = OTX2_MBOX_REQ_SIG; 3074 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 3075 3076 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 3077 } 3078 3079 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 3080 { 3081 struct net_device *netdev = pci_get_drvdata(pdev); 3082 struct otx2_nic *pf = netdev_priv(netdev); 3083 int ret; 3084 3085 /* Init PF <=> VF mailbox stuff */ 3086 ret = otx2_pfvf_mbox_init(pf, numvfs); 3087 if (ret) 3088 return ret; 3089 3090 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 3091 if (ret) 3092 goto free_mbox; 3093 3094 ret = otx2_pf_flr_init(pf, numvfs); 3095 if (ret) 3096 goto free_intr; 3097 3098 ret = otx2_register_flr_me_intr(pf, numvfs); 3099 if (ret) 3100 goto free_flr; 3101 3102 ret = pci_enable_sriov(pdev, numvfs); 3103 if (ret) 3104 goto free_flr_intr; 3105 3106 return numvfs; 3107 free_flr_intr: 3108 otx2_disable_flr_me_intr(pf); 3109 free_flr: 3110 otx2_flr_wq_destroy(pf); 3111 free_intr: 3112 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3113 free_mbox: 3114 otx2_pfvf_mbox_destroy(pf); 3115 return ret; 3116 } 3117 3118 static int otx2_sriov_disable(struct pci_dev *pdev) 3119 { 3120 struct net_device *netdev = pci_get_drvdata(pdev); 3121 struct otx2_nic *pf = netdev_priv(netdev); 3122 int numvfs = pci_num_vf(pdev); 3123 3124 if (!numvfs) 3125 return 0; 3126 3127 pci_disable_sriov(pdev); 3128 3129 otx2_disable_flr_me_intr(pf); 3130 otx2_flr_wq_destroy(pf); 3131 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3132 otx2_pfvf_mbox_destroy(pf); 3133 3134 return 0; 3135 } 3136 3137 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 3138 { 3139 if (numvfs == 0) 3140 return otx2_sriov_disable(pdev); 3141 else 3142 return otx2_sriov_enable(pdev, numvfs); 3143 } 3144 3145 static void otx2_remove(struct pci_dev *pdev) 3146 { 3147 struct net_device *netdev = pci_get_drvdata(pdev); 3148 struct otx2_nic *pf; 3149 3150 if (!netdev) 3151 return; 3152 3153 pf = netdev_priv(netdev); 3154 3155 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 3156 3157 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 3158 otx2_config_hw_tx_tstamp(pf, false); 3159 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 3160 otx2_config_hw_rx_tstamp(pf, false); 3161 3162 /* Disable 802.3x pause frames */ 3163 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 3164 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 3165 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 3166 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 3167 otx2_config_pause_frm(pf); 3168 } 3169 3170 #ifdef CONFIG_DCB 3171 /* Disable PFC config */ 3172 if (pf->pfc_en) { 3173 pf->pfc_en = 0; 3174 otx2_config_priority_flow_ctrl(pf); 3175 } 3176 #endif 3177 cancel_work_sync(&pf->reset_task); 3178 /* Disable link notifications */ 3179 otx2_cgx_config_linkevents(pf, false); 3180 3181 otx2_unregister_dl(pf); 3182 unregister_netdev(netdev); 3183 cn10k_mcs_free(pf); 3184 otx2_sriov_disable(pf->pdev); 3185 otx2_sriov_vfcfg_cleanup(pf); 3186 if (pf->otx2_wq) 3187 destroy_workqueue(pf->otx2_wq); 3188 3189 otx2_ptp_destroy(pf); 3190 otx2_mcam_flow_del(pf); 3191 otx2_shutdown_tc(pf); 3192 otx2_shutdown_qos(pf); 3193 otx2_detach_resources(&pf->mbox); 3194 if (pf->hw.lmt_info) 3195 free_percpu(pf->hw.lmt_info); 3196 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3197 qmem_free(pf->dev, pf->dync_lmt); 3198 otx2_disable_mbox_intr(pf); 3199 otx2_pfaf_mbox_destroy(pf); 3200 pci_free_irq_vectors(pf->pdev); 3201 pci_set_drvdata(pdev, NULL); 3202 free_netdev(netdev); 3203 3204 pci_release_regions(pdev); 3205 } 3206 3207 static struct pci_driver otx2_pf_driver = { 3208 .name = DRV_NAME, 3209 .id_table = otx2_pf_id_table, 3210 .probe = otx2_probe, 3211 .shutdown = otx2_remove, 3212 .remove = otx2_remove, 3213 .sriov_configure = otx2_sriov_configure 3214 }; 3215 3216 static int __init otx2_rvupf_init_module(void) 3217 { 3218 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3219 3220 return pci_register_driver(&otx2_pf_driver); 3221 } 3222 3223 static void __exit otx2_rvupf_cleanup_module(void) 3224 { 3225 pci_unregister_driver(&otx2_pf_driver); 3226 } 3227 3228 module_init(otx2_rvupf_init_module); 3229 module_exit(otx2_rvupf_cleanup_module); 3230