1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 #include <linux/bitfield.h> 19 #include <net/page_pool/types.h> 20 21 #include "otx2_reg.h" 22 #include "otx2_common.h" 23 #include "otx2_txrx.h" 24 #include "otx2_struct.h" 25 #include "otx2_ptp.h" 26 #include "cn10k.h" 27 #include "qos.h" 28 #include <rvu_trace.h> 29 #include "cn10k_ipsec.h" 30 #include "otx2_xsk.h" 31 32 #define DRV_NAME "rvu_nicpf" 33 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 34 35 /* Supported devices */ 36 static const struct pci_device_id otx2_pf_id_table[] = { 37 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 38 { 0, } /* end of table */ 39 }; 40 41 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 42 MODULE_DESCRIPTION(DRV_STRING); 43 MODULE_LICENSE("GPL v2"); 44 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 45 46 static void otx2_vf_link_event_task(struct work_struct *work); 47 48 enum { 49 TYPE_PFAF, 50 TYPE_PFVF, 51 }; 52 53 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 54 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 55 56 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 57 { 58 struct otx2_nic *pf = netdev_priv(netdev); 59 bool if_up = netif_running(netdev); 60 int err = 0; 61 62 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 63 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 64 netdev->mtu); 65 return -EINVAL; 66 } 67 if (if_up) 68 otx2_stop(netdev); 69 70 netdev_info(netdev, "Changing MTU from %d to %d\n", 71 netdev->mtu, new_mtu); 72 WRITE_ONCE(netdev->mtu, new_mtu); 73 74 if (if_up) 75 err = otx2_open(netdev); 76 77 return err; 78 } 79 80 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 81 { 82 int irq, vfs = pf->total_vfs; 83 84 /* Disable VFs ME interrupts */ 85 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 86 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 87 free_irq(irq, pf); 88 89 /* Disable VFs FLR interrupts */ 90 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 91 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 92 free_irq(irq, pf); 93 94 if (vfs <= 64) 95 return; 96 97 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 98 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 99 free_irq(irq, pf); 100 101 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 102 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 103 free_irq(irq, pf); 104 } 105 106 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 107 { 108 if (!pf->flr_wq) 109 return; 110 destroy_workqueue(pf->flr_wq); 111 pf->flr_wq = NULL; 112 devm_kfree(pf->dev, pf->flr_wrk); 113 } 114 115 static void otx2_flr_handler(struct work_struct *work) 116 { 117 struct flr_work *flrwork = container_of(work, struct flr_work, work); 118 struct otx2_nic *pf = flrwork->pf; 119 struct mbox *mbox = &pf->mbox; 120 struct msg_req *req; 121 int vf, reg = 0; 122 123 vf = flrwork - pf->flr_wrk; 124 125 mutex_lock(&mbox->lock); 126 req = otx2_mbox_alloc_msg_vf_flr(mbox); 127 if (!req) { 128 mutex_unlock(&mbox->lock); 129 return; 130 } 131 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 132 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 133 134 if (!otx2_sync_mbox_msg(&pf->mbox)) { 135 if (vf >= 64) { 136 reg = 1; 137 vf = vf - 64; 138 } 139 /* clear transcation pending bit */ 140 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 141 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 142 } 143 144 mutex_unlock(&mbox->lock); 145 } 146 147 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 148 { 149 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 150 int reg, dev, vf, start_vf, num_reg = 1; 151 u64 intr; 152 153 if (pf->total_vfs > 64) 154 num_reg = 2; 155 156 for (reg = 0; reg < num_reg; reg++) { 157 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 158 if (!intr) 159 continue; 160 start_vf = 64 * reg; 161 for (vf = 0; vf < 64; vf++) { 162 if (!(intr & BIT_ULL(vf))) 163 continue; 164 dev = vf + start_vf; 165 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 166 /* Clear interrupt */ 167 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 168 /* Disable the interrupt */ 169 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 170 BIT_ULL(vf)); 171 } 172 } 173 return IRQ_HANDLED; 174 } 175 176 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 177 { 178 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 179 int vf, reg, num_reg = 1; 180 u64 intr; 181 182 if (pf->total_vfs > 64) 183 num_reg = 2; 184 185 for (reg = 0; reg < num_reg; reg++) { 186 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 187 if (!intr) 188 continue; 189 for (vf = 0; vf < 64; vf++) { 190 if (!(intr & BIT_ULL(vf))) 191 continue; 192 /* clear trpend bit */ 193 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 194 /* clear interrupt */ 195 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 196 } 197 } 198 return IRQ_HANDLED; 199 } 200 201 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 202 { 203 struct otx2_hw *hw = &pf->hw; 204 char *irq_name; 205 int ret; 206 207 /* Register ME interrupt handler*/ 208 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 209 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 210 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 211 otx2_pf_me_intr_handler, 0, irq_name, pf); 212 if (ret) { 213 dev_err(pf->dev, 214 "RVUPF: IRQ registration failed for ME0\n"); 215 } 216 217 /* Register FLR interrupt handler */ 218 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 219 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 220 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 221 otx2_pf_flr_intr_handler, 0, irq_name, pf); 222 if (ret) { 223 dev_err(pf->dev, 224 "RVUPF: IRQ registration failed for FLR0\n"); 225 return ret; 226 } 227 228 if (numvfs > 64) { 229 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 230 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 231 rvu_get_pf(pf->pcifunc)); 232 ret = request_irq(pci_irq_vector 233 (pf->pdev, RVU_PF_INT_VEC_VFME1), 234 otx2_pf_me_intr_handler, 0, irq_name, pf); 235 if (ret) { 236 dev_err(pf->dev, 237 "RVUPF: IRQ registration failed for ME1\n"); 238 } 239 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 240 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 241 rvu_get_pf(pf->pcifunc)); 242 ret = request_irq(pci_irq_vector 243 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 244 otx2_pf_flr_intr_handler, 0, irq_name, pf); 245 if (ret) { 246 dev_err(pf->dev, 247 "RVUPF: IRQ registration failed for FLR1\n"); 248 return ret; 249 } 250 } 251 252 /* Enable ME interrupt for all VFs*/ 253 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 254 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 255 256 /* Enable FLR interrupt for all VFs*/ 257 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 258 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 259 260 if (numvfs > 64) { 261 numvfs -= 64; 262 263 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 264 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 265 INTR_MASK(numvfs)); 266 267 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 268 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 269 INTR_MASK(numvfs)); 270 } 271 return 0; 272 } 273 274 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 275 { 276 int vf; 277 278 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI); 279 if (!pf->flr_wq) 280 return -ENOMEM; 281 282 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 283 sizeof(struct flr_work), GFP_KERNEL); 284 if (!pf->flr_wrk) { 285 destroy_workqueue(pf->flr_wq); 286 return -ENOMEM; 287 } 288 289 for (vf = 0; vf < num_vfs; vf++) { 290 pf->flr_wrk[vf].pf = pf; 291 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 292 } 293 294 return 0; 295 } 296 297 static void otx2_queue_vf_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 298 int first, int mdevs, u64 intr) 299 { 300 struct otx2_mbox_dev *mdev; 301 struct otx2_mbox *mbox; 302 struct mbox_hdr *hdr; 303 int i; 304 305 for (i = first; i < mdevs; i++) { 306 /* start from 0 */ 307 if (!(intr & BIT_ULL(i - first))) 308 continue; 309 310 mbox = &mw->mbox; 311 mdev = &mbox->dev[i]; 312 hdr = mdev->mbase + mbox->rx_start; 313 /* The hdr->num_msgs is set to zero immediately in the interrupt 314 * handler to ensure that it holds a correct value next time 315 * when the interrupt handler is called. pf->mw[i].num_msgs 316 * holds the data for use in otx2_pfvf_mbox_handler and 317 * pf->mw[i].up_num_msgs holds the data for use in 318 * otx2_pfvf_mbox_up_handler. 319 */ 320 if (hdr->num_msgs) { 321 mw[i].num_msgs = hdr->num_msgs; 322 hdr->num_msgs = 0; 323 queue_work(mbox_wq, &mw[i].mbox_wrk); 324 } 325 326 mbox = &mw->mbox_up; 327 mdev = &mbox->dev[i]; 328 hdr = mdev->mbase + mbox->rx_start; 329 if (hdr->num_msgs) { 330 mw[i].up_num_msgs = hdr->num_msgs; 331 hdr->num_msgs = 0; 332 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 333 } 334 } 335 } 336 337 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 338 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 339 int devid) 340 { 341 struct otx2_mbox_dev *src_mdev = mdev; 342 int offset; 343 344 /* Msgs are already copied, trigger VF's mbox irq */ 345 smp_wmb(); 346 347 otx2_mbox_wait_for_zero(pfvf_mbox, devid); 348 349 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 350 writeq(MBOX_DOWN_MSG, (void __iomem *)pfvf_mbox->reg_base + offset); 351 352 /* Restore VF's mbox bounce buffer region address */ 353 src_mdev->mbase = bbuf_base; 354 } 355 356 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 357 struct otx2_mbox *src_mbox, 358 int dir, int vf, int num_msgs) 359 { 360 struct otx2_mbox_dev *src_mdev, *dst_mdev; 361 struct mbox_hdr *mbox_hdr; 362 struct mbox_hdr *req_hdr; 363 struct mbox *dst_mbox; 364 int dst_size, err; 365 366 if (dir == MBOX_DIR_PFAF) { 367 /* Set VF's mailbox memory as PF's bounce buffer memory, so 368 * that explicit copying of VF's msgs to PF=>AF mbox region 369 * and AF=>PF responses to VF's mbox region can be avoided. 370 */ 371 src_mdev = &src_mbox->dev[vf]; 372 mbox_hdr = src_mbox->hwbase + 373 src_mbox->rx_start + (vf * MBOX_SIZE); 374 375 dst_mbox = &pf->mbox; 376 dst_size = dst_mbox->mbox.tx_size - 377 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 378 /* Check if msgs fit into destination area and has valid size */ 379 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 380 return -EINVAL; 381 382 dst_mdev = &dst_mbox->mbox.dev[0]; 383 384 mutex_lock(&pf->mbox.lock); 385 dst_mdev->mbase = src_mdev->mbase; 386 dst_mdev->msg_size = mbox_hdr->msg_size; 387 dst_mdev->num_msgs = num_msgs; 388 err = otx2_sync_mbox_msg(dst_mbox); 389 /* Error code -EIO indicate there is a communication failure 390 * to the AF. Rest of the error codes indicate that AF processed 391 * VF messages and set the error codes in response messages 392 * (if any) so simply forward responses to VF. 393 */ 394 if (err == -EIO) { 395 dev_warn(pf->dev, 396 "AF not responding to VF%d messages\n", vf); 397 /* restore PF mbase and exit */ 398 dst_mdev->mbase = pf->mbox.bbuf_base; 399 mutex_unlock(&pf->mbox.lock); 400 return err; 401 } 402 /* At this point, all the VF messages sent to AF are acked 403 * with proper responses and responses are copied to VF 404 * mailbox hence raise interrupt to VF. 405 */ 406 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 407 dst_mbox->mbox.rx_start); 408 req_hdr->num_msgs = num_msgs; 409 410 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 411 pf->mbox.bbuf_base, vf); 412 mutex_unlock(&pf->mbox.lock); 413 } else if (dir == MBOX_DIR_PFVF_UP) { 414 src_mdev = &src_mbox->dev[0]; 415 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 416 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 417 src_mbox->rx_start); 418 req_hdr->num_msgs = num_msgs; 419 420 dst_mbox = &pf->mbox_pfvf[0]; 421 dst_size = dst_mbox->mbox_up.tx_size - 422 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 423 /* Check if msgs fit into destination area */ 424 if (mbox_hdr->msg_size > dst_size) 425 return -EINVAL; 426 427 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 428 dst_mdev->mbase = src_mdev->mbase; 429 dst_mdev->msg_size = mbox_hdr->msg_size; 430 dst_mdev->num_msgs = mbox_hdr->num_msgs; 431 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 432 if (err) { 433 dev_warn(pf->dev, 434 "VF%d is not responding to mailbox\n", vf); 435 return err; 436 } 437 } else if (dir == MBOX_DIR_VFPF_UP) { 438 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 439 src_mbox->rx_start); 440 req_hdr->num_msgs = num_msgs; 441 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 442 &pf->mbox.mbox_up, 443 pf->mbox_pfvf[vf].bbuf_base, 444 0); 445 } 446 447 return 0; 448 } 449 450 static void otx2_pfvf_mbox_handler(struct work_struct *work) 451 { 452 struct mbox_msghdr *msg = NULL; 453 int offset, vf_idx, id, err; 454 struct otx2_mbox_dev *mdev; 455 struct otx2_mbox *mbox; 456 struct mbox *vf_mbox; 457 struct otx2_nic *pf; 458 459 vf_mbox = container_of(work, struct mbox, mbox_wrk); 460 pf = vf_mbox->pfvf; 461 vf_idx = vf_mbox - pf->mbox_pfvf; 462 463 mbox = &pf->mbox_pfvf[0].mbox; 464 mdev = &mbox->dev[vf_idx]; 465 466 offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 467 468 for (id = 0; id < vf_mbox->num_msgs; id++) { 469 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 470 offset); 471 472 if (msg->sig != OTX2_MBOX_REQ_SIG) 473 goto inval_msg; 474 475 /* Set VF's number in each of the msg */ 476 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 477 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 478 offset = msg->next_msgoff; 479 } 480 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 481 vf_mbox->num_msgs); 482 if (err) 483 goto inval_msg; 484 return; 485 486 inval_msg: 487 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 488 otx2_mbox_msg_send(mbox, vf_idx); 489 } 490 491 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 492 { 493 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 494 struct otx2_nic *pf = vf_mbox->pfvf; 495 struct otx2_mbox_dev *mdev; 496 int offset, id, vf_idx = 0; 497 struct mbox_msghdr *msg; 498 struct otx2_mbox *mbox; 499 500 vf_idx = vf_mbox - pf->mbox_pfvf; 501 mbox = &pf->mbox_pfvf[0].mbox_up; 502 mdev = &mbox->dev[vf_idx]; 503 504 offset = mbox->rx_start + ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 505 506 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 507 msg = mdev->mbase + offset; 508 509 if (msg->id >= MBOX_MSG_MAX) { 510 dev_err(pf->dev, 511 "Mbox msg with unknown ID 0x%x\n", msg->id); 512 goto end; 513 } 514 515 if (msg->sig != OTX2_MBOX_RSP_SIG) { 516 dev_err(pf->dev, 517 "Mbox msg with wrong signature %x, ID 0x%x\n", 518 msg->sig, msg->id); 519 goto end; 520 } 521 522 switch (msg->id) { 523 case MBOX_MSG_CGX_LINK_EVENT: 524 case MBOX_MSG_REP_EVENT_UP_NOTIFY: 525 break; 526 default: 527 if (msg->rc) 528 dev_err(pf->dev, 529 "Mbox msg response has err %d, ID 0x%x\n", 530 msg->rc, msg->id); 531 break; 532 } 533 534 end: 535 offset = mbox->rx_start + msg->next_msgoff; 536 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 537 __otx2_mbox_reset(mbox, vf_idx); 538 mdev->msgs_acked++; 539 } 540 } 541 542 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 543 { 544 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 545 int vfs = pf->total_vfs; 546 struct mbox *mbox; 547 u64 intr; 548 549 mbox = pf->mbox_pfvf; 550 /* Handle VF interrupts */ 551 if (vfs > 64) { 552 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 553 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 554 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr); 555 if (intr) 556 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 557 vfs = 64; 558 } 559 560 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 561 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 562 563 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr); 564 565 if (intr) 566 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 567 568 return IRQ_HANDLED; 569 } 570 571 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 572 { 573 void __iomem *hwbase; 574 struct mbox *mbox; 575 int err, vf; 576 u64 base; 577 578 if (!numvfs) 579 return -EINVAL; 580 581 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 582 sizeof(struct mbox), GFP_KERNEL); 583 if (!pf->mbox_pfvf) 584 return -ENOMEM; 585 586 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 587 WQ_UNBOUND | WQ_HIGHPRI | 588 WQ_MEM_RECLAIM, 0); 589 if (!pf->mbox_pfvf_wq) 590 return -ENOMEM; 591 592 /* On CN10K platform, PF <-> VF mailbox region follows after 593 * PF <-> AF mailbox region. 594 */ 595 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 596 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 597 MBOX_SIZE; 598 else 599 base = readq((void __iomem *)((u64)pf->reg_base + 600 RVU_PF_VF_BAR4_ADDR)); 601 602 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 603 if (!hwbase) { 604 err = -ENOMEM; 605 goto free_wq; 606 } 607 608 mbox = &pf->mbox_pfvf[0]; 609 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 610 MBOX_DIR_PFVF, numvfs); 611 if (err) 612 goto free_iomem; 613 614 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 615 MBOX_DIR_PFVF_UP, numvfs); 616 if (err) 617 goto free_iomem; 618 619 for (vf = 0; vf < numvfs; vf++) { 620 mbox->pfvf = pf; 621 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 622 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 623 mbox++; 624 } 625 626 return 0; 627 628 free_iomem: 629 if (hwbase) 630 iounmap(hwbase); 631 free_wq: 632 destroy_workqueue(pf->mbox_pfvf_wq); 633 return err; 634 } 635 636 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 637 { 638 struct mbox *mbox = &pf->mbox_pfvf[0]; 639 640 if (!mbox) 641 return; 642 643 if (pf->mbox_pfvf_wq) { 644 destroy_workqueue(pf->mbox_pfvf_wq); 645 pf->mbox_pfvf_wq = NULL; 646 } 647 648 if (mbox->mbox.hwbase) 649 iounmap(mbox->mbox.hwbase); 650 651 otx2_mbox_destroy(&mbox->mbox); 652 } 653 654 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 655 { 656 /* Clear PF <=> VF mailbox IRQ */ 657 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 658 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 659 660 /* Enable PF <=> VF mailbox IRQ */ 661 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 662 if (numvfs > 64) { 663 numvfs -= 64; 664 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 665 INTR_MASK(numvfs)); 666 } 667 } 668 669 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 670 { 671 int vector; 672 673 /* Disable PF <=> VF mailbox IRQ */ 674 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 675 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 676 677 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 678 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 679 free_irq(vector, pf); 680 681 if (numvfs > 64) { 682 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 683 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 684 free_irq(vector, pf); 685 } 686 } 687 688 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 689 { 690 struct otx2_hw *hw = &pf->hw; 691 char *irq_name; 692 int err; 693 694 /* Register MBOX0 interrupt handler */ 695 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 696 if (pf->pcifunc) 697 snprintf(irq_name, NAME_SIZE, 698 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 699 else 700 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 701 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 702 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 703 if (err) { 704 dev_err(pf->dev, 705 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 706 return err; 707 } 708 709 if (numvfs > 64) { 710 /* Register MBOX1 interrupt handler */ 711 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 712 if (pf->pcifunc) 713 snprintf(irq_name, NAME_SIZE, 714 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 715 else 716 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 717 err = request_irq(pci_irq_vector(pf->pdev, 718 RVU_PF_INT_VEC_VFPF_MBOX1), 719 otx2_pfvf_mbox_intr_handler, 720 0, irq_name, pf); 721 if (err) { 722 dev_err(pf->dev, 723 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 724 return err; 725 } 726 } 727 728 otx2_enable_pfvf_mbox_intr(pf, numvfs); 729 730 return 0; 731 } 732 733 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 734 struct mbox_msghdr *msg) 735 { 736 int devid; 737 738 if (msg->id >= MBOX_MSG_MAX) { 739 dev_err(pf->dev, 740 "Mbox msg with unknown ID 0x%x\n", msg->id); 741 return; 742 } 743 744 if (msg->sig != OTX2_MBOX_RSP_SIG) { 745 dev_err(pf->dev, 746 "Mbox msg with wrong signature %x, ID 0x%x\n", 747 msg->sig, msg->id); 748 return; 749 } 750 751 /* message response heading VF */ 752 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 753 if (devid) { 754 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 755 struct delayed_work *dwork; 756 757 switch (msg->id) { 758 case MBOX_MSG_NIX_LF_START_RX: 759 config->intf_down = false; 760 dwork = &config->link_event_work; 761 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 762 break; 763 case MBOX_MSG_NIX_LF_STOP_RX: 764 config->intf_down = true; 765 break; 766 } 767 768 return; 769 } 770 771 switch (msg->id) { 772 case MBOX_MSG_READY: 773 pf->pcifunc = msg->pcifunc; 774 break; 775 case MBOX_MSG_MSIX_OFFSET: 776 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 777 break; 778 case MBOX_MSG_NPA_LF_ALLOC: 779 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 780 break; 781 case MBOX_MSG_NIX_LF_ALLOC: 782 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 783 break; 784 case MBOX_MSG_NIX_BP_ENABLE: 785 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 786 break; 787 case MBOX_MSG_CGX_STATS: 788 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 789 break; 790 case MBOX_MSG_CGX_FEC_STATS: 791 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 792 break; 793 default: 794 if (msg->rc) 795 dev_err(pf->dev, 796 "Mbox msg response has err %d, ID 0x%x\n", 797 msg->rc, msg->id); 798 break; 799 } 800 } 801 802 static void otx2_pfaf_mbox_handler(struct work_struct *work) 803 { 804 struct otx2_mbox_dev *mdev; 805 struct mbox_hdr *rsp_hdr; 806 struct mbox_msghdr *msg; 807 struct otx2_mbox *mbox; 808 struct mbox *af_mbox; 809 struct otx2_nic *pf; 810 int offset, id; 811 u16 num_msgs; 812 813 af_mbox = container_of(work, struct mbox, mbox_wrk); 814 mbox = &af_mbox->mbox; 815 mdev = &mbox->dev[0]; 816 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 817 num_msgs = rsp_hdr->num_msgs; 818 819 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 820 pf = af_mbox->pfvf; 821 822 for (id = 0; id < num_msgs; id++) { 823 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 824 otx2_process_pfaf_mbox_msg(pf, msg); 825 offset = mbox->rx_start + msg->next_msgoff; 826 if (mdev->msgs_acked == (num_msgs - 1)) 827 __otx2_mbox_reset(mbox, 0); 828 mdev->msgs_acked++; 829 } 830 831 } 832 833 static void otx2_handle_link_event(struct otx2_nic *pf) 834 { 835 struct cgx_link_user_info *linfo = &pf->linfo; 836 struct net_device *netdev = pf->netdev; 837 838 if (pf->flags & OTX2_FLAG_PORT_UP) 839 return; 840 841 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 842 linfo->link_up ? "UP" : "DOWN", linfo->speed, 843 linfo->full_duplex ? "Full" : "Half"); 844 if (linfo->link_up) { 845 netif_carrier_on(netdev); 846 netif_tx_start_all_queues(netdev); 847 } else { 848 netif_tx_stop_all_queues(netdev); 849 netif_carrier_off(netdev); 850 } 851 } 852 853 static int otx2_mbox_up_handler_rep_event_up_notify(struct otx2_nic *pf, 854 struct rep_event *info, 855 struct msg_rsp *rsp) 856 { 857 struct net_device *netdev = pf->netdev; 858 859 if (info->event == RVU_EVENT_MTU_CHANGE) { 860 netdev->mtu = info->evt_data.mtu; 861 return 0; 862 } 863 864 if (info->event == RVU_EVENT_PORT_STATE) { 865 if (info->evt_data.port_state) { 866 pf->flags |= OTX2_FLAG_PORT_UP; 867 netif_carrier_on(netdev); 868 netif_tx_start_all_queues(netdev); 869 } else { 870 pf->flags &= ~OTX2_FLAG_PORT_UP; 871 netif_tx_stop_all_queues(netdev); 872 netif_carrier_off(netdev); 873 } 874 return 0; 875 } 876 #ifdef CONFIG_RVU_ESWITCH 877 rvu_event_up_notify(pf, info); 878 #endif 879 return 0; 880 } 881 882 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 883 struct mcs_intr_info *event, 884 struct msg_rsp *rsp) 885 { 886 cn10k_handle_mcs_event(pf, event); 887 888 return 0; 889 } 890 891 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 892 struct cgx_link_info_msg *msg, 893 struct msg_rsp *rsp) 894 { 895 int i; 896 897 /* Copy the link info sent by AF */ 898 pf->linfo = msg->link_info; 899 900 /* notify VFs about link event */ 901 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 902 struct otx2_vf_config *config = &pf->vf_configs[i]; 903 struct delayed_work *dwork = &config->link_event_work; 904 905 if (config->intf_down) 906 continue; 907 908 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 909 } 910 911 /* interface has not been fully configured yet */ 912 if (pf->flags & OTX2_FLAG_INTF_DOWN) 913 return 0; 914 915 otx2_handle_link_event(pf); 916 return 0; 917 } 918 919 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 920 struct mbox_msghdr *req) 921 { 922 /* Check if valid, if not reply with a invalid msg */ 923 if (req->sig != OTX2_MBOX_REQ_SIG) { 924 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 925 return -ENODEV; 926 } 927 928 switch (req->id) { 929 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 930 case _id: { \ 931 struct _rsp_type *rsp; \ 932 int err; \ 933 \ 934 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 935 &pf->mbox.mbox_up, 0, \ 936 sizeof(struct _rsp_type)); \ 937 if (!rsp) \ 938 return -ENOMEM; \ 939 \ 940 rsp->hdr.id = _id; \ 941 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 942 rsp->hdr.pcifunc = 0; \ 943 rsp->hdr.rc = 0; \ 944 \ 945 err = otx2_mbox_up_handler_ ## _fn_name( \ 946 pf, (struct _req_type *)req, rsp); \ 947 return err; \ 948 } 949 MBOX_UP_CGX_MESSAGES 950 MBOX_UP_MCS_MESSAGES 951 MBOX_UP_REP_MESSAGES 952 #undef M 953 break; 954 default: 955 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 956 return -ENODEV; 957 } 958 return 0; 959 } 960 961 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 962 { 963 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 964 struct otx2_mbox *mbox = &af_mbox->mbox_up; 965 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 966 struct otx2_nic *pf = af_mbox->pfvf; 967 int offset, id, devid = 0; 968 struct mbox_hdr *rsp_hdr; 969 struct mbox_msghdr *msg; 970 u16 num_msgs; 971 972 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 973 num_msgs = rsp_hdr->num_msgs; 974 975 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 976 977 for (id = 0; id < num_msgs; id++) { 978 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 979 980 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 981 /* Skip processing VF's messages */ 982 if (!devid) 983 otx2_process_mbox_msg_up(pf, msg); 984 offset = mbox->rx_start + msg->next_msgoff; 985 } 986 /* Forward to VF iff VFs are really present */ 987 if (devid && pci_num_vf(pf->pdev)) { 988 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 989 MBOX_DIR_PFVF_UP, devid - 1, 990 num_msgs); 991 return; 992 } 993 994 otx2_mbox_msg_send(mbox, 0); 995 } 996 997 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 998 { 999 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 1000 struct mbox *mw = &pf->mbox; 1001 struct otx2_mbox_dev *mdev; 1002 struct otx2_mbox *mbox; 1003 struct mbox_hdr *hdr; 1004 u64 mbox_data; 1005 1006 /* Clear the IRQ */ 1007 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1008 1009 1010 mbox_data = otx2_read64(pf, RVU_PF_PFAF_MBOX0); 1011 1012 if (mbox_data & MBOX_UP_MSG) { 1013 mbox_data &= ~MBOX_UP_MSG; 1014 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); 1015 1016 mbox = &mw->mbox_up; 1017 mdev = &mbox->dev[0]; 1018 otx2_sync_mbox_bbuf(mbox, 0); 1019 1020 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 1021 if (hdr->num_msgs) 1022 queue_work(pf->mbox_wq, &mw->mbox_up_wrk); 1023 1024 trace_otx2_msg_interrupt(pf->pdev, "UP message from AF to PF", 1025 BIT_ULL(0)); 1026 } 1027 1028 if (mbox_data & MBOX_DOWN_MSG) { 1029 mbox_data &= ~MBOX_DOWN_MSG; 1030 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); 1031 1032 mbox = &mw->mbox; 1033 mdev = &mbox->dev[0]; 1034 otx2_sync_mbox_bbuf(mbox, 0); 1035 1036 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 1037 if (hdr->num_msgs) 1038 queue_work(pf->mbox_wq, &mw->mbox_wrk); 1039 1040 trace_otx2_msg_interrupt(pf->pdev, "DOWN reply from AF to PF", 1041 BIT_ULL(0)); 1042 } 1043 1044 return IRQ_HANDLED; 1045 } 1046 1047 void otx2_disable_mbox_intr(struct otx2_nic *pf) 1048 { 1049 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 1050 1051 /* Disable AF => PF mailbox IRQ */ 1052 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 1053 free_irq(vector, pf); 1054 } 1055 EXPORT_SYMBOL(otx2_disable_mbox_intr); 1056 1057 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 1058 { 1059 struct otx2_hw *hw = &pf->hw; 1060 struct msg_req *req; 1061 char *irq_name; 1062 int err; 1063 1064 /* Register mailbox interrupt handler */ 1065 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1066 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 1067 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1068 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1069 if (err) { 1070 dev_err(pf->dev, 1071 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1072 return err; 1073 } 1074 1075 /* Enable mailbox interrupt for msgs coming from AF. 1076 * First clear to avoid spurious interrupts, if any. 1077 */ 1078 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1079 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1080 1081 if (!probe_af) 1082 return 0; 1083 1084 /* Check mailbox communication with AF */ 1085 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1086 if (!req) { 1087 otx2_disable_mbox_intr(pf); 1088 return -ENOMEM; 1089 } 1090 err = otx2_sync_mbox_msg(&pf->mbox); 1091 if (err) { 1092 dev_warn(pf->dev, 1093 "AF not responding to mailbox, deferring probe\n"); 1094 otx2_disable_mbox_intr(pf); 1095 return -EPROBE_DEFER; 1096 } 1097 1098 return 0; 1099 } 1100 1101 void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1102 { 1103 struct mbox *mbox = &pf->mbox; 1104 1105 if (pf->mbox_wq) { 1106 destroy_workqueue(pf->mbox_wq); 1107 pf->mbox_wq = NULL; 1108 } 1109 1110 if (mbox->mbox.hwbase) 1111 iounmap((void __iomem *)mbox->mbox.hwbase); 1112 1113 otx2_mbox_destroy(&mbox->mbox); 1114 otx2_mbox_destroy(&mbox->mbox_up); 1115 } 1116 EXPORT_SYMBOL(otx2_pfaf_mbox_destroy); 1117 1118 int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1119 { 1120 struct mbox *mbox = &pf->mbox; 1121 void __iomem *hwbase; 1122 int err; 1123 1124 mbox->pfvf = pf; 1125 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox", 1126 WQ_HIGHPRI | WQ_MEM_RECLAIM); 1127 if (!pf->mbox_wq) 1128 return -ENOMEM; 1129 1130 /* Mailbox is a reserved memory (in RAM) region shared between 1131 * admin function (i.e AF) and this PF, shouldn't be mapped as 1132 * device memory to allow unaligned accesses. 1133 */ 1134 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1135 MBOX_SIZE); 1136 if (!hwbase) { 1137 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1138 err = -ENOMEM; 1139 goto exit; 1140 } 1141 1142 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1143 MBOX_DIR_PFAF, 1); 1144 if (err) 1145 goto exit; 1146 1147 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1148 MBOX_DIR_PFAF_UP, 1); 1149 if (err) 1150 goto exit; 1151 1152 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1153 if (err) 1154 goto exit; 1155 1156 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1157 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1158 mutex_init(&mbox->lock); 1159 1160 return 0; 1161 exit: 1162 otx2_pfaf_mbox_destroy(pf); 1163 return err; 1164 } 1165 1166 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1167 { 1168 struct msg_req *msg; 1169 int err; 1170 1171 mutex_lock(&pf->mbox.lock); 1172 if (enable) 1173 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1174 else 1175 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1176 1177 if (!msg) { 1178 mutex_unlock(&pf->mbox.lock); 1179 return -ENOMEM; 1180 } 1181 1182 err = otx2_sync_mbox_msg(&pf->mbox); 1183 mutex_unlock(&pf->mbox.lock); 1184 return err; 1185 } 1186 1187 int otx2_reset_mac_stats(struct otx2_nic *pfvf) 1188 { 1189 struct msg_req *req; 1190 int err; 1191 1192 mutex_lock(&pfvf->mbox.lock); 1193 req = otx2_mbox_alloc_msg_cgx_stats_rst(&pfvf->mbox); 1194 if (!req) { 1195 mutex_unlock(&pfvf->mbox.lock); 1196 return -ENOMEM; 1197 } 1198 1199 err = otx2_sync_mbox_msg(&pfvf->mbox); 1200 mutex_unlock(&pfvf->mbox.lock); 1201 return err; 1202 } 1203 1204 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1205 { 1206 struct msg_req *msg; 1207 int err; 1208 1209 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1210 pf->flow_cfg->dmacflt_max_flows)) 1211 netdev_warn(pf->netdev, 1212 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1213 1214 mutex_lock(&pf->mbox.lock); 1215 if (enable) 1216 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1217 else 1218 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1219 1220 if (!msg) { 1221 mutex_unlock(&pf->mbox.lock); 1222 return -ENOMEM; 1223 } 1224 1225 err = otx2_sync_mbox_msg(&pf->mbox); 1226 mutex_unlock(&pf->mbox.lock); 1227 return err; 1228 } 1229 1230 int otx2_set_real_num_queues(struct net_device *netdev, 1231 int tx_queues, int rx_queues) 1232 { 1233 int err; 1234 1235 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1236 if (err) { 1237 netdev_err(netdev, 1238 "Failed to set no of Tx queues: %d\n", tx_queues); 1239 return err; 1240 } 1241 1242 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1243 if (err) 1244 netdev_err(netdev, 1245 "Failed to set no of Rx queues: %d\n", rx_queues); 1246 return err; 1247 } 1248 EXPORT_SYMBOL(otx2_set_real_num_queues); 1249 1250 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = { 1251 "NIX_SQOPERR_OOR", 1252 "NIX_SQOPERR_CTX_FAULT", 1253 "NIX_SQOPERR_CTX_POISON", 1254 "NIX_SQOPERR_DISABLED", 1255 "NIX_SQOPERR_SIZE_ERR", 1256 "NIX_SQOPERR_OFLOW", 1257 "NIX_SQOPERR_SQB_NULL", 1258 "NIX_SQOPERR_SQB_FAULT", 1259 "NIX_SQOPERR_SQE_SZ_ZERO", 1260 }; 1261 1262 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = { 1263 "NIX_MNQERR_SQ_CTX_FAULT", 1264 "NIX_MNQERR_SQ_CTX_POISON", 1265 "NIX_MNQERR_SQB_FAULT", 1266 "NIX_MNQERR_SQB_POISON", 1267 "NIX_MNQERR_TOTAL_ERR", 1268 "NIX_MNQERR_LSO_ERR", 1269 "NIX_MNQERR_CQ_QUERY_ERR", 1270 "NIX_MNQERR_MAX_SQE_SIZE_ERR", 1271 "NIX_MNQERR_MAXLEN_ERR", 1272 "NIX_MNQERR_SQE_SIZEM1_ZERO", 1273 }; 1274 1275 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = { 1276 [NIX_SND_STATUS_GOOD] = "NIX_SND_STATUS_GOOD", 1277 [NIX_SND_STATUS_SQ_CTX_FAULT] = "NIX_SND_STATUS_SQ_CTX_FAULT", 1278 [NIX_SND_STATUS_SQ_CTX_POISON] = "NIX_SND_STATUS_SQ_CTX_POISON", 1279 [NIX_SND_STATUS_SQB_FAULT] = "NIX_SND_STATUS_SQB_FAULT", 1280 [NIX_SND_STATUS_SQB_POISON] = "NIX_SND_STATUS_SQB_POISON", 1281 [NIX_SND_STATUS_HDR_ERR] = "NIX_SND_STATUS_HDR_ERR", 1282 [NIX_SND_STATUS_EXT_ERR] = "NIX_SND_STATUS_EXT_ERR", 1283 [NIX_SND_STATUS_JUMP_FAULT] = "NIX_SND_STATUS_JUMP_FAULT", 1284 [NIX_SND_STATUS_JUMP_POISON] = "NIX_SND_STATUS_JUMP_POISON", 1285 [NIX_SND_STATUS_CRC_ERR] = "NIX_SND_STATUS_CRC_ERR", 1286 [NIX_SND_STATUS_IMM_ERR] = "NIX_SND_STATUS_IMM_ERR", 1287 [NIX_SND_STATUS_SG_ERR] = "NIX_SND_STATUS_SG_ERR", 1288 [NIX_SND_STATUS_MEM_ERR] = "NIX_SND_STATUS_MEM_ERR", 1289 [NIX_SND_STATUS_INVALID_SUBDC] = "NIX_SND_STATUS_INVALID_SUBDC", 1290 [NIX_SND_STATUS_SUBDC_ORDER_ERR] = "NIX_SND_STATUS_SUBDC_ORDER_ERR", 1291 [NIX_SND_STATUS_DATA_FAULT] = "NIX_SND_STATUS_DATA_FAULT", 1292 [NIX_SND_STATUS_DATA_POISON] = "NIX_SND_STATUS_DATA_POISON", 1293 [NIX_SND_STATUS_NPC_DROP_ACTION] = "NIX_SND_STATUS_NPC_DROP_ACTION", 1294 [NIX_SND_STATUS_LOCK_VIOL] = "NIX_SND_STATUS_LOCK_VIOL", 1295 [NIX_SND_STATUS_NPC_UCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_UCAST_CHAN_ERR", 1296 [NIX_SND_STATUS_NPC_MCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_MCAST_CHAN_ERR", 1297 [NIX_SND_STATUS_NPC_MCAST_ABORT] = "NIX_SND_STATUS_NPC_MCAST_ABORT", 1298 [NIX_SND_STATUS_NPC_VTAG_PTR_ERR] = "NIX_SND_STATUS_NPC_VTAG_PTR_ERR", 1299 [NIX_SND_STATUS_NPC_VTAG_SIZE_ERR] = "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR", 1300 [NIX_SND_STATUS_SEND_MEM_FAULT] = "NIX_SND_STATUS_SEND_MEM_FAULT", 1301 [NIX_SND_STATUS_SEND_STATS_ERR] = "NIX_SND_STATUS_SEND_STATS_ERR", 1302 }; 1303 1304 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1305 { 1306 struct otx2_nic *pf = data; 1307 struct otx2_snd_queue *sq; 1308 u64 val, *ptr; 1309 u64 qidx = 0; 1310 1311 /* CQ */ 1312 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1313 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1314 val = otx2_atomic64_add((qidx << 44), ptr); 1315 1316 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1317 (val & NIX_CQERRINT_BITS)); 1318 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1319 continue; 1320 1321 if (val & BIT_ULL(42)) { 1322 netdev_err(pf->netdev, 1323 "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1324 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1325 } else { 1326 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1327 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1328 qidx); 1329 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1330 netdev_err(pf->netdev, 1331 "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1332 qidx); 1333 } 1334 1335 schedule_work(&pf->reset_task); 1336 } 1337 1338 /* SQ */ 1339 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1340 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg; 1341 u8 sq_op_err_code, mnq_err_code, snd_err_code; 1342 1343 sq = &pf->qset.sq[qidx]; 1344 if (!sq->sqb_ptrs) 1345 continue; 1346 1347 /* Below debug registers captures first errors corresponding to 1348 * those registers. We don't have to check against SQ qid as 1349 * these are fatal errors. 1350 */ 1351 1352 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1353 val = otx2_atomic64_add((qidx << 44), ptr); 1354 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1355 (val & NIX_SQINT_BITS)); 1356 1357 if (val & BIT_ULL(42)) { 1358 netdev_err(pf->netdev, 1359 "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1360 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1361 goto done; 1362 } 1363 1364 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG); 1365 if (!(sq_op_err_dbg & BIT(44))) 1366 goto chk_mnq_err_dbg; 1367 1368 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg); 1369 netdev_err(pf->netdev, 1370 "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(0x%llx) err=%s(%#x)\n", 1371 qidx, sq_op_err_dbg, 1372 nix_sqoperr_e_str[sq_op_err_code], 1373 sq_op_err_code); 1374 1375 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44)); 1376 1377 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL) 1378 goto chk_mnq_err_dbg; 1379 1380 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure. 1381 * TODO: But we are in irq context. How to call mbox functions which does sleep 1382 */ 1383 1384 chk_mnq_err_dbg: 1385 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG); 1386 if (!(mnq_err_dbg & BIT(44))) 1387 goto chk_snd_err_dbg; 1388 1389 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg); 1390 netdev_err(pf->netdev, 1391 "SQ%lld: NIX_LF_MNQ_ERR_DBG(0x%llx) err=%s(%#x)\n", 1392 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code], 1393 mnq_err_code); 1394 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44)); 1395 1396 chk_snd_err_dbg: 1397 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG); 1398 if (snd_err_dbg & BIT(44)) { 1399 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg); 1400 netdev_err(pf->netdev, 1401 "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s(%#x)\n", 1402 qidx, snd_err_dbg, 1403 nix_snd_status_e_str[snd_err_code], 1404 snd_err_code); 1405 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44)); 1406 } 1407 1408 done: 1409 /* Print values and reset */ 1410 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1411 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1412 qidx); 1413 1414 schedule_work(&pf->reset_task); 1415 } 1416 1417 return IRQ_HANDLED; 1418 } 1419 1420 irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1421 { 1422 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1423 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1424 int qidx = cq_poll->cint_idx; 1425 1426 /* Disable interrupts. 1427 * 1428 * Completion interrupts behave in a level-triggered interrupt 1429 * fashion, and hence have to be cleared only after it is serviced. 1430 */ 1431 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1432 1433 /* Schedule NAPI */ 1434 pf->napi_events++; 1435 napi_schedule_irqoff(&cq_poll->napi); 1436 1437 return IRQ_HANDLED; 1438 } 1439 EXPORT_SYMBOL(otx2_cq_intr_handler); 1440 1441 void otx2_disable_napi(struct otx2_nic *pf) 1442 { 1443 struct otx2_qset *qset = &pf->qset; 1444 struct otx2_cq_poll *cq_poll; 1445 struct work_struct *work; 1446 int qidx; 1447 1448 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1449 cq_poll = &qset->napi[qidx]; 1450 work = &cq_poll->dim.work; 1451 if (work->func) 1452 cancel_work_sync(work); 1453 napi_disable(&cq_poll->napi); 1454 netif_napi_del(&cq_poll->napi); 1455 } 1456 } 1457 EXPORT_SYMBOL(otx2_disable_napi); 1458 1459 static void otx2_free_cq_res(struct otx2_nic *pf) 1460 { 1461 struct otx2_qset *qset = &pf->qset; 1462 struct otx2_cq_queue *cq; 1463 int qidx; 1464 1465 /* Disable CQs */ 1466 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1467 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1468 cq = &qset->cq[qidx]; 1469 qmem_free(pf->dev, cq->cqe); 1470 } 1471 } 1472 1473 static void otx2_free_sq_res(struct otx2_nic *pf) 1474 { 1475 struct otx2_qset *qset = &pf->qset; 1476 struct otx2_snd_queue *sq; 1477 int qidx; 1478 1479 /* Disable SQs */ 1480 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1481 /* Free SQB pointers */ 1482 otx2_sq_free_sqbs(pf); 1483 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1484 sq = &qset->sq[qidx]; 1485 /* Skip freeing Qos queues if they are not initialized */ 1486 if (!sq->sqe) 1487 continue; 1488 qmem_free(pf->dev, sq->sqe); 1489 qmem_free(pf->dev, sq->sqe_ring); 1490 qmem_free(pf->dev, sq->cpt_resp); 1491 qmem_free(pf->dev, sq->tso_hdrs); 1492 kfree(sq->sg); 1493 kfree(sq->sqb_ptrs); 1494 } 1495 } 1496 1497 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1498 { 1499 int frame_size; 1500 int total_size; 1501 int rbuf_size; 1502 1503 if (pf->hw.rbuf_len) 1504 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1505 1506 /* The data transferred by NIX to memory consists of actual packet 1507 * plus additional data which has timestamp and/or EDSA/HIGIG2 1508 * headers if interface is configured in corresponding modes. 1509 * NIX transfers entire data using 6 segments/buffers and writes 1510 * a CQE_RX descriptor with those segment addresses. First segment 1511 * has additional data prepended to packet. Also software omits a 1512 * headroom of 128 bytes in each segment. Hence the total size of 1513 * memory needed to receive a packet with 'mtu' is: 1514 * frame size = mtu + additional data; 1515 * memory = frame_size + headroom * 6; 1516 * each receive buffer size = memory / 6; 1517 */ 1518 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1519 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1520 rbuf_size = total_size / 6; 1521 1522 return ALIGN(rbuf_size, 2048); 1523 } 1524 1525 int otx2_init_hw_resources(struct otx2_nic *pf) 1526 { 1527 struct nix_lf_free_req *free_req; 1528 struct mbox *mbox = &pf->mbox; 1529 struct otx2_hw *hw = &pf->hw; 1530 struct msg_req *req; 1531 int err = 0, lvl; 1532 1533 /* Set required NPA LF's pool counts 1534 * Auras and Pools are used in a 1:1 mapping, 1535 * so, aura count = pool count. 1536 */ 1537 hw->rqpool_cnt = hw->rx_queues; 1538 hw->sqpool_cnt = otx2_get_total_tx_queues(pf); 1539 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1540 1541 if (!otx2_rep_dev(pf->pdev)) { 1542 /* Maximum hardware supported transmit length */ 1543 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1544 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1545 } 1546 1547 mutex_lock(&mbox->lock); 1548 /* NPA init */ 1549 err = otx2_config_npa(pf); 1550 if (err) 1551 goto exit; 1552 1553 /* NIX init */ 1554 err = otx2_config_nix(pf); 1555 if (err) 1556 goto err_free_npa_lf; 1557 1558 /* Default disable backpressure on NIX-CPT */ 1559 otx2_nix_cpt_config_bp(pf, false); 1560 1561 /* Enable backpressure for CGX mapped PF/VFs */ 1562 if (!is_otx2_lbkvf(pf->pdev)) 1563 otx2_nix_config_bp(pf, true); 1564 1565 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1566 err = otx2_rq_aura_pool_init(pf); 1567 if (err) { 1568 mutex_unlock(&mbox->lock); 1569 goto err_free_nix_lf; 1570 } 1571 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1572 err = otx2_sq_aura_pool_init(pf); 1573 if (err) { 1574 mutex_unlock(&mbox->lock); 1575 goto err_free_rq_ptrs; 1576 } 1577 1578 err = otx2_txsch_alloc(pf); 1579 if (err) { 1580 mutex_unlock(&mbox->lock); 1581 goto err_free_sq_ptrs; 1582 } 1583 1584 #ifdef CONFIG_DCB 1585 if (pf->pfc_en) { 1586 err = otx2_pfc_txschq_alloc(pf); 1587 if (err) { 1588 mutex_unlock(&mbox->lock); 1589 goto err_free_sq_ptrs; 1590 } 1591 } 1592 #endif 1593 1594 err = otx2_config_nix_queues(pf); 1595 if (err) { 1596 mutex_unlock(&mbox->lock); 1597 goto err_free_txsch; 1598 } 1599 1600 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1601 int idx; 1602 1603 for (idx = 0; idx < pf->hw.txschq_cnt[lvl]; idx++) { 1604 err = otx2_txschq_config(pf, lvl, idx, false); 1605 if (err) { 1606 dev_err(pf->dev, "Failed to config TXSCH\n"); 1607 mutex_unlock(&mbox->lock); 1608 goto err_free_nix_queues; 1609 } 1610 } 1611 } 1612 1613 #ifdef CONFIG_DCB 1614 if (pf->pfc_en) { 1615 err = otx2_pfc_txschq_config(pf); 1616 if (err) { 1617 mutex_unlock(&mbox->lock); 1618 goto err_free_nix_queues; 1619 } 1620 } 1621 #endif 1622 1623 mutex_unlock(&mbox->lock); 1624 return err; 1625 1626 err_free_nix_queues: 1627 otx2_free_sq_res(pf); 1628 otx2_free_cq_res(pf); 1629 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1630 err_free_txsch: 1631 otx2_txschq_stop(pf); 1632 err_free_sq_ptrs: 1633 otx2_sq_free_sqbs(pf); 1634 err_free_rq_ptrs: 1635 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1636 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1637 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1638 otx2_aura_pool_free(pf); 1639 err_free_nix_lf: 1640 mutex_lock(&mbox->lock); 1641 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1642 if (free_req) { 1643 free_req->flags = NIX_LF_DISABLE_FLOWS; 1644 if (otx2_sync_mbox_msg(mbox)) 1645 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1646 } 1647 err_free_npa_lf: 1648 /* Reset NPA LF */ 1649 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1650 if (req) { 1651 if (otx2_sync_mbox_msg(mbox)) 1652 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1653 } 1654 exit: 1655 mutex_unlock(&mbox->lock); 1656 return err; 1657 } 1658 EXPORT_SYMBOL(otx2_init_hw_resources); 1659 1660 void otx2_free_hw_resources(struct otx2_nic *pf) 1661 { 1662 struct otx2_qset *qset = &pf->qset; 1663 struct nix_lf_free_req *free_req; 1664 struct mbox *mbox = &pf->mbox; 1665 struct otx2_cq_queue *cq; 1666 struct msg_req *req; 1667 int qidx; 1668 1669 /* Ensure all SQE are processed */ 1670 otx2_sqb_flush(pf); 1671 1672 /* Stop transmission */ 1673 otx2_txschq_stop(pf); 1674 1675 #ifdef CONFIG_DCB 1676 if (pf->pfc_en) 1677 otx2_pfc_txschq_stop(pf); 1678 #endif 1679 1680 if (!otx2_rep_dev(pf->pdev)) 1681 otx2_clean_qos_queues(pf); 1682 1683 mutex_lock(&mbox->lock); 1684 /* Disable backpressure */ 1685 if (!is_otx2_lbkvf(pf->pdev)) 1686 otx2_nix_config_bp(pf, false); 1687 mutex_unlock(&mbox->lock); 1688 1689 /* Disable RQs */ 1690 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1691 1692 /*Dequeue all CQEs */ 1693 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1694 cq = &qset->cq[qidx]; 1695 if (cq->cq_type == CQ_RX) 1696 otx2_cleanup_rx_cqes(pf, cq, qidx); 1697 else 1698 otx2_cleanup_tx_cqes(pf, cq); 1699 } 1700 otx2_free_pending_sqe(pf); 1701 1702 otx2_free_sq_res(pf); 1703 1704 /* Free RQ buffer pointers*/ 1705 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1706 1707 otx2_free_cq_res(pf); 1708 1709 /* Free all ingress bandwidth profiles allocated */ 1710 if (!otx2_rep_dev(pf->pdev)) 1711 cn10k_free_all_ipolicers(pf); 1712 1713 mutex_lock(&mbox->lock); 1714 /* Reset NIX LF */ 1715 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1716 if (free_req) { 1717 free_req->flags = NIX_LF_DISABLE_FLOWS; 1718 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1719 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1720 if (otx2_sync_mbox_msg(mbox)) 1721 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1722 } 1723 mutex_unlock(&mbox->lock); 1724 1725 /* Disable NPA Pool and Aura hw context */ 1726 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1727 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1728 otx2_aura_pool_free(pf); 1729 1730 mutex_lock(&mbox->lock); 1731 /* Reset NPA LF */ 1732 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1733 if (req) { 1734 if (otx2_sync_mbox_msg(mbox)) 1735 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1736 } 1737 mutex_unlock(&mbox->lock); 1738 } 1739 EXPORT_SYMBOL(otx2_free_hw_resources); 1740 1741 static bool otx2_promisc_use_mce_list(struct otx2_nic *pfvf) 1742 { 1743 int vf; 1744 1745 /* The AF driver will determine whether to allow the VF netdev or not */ 1746 if (is_otx2_vf(pfvf->pcifunc)) 1747 return true; 1748 1749 /* check if there are any trusted VFs associated with the PF netdev */ 1750 for (vf = 0; vf < pci_num_vf(pfvf->pdev); vf++) 1751 if (pfvf->vf_configs[vf].trusted) 1752 return true; 1753 return false; 1754 } 1755 1756 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1757 { 1758 struct net_device *netdev = pf->netdev; 1759 struct nix_rx_mode *req; 1760 bool promisc = false; 1761 1762 if (!(netdev->flags & IFF_UP)) 1763 return; 1764 1765 if ((netdev->flags & IFF_PROMISC) || 1766 (netdev_uc_count(netdev) > pf->flow_cfg->ucast_flt_cnt)) { 1767 promisc = true; 1768 } 1769 1770 /* Write unicast address to mcam entries or del from mcam */ 1771 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1772 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1773 1774 mutex_lock(&pf->mbox.lock); 1775 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1776 if (!req) { 1777 mutex_unlock(&pf->mbox.lock); 1778 return; 1779 } 1780 1781 req->mode = NIX_RX_MODE_UCAST; 1782 1783 if (promisc) 1784 req->mode |= NIX_RX_MODE_PROMISC; 1785 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1786 req->mode |= NIX_RX_MODE_ALLMULTI; 1787 1788 if (otx2_promisc_use_mce_list(pf)) 1789 req->mode |= NIX_RX_MODE_USE_MCE; 1790 1791 otx2_sync_mbox_msg(&pf->mbox); 1792 mutex_unlock(&pf->mbox.lock); 1793 } 1794 1795 static void otx2_set_irq_coalesce(struct otx2_nic *pfvf) 1796 { 1797 int cint; 1798 1799 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++) 1800 otx2_config_irq_coalescing(pfvf, cint); 1801 } 1802 1803 static void otx2_dim_work(struct work_struct *w) 1804 { 1805 struct dim_cq_moder cur_moder; 1806 struct otx2_cq_poll *cq_poll; 1807 struct otx2_nic *pfvf; 1808 struct dim *dim; 1809 1810 dim = container_of(w, struct dim, work); 1811 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1812 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1813 pfvf = (struct otx2_nic *)cq_poll->dev; 1814 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1815 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1816 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1817 NAPI_POLL_WEIGHT : cur_moder.pkts; 1818 otx2_set_irq_coalesce(pfvf); 1819 dim->state = DIM_START_MEASURE; 1820 } 1821 1822 void otx2_free_queue_mem(struct otx2_qset *qset) 1823 { 1824 kfree(qset->sq); 1825 qset->sq = NULL; 1826 kfree(qset->cq); 1827 qset->cq = NULL; 1828 kfree(qset->rq); 1829 qset->rq = NULL; 1830 kfree(qset->napi); 1831 qset->napi = NULL; 1832 } 1833 EXPORT_SYMBOL(otx2_free_queue_mem); 1834 1835 int otx2_alloc_queue_mem(struct otx2_nic *pf) 1836 { 1837 struct otx2_qset *qset = &pf->qset; 1838 struct otx2_cq_poll *cq_poll; 1839 1840 1841 /* RQ and SQs are mapped to different CQs, 1842 * so find out max CQ IRQs (i.e CINTs) needed. 1843 */ 1844 pf->hw.non_qos_queues = pf->hw.tx_queues + pf->hw.xdp_queues; 1845 pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues, 1846 pf->hw.tc_tx_queues); 1847 1848 pf->qset.cq_cnt = pf->hw.rx_queues + otx2_get_total_tx_queues(pf); 1849 1850 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1851 if (!qset->napi) 1852 return -ENOMEM; 1853 1854 /* CQ size of RQ */ 1855 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1856 /* CQ size of SQ */ 1857 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1858 1859 qset->cq = kcalloc(pf->qset.cq_cnt, 1860 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1861 if (!qset->cq) 1862 goto err_free_mem; 1863 1864 qset->sq = kcalloc(otx2_get_total_tx_queues(pf), 1865 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1866 if (!qset->sq) 1867 goto err_free_mem; 1868 1869 qset->rq = kcalloc(pf->hw.rx_queues, 1870 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1871 if (!qset->rq) 1872 goto err_free_mem; 1873 1874 return 0; 1875 1876 err_free_mem: 1877 otx2_free_queue_mem(qset); 1878 return -ENOMEM; 1879 } 1880 EXPORT_SYMBOL(otx2_alloc_queue_mem); 1881 1882 int otx2_open(struct net_device *netdev) 1883 { 1884 struct otx2_nic *pf = netdev_priv(netdev); 1885 struct otx2_cq_poll *cq_poll = NULL; 1886 struct otx2_qset *qset = &pf->qset; 1887 int err = 0, qidx, vec; 1888 char *irq_name; 1889 1890 netif_carrier_off(netdev); 1891 1892 err = otx2_alloc_queue_mem(pf); 1893 if (err) 1894 return err; 1895 1896 err = otx2_init_hw_resources(pf); 1897 if (err) 1898 goto err_free_mem; 1899 1900 /* Register NAPI handler */ 1901 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1902 cq_poll = &qset->napi[qidx]; 1903 cq_poll->cint_idx = qidx; 1904 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1905 * 'cq_ids[0]' points to RQ's CQ and 1906 * 'cq_ids[1]' points to SQ's CQ and 1907 * 'cq_ids[2]' points to XDP's CQ and 1908 */ 1909 cq_poll->cq_ids[CQ_RX] = 1910 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1911 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1912 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1913 if (pf->xdp_prog) 1914 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1915 (qidx + pf->hw.rx_queues + 1916 pf->hw.tx_queues) : 1917 CINT_INVALID_CQ; 1918 else 1919 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1920 1921 cq_poll->cq_ids[CQ_QOS] = (qidx < pf->hw.tc_tx_queues) ? 1922 (qidx + pf->hw.rx_queues + 1923 pf->hw.non_qos_queues) : 1924 CINT_INVALID_CQ; 1925 1926 cq_poll->dev = (void *)pf; 1927 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1928 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1929 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1930 napi_enable(&cq_poll->napi); 1931 } 1932 1933 /* Set maximum frame size allowed in HW */ 1934 err = otx2_hw_set_mtu(pf, netdev->mtu); 1935 if (err) 1936 goto err_disable_napi; 1937 1938 /* Setup segmentation algorithms, if failed, clear offload capability */ 1939 otx2_setup_segmentation(pf); 1940 1941 /* Initialize RSS */ 1942 err = otx2_rss_init(pf); 1943 if (err) 1944 goto err_disable_napi; 1945 1946 /* Register Queue IRQ handlers */ 1947 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1948 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1949 1950 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1951 1952 err = request_irq(pci_irq_vector(pf->pdev, vec), 1953 otx2_q_intr_handler, 0, irq_name, pf); 1954 if (err) { 1955 dev_err(pf->dev, 1956 "RVUPF%d: IRQ registration failed for QERR\n", 1957 rvu_get_pf(pf->pcifunc)); 1958 goto err_disable_napi; 1959 } 1960 1961 /* Enable QINT IRQ */ 1962 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1963 1964 /* Register CQ IRQ handlers */ 1965 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1966 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1967 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1968 int name_len; 1969 1970 name_len = snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", 1971 pf->netdev->name, qidx); 1972 if (name_len >= NAME_SIZE) { 1973 dev_err(pf->dev, 1974 "RVUPF%d: IRQ registration failed for CQ%d, irq name is too long\n", 1975 rvu_get_pf(pf->pcifunc), qidx); 1976 err = -EINVAL; 1977 goto err_free_cints; 1978 } 1979 1980 err = request_irq(pci_irq_vector(pf->pdev, vec), 1981 otx2_cq_intr_handler, 0, irq_name, 1982 &qset->napi[qidx]); 1983 if (err) { 1984 dev_err(pf->dev, 1985 "RVUPF%d: IRQ registration failed for CQ%d\n", 1986 rvu_get_pf(pf->pcifunc), qidx); 1987 goto err_free_cints; 1988 } 1989 vec++; 1990 1991 otx2_config_irq_coalescing(pf, qidx); 1992 1993 /* Enable CQ IRQ */ 1994 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1995 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1996 } 1997 1998 otx2_set_cints_affinity(pf); 1999 2000 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2001 otx2_enable_rxvlan(pf, true); 2002 2003 /* When reinitializing enable time stamping if it is enabled before */ 2004 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 2005 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2006 otx2_config_hw_tx_tstamp(pf, true); 2007 } 2008 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 2009 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2010 otx2_config_hw_rx_tstamp(pf, true); 2011 } 2012 2013 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 2014 pf->flags &= ~OTX2_FLAG_PORT_UP; 2015 /* 'intf_down' may be checked on any cpu */ 2016 smp_wmb(); 2017 2018 /* Enable QoS configuration before starting tx queues */ 2019 otx2_qos_config_txschq(pf); 2020 2021 /* we have already received link status notification */ 2022 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 2023 otx2_handle_link_event(pf); 2024 2025 /* Install DMAC Filters */ 2026 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 2027 otx2_dmacflt_reinstall_flows(pf); 2028 2029 otx2_tc_apply_ingress_police_rules(pf); 2030 2031 err = otx2_rxtx_enable(pf, true); 2032 /* If a mbox communication error happens at this point then interface 2033 * will end up in a state such that it is in down state but hardware 2034 * mcam entries are enabled to receive the packets. Hence disable the 2035 * packet I/O. 2036 */ 2037 if (err == -EIO) 2038 goto err_disable_rxtx; 2039 else if (err) 2040 goto err_tx_stop_queues; 2041 2042 otx2_do_set_rx_mode(pf); 2043 2044 return 0; 2045 2046 err_disable_rxtx: 2047 otx2_rxtx_enable(pf, false); 2048 err_tx_stop_queues: 2049 netif_tx_stop_all_queues(netdev); 2050 netif_carrier_off(netdev); 2051 pf->flags |= OTX2_FLAG_INTF_DOWN; 2052 err_free_cints: 2053 otx2_free_cints(pf, qidx); 2054 vec = pci_irq_vector(pf->pdev, 2055 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 2056 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 2057 free_irq(vec, pf); 2058 err_disable_napi: 2059 otx2_disable_napi(pf); 2060 otx2_free_hw_resources(pf); 2061 err_free_mem: 2062 otx2_free_queue_mem(qset); 2063 return err; 2064 } 2065 EXPORT_SYMBOL(otx2_open); 2066 2067 int otx2_stop(struct net_device *netdev) 2068 { 2069 struct otx2_nic *pf = netdev_priv(netdev); 2070 struct otx2_cq_poll *cq_poll = NULL; 2071 struct otx2_qset *qset = &pf->qset; 2072 struct otx2_rss_info *rss; 2073 int qidx, vec, wrk; 2074 2075 /* If the DOWN flag is set resources are already freed */ 2076 if (pf->flags & OTX2_FLAG_INTF_DOWN) 2077 return 0; 2078 2079 netif_carrier_off(netdev); 2080 netif_tx_stop_all_queues(netdev); 2081 2082 pf->flags |= OTX2_FLAG_INTF_DOWN; 2083 /* 'intf_down' may be checked on any cpu */ 2084 smp_wmb(); 2085 2086 /* First stop packet Rx/Tx */ 2087 otx2_rxtx_enable(pf, false); 2088 2089 /* Clear RSS enable flag */ 2090 rss = &pf->hw.rss_info; 2091 rss->enable = false; 2092 if (!netif_is_rxfh_configured(netdev)) 2093 kfree(rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 2094 2095 /* Cleanup Queue IRQ */ 2096 vec = pci_irq_vector(pf->pdev, 2097 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 2098 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 2099 free_irq(vec, pf); 2100 2101 /* Cleanup CQ NAPI and IRQ */ 2102 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 2103 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 2104 /* Disable interrupt */ 2105 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 2106 2107 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 2108 2109 cq_poll = &qset->napi[qidx]; 2110 napi_synchronize(&cq_poll->napi); 2111 vec++; 2112 } 2113 2114 netif_tx_disable(netdev); 2115 2116 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 2117 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 2118 devm_kfree(pf->dev, pf->refill_wrk); 2119 2120 otx2_free_hw_resources(pf); 2121 otx2_free_cints(pf, pf->hw.cint_cnt); 2122 otx2_disable_napi(pf); 2123 2124 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 2125 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 2126 2127 otx2_free_queue_mem(qset); 2128 /* Do not clear RQ/SQ ringsize settings */ 2129 memset_startat(qset, 0, sqe_cnt); 2130 return 0; 2131 } 2132 EXPORT_SYMBOL(otx2_stop); 2133 2134 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 2135 { 2136 struct otx2_nic *pf = netdev_priv(netdev); 2137 int qidx = skb_get_queue_mapping(skb); 2138 struct otx2_snd_queue *sq; 2139 struct netdev_queue *txq; 2140 int sq_idx; 2141 2142 /* XDP SQs are not mapped with TXQs 2143 * advance qid to derive correct sq mapped with QOS 2144 */ 2145 sq_idx = (qidx >= pf->hw.tx_queues) ? (qidx + pf->hw.xdp_queues) : qidx; 2146 2147 /* Check for minimum and maximum packet length */ 2148 if (skb->len <= ETH_HLEN || 2149 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 2150 dev_kfree_skb(skb); 2151 return NETDEV_TX_OK; 2152 } 2153 2154 sq = &pf->qset.sq[sq_idx]; 2155 txq = netdev_get_tx_queue(netdev, qidx); 2156 2157 if (!otx2_sq_append_skb(pf, txq, sq, skb, qidx)) { 2158 netif_tx_stop_queue(txq); 2159 2160 /* Check again, incase SQBs got freed up */ 2161 smp_mb(); 2162 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 2163 > sq->sqe_thresh) 2164 netif_tx_wake_queue(txq); 2165 2166 return NETDEV_TX_BUSY; 2167 } 2168 2169 return NETDEV_TX_OK; 2170 } 2171 2172 static int otx2_qos_select_htb_queue(struct otx2_nic *pf, struct sk_buff *skb, 2173 u16 htb_maj_id) 2174 { 2175 u16 classid; 2176 2177 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id) 2178 classid = TC_H_MIN(skb->priority); 2179 else 2180 classid = READ_ONCE(pf->qos.defcls); 2181 2182 if (!classid) 2183 return 0; 2184 2185 return otx2_get_txq_by_classid(pf, classid); 2186 } 2187 2188 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 2189 struct net_device *sb_dev) 2190 { 2191 struct otx2_nic *pf = netdev_priv(netdev); 2192 bool qos_enabled; 2193 #ifdef CONFIG_DCB 2194 u8 vlan_prio; 2195 #endif 2196 int txq; 2197 2198 qos_enabled = netdev->real_num_tx_queues > pf->hw.tx_queues; 2199 if (unlikely(qos_enabled)) { 2200 /* This smp_load_acquire() pairs with smp_store_release() in 2201 * otx2_qos_root_add() called from htb offload root creation 2202 */ 2203 u16 htb_maj_id = smp_load_acquire(&pf->qos.maj_id); 2204 2205 if (unlikely(htb_maj_id)) { 2206 txq = otx2_qos_select_htb_queue(pf, skb, htb_maj_id); 2207 if (txq > 0) 2208 return txq; 2209 goto process_pfc; 2210 } 2211 } 2212 2213 process_pfc: 2214 #ifdef CONFIG_DCB 2215 if (!skb_vlan_tag_present(skb)) 2216 goto pick_tx; 2217 2218 vlan_prio = skb->vlan_tci >> 13; 2219 if ((vlan_prio > pf->hw.tx_queues - 1) || 2220 !pf->pfc_alloc_status[vlan_prio]) 2221 goto pick_tx; 2222 2223 return vlan_prio; 2224 2225 pick_tx: 2226 #endif 2227 txq = netdev_pick_tx(netdev, skb, NULL); 2228 if (unlikely(qos_enabled)) 2229 return txq % pf->hw.tx_queues; 2230 2231 return txq; 2232 } 2233 EXPORT_SYMBOL(otx2_select_queue); 2234 2235 static netdev_features_t otx2_fix_features(struct net_device *dev, 2236 netdev_features_t features) 2237 { 2238 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2239 features |= NETIF_F_HW_VLAN_STAG_RX; 2240 else 2241 features &= ~NETIF_F_HW_VLAN_STAG_RX; 2242 2243 return features; 2244 } 2245 2246 static void otx2_set_rx_mode(struct net_device *netdev) 2247 { 2248 struct otx2_nic *pf = netdev_priv(netdev); 2249 2250 queue_work(pf->otx2_wq, &pf->rx_mode_work); 2251 } 2252 2253 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 2254 { 2255 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 2256 2257 otx2_do_set_rx_mode(pf); 2258 } 2259 2260 static int otx2_set_features(struct net_device *netdev, 2261 netdev_features_t features) 2262 { 2263 netdev_features_t changed = features ^ netdev->features; 2264 struct otx2_nic *pf = netdev_priv(netdev); 2265 2266 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 2267 return otx2_cgx_config_loopback(pf, 2268 features & NETIF_F_LOOPBACK); 2269 2270 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 2271 return otx2_enable_rxvlan(pf, 2272 features & NETIF_F_HW_VLAN_CTAG_RX); 2273 2274 if (changed & NETIF_F_HW_ESP) 2275 return cn10k_ipsec_ethtool_init(netdev, 2276 features & NETIF_F_HW_ESP); 2277 2278 return otx2_handle_ntuple_tc_features(netdev, features); 2279 } 2280 2281 static void otx2_reset_task(struct work_struct *work) 2282 { 2283 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 2284 2285 if (!netif_running(pf->netdev)) 2286 return; 2287 2288 rtnl_lock(); 2289 otx2_stop(pf->netdev); 2290 pf->reset_count++; 2291 otx2_open(pf->netdev); 2292 netif_trans_update(pf->netdev); 2293 rtnl_unlock(); 2294 } 2295 2296 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 2297 { 2298 struct msg_req *req; 2299 int err; 2300 2301 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 2302 return 0; 2303 2304 mutex_lock(&pfvf->mbox.lock); 2305 if (enable) 2306 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 2307 else 2308 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 2309 if (!req) { 2310 mutex_unlock(&pfvf->mbox.lock); 2311 return -ENOMEM; 2312 } 2313 2314 err = otx2_sync_mbox_msg(&pfvf->mbox); 2315 if (err) { 2316 mutex_unlock(&pfvf->mbox.lock); 2317 return err; 2318 } 2319 2320 mutex_unlock(&pfvf->mbox.lock); 2321 if (enable) 2322 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2323 else 2324 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2325 return 0; 2326 } 2327 2328 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2329 { 2330 struct msg_req *req; 2331 int err; 2332 2333 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2334 return 0; 2335 2336 mutex_lock(&pfvf->mbox.lock); 2337 if (enable) 2338 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2339 else 2340 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2341 if (!req) { 2342 mutex_unlock(&pfvf->mbox.lock); 2343 return -ENOMEM; 2344 } 2345 2346 err = otx2_sync_mbox_msg(&pfvf->mbox); 2347 if (err) { 2348 mutex_unlock(&pfvf->mbox.lock); 2349 return err; 2350 } 2351 2352 mutex_unlock(&pfvf->mbox.lock); 2353 if (enable) 2354 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2355 else 2356 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2357 return 0; 2358 } 2359 2360 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2361 { 2362 struct otx2_nic *pfvf = netdev_priv(netdev); 2363 struct hwtstamp_config config; 2364 2365 if (!pfvf->ptp) 2366 return -ENODEV; 2367 2368 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2369 return -EFAULT; 2370 2371 switch (config.tx_type) { 2372 case HWTSTAMP_TX_OFF: 2373 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2374 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2375 2376 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2377 otx2_config_hw_tx_tstamp(pfvf, false); 2378 break; 2379 case HWTSTAMP_TX_ONESTEP_SYNC: 2380 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2381 return -ERANGE; 2382 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2383 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2384 msecs_to_jiffies(500)); 2385 fallthrough; 2386 case HWTSTAMP_TX_ON: 2387 otx2_config_hw_tx_tstamp(pfvf, true); 2388 break; 2389 default: 2390 return -ERANGE; 2391 } 2392 2393 switch (config.rx_filter) { 2394 case HWTSTAMP_FILTER_NONE: 2395 otx2_config_hw_rx_tstamp(pfvf, false); 2396 break; 2397 case HWTSTAMP_FILTER_ALL: 2398 case HWTSTAMP_FILTER_SOME: 2399 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2400 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2401 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2402 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2403 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2404 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2405 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2406 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2407 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2408 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2409 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2410 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2411 otx2_config_hw_rx_tstamp(pfvf, true); 2412 config.rx_filter = HWTSTAMP_FILTER_ALL; 2413 break; 2414 default: 2415 return -ERANGE; 2416 } 2417 2418 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2419 2420 return copy_to_user(ifr->ifr_data, &config, 2421 sizeof(config)) ? -EFAULT : 0; 2422 } 2423 EXPORT_SYMBOL(otx2_config_hwtstamp); 2424 2425 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2426 { 2427 struct otx2_nic *pfvf = netdev_priv(netdev); 2428 struct hwtstamp_config *cfg = &pfvf->tstamp; 2429 2430 switch (cmd) { 2431 case SIOCSHWTSTAMP: 2432 return otx2_config_hwtstamp(netdev, req); 2433 case SIOCGHWTSTAMP: 2434 return copy_to_user(req->ifr_data, cfg, 2435 sizeof(*cfg)) ? -EFAULT : 0; 2436 default: 2437 return -EOPNOTSUPP; 2438 } 2439 } 2440 EXPORT_SYMBOL(otx2_ioctl); 2441 2442 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2443 { 2444 struct npc_install_flow_req *req; 2445 int err; 2446 2447 mutex_lock(&pf->mbox.lock); 2448 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2449 if (!req) { 2450 err = -ENOMEM; 2451 goto out; 2452 } 2453 2454 ether_addr_copy(req->packet.dmac, mac); 2455 eth_broadcast_addr((u8 *)&req->mask.dmac); 2456 req->features = BIT_ULL(NPC_DMAC); 2457 req->channel = pf->hw.rx_chan_base; 2458 req->intf = NIX_INTF_RX; 2459 req->default_rule = 1; 2460 req->append = 1; 2461 req->vf = vf + 1; 2462 req->op = NIX_RX_ACTION_DEFAULT; 2463 2464 err = otx2_sync_mbox_msg(&pf->mbox); 2465 out: 2466 mutex_unlock(&pf->mbox.lock); 2467 return err; 2468 } 2469 2470 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2471 { 2472 struct otx2_nic *pf = netdev_priv(netdev); 2473 struct pci_dev *pdev = pf->pdev; 2474 struct otx2_vf_config *config; 2475 int ret; 2476 2477 if (!netif_running(netdev)) 2478 return -EAGAIN; 2479 2480 if (vf >= pf->total_vfs) 2481 return -EINVAL; 2482 2483 if (!is_valid_ether_addr(mac)) 2484 return -EINVAL; 2485 2486 config = &pf->vf_configs[vf]; 2487 ether_addr_copy(config->mac, mac); 2488 2489 ret = otx2_do_set_vf_mac(pf, vf, mac); 2490 if (ret == 0) 2491 dev_info(&pdev->dev, 2492 "Load/Reload VF driver\n"); 2493 2494 return ret; 2495 } 2496 2497 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2498 __be16 proto) 2499 { 2500 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2501 struct nix_vtag_config_rsp *vtag_rsp; 2502 struct npc_delete_flow_req *del_req; 2503 struct nix_vtag_config *vtag_req; 2504 struct npc_install_flow_req *req; 2505 struct otx2_vf_config *config; 2506 int err = 0; 2507 u32 idx; 2508 2509 config = &pf->vf_configs[vf]; 2510 2511 if (!vlan && !config->vlan) 2512 goto out; 2513 2514 mutex_lock(&pf->mbox.lock); 2515 2516 /* free old tx vtag entry */ 2517 if (config->vlan) { 2518 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2519 if (!vtag_req) { 2520 err = -ENOMEM; 2521 goto out; 2522 } 2523 vtag_req->cfg_type = 0; 2524 vtag_req->tx.free_vtag0 = 1; 2525 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2526 2527 err = otx2_sync_mbox_msg(&pf->mbox); 2528 if (err) 2529 goto out; 2530 } 2531 2532 if (!vlan && config->vlan) { 2533 /* rx */ 2534 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2535 if (!del_req) { 2536 err = -ENOMEM; 2537 goto out; 2538 } 2539 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2540 del_req->entry = 2541 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2542 err = otx2_sync_mbox_msg(&pf->mbox); 2543 if (err) 2544 goto out; 2545 2546 /* tx */ 2547 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2548 if (!del_req) { 2549 err = -ENOMEM; 2550 goto out; 2551 } 2552 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2553 del_req->entry = 2554 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2555 err = otx2_sync_mbox_msg(&pf->mbox); 2556 2557 goto out; 2558 } 2559 2560 /* rx */ 2561 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2562 if (!req) { 2563 err = -ENOMEM; 2564 goto out; 2565 } 2566 2567 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2568 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2569 req->packet.vlan_tci = htons(vlan); 2570 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2571 /* af fills the destination mac addr */ 2572 eth_broadcast_addr((u8 *)&req->mask.dmac); 2573 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2574 req->channel = pf->hw.rx_chan_base; 2575 req->intf = NIX_INTF_RX; 2576 req->vf = vf + 1; 2577 req->op = NIX_RX_ACTION_DEFAULT; 2578 req->vtag0_valid = true; 2579 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2580 req->set_cntr = 1; 2581 2582 err = otx2_sync_mbox_msg(&pf->mbox); 2583 if (err) 2584 goto out; 2585 2586 /* tx */ 2587 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2588 if (!vtag_req) { 2589 err = -ENOMEM; 2590 goto out; 2591 } 2592 2593 /* configure tx vtag params */ 2594 vtag_req->vtag_size = VTAGSIZE_T4; 2595 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2596 vtag_req->tx.cfg_vtag0 = 1; 2597 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2598 2599 err = otx2_sync_mbox_msg(&pf->mbox); 2600 if (err) 2601 goto out; 2602 2603 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2604 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2605 if (IS_ERR(vtag_rsp)) { 2606 err = PTR_ERR(vtag_rsp); 2607 goto out; 2608 } 2609 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2610 2611 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2612 if (!req) { 2613 err = -ENOMEM; 2614 goto out; 2615 } 2616 2617 eth_zero_addr((u8 *)&req->mask.dmac); 2618 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2619 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2620 req->features = BIT_ULL(NPC_DMAC); 2621 req->channel = pf->hw.tx_chan_base; 2622 req->intf = NIX_INTF_TX; 2623 req->vf = vf + 1; 2624 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2625 req->vtag0_def = vtag_rsp->vtag0_idx; 2626 req->vtag0_op = VTAG_INSERT; 2627 req->set_cntr = 1; 2628 2629 err = otx2_sync_mbox_msg(&pf->mbox); 2630 out: 2631 config->vlan = vlan; 2632 mutex_unlock(&pf->mbox.lock); 2633 return err; 2634 } 2635 2636 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2637 __be16 proto) 2638 { 2639 struct otx2_nic *pf = netdev_priv(netdev); 2640 struct pci_dev *pdev = pf->pdev; 2641 2642 if (!netif_running(netdev)) 2643 return -EAGAIN; 2644 2645 if (vf >= pci_num_vf(pdev)) 2646 return -EINVAL; 2647 2648 /* qos is currently unsupported */ 2649 if (vlan >= VLAN_N_VID || qos) 2650 return -EINVAL; 2651 2652 if (proto != htons(ETH_P_8021Q)) 2653 return -EPROTONOSUPPORT; 2654 2655 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2656 return -EOPNOTSUPP; 2657 2658 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2659 } 2660 2661 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2662 struct ifla_vf_info *ivi) 2663 { 2664 struct otx2_nic *pf = netdev_priv(netdev); 2665 struct pci_dev *pdev = pf->pdev; 2666 struct otx2_vf_config *config; 2667 2668 if (!netif_running(netdev)) 2669 return -EAGAIN; 2670 2671 if (vf >= pci_num_vf(pdev)) 2672 return -EINVAL; 2673 2674 config = &pf->vf_configs[vf]; 2675 ivi->vf = vf; 2676 ether_addr_copy(ivi->mac, config->mac); 2677 ivi->vlan = config->vlan; 2678 ivi->trusted = config->trusted; 2679 2680 return 0; 2681 } 2682 2683 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2684 int qidx) 2685 { 2686 u64 dma_addr; 2687 int err = 0; 2688 2689 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2690 offset_in_page(xdpf->data), xdpf->len, 2691 DMA_TO_DEVICE); 2692 if (dma_mapping_error(pf->dev, dma_addr)) 2693 return -ENOMEM; 2694 2695 err = otx2_xdp_sq_append_pkt(pf, xdpf, dma_addr, xdpf->len, 2696 qidx, OTX2_XDP_REDIRECT); 2697 if (!err) { 2698 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2699 xdp_return_frame(xdpf); 2700 return -ENOMEM; 2701 } 2702 return 0; 2703 } 2704 2705 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2706 struct xdp_frame **frames, u32 flags) 2707 { 2708 struct otx2_nic *pf = netdev_priv(netdev); 2709 int qidx = smp_processor_id(); 2710 struct otx2_snd_queue *sq; 2711 int drops = 0, i; 2712 2713 if (!netif_running(netdev)) 2714 return -ENETDOWN; 2715 2716 qidx += pf->hw.tx_queues; 2717 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2718 2719 /* Abort xmit if xdp queue is not */ 2720 if (unlikely(!sq)) 2721 return -ENXIO; 2722 2723 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2724 return -EINVAL; 2725 2726 for (i = 0; i < n; i++) { 2727 struct xdp_frame *xdpf = frames[i]; 2728 int err; 2729 2730 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2731 if (err) 2732 drops++; 2733 } 2734 return n - drops; 2735 } 2736 2737 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2738 { 2739 struct net_device *dev = pf->netdev; 2740 bool if_up = netif_running(pf->netdev); 2741 struct bpf_prog *old_prog; 2742 2743 if (prog && dev->mtu > MAX_XDP_MTU) { 2744 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2745 return -EOPNOTSUPP; 2746 } 2747 2748 if (if_up) 2749 otx2_stop(pf->netdev); 2750 2751 old_prog = xchg(&pf->xdp_prog, prog); 2752 2753 if (old_prog) 2754 bpf_prog_put(old_prog); 2755 2756 if (pf->xdp_prog) 2757 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2758 2759 /* Network stack and XDP shared same rx queues. 2760 * Use separate tx queues for XDP and network stack. 2761 */ 2762 if (pf->xdp_prog) { 2763 pf->hw.xdp_queues = pf->hw.rx_queues; 2764 xdp_features_set_redirect_target(dev, false); 2765 } else { 2766 pf->hw.xdp_queues = 0; 2767 xdp_features_clear_redirect_target(dev); 2768 } 2769 2770 if (if_up) 2771 otx2_open(pf->netdev); 2772 2773 return 0; 2774 } 2775 2776 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2777 { 2778 struct otx2_nic *pf = netdev_priv(netdev); 2779 2780 switch (xdp->command) { 2781 case XDP_SETUP_PROG: 2782 return otx2_xdp_setup(pf, xdp->prog); 2783 case XDP_SETUP_XSK_POOL: 2784 return otx2_xsk_pool_setup(pf, xdp->xsk.pool, xdp->xsk.queue_id); 2785 default: 2786 return -EINVAL; 2787 } 2788 } 2789 2790 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2791 int req_perm) 2792 { 2793 struct set_vf_perm *req; 2794 int rc; 2795 2796 mutex_lock(&pf->mbox.lock); 2797 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2798 if (!req) { 2799 rc = -ENOMEM; 2800 goto out; 2801 } 2802 2803 /* Let AF reset VF permissions as sriov is disabled */ 2804 if (req_perm == OTX2_RESET_VF_PERM) { 2805 req->flags |= RESET_VF_PERM; 2806 } else if (req_perm == OTX2_TRUSTED_VF) { 2807 if (pf->vf_configs[vf].trusted) 2808 req->flags |= VF_TRUSTED; 2809 } 2810 2811 req->vf = vf; 2812 rc = otx2_sync_mbox_msg(&pf->mbox); 2813 out: 2814 mutex_unlock(&pf->mbox.lock); 2815 return rc; 2816 } 2817 2818 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2819 bool enable) 2820 { 2821 struct otx2_nic *pf = netdev_priv(netdev); 2822 struct pci_dev *pdev = pf->pdev; 2823 int rc; 2824 2825 if (vf >= pci_num_vf(pdev)) 2826 return -EINVAL; 2827 2828 if (pf->vf_configs[vf].trusted == enable) 2829 return 0; 2830 2831 pf->vf_configs[vf].trusted = enable; 2832 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2833 2834 if (rc) { 2835 pf->vf_configs[vf].trusted = !enable; 2836 } else { 2837 netdev_info(pf->netdev, "VF %d is %strusted\n", 2838 vf, enable ? "" : "not "); 2839 otx2_set_rx_mode(netdev); 2840 } 2841 2842 return rc; 2843 } 2844 2845 static const struct net_device_ops otx2_netdev_ops = { 2846 .ndo_open = otx2_open, 2847 .ndo_stop = otx2_stop, 2848 .ndo_start_xmit = otx2_xmit, 2849 .ndo_select_queue = otx2_select_queue, 2850 .ndo_fix_features = otx2_fix_features, 2851 .ndo_set_mac_address = otx2_set_mac_address, 2852 .ndo_change_mtu = otx2_change_mtu, 2853 .ndo_set_rx_mode = otx2_set_rx_mode, 2854 .ndo_set_features = otx2_set_features, 2855 .ndo_tx_timeout = otx2_tx_timeout, 2856 .ndo_get_stats64 = otx2_get_stats64, 2857 .ndo_eth_ioctl = otx2_ioctl, 2858 .ndo_set_vf_mac = otx2_set_vf_mac, 2859 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2860 .ndo_get_vf_config = otx2_get_vf_config, 2861 .ndo_bpf = otx2_xdp, 2862 .ndo_xsk_wakeup = otx2_xsk_wakeup, 2863 .ndo_xdp_xmit = otx2_xdp_xmit, 2864 .ndo_setup_tc = otx2_setup_tc, 2865 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2866 }; 2867 2868 int otx2_wq_init(struct otx2_nic *pf) 2869 { 2870 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2871 if (!pf->otx2_wq) 2872 return -ENOMEM; 2873 2874 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2875 INIT_WORK(&pf->reset_task, otx2_reset_task); 2876 return 0; 2877 } 2878 2879 int otx2_check_pf_usable(struct otx2_nic *nic) 2880 { 2881 u64 rev; 2882 2883 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2884 rev = (rev >> 12) & 0xFF; 2885 /* Check if AF has setup revision for RVUM block, 2886 * otherwise this driver probe should be deferred 2887 * until AF driver comes up. 2888 */ 2889 if (!rev) { 2890 dev_warn(nic->dev, 2891 "AF is not initialized, deferring probe\n"); 2892 return -EPROBE_DEFER; 2893 } 2894 return 0; 2895 } 2896 2897 int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2898 { 2899 struct otx2_hw *hw = &pf->hw; 2900 int num_vec, err; 2901 2902 /* NPA interrupts are inot registered, so alloc only 2903 * upto NIX vector offset. 2904 */ 2905 num_vec = hw->nix_msixoff; 2906 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2907 2908 otx2_disable_mbox_intr(pf); 2909 pci_free_irq_vectors(hw->pdev); 2910 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2911 if (err < 0) { 2912 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2913 __func__, num_vec); 2914 return err; 2915 } 2916 2917 return otx2_register_mbox_intr(pf, false); 2918 } 2919 EXPORT_SYMBOL(otx2_realloc_msix_vectors); 2920 2921 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2922 { 2923 int i; 2924 2925 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2926 sizeof(struct otx2_vf_config), 2927 GFP_KERNEL); 2928 if (!pf->vf_configs) 2929 return -ENOMEM; 2930 2931 for (i = 0; i < pf->total_vfs; i++) { 2932 pf->vf_configs[i].pf = pf; 2933 pf->vf_configs[i].intf_down = true; 2934 pf->vf_configs[i].trusted = false; 2935 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2936 otx2_vf_link_event_task); 2937 } 2938 2939 return 0; 2940 } 2941 2942 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2943 { 2944 int i; 2945 2946 if (!pf->vf_configs) 2947 return; 2948 2949 for (i = 0; i < pf->total_vfs; i++) { 2950 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2951 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2952 } 2953 } 2954 2955 int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf) 2956 { 2957 struct device *dev = &pdev->dev; 2958 struct otx2_hw *hw = &pf->hw; 2959 int num_vec, err; 2960 2961 num_vec = pci_msix_vec_count(pdev); 2962 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2963 GFP_KERNEL); 2964 if (!hw->irq_name) 2965 return -ENOMEM; 2966 2967 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2968 sizeof(cpumask_var_t), GFP_KERNEL); 2969 if (!hw->affinity_mask) 2970 return -ENOMEM; 2971 2972 /* Map CSRs */ 2973 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2974 if (!pf->reg_base) { 2975 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2976 return -ENOMEM; 2977 } 2978 2979 err = otx2_check_pf_usable(pf); 2980 if (err) 2981 return err; 2982 2983 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2984 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2985 if (err < 0) { 2986 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2987 __func__, num_vec); 2988 return err; 2989 } 2990 2991 otx2_setup_dev_hw_settings(pf); 2992 2993 /* Init PF <=> AF mailbox stuff */ 2994 err = otx2_pfaf_mbox_init(pf); 2995 if (err) 2996 goto err_free_irq_vectors; 2997 2998 /* Register mailbox interrupt */ 2999 err = otx2_register_mbox_intr(pf, true); 3000 if (err) 3001 goto err_mbox_destroy; 3002 3003 /* Request AF to attach NPA and NIX LFs to this PF. 3004 * NIX and NPA LFs are needed for this PF to function as a NIC. 3005 */ 3006 err = otx2_attach_npa_nix(pf); 3007 if (err) 3008 goto err_disable_mbox_intr; 3009 3010 err = otx2_realloc_msix_vectors(pf); 3011 if (err) 3012 goto err_detach_rsrc; 3013 3014 err = cn10k_lmtst_init(pf); 3015 if (err) 3016 goto err_detach_rsrc; 3017 3018 return 0; 3019 3020 err_detach_rsrc: 3021 if (pf->hw.lmt_info) 3022 free_percpu(pf->hw.lmt_info); 3023 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3024 qmem_free(pf->dev, pf->dync_lmt); 3025 otx2_detach_resources(&pf->mbox); 3026 err_disable_mbox_intr: 3027 otx2_disable_mbox_intr(pf); 3028 err_mbox_destroy: 3029 otx2_pfaf_mbox_destroy(pf); 3030 err_free_irq_vectors: 3031 pci_free_irq_vectors(hw->pdev); 3032 3033 return err; 3034 } 3035 EXPORT_SYMBOL(otx2_init_rsrc); 3036 3037 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3038 { 3039 struct device *dev = &pdev->dev; 3040 int err, qcount, qos_txqs; 3041 struct net_device *netdev; 3042 struct otx2_nic *pf; 3043 struct otx2_hw *hw; 3044 3045 err = pcim_enable_device(pdev); 3046 if (err) { 3047 dev_err(dev, "Failed to enable PCI device\n"); 3048 return err; 3049 } 3050 3051 err = pci_request_regions(pdev, DRV_NAME); 3052 if (err) { 3053 dev_err(dev, "PCI request regions failed 0x%x\n", err); 3054 return err; 3055 } 3056 3057 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3058 if (err) { 3059 dev_err(dev, "DMA mask config failed, abort\n"); 3060 goto err_release_regions; 3061 } 3062 3063 pci_set_master(pdev); 3064 3065 /* Set number of queues */ 3066 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 3067 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 3068 3069 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount + qos_txqs, qcount); 3070 if (!netdev) { 3071 err = -ENOMEM; 3072 goto err_release_regions; 3073 } 3074 3075 pci_set_drvdata(pdev, netdev); 3076 SET_NETDEV_DEV(netdev, &pdev->dev); 3077 pf = netdev_priv(netdev); 3078 pf->netdev = netdev; 3079 pf->pdev = pdev; 3080 pf->dev = dev; 3081 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 3082 pf->flags |= OTX2_FLAG_INTF_DOWN; 3083 3084 hw = &pf->hw; 3085 hw->pdev = pdev; 3086 hw->rx_queues = qcount; 3087 hw->tx_queues = qcount; 3088 hw->non_qos_queues = qcount; 3089 hw->max_queues = qcount; 3090 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 3091 /* Use CQE of 128 byte descriptor size by default */ 3092 hw->xqe_size = 128; 3093 3094 err = otx2_init_rsrc(pdev, pf); 3095 if (err) 3096 goto err_free_netdev; 3097 3098 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 3099 if (err) 3100 goto err_detach_rsrc; 3101 3102 /* Assign default mac address */ 3103 otx2_get_mac_from_af(netdev); 3104 3105 /* Don't check for error. Proceed without ptp */ 3106 otx2_ptp_init(pf); 3107 3108 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 3109 * HW allocates buffer pointer from stack and uses it for DMA'ing 3110 * ingress packet. In some scenarios HW can free back allocated buffer 3111 * pointers to pool. This makes it impossible for SW to maintain a 3112 * parallel list where physical addresses of buffer pointers (IOVAs) 3113 * given to HW can be saved for later reference. 3114 * 3115 * So the only way to convert Rx packet's buffer address is to use 3116 * IOMMU's iova_to_phys() handler which translates the address by 3117 * walking through the translation tables. 3118 */ 3119 pf->iommu_domain = iommu_get_domain_for_dev(dev); 3120 3121 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 3122 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 3123 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 3124 NETIF_F_GSO_UDP_L4); 3125 netdev->features |= netdev->hw_features; 3126 3127 err = otx2_mcam_flow_init(pf); 3128 if (err) 3129 goto err_ptp_destroy; 3130 3131 err = cn10k_mcs_init(pf); 3132 if (err) 3133 goto err_del_mcam_entries; 3134 3135 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 3136 netdev->hw_features |= NETIF_F_NTUPLE; 3137 3138 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 3139 netdev->priv_flags |= IFF_UNICAST_FLT; 3140 3141 /* Support TSO on tag interface */ 3142 netdev->vlan_features |= netdev->features; 3143 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 3144 NETIF_F_HW_VLAN_STAG_TX; 3145 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 3146 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 3147 NETIF_F_HW_VLAN_STAG_RX; 3148 netdev->features |= netdev->hw_features; 3149 3150 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 3151 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 3152 netdev->hw_features |= NETIF_F_HW_TC; 3153 3154 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 3155 3156 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 3157 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 3158 3159 netdev->netdev_ops = &otx2_netdev_ops; 3160 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3161 3162 netdev->min_mtu = OTX2_MIN_MTU; 3163 netdev->max_mtu = otx2_get_max_mtu(pf); 3164 hw->max_mtu = netdev->max_mtu; 3165 3166 /* reset CGX/RPM MAC stats */ 3167 otx2_reset_mac_stats(pf); 3168 3169 err = cn10k_ipsec_init(netdev); 3170 if (err) 3171 goto err_mcs_free; 3172 3173 err = register_netdev(netdev); 3174 if (err) { 3175 dev_err(dev, "Failed to register netdevice\n"); 3176 goto err_ipsec_clean; 3177 } 3178 3179 err = otx2_wq_init(pf); 3180 if (err) 3181 goto err_unreg_netdev; 3182 3183 otx2_set_ethtool_ops(netdev); 3184 3185 err = otx2_init_tc(pf); 3186 if (err) 3187 goto err_mcam_flow_del; 3188 3189 err = otx2_register_dl(pf); 3190 if (err) 3191 goto err_mcam_flow_del; 3192 3193 /* Initialize SR-IOV resources */ 3194 err = otx2_sriov_vfcfg_init(pf); 3195 if (err) 3196 goto err_pf_sriov_init; 3197 3198 /* Enable link notifications */ 3199 otx2_cgx_config_linkevents(pf, true); 3200 3201 pf->af_xdp_zc_qidx = bitmap_zalloc(qcount, GFP_KERNEL); 3202 if (!pf->af_xdp_zc_qidx) { 3203 err = -ENOMEM; 3204 goto err_sriov_cleannup; 3205 } 3206 3207 #ifdef CONFIG_DCB 3208 err = otx2_dcbnl_set_ops(netdev); 3209 if (err) 3210 goto err_free_zc_bmap; 3211 #endif 3212 3213 otx2_qos_init(pf, qos_txqs); 3214 3215 return 0; 3216 3217 #ifdef CONFIG_DCB 3218 err_free_zc_bmap: 3219 bitmap_free(pf->af_xdp_zc_qidx); 3220 #endif 3221 err_sriov_cleannup: 3222 otx2_sriov_vfcfg_cleanup(pf); 3223 err_pf_sriov_init: 3224 otx2_shutdown_tc(pf); 3225 err_mcam_flow_del: 3226 otx2_mcam_flow_del(pf); 3227 err_unreg_netdev: 3228 unregister_netdev(netdev); 3229 err_ipsec_clean: 3230 cn10k_ipsec_clean(pf); 3231 err_mcs_free: 3232 cn10k_mcs_free(pf); 3233 err_del_mcam_entries: 3234 otx2_mcam_flow_del(pf); 3235 err_ptp_destroy: 3236 otx2_ptp_destroy(pf); 3237 err_detach_rsrc: 3238 if (pf->hw.lmt_info) 3239 free_percpu(pf->hw.lmt_info); 3240 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3241 qmem_free(pf->dev, pf->dync_lmt); 3242 otx2_detach_resources(&pf->mbox); 3243 otx2_disable_mbox_intr(pf); 3244 otx2_pfaf_mbox_destroy(pf); 3245 pci_free_irq_vectors(hw->pdev); 3246 err_free_netdev: 3247 pci_set_drvdata(pdev, NULL); 3248 free_netdev(netdev); 3249 err_release_regions: 3250 pci_release_regions(pdev); 3251 return err; 3252 } 3253 3254 static void otx2_vf_link_event_task(struct work_struct *work) 3255 { 3256 struct otx2_vf_config *config; 3257 struct cgx_link_info_msg *req; 3258 struct mbox_msghdr *msghdr; 3259 struct delayed_work *dwork; 3260 struct otx2_nic *pf; 3261 int vf_idx; 3262 3263 config = container_of(work, struct otx2_vf_config, 3264 link_event_work.work); 3265 vf_idx = config - config->pf->vf_configs; 3266 pf = config->pf; 3267 3268 if (config->intf_down) 3269 return; 3270 3271 mutex_lock(&pf->mbox.lock); 3272 3273 dwork = &config->link_event_work; 3274 3275 if (!otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx)) { 3276 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 3277 mutex_unlock(&pf->mbox.lock); 3278 return; 3279 } 3280 3281 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 3282 sizeof(*req), sizeof(struct msg_rsp)); 3283 if (!msghdr) { 3284 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 3285 mutex_unlock(&pf->mbox.lock); 3286 return; 3287 } 3288 3289 req = (struct cgx_link_info_msg *)msghdr; 3290 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 3291 req->hdr.sig = OTX2_MBOX_REQ_SIG; 3292 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 3293 3294 otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx); 3295 3296 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 3297 3298 mutex_unlock(&pf->mbox.lock); 3299 } 3300 3301 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 3302 { 3303 struct net_device *netdev = pci_get_drvdata(pdev); 3304 struct otx2_nic *pf = netdev_priv(netdev); 3305 int ret; 3306 3307 /* Init PF <=> VF mailbox stuff */ 3308 ret = otx2_pfvf_mbox_init(pf, numvfs); 3309 if (ret) 3310 return ret; 3311 3312 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 3313 if (ret) 3314 goto free_mbox; 3315 3316 ret = otx2_pf_flr_init(pf, numvfs); 3317 if (ret) 3318 goto free_intr; 3319 3320 ret = otx2_register_flr_me_intr(pf, numvfs); 3321 if (ret) 3322 goto free_flr; 3323 3324 ret = pci_enable_sriov(pdev, numvfs); 3325 if (ret) 3326 goto free_flr_intr; 3327 3328 return numvfs; 3329 free_flr_intr: 3330 otx2_disable_flr_me_intr(pf); 3331 free_flr: 3332 otx2_flr_wq_destroy(pf); 3333 free_intr: 3334 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3335 free_mbox: 3336 otx2_pfvf_mbox_destroy(pf); 3337 return ret; 3338 } 3339 3340 static int otx2_sriov_disable(struct pci_dev *pdev) 3341 { 3342 struct net_device *netdev = pci_get_drvdata(pdev); 3343 struct otx2_nic *pf = netdev_priv(netdev); 3344 int numvfs = pci_num_vf(pdev); 3345 3346 if (!numvfs) 3347 return 0; 3348 3349 pci_disable_sriov(pdev); 3350 3351 otx2_disable_flr_me_intr(pf); 3352 otx2_flr_wq_destroy(pf); 3353 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3354 otx2_pfvf_mbox_destroy(pf); 3355 3356 return 0; 3357 } 3358 3359 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 3360 { 3361 if (numvfs == 0) 3362 return otx2_sriov_disable(pdev); 3363 else 3364 return otx2_sriov_enable(pdev, numvfs); 3365 } 3366 3367 static void otx2_ndc_sync(struct otx2_nic *pf) 3368 { 3369 struct mbox *mbox = &pf->mbox; 3370 struct ndc_sync_op *req; 3371 3372 mutex_lock(&mbox->lock); 3373 3374 req = otx2_mbox_alloc_msg_ndc_sync_op(mbox); 3375 if (!req) { 3376 mutex_unlock(&mbox->lock); 3377 return; 3378 } 3379 3380 req->nix_lf_tx_sync = 1; 3381 req->nix_lf_rx_sync = 1; 3382 req->npa_lf_sync = 1; 3383 3384 if (!otx2_sync_mbox_msg(mbox)) 3385 dev_err(pf->dev, "NDC sync operation failed\n"); 3386 3387 mutex_unlock(&mbox->lock); 3388 } 3389 3390 static void otx2_remove(struct pci_dev *pdev) 3391 { 3392 struct net_device *netdev = pci_get_drvdata(pdev); 3393 struct otx2_nic *pf; 3394 3395 if (!netdev) 3396 return; 3397 3398 pf = netdev_priv(netdev); 3399 3400 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 3401 3402 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 3403 otx2_config_hw_tx_tstamp(pf, false); 3404 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 3405 otx2_config_hw_rx_tstamp(pf, false); 3406 3407 /* Disable 802.3x pause frames */ 3408 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 3409 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 3410 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 3411 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 3412 otx2_config_pause_frm(pf); 3413 } 3414 3415 #ifdef CONFIG_DCB 3416 /* Disable PFC config */ 3417 if (pf->pfc_en) { 3418 pf->pfc_en = 0; 3419 otx2_config_priority_flow_ctrl(pf); 3420 } 3421 #endif 3422 cancel_work_sync(&pf->reset_task); 3423 /* Disable link notifications */ 3424 otx2_cgx_config_linkevents(pf, false); 3425 3426 otx2_unregister_dl(pf); 3427 unregister_netdev(netdev); 3428 cn10k_ipsec_clean(pf); 3429 cn10k_mcs_free(pf); 3430 otx2_sriov_disable(pf->pdev); 3431 otx2_sriov_vfcfg_cleanup(pf); 3432 if (pf->otx2_wq) 3433 destroy_workqueue(pf->otx2_wq); 3434 3435 otx2_ptp_destroy(pf); 3436 otx2_mcam_flow_del(pf); 3437 otx2_shutdown_tc(pf); 3438 otx2_shutdown_qos(pf); 3439 otx2_ndc_sync(pf); 3440 otx2_detach_resources(&pf->mbox); 3441 if (pf->hw.lmt_info) 3442 free_percpu(pf->hw.lmt_info); 3443 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3444 qmem_free(pf->dev, pf->dync_lmt); 3445 otx2_disable_mbox_intr(pf); 3446 otx2_pfaf_mbox_destroy(pf); 3447 pci_free_irq_vectors(pf->pdev); 3448 pci_set_drvdata(pdev, NULL); 3449 free_netdev(netdev); 3450 3451 pci_release_regions(pdev); 3452 } 3453 3454 static struct pci_driver otx2_pf_driver = { 3455 .name = DRV_NAME, 3456 .id_table = otx2_pf_id_table, 3457 .probe = otx2_probe, 3458 .shutdown = otx2_remove, 3459 .remove = otx2_remove, 3460 .sriov_configure = otx2_sriov_configure 3461 }; 3462 3463 static int __init otx2_rvupf_init_module(void) 3464 { 3465 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3466 3467 return pci_register_driver(&otx2_pf_driver); 3468 } 3469 3470 static void __exit otx2_rvupf_cleanup_module(void) 3471 { 3472 pci_unregister_driver(&otx2_pf_driver); 3473 } 3474 3475 module_init(otx2_rvupf_init_module); 3476 module_exit(otx2_rvupf_cleanup_module); 3477