1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/pci.h> 9 #include <linux/ethtool.h> 10 #include <linux/stddef.h> 11 #include <linux/etherdevice.h> 12 #include <linux/log2.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/linkmode.h> 15 16 #include "otx2_common.h" 17 #include "otx2_ptp.h" 18 19 #define DRV_NAME "rvu-nicpf" 20 #define DRV_VF_NAME "rvu-nicvf" 21 22 struct otx2_stat { 23 char name[ETH_GSTRING_LEN]; 24 unsigned int index; 25 }; 26 27 /* HW device stats */ 28 #define OTX2_DEV_STAT(stat) { \ 29 .name = #stat, \ 30 .index = offsetof(struct otx2_dev_stats, stat) / sizeof(u64), \ 31 } 32 33 enum link_mode { 34 OTX2_MODE_SUPPORTED, 35 OTX2_MODE_ADVERTISED 36 }; 37 38 static const struct otx2_stat otx2_dev_stats[] = { 39 OTX2_DEV_STAT(rx_ucast_frames), 40 OTX2_DEV_STAT(rx_bcast_frames), 41 OTX2_DEV_STAT(rx_mcast_frames), 42 43 OTX2_DEV_STAT(tx_ucast_frames), 44 OTX2_DEV_STAT(tx_bcast_frames), 45 OTX2_DEV_STAT(tx_mcast_frames), 46 }; 47 48 /* Driver level stats */ 49 #define OTX2_DRV_STAT(stat) { \ 50 .name = #stat, \ 51 .index = offsetof(struct otx2_drv_stats, stat) / sizeof(atomic_t), \ 52 } 53 54 static const struct otx2_stat otx2_drv_stats[] = { 55 OTX2_DRV_STAT(rx_fcs_errs), 56 OTX2_DRV_STAT(rx_oversize_errs), 57 OTX2_DRV_STAT(rx_undersize_errs), 58 OTX2_DRV_STAT(rx_csum_errs), 59 OTX2_DRV_STAT(rx_len_errs), 60 OTX2_DRV_STAT(rx_other_errs), 61 }; 62 63 static const struct otx2_stat otx2_queue_stats[] = { 64 { "bytes", 0 }, 65 { "frames", 1 }, 66 }; 67 68 static const unsigned int otx2_n_dev_stats = ARRAY_SIZE(otx2_dev_stats); 69 static const unsigned int otx2_n_drv_stats = ARRAY_SIZE(otx2_drv_stats); 70 static const unsigned int otx2_n_queue_stats = ARRAY_SIZE(otx2_queue_stats); 71 72 static struct cgx_fw_data *otx2_get_fwdata(struct otx2_nic *pfvf); 73 74 static void otx2_get_drvinfo(struct net_device *netdev, 75 struct ethtool_drvinfo *info) 76 { 77 struct otx2_nic *pfvf = netdev_priv(netdev); 78 79 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 80 strscpy(info->bus_info, pci_name(pfvf->pdev), sizeof(info->bus_info)); 81 } 82 83 static void otx2_get_qset_strings(struct otx2_nic *pfvf, u8 **data, int qset) 84 { 85 int start_qidx = qset * pfvf->hw.rx_queues; 86 int qidx, stats; 87 88 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) 89 for (stats = 0; stats < otx2_n_queue_stats; stats++) 90 ethtool_sprintf(data, "rxq%d: %s", qidx + start_qidx, 91 otx2_queue_stats[stats].name); 92 93 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) 94 for (stats = 0; stats < otx2_n_queue_stats; stats++) 95 if (qidx >= pfvf->hw.non_qos_queues) 96 ethtool_sprintf(data, "txq_qos%d: %s", 97 qidx + start_qidx - 98 pfvf->hw.non_qos_queues, 99 otx2_queue_stats[stats].name); 100 else 101 ethtool_sprintf(data, "txq%d: %s", 102 qidx + start_qidx, 103 otx2_queue_stats[stats].name); 104 } 105 106 static void otx2_get_strings(struct net_device *netdev, u32 sset, u8 *data) 107 { 108 struct otx2_nic *pfvf = netdev_priv(netdev); 109 int stats; 110 111 if (sset != ETH_SS_STATS) 112 return; 113 114 for (stats = 0; stats < otx2_n_dev_stats; stats++) 115 ethtool_puts(&data, otx2_dev_stats[stats].name); 116 117 for (stats = 0; stats < otx2_n_drv_stats; stats++) 118 ethtool_puts(&data, otx2_drv_stats[stats].name); 119 120 otx2_get_qset_strings(pfvf, &data, 0); 121 122 if (!test_bit(CN10K_RPM, &pfvf->hw.cap_flag)) { 123 for (stats = 0; stats < CGX_RX_STATS_COUNT; stats++) 124 ethtool_sprintf(&data, "cgx_rxstat%d: ", stats); 125 126 for (stats = 0; stats < CGX_TX_STATS_COUNT; stats++) 127 ethtool_sprintf(&data, "cgx_txstat%d: ", stats); 128 } 129 130 ethtool_puts(&data, "reset_count"); 131 ethtool_puts(&data, "Fec Corrected Errors: "); 132 ethtool_puts(&data, "Fec Uncorrected Errors: "); 133 } 134 135 static void otx2_get_qset_stats(struct otx2_nic *pfvf, 136 struct ethtool_stats *stats, u64 **data) 137 { 138 int stat, qidx; 139 140 if (!pfvf) 141 return; 142 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 143 if (!otx2_update_rq_stats(pfvf, qidx)) { 144 for (stat = 0; stat < otx2_n_queue_stats; stat++) 145 *((*data)++) = 0; 146 continue; 147 } 148 for (stat = 0; stat < otx2_n_queue_stats; stat++) 149 *((*data)++) = ((u64 *)&pfvf->qset.rq[qidx].stats) 150 [otx2_queue_stats[stat].index]; 151 } 152 153 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 154 if (!otx2_update_sq_stats(pfvf, qidx)) { 155 for (stat = 0; stat < otx2_n_queue_stats; stat++) 156 *((*data)++) = 0; 157 continue; 158 } 159 for (stat = 0; stat < otx2_n_queue_stats; stat++) 160 *((*data)++) = ((u64 *)&pfvf->qset.sq[qidx].stats) 161 [otx2_queue_stats[stat].index]; 162 } 163 } 164 165 static int otx2_get_phy_fec_stats(struct otx2_nic *pfvf) 166 { 167 struct msg_req *req; 168 int rc = -ENOMEM; 169 170 mutex_lock(&pfvf->mbox.lock); 171 req = otx2_mbox_alloc_msg_cgx_get_phy_fec_stats(&pfvf->mbox); 172 if (!req) 173 goto end; 174 175 if (!otx2_sync_mbox_msg(&pfvf->mbox)) 176 rc = 0; 177 end: 178 mutex_unlock(&pfvf->mbox.lock); 179 return rc; 180 } 181 182 /* Get device and per queue statistics */ 183 static void otx2_get_ethtool_stats(struct net_device *netdev, 184 struct ethtool_stats *stats, u64 *data) 185 { 186 struct otx2_nic *pfvf = netdev_priv(netdev); 187 u64 fec_corr_blks, fec_uncorr_blks; 188 struct cgx_fw_data *rsp; 189 int stat; 190 191 otx2_get_dev_stats(pfvf); 192 for (stat = 0; stat < otx2_n_dev_stats; stat++) 193 *(data++) = ((u64 *)&pfvf->hw.dev_stats) 194 [otx2_dev_stats[stat].index]; 195 196 for (stat = 0; stat < otx2_n_drv_stats; stat++) 197 *(data++) = atomic_read(&((atomic_t *)&pfvf->hw.drv_stats) 198 [otx2_drv_stats[stat].index]); 199 200 otx2_get_qset_stats(pfvf, stats, &data); 201 202 if (!test_bit(CN10K_RPM, &pfvf->hw.cap_flag)) { 203 otx2_update_lmac_stats(pfvf); 204 for (stat = 0; stat < CGX_RX_STATS_COUNT; stat++) 205 *(data++) = pfvf->hw.cgx_rx_stats[stat]; 206 for (stat = 0; stat < CGX_TX_STATS_COUNT; stat++) 207 *(data++) = pfvf->hw.cgx_tx_stats[stat]; 208 } 209 210 *(data++) = pfvf->reset_count; 211 212 fec_corr_blks = pfvf->hw.cgx_fec_corr_blks; 213 fec_uncorr_blks = pfvf->hw.cgx_fec_uncorr_blks; 214 215 rsp = otx2_get_fwdata(pfvf); 216 if (!IS_ERR(rsp) && rsp->fwdata.phy.misc.has_fec_stats && 217 !otx2_get_phy_fec_stats(pfvf)) { 218 /* Fetch fwdata again because it's been recently populated with 219 * latest PHY FEC stats. 220 */ 221 rsp = otx2_get_fwdata(pfvf); 222 if (!IS_ERR(rsp)) { 223 struct fec_stats_s *p = &rsp->fwdata.phy.fec_stats; 224 225 if (pfvf->linfo.fec == OTX2_FEC_BASER) { 226 fec_corr_blks = p->brfec_corr_blks; 227 fec_uncorr_blks = p->brfec_uncorr_blks; 228 } else { 229 fec_corr_blks = p->rsfec_corr_cws; 230 fec_uncorr_blks = p->rsfec_uncorr_cws; 231 } 232 } 233 } 234 235 *(data++) = fec_corr_blks; 236 *(data++) = fec_uncorr_blks; 237 } 238 239 static int otx2_get_sset_count(struct net_device *netdev, int sset) 240 { 241 struct otx2_nic *pfvf = netdev_priv(netdev); 242 int qstats_count, mac_stats = 0; 243 244 if (sset != ETH_SS_STATS) 245 return -EINVAL; 246 247 qstats_count = otx2_n_queue_stats * 248 (pfvf->hw.rx_queues + otx2_get_total_tx_queues(pfvf)); 249 if (!test_bit(CN10K_RPM, &pfvf->hw.cap_flag)) 250 mac_stats = CGX_RX_STATS_COUNT + CGX_TX_STATS_COUNT; 251 otx2_update_lmac_fec_stats(pfvf); 252 253 return otx2_n_dev_stats + otx2_n_drv_stats + qstats_count + 254 mac_stats + OTX2_FEC_STATS_CNT + 1; 255 } 256 257 /* Get no of queues device supports and current queue count */ 258 static void otx2_get_channels(struct net_device *dev, 259 struct ethtool_channels *channel) 260 { 261 struct otx2_nic *pfvf = netdev_priv(dev); 262 263 channel->max_rx = pfvf->hw.max_queues; 264 channel->max_tx = pfvf->hw.max_queues; 265 266 channel->rx_count = pfvf->hw.rx_queues; 267 channel->tx_count = pfvf->hw.tx_queues; 268 } 269 270 /* Set no of Tx, Rx queues to be used */ 271 static int otx2_set_channels(struct net_device *dev, 272 struct ethtool_channels *channel) 273 { 274 struct otx2_nic *pfvf = netdev_priv(dev); 275 bool if_up = netif_running(dev); 276 int err, qos_txqs; 277 278 if (!channel->rx_count || !channel->tx_count) 279 return -EINVAL; 280 281 if (bitmap_weight(&pfvf->rq_bmap, pfvf->hw.rx_queues) > 1) { 282 netdev_err(dev, 283 "Receive queues are in use by TC police action\n"); 284 return -EINVAL; 285 } 286 287 if (if_up) 288 dev->netdev_ops->ndo_stop(dev); 289 290 qos_txqs = bitmap_weight(pfvf->qos.qos_sq_bmap, 291 OTX2_QOS_MAX_LEAF_NODES); 292 293 err = otx2_set_real_num_queues(dev, channel->tx_count + qos_txqs, 294 channel->rx_count); 295 if (err) 296 return err; 297 298 pfvf->hw.rx_queues = channel->rx_count; 299 pfvf->hw.tx_queues = channel->tx_count; 300 if (pfvf->xdp_prog) 301 pfvf->hw.xdp_queues = channel->rx_count; 302 303 if (if_up) 304 err = dev->netdev_ops->ndo_open(dev); 305 306 netdev_info(dev, "Setting num Tx rings to %d, Rx rings to %d success\n", 307 pfvf->hw.tx_queues, pfvf->hw.rx_queues); 308 309 return err; 310 } 311 312 static void otx2_get_pauseparam(struct net_device *netdev, 313 struct ethtool_pauseparam *pause) 314 { 315 struct otx2_nic *pfvf = netdev_priv(netdev); 316 struct cgx_pause_frm_cfg *req, *rsp; 317 318 if (is_otx2_lbkvf(pfvf->pdev)) 319 return; 320 321 mutex_lock(&pfvf->mbox.lock); 322 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 323 if (!req) { 324 mutex_unlock(&pfvf->mbox.lock); 325 return; 326 } 327 328 if (!otx2_sync_mbox_msg(&pfvf->mbox)) { 329 rsp = (struct cgx_pause_frm_cfg *) 330 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 331 if (IS_ERR(rsp)) { 332 mutex_unlock(&pfvf->mbox.lock); 333 return; 334 } 335 336 pause->rx_pause = rsp->rx_pause; 337 pause->tx_pause = rsp->tx_pause; 338 } 339 mutex_unlock(&pfvf->mbox.lock); 340 } 341 342 static int otx2_set_pauseparam(struct net_device *netdev, 343 struct ethtool_pauseparam *pause) 344 { 345 struct otx2_nic *pfvf = netdev_priv(netdev); 346 347 if (pause->autoneg) 348 return -EOPNOTSUPP; 349 350 if (is_otx2_lbkvf(pfvf->pdev)) 351 return -EOPNOTSUPP; 352 353 if (pause->rx_pause) 354 pfvf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 355 else 356 pfvf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 357 358 if (pause->tx_pause) 359 pfvf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 360 else 361 pfvf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 362 363 return otx2_config_pause_frm(pfvf); 364 } 365 366 static void otx2_get_ringparam(struct net_device *netdev, 367 struct ethtool_ringparam *ring, 368 struct kernel_ethtool_ringparam *kernel_ring, 369 struct netlink_ext_ack *extack) 370 { 371 struct otx2_nic *pfvf = netdev_priv(netdev); 372 struct otx2_qset *qs = &pfvf->qset; 373 374 ring->rx_max_pending = Q_COUNT(Q_SIZE_MAX); 375 ring->rx_pending = qs->rqe_cnt ? qs->rqe_cnt : Q_COUNT(Q_SIZE_256); 376 ring->tx_max_pending = Q_COUNT(Q_SIZE_MAX); 377 ring->tx_pending = qs->sqe_cnt ? qs->sqe_cnt : Q_COUNT(Q_SIZE_4K); 378 kernel_ring->rx_buf_len = pfvf->hw.rbuf_len; 379 kernel_ring->cqe_size = pfvf->hw.xqe_size; 380 } 381 382 static int otx2_set_ringparam(struct net_device *netdev, 383 struct ethtool_ringparam *ring, 384 struct kernel_ethtool_ringparam *kernel_ring, 385 struct netlink_ext_ack *extack) 386 { 387 struct otx2_nic *pfvf = netdev_priv(netdev); 388 u32 rx_buf_len = kernel_ring->rx_buf_len; 389 u32 old_rx_buf_len = pfvf->hw.rbuf_len; 390 u32 xqe_size = kernel_ring->cqe_size; 391 bool if_up = netif_running(netdev); 392 struct otx2_qset *qs = &pfvf->qset; 393 u32 rx_count, tx_count; 394 395 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 396 return -EINVAL; 397 398 /* Hardware supports max size of 32k for a receive buffer 399 * and 1536 is typical ethernet frame size. 400 */ 401 if (rx_buf_len && (rx_buf_len < 1536 || rx_buf_len > 32768)) { 402 netdev_err(netdev, 403 "Receive buffer range is 1536 - 32768"); 404 return -EINVAL; 405 } 406 407 if (xqe_size != 128 && xqe_size != 512) { 408 netdev_err(netdev, 409 "Completion event size must be 128 or 512"); 410 return -EINVAL; 411 } 412 413 /* Permitted lengths are 16 64 256 1K 4K 16K 64K 256K 1M */ 414 rx_count = ring->rx_pending; 415 /* On some silicon variants a skid or reserved CQEs are 416 * needed to avoid CQ overflow. 417 */ 418 if (rx_count < pfvf->hw.rq_skid) 419 rx_count = pfvf->hw.rq_skid; 420 rx_count = Q_COUNT(Q_SIZE(rx_count, 3)); 421 422 /* Due pipelining impact minimum 2000 unused SQ CQE's 423 * need to be maintained to avoid CQ overflow, hence the 424 * minimum 4K size. 425 */ 426 tx_count = clamp_t(u32, ring->tx_pending, 427 Q_COUNT(Q_SIZE_4K), Q_COUNT(Q_SIZE_MAX)); 428 tx_count = Q_COUNT(Q_SIZE(tx_count, 3)); 429 430 if (tx_count == qs->sqe_cnt && rx_count == qs->rqe_cnt && 431 rx_buf_len == old_rx_buf_len && xqe_size == pfvf->hw.xqe_size) 432 return 0; 433 434 if (if_up) 435 netdev->netdev_ops->ndo_stop(netdev); 436 437 /* Assigned to the nearest possible exponent. */ 438 qs->sqe_cnt = tx_count; 439 qs->rqe_cnt = rx_count; 440 441 pfvf->hw.rbuf_len = rx_buf_len; 442 pfvf->hw.xqe_size = xqe_size; 443 444 if (if_up) 445 return netdev->netdev_ops->ndo_open(netdev); 446 447 return 0; 448 } 449 450 static int otx2_get_coalesce(struct net_device *netdev, 451 struct ethtool_coalesce *cmd, 452 struct kernel_ethtool_coalesce *kernel_coal, 453 struct netlink_ext_ack *extack) 454 { 455 struct otx2_nic *pfvf = netdev_priv(netdev); 456 struct otx2_hw *hw = &pfvf->hw; 457 458 cmd->rx_coalesce_usecs = hw->cq_time_wait; 459 cmd->rx_max_coalesced_frames = hw->cq_ecount_wait; 460 cmd->tx_coalesce_usecs = hw->cq_time_wait; 461 cmd->tx_max_coalesced_frames = hw->cq_ecount_wait; 462 if ((pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED) == 463 OTX2_FLAG_ADPTV_INT_COAL_ENABLED) { 464 cmd->use_adaptive_rx_coalesce = 1; 465 cmd->use_adaptive_tx_coalesce = 1; 466 } else { 467 cmd->use_adaptive_rx_coalesce = 0; 468 cmd->use_adaptive_tx_coalesce = 0; 469 } 470 471 return 0; 472 } 473 474 static int otx2_set_coalesce(struct net_device *netdev, 475 struct ethtool_coalesce *ec, 476 struct kernel_ethtool_coalesce *kernel_coal, 477 struct netlink_ext_ack *extack) 478 { 479 struct otx2_nic *pfvf = netdev_priv(netdev); 480 struct otx2_hw *hw = &pfvf->hw; 481 u8 priv_coalesce_status; 482 int qidx; 483 484 if (!ec->rx_max_coalesced_frames || !ec->tx_max_coalesced_frames) 485 return 0; 486 487 if (ec->use_adaptive_rx_coalesce != ec->use_adaptive_tx_coalesce) { 488 netdev_err(netdev, 489 "adaptive-rx should be same as adaptive-tx"); 490 return -EINVAL; 491 } 492 493 /* Check and update coalesce status */ 494 if ((pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED) == 495 OTX2_FLAG_ADPTV_INT_COAL_ENABLED) { 496 priv_coalesce_status = 1; 497 if (!ec->use_adaptive_rx_coalesce) 498 pfvf->flags &= ~OTX2_FLAG_ADPTV_INT_COAL_ENABLED; 499 } else { 500 priv_coalesce_status = 0; 501 if (ec->use_adaptive_rx_coalesce) 502 pfvf->flags |= OTX2_FLAG_ADPTV_INT_COAL_ENABLED; 503 } 504 505 /* 'cq_time_wait' is 8bit and is in multiple of 100ns, 506 * so clamp the user given value to the range of 1 to 25usec. 507 */ 508 ec->rx_coalesce_usecs = clamp_t(u32, ec->rx_coalesce_usecs, 509 1, CQ_TIMER_THRESH_MAX); 510 ec->tx_coalesce_usecs = clamp_t(u32, ec->tx_coalesce_usecs, 511 1, CQ_TIMER_THRESH_MAX); 512 513 /* Rx and Tx are mapped to same CQ, check which one 514 * is changed, if both then choose the min. 515 */ 516 if (hw->cq_time_wait == ec->rx_coalesce_usecs) 517 hw->cq_time_wait = ec->tx_coalesce_usecs; 518 else if (hw->cq_time_wait == ec->tx_coalesce_usecs) 519 hw->cq_time_wait = ec->rx_coalesce_usecs; 520 else 521 hw->cq_time_wait = min_t(u8, ec->rx_coalesce_usecs, 522 ec->tx_coalesce_usecs); 523 524 /* Max ecount_wait supported is 16bit, 525 * so clamp the user given value to the range of 1 to 64k. 526 */ 527 ec->rx_max_coalesced_frames = clamp_t(u32, ec->rx_max_coalesced_frames, 528 1, NAPI_POLL_WEIGHT); 529 ec->tx_max_coalesced_frames = clamp_t(u32, ec->tx_max_coalesced_frames, 530 1, NAPI_POLL_WEIGHT); 531 532 /* Rx and Tx are mapped to same CQ, check which one 533 * is changed, if both then choose the min. 534 */ 535 if (hw->cq_ecount_wait == ec->rx_max_coalesced_frames) 536 hw->cq_ecount_wait = ec->tx_max_coalesced_frames; 537 else if (hw->cq_ecount_wait == ec->tx_max_coalesced_frames) 538 hw->cq_ecount_wait = ec->rx_max_coalesced_frames; 539 else 540 hw->cq_ecount_wait = min_t(u16, ec->rx_max_coalesced_frames, 541 ec->tx_max_coalesced_frames); 542 543 /* Reset 'cq_time_wait' and 'cq_ecount_wait' to 544 * default values if coalesce status changed from 545 * 'on' to 'off'. 546 */ 547 if (priv_coalesce_status && 548 ((pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED) != 549 OTX2_FLAG_ADPTV_INT_COAL_ENABLED)) { 550 hw->cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 551 hw->cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 552 } 553 554 if (netif_running(netdev)) { 555 for (qidx = 0; qidx < pfvf->hw.cint_cnt; qidx++) 556 otx2_config_irq_coalescing(pfvf, qidx); 557 } 558 559 return 0; 560 } 561 562 static int otx2_get_rss_hash_opts(struct otx2_nic *pfvf, 563 struct ethtool_rxnfc *nfc) 564 { 565 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 566 567 if (!(rss->flowkey_cfg & 568 (NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6))) 569 return 0; 570 571 /* Mimimum is IPv4 and IPv6, SIP/DIP */ 572 nfc->data = RXH_IP_SRC | RXH_IP_DST; 573 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_VLAN) 574 nfc->data |= RXH_VLAN; 575 576 switch (nfc->flow_type) { 577 case TCP_V4_FLOW: 578 case TCP_V6_FLOW: 579 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_TCP) 580 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 581 break; 582 case UDP_V4_FLOW: 583 case UDP_V6_FLOW: 584 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_UDP) 585 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 586 break; 587 case SCTP_V4_FLOW: 588 case SCTP_V6_FLOW: 589 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_SCTP) 590 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 591 break; 592 case AH_ESP_V4_FLOW: 593 case AH_ESP_V6_FLOW: 594 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_ESP) 595 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 596 break; 597 case AH_V4_FLOW: 598 case ESP_V4_FLOW: 599 case IPV4_FLOW: 600 break; 601 case AH_V6_FLOW: 602 case ESP_V6_FLOW: 603 case IPV6_FLOW: 604 break; 605 default: 606 return -EINVAL; 607 } 608 609 return 0; 610 } 611 612 static int otx2_set_rss_hash_opts(struct otx2_nic *pfvf, 613 struct ethtool_rxnfc *nfc) 614 { 615 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 616 u32 rxh_l4 = RXH_L4_B_0_1 | RXH_L4_B_2_3; 617 u32 rss_cfg = rss->flowkey_cfg; 618 619 if (!rss->enable) { 620 netdev_err(pfvf->netdev, 621 "RSS is disabled, cannot change settings\n"); 622 return -EIO; 623 } 624 625 /* Mimimum is IPv4 and IPv6, SIP/DIP */ 626 if (!(nfc->data & RXH_IP_SRC) || !(nfc->data & RXH_IP_DST)) 627 return -EINVAL; 628 629 if (nfc->data & RXH_VLAN) 630 rss_cfg |= NIX_FLOW_KEY_TYPE_VLAN; 631 else 632 rss_cfg &= ~NIX_FLOW_KEY_TYPE_VLAN; 633 634 switch (nfc->flow_type) { 635 case TCP_V4_FLOW: 636 case TCP_V6_FLOW: 637 /* Different config for v4 and v6 is not supported. 638 * Both of them have to be either 4-tuple or 2-tuple. 639 */ 640 switch (nfc->data & rxh_l4) { 641 case 0: 642 rss_cfg &= ~NIX_FLOW_KEY_TYPE_TCP; 643 break; 644 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 645 rss_cfg |= NIX_FLOW_KEY_TYPE_TCP; 646 break; 647 default: 648 return -EINVAL; 649 } 650 break; 651 case UDP_V4_FLOW: 652 case UDP_V6_FLOW: 653 switch (nfc->data & rxh_l4) { 654 case 0: 655 rss_cfg &= ~NIX_FLOW_KEY_TYPE_UDP; 656 break; 657 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 658 rss_cfg |= NIX_FLOW_KEY_TYPE_UDP; 659 break; 660 default: 661 return -EINVAL; 662 } 663 break; 664 case SCTP_V4_FLOW: 665 case SCTP_V6_FLOW: 666 switch (nfc->data & rxh_l4) { 667 case 0: 668 rss_cfg &= ~NIX_FLOW_KEY_TYPE_SCTP; 669 break; 670 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 671 rss_cfg |= NIX_FLOW_KEY_TYPE_SCTP; 672 break; 673 default: 674 return -EINVAL; 675 } 676 break; 677 case AH_ESP_V4_FLOW: 678 case AH_ESP_V6_FLOW: 679 switch (nfc->data & rxh_l4) { 680 case 0: 681 rss_cfg &= ~(NIX_FLOW_KEY_TYPE_ESP | 682 NIX_FLOW_KEY_TYPE_AH); 683 rss_cfg |= NIX_FLOW_KEY_TYPE_VLAN | 684 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 685 break; 686 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 687 /* If VLAN hashing is also requested for ESP then do not 688 * allow because of hardware 40 bytes flow key limit. 689 */ 690 if (rss_cfg & NIX_FLOW_KEY_TYPE_VLAN) { 691 netdev_err(pfvf->netdev, 692 "RSS hash of ESP or AH with VLAN is not supported\n"); 693 return -EOPNOTSUPP; 694 } 695 696 rss_cfg |= NIX_FLOW_KEY_TYPE_ESP | NIX_FLOW_KEY_TYPE_AH; 697 /* Disable IPv4 proto hashing since IPv6 SA+DA(32 bytes) 698 * and ESP SPI+sequence(8 bytes) uses hardware maximum 699 * limit of 40 byte flow key. 700 */ 701 rss_cfg &= ~NIX_FLOW_KEY_TYPE_IPV4_PROTO; 702 break; 703 default: 704 return -EINVAL; 705 } 706 break; 707 case IPV4_FLOW: 708 case IPV6_FLOW: 709 rss_cfg = NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6; 710 break; 711 default: 712 return -EINVAL; 713 } 714 715 rss->flowkey_cfg = rss_cfg; 716 otx2_set_flowkey_cfg(pfvf); 717 return 0; 718 } 719 720 static int otx2_get_rxnfc(struct net_device *dev, 721 struct ethtool_rxnfc *nfc, u32 *rules) 722 { 723 bool ntuple = !!(dev->features & NETIF_F_NTUPLE); 724 struct otx2_nic *pfvf = netdev_priv(dev); 725 int ret = -EOPNOTSUPP; 726 727 switch (nfc->cmd) { 728 case ETHTOOL_GRXRINGS: 729 nfc->data = pfvf->hw.rx_queues; 730 ret = 0; 731 break; 732 case ETHTOOL_GRXCLSRLCNT: 733 if (netif_running(dev) && ntuple) { 734 nfc->rule_cnt = pfvf->flow_cfg->nr_flows; 735 ret = 0; 736 } 737 break; 738 case ETHTOOL_GRXCLSRULE: 739 if (netif_running(dev) && ntuple) 740 ret = otx2_get_flow(pfvf, nfc, nfc->fs.location); 741 break; 742 case ETHTOOL_GRXCLSRLALL: 743 if (netif_running(dev) && ntuple) 744 ret = otx2_get_all_flows(pfvf, nfc, rules); 745 break; 746 case ETHTOOL_GRXFH: 747 return otx2_get_rss_hash_opts(pfvf, nfc); 748 default: 749 break; 750 } 751 return ret; 752 } 753 754 static int otx2_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *nfc) 755 { 756 bool ntuple = !!(dev->features & NETIF_F_NTUPLE); 757 struct otx2_nic *pfvf = netdev_priv(dev); 758 int ret = -EOPNOTSUPP; 759 760 pfvf->flow_cfg->ntuple = ntuple; 761 switch (nfc->cmd) { 762 case ETHTOOL_SRXFH: 763 ret = otx2_set_rss_hash_opts(pfvf, nfc); 764 break; 765 case ETHTOOL_SRXCLSRLINS: 766 if (netif_running(dev) && ntuple) 767 ret = otx2_add_flow(pfvf, nfc); 768 break; 769 case ETHTOOL_SRXCLSRLDEL: 770 if (netif_running(dev) && ntuple) 771 ret = otx2_remove_flow(pfvf, nfc->fs.location); 772 break; 773 default: 774 break; 775 } 776 777 return ret; 778 } 779 780 static u32 otx2_get_rxfh_key_size(struct net_device *netdev) 781 { 782 struct otx2_nic *pfvf = netdev_priv(netdev); 783 struct otx2_rss_info *rss; 784 785 rss = &pfvf->hw.rss_info; 786 787 return sizeof(rss->key); 788 } 789 790 static u32 otx2_get_rxfh_indir_size(struct net_device *dev) 791 { 792 return MAX_RSS_INDIR_TBL_SIZE; 793 } 794 795 static int otx2_rss_ctx_delete(struct otx2_nic *pfvf, int ctx_id) 796 { 797 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 798 799 otx2_rss_ctx_flow_del(pfvf, ctx_id); 800 kfree(rss->rss_ctx[ctx_id]); 801 rss->rss_ctx[ctx_id] = NULL; 802 803 return 0; 804 } 805 806 static int otx2_rss_ctx_create(struct otx2_nic *pfvf, 807 u32 *rss_context) 808 { 809 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 810 u8 ctx; 811 812 for (ctx = 0; ctx < MAX_RSS_GROUPS; ctx++) { 813 if (!rss->rss_ctx[ctx]) 814 break; 815 } 816 if (ctx == MAX_RSS_GROUPS) 817 return -EINVAL; 818 819 rss->rss_ctx[ctx] = kzalloc(sizeof(*rss->rss_ctx[ctx]), GFP_KERNEL); 820 if (!rss->rss_ctx[ctx]) 821 return -ENOMEM; 822 *rss_context = ctx; 823 824 return 0; 825 } 826 827 /* Configure RSS table and hash key */ 828 static int otx2_set_rxfh(struct net_device *dev, 829 struct ethtool_rxfh_param *rxfh, 830 struct netlink_ext_ack *extack) 831 { 832 u32 rss_context = DEFAULT_RSS_CONTEXT_GROUP; 833 struct otx2_nic *pfvf = netdev_priv(dev); 834 struct otx2_rss_ctx *rss_ctx; 835 struct otx2_rss_info *rss; 836 int ret, idx; 837 838 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 839 rxfh->hfunc != ETH_RSS_HASH_TOP) 840 return -EOPNOTSUPP; 841 842 if (rxfh->rss_context) 843 rss_context = rxfh->rss_context; 844 845 if (rss_context != ETH_RXFH_CONTEXT_ALLOC && 846 rss_context >= MAX_RSS_GROUPS) 847 return -EINVAL; 848 849 rss = &pfvf->hw.rss_info; 850 851 if (!rss->enable) { 852 netdev_err(dev, "RSS is disabled, cannot change settings\n"); 853 return -EIO; 854 } 855 856 if (rxfh->key) { 857 memcpy(rss->key, rxfh->key, sizeof(rss->key)); 858 otx2_set_rss_key(pfvf); 859 } 860 if (rxfh->rss_delete) 861 return otx2_rss_ctx_delete(pfvf, rss_context); 862 863 if (rss_context == ETH_RXFH_CONTEXT_ALLOC) { 864 ret = otx2_rss_ctx_create(pfvf, &rss_context); 865 rxfh->rss_context = rss_context; 866 if (ret) 867 return ret; 868 } 869 if (rxfh->indir) { 870 rss_ctx = rss->rss_ctx[rss_context]; 871 for (idx = 0; idx < rss->rss_size; idx++) 872 rss_ctx->ind_tbl[idx] = rxfh->indir[idx]; 873 } 874 otx2_set_rss_table(pfvf, rss_context); 875 876 return 0; 877 } 878 879 /* Get RSS configuration */ 880 static int otx2_get_rxfh(struct net_device *dev, 881 struct ethtool_rxfh_param *rxfh) 882 { 883 u32 rss_context = DEFAULT_RSS_CONTEXT_GROUP; 884 struct otx2_nic *pfvf = netdev_priv(dev); 885 struct otx2_rss_ctx *rss_ctx; 886 struct otx2_rss_info *rss; 887 u32 *indir = rxfh->indir; 888 int idx, rx_queues; 889 890 rss = &pfvf->hw.rss_info; 891 892 rxfh->hfunc = ETH_RSS_HASH_TOP; 893 if (rxfh->rss_context) 894 rss_context = rxfh->rss_context; 895 896 if (!indir) 897 return 0; 898 899 if (!rss->enable && rss_context == DEFAULT_RSS_CONTEXT_GROUP) { 900 rx_queues = pfvf->hw.rx_queues; 901 for (idx = 0; idx < MAX_RSS_INDIR_TBL_SIZE; idx++) 902 indir[idx] = ethtool_rxfh_indir_default(idx, rx_queues); 903 return 0; 904 } 905 if (rss_context >= MAX_RSS_GROUPS) 906 return -ENOENT; 907 908 rss_ctx = rss->rss_ctx[rss_context]; 909 if (!rss_ctx) 910 return -ENOENT; 911 912 if (indir) { 913 for (idx = 0; idx < rss->rss_size; idx++) 914 indir[idx] = rss_ctx->ind_tbl[idx]; 915 } 916 if (rxfh->key) 917 memcpy(rxfh->key, rss->key, sizeof(rss->key)); 918 919 return 0; 920 } 921 922 static u32 otx2_get_msglevel(struct net_device *netdev) 923 { 924 struct otx2_nic *pfvf = netdev_priv(netdev); 925 926 return pfvf->msg_enable; 927 } 928 929 static void otx2_set_msglevel(struct net_device *netdev, u32 val) 930 { 931 struct otx2_nic *pfvf = netdev_priv(netdev); 932 933 pfvf->msg_enable = val; 934 } 935 936 static u32 otx2_get_link(struct net_device *netdev) 937 { 938 struct otx2_nic *pfvf = netdev_priv(netdev); 939 940 /* LBK link is internal and always UP */ 941 if (is_otx2_lbkvf(pfvf->pdev)) 942 return 1; 943 return pfvf->linfo.link_up; 944 } 945 946 static int otx2_get_ts_info(struct net_device *netdev, 947 struct kernel_ethtool_ts_info *info) 948 { 949 struct otx2_nic *pfvf = netdev_priv(netdev); 950 951 if (!pfvf->ptp) 952 return ethtool_op_get_ts_info(netdev, info); 953 954 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 955 SOF_TIMESTAMPING_TX_HARDWARE | 956 SOF_TIMESTAMPING_RX_HARDWARE | 957 SOF_TIMESTAMPING_RAW_HARDWARE; 958 959 info->phc_index = otx2_ptp_clock_index(pfvf); 960 961 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 962 if (test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 963 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_SYNC); 964 965 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 966 BIT(HWTSTAMP_FILTER_ALL); 967 968 return 0; 969 } 970 971 static struct cgx_fw_data *otx2_get_fwdata(struct otx2_nic *pfvf) 972 { 973 struct cgx_fw_data *rsp = NULL; 974 struct msg_req *req; 975 int err = 0; 976 977 mutex_lock(&pfvf->mbox.lock); 978 req = otx2_mbox_alloc_msg_cgx_get_aux_link_info(&pfvf->mbox); 979 if (!req) { 980 mutex_unlock(&pfvf->mbox.lock); 981 return ERR_PTR(-ENOMEM); 982 } 983 984 err = otx2_sync_mbox_msg(&pfvf->mbox); 985 if (!err) { 986 rsp = (struct cgx_fw_data *) 987 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 988 } else { 989 rsp = ERR_PTR(err); 990 } 991 992 mutex_unlock(&pfvf->mbox.lock); 993 return rsp; 994 } 995 996 static int otx2_get_fecparam(struct net_device *netdev, 997 struct ethtool_fecparam *fecparam) 998 { 999 struct otx2_nic *pfvf = netdev_priv(netdev); 1000 struct cgx_fw_data *rsp; 1001 const int fec[] = { 1002 ETHTOOL_FEC_OFF, 1003 ETHTOOL_FEC_BASER, 1004 ETHTOOL_FEC_RS, 1005 ETHTOOL_FEC_BASER | ETHTOOL_FEC_RS}; 1006 #define FEC_MAX_INDEX 4 1007 if (pfvf->linfo.fec < FEC_MAX_INDEX) 1008 fecparam->active_fec = fec[pfvf->linfo.fec]; 1009 1010 rsp = otx2_get_fwdata(pfvf); 1011 if (IS_ERR(rsp)) 1012 return PTR_ERR(rsp); 1013 1014 if (rsp->fwdata.supported_fec < FEC_MAX_INDEX) { 1015 if (!rsp->fwdata.supported_fec) 1016 fecparam->fec = ETHTOOL_FEC_NONE; 1017 else 1018 fecparam->fec = fec[rsp->fwdata.supported_fec]; 1019 } 1020 return 0; 1021 } 1022 1023 static int otx2_set_fecparam(struct net_device *netdev, 1024 struct ethtool_fecparam *fecparam) 1025 { 1026 struct otx2_nic *pfvf = netdev_priv(netdev); 1027 struct mbox *mbox = &pfvf->mbox; 1028 struct fec_mode *req, *rsp; 1029 int err = 0, fec = 0; 1030 1031 switch (fecparam->fec) { 1032 /* Firmware does not support AUTO mode consider it as FEC_OFF */ 1033 case ETHTOOL_FEC_OFF: 1034 case ETHTOOL_FEC_AUTO: 1035 fec = OTX2_FEC_OFF; 1036 break; 1037 case ETHTOOL_FEC_RS: 1038 fec = OTX2_FEC_RS; 1039 break; 1040 case ETHTOOL_FEC_BASER: 1041 fec = OTX2_FEC_BASER; 1042 break; 1043 default: 1044 netdev_warn(pfvf->netdev, "Unsupported FEC mode: %d", 1045 fecparam->fec); 1046 return -EINVAL; 1047 } 1048 1049 if (fec == pfvf->linfo.fec) 1050 return 0; 1051 1052 mutex_lock(&mbox->lock); 1053 req = otx2_mbox_alloc_msg_cgx_set_fec_param(&pfvf->mbox); 1054 if (!req) { 1055 err = -ENOMEM; 1056 goto end; 1057 } 1058 req->fec = fec; 1059 err = otx2_sync_mbox_msg(&pfvf->mbox); 1060 if (err) 1061 goto end; 1062 1063 rsp = (struct fec_mode *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 1064 0, &req->hdr); 1065 if (IS_ERR(rsp)) { 1066 err = PTR_ERR(rsp); 1067 goto end; 1068 } 1069 1070 if (rsp->fec >= 0) 1071 pfvf->linfo.fec = rsp->fec; 1072 else 1073 err = rsp->fec; 1074 end: 1075 mutex_unlock(&mbox->lock); 1076 return err; 1077 } 1078 1079 static void otx2_get_fec_info(u64 index, int req_mode, 1080 struct ethtool_link_ksettings *link_ksettings) 1081 { 1082 __ETHTOOL_DECLARE_LINK_MODE_MASK(otx2_fec_modes) = { 0, }; 1083 1084 switch (index) { 1085 case OTX2_FEC_NONE: 1086 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1087 otx2_fec_modes); 1088 break; 1089 case OTX2_FEC_BASER: 1090 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1091 otx2_fec_modes); 1092 break; 1093 case OTX2_FEC_RS: 1094 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1095 otx2_fec_modes); 1096 break; 1097 case OTX2_FEC_BASER | OTX2_FEC_RS: 1098 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1099 otx2_fec_modes); 1100 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1101 otx2_fec_modes); 1102 break; 1103 } 1104 1105 /* Add fec modes to existing modes */ 1106 if (req_mode == OTX2_MODE_ADVERTISED) 1107 linkmode_or(link_ksettings->link_modes.advertising, 1108 link_ksettings->link_modes.advertising, 1109 otx2_fec_modes); 1110 else 1111 linkmode_or(link_ksettings->link_modes.supported, 1112 link_ksettings->link_modes.supported, 1113 otx2_fec_modes); 1114 } 1115 1116 static void otx2_get_link_mode_info(u64 link_mode_bmap, 1117 bool req_mode, 1118 struct ethtool_link_ksettings 1119 *link_ksettings) 1120 { 1121 __ETHTOOL_DECLARE_LINK_MODE_MASK(otx2_link_modes) = { 0, }; 1122 const int otx2_sgmii_features[6] = { 1123 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 1124 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 1125 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1126 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1127 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1128 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1129 }; 1130 /* CGX link modes to Ethtool link mode mapping */ 1131 const int cgx_link_mode[27] = { 1132 0, /* SGMII Mode */ 1133 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1134 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1135 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1136 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1137 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1138 0, 1139 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1140 0, 1141 0, 1142 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1143 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1144 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1145 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1146 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1147 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1148 0, 1149 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 1150 0, 1151 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1152 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 1153 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 1154 0, 1155 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1156 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1157 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1158 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT 1159 }; 1160 u8 bit; 1161 1162 for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, 27) { 1163 /* SGMII mode is set */ 1164 if (bit == 0) 1165 linkmode_set_bit_array(otx2_sgmii_features, 1166 ARRAY_SIZE(otx2_sgmii_features), 1167 otx2_link_modes); 1168 else 1169 linkmode_set_bit(cgx_link_mode[bit], otx2_link_modes); 1170 } 1171 1172 if (req_mode == OTX2_MODE_ADVERTISED) 1173 linkmode_copy(link_ksettings->link_modes.advertising, 1174 otx2_link_modes); 1175 else 1176 linkmode_copy(link_ksettings->link_modes.supported, 1177 otx2_link_modes); 1178 } 1179 1180 static int otx2_get_link_ksettings(struct net_device *netdev, 1181 struct ethtool_link_ksettings *cmd) 1182 { 1183 struct otx2_nic *pfvf = netdev_priv(netdev); 1184 struct cgx_fw_data *rsp = NULL; 1185 1186 cmd->base.duplex = pfvf->linfo.full_duplex; 1187 cmd->base.speed = pfvf->linfo.speed; 1188 cmd->base.autoneg = pfvf->linfo.an; 1189 1190 rsp = otx2_get_fwdata(pfvf); 1191 if (IS_ERR(rsp)) 1192 return PTR_ERR(rsp); 1193 1194 if (rsp->fwdata.supported_an) 1195 ethtool_link_ksettings_add_link_mode(cmd, 1196 supported, 1197 Autoneg); 1198 1199 otx2_get_link_mode_info(rsp->fwdata.advertised_link_modes, 1200 OTX2_MODE_ADVERTISED, cmd); 1201 otx2_get_fec_info(rsp->fwdata.advertised_fec, 1202 OTX2_MODE_ADVERTISED, cmd); 1203 otx2_get_link_mode_info(rsp->fwdata.supported_link_modes, 1204 OTX2_MODE_SUPPORTED, cmd); 1205 otx2_get_fec_info(rsp->fwdata.supported_fec, 1206 OTX2_MODE_SUPPORTED, cmd); 1207 return 0; 1208 } 1209 1210 static void otx2_get_advertised_mode(const struct ethtool_link_ksettings *cmd, 1211 u64 *mode) 1212 { 1213 u32 bit_pos; 1214 1215 /* Firmware does not support requesting multiple advertised modes 1216 * return first set bit 1217 */ 1218 bit_pos = find_first_bit(cmd->link_modes.advertising, 1219 __ETHTOOL_LINK_MODE_MASK_NBITS); 1220 if (bit_pos != __ETHTOOL_LINK_MODE_MASK_NBITS) 1221 *mode = bit_pos; 1222 } 1223 1224 static int otx2_set_link_ksettings(struct net_device *netdev, 1225 const struct ethtool_link_ksettings *cmd) 1226 { 1227 struct otx2_nic *pf = netdev_priv(netdev); 1228 struct ethtool_link_ksettings cur_ks; 1229 struct cgx_set_link_mode_req *req; 1230 struct mbox *mbox = &pf->mbox; 1231 int err = 0; 1232 1233 memset(&cur_ks, 0, sizeof(struct ethtool_link_ksettings)); 1234 1235 if (!ethtool_validate_speed(cmd->base.speed) || 1236 !ethtool_validate_duplex(cmd->base.duplex)) 1237 return -EINVAL; 1238 1239 if (cmd->base.autoneg != AUTONEG_ENABLE && 1240 cmd->base.autoneg != AUTONEG_DISABLE) 1241 return -EINVAL; 1242 1243 otx2_get_link_ksettings(netdev, &cur_ks); 1244 1245 /* Check requested modes against supported modes by hardware */ 1246 if (!linkmode_subset(cmd->link_modes.advertising, 1247 cur_ks.link_modes.supported)) 1248 return -EINVAL; 1249 1250 mutex_lock(&mbox->lock); 1251 req = otx2_mbox_alloc_msg_cgx_set_link_mode(&pf->mbox); 1252 if (!req) { 1253 err = -ENOMEM; 1254 goto end; 1255 } 1256 1257 req->args.speed = cmd->base.speed; 1258 /* firmware expects 1 for half duplex and 0 for full duplex 1259 * hence inverting 1260 */ 1261 req->args.duplex = cmd->base.duplex ^ 0x1; 1262 req->args.an = cmd->base.autoneg; 1263 otx2_get_advertised_mode(cmd, &req->args.mode); 1264 1265 err = otx2_sync_mbox_msg(&pf->mbox); 1266 end: 1267 mutex_unlock(&mbox->lock); 1268 return err; 1269 } 1270 1271 static void otx2_get_fec_stats(struct net_device *netdev, 1272 struct ethtool_fec_stats *fec_stats) 1273 { 1274 struct otx2_nic *pfvf = netdev_priv(netdev); 1275 struct cgx_fw_data *rsp; 1276 1277 otx2_update_lmac_fec_stats(pfvf); 1278 1279 /* Report MAC FEC stats */ 1280 fec_stats->corrected_blocks.total = pfvf->hw.cgx_fec_corr_blks; 1281 fec_stats->uncorrectable_blocks.total = pfvf->hw.cgx_fec_uncorr_blks; 1282 1283 rsp = otx2_get_fwdata(pfvf); 1284 if (!IS_ERR(rsp) && rsp->fwdata.phy.misc.has_fec_stats && 1285 !otx2_get_phy_fec_stats(pfvf)) { 1286 /* Fetch fwdata again because it's been recently populated with 1287 * latest PHY FEC stats. 1288 */ 1289 rsp = otx2_get_fwdata(pfvf); 1290 if (!IS_ERR(rsp)) { 1291 struct fec_stats_s *p = &rsp->fwdata.phy.fec_stats; 1292 1293 if (pfvf->linfo.fec == OTX2_FEC_BASER) { 1294 fec_stats->corrected_blocks.total = p->brfec_corr_blks; 1295 fec_stats->uncorrectable_blocks.total = p->brfec_uncorr_blks; 1296 } else { 1297 fec_stats->corrected_blocks.total = p->rsfec_corr_cws; 1298 fec_stats->uncorrectable_blocks.total = p->rsfec_uncorr_cws; 1299 } 1300 } 1301 } 1302 } 1303 1304 static const struct ethtool_ops otx2_ethtool_ops = { 1305 .cap_rss_ctx_supported = true, 1306 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1307 ETHTOOL_COALESCE_MAX_FRAMES | 1308 ETHTOOL_COALESCE_USE_ADAPTIVE, 1309 .supported_ring_params = ETHTOOL_RING_USE_RX_BUF_LEN | 1310 ETHTOOL_RING_USE_CQE_SIZE, 1311 .get_link = otx2_get_link, 1312 .get_drvinfo = otx2_get_drvinfo, 1313 .get_strings = otx2_get_strings, 1314 .get_ethtool_stats = otx2_get_ethtool_stats, 1315 .get_sset_count = otx2_get_sset_count, 1316 .set_channels = otx2_set_channels, 1317 .get_channels = otx2_get_channels, 1318 .get_ringparam = otx2_get_ringparam, 1319 .set_ringparam = otx2_set_ringparam, 1320 .get_coalesce = otx2_get_coalesce, 1321 .set_coalesce = otx2_set_coalesce, 1322 .get_rxnfc = otx2_get_rxnfc, 1323 .set_rxnfc = otx2_set_rxnfc, 1324 .get_rxfh_key_size = otx2_get_rxfh_key_size, 1325 .get_rxfh_indir_size = otx2_get_rxfh_indir_size, 1326 .get_rxfh = otx2_get_rxfh, 1327 .set_rxfh = otx2_set_rxfh, 1328 .get_msglevel = otx2_get_msglevel, 1329 .set_msglevel = otx2_set_msglevel, 1330 .get_pauseparam = otx2_get_pauseparam, 1331 .set_pauseparam = otx2_set_pauseparam, 1332 .get_ts_info = otx2_get_ts_info, 1333 .get_fec_stats = otx2_get_fec_stats, 1334 .get_fecparam = otx2_get_fecparam, 1335 .set_fecparam = otx2_set_fecparam, 1336 .get_link_ksettings = otx2_get_link_ksettings, 1337 .set_link_ksettings = otx2_set_link_ksettings, 1338 }; 1339 1340 void otx2_set_ethtool_ops(struct net_device *netdev) 1341 { 1342 netdev->ethtool_ops = &otx2_ethtool_ops; 1343 } 1344 1345 /* VF's ethtool APIs */ 1346 static void otx2vf_get_drvinfo(struct net_device *netdev, 1347 struct ethtool_drvinfo *info) 1348 { 1349 struct otx2_nic *vf = netdev_priv(netdev); 1350 1351 strscpy(info->driver, DRV_VF_NAME, sizeof(info->driver)); 1352 strscpy(info->bus_info, pci_name(vf->pdev), sizeof(info->bus_info)); 1353 } 1354 1355 static void otx2vf_get_strings(struct net_device *netdev, u32 sset, u8 *data) 1356 { 1357 struct otx2_nic *vf = netdev_priv(netdev); 1358 int stats; 1359 1360 if (sset != ETH_SS_STATS) 1361 return; 1362 1363 for (stats = 0; stats < otx2_n_dev_stats; stats++) 1364 ethtool_puts(&data, otx2_dev_stats[stats].name); 1365 1366 for (stats = 0; stats < otx2_n_drv_stats; stats++) 1367 ethtool_puts(&data, otx2_drv_stats[stats].name); 1368 1369 otx2_get_qset_strings(vf, &data, 0); 1370 1371 ethtool_puts(&data, "reset_count"); 1372 } 1373 1374 static void otx2vf_get_ethtool_stats(struct net_device *netdev, 1375 struct ethtool_stats *stats, u64 *data) 1376 { 1377 struct otx2_nic *vf = netdev_priv(netdev); 1378 int stat; 1379 1380 otx2_get_dev_stats(vf); 1381 for (stat = 0; stat < otx2_n_dev_stats; stat++) 1382 *(data++) = ((u64 *)&vf->hw.dev_stats) 1383 [otx2_dev_stats[stat].index]; 1384 1385 for (stat = 0; stat < otx2_n_drv_stats; stat++) 1386 *(data++) = atomic_read(&((atomic_t *)&vf->hw.drv_stats) 1387 [otx2_drv_stats[stat].index]); 1388 1389 otx2_get_qset_stats(vf, stats, &data); 1390 *(data++) = vf->reset_count; 1391 } 1392 1393 static int otx2vf_get_sset_count(struct net_device *netdev, int sset) 1394 { 1395 struct otx2_nic *vf = netdev_priv(netdev); 1396 int qstats_count; 1397 1398 if (sset != ETH_SS_STATS) 1399 return -EINVAL; 1400 1401 qstats_count = otx2_n_queue_stats * 1402 (vf->hw.rx_queues + otx2_get_total_tx_queues(vf)); 1403 1404 return otx2_n_dev_stats + otx2_n_drv_stats + qstats_count + 1; 1405 } 1406 1407 static int otx2vf_get_link_ksettings(struct net_device *netdev, 1408 struct ethtool_link_ksettings *cmd) 1409 { 1410 struct otx2_nic *pfvf = netdev_priv(netdev); 1411 1412 if (is_otx2_lbkvf(pfvf->pdev)) { 1413 cmd->base.duplex = DUPLEX_FULL; 1414 cmd->base.speed = SPEED_100000; 1415 } else { 1416 return otx2_get_link_ksettings(netdev, cmd); 1417 } 1418 return 0; 1419 } 1420 1421 static const struct ethtool_ops otx2vf_ethtool_ops = { 1422 .cap_rss_ctx_supported = true, 1423 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1424 ETHTOOL_COALESCE_MAX_FRAMES | 1425 ETHTOOL_COALESCE_USE_ADAPTIVE, 1426 .supported_ring_params = ETHTOOL_RING_USE_RX_BUF_LEN | 1427 ETHTOOL_RING_USE_CQE_SIZE, 1428 .get_link = otx2_get_link, 1429 .get_drvinfo = otx2vf_get_drvinfo, 1430 .get_strings = otx2vf_get_strings, 1431 .get_ethtool_stats = otx2vf_get_ethtool_stats, 1432 .get_sset_count = otx2vf_get_sset_count, 1433 .set_channels = otx2_set_channels, 1434 .get_channels = otx2_get_channels, 1435 .get_rxnfc = otx2_get_rxnfc, 1436 .set_rxnfc = otx2_set_rxnfc, 1437 .get_rxfh_key_size = otx2_get_rxfh_key_size, 1438 .get_rxfh_indir_size = otx2_get_rxfh_indir_size, 1439 .get_rxfh = otx2_get_rxfh, 1440 .set_rxfh = otx2_set_rxfh, 1441 .get_ringparam = otx2_get_ringparam, 1442 .set_ringparam = otx2_set_ringparam, 1443 .get_coalesce = otx2_get_coalesce, 1444 .set_coalesce = otx2_set_coalesce, 1445 .get_msglevel = otx2_get_msglevel, 1446 .set_msglevel = otx2_set_msglevel, 1447 .get_pauseparam = otx2_get_pauseparam, 1448 .set_pauseparam = otx2_set_pauseparam, 1449 .get_link_ksettings = otx2vf_get_link_ksettings, 1450 .get_ts_info = otx2_get_ts_info, 1451 }; 1452 1453 void otx2vf_set_ethtool_ops(struct net_device *netdev) 1454 { 1455 netdev->ethtool_ops = &otx2vf_ethtool_ops; 1456 } 1457 EXPORT_SYMBOL(otx2vf_set_ethtool_ops); 1458