1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/pci.h> 9 #include <linux/ethtool.h> 10 #include <linux/stddef.h> 11 #include <linux/etherdevice.h> 12 #include <linux/log2.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/linkmode.h> 15 16 #include "otx2_common.h" 17 #include "otx2_ptp.h" 18 19 #define DRV_NAME "rvu-nicpf" 20 #define DRV_VF_NAME "rvu-nicvf" 21 22 struct otx2_stat { 23 char name[ETH_GSTRING_LEN]; 24 unsigned int index; 25 }; 26 27 /* HW device stats */ 28 #define OTX2_DEV_STAT(stat) { \ 29 .name = #stat, \ 30 .index = offsetof(struct otx2_dev_stats, stat) / sizeof(u64), \ 31 } 32 33 enum link_mode { 34 OTX2_MODE_SUPPORTED, 35 OTX2_MODE_ADVERTISED 36 }; 37 38 static const struct otx2_stat otx2_dev_stats[] = { 39 OTX2_DEV_STAT(rx_ucast_frames), 40 OTX2_DEV_STAT(rx_bcast_frames), 41 OTX2_DEV_STAT(rx_mcast_frames), 42 43 OTX2_DEV_STAT(tx_ucast_frames), 44 OTX2_DEV_STAT(tx_bcast_frames), 45 OTX2_DEV_STAT(tx_mcast_frames), 46 }; 47 48 /* Driver level stats */ 49 #define OTX2_DRV_STAT(stat) { \ 50 .name = #stat, \ 51 .index = offsetof(struct otx2_drv_stats, stat) / sizeof(atomic_t), \ 52 } 53 54 static const struct otx2_stat otx2_drv_stats[] = { 55 OTX2_DRV_STAT(rx_fcs_errs), 56 OTX2_DRV_STAT(rx_oversize_errs), 57 OTX2_DRV_STAT(rx_undersize_errs), 58 OTX2_DRV_STAT(rx_csum_errs), 59 OTX2_DRV_STAT(rx_len_errs), 60 OTX2_DRV_STAT(rx_other_errs), 61 }; 62 63 static const struct otx2_stat otx2_queue_stats[] = { 64 { "bytes", 0 }, 65 { "frames", 1 }, 66 }; 67 68 static const unsigned int otx2_n_dev_stats = ARRAY_SIZE(otx2_dev_stats); 69 static const unsigned int otx2_n_drv_stats = ARRAY_SIZE(otx2_drv_stats); 70 static const unsigned int otx2_n_queue_stats = ARRAY_SIZE(otx2_queue_stats); 71 72 static struct cgx_fw_data *otx2_get_fwdata(struct otx2_nic *pfvf); 73 74 static void otx2_get_drvinfo(struct net_device *netdev, 75 struct ethtool_drvinfo *info) 76 { 77 struct otx2_nic *pfvf = netdev_priv(netdev); 78 79 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 80 strscpy(info->bus_info, pci_name(pfvf->pdev), sizeof(info->bus_info)); 81 } 82 83 static void otx2_get_qset_strings(struct otx2_nic *pfvf, u8 **data, int qset) 84 { 85 int start_qidx = qset * pfvf->hw.rx_queues; 86 int qidx, stats; 87 88 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 89 for (stats = 0; stats < otx2_n_queue_stats; stats++) { 90 sprintf(*data, "rxq%d: %s", qidx + start_qidx, 91 otx2_queue_stats[stats].name); 92 *data += ETH_GSTRING_LEN; 93 } 94 } 95 96 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 97 for (stats = 0; stats < otx2_n_queue_stats; stats++) { 98 if (qidx >= pfvf->hw.non_qos_queues) 99 sprintf(*data, "txq_qos%d: %s", 100 qidx + start_qidx - pfvf->hw.non_qos_queues, 101 otx2_queue_stats[stats].name); 102 else 103 sprintf(*data, "txq%d: %s", qidx + start_qidx, 104 otx2_queue_stats[stats].name); 105 *data += ETH_GSTRING_LEN; 106 } 107 } 108 } 109 110 static void otx2_get_strings(struct net_device *netdev, u32 sset, u8 *data) 111 { 112 struct otx2_nic *pfvf = netdev_priv(netdev); 113 int stats; 114 115 if (sset != ETH_SS_STATS) 116 return; 117 118 for (stats = 0; stats < otx2_n_dev_stats; stats++) { 119 memcpy(data, otx2_dev_stats[stats].name, ETH_GSTRING_LEN); 120 data += ETH_GSTRING_LEN; 121 } 122 123 for (stats = 0; stats < otx2_n_drv_stats; stats++) { 124 memcpy(data, otx2_drv_stats[stats].name, ETH_GSTRING_LEN); 125 data += ETH_GSTRING_LEN; 126 } 127 128 otx2_get_qset_strings(pfvf, &data, 0); 129 130 if (!test_bit(CN10K_RPM, &pfvf->hw.cap_flag)) { 131 for (stats = 0; stats < CGX_RX_STATS_COUNT; stats++) { 132 sprintf(data, "cgx_rxstat%d: ", stats); 133 data += ETH_GSTRING_LEN; 134 } 135 136 for (stats = 0; stats < CGX_TX_STATS_COUNT; stats++) { 137 sprintf(data, "cgx_txstat%d: ", stats); 138 data += ETH_GSTRING_LEN; 139 } 140 } 141 142 strcpy(data, "reset_count"); 143 data += ETH_GSTRING_LEN; 144 sprintf(data, "Fec Corrected Errors: "); 145 data += ETH_GSTRING_LEN; 146 sprintf(data, "Fec Uncorrected Errors: "); 147 data += ETH_GSTRING_LEN; 148 } 149 150 static void otx2_get_qset_stats(struct otx2_nic *pfvf, 151 struct ethtool_stats *stats, u64 **data) 152 { 153 int stat, qidx; 154 155 if (!pfvf) 156 return; 157 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 158 if (!otx2_update_rq_stats(pfvf, qidx)) { 159 for (stat = 0; stat < otx2_n_queue_stats; stat++) 160 *((*data)++) = 0; 161 continue; 162 } 163 for (stat = 0; stat < otx2_n_queue_stats; stat++) 164 *((*data)++) = ((u64 *)&pfvf->qset.rq[qidx].stats) 165 [otx2_queue_stats[stat].index]; 166 } 167 168 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 169 if (!otx2_update_sq_stats(pfvf, qidx)) { 170 for (stat = 0; stat < otx2_n_queue_stats; stat++) 171 *((*data)++) = 0; 172 continue; 173 } 174 for (stat = 0; stat < otx2_n_queue_stats; stat++) 175 *((*data)++) = ((u64 *)&pfvf->qset.sq[qidx].stats) 176 [otx2_queue_stats[stat].index]; 177 } 178 } 179 180 static int otx2_get_phy_fec_stats(struct otx2_nic *pfvf) 181 { 182 struct msg_req *req; 183 int rc = -ENOMEM; 184 185 mutex_lock(&pfvf->mbox.lock); 186 req = otx2_mbox_alloc_msg_cgx_get_phy_fec_stats(&pfvf->mbox); 187 if (!req) 188 goto end; 189 190 if (!otx2_sync_mbox_msg(&pfvf->mbox)) 191 rc = 0; 192 end: 193 mutex_unlock(&pfvf->mbox.lock); 194 return rc; 195 } 196 197 /* Get device and per queue statistics */ 198 static void otx2_get_ethtool_stats(struct net_device *netdev, 199 struct ethtool_stats *stats, u64 *data) 200 { 201 struct otx2_nic *pfvf = netdev_priv(netdev); 202 u64 fec_corr_blks, fec_uncorr_blks; 203 struct cgx_fw_data *rsp; 204 int stat; 205 206 otx2_get_dev_stats(pfvf); 207 for (stat = 0; stat < otx2_n_dev_stats; stat++) 208 *(data++) = ((u64 *)&pfvf->hw.dev_stats) 209 [otx2_dev_stats[stat].index]; 210 211 for (stat = 0; stat < otx2_n_drv_stats; stat++) 212 *(data++) = atomic_read(&((atomic_t *)&pfvf->hw.drv_stats) 213 [otx2_drv_stats[stat].index]); 214 215 otx2_get_qset_stats(pfvf, stats, &data); 216 217 if (!test_bit(CN10K_RPM, &pfvf->hw.cap_flag)) { 218 otx2_update_lmac_stats(pfvf); 219 for (stat = 0; stat < CGX_RX_STATS_COUNT; stat++) 220 *(data++) = pfvf->hw.cgx_rx_stats[stat]; 221 for (stat = 0; stat < CGX_TX_STATS_COUNT; stat++) 222 *(data++) = pfvf->hw.cgx_tx_stats[stat]; 223 } 224 225 *(data++) = pfvf->reset_count; 226 227 fec_corr_blks = pfvf->hw.cgx_fec_corr_blks; 228 fec_uncorr_blks = pfvf->hw.cgx_fec_uncorr_blks; 229 230 rsp = otx2_get_fwdata(pfvf); 231 if (!IS_ERR(rsp) && rsp->fwdata.phy.misc.has_fec_stats && 232 !otx2_get_phy_fec_stats(pfvf)) { 233 /* Fetch fwdata again because it's been recently populated with 234 * latest PHY FEC stats. 235 */ 236 rsp = otx2_get_fwdata(pfvf); 237 if (!IS_ERR(rsp)) { 238 struct fec_stats_s *p = &rsp->fwdata.phy.fec_stats; 239 240 if (pfvf->linfo.fec == OTX2_FEC_BASER) { 241 fec_corr_blks = p->brfec_corr_blks; 242 fec_uncorr_blks = p->brfec_uncorr_blks; 243 } else { 244 fec_corr_blks = p->rsfec_corr_cws; 245 fec_uncorr_blks = p->rsfec_uncorr_cws; 246 } 247 } 248 } 249 250 *(data++) = fec_corr_blks; 251 *(data++) = fec_uncorr_blks; 252 } 253 254 static int otx2_get_sset_count(struct net_device *netdev, int sset) 255 { 256 struct otx2_nic *pfvf = netdev_priv(netdev); 257 int qstats_count, mac_stats = 0; 258 259 if (sset != ETH_SS_STATS) 260 return -EINVAL; 261 262 qstats_count = otx2_n_queue_stats * 263 (pfvf->hw.rx_queues + otx2_get_total_tx_queues(pfvf)); 264 if (!test_bit(CN10K_RPM, &pfvf->hw.cap_flag)) 265 mac_stats = CGX_RX_STATS_COUNT + CGX_TX_STATS_COUNT; 266 otx2_update_lmac_fec_stats(pfvf); 267 268 return otx2_n_dev_stats + otx2_n_drv_stats + qstats_count + 269 mac_stats + OTX2_FEC_STATS_CNT + 1; 270 } 271 272 /* Get no of queues device supports and current queue count */ 273 static void otx2_get_channels(struct net_device *dev, 274 struct ethtool_channels *channel) 275 { 276 struct otx2_nic *pfvf = netdev_priv(dev); 277 278 channel->max_rx = pfvf->hw.max_queues; 279 channel->max_tx = pfvf->hw.max_queues; 280 281 channel->rx_count = pfvf->hw.rx_queues; 282 channel->tx_count = pfvf->hw.tx_queues; 283 } 284 285 /* Set no of Tx, Rx queues to be used */ 286 static int otx2_set_channels(struct net_device *dev, 287 struct ethtool_channels *channel) 288 { 289 struct otx2_nic *pfvf = netdev_priv(dev); 290 bool if_up = netif_running(dev); 291 int err, qos_txqs; 292 293 if (!channel->rx_count || !channel->tx_count) 294 return -EINVAL; 295 296 if (bitmap_weight(&pfvf->rq_bmap, pfvf->hw.rx_queues) > 1) { 297 netdev_err(dev, 298 "Receive queues are in use by TC police action\n"); 299 return -EINVAL; 300 } 301 302 if (if_up) 303 dev->netdev_ops->ndo_stop(dev); 304 305 qos_txqs = bitmap_weight(pfvf->qos.qos_sq_bmap, 306 OTX2_QOS_MAX_LEAF_NODES); 307 308 err = otx2_set_real_num_queues(dev, channel->tx_count + qos_txqs, 309 channel->rx_count); 310 if (err) 311 return err; 312 313 pfvf->hw.rx_queues = channel->rx_count; 314 pfvf->hw.tx_queues = channel->tx_count; 315 if (pfvf->xdp_prog) 316 pfvf->hw.xdp_queues = channel->rx_count; 317 pfvf->hw.non_qos_queues = pfvf->hw.tx_queues + pfvf->hw.xdp_queues; 318 319 if (if_up) 320 err = dev->netdev_ops->ndo_open(dev); 321 322 netdev_info(dev, "Setting num Tx rings to %d, Rx rings to %d success\n", 323 pfvf->hw.tx_queues, pfvf->hw.rx_queues); 324 325 return err; 326 } 327 328 static void otx2_get_pauseparam(struct net_device *netdev, 329 struct ethtool_pauseparam *pause) 330 { 331 struct otx2_nic *pfvf = netdev_priv(netdev); 332 struct cgx_pause_frm_cfg *req, *rsp; 333 334 if (is_otx2_lbkvf(pfvf->pdev)) 335 return; 336 337 mutex_lock(&pfvf->mbox.lock); 338 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 339 if (!req) { 340 mutex_unlock(&pfvf->mbox.lock); 341 return; 342 } 343 344 if (!otx2_sync_mbox_msg(&pfvf->mbox)) { 345 rsp = (struct cgx_pause_frm_cfg *) 346 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 347 pause->rx_pause = rsp->rx_pause; 348 pause->tx_pause = rsp->tx_pause; 349 } 350 mutex_unlock(&pfvf->mbox.lock); 351 } 352 353 static int otx2_set_pauseparam(struct net_device *netdev, 354 struct ethtool_pauseparam *pause) 355 { 356 struct otx2_nic *pfvf = netdev_priv(netdev); 357 358 if (pause->autoneg) 359 return -EOPNOTSUPP; 360 361 if (is_otx2_lbkvf(pfvf->pdev)) 362 return -EOPNOTSUPP; 363 364 if (pause->rx_pause) 365 pfvf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 366 else 367 pfvf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 368 369 if (pause->tx_pause) 370 pfvf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 371 else 372 pfvf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 373 374 return otx2_config_pause_frm(pfvf); 375 } 376 377 static void otx2_get_ringparam(struct net_device *netdev, 378 struct ethtool_ringparam *ring, 379 struct kernel_ethtool_ringparam *kernel_ring, 380 struct netlink_ext_ack *extack) 381 { 382 struct otx2_nic *pfvf = netdev_priv(netdev); 383 struct otx2_qset *qs = &pfvf->qset; 384 385 ring->rx_max_pending = Q_COUNT(Q_SIZE_MAX); 386 ring->rx_pending = qs->rqe_cnt ? qs->rqe_cnt : Q_COUNT(Q_SIZE_256); 387 ring->tx_max_pending = Q_COUNT(Q_SIZE_MAX); 388 ring->tx_pending = qs->sqe_cnt ? qs->sqe_cnt : Q_COUNT(Q_SIZE_4K); 389 kernel_ring->rx_buf_len = pfvf->hw.rbuf_len; 390 kernel_ring->cqe_size = pfvf->hw.xqe_size; 391 } 392 393 static int otx2_set_ringparam(struct net_device *netdev, 394 struct ethtool_ringparam *ring, 395 struct kernel_ethtool_ringparam *kernel_ring, 396 struct netlink_ext_ack *extack) 397 { 398 struct otx2_nic *pfvf = netdev_priv(netdev); 399 u32 rx_buf_len = kernel_ring->rx_buf_len; 400 u32 old_rx_buf_len = pfvf->hw.rbuf_len; 401 u32 xqe_size = kernel_ring->cqe_size; 402 bool if_up = netif_running(netdev); 403 struct otx2_qset *qs = &pfvf->qset; 404 u32 rx_count, tx_count; 405 406 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 407 return -EINVAL; 408 409 /* Hardware supports max size of 32k for a receive buffer 410 * and 1536 is typical ethernet frame size. 411 */ 412 if (rx_buf_len && (rx_buf_len < 1536 || rx_buf_len > 32768)) { 413 netdev_err(netdev, 414 "Receive buffer range is 1536 - 32768"); 415 return -EINVAL; 416 } 417 418 if (xqe_size != 128 && xqe_size != 512) { 419 netdev_err(netdev, 420 "Completion event size must be 128 or 512"); 421 return -EINVAL; 422 } 423 424 /* Permitted lengths are 16 64 256 1K 4K 16K 64K 256K 1M */ 425 rx_count = ring->rx_pending; 426 /* On some silicon variants a skid or reserved CQEs are 427 * needed to avoid CQ overflow. 428 */ 429 if (rx_count < pfvf->hw.rq_skid) 430 rx_count = pfvf->hw.rq_skid; 431 rx_count = Q_COUNT(Q_SIZE(rx_count, 3)); 432 433 /* Due pipelining impact minimum 2000 unused SQ CQE's 434 * need to be maintained to avoid CQ overflow, hence the 435 * minimum 4K size. 436 */ 437 tx_count = clamp_t(u32, ring->tx_pending, 438 Q_COUNT(Q_SIZE_4K), Q_COUNT(Q_SIZE_MAX)); 439 tx_count = Q_COUNT(Q_SIZE(tx_count, 3)); 440 441 if (tx_count == qs->sqe_cnt && rx_count == qs->rqe_cnt && 442 rx_buf_len == old_rx_buf_len && xqe_size == pfvf->hw.xqe_size) 443 return 0; 444 445 if (if_up) 446 netdev->netdev_ops->ndo_stop(netdev); 447 448 /* Assigned to the nearest possible exponent. */ 449 qs->sqe_cnt = tx_count; 450 qs->rqe_cnt = rx_count; 451 452 pfvf->hw.rbuf_len = rx_buf_len; 453 pfvf->hw.xqe_size = xqe_size; 454 455 if (if_up) 456 return netdev->netdev_ops->ndo_open(netdev); 457 458 return 0; 459 } 460 461 static int otx2_get_coalesce(struct net_device *netdev, 462 struct ethtool_coalesce *cmd, 463 struct kernel_ethtool_coalesce *kernel_coal, 464 struct netlink_ext_ack *extack) 465 { 466 struct otx2_nic *pfvf = netdev_priv(netdev); 467 struct otx2_hw *hw = &pfvf->hw; 468 469 cmd->rx_coalesce_usecs = hw->cq_time_wait; 470 cmd->rx_max_coalesced_frames = hw->cq_ecount_wait; 471 cmd->tx_coalesce_usecs = hw->cq_time_wait; 472 cmd->tx_max_coalesced_frames = hw->cq_ecount_wait; 473 if ((pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED) == 474 OTX2_FLAG_ADPTV_INT_COAL_ENABLED) { 475 cmd->use_adaptive_rx_coalesce = 1; 476 cmd->use_adaptive_tx_coalesce = 1; 477 } else { 478 cmd->use_adaptive_rx_coalesce = 0; 479 cmd->use_adaptive_tx_coalesce = 0; 480 } 481 482 return 0; 483 } 484 485 static int otx2_set_coalesce(struct net_device *netdev, 486 struct ethtool_coalesce *ec, 487 struct kernel_ethtool_coalesce *kernel_coal, 488 struct netlink_ext_ack *extack) 489 { 490 struct otx2_nic *pfvf = netdev_priv(netdev); 491 struct otx2_hw *hw = &pfvf->hw; 492 u8 priv_coalesce_status; 493 int qidx; 494 495 if (!ec->rx_max_coalesced_frames || !ec->tx_max_coalesced_frames) 496 return 0; 497 498 if (ec->use_adaptive_rx_coalesce != ec->use_adaptive_tx_coalesce) { 499 netdev_err(netdev, 500 "adaptive-rx should be same as adaptive-tx"); 501 return -EINVAL; 502 } 503 504 /* Check and update coalesce status */ 505 if ((pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED) == 506 OTX2_FLAG_ADPTV_INT_COAL_ENABLED) { 507 priv_coalesce_status = 1; 508 if (!ec->use_adaptive_rx_coalesce) 509 pfvf->flags &= ~OTX2_FLAG_ADPTV_INT_COAL_ENABLED; 510 } else { 511 priv_coalesce_status = 0; 512 if (ec->use_adaptive_rx_coalesce) 513 pfvf->flags |= OTX2_FLAG_ADPTV_INT_COAL_ENABLED; 514 } 515 516 /* 'cq_time_wait' is 8bit and is in multiple of 100ns, 517 * so clamp the user given value to the range of 1 to 25usec. 518 */ 519 ec->rx_coalesce_usecs = clamp_t(u32, ec->rx_coalesce_usecs, 520 1, CQ_TIMER_THRESH_MAX); 521 ec->tx_coalesce_usecs = clamp_t(u32, ec->tx_coalesce_usecs, 522 1, CQ_TIMER_THRESH_MAX); 523 524 /* Rx and Tx are mapped to same CQ, check which one 525 * is changed, if both then choose the min. 526 */ 527 if (hw->cq_time_wait == ec->rx_coalesce_usecs) 528 hw->cq_time_wait = ec->tx_coalesce_usecs; 529 else if (hw->cq_time_wait == ec->tx_coalesce_usecs) 530 hw->cq_time_wait = ec->rx_coalesce_usecs; 531 else 532 hw->cq_time_wait = min_t(u8, ec->rx_coalesce_usecs, 533 ec->tx_coalesce_usecs); 534 535 /* Max ecount_wait supported is 16bit, 536 * so clamp the user given value to the range of 1 to 64k. 537 */ 538 ec->rx_max_coalesced_frames = clamp_t(u32, ec->rx_max_coalesced_frames, 539 1, NAPI_POLL_WEIGHT); 540 ec->tx_max_coalesced_frames = clamp_t(u32, ec->tx_max_coalesced_frames, 541 1, NAPI_POLL_WEIGHT); 542 543 /* Rx and Tx are mapped to same CQ, check which one 544 * is changed, if both then choose the min. 545 */ 546 if (hw->cq_ecount_wait == ec->rx_max_coalesced_frames) 547 hw->cq_ecount_wait = ec->tx_max_coalesced_frames; 548 else if (hw->cq_ecount_wait == ec->tx_max_coalesced_frames) 549 hw->cq_ecount_wait = ec->rx_max_coalesced_frames; 550 else 551 hw->cq_ecount_wait = min_t(u16, ec->rx_max_coalesced_frames, 552 ec->tx_max_coalesced_frames); 553 554 /* Reset 'cq_time_wait' and 'cq_ecount_wait' to 555 * default values if coalesce status changed from 556 * 'on' to 'off'. 557 */ 558 if (priv_coalesce_status && 559 ((pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED) != 560 OTX2_FLAG_ADPTV_INT_COAL_ENABLED)) { 561 hw->cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 562 hw->cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 563 } 564 565 if (netif_running(netdev)) { 566 for (qidx = 0; qidx < pfvf->hw.cint_cnt; qidx++) 567 otx2_config_irq_coalescing(pfvf, qidx); 568 } 569 570 return 0; 571 } 572 573 static int otx2_get_rss_hash_opts(struct otx2_nic *pfvf, 574 struct ethtool_rxnfc *nfc) 575 { 576 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 577 578 if (!(rss->flowkey_cfg & 579 (NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6))) 580 return 0; 581 582 /* Mimimum is IPv4 and IPv6, SIP/DIP */ 583 nfc->data = RXH_IP_SRC | RXH_IP_DST; 584 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_VLAN) 585 nfc->data |= RXH_VLAN; 586 587 switch (nfc->flow_type) { 588 case TCP_V4_FLOW: 589 case TCP_V6_FLOW: 590 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_TCP) 591 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 592 break; 593 case UDP_V4_FLOW: 594 case UDP_V6_FLOW: 595 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_UDP) 596 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 597 break; 598 case SCTP_V4_FLOW: 599 case SCTP_V6_FLOW: 600 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_SCTP) 601 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 602 break; 603 case AH_ESP_V4_FLOW: 604 case AH_ESP_V6_FLOW: 605 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_ESP) 606 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 607 break; 608 case AH_V4_FLOW: 609 case ESP_V4_FLOW: 610 case IPV4_FLOW: 611 break; 612 case AH_V6_FLOW: 613 case ESP_V6_FLOW: 614 case IPV6_FLOW: 615 break; 616 default: 617 return -EINVAL; 618 } 619 620 return 0; 621 } 622 623 static int otx2_set_rss_hash_opts(struct otx2_nic *pfvf, 624 struct ethtool_rxnfc *nfc) 625 { 626 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 627 u32 rxh_l4 = RXH_L4_B_0_1 | RXH_L4_B_2_3; 628 u32 rss_cfg = rss->flowkey_cfg; 629 630 if (!rss->enable) { 631 netdev_err(pfvf->netdev, 632 "RSS is disabled, cannot change settings\n"); 633 return -EIO; 634 } 635 636 /* Mimimum is IPv4 and IPv6, SIP/DIP */ 637 if (!(nfc->data & RXH_IP_SRC) || !(nfc->data & RXH_IP_DST)) 638 return -EINVAL; 639 640 if (nfc->data & RXH_VLAN) 641 rss_cfg |= NIX_FLOW_KEY_TYPE_VLAN; 642 else 643 rss_cfg &= ~NIX_FLOW_KEY_TYPE_VLAN; 644 645 switch (nfc->flow_type) { 646 case TCP_V4_FLOW: 647 case TCP_V6_FLOW: 648 /* Different config for v4 and v6 is not supported. 649 * Both of them have to be either 4-tuple or 2-tuple. 650 */ 651 switch (nfc->data & rxh_l4) { 652 case 0: 653 rss_cfg &= ~NIX_FLOW_KEY_TYPE_TCP; 654 break; 655 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 656 rss_cfg |= NIX_FLOW_KEY_TYPE_TCP; 657 break; 658 default: 659 return -EINVAL; 660 } 661 break; 662 case UDP_V4_FLOW: 663 case UDP_V6_FLOW: 664 switch (nfc->data & rxh_l4) { 665 case 0: 666 rss_cfg &= ~NIX_FLOW_KEY_TYPE_UDP; 667 break; 668 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 669 rss_cfg |= NIX_FLOW_KEY_TYPE_UDP; 670 break; 671 default: 672 return -EINVAL; 673 } 674 break; 675 case SCTP_V4_FLOW: 676 case SCTP_V6_FLOW: 677 switch (nfc->data & rxh_l4) { 678 case 0: 679 rss_cfg &= ~NIX_FLOW_KEY_TYPE_SCTP; 680 break; 681 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 682 rss_cfg |= NIX_FLOW_KEY_TYPE_SCTP; 683 break; 684 default: 685 return -EINVAL; 686 } 687 break; 688 case AH_ESP_V4_FLOW: 689 case AH_ESP_V6_FLOW: 690 switch (nfc->data & rxh_l4) { 691 case 0: 692 rss_cfg &= ~(NIX_FLOW_KEY_TYPE_ESP | 693 NIX_FLOW_KEY_TYPE_AH); 694 rss_cfg |= NIX_FLOW_KEY_TYPE_VLAN | 695 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 696 break; 697 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 698 /* If VLAN hashing is also requested for ESP then do not 699 * allow because of hardware 40 bytes flow key limit. 700 */ 701 if (rss_cfg & NIX_FLOW_KEY_TYPE_VLAN) { 702 netdev_err(pfvf->netdev, 703 "RSS hash of ESP or AH with VLAN is not supported\n"); 704 return -EOPNOTSUPP; 705 } 706 707 rss_cfg |= NIX_FLOW_KEY_TYPE_ESP | NIX_FLOW_KEY_TYPE_AH; 708 /* Disable IPv4 proto hashing since IPv6 SA+DA(32 bytes) 709 * and ESP SPI+sequence(8 bytes) uses hardware maximum 710 * limit of 40 byte flow key. 711 */ 712 rss_cfg &= ~NIX_FLOW_KEY_TYPE_IPV4_PROTO; 713 break; 714 default: 715 return -EINVAL; 716 } 717 break; 718 case IPV4_FLOW: 719 case IPV6_FLOW: 720 rss_cfg = NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6; 721 break; 722 default: 723 return -EINVAL; 724 } 725 726 rss->flowkey_cfg = rss_cfg; 727 otx2_set_flowkey_cfg(pfvf); 728 return 0; 729 } 730 731 static int otx2_get_rxnfc(struct net_device *dev, 732 struct ethtool_rxnfc *nfc, u32 *rules) 733 { 734 bool ntuple = !!(dev->features & NETIF_F_NTUPLE); 735 struct otx2_nic *pfvf = netdev_priv(dev); 736 int ret = -EOPNOTSUPP; 737 738 switch (nfc->cmd) { 739 case ETHTOOL_GRXRINGS: 740 nfc->data = pfvf->hw.rx_queues; 741 ret = 0; 742 break; 743 case ETHTOOL_GRXCLSRLCNT: 744 if (netif_running(dev) && ntuple) { 745 nfc->rule_cnt = pfvf->flow_cfg->nr_flows; 746 ret = 0; 747 } 748 break; 749 case ETHTOOL_GRXCLSRULE: 750 if (netif_running(dev) && ntuple) 751 ret = otx2_get_flow(pfvf, nfc, nfc->fs.location); 752 break; 753 case ETHTOOL_GRXCLSRLALL: 754 if (netif_running(dev) && ntuple) 755 ret = otx2_get_all_flows(pfvf, nfc, rules); 756 break; 757 case ETHTOOL_GRXFH: 758 return otx2_get_rss_hash_opts(pfvf, nfc); 759 default: 760 break; 761 } 762 return ret; 763 } 764 765 static int otx2_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *nfc) 766 { 767 bool ntuple = !!(dev->features & NETIF_F_NTUPLE); 768 struct otx2_nic *pfvf = netdev_priv(dev); 769 int ret = -EOPNOTSUPP; 770 771 pfvf->flow_cfg->ntuple = ntuple; 772 switch (nfc->cmd) { 773 case ETHTOOL_SRXFH: 774 ret = otx2_set_rss_hash_opts(pfvf, nfc); 775 break; 776 case ETHTOOL_SRXCLSRLINS: 777 if (netif_running(dev) && ntuple) 778 ret = otx2_add_flow(pfvf, nfc); 779 break; 780 case ETHTOOL_SRXCLSRLDEL: 781 if (netif_running(dev) && ntuple) 782 ret = otx2_remove_flow(pfvf, nfc->fs.location); 783 break; 784 default: 785 break; 786 } 787 788 return ret; 789 } 790 791 static u32 otx2_get_rxfh_key_size(struct net_device *netdev) 792 { 793 struct otx2_nic *pfvf = netdev_priv(netdev); 794 struct otx2_rss_info *rss; 795 796 rss = &pfvf->hw.rss_info; 797 798 return sizeof(rss->key); 799 } 800 801 static u32 otx2_get_rxfh_indir_size(struct net_device *dev) 802 { 803 return MAX_RSS_INDIR_TBL_SIZE; 804 } 805 806 static int otx2_rss_ctx_delete(struct otx2_nic *pfvf, int ctx_id) 807 { 808 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 809 810 otx2_rss_ctx_flow_del(pfvf, ctx_id); 811 kfree(rss->rss_ctx[ctx_id]); 812 rss->rss_ctx[ctx_id] = NULL; 813 814 return 0; 815 } 816 817 static int otx2_rss_ctx_create(struct otx2_nic *pfvf, 818 u32 *rss_context) 819 { 820 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 821 u8 ctx; 822 823 for (ctx = 0; ctx < MAX_RSS_GROUPS; ctx++) { 824 if (!rss->rss_ctx[ctx]) 825 break; 826 } 827 if (ctx == MAX_RSS_GROUPS) 828 return -EINVAL; 829 830 rss->rss_ctx[ctx] = kzalloc(sizeof(*rss->rss_ctx[ctx]), GFP_KERNEL); 831 if (!rss->rss_ctx[ctx]) 832 return -ENOMEM; 833 *rss_context = ctx; 834 835 return 0; 836 } 837 838 /* Configure RSS table and hash key */ 839 static int otx2_set_rxfh(struct net_device *dev, 840 struct ethtool_rxfh_param *rxfh, 841 struct netlink_ext_ack *extack) 842 { 843 u32 rss_context = DEFAULT_RSS_CONTEXT_GROUP; 844 struct otx2_nic *pfvf = netdev_priv(dev); 845 struct otx2_rss_ctx *rss_ctx; 846 struct otx2_rss_info *rss; 847 int ret, idx; 848 849 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 850 rxfh->hfunc != ETH_RSS_HASH_TOP) 851 return -EOPNOTSUPP; 852 853 if (rxfh->rss_context) 854 rss_context = rxfh->rss_context; 855 856 if (rss_context != ETH_RXFH_CONTEXT_ALLOC && 857 rss_context >= MAX_RSS_GROUPS) 858 return -EINVAL; 859 860 rss = &pfvf->hw.rss_info; 861 862 if (!rss->enable) { 863 netdev_err(dev, "RSS is disabled, cannot change settings\n"); 864 return -EIO; 865 } 866 867 if (rxfh->key) { 868 memcpy(rss->key, rxfh->key, sizeof(rss->key)); 869 otx2_set_rss_key(pfvf); 870 } 871 if (rxfh->rss_delete) 872 return otx2_rss_ctx_delete(pfvf, rss_context); 873 874 if (rss_context == ETH_RXFH_CONTEXT_ALLOC) { 875 ret = otx2_rss_ctx_create(pfvf, &rss_context); 876 rxfh->rss_context = rss_context; 877 if (ret) 878 return ret; 879 } 880 if (rxfh->indir) { 881 rss_ctx = rss->rss_ctx[rss_context]; 882 for (idx = 0; idx < rss->rss_size; idx++) 883 rss_ctx->ind_tbl[idx] = rxfh->indir[idx]; 884 } 885 otx2_set_rss_table(pfvf, rss_context); 886 887 return 0; 888 } 889 890 /* Get RSS configuration */ 891 static int otx2_get_rxfh(struct net_device *dev, 892 struct ethtool_rxfh_param *rxfh) 893 { 894 u32 rss_context = DEFAULT_RSS_CONTEXT_GROUP; 895 struct otx2_nic *pfvf = netdev_priv(dev); 896 struct otx2_rss_ctx *rss_ctx; 897 struct otx2_rss_info *rss; 898 u32 *indir = rxfh->indir; 899 int idx, rx_queues; 900 901 rss = &pfvf->hw.rss_info; 902 903 rxfh->hfunc = ETH_RSS_HASH_TOP; 904 if (rxfh->rss_context) 905 rss_context = rxfh->rss_context; 906 907 if (!indir) 908 return 0; 909 910 if (!rss->enable && rss_context == DEFAULT_RSS_CONTEXT_GROUP) { 911 rx_queues = pfvf->hw.rx_queues; 912 for (idx = 0; idx < MAX_RSS_INDIR_TBL_SIZE; idx++) 913 indir[idx] = ethtool_rxfh_indir_default(idx, rx_queues); 914 return 0; 915 } 916 if (rss_context >= MAX_RSS_GROUPS) 917 return -ENOENT; 918 919 rss_ctx = rss->rss_ctx[rss_context]; 920 if (!rss_ctx) 921 return -ENOENT; 922 923 if (indir) { 924 for (idx = 0; idx < rss->rss_size; idx++) 925 indir[idx] = rss_ctx->ind_tbl[idx]; 926 } 927 if (rxfh->key) 928 memcpy(rxfh->key, rss->key, sizeof(rss->key)); 929 930 return 0; 931 } 932 933 static u32 otx2_get_msglevel(struct net_device *netdev) 934 { 935 struct otx2_nic *pfvf = netdev_priv(netdev); 936 937 return pfvf->msg_enable; 938 } 939 940 static void otx2_set_msglevel(struct net_device *netdev, u32 val) 941 { 942 struct otx2_nic *pfvf = netdev_priv(netdev); 943 944 pfvf->msg_enable = val; 945 } 946 947 static u32 otx2_get_link(struct net_device *netdev) 948 { 949 struct otx2_nic *pfvf = netdev_priv(netdev); 950 951 /* LBK link is internal and always UP */ 952 if (is_otx2_lbkvf(pfvf->pdev)) 953 return 1; 954 return pfvf->linfo.link_up; 955 } 956 957 static int otx2_get_ts_info(struct net_device *netdev, 958 struct ethtool_ts_info *info) 959 { 960 struct otx2_nic *pfvf = netdev_priv(netdev); 961 962 if (!pfvf->ptp) 963 return ethtool_op_get_ts_info(netdev, info); 964 965 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 966 SOF_TIMESTAMPING_RX_SOFTWARE | 967 SOF_TIMESTAMPING_SOFTWARE | 968 SOF_TIMESTAMPING_TX_HARDWARE | 969 SOF_TIMESTAMPING_RX_HARDWARE | 970 SOF_TIMESTAMPING_RAW_HARDWARE; 971 972 info->phc_index = otx2_ptp_clock_index(pfvf); 973 974 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 975 if (test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 976 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_SYNC); 977 978 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 979 BIT(HWTSTAMP_FILTER_ALL); 980 981 return 0; 982 } 983 984 static struct cgx_fw_data *otx2_get_fwdata(struct otx2_nic *pfvf) 985 { 986 struct cgx_fw_data *rsp = NULL; 987 struct msg_req *req; 988 int err = 0; 989 990 mutex_lock(&pfvf->mbox.lock); 991 req = otx2_mbox_alloc_msg_cgx_get_aux_link_info(&pfvf->mbox); 992 if (!req) { 993 mutex_unlock(&pfvf->mbox.lock); 994 return ERR_PTR(-ENOMEM); 995 } 996 997 err = otx2_sync_mbox_msg(&pfvf->mbox); 998 if (!err) { 999 rsp = (struct cgx_fw_data *) 1000 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1001 } else { 1002 rsp = ERR_PTR(err); 1003 } 1004 1005 mutex_unlock(&pfvf->mbox.lock); 1006 return rsp; 1007 } 1008 1009 static int otx2_get_fecparam(struct net_device *netdev, 1010 struct ethtool_fecparam *fecparam) 1011 { 1012 struct otx2_nic *pfvf = netdev_priv(netdev); 1013 struct cgx_fw_data *rsp; 1014 const int fec[] = { 1015 ETHTOOL_FEC_OFF, 1016 ETHTOOL_FEC_BASER, 1017 ETHTOOL_FEC_RS, 1018 ETHTOOL_FEC_BASER | ETHTOOL_FEC_RS}; 1019 #define FEC_MAX_INDEX 4 1020 if (pfvf->linfo.fec < FEC_MAX_INDEX) 1021 fecparam->active_fec = fec[pfvf->linfo.fec]; 1022 1023 rsp = otx2_get_fwdata(pfvf); 1024 if (IS_ERR(rsp)) 1025 return PTR_ERR(rsp); 1026 1027 if (rsp->fwdata.supported_fec < FEC_MAX_INDEX) { 1028 if (!rsp->fwdata.supported_fec) 1029 fecparam->fec = ETHTOOL_FEC_NONE; 1030 else 1031 fecparam->fec = fec[rsp->fwdata.supported_fec]; 1032 } 1033 return 0; 1034 } 1035 1036 static int otx2_set_fecparam(struct net_device *netdev, 1037 struct ethtool_fecparam *fecparam) 1038 { 1039 struct otx2_nic *pfvf = netdev_priv(netdev); 1040 struct mbox *mbox = &pfvf->mbox; 1041 struct fec_mode *req, *rsp; 1042 int err = 0, fec = 0; 1043 1044 switch (fecparam->fec) { 1045 /* Firmware does not support AUTO mode consider it as FEC_OFF */ 1046 case ETHTOOL_FEC_OFF: 1047 case ETHTOOL_FEC_AUTO: 1048 fec = OTX2_FEC_OFF; 1049 break; 1050 case ETHTOOL_FEC_RS: 1051 fec = OTX2_FEC_RS; 1052 break; 1053 case ETHTOOL_FEC_BASER: 1054 fec = OTX2_FEC_BASER; 1055 break; 1056 default: 1057 netdev_warn(pfvf->netdev, "Unsupported FEC mode: %d", 1058 fecparam->fec); 1059 return -EINVAL; 1060 } 1061 1062 if (fec == pfvf->linfo.fec) 1063 return 0; 1064 1065 mutex_lock(&mbox->lock); 1066 req = otx2_mbox_alloc_msg_cgx_set_fec_param(&pfvf->mbox); 1067 if (!req) { 1068 err = -ENOMEM; 1069 goto end; 1070 } 1071 req->fec = fec; 1072 err = otx2_sync_mbox_msg(&pfvf->mbox); 1073 if (err) 1074 goto end; 1075 1076 rsp = (struct fec_mode *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 1077 0, &req->hdr); 1078 if (rsp->fec >= 0) 1079 pfvf->linfo.fec = rsp->fec; 1080 else 1081 err = rsp->fec; 1082 end: 1083 mutex_unlock(&mbox->lock); 1084 return err; 1085 } 1086 1087 static void otx2_get_fec_info(u64 index, int req_mode, 1088 struct ethtool_link_ksettings *link_ksettings) 1089 { 1090 __ETHTOOL_DECLARE_LINK_MODE_MASK(otx2_fec_modes) = { 0, }; 1091 1092 switch (index) { 1093 case OTX2_FEC_NONE: 1094 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1095 otx2_fec_modes); 1096 break; 1097 case OTX2_FEC_BASER: 1098 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1099 otx2_fec_modes); 1100 break; 1101 case OTX2_FEC_RS: 1102 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1103 otx2_fec_modes); 1104 break; 1105 case OTX2_FEC_BASER | OTX2_FEC_RS: 1106 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1107 otx2_fec_modes); 1108 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1109 otx2_fec_modes); 1110 break; 1111 } 1112 1113 /* Add fec modes to existing modes */ 1114 if (req_mode == OTX2_MODE_ADVERTISED) 1115 linkmode_or(link_ksettings->link_modes.advertising, 1116 link_ksettings->link_modes.advertising, 1117 otx2_fec_modes); 1118 else 1119 linkmode_or(link_ksettings->link_modes.supported, 1120 link_ksettings->link_modes.supported, 1121 otx2_fec_modes); 1122 } 1123 1124 static void otx2_get_link_mode_info(u64 link_mode_bmap, 1125 bool req_mode, 1126 struct ethtool_link_ksettings 1127 *link_ksettings) 1128 { 1129 __ETHTOOL_DECLARE_LINK_MODE_MASK(otx2_link_modes) = { 0, }; 1130 const int otx2_sgmii_features[6] = { 1131 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 1132 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 1133 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1134 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1135 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1136 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1137 }; 1138 /* CGX link modes to Ethtool link mode mapping */ 1139 const int cgx_link_mode[27] = { 1140 0, /* SGMII Mode */ 1141 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1142 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1143 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1144 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1145 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1146 0, 1147 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1148 0, 1149 0, 1150 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1151 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1152 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1153 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1154 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1155 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1156 0, 1157 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 1158 0, 1159 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1160 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 1161 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 1162 0, 1163 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1164 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1165 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1166 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT 1167 }; 1168 u8 bit; 1169 1170 for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, 27) { 1171 /* SGMII mode is set */ 1172 if (bit == 0) 1173 linkmode_set_bit_array(otx2_sgmii_features, 1174 ARRAY_SIZE(otx2_sgmii_features), 1175 otx2_link_modes); 1176 else 1177 linkmode_set_bit(cgx_link_mode[bit], otx2_link_modes); 1178 } 1179 1180 if (req_mode == OTX2_MODE_ADVERTISED) 1181 linkmode_copy(link_ksettings->link_modes.advertising, 1182 otx2_link_modes); 1183 else 1184 linkmode_copy(link_ksettings->link_modes.supported, 1185 otx2_link_modes); 1186 } 1187 1188 static int otx2_get_link_ksettings(struct net_device *netdev, 1189 struct ethtool_link_ksettings *cmd) 1190 { 1191 struct otx2_nic *pfvf = netdev_priv(netdev); 1192 struct cgx_fw_data *rsp = NULL; 1193 1194 cmd->base.duplex = pfvf->linfo.full_duplex; 1195 cmd->base.speed = pfvf->linfo.speed; 1196 cmd->base.autoneg = pfvf->linfo.an; 1197 1198 rsp = otx2_get_fwdata(pfvf); 1199 if (IS_ERR(rsp)) 1200 return PTR_ERR(rsp); 1201 1202 if (rsp->fwdata.supported_an) 1203 ethtool_link_ksettings_add_link_mode(cmd, 1204 supported, 1205 Autoneg); 1206 1207 otx2_get_link_mode_info(rsp->fwdata.advertised_link_modes, 1208 OTX2_MODE_ADVERTISED, cmd); 1209 otx2_get_fec_info(rsp->fwdata.advertised_fec, 1210 OTX2_MODE_ADVERTISED, cmd); 1211 otx2_get_link_mode_info(rsp->fwdata.supported_link_modes, 1212 OTX2_MODE_SUPPORTED, cmd); 1213 otx2_get_fec_info(rsp->fwdata.supported_fec, 1214 OTX2_MODE_SUPPORTED, cmd); 1215 return 0; 1216 } 1217 1218 static void otx2_get_advertised_mode(const struct ethtool_link_ksettings *cmd, 1219 u64 *mode) 1220 { 1221 u32 bit_pos; 1222 1223 /* Firmware does not support requesting multiple advertised modes 1224 * return first set bit 1225 */ 1226 bit_pos = find_first_bit(cmd->link_modes.advertising, 1227 __ETHTOOL_LINK_MODE_MASK_NBITS); 1228 if (bit_pos != __ETHTOOL_LINK_MODE_MASK_NBITS) 1229 *mode = bit_pos; 1230 } 1231 1232 static int otx2_set_link_ksettings(struct net_device *netdev, 1233 const struct ethtool_link_ksettings *cmd) 1234 { 1235 struct otx2_nic *pf = netdev_priv(netdev); 1236 struct ethtool_link_ksettings cur_ks; 1237 struct cgx_set_link_mode_req *req; 1238 struct mbox *mbox = &pf->mbox; 1239 int err = 0; 1240 1241 memset(&cur_ks, 0, sizeof(struct ethtool_link_ksettings)); 1242 1243 if (!ethtool_validate_speed(cmd->base.speed) || 1244 !ethtool_validate_duplex(cmd->base.duplex)) 1245 return -EINVAL; 1246 1247 if (cmd->base.autoneg != AUTONEG_ENABLE && 1248 cmd->base.autoneg != AUTONEG_DISABLE) 1249 return -EINVAL; 1250 1251 otx2_get_link_ksettings(netdev, &cur_ks); 1252 1253 /* Check requested modes against supported modes by hardware */ 1254 if (!linkmode_subset(cmd->link_modes.advertising, 1255 cur_ks.link_modes.supported)) 1256 return -EINVAL; 1257 1258 mutex_lock(&mbox->lock); 1259 req = otx2_mbox_alloc_msg_cgx_set_link_mode(&pf->mbox); 1260 if (!req) { 1261 err = -ENOMEM; 1262 goto end; 1263 } 1264 1265 req->args.speed = cmd->base.speed; 1266 /* firmware expects 1 for half duplex and 0 for full duplex 1267 * hence inverting 1268 */ 1269 req->args.duplex = cmd->base.duplex ^ 0x1; 1270 req->args.an = cmd->base.autoneg; 1271 otx2_get_advertised_mode(cmd, &req->args.mode); 1272 1273 err = otx2_sync_mbox_msg(&pf->mbox); 1274 end: 1275 mutex_unlock(&mbox->lock); 1276 return err; 1277 } 1278 1279 static void otx2_get_fec_stats(struct net_device *netdev, 1280 struct ethtool_fec_stats *fec_stats) 1281 { 1282 struct otx2_nic *pfvf = netdev_priv(netdev); 1283 struct cgx_fw_data *rsp; 1284 1285 otx2_update_lmac_fec_stats(pfvf); 1286 1287 /* Report MAC FEC stats */ 1288 fec_stats->corrected_blocks.total = pfvf->hw.cgx_fec_corr_blks; 1289 fec_stats->uncorrectable_blocks.total = pfvf->hw.cgx_fec_uncorr_blks; 1290 1291 rsp = otx2_get_fwdata(pfvf); 1292 if (!IS_ERR(rsp) && rsp->fwdata.phy.misc.has_fec_stats && 1293 !otx2_get_phy_fec_stats(pfvf)) { 1294 /* Fetch fwdata again because it's been recently populated with 1295 * latest PHY FEC stats. 1296 */ 1297 rsp = otx2_get_fwdata(pfvf); 1298 if (!IS_ERR(rsp)) { 1299 struct fec_stats_s *p = &rsp->fwdata.phy.fec_stats; 1300 1301 if (pfvf->linfo.fec == OTX2_FEC_BASER) { 1302 fec_stats->corrected_blocks.total = p->brfec_corr_blks; 1303 fec_stats->uncorrectable_blocks.total = p->brfec_uncorr_blks; 1304 } else { 1305 fec_stats->corrected_blocks.total = p->rsfec_corr_cws; 1306 fec_stats->uncorrectable_blocks.total = p->rsfec_uncorr_cws; 1307 } 1308 } 1309 } 1310 } 1311 1312 static const struct ethtool_ops otx2_ethtool_ops = { 1313 .cap_rss_ctx_supported = true, 1314 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1315 ETHTOOL_COALESCE_MAX_FRAMES | 1316 ETHTOOL_COALESCE_USE_ADAPTIVE, 1317 .supported_ring_params = ETHTOOL_RING_USE_RX_BUF_LEN | 1318 ETHTOOL_RING_USE_CQE_SIZE, 1319 .get_link = otx2_get_link, 1320 .get_drvinfo = otx2_get_drvinfo, 1321 .get_strings = otx2_get_strings, 1322 .get_ethtool_stats = otx2_get_ethtool_stats, 1323 .get_sset_count = otx2_get_sset_count, 1324 .set_channels = otx2_set_channels, 1325 .get_channels = otx2_get_channels, 1326 .get_ringparam = otx2_get_ringparam, 1327 .set_ringparam = otx2_set_ringparam, 1328 .get_coalesce = otx2_get_coalesce, 1329 .set_coalesce = otx2_set_coalesce, 1330 .get_rxnfc = otx2_get_rxnfc, 1331 .set_rxnfc = otx2_set_rxnfc, 1332 .get_rxfh_key_size = otx2_get_rxfh_key_size, 1333 .get_rxfh_indir_size = otx2_get_rxfh_indir_size, 1334 .get_rxfh = otx2_get_rxfh, 1335 .set_rxfh = otx2_set_rxfh, 1336 .get_msglevel = otx2_get_msglevel, 1337 .set_msglevel = otx2_set_msglevel, 1338 .get_pauseparam = otx2_get_pauseparam, 1339 .set_pauseparam = otx2_set_pauseparam, 1340 .get_ts_info = otx2_get_ts_info, 1341 .get_fec_stats = otx2_get_fec_stats, 1342 .get_fecparam = otx2_get_fecparam, 1343 .set_fecparam = otx2_set_fecparam, 1344 .get_link_ksettings = otx2_get_link_ksettings, 1345 .set_link_ksettings = otx2_set_link_ksettings, 1346 }; 1347 1348 void otx2_set_ethtool_ops(struct net_device *netdev) 1349 { 1350 netdev->ethtool_ops = &otx2_ethtool_ops; 1351 } 1352 1353 /* VF's ethtool APIs */ 1354 static void otx2vf_get_drvinfo(struct net_device *netdev, 1355 struct ethtool_drvinfo *info) 1356 { 1357 struct otx2_nic *vf = netdev_priv(netdev); 1358 1359 strscpy(info->driver, DRV_VF_NAME, sizeof(info->driver)); 1360 strscpy(info->bus_info, pci_name(vf->pdev), sizeof(info->bus_info)); 1361 } 1362 1363 static void otx2vf_get_strings(struct net_device *netdev, u32 sset, u8 *data) 1364 { 1365 struct otx2_nic *vf = netdev_priv(netdev); 1366 int stats; 1367 1368 if (sset != ETH_SS_STATS) 1369 return; 1370 1371 for (stats = 0; stats < otx2_n_dev_stats; stats++) { 1372 memcpy(data, otx2_dev_stats[stats].name, ETH_GSTRING_LEN); 1373 data += ETH_GSTRING_LEN; 1374 } 1375 1376 for (stats = 0; stats < otx2_n_drv_stats; stats++) { 1377 memcpy(data, otx2_drv_stats[stats].name, ETH_GSTRING_LEN); 1378 data += ETH_GSTRING_LEN; 1379 } 1380 1381 otx2_get_qset_strings(vf, &data, 0); 1382 1383 strcpy(data, "reset_count"); 1384 data += ETH_GSTRING_LEN; 1385 } 1386 1387 static void otx2vf_get_ethtool_stats(struct net_device *netdev, 1388 struct ethtool_stats *stats, u64 *data) 1389 { 1390 struct otx2_nic *vf = netdev_priv(netdev); 1391 int stat; 1392 1393 otx2_get_dev_stats(vf); 1394 for (stat = 0; stat < otx2_n_dev_stats; stat++) 1395 *(data++) = ((u64 *)&vf->hw.dev_stats) 1396 [otx2_dev_stats[stat].index]; 1397 1398 for (stat = 0; stat < otx2_n_drv_stats; stat++) 1399 *(data++) = atomic_read(&((atomic_t *)&vf->hw.drv_stats) 1400 [otx2_drv_stats[stat].index]); 1401 1402 otx2_get_qset_stats(vf, stats, &data); 1403 *(data++) = vf->reset_count; 1404 } 1405 1406 static int otx2vf_get_sset_count(struct net_device *netdev, int sset) 1407 { 1408 struct otx2_nic *vf = netdev_priv(netdev); 1409 int qstats_count; 1410 1411 if (sset != ETH_SS_STATS) 1412 return -EINVAL; 1413 1414 qstats_count = otx2_n_queue_stats * 1415 (vf->hw.rx_queues + otx2_get_total_tx_queues(vf)); 1416 1417 return otx2_n_dev_stats + otx2_n_drv_stats + qstats_count + 1; 1418 } 1419 1420 static int otx2vf_get_link_ksettings(struct net_device *netdev, 1421 struct ethtool_link_ksettings *cmd) 1422 { 1423 struct otx2_nic *pfvf = netdev_priv(netdev); 1424 1425 if (is_otx2_lbkvf(pfvf->pdev)) { 1426 cmd->base.duplex = DUPLEX_FULL; 1427 cmd->base.speed = SPEED_100000; 1428 } else { 1429 return otx2_get_link_ksettings(netdev, cmd); 1430 } 1431 return 0; 1432 } 1433 1434 static const struct ethtool_ops otx2vf_ethtool_ops = { 1435 .cap_rss_ctx_supported = true, 1436 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1437 ETHTOOL_COALESCE_MAX_FRAMES | 1438 ETHTOOL_COALESCE_USE_ADAPTIVE, 1439 .supported_ring_params = ETHTOOL_RING_USE_RX_BUF_LEN | 1440 ETHTOOL_RING_USE_CQE_SIZE, 1441 .get_link = otx2_get_link, 1442 .get_drvinfo = otx2vf_get_drvinfo, 1443 .get_strings = otx2vf_get_strings, 1444 .get_ethtool_stats = otx2vf_get_ethtool_stats, 1445 .get_sset_count = otx2vf_get_sset_count, 1446 .set_channels = otx2_set_channels, 1447 .get_channels = otx2_get_channels, 1448 .get_rxnfc = otx2_get_rxnfc, 1449 .set_rxnfc = otx2_set_rxnfc, 1450 .get_rxfh_key_size = otx2_get_rxfh_key_size, 1451 .get_rxfh_indir_size = otx2_get_rxfh_indir_size, 1452 .get_rxfh = otx2_get_rxfh, 1453 .set_rxfh = otx2_set_rxfh, 1454 .get_ringparam = otx2_get_ringparam, 1455 .set_ringparam = otx2_set_ringparam, 1456 .get_coalesce = otx2_get_coalesce, 1457 .set_coalesce = otx2_set_coalesce, 1458 .get_msglevel = otx2_get_msglevel, 1459 .set_msglevel = otx2_set_msglevel, 1460 .get_pauseparam = otx2_get_pauseparam, 1461 .set_pauseparam = otx2_set_pauseparam, 1462 .get_link_ksettings = otx2vf_get_link_ksettings, 1463 .get_ts_info = otx2_get_ts_info, 1464 }; 1465 1466 void otx2vf_set_ethtool_ops(struct net_device *netdev) 1467 { 1468 netdev->ethtool_ops = &otx2vf_ethtool_ops; 1469 } 1470 EXPORT_SYMBOL(otx2vf_set_ethtool_ops); 1471