1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_COMMON_H 9 #define OTX2_COMMON_H 10 11 #include <linux/ethtool.h> 12 #include <linux/pci.h> 13 #include <linux/iommu.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/ptp_clock_kernel.h> 16 #include <linux/timecounter.h> 17 #include <linux/soc/marvell/octeontx2/asm.h> 18 #include <net/macsec.h> 19 #include <net/pkt_cls.h> 20 #include <net/devlink.h> 21 #include <linux/time64.h> 22 #include <linux/dim.h> 23 #include <uapi/linux/if_macsec.h> 24 #include <net/page_pool/helpers.h> 25 26 #include <mbox.h> 27 #include <npc.h> 28 #include "otx2_reg.h" 29 #include "otx2_txrx.h" 30 #include "otx2_devlink.h" 31 #include <rvu.h> 32 #include <rvu_trace.h> 33 #include "qos.h" 34 #include "rep.h" 35 #include "cn10k_ipsec.h" 36 #include "cn20k.h" 37 38 /* IPv4 flag more fragment bit */ 39 #define IPV4_FLAG_MORE 0x20 40 41 /* PCI device IDs */ 42 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 43 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 44 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 45 46 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 47 #define PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF 0xB900 48 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00 49 50 #define PCI_DEVID_OCTEONTX2_SDP_REP 0xA0F7 51 52 /* PCI BAR nos */ 53 #define PCI_CFG_REG_BAR_NUM 2 54 #define PCI_MBOX_BAR_NUM 4 55 56 #define NAME_SIZE 32 57 58 #ifdef CONFIG_DCB 59 /* Max priority supported for PFC */ 60 #define NIX_PF_PFC_PRIO_MAX 8 61 #endif 62 63 /* Number of segments per SG structure */ 64 #define MAX_SEGS_PER_SG 3 65 66 irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq); 67 irqreturn_t cn20k_pfaf_mbox_intr_handler(int irq, void *pf_irq); 68 irqreturn_t cn20k_vfaf_mbox_intr_handler(int irq, void *vf_irq); 69 irqreturn_t cn20k_pfvf_mbox_intr_handler(int irq, void *pf_irq); 70 irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq); 71 72 enum arua_mapped_qtypes { 73 AURA_NIX_RQ, 74 AURA_NIX_SQ, 75 }; 76 77 /* NIX LF interrupts range*/ 78 #define NIX_LF_QINT_VEC_START 0x00 79 #define NIX_LF_CINT_VEC_START 0x40 80 #define NIX_LF_GINT_VEC 0x80 81 #define NIX_LF_ERR_VEC 0x81 82 #define NIX_LF_POISON_VEC 0x82 83 84 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 85 #define SEND_CQ_SKID 2000 86 87 #define OTX2_GET_RX_STATS(reg) \ 88 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 89 #define OTX2_GET_TX_STATS(reg) \ 90 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 91 92 struct otx2_lmt_info { 93 u64 lmt_addr; 94 u16 lmt_id; 95 }; 96 97 struct otx2_rss_info { 98 u8 enable; 99 u32 flowkey_cfg; 100 u16 rss_size; 101 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 102 u8 key[RSS_HASH_KEY_SIZE]; 103 u32 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 104 }; 105 106 /* NIX (or NPC) RX errors */ 107 enum otx2_errlvl { 108 NPC_ERRLVL_RE, 109 NPC_ERRLVL_LID_LA, 110 NPC_ERRLVL_LID_LB, 111 NPC_ERRLVL_LID_LC, 112 NPC_ERRLVL_LID_LD, 113 NPC_ERRLVL_LID_LE, 114 NPC_ERRLVL_LID_LF, 115 NPC_ERRLVL_LID_LG, 116 NPC_ERRLVL_LID_LH, 117 NPC_ERRLVL_NIX = 0x0F, 118 }; 119 120 enum otx2_errcodes_re { 121 /* NPC_ERRLVL_RE errcodes */ 122 ERRCODE_FCS = 0x7, 123 ERRCODE_FCS_RCV = 0x8, 124 ERRCODE_UNDERSIZE = 0x10, 125 ERRCODE_OVERSIZE = 0x11, 126 ERRCODE_OL2_LEN_MISMATCH = 0x12, 127 /* NPC_ERRLVL_NIX errcodes */ 128 ERRCODE_OL3_LEN = 0x10, 129 ERRCODE_OL4_LEN = 0x11, 130 ERRCODE_OL4_CSUM = 0x12, 131 ERRCODE_IL3_LEN = 0x20, 132 ERRCODE_IL4_LEN = 0x21, 133 ERRCODE_IL4_CSUM = 0x22, 134 }; 135 136 enum otx2_xdp_action { 137 OTX2_XDP_TX = BIT(0), 138 OTX2_XDP_REDIRECT = BIT(1), 139 OTX2_AF_XDP_FRAME = BIT(2), 140 }; 141 142 struct otx2_dev_stats { 143 u64 rx_bytes; 144 u64 rx_frames; 145 u64 rx_ucast_frames; 146 u64 rx_bcast_frames; 147 u64 rx_mcast_frames; 148 u64 rx_drops; 149 150 u64 tx_bytes; 151 u64 tx_frames; 152 u64 tx_ucast_frames; 153 u64 tx_bcast_frames; 154 u64 tx_mcast_frames; 155 u64 tx_drops; 156 }; 157 158 /* Driver counted stats */ 159 struct otx2_drv_stats { 160 atomic_t rx_fcs_errs; 161 atomic_t rx_oversize_errs; 162 atomic_t rx_undersize_errs; 163 atomic_t rx_csum_errs; 164 atomic_t rx_len_errs; 165 atomic_t rx_other_errs; 166 }; 167 168 struct mbox { 169 struct otx2_mbox mbox; 170 struct work_struct mbox_wrk; 171 struct otx2_mbox mbox_up; 172 struct work_struct mbox_up_wrk; 173 struct otx2_nic *pfvf; 174 void *bbuf_base; /* Bounce buffer for mbox memory */ 175 struct mutex lock; /* serialize mailbox access */ 176 int num_msgs; /* mbox number of messages */ 177 int up_num_msgs; /* mbox_up number of messages */ 178 }; 179 180 /* Egress rate limiting definitions */ 181 #define MAX_BURST_EXPONENT 0x0FULL 182 #define MAX_BURST_MANTISSA 0xFFULL 183 #define MAX_BURST_SIZE 130816ULL 184 #define MAX_RATE_DIVIDER_EXPONENT 12ULL 185 #define MAX_RATE_EXPONENT 0x0FULL 186 #define MAX_RATE_MANTISSA 0xFFULL 187 188 /* Bitfields in NIX_TLX_PIR register */ 189 #define TLX_RATE_MANTISSA GENMASK_ULL(8, 1) 190 #define TLX_RATE_EXPONENT GENMASK_ULL(12, 9) 191 #define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13) 192 #define TLX_BURST_MANTISSA GENMASK_ULL(36, 29) 193 #define TLX_BURST_EXPONENT GENMASK_ULL(40, 37) 194 195 struct otx2_hw { 196 struct pci_dev *pdev; 197 struct otx2_rss_info rss_info; 198 u16 rx_queues; 199 u16 tx_queues; 200 u16 xdp_queues; 201 u16 tc_tx_queues; 202 u16 non_qos_queues; /* tx queues plus xdp queues */ 203 u16 max_queues; 204 u16 pool_cnt; 205 u16 rqpool_cnt; 206 u16 sqpool_cnt; 207 208 #define OTX2_DEFAULT_RBUF_LEN 2048 209 u16 rbuf_len; 210 u32 xqe_size; 211 212 /* NPA */ 213 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 214 u32 stack_pg_bytes; /* Size of stack page */ 215 u16 sqb_size; 216 217 /* NIX */ 218 u8 txschq_link_cfg_lvl; 219 u8 txschq_cnt[NIX_TXSCH_LVL_CNT]; 220 u8 txschq_aggr_lvl_rr_prio; 221 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 222 u16 matchall_ipolicer; 223 u32 dwrr_mtu; 224 u32 max_mtu; 225 u8 smq_link_type; 226 227 /* HW settings, coalescing etc */ 228 u16 rx_chan_base; 229 u16 tx_chan_base; 230 u8 rx_chan_cnt; 231 u8 tx_chan_cnt; 232 u16 cq_qcount_wait; 233 u16 cq_ecount_wait; 234 u16 rq_skid; 235 u8 cq_time_wait; 236 237 /* Segmentation */ 238 u8 lso_tsov4_idx; 239 u8 lso_tsov6_idx; 240 u8 lso_udpv4_idx; 241 u8 lso_udpv6_idx; 242 243 /* RSS */ 244 u8 flowkey_alg_idx; 245 246 /* MSI-X */ 247 u8 cint_cnt; /* CQ interrupt count */ 248 u16 npa_msixoff; /* Offset of NPA vectors */ 249 u16 nix_msixoff; /* Offset of NIX vectors */ 250 char *irq_name; 251 cpumask_var_t *affinity_mask; 252 struct pf_irq_data *pfvf_irq_devid[4]; 253 254 /* Stats */ 255 struct otx2_dev_stats dev_stats; 256 struct otx2_drv_stats drv_stats; 257 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 258 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 259 u64 cgx_fec_corr_blks; 260 u64 cgx_fec_uncorr_blks; 261 u8 cgx_links; /* No. of CGX links present in HW */ 262 u8 lbk_links; /* No. of LBK links present in HW */ 263 u8 tx_link; /* Transmit channel link number */ 264 #define HW_TSO 0 265 #define CN10K_MBOX 1 266 #define CN10K_LMTST 2 267 #define CN10K_RPM 3 268 #define CN10K_PTP_ONESTEP 4 269 #define CN10K_HW_MACSEC 5 270 #define QOS_CIR_PIR_SUPPORT 6 271 unsigned long cap_flag; 272 273 #define LMT_LINE_SIZE 128 274 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 275 u64 *lmt_base; 276 struct otx2_lmt_info __percpu *lmt_info; 277 }; 278 279 enum vfperm { 280 OTX2_RESET_VF_PERM, 281 OTX2_TRUSTED_VF, 282 }; 283 284 struct otx2_vf_config { 285 struct otx2_nic *pf; 286 struct delayed_work link_event_work; 287 bool intf_down; /* interface was either configured or not */ 288 u8 mac[ETH_ALEN]; 289 u16 vlan; 290 int tx_vtag_idx; 291 bool trusted; 292 }; 293 294 struct flr_work { 295 struct work_struct work; 296 struct otx2_nic *pf; 297 }; 298 299 struct refill_work { 300 struct delayed_work pool_refill_work; 301 struct otx2_nic *pf; 302 struct napi_struct *napi; 303 }; 304 305 /* PTPv2 originTimestamp structure */ 306 struct ptpv2_tstamp { 307 __be16 seconds_msb; /* 16 bits + */ 308 __be32 seconds_lsb; /* 32 bits = 48 bits*/ 309 __be32 nanoseconds; 310 } __packed; 311 312 struct otx2_ptp { 313 struct ptp_clock_info ptp_info; 314 struct ptp_clock *ptp_clock; 315 struct otx2_nic *nic; 316 317 struct cyclecounter cycle_counter; 318 struct timecounter time_counter; 319 320 struct delayed_work extts_work; 321 u64 last_extts; 322 u64 thresh; 323 324 struct ptp_pin_desc extts_config; 325 u64 (*convert_rx_ptp_tstmp)(u64 timestamp); 326 u64 (*convert_tx_ptp_tstmp)(u64 timestamp); 327 u64 (*ptp_tstamp2nsec)(const struct timecounter *time_counter, u64 timestamp); 328 struct delayed_work synctstamp_work; 329 u64 tstamp; 330 u32 base_ns; 331 }; 332 333 #define OTX2_HW_TIMESTAMP_LEN 8 334 335 struct otx2_mac_table { 336 u8 addr[ETH_ALEN]; 337 u16 mcam_entry; 338 bool inuse; 339 }; 340 341 struct otx2_flow_config { 342 u16 *flow_ent; 343 u16 *def_ent; 344 u16 nr_flows; 345 #define OTX2_DEFAULT_FLOWCOUNT 16 346 #define OTX2_DEFAULT_UNICAST_FLOWS 4 347 #define OTX2_MAX_VLAN_FLOWS 1 348 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 349 u16 unicast_offset; 350 u16 rx_vlan_offset; 351 u16 vf_vlan_offset; 352 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 353 #define OTX2_VF_VLAN_RX_INDEX 0 354 #define OTX2_VF_VLAN_TX_INDEX 1 355 u32 *bmap_to_dmacindex; 356 unsigned long *dmacflt_bmap; 357 struct list_head flow_list; 358 u32 dmacflt_max_flows; 359 u16 max_flows; 360 refcount_t mark_flows; 361 struct list_head flow_list_tc; 362 u8 ucast_flt_cnt; 363 bool ntuple; 364 u16 ntuple_cnt; 365 }; 366 367 struct dev_hw_ops { 368 int (*sq_aq_init)(void *dev, u16 qidx, u8 chan_offset, 369 u16 sqb_aura); 370 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 371 int size, int qidx); 372 int (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 373 void (*aura_freeptr)(void *dev, int aura, u64 buf); 374 irqreturn_t (*pfaf_mbox_intr_handler)(int irq, void *pf_irq); 375 irqreturn_t (*vfaf_mbox_intr_handler)(int irq, void *pf_irq); 376 irqreturn_t (*pfvf_mbox_intr_handler)(int irq, void *pf_irq); 377 }; 378 379 #define CN10K_MCS_SA_PER_SC 4 380 381 /* Stats which need to be accumulated in software because 382 * of shared counters in hardware. 383 */ 384 struct cn10k_txsc_stats { 385 u64 InPktsUntagged; 386 u64 InPktsNoTag; 387 u64 InPktsBadTag; 388 u64 InPktsUnknownSCI; 389 u64 InPktsNoSCI; 390 u64 InPktsOverrun; 391 }; 392 393 struct cn10k_rxsc_stats { 394 u64 InOctetsValidated; 395 u64 InOctetsDecrypted; 396 u64 InPktsUnchecked; 397 u64 InPktsDelayed; 398 u64 InPktsOK; 399 u64 InPktsInvalid; 400 u64 InPktsLate; 401 u64 InPktsNotValid; 402 u64 InPktsNotUsingSA; 403 u64 InPktsUnusedSA; 404 }; 405 406 struct cn10k_mcs_txsc { 407 struct macsec_secy *sw_secy; 408 struct cn10k_txsc_stats stats; 409 struct list_head entry; 410 enum macsec_validation_type last_validate_frames; 411 bool last_replay_protect; 412 u16 hw_secy_id_tx; 413 u16 hw_secy_id_rx; 414 u16 hw_flow_id; 415 u16 hw_sc_id; 416 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 417 u8 sa_bmap; 418 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 419 u8 encoding_sa; 420 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 421 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 422 bool vlan_dev; /* macsec running on VLAN ? */ 423 }; 424 425 struct cn10k_mcs_rxsc { 426 struct macsec_secy *sw_secy; 427 struct macsec_rx_sc *sw_rxsc; 428 struct cn10k_rxsc_stats stats; 429 struct list_head entry; 430 u16 hw_flow_id; 431 u16 hw_sc_id; 432 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 433 u8 sa_bmap; 434 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 435 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 436 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 437 }; 438 439 struct cn10k_mcs_cfg { 440 struct list_head txsc_list; 441 struct list_head rxsc_list; 442 }; 443 444 struct pf_irq_data { 445 u64 intr_status; 446 void (*pf_queue_work_hdlr)(struct mbox *mb, struct workqueue_struct *mw, 447 int first, int mdevs, u64 intr); 448 struct otx2_nic *pf; 449 int vec_num; 450 int start; 451 int mdevs; 452 }; 453 454 struct otx2_nic { 455 void __iomem *reg_base; 456 struct net_device *netdev; 457 struct dev_hw_ops *hw_ops; 458 void *iommu_domain; 459 u16 tx_max_pktlen; 460 u16 rbsize; /* Receive buffer size */ 461 462 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 463 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 464 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 465 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 466 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 467 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 468 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 469 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 470 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 471 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 472 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 473 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 474 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 475 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 476 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 477 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15) 478 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) 479 #define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17) 480 #define OTX2_FLAG_REP_MODE_ENABLED BIT_ULL(18) 481 #define OTX2_FLAG_PORT_UP BIT_ULL(19) 482 #define OTX2_FLAG_IPSEC_OFFLOAD_ENABLED BIT_ULL(20) 483 u64 flags; 484 u64 *cq_op_addr; 485 486 struct bpf_prog *xdp_prog; 487 struct otx2_qset qset; 488 struct otx2_hw hw; 489 struct pci_dev *pdev; 490 struct device *dev; 491 492 /* Mbox */ 493 struct mbox mbox; 494 struct mbox *mbox_pfvf; 495 struct workqueue_struct *mbox_wq; 496 struct workqueue_struct *mbox_pfvf_wq; 497 struct qmem *pfvf_mbox_addr; 498 499 u8 total_vfs; 500 u16 pcifunc; /* RVU PF_FUNC */ 501 u16 bpid[NIX_MAX_BPID_CHAN]; 502 struct otx2_vf_config *vf_configs; 503 struct cgx_link_user_info linfo; 504 505 /* NPC MCAM */ 506 struct otx2_flow_config *flow_cfg; 507 struct otx2_mac_table *mac_table; 508 509 u64 reset_count; 510 struct work_struct reset_task; 511 struct workqueue_struct *flr_wq; 512 struct flr_work *flr_wrk; 513 struct refill_work *refill_wrk; 514 struct workqueue_struct *otx2_wq; 515 struct work_struct rx_mode_work; 516 517 /* Ethtool stuff */ 518 u32 msg_enable; 519 520 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 521 int nix_blkaddr; 522 /* LMTST Lines info */ 523 struct qmem *dync_lmt; 524 u16 tot_lmt_lines; 525 u16 npa_lmt_lines; 526 u32 nix_lmt_size; 527 528 struct otx2_ptp *ptp; 529 struct hwtstamp_config tstamp; 530 531 unsigned long rq_bmap; 532 533 /* Devlink */ 534 struct otx2_devlink *dl; 535 /* PFC */ 536 u8 pfc_en; 537 #ifdef CONFIG_DCB 538 u8 *queue_to_pfc_map; 539 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 540 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX]; 541 #endif 542 /* qos */ 543 struct otx2_qos qos; 544 545 /* napi event count. It is needed for adaptive irq coalescing. */ 546 u32 napi_events; 547 548 #if IS_ENABLED(CONFIG_MACSEC) 549 struct cn10k_mcs_cfg *macsec_cfg; 550 #endif 551 552 #if IS_ENABLED(CONFIG_RVU_ESWITCH) 553 struct rep_dev **reps; 554 int rep_cnt; 555 u16 rep_pf_map[RVU_MAX_REP]; 556 u16 esw_mode; 557 #endif 558 559 /* Inline ipsec */ 560 struct cn10k_ipsec ipsec; 561 /* af_xdp zero-copy */ 562 unsigned long *af_xdp_zc_qidx; 563 }; 564 565 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 566 { 567 return (pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF) || 568 (pdev->device == PCI_DEVID_RVU_REP); 569 } 570 571 static inline bool is_96xx_A0(struct pci_dev *pdev) 572 { 573 return (pdev->revision == 0x00) && 574 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 575 } 576 577 static inline bool is_96xx_B0(struct pci_dev *pdev) 578 { 579 return (pdev->revision == 0x01) && 580 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 581 } 582 583 static inline bool is_otx2_sdp_rep(struct pci_dev *pdev) 584 { 585 return pdev->device == PCI_DEVID_OCTEONTX2_SDP_REP; 586 } 587 588 /* REVID for PCIe devices. 589 * Bits 0..1: minor pass, bit 3..2: major pass 590 * bits 7..4: midr id 591 */ 592 #define PCI_REVISION_ID_96XX 0x00 593 #define PCI_REVISION_ID_95XX 0x10 594 #define PCI_REVISION_ID_95XXN 0x20 595 #define PCI_REVISION_ID_98XX 0x30 596 #define PCI_REVISION_ID_95XXMM 0x40 597 #define PCI_REVISION_ID_95XXO 0xE0 598 599 static inline bool is_dev_otx2(struct pci_dev *pdev) 600 { 601 u8 midr = pdev->revision & 0xF0; 602 603 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 604 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 605 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 606 } 607 608 static inline bool is_dev_cn10kb(struct pci_dev *pdev) 609 { 610 return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF; 611 } 612 613 static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev) 614 { 615 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF && 616 (pdev->revision & 0xFF) == 0x54) 617 return true; 618 619 return false; 620 } 621 622 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 623 { 624 struct otx2_hw *hw = &pfvf->hw; 625 626 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 627 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 628 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 629 630 __set_bit(HW_TSO, &hw->cap_flag); 631 632 if (is_96xx_A0(pfvf->pdev)) { 633 __clear_bit(HW_TSO, &hw->cap_flag); 634 635 /* Time based irq coalescing is not supported */ 636 pfvf->hw.cq_qcount_wait = 0x0; 637 638 /* Due to HW issue previous silicons required minimum 639 * 600 unused CQE to avoid CQ overflow. 640 */ 641 pfvf->hw.rq_skid = 600; 642 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 643 } 644 if (is_96xx_B0(pfvf->pdev)) 645 __clear_bit(HW_TSO, &hw->cap_flag); 646 647 if (!is_dev_otx2(pfvf->pdev)) { 648 __set_bit(CN10K_MBOX, &hw->cap_flag); 649 __set_bit(CN10K_LMTST, &hw->cap_flag); 650 __set_bit(CN10K_RPM, &hw->cap_flag); 651 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag); 652 __set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag); 653 } 654 } 655 656 /* Register read/write APIs */ 657 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 658 { 659 u64 blkaddr; 660 661 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 662 case BLKTYPE_NIX: 663 blkaddr = nic->nix_blkaddr; 664 break; 665 case BLKTYPE_NPA: 666 blkaddr = BLKADDR_NPA; 667 break; 668 case BLKTYPE_CPT: 669 blkaddr = BLKADDR_CPT0; 670 break; 671 default: 672 blkaddr = BLKADDR_RVUM; 673 break; 674 } 675 676 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 677 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 678 679 return nic->reg_base + offset; 680 } 681 682 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 683 { 684 void __iomem *addr = otx2_get_regaddr(nic, offset); 685 686 writeq(val, addr); 687 } 688 689 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 690 { 691 void __iomem *addr = otx2_get_regaddr(nic, offset); 692 693 return readq(addr); 694 } 695 696 /* Mbox bounce buffer APIs */ 697 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 698 { 699 struct otx2_mbox *otx2_mbox; 700 struct otx2_mbox_dev *mdev; 701 702 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 703 if (!mbox->bbuf_base) 704 return -ENOMEM; 705 706 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 707 * prepare all mbox messages in bounce buffer instead of directly 708 * in hw mbox memory. 709 */ 710 otx2_mbox = &mbox->mbox; 711 mdev = &otx2_mbox->dev[0]; 712 mdev->mbase = mbox->bbuf_base; 713 714 otx2_mbox = &mbox->mbox_up; 715 mdev = &otx2_mbox->dev[0]; 716 mdev->mbase = mbox->bbuf_base; 717 return 0; 718 } 719 720 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 721 { 722 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 723 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 724 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 725 struct mbox_hdr *hdr; 726 u64 msg_size; 727 728 if (mdev->mbase == hw_mbase) 729 return; 730 731 hdr = hw_mbase + mbox->rx_start; 732 msg_size = hdr->msg_size; 733 734 if (msg_size > mbox->rx_size - msgs_offset) 735 msg_size = mbox->rx_size - msgs_offset; 736 737 /* Copy mbox messages from mbox memory to bounce buffer */ 738 memcpy(mdev->mbase + mbox->rx_start, 739 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 740 } 741 742 /* With the absence of API for 128-bit IO memory access for arm64, 743 * implement required operations at place. 744 */ 745 #if defined(CONFIG_ARM64) 746 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 747 { 748 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 749 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 750 } 751 752 static inline u64 otx2_atomic64_add(u64 incr, void __iomem *addr) 753 { 754 u64 __iomem *ptr = addr; 755 u64 result; 756 757 __asm__ volatile(".cpu generic+lse\n" 758 "ldadd %x[i], %x[r], [%[b]]" 759 : [r]"=r"(result), "+m"(*ptr) 760 : [i]"r"(incr), [b]"r"(ptr) 761 : "memory"); 762 return result; 763 } 764 765 #else 766 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 767 768 static inline u64 otx2_atomic64_add(u64 incr, void __iomem *addr) 769 { 770 return 0; 771 } 772 #endif 773 774 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 775 u64 *ptrs, u64 num_ptrs) 776 { 777 struct otx2_lmt_info *lmt_info; 778 u64 size = 0, count_eot = 0; 779 u64 tar_addr, val = 0; 780 781 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); 782 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 783 /* LMTID is same as AURA Id */ 784 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); 785 /* Set if [127:64] of last 128bit word has a valid pointer */ 786 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 787 /* Set AURA ID to free pointer */ 788 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 789 /* Target address for LMTST flush tells HW how many 128bit 790 * words are valid from NPA_LF_AURA_BATCH_FREE0. 791 * 792 * tar_addr[6:4] is LMTST size-1 in units of 128b. 793 */ 794 if (num_ptrs > 2) { 795 size = (sizeof(u64) * num_ptrs) / 16; 796 if (!count_eot) 797 size++; 798 tar_addr |= ((size - 1) & 0x7) << 4; 799 } 800 dma_wmb(); 801 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); 802 /* Perform LMTST flush */ 803 cn10k_lmt_flush(val, tar_addr); 804 } 805 806 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 807 { 808 struct otx2_nic *pfvf = dev; 809 u64 ptrs[2]; 810 811 ptrs[1] = buf; 812 get_cpu(); 813 /* Free only one buffer at time during init and teardown */ 814 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); 815 put_cpu(); 816 } 817 818 /* Alloc pointer from pool/aura */ 819 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 820 { 821 void __iomem *ptr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_ALLOCX(0)); 822 u64 incr = (u64)aura | BIT_ULL(63); 823 824 return otx2_atomic64_add(incr, ptr); 825 } 826 827 /* Free pointer to a pool/aura */ 828 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 829 { 830 struct otx2_nic *pfvf = dev; 831 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 832 833 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 834 } 835 836 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 837 { 838 if (type == AURA_NIX_SQ) 839 return pfvf->hw.rqpool_cnt + idx; 840 841 /* AURA_NIX_RQ */ 842 return idx; 843 } 844 845 /* Mbox APIs */ 846 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 847 { 848 int err; 849 850 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 851 return 0; 852 otx2_mbox_msg_send(&mbox->mbox, 0); 853 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 854 if (err) 855 return err; 856 857 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 858 } 859 860 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 861 { 862 int err; 863 864 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 865 return 0; 866 otx2_mbox_msg_send_up(&mbox->mbox_up, devid); 867 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 868 if (err) 869 return err; 870 871 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 872 } 873 874 /* Use this API to send mbox msgs in atomic context 875 * where sleeping is not allowed 876 */ 877 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 878 { 879 int err; 880 881 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 882 return 0; 883 otx2_mbox_msg_send(&mbox->mbox, 0); 884 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 885 if (err) 886 return err; 887 888 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 889 } 890 891 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 892 static struct _req_type __maybe_unused \ 893 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 894 { \ 895 struct _req_type *req; \ 896 u16 pcifunc = mbox->pfvf->pcifunc; \ 897 \ 898 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 899 &mbox->mbox, 0, sizeof(struct _req_type), \ 900 sizeof(struct _rsp_type)); \ 901 if (!req) \ 902 return NULL; \ 903 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 904 req->hdr.id = _id; \ 905 req->hdr.pcifunc = pcifunc; \ 906 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req), pcifunc); \ 907 return req; \ 908 } 909 910 MBOX_MESSAGES 911 #undef M 912 913 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 914 int \ 915 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 916 struct _req_type *req, \ 917 struct _rsp_type *rsp); \ 918 919 MBOX_UP_CGX_MESSAGES 920 MBOX_UP_MCS_MESSAGES 921 #undef M 922 923 /* Time to wait before watchdog kicks off */ 924 #define OTX2_TX_TIMEOUT (100 * HZ) 925 926 static inline bool is_otx2_vf(u16 pcifunc) 927 { 928 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 929 } 930 931 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 932 struct page *page, 933 size_t offset, size_t size, 934 enum dma_data_direction dir) 935 { 936 dma_addr_t iova; 937 938 iova = dma_map_page_attrs(pfvf->dev, page, 939 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 940 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 941 return (dma_addr_t)NULL; 942 return iova; 943 } 944 945 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 946 dma_addr_t addr, size_t size, 947 enum dma_data_direction dir) 948 { 949 dma_unmap_page_attrs(pfvf->dev, addr, size, 950 dir, DMA_ATTR_SKIP_CPU_SYNC); 951 } 952 953 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx) 954 { 955 u16 smq; 956 int idx; 957 958 #ifdef CONFIG_DCB 959 if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx]) 960 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx]; 961 #endif 962 /* check if qidx falls under QOS queues */ 963 if (qidx >= pfvf->hw.non_qos_queues) { 964 smq = pfvf->qos.qid_to_sqmap[qidx - pfvf->hw.non_qos_queues]; 965 } else { 966 idx = qidx % pfvf->hw.txschq_cnt[NIX_TXSCH_LVL_SMQ]; 967 smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][idx]; 968 } 969 970 return smq; 971 } 972 973 static inline u16 otx2_get_total_tx_queues(struct otx2_nic *pfvf) 974 { 975 return pfvf->hw.non_qos_queues + pfvf->hw.tc_tx_queues; 976 } 977 978 static inline u64 otx2_convert_rate(u64 rate) 979 { 980 u64 converted_rate; 981 982 /* Convert bytes per second to Mbps */ 983 converted_rate = rate * 8; 984 converted_rate = max_t(u64, converted_rate / 1000000, 1); 985 986 return converted_rate; 987 } 988 989 static inline int otx2_tc_flower_rule_cnt(struct otx2_nic *pfvf) 990 { 991 /* return here if MCAM entries not allocated */ 992 if (!pfvf->flow_cfg) 993 return 0; 994 995 return pfvf->flow_cfg->nr_flows; 996 } 997 998 /* MSI-X APIs */ 999 void otx2_free_cints(struct otx2_nic *pfvf, int n); 1000 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 1001 int otx2_set_mac_address(struct net_device *netdev, void *p); 1002 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 1003 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 1004 void otx2_get_mac_from_af(struct net_device *netdev); 1005 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 1006 int otx2_config_pause_frm(struct otx2_nic *pfvf); 1007 void otx2_setup_segmentation(struct otx2_nic *pfvf); 1008 int otx2_reset_mac_stats(struct otx2_nic *pfvf); 1009 1010 /* RVU block related APIs */ 1011 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 1012 int otx2_detach_resources(struct mbox *mbox); 1013 int otx2_config_npa(struct otx2_nic *pfvf); 1014 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 1015 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 1016 void otx2_aura_pool_free(struct otx2_nic *pfvf); 1017 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 1018 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 1019 int otx2_config_nix(struct otx2_nic *pfvf); 1020 int otx2_config_nix_queues(struct otx2_nic *pfvf); 1021 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en); 1022 int otx2_txsch_alloc(struct otx2_nic *pfvf); 1023 void otx2_txschq_stop(struct otx2_nic *pfvf); 1024 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq); 1025 void otx2_free_pending_sqe(struct otx2_nic *pfvf); 1026 void otx2_sqb_flush(struct otx2_nic *pfvf); 1027 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 1028 dma_addr_t *dma, int qidx, int idx); 1029 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 1030 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 1031 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 1032 int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable); 1033 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx); 1034 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 1035 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura); 1036 int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); 1037 int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); 1038 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 1039 dma_addr_t *dma); 1040 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1041 int stack_pages, int numptrs, int buf_size, int type); 1042 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1043 int pool_id, int numptrs); 1044 int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf); 1045 void otx2_free_queue_mem(struct otx2_qset *qset); 1046 int otx2_alloc_queue_mem(struct otx2_nic *pf); 1047 int otx2_init_hw_resources(struct otx2_nic *pfvf); 1048 void otx2_free_hw_resources(struct otx2_nic *pf); 1049 int otx2_wq_init(struct otx2_nic *pf); 1050 int otx2_check_pf_usable(struct otx2_nic *pf); 1051 int otx2_pfaf_mbox_init(struct otx2_nic *pf); 1052 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af); 1053 int otx2_realloc_msix_vectors(struct otx2_nic *pf); 1054 void otx2_pfaf_mbox_destroy(struct otx2_nic *pf); 1055 void otx2_disable_mbox_intr(struct otx2_nic *pf); 1056 void otx2_disable_napi(struct otx2_nic *pf); 1057 irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq); 1058 int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura); 1059 int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx); 1060 int otx2_set_hw_capabilities(struct otx2_nic *pfvf); 1061 1062 /* RSS configuration APIs*/ 1063 int otx2_rss_init(struct otx2_nic *pfvf); 1064 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 1065 void otx2_set_rss_key(struct otx2_nic *pfvf); 1066 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id, const u32 *ind_tbl); 1067 1068 /* Mbox handlers */ 1069 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1070 struct msix_offset_rsp *rsp); 1071 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1072 struct npa_lf_alloc_rsp *rsp); 1073 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1074 struct nix_lf_alloc_rsp *rsp); 1075 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1076 struct nix_txsch_alloc_rsp *rsp); 1077 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1078 struct cgx_stats_rsp *rsp); 1079 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1080 struct cgx_fec_stats_rsp *rsp); 1081 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 1082 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1083 struct nix_bp_cfg_rsp *rsp); 1084 1085 /* Device stats APIs */ 1086 void otx2_get_dev_stats(struct otx2_nic *pfvf); 1087 void otx2_get_stats64(struct net_device *netdev, 1088 struct rtnl_link_stats64 *stats); 1089 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 1090 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 1091 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 1092 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 1093 void otx2_set_ethtool_ops(struct net_device *netdev); 1094 void otx2vf_set_ethtool_ops(struct net_device *netdev); 1095 1096 int otx2_open(struct net_device *netdev); 1097 int otx2_stop(struct net_device *netdev); 1098 int otx2_set_real_num_queues(struct net_device *netdev, 1099 int tx_queues, int rx_queues); 1100 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd); 1101 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr); 1102 1103 /* MCAM filter related APIs */ 1104 int otx2_mcam_flow_init(struct otx2_nic *pf); 1105 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 1106 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 1107 void otx2_mcam_flow_del(struct otx2_nic *pf); 1108 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 1109 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 1110 int otx2_get_flow(struct otx2_nic *pfvf, 1111 struct ethtool_rxnfc *nfc, u32 location); 1112 int otx2_get_all_flows(struct otx2_nic *pfvf, 1113 struct ethtool_rxnfc *nfc, u32 *rule_locs); 1114 int otx2_add_flow(struct otx2_nic *pfvf, 1115 struct ethtool_rxnfc *nfc); 1116 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 1117 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 1118 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 1119 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 1120 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 1121 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 1122 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 1123 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, struct xdp_frame *xdpf, 1124 u64 iova, int len, u16 qidx, u16 flags); 1125 void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, struct xdp_frame *xdpf, 1126 u64 dma_addr, int len, int *offset, u16 flags); 1127 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 1128 int otx2_handle_ntuple_tc_features(struct net_device *netdev, 1129 netdev_features_t features); 1130 int otx2_smq_flush(struct otx2_nic *pfvf, int smq); 1131 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1132 u64 iova, int size); 1133 int otx2_mcam_entry_init(struct otx2_nic *pfvf); 1134 1135 /* tc support */ 1136 int otx2_init_tc(struct otx2_nic *nic); 1137 void otx2_shutdown_tc(struct otx2_nic *nic); 1138 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 1139 void *type_data); 1140 void otx2_tc_apply_ingress_police_rules(struct otx2_nic *nic); 1141 1142 /* CGX/RPM DMAC filters support */ 1143 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 1144 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1145 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1146 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos); 1147 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 1148 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 1149 1150 #ifdef CONFIG_DCB 1151 /* DCB support*/ 1152 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable); 1153 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf); 1154 int otx2_dcbnl_set_ops(struct net_device *dev); 1155 /* PFC support */ 1156 int otx2_pfc_txschq_config(struct otx2_nic *pfvf); 1157 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf); 1158 int otx2_pfc_txschq_update(struct otx2_nic *pfvf); 1159 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf); 1160 #endif 1161 1162 #if IS_ENABLED(CONFIG_MACSEC) 1163 /* MACSEC offload support */ 1164 int cn10k_mcs_init(struct otx2_nic *pfvf); 1165 void cn10k_mcs_free(struct otx2_nic *pfvf); 1166 void cn10k_handle_mcs_event(struct otx2_nic *pfvf, struct mcs_intr_info *event); 1167 #else 1168 static inline int cn10k_mcs_init(struct otx2_nic *pfvf) { return 0; } 1169 static inline void cn10k_mcs_free(struct otx2_nic *pfvf) {} 1170 static inline void cn10k_handle_mcs_event(struct otx2_nic *pfvf, 1171 struct mcs_intr_info *event) 1172 {} 1173 #endif /* CONFIG_MACSEC */ 1174 1175 /* qos support */ 1176 static inline void otx2_qos_init(struct otx2_nic *pfvf, int qos_txqs) 1177 { 1178 struct otx2_hw *hw = &pfvf->hw; 1179 1180 hw->tc_tx_queues = qos_txqs; 1181 INIT_LIST_HEAD(&pfvf->qos.qos_tree); 1182 mutex_init(&pfvf->qos.qos_lock); 1183 } 1184 1185 static inline void otx2_shutdown_qos(struct otx2_nic *pfvf) 1186 { 1187 mutex_destroy(&pfvf->qos.qos_lock); 1188 } 1189 1190 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1191 struct net_device *sb_dev); 1192 int otx2_get_txq_by_classid(struct otx2_nic *pfvf, u16 classid); 1193 void otx2_qos_config_txschq(struct otx2_nic *pfvf); 1194 void otx2_clean_qos_queues(struct otx2_nic *pfvf); 1195 int rvu_event_up_notify(struct otx2_nic *pf, struct rep_event *info); 1196 int otx2_setup_tc_cls_flower(struct otx2_nic *nic, 1197 struct flow_cls_offload *cls_flower); 1198 1199 static inline int mcam_entry_cmp(const void *a, const void *b) 1200 { 1201 return *(u16 *)a - *(u16 *)b; 1202 } 1203 1204 dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 1205 struct sk_buff *skb, int seg, int *len); 1206 void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg); 1207 int otx2_read_free_sqe(struct otx2_nic *pfvf, u16 qidx); 1208 void otx2_queue_vf_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 1209 int first, int mdevs, u64 intr); 1210 #endif /* OTX2_COMMON_H */ 1211