1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_COMMON_H 9 #define OTX2_COMMON_H 10 11 #include <linux/ethtool.h> 12 #include <linux/pci.h> 13 #include <linux/iommu.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/ptp_clock_kernel.h> 16 #include <linux/timecounter.h> 17 #include <linux/soc/marvell/octeontx2/asm.h> 18 #include <net/macsec.h> 19 #include <net/pkt_cls.h> 20 #include <net/devlink.h> 21 #include <linux/time64.h> 22 #include <linux/dim.h> 23 #include <uapi/linux/if_macsec.h> 24 25 #include <mbox.h> 26 #include <npc.h> 27 #include "otx2_reg.h" 28 #include "otx2_txrx.h" 29 #include "otx2_devlink.h" 30 #include <rvu_trace.h> 31 #include "qos.h" 32 #include "rep.h" 33 34 /* IPv4 flag more fragment bit */ 35 #define IPV4_FLAG_MORE 0x20 36 37 /* PCI device IDs */ 38 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 39 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 40 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 41 42 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 43 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00 44 45 #define PCI_DEVID_OCTEONTX2_SDP_REP 0xA0F7 46 47 /* PCI BAR nos */ 48 #define PCI_CFG_REG_BAR_NUM 2 49 #define PCI_MBOX_BAR_NUM 4 50 51 #define NAME_SIZE 32 52 53 #ifdef CONFIG_DCB 54 /* Max priority supported for PFC */ 55 #define NIX_PF_PFC_PRIO_MAX 8 56 #endif 57 58 enum arua_mapped_qtypes { 59 AURA_NIX_RQ, 60 AURA_NIX_SQ, 61 }; 62 63 /* NIX LF interrupts range*/ 64 #define NIX_LF_QINT_VEC_START 0x00 65 #define NIX_LF_CINT_VEC_START 0x40 66 #define NIX_LF_GINT_VEC 0x80 67 #define NIX_LF_ERR_VEC 0x81 68 #define NIX_LF_POISON_VEC 0x82 69 70 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 71 #define SEND_CQ_SKID 2000 72 73 #define OTX2_GET_RX_STATS(reg) \ 74 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 75 #define OTX2_GET_TX_STATS(reg) \ 76 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 77 78 struct otx2_lmt_info { 79 u64 lmt_addr; 80 u16 lmt_id; 81 }; 82 /* RSS configuration */ 83 struct otx2_rss_ctx { 84 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 85 }; 86 87 struct otx2_rss_info { 88 u8 enable; 89 u32 flowkey_cfg; 90 u16 rss_size; 91 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 92 u8 key[RSS_HASH_KEY_SIZE]; 93 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 94 }; 95 96 /* NIX (or NPC) RX errors */ 97 enum otx2_errlvl { 98 NPC_ERRLVL_RE, 99 NPC_ERRLVL_LID_LA, 100 NPC_ERRLVL_LID_LB, 101 NPC_ERRLVL_LID_LC, 102 NPC_ERRLVL_LID_LD, 103 NPC_ERRLVL_LID_LE, 104 NPC_ERRLVL_LID_LF, 105 NPC_ERRLVL_LID_LG, 106 NPC_ERRLVL_LID_LH, 107 NPC_ERRLVL_NIX = 0x0F, 108 }; 109 110 enum otx2_errcodes_re { 111 /* NPC_ERRLVL_RE errcodes */ 112 ERRCODE_FCS = 0x7, 113 ERRCODE_FCS_RCV = 0x8, 114 ERRCODE_UNDERSIZE = 0x10, 115 ERRCODE_OVERSIZE = 0x11, 116 ERRCODE_OL2_LEN_MISMATCH = 0x12, 117 /* NPC_ERRLVL_NIX errcodes */ 118 ERRCODE_OL3_LEN = 0x10, 119 ERRCODE_OL4_LEN = 0x11, 120 ERRCODE_OL4_CSUM = 0x12, 121 ERRCODE_IL3_LEN = 0x20, 122 ERRCODE_IL4_LEN = 0x21, 123 ERRCODE_IL4_CSUM = 0x22, 124 }; 125 126 struct otx2_dev_stats { 127 u64 rx_bytes; 128 u64 rx_frames; 129 u64 rx_ucast_frames; 130 u64 rx_bcast_frames; 131 u64 rx_mcast_frames; 132 u64 rx_drops; 133 134 u64 tx_bytes; 135 u64 tx_frames; 136 u64 tx_ucast_frames; 137 u64 tx_bcast_frames; 138 u64 tx_mcast_frames; 139 u64 tx_drops; 140 }; 141 142 /* Driver counted stats */ 143 struct otx2_drv_stats { 144 atomic_t rx_fcs_errs; 145 atomic_t rx_oversize_errs; 146 atomic_t rx_undersize_errs; 147 atomic_t rx_csum_errs; 148 atomic_t rx_len_errs; 149 atomic_t rx_other_errs; 150 }; 151 152 struct mbox { 153 struct otx2_mbox mbox; 154 struct work_struct mbox_wrk; 155 struct otx2_mbox mbox_up; 156 struct work_struct mbox_up_wrk; 157 struct otx2_nic *pfvf; 158 void *bbuf_base; /* Bounce buffer for mbox memory */ 159 struct mutex lock; /* serialize mailbox access */ 160 int num_msgs; /* mbox number of messages */ 161 int up_num_msgs; /* mbox_up number of messages */ 162 }; 163 164 /* Egress rate limiting definitions */ 165 #define MAX_BURST_EXPONENT 0x0FULL 166 #define MAX_BURST_MANTISSA 0xFFULL 167 #define MAX_BURST_SIZE 130816ULL 168 #define MAX_RATE_DIVIDER_EXPONENT 12ULL 169 #define MAX_RATE_EXPONENT 0x0FULL 170 #define MAX_RATE_MANTISSA 0xFFULL 171 172 /* Bitfields in NIX_TLX_PIR register */ 173 #define TLX_RATE_MANTISSA GENMASK_ULL(8, 1) 174 #define TLX_RATE_EXPONENT GENMASK_ULL(12, 9) 175 #define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13) 176 #define TLX_BURST_MANTISSA GENMASK_ULL(36, 29) 177 #define TLX_BURST_EXPONENT GENMASK_ULL(40, 37) 178 179 struct otx2_hw { 180 struct pci_dev *pdev; 181 struct otx2_rss_info rss_info; 182 u16 rx_queues; 183 u16 tx_queues; 184 u16 xdp_queues; 185 u16 tc_tx_queues; 186 u16 non_qos_queues; /* tx queues plus xdp queues */ 187 u16 max_queues; 188 u16 pool_cnt; 189 u16 rqpool_cnt; 190 u16 sqpool_cnt; 191 192 #define OTX2_DEFAULT_RBUF_LEN 2048 193 u16 rbuf_len; 194 u32 xqe_size; 195 196 /* NPA */ 197 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 198 u32 stack_pg_bytes; /* Size of stack page */ 199 u16 sqb_size; 200 201 /* NIX */ 202 u8 txschq_link_cfg_lvl; 203 u8 txschq_cnt[NIX_TXSCH_LVL_CNT]; 204 u8 txschq_aggr_lvl_rr_prio; 205 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 206 u16 matchall_ipolicer; 207 u32 dwrr_mtu; 208 u32 max_mtu; 209 u8 smq_link_type; 210 211 /* HW settings, coalescing etc */ 212 u16 rx_chan_base; 213 u16 tx_chan_base; 214 u8 rx_chan_cnt; 215 u8 tx_chan_cnt; 216 u16 cq_qcount_wait; 217 u16 cq_ecount_wait; 218 u16 rq_skid; 219 u8 cq_time_wait; 220 221 /* Segmentation */ 222 u8 lso_tsov4_idx; 223 u8 lso_tsov6_idx; 224 u8 lso_udpv4_idx; 225 u8 lso_udpv6_idx; 226 227 /* RSS */ 228 u8 flowkey_alg_idx; 229 230 /* MSI-X */ 231 u8 cint_cnt; /* CQ interrupt count */ 232 u16 npa_msixoff; /* Offset of NPA vectors */ 233 u16 nix_msixoff; /* Offset of NIX vectors */ 234 char *irq_name; 235 cpumask_var_t *affinity_mask; 236 237 /* Stats */ 238 struct otx2_dev_stats dev_stats; 239 struct otx2_drv_stats drv_stats; 240 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 241 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 242 u64 cgx_fec_corr_blks; 243 u64 cgx_fec_uncorr_blks; 244 u8 cgx_links; /* No. of CGX links present in HW */ 245 u8 lbk_links; /* No. of LBK links present in HW */ 246 u8 tx_link; /* Transmit channel link number */ 247 #define HW_TSO 0 248 #define CN10K_MBOX 1 249 #define CN10K_LMTST 2 250 #define CN10K_RPM 3 251 #define CN10K_PTP_ONESTEP 4 252 #define CN10K_HW_MACSEC 5 253 #define QOS_CIR_PIR_SUPPORT 6 254 unsigned long cap_flag; 255 256 #define LMT_LINE_SIZE 128 257 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 258 u64 *lmt_base; 259 struct otx2_lmt_info __percpu *lmt_info; 260 }; 261 262 enum vfperm { 263 OTX2_RESET_VF_PERM, 264 OTX2_TRUSTED_VF, 265 }; 266 267 struct otx2_vf_config { 268 struct otx2_nic *pf; 269 struct delayed_work link_event_work; 270 bool intf_down; /* interface was either configured or not */ 271 u8 mac[ETH_ALEN]; 272 u16 vlan; 273 int tx_vtag_idx; 274 bool trusted; 275 }; 276 277 struct flr_work { 278 struct work_struct work; 279 struct otx2_nic *pf; 280 }; 281 282 struct refill_work { 283 struct delayed_work pool_refill_work; 284 struct otx2_nic *pf; 285 struct napi_struct *napi; 286 }; 287 288 /* PTPv2 originTimestamp structure */ 289 struct ptpv2_tstamp { 290 __be16 seconds_msb; /* 16 bits + */ 291 __be32 seconds_lsb; /* 32 bits = 48 bits*/ 292 __be32 nanoseconds; 293 } __packed; 294 295 struct otx2_ptp { 296 struct ptp_clock_info ptp_info; 297 struct ptp_clock *ptp_clock; 298 struct otx2_nic *nic; 299 300 struct cyclecounter cycle_counter; 301 struct timecounter time_counter; 302 303 struct delayed_work extts_work; 304 u64 last_extts; 305 u64 thresh; 306 307 struct ptp_pin_desc extts_config; 308 u64 (*convert_rx_ptp_tstmp)(u64 timestamp); 309 u64 (*convert_tx_ptp_tstmp)(u64 timestamp); 310 u64 (*ptp_tstamp2nsec)(const struct timecounter *time_counter, u64 timestamp); 311 struct delayed_work synctstamp_work; 312 u64 tstamp; 313 u32 base_ns; 314 }; 315 316 #define OTX2_HW_TIMESTAMP_LEN 8 317 318 struct otx2_mac_table { 319 u8 addr[ETH_ALEN]; 320 u16 mcam_entry; 321 bool inuse; 322 }; 323 324 struct otx2_flow_config { 325 u16 *flow_ent; 326 u16 *def_ent; 327 u16 nr_flows; 328 #define OTX2_DEFAULT_FLOWCOUNT 16 329 #define OTX2_DEFAULT_UNICAST_FLOWS 4 330 #define OTX2_MAX_VLAN_FLOWS 1 331 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 332 u16 unicast_offset; 333 u16 rx_vlan_offset; 334 u16 vf_vlan_offset; 335 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 336 #define OTX2_VF_VLAN_RX_INDEX 0 337 #define OTX2_VF_VLAN_TX_INDEX 1 338 u32 *bmap_to_dmacindex; 339 unsigned long *dmacflt_bmap; 340 struct list_head flow_list; 341 u32 dmacflt_max_flows; 342 u16 max_flows; 343 refcount_t mark_flows; 344 struct list_head flow_list_tc; 345 u8 ucast_flt_cnt; 346 bool ntuple; 347 }; 348 349 struct dev_hw_ops { 350 int (*sq_aq_init)(void *dev, u16 qidx, u8 chan_offset, 351 u16 sqb_aura); 352 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 353 int size, int qidx); 354 int (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 355 void (*aura_freeptr)(void *dev, int aura, u64 buf); 356 }; 357 358 #define CN10K_MCS_SA_PER_SC 4 359 360 /* Stats which need to be accumulated in software because 361 * of shared counters in hardware. 362 */ 363 struct cn10k_txsc_stats { 364 u64 InPktsUntagged; 365 u64 InPktsNoTag; 366 u64 InPktsBadTag; 367 u64 InPktsUnknownSCI; 368 u64 InPktsNoSCI; 369 u64 InPktsOverrun; 370 }; 371 372 struct cn10k_rxsc_stats { 373 u64 InOctetsValidated; 374 u64 InOctetsDecrypted; 375 u64 InPktsUnchecked; 376 u64 InPktsDelayed; 377 u64 InPktsOK; 378 u64 InPktsInvalid; 379 u64 InPktsLate; 380 u64 InPktsNotValid; 381 u64 InPktsNotUsingSA; 382 u64 InPktsUnusedSA; 383 }; 384 385 struct cn10k_mcs_txsc { 386 struct macsec_secy *sw_secy; 387 struct cn10k_txsc_stats stats; 388 struct list_head entry; 389 enum macsec_validation_type last_validate_frames; 390 bool last_replay_protect; 391 u16 hw_secy_id_tx; 392 u16 hw_secy_id_rx; 393 u16 hw_flow_id; 394 u16 hw_sc_id; 395 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 396 u8 sa_bmap; 397 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 398 u8 encoding_sa; 399 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 400 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 401 bool vlan_dev; /* macsec running on VLAN ? */ 402 }; 403 404 struct cn10k_mcs_rxsc { 405 struct macsec_secy *sw_secy; 406 struct macsec_rx_sc *sw_rxsc; 407 struct cn10k_rxsc_stats stats; 408 struct list_head entry; 409 u16 hw_flow_id; 410 u16 hw_sc_id; 411 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 412 u8 sa_bmap; 413 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 414 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 415 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 416 }; 417 418 struct cn10k_mcs_cfg { 419 struct list_head txsc_list; 420 struct list_head rxsc_list; 421 }; 422 423 struct otx2_nic { 424 void __iomem *reg_base; 425 struct net_device *netdev; 426 struct dev_hw_ops *hw_ops; 427 void *iommu_domain; 428 u16 tx_max_pktlen; 429 u16 rbsize; /* Receive buffer size */ 430 431 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 432 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 433 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 434 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 435 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 436 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 437 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 438 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 439 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 440 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 441 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 442 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 443 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 444 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 445 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 446 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15) 447 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) 448 #define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17) 449 #define OTX2_FLAG_REP_MODE_ENABLED BIT_ULL(18) 450 #define OTX2_FLAG_PORT_UP BIT_ULL(19) 451 u64 flags; 452 u64 *cq_op_addr; 453 454 struct bpf_prog *xdp_prog; 455 struct otx2_qset qset; 456 struct otx2_hw hw; 457 struct pci_dev *pdev; 458 struct device *dev; 459 460 /* Mbox */ 461 struct mbox mbox; 462 struct mbox *mbox_pfvf; 463 struct workqueue_struct *mbox_wq; 464 struct workqueue_struct *mbox_pfvf_wq; 465 466 u8 total_vfs; 467 u16 pcifunc; /* RVU PF_FUNC */ 468 u16 bpid[NIX_MAX_BPID_CHAN]; 469 struct otx2_vf_config *vf_configs; 470 struct cgx_link_user_info linfo; 471 472 /* NPC MCAM */ 473 struct otx2_flow_config *flow_cfg; 474 struct otx2_mac_table *mac_table; 475 476 u64 reset_count; 477 struct work_struct reset_task; 478 struct workqueue_struct *flr_wq; 479 struct flr_work *flr_wrk; 480 struct refill_work *refill_wrk; 481 struct workqueue_struct *otx2_wq; 482 struct work_struct rx_mode_work; 483 484 /* Ethtool stuff */ 485 u32 msg_enable; 486 487 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 488 int nix_blkaddr; 489 /* LMTST Lines info */ 490 struct qmem *dync_lmt; 491 u16 tot_lmt_lines; 492 u16 npa_lmt_lines; 493 u32 nix_lmt_size; 494 495 struct otx2_ptp *ptp; 496 struct hwtstamp_config tstamp; 497 498 unsigned long rq_bmap; 499 500 /* Devlink */ 501 struct otx2_devlink *dl; 502 #ifdef CONFIG_DCB 503 /* PFC */ 504 u8 pfc_en; 505 u8 *queue_to_pfc_map; 506 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 507 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX]; 508 #endif 509 /* qos */ 510 struct otx2_qos qos; 511 512 /* napi event count. It is needed for adaptive irq coalescing. */ 513 u32 napi_events; 514 515 #if IS_ENABLED(CONFIG_MACSEC) 516 struct cn10k_mcs_cfg *macsec_cfg; 517 #endif 518 519 #if IS_ENABLED(CONFIG_RVU_ESWITCH) 520 struct rep_dev **reps; 521 int rep_cnt; 522 u16 rep_pf_map[RVU_MAX_REP]; 523 u16 esw_mode; 524 #endif 525 }; 526 527 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 528 { 529 return (pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF) || 530 (pdev->device == PCI_DEVID_RVU_REP); 531 } 532 533 static inline bool is_96xx_A0(struct pci_dev *pdev) 534 { 535 return (pdev->revision == 0x00) && 536 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 537 } 538 539 static inline bool is_96xx_B0(struct pci_dev *pdev) 540 { 541 return (pdev->revision == 0x01) && 542 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 543 } 544 545 static inline bool is_otx2_sdp_rep(struct pci_dev *pdev) 546 { 547 return pdev->device == PCI_DEVID_OCTEONTX2_SDP_REP; 548 } 549 550 /* REVID for PCIe devices. 551 * Bits 0..1: minor pass, bit 3..2: major pass 552 * bits 7..4: midr id 553 */ 554 #define PCI_REVISION_ID_96XX 0x00 555 #define PCI_REVISION_ID_95XX 0x10 556 #define PCI_REVISION_ID_95XXN 0x20 557 #define PCI_REVISION_ID_98XX 0x30 558 #define PCI_REVISION_ID_95XXMM 0x40 559 #define PCI_REVISION_ID_95XXO 0xE0 560 561 static inline bool is_dev_otx2(struct pci_dev *pdev) 562 { 563 u8 midr = pdev->revision & 0xF0; 564 565 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 566 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 567 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 568 } 569 570 static inline bool is_dev_cn10kb(struct pci_dev *pdev) 571 { 572 return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF; 573 } 574 575 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 576 { 577 struct otx2_hw *hw = &pfvf->hw; 578 579 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 580 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 581 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 582 583 __set_bit(HW_TSO, &hw->cap_flag); 584 585 if (is_96xx_A0(pfvf->pdev)) { 586 __clear_bit(HW_TSO, &hw->cap_flag); 587 588 /* Time based irq coalescing is not supported */ 589 pfvf->hw.cq_qcount_wait = 0x0; 590 591 /* Due to HW issue previous silicons required minimum 592 * 600 unused CQE to avoid CQ overflow. 593 */ 594 pfvf->hw.rq_skid = 600; 595 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 596 } 597 if (is_96xx_B0(pfvf->pdev)) 598 __clear_bit(HW_TSO, &hw->cap_flag); 599 600 if (!is_dev_otx2(pfvf->pdev)) { 601 __set_bit(CN10K_MBOX, &hw->cap_flag); 602 __set_bit(CN10K_LMTST, &hw->cap_flag); 603 __set_bit(CN10K_RPM, &hw->cap_flag); 604 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag); 605 __set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag); 606 } 607 608 if (is_dev_cn10kb(pfvf->pdev)) 609 __set_bit(CN10K_HW_MACSEC, &hw->cap_flag); 610 } 611 612 /* Register read/write APIs */ 613 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 614 { 615 u64 blkaddr; 616 617 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 618 case BLKTYPE_NIX: 619 blkaddr = nic->nix_blkaddr; 620 break; 621 case BLKTYPE_NPA: 622 blkaddr = BLKADDR_NPA; 623 break; 624 default: 625 blkaddr = BLKADDR_RVUM; 626 break; 627 } 628 629 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 630 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 631 632 return nic->reg_base + offset; 633 } 634 635 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 636 { 637 void __iomem *addr = otx2_get_regaddr(nic, offset); 638 639 writeq(val, addr); 640 } 641 642 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 643 { 644 void __iomem *addr = otx2_get_regaddr(nic, offset); 645 646 return readq(addr); 647 } 648 649 /* Mbox bounce buffer APIs */ 650 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 651 { 652 struct otx2_mbox *otx2_mbox; 653 struct otx2_mbox_dev *mdev; 654 655 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 656 if (!mbox->bbuf_base) 657 return -ENOMEM; 658 659 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 660 * prepare all mbox messages in bounce buffer instead of directly 661 * in hw mbox memory. 662 */ 663 otx2_mbox = &mbox->mbox; 664 mdev = &otx2_mbox->dev[0]; 665 mdev->mbase = mbox->bbuf_base; 666 667 otx2_mbox = &mbox->mbox_up; 668 mdev = &otx2_mbox->dev[0]; 669 mdev->mbase = mbox->bbuf_base; 670 return 0; 671 } 672 673 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 674 { 675 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 676 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 677 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 678 struct mbox_hdr *hdr; 679 u64 msg_size; 680 681 if (mdev->mbase == hw_mbase) 682 return; 683 684 hdr = hw_mbase + mbox->rx_start; 685 msg_size = hdr->msg_size; 686 687 if (msg_size > mbox->rx_size - msgs_offset) 688 msg_size = mbox->rx_size - msgs_offset; 689 690 /* Copy mbox messages from mbox memory to bounce buffer */ 691 memcpy(mdev->mbase + mbox->rx_start, 692 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 693 } 694 695 /* With the absence of API for 128-bit IO memory access for arm64, 696 * implement required operations at place. 697 */ 698 #if defined(CONFIG_ARM64) 699 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 700 { 701 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 702 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 703 } 704 705 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 706 { 707 u64 result; 708 709 __asm__ volatile(".cpu generic+lse\n" 710 "ldadd %x[i], %x[r], [%[b]]" 711 : [r]"=r"(result), "+m"(*ptr) 712 : [i]"r"(incr), [b]"r"(ptr) 713 : "memory"); 714 return result; 715 } 716 717 #else 718 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 719 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 720 #endif 721 722 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 723 u64 *ptrs, u64 num_ptrs) 724 { 725 struct otx2_lmt_info *lmt_info; 726 u64 size = 0, count_eot = 0; 727 u64 tar_addr, val = 0; 728 729 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); 730 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 731 /* LMTID is same as AURA Id */ 732 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); 733 /* Set if [127:64] of last 128bit word has a valid pointer */ 734 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 735 /* Set AURA ID to free pointer */ 736 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 737 /* Target address for LMTST flush tells HW how many 128bit 738 * words are valid from NPA_LF_AURA_BATCH_FREE0. 739 * 740 * tar_addr[6:4] is LMTST size-1 in units of 128b. 741 */ 742 if (num_ptrs > 2) { 743 size = (sizeof(u64) * num_ptrs) / 16; 744 if (!count_eot) 745 size++; 746 tar_addr |= ((size - 1) & 0x7) << 4; 747 } 748 dma_wmb(); 749 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); 750 /* Perform LMTST flush */ 751 cn10k_lmt_flush(val, tar_addr); 752 } 753 754 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 755 { 756 struct otx2_nic *pfvf = dev; 757 u64 ptrs[2]; 758 759 ptrs[1] = buf; 760 get_cpu(); 761 /* Free only one buffer at time during init and teardown */ 762 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); 763 put_cpu(); 764 } 765 766 /* Alloc pointer from pool/aura */ 767 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 768 { 769 u64 *ptr = (__force u64 *)otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_ALLOCX(0)); 770 u64 incr = (u64)aura | BIT_ULL(63); 771 772 return otx2_atomic64_add(incr, ptr); 773 } 774 775 /* Free pointer to a pool/aura */ 776 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 777 { 778 struct otx2_nic *pfvf = dev; 779 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 780 781 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 782 } 783 784 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 785 { 786 if (type == AURA_NIX_SQ) 787 return pfvf->hw.rqpool_cnt + idx; 788 789 /* AURA_NIX_RQ */ 790 return idx; 791 } 792 793 /* Mbox APIs */ 794 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 795 { 796 int err; 797 798 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 799 return 0; 800 otx2_mbox_msg_send(&mbox->mbox, 0); 801 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 802 if (err) 803 return err; 804 805 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 806 } 807 808 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 809 { 810 int err; 811 812 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 813 return 0; 814 otx2_mbox_msg_send_up(&mbox->mbox_up, devid); 815 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 816 if (err) 817 return err; 818 819 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 820 } 821 822 /* Use this API to send mbox msgs in atomic context 823 * where sleeping is not allowed 824 */ 825 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 826 { 827 int err; 828 829 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 830 return 0; 831 otx2_mbox_msg_send(&mbox->mbox, 0); 832 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 833 if (err) 834 return err; 835 836 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 837 } 838 839 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 840 static struct _req_type __maybe_unused \ 841 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 842 { \ 843 struct _req_type *req; \ 844 \ 845 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 846 &mbox->mbox, 0, sizeof(struct _req_type), \ 847 sizeof(struct _rsp_type)); \ 848 if (!req) \ 849 return NULL; \ 850 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 851 req->hdr.id = _id; \ 852 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 853 return req; \ 854 } 855 856 MBOX_MESSAGES 857 #undef M 858 859 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 860 int \ 861 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 862 struct _req_type *req, \ 863 struct _rsp_type *rsp); \ 864 865 MBOX_UP_CGX_MESSAGES 866 MBOX_UP_MCS_MESSAGES 867 #undef M 868 869 /* Time to wait before watchdog kicks off */ 870 #define OTX2_TX_TIMEOUT (100 * HZ) 871 872 #define RVU_PFVF_PF_SHIFT 10 873 #define RVU_PFVF_PF_MASK 0x3F 874 #define RVU_PFVF_FUNC_SHIFT 0 875 #define RVU_PFVF_FUNC_MASK 0x3FF 876 877 static inline bool is_otx2_vf(u16 pcifunc) 878 { 879 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 880 } 881 882 static inline int rvu_get_pf(u16 pcifunc) 883 { 884 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 885 } 886 887 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 888 struct page *page, 889 size_t offset, size_t size, 890 enum dma_data_direction dir) 891 { 892 dma_addr_t iova; 893 894 iova = dma_map_page_attrs(pfvf->dev, page, 895 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 896 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 897 return (dma_addr_t)NULL; 898 return iova; 899 } 900 901 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 902 dma_addr_t addr, size_t size, 903 enum dma_data_direction dir) 904 { 905 dma_unmap_page_attrs(pfvf->dev, addr, size, 906 dir, DMA_ATTR_SKIP_CPU_SYNC); 907 } 908 909 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx) 910 { 911 u16 smq; 912 int idx; 913 914 #ifdef CONFIG_DCB 915 if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx]) 916 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx]; 917 #endif 918 /* check if qidx falls under QOS queues */ 919 if (qidx >= pfvf->hw.non_qos_queues) { 920 smq = pfvf->qos.qid_to_sqmap[qidx - pfvf->hw.non_qos_queues]; 921 } else { 922 idx = qidx % pfvf->hw.txschq_cnt[NIX_TXSCH_LVL_SMQ]; 923 smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][idx]; 924 } 925 926 return smq; 927 } 928 929 static inline u16 otx2_get_total_tx_queues(struct otx2_nic *pfvf) 930 { 931 return pfvf->hw.non_qos_queues + pfvf->hw.tc_tx_queues; 932 } 933 934 static inline u64 otx2_convert_rate(u64 rate) 935 { 936 u64 converted_rate; 937 938 /* Convert bytes per second to Mbps */ 939 converted_rate = rate * 8; 940 converted_rate = max_t(u64, converted_rate / 1000000, 1); 941 942 return converted_rate; 943 } 944 945 static inline int otx2_tc_flower_rule_cnt(struct otx2_nic *pfvf) 946 { 947 /* return here if MCAM entries not allocated */ 948 if (!pfvf->flow_cfg) 949 return 0; 950 951 return pfvf->flow_cfg->nr_flows; 952 } 953 954 /* MSI-X APIs */ 955 void otx2_free_cints(struct otx2_nic *pfvf, int n); 956 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 957 int otx2_set_mac_address(struct net_device *netdev, void *p); 958 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 959 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 960 void otx2_get_mac_from_af(struct net_device *netdev); 961 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 962 int otx2_config_pause_frm(struct otx2_nic *pfvf); 963 void otx2_setup_segmentation(struct otx2_nic *pfvf); 964 int otx2_reset_mac_stats(struct otx2_nic *pfvf); 965 966 /* RVU block related APIs */ 967 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 968 int otx2_detach_resources(struct mbox *mbox); 969 int otx2_config_npa(struct otx2_nic *pfvf); 970 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 971 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 972 void otx2_aura_pool_free(struct otx2_nic *pfvf); 973 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 974 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 975 int otx2_config_nix(struct otx2_nic *pfvf); 976 int otx2_config_nix_queues(struct otx2_nic *pfvf); 977 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en); 978 int otx2_txsch_alloc(struct otx2_nic *pfvf); 979 void otx2_txschq_stop(struct otx2_nic *pfvf); 980 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq); 981 void otx2_free_pending_sqe(struct otx2_nic *pfvf); 982 void otx2_sqb_flush(struct otx2_nic *pfvf); 983 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 984 dma_addr_t *dma); 985 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 986 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 987 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 988 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx); 989 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 990 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura); 991 int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); 992 int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); 993 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 994 dma_addr_t *dma); 995 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 996 int stack_pages, int numptrs, int buf_size, int type); 997 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 998 int pool_id, int numptrs); 999 int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf); 1000 void otx2_free_queue_mem(struct otx2_qset *qset); 1001 int otx2_alloc_queue_mem(struct otx2_nic *pf); 1002 int otx2_init_hw_resources(struct otx2_nic *pfvf); 1003 void otx2_free_hw_resources(struct otx2_nic *pf); 1004 int otx2_wq_init(struct otx2_nic *pf); 1005 int otx2_check_pf_usable(struct otx2_nic *pf); 1006 int otx2_pfaf_mbox_init(struct otx2_nic *pf); 1007 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af); 1008 int otx2_realloc_msix_vectors(struct otx2_nic *pf); 1009 void otx2_pfaf_mbox_destroy(struct otx2_nic *pf); 1010 void otx2_disable_mbox_intr(struct otx2_nic *pf); 1011 void otx2_disable_napi(struct otx2_nic *pf); 1012 irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq); 1013 1014 /* RSS configuration APIs*/ 1015 int otx2_rss_init(struct otx2_nic *pfvf); 1016 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 1017 void otx2_set_rss_key(struct otx2_nic *pfvf); 1018 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 1019 1020 /* Mbox handlers */ 1021 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1022 struct msix_offset_rsp *rsp); 1023 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1024 struct npa_lf_alloc_rsp *rsp); 1025 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1026 struct nix_lf_alloc_rsp *rsp); 1027 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1028 struct nix_txsch_alloc_rsp *rsp); 1029 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1030 struct cgx_stats_rsp *rsp); 1031 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1032 struct cgx_fec_stats_rsp *rsp); 1033 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 1034 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1035 struct nix_bp_cfg_rsp *rsp); 1036 1037 /* Device stats APIs */ 1038 void otx2_get_dev_stats(struct otx2_nic *pfvf); 1039 void otx2_get_stats64(struct net_device *netdev, 1040 struct rtnl_link_stats64 *stats); 1041 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 1042 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 1043 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 1044 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 1045 void otx2_set_ethtool_ops(struct net_device *netdev); 1046 void otx2vf_set_ethtool_ops(struct net_device *netdev); 1047 1048 int otx2_open(struct net_device *netdev); 1049 int otx2_stop(struct net_device *netdev); 1050 int otx2_set_real_num_queues(struct net_device *netdev, 1051 int tx_queues, int rx_queues); 1052 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd); 1053 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr); 1054 1055 /* MCAM filter related APIs */ 1056 int otx2_mcam_flow_init(struct otx2_nic *pf); 1057 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 1058 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 1059 void otx2_mcam_flow_del(struct otx2_nic *pf); 1060 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 1061 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 1062 int otx2_get_flow(struct otx2_nic *pfvf, 1063 struct ethtool_rxnfc *nfc, u32 location); 1064 int otx2_get_all_flows(struct otx2_nic *pfvf, 1065 struct ethtool_rxnfc *nfc, u32 *rule_locs); 1066 int otx2_add_flow(struct otx2_nic *pfvf, 1067 struct ethtool_rxnfc *nfc); 1068 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 1069 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 1070 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 1071 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 1072 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 1073 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 1074 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 1075 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx); 1076 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 1077 int otx2_handle_ntuple_tc_features(struct net_device *netdev, 1078 netdev_features_t features); 1079 int otx2_smq_flush(struct otx2_nic *pfvf, int smq); 1080 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1081 u64 iova, int size); 1082 int otx2_mcam_entry_init(struct otx2_nic *pfvf); 1083 1084 /* tc support */ 1085 int otx2_init_tc(struct otx2_nic *nic); 1086 void otx2_shutdown_tc(struct otx2_nic *nic); 1087 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 1088 void *type_data); 1089 void otx2_tc_apply_ingress_police_rules(struct otx2_nic *nic); 1090 1091 /* CGX/RPM DMAC filters support */ 1092 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 1093 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1094 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1095 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos); 1096 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 1097 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 1098 1099 #ifdef CONFIG_DCB 1100 /* DCB support*/ 1101 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable); 1102 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf); 1103 int otx2_dcbnl_set_ops(struct net_device *dev); 1104 /* PFC support */ 1105 int otx2_pfc_txschq_config(struct otx2_nic *pfvf); 1106 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf); 1107 int otx2_pfc_txschq_update(struct otx2_nic *pfvf); 1108 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf); 1109 #endif 1110 1111 #if IS_ENABLED(CONFIG_MACSEC) 1112 /* MACSEC offload support */ 1113 int cn10k_mcs_init(struct otx2_nic *pfvf); 1114 void cn10k_mcs_free(struct otx2_nic *pfvf); 1115 void cn10k_handle_mcs_event(struct otx2_nic *pfvf, struct mcs_intr_info *event); 1116 #else 1117 static inline int cn10k_mcs_init(struct otx2_nic *pfvf) { return 0; } 1118 static inline void cn10k_mcs_free(struct otx2_nic *pfvf) {} 1119 static inline void cn10k_handle_mcs_event(struct otx2_nic *pfvf, 1120 struct mcs_intr_info *event) 1121 {} 1122 #endif /* CONFIG_MACSEC */ 1123 1124 /* qos support */ 1125 static inline void otx2_qos_init(struct otx2_nic *pfvf, int qos_txqs) 1126 { 1127 struct otx2_hw *hw = &pfvf->hw; 1128 1129 hw->tc_tx_queues = qos_txqs; 1130 INIT_LIST_HEAD(&pfvf->qos.qos_tree); 1131 mutex_init(&pfvf->qos.qos_lock); 1132 } 1133 1134 static inline void otx2_shutdown_qos(struct otx2_nic *pfvf) 1135 { 1136 mutex_destroy(&pfvf->qos.qos_lock); 1137 } 1138 1139 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1140 struct net_device *sb_dev); 1141 int otx2_get_txq_by_classid(struct otx2_nic *pfvf, u16 classid); 1142 void otx2_qos_config_txschq(struct otx2_nic *pfvf); 1143 void otx2_clean_qos_queues(struct otx2_nic *pfvf); 1144 int rvu_event_up_notify(struct otx2_nic *pf, struct rep_event *info); 1145 int otx2_setup_tc_cls_flower(struct otx2_nic *nic, 1146 struct flow_cls_offload *cls_flower); 1147 1148 static inline int mcam_entry_cmp(const void *a, const void *b) 1149 { 1150 return *(u16 *)a - *(u16 *)b; 1151 } 1152 #endif /* OTX2_COMMON_H */ 1153