1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_COMMON_H 9 #define OTX2_COMMON_H 10 11 #include <linux/ethtool.h> 12 #include <linux/pci.h> 13 #include <linux/iommu.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/ptp_clock_kernel.h> 16 #include <linux/timecounter.h> 17 #include <linux/soc/marvell/octeontx2/asm.h> 18 #include <net/macsec.h> 19 #include <net/pkt_cls.h> 20 #include <net/devlink.h> 21 #include <linux/time64.h> 22 #include <linux/dim.h> 23 #include <uapi/linux/if_macsec.h> 24 #include <net/page_pool/helpers.h> 25 26 #include <mbox.h> 27 #include <npc.h> 28 #include "otx2_reg.h" 29 #include "otx2_txrx.h" 30 #include "otx2_devlink.h" 31 #include <rvu.h> 32 #include <rvu_trace.h> 33 #include "qos.h" 34 #include "rep.h" 35 #include "cn10k_ipsec.h" 36 #include "cn20k.h" 37 38 /* IPv4 flag more fragment bit */ 39 #define IPV4_FLAG_MORE 0x20 40 41 /* PCI device IDs */ 42 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 43 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 44 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 45 46 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 47 #define PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF 0xB900 48 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00 49 50 #define PCI_DEVID_OCTEONTX2_SDP_REP 0xA0F7 51 52 /* PCI BAR nos */ 53 #define PCI_CFG_REG_BAR_NUM 2 54 #define PCI_MBOX_BAR_NUM 4 55 56 #define NAME_SIZE 32 57 58 #ifdef CONFIG_DCB 59 /* Max priority supported for PFC */ 60 #define NIX_PF_PFC_PRIO_MAX 8 61 #endif 62 63 /* Number of segments per SG structure */ 64 #define MAX_SEGS_PER_SG 3 65 66 irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq); 67 irqreturn_t cn20k_pfaf_mbox_intr_handler(int irq, void *pf_irq); 68 irqreturn_t cn20k_vfaf_mbox_intr_handler(int irq, void *vf_irq); 69 irqreturn_t cn20k_pfvf_mbox_intr_handler(int irq, void *pf_irq); 70 irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq); 71 72 enum arua_mapped_qtypes { 73 AURA_NIX_RQ, 74 AURA_NIX_SQ, 75 }; 76 77 /* NIX LF interrupts range*/ 78 #define NIX_LF_QINT_VEC_START 0x00 79 #define NIX_LF_CINT_VEC_START 0x40 80 #define NIX_LF_GINT_VEC 0x80 81 #define NIX_LF_ERR_VEC 0x81 82 #define NIX_LF_POISON_VEC 0x82 83 84 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 85 #define SEND_CQ_SKID 2000 86 87 #define OTX2_GET_RX_STATS(reg) \ 88 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 89 #define OTX2_GET_TX_STATS(reg) \ 90 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 91 92 struct otx2_lmt_info { 93 u64 lmt_addr; 94 u16 lmt_id; 95 }; 96 /* RSS configuration */ 97 struct otx2_rss_ctx { 98 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 99 }; 100 101 struct otx2_rss_info { 102 u8 enable; 103 u32 flowkey_cfg; 104 u16 rss_size; 105 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 106 u8 key[RSS_HASH_KEY_SIZE]; 107 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 108 }; 109 110 /* NIX (or NPC) RX errors */ 111 enum otx2_errlvl { 112 NPC_ERRLVL_RE, 113 NPC_ERRLVL_LID_LA, 114 NPC_ERRLVL_LID_LB, 115 NPC_ERRLVL_LID_LC, 116 NPC_ERRLVL_LID_LD, 117 NPC_ERRLVL_LID_LE, 118 NPC_ERRLVL_LID_LF, 119 NPC_ERRLVL_LID_LG, 120 NPC_ERRLVL_LID_LH, 121 NPC_ERRLVL_NIX = 0x0F, 122 }; 123 124 enum otx2_errcodes_re { 125 /* NPC_ERRLVL_RE errcodes */ 126 ERRCODE_FCS = 0x7, 127 ERRCODE_FCS_RCV = 0x8, 128 ERRCODE_UNDERSIZE = 0x10, 129 ERRCODE_OVERSIZE = 0x11, 130 ERRCODE_OL2_LEN_MISMATCH = 0x12, 131 /* NPC_ERRLVL_NIX errcodes */ 132 ERRCODE_OL3_LEN = 0x10, 133 ERRCODE_OL4_LEN = 0x11, 134 ERRCODE_OL4_CSUM = 0x12, 135 ERRCODE_IL3_LEN = 0x20, 136 ERRCODE_IL4_LEN = 0x21, 137 ERRCODE_IL4_CSUM = 0x22, 138 }; 139 140 enum otx2_xdp_action { 141 OTX2_XDP_TX = BIT(0), 142 OTX2_XDP_REDIRECT = BIT(1), 143 OTX2_AF_XDP_FRAME = BIT(2), 144 }; 145 146 struct otx2_dev_stats { 147 u64 rx_bytes; 148 u64 rx_frames; 149 u64 rx_ucast_frames; 150 u64 rx_bcast_frames; 151 u64 rx_mcast_frames; 152 u64 rx_drops; 153 154 u64 tx_bytes; 155 u64 tx_frames; 156 u64 tx_ucast_frames; 157 u64 tx_bcast_frames; 158 u64 tx_mcast_frames; 159 u64 tx_drops; 160 }; 161 162 /* Driver counted stats */ 163 struct otx2_drv_stats { 164 atomic_t rx_fcs_errs; 165 atomic_t rx_oversize_errs; 166 atomic_t rx_undersize_errs; 167 atomic_t rx_csum_errs; 168 atomic_t rx_len_errs; 169 atomic_t rx_other_errs; 170 }; 171 172 struct mbox { 173 struct otx2_mbox mbox; 174 struct work_struct mbox_wrk; 175 struct otx2_mbox mbox_up; 176 struct work_struct mbox_up_wrk; 177 struct otx2_nic *pfvf; 178 void *bbuf_base; /* Bounce buffer for mbox memory */ 179 struct mutex lock; /* serialize mailbox access */ 180 int num_msgs; /* mbox number of messages */ 181 int up_num_msgs; /* mbox_up number of messages */ 182 }; 183 184 /* Egress rate limiting definitions */ 185 #define MAX_BURST_EXPONENT 0x0FULL 186 #define MAX_BURST_MANTISSA 0xFFULL 187 #define MAX_BURST_SIZE 130816ULL 188 #define MAX_RATE_DIVIDER_EXPONENT 12ULL 189 #define MAX_RATE_EXPONENT 0x0FULL 190 #define MAX_RATE_MANTISSA 0xFFULL 191 192 /* Bitfields in NIX_TLX_PIR register */ 193 #define TLX_RATE_MANTISSA GENMASK_ULL(8, 1) 194 #define TLX_RATE_EXPONENT GENMASK_ULL(12, 9) 195 #define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13) 196 #define TLX_BURST_MANTISSA GENMASK_ULL(36, 29) 197 #define TLX_BURST_EXPONENT GENMASK_ULL(40, 37) 198 199 struct otx2_hw { 200 struct pci_dev *pdev; 201 struct otx2_rss_info rss_info; 202 u16 rx_queues; 203 u16 tx_queues; 204 u16 xdp_queues; 205 u16 tc_tx_queues; 206 u16 non_qos_queues; /* tx queues plus xdp queues */ 207 u16 max_queues; 208 u16 pool_cnt; 209 u16 rqpool_cnt; 210 u16 sqpool_cnt; 211 212 #define OTX2_DEFAULT_RBUF_LEN 2048 213 u16 rbuf_len; 214 u32 xqe_size; 215 216 /* NPA */ 217 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 218 u32 stack_pg_bytes; /* Size of stack page */ 219 u16 sqb_size; 220 221 /* NIX */ 222 u8 txschq_link_cfg_lvl; 223 u8 txschq_cnt[NIX_TXSCH_LVL_CNT]; 224 u8 txschq_aggr_lvl_rr_prio; 225 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 226 u16 matchall_ipolicer; 227 u32 dwrr_mtu; 228 u32 max_mtu; 229 u8 smq_link_type; 230 231 /* HW settings, coalescing etc */ 232 u16 rx_chan_base; 233 u16 tx_chan_base; 234 u8 rx_chan_cnt; 235 u8 tx_chan_cnt; 236 u16 cq_qcount_wait; 237 u16 cq_ecount_wait; 238 u16 rq_skid; 239 u8 cq_time_wait; 240 241 /* Segmentation */ 242 u8 lso_tsov4_idx; 243 u8 lso_tsov6_idx; 244 u8 lso_udpv4_idx; 245 u8 lso_udpv6_idx; 246 247 /* RSS */ 248 u8 flowkey_alg_idx; 249 250 /* MSI-X */ 251 u8 cint_cnt; /* CQ interrupt count */ 252 u16 npa_msixoff; /* Offset of NPA vectors */ 253 u16 nix_msixoff; /* Offset of NIX vectors */ 254 char *irq_name; 255 cpumask_var_t *affinity_mask; 256 struct pf_irq_data *pfvf_irq_devid[4]; 257 258 /* Stats */ 259 struct otx2_dev_stats dev_stats; 260 struct otx2_drv_stats drv_stats; 261 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 262 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 263 u64 cgx_fec_corr_blks; 264 u64 cgx_fec_uncorr_blks; 265 u8 cgx_links; /* No. of CGX links present in HW */ 266 u8 lbk_links; /* No. of LBK links present in HW */ 267 u8 tx_link; /* Transmit channel link number */ 268 #define HW_TSO 0 269 #define CN10K_MBOX 1 270 #define CN10K_LMTST 2 271 #define CN10K_RPM 3 272 #define CN10K_PTP_ONESTEP 4 273 #define CN10K_HW_MACSEC 5 274 #define QOS_CIR_PIR_SUPPORT 6 275 unsigned long cap_flag; 276 277 #define LMT_LINE_SIZE 128 278 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 279 u64 *lmt_base; 280 struct otx2_lmt_info __percpu *lmt_info; 281 }; 282 283 enum vfperm { 284 OTX2_RESET_VF_PERM, 285 OTX2_TRUSTED_VF, 286 }; 287 288 struct otx2_vf_config { 289 struct otx2_nic *pf; 290 struct delayed_work link_event_work; 291 bool intf_down; /* interface was either configured or not */ 292 u8 mac[ETH_ALEN]; 293 u16 vlan; 294 int tx_vtag_idx; 295 bool trusted; 296 }; 297 298 struct flr_work { 299 struct work_struct work; 300 struct otx2_nic *pf; 301 }; 302 303 struct refill_work { 304 struct delayed_work pool_refill_work; 305 struct otx2_nic *pf; 306 struct napi_struct *napi; 307 }; 308 309 /* PTPv2 originTimestamp structure */ 310 struct ptpv2_tstamp { 311 __be16 seconds_msb; /* 16 bits + */ 312 __be32 seconds_lsb; /* 32 bits = 48 bits*/ 313 __be32 nanoseconds; 314 } __packed; 315 316 struct otx2_ptp { 317 struct ptp_clock_info ptp_info; 318 struct ptp_clock *ptp_clock; 319 struct otx2_nic *nic; 320 321 struct cyclecounter cycle_counter; 322 struct timecounter time_counter; 323 324 struct delayed_work extts_work; 325 u64 last_extts; 326 u64 thresh; 327 328 struct ptp_pin_desc extts_config; 329 u64 (*convert_rx_ptp_tstmp)(u64 timestamp); 330 u64 (*convert_tx_ptp_tstmp)(u64 timestamp); 331 u64 (*ptp_tstamp2nsec)(const struct timecounter *time_counter, u64 timestamp); 332 struct delayed_work synctstamp_work; 333 u64 tstamp; 334 u32 base_ns; 335 }; 336 337 #define OTX2_HW_TIMESTAMP_LEN 8 338 339 struct otx2_mac_table { 340 u8 addr[ETH_ALEN]; 341 u16 mcam_entry; 342 bool inuse; 343 }; 344 345 struct otx2_flow_config { 346 u16 *flow_ent; 347 u16 *def_ent; 348 u16 nr_flows; 349 #define OTX2_DEFAULT_FLOWCOUNT 16 350 #define OTX2_DEFAULT_UNICAST_FLOWS 4 351 #define OTX2_MAX_VLAN_FLOWS 1 352 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 353 u16 unicast_offset; 354 u16 rx_vlan_offset; 355 u16 vf_vlan_offset; 356 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 357 #define OTX2_VF_VLAN_RX_INDEX 0 358 #define OTX2_VF_VLAN_TX_INDEX 1 359 u32 *bmap_to_dmacindex; 360 unsigned long *dmacflt_bmap; 361 struct list_head flow_list; 362 u32 dmacflt_max_flows; 363 u16 max_flows; 364 refcount_t mark_flows; 365 struct list_head flow_list_tc; 366 u8 ucast_flt_cnt; 367 bool ntuple; 368 u16 ntuple_cnt; 369 }; 370 371 struct dev_hw_ops { 372 int (*sq_aq_init)(void *dev, u16 qidx, u8 chan_offset, 373 u16 sqb_aura); 374 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 375 int size, int qidx); 376 int (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 377 void (*aura_freeptr)(void *dev, int aura, u64 buf); 378 irqreturn_t (*pfaf_mbox_intr_handler)(int irq, void *pf_irq); 379 irqreturn_t (*vfaf_mbox_intr_handler)(int irq, void *pf_irq); 380 irqreturn_t (*pfvf_mbox_intr_handler)(int irq, void *pf_irq); 381 }; 382 383 #define CN10K_MCS_SA_PER_SC 4 384 385 /* Stats which need to be accumulated in software because 386 * of shared counters in hardware. 387 */ 388 struct cn10k_txsc_stats { 389 u64 InPktsUntagged; 390 u64 InPktsNoTag; 391 u64 InPktsBadTag; 392 u64 InPktsUnknownSCI; 393 u64 InPktsNoSCI; 394 u64 InPktsOverrun; 395 }; 396 397 struct cn10k_rxsc_stats { 398 u64 InOctetsValidated; 399 u64 InOctetsDecrypted; 400 u64 InPktsUnchecked; 401 u64 InPktsDelayed; 402 u64 InPktsOK; 403 u64 InPktsInvalid; 404 u64 InPktsLate; 405 u64 InPktsNotValid; 406 u64 InPktsNotUsingSA; 407 u64 InPktsUnusedSA; 408 }; 409 410 struct cn10k_mcs_txsc { 411 struct macsec_secy *sw_secy; 412 struct cn10k_txsc_stats stats; 413 struct list_head entry; 414 enum macsec_validation_type last_validate_frames; 415 bool last_replay_protect; 416 u16 hw_secy_id_tx; 417 u16 hw_secy_id_rx; 418 u16 hw_flow_id; 419 u16 hw_sc_id; 420 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 421 u8 sa_bmap; 422 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 423 u8 encoding_sa; 424 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 425 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 426 bool vlan_dev; /* macsec running on VLAN ? */ 427 }; 428 429 struct cn10k_mcs_rxsc { 430 struct macsec_secy *sw_secy; 431 struct macsec_rx_sc *sw_rxsc; 432 struct cn10k_rxsc_stats stats; 433 struct list_head entry; 434 u16 hw_flow_id; 435 u16 hw_sc_id; 436 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 437 u8 sa_bmap; 438 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 439 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 440 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 441 }; 442 443 struct cn10k_mcs_cfg { 444 struct list_head txsc_list; 445 struct list_head rxsc_list; 446 }; 447 448 struct pf_irq_data { 449 u64 intr_status; 450 void (*pf_queue_work_hdlr)(struct mbox *mb, struct workqueue_struct *mw, 451 int first, int mdevs, u64 intr); 452 struct otx2_nic *pf; 453 int vec_num; 454 int start; 455 int mdevs; 456 }; 457 458 struct otx2_nic { 459 void __iomem *reg_base; 460 struct net_device *netdev; 461 struct dev_hw_ops *hw_ops; 462 void *iommu_domain; 463 u16 tx_max_pktlen; 464 u16 rbsize; /* Receive buffer size */ 465 466 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 467 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 468 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 469 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 470 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 471 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 472 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 473 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 474 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 475 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 476 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 477 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 478 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 479 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 480 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 481 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15) 482 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) 483 #define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17) 484 #define OTX2_FLAG_REP_MODE_ENABLED BIT_ULL(18) 485 #define OTX2_FLAG_PORT_UP BIT_ULL(19) 486 #define OTX2_FLAG_IPSEC_OFFLOAD_ENABLED BIT_ULL(20) 487 u64 flags; 488 u64 *cq_op_addr; 489 490 struct bpf_prog *xdp_prog; 491 struct otx2_qset qset; 492 struct otx2_hw hw; 493 struct pci_dev *pdev; 494 struct device *dev; 495 496 /* Mbox */ 497 struct mbox mbox; 498 struct mbox *mbox_pfvf; 499 struct workqueue_struct *mbox_wq; 500 struct workqueue_struct *mbox_pfvf_wq; 501 struct qmem *pfvf_mbox_addr; 502 503 u8 total_vfs; 504 u16 pcifunc; /* RVU PF_FUNC */ 505 u16 bpid[NIX_MAX_BPID_CHAN]; 506 struct otx2_vf_config *vf_configs; 507 struct cgx_link_user_info linfo; 508 509 /* NPC MCAM */ 510 struct otx2_flow_config *flow_cfg; 511 struct otx2_mac_table *mac_table; 512 513 u64 reset_count; 514 struct work_struct reset_task; 515 struct workqueue_struct *flr_wq; 516 struct flr_work *flr_wrk; 517 struct refill_work *refill_wrk; 518 struct workqueue_struct *otx2_wq; 519 struct work_struct rx_mode_work; 520 521 /* Ethtool stuff */ 522 u32 msg_enable; 523 524 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 525 int nix_blkaddr; 526 /* LMTST Lines info */ 527 struct qmem *dync_lmt; 528 u16 tot_lmt_lines; 529 u16 npa_lmt_lines; 530 u32 nix_lmt_size; 531 532 struct otx2_ptp *ptp; 533 struct hwtstamp_config tstamp; 534 535 unsigned long rq_bmap; 536 537 /* Devlink */ 538 struct otx2_devlink *dl; 539 /* PFC */ 540 u8 pfc_en; 541 #ifdef CONFIG_DCB 542 u8 *queue_to_pfc_map; 543 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 544 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX]; 545 #endif 546 /* qos */ 547 struct otx2_qos qos; 548 549 /* napi event count. It is needed for adaptive irq coalescing. */ 550 u32 napi_events; 551 552 #if IS_ENABLED(CONFIG_MACSEC) 553 struct cn10k_mcs_cfg *macsec_cfg; 554 #endif 555 556 #if IS_ENABLED(CONFIG_RVU_ESWITCH) 557 struct rep_dev **reps; 558 int rep_cnt; 559 u16 rep_pf_map[RVU_MAX_REP]; 560 u16 esw_mode; 561 #endif 562 563 /* Inline ipsec */ 564 struct cn10k_ipsec ipsec; 565 /* af_xdp zero-copy */ 566 unsigned long *af_xdp_zc_qidx; 567 }; 568 569 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 570 { 571 return (pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF) || 572 (pdev->device == PCI_DEVID_RVU_REP); 573 } 574 575 static inline bool is_96xx_A0(struct pci_dev *pdev) 576 { 577 return (pdev->revision == 0x00) && 578 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 579 } 580 581 static inline bool is_96xx_B0(struct pci_dev *pdev) 582 { 583 return (pdev->revision == 0x01) && 584 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 585 } 586 587 static inline bool is_otx2_sdp_rep(struct pci_dev *pdev) 588 { 589 return pdev->device == PCI_DEVID_OCTEONTX2_SDP_REP; 590 } 591 592 /* REVID for PCIe devices. 593 * Bits 0..1: minor pass, bit 3..2: major pass 594 * bits 7..4: midr id 595 */ 596 #define PCI_REVISION_ID_96XX 0x00 597 #define PCI_REVISION_ID_95XX 0x10 598 #define PCI_REVISION_ID_95XXN 0x20 599 #define PCI_REVISION_ID_98XX 0x30 600 #define PCI_REVISION_ID_95XXMM 0x40 601 #define PCI_REVISION_ID_95XXO 0xE0 602 603 static inline bool is_dev_otx2(struct pci_dev *pdev) 604 { 605 u8 midr = pdev->revision & 0xF0; 606 607 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 608 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 609 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 610 } 611 612 static inline bool is_dev_cn10kb(struct pci_dev *pdev) 613 { 614 return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF; 615 } 616 617 static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev) 618 { 619 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF && 620 (pdev->revision & 0xFF) == 0x54) 621 return true; 622 623 return false; 624 } 625 626 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 627 { 628 struct otx2_hw *hw = &pfvf->hw; 629 630 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 631 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 632 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 633 634 __set_bit(HW_TSO, &hw->cap_flag); 635 636 if (is_96xx_A0(pfvf->pdev)) { 637 __clear_bit(HW_TSO, &hw->cap_flag); 638 639 /* Time based irq coalescing is not supported */ 640 pfvf->hw.cq_qcount_wait = 0x0; 641 642 /* Due to HW issue previous silicons required minimum 643 * 600 unused CQE to avoid CQ overflow. 644 */ 645 pfvf->hw.rq_skid = 600; 646 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 647 } 648 if (is_96xx_B0(pfvf->pdev)) 649 __clear_bit(HW_TSO, &hw->cap_flag); 650 651 if (!is_dev_otx2(pfvf->pdev)) { 652 __set_bit(CN10K_MBOX, &hw->cap_flag); 653 __set_bit(CN10K_LMTST, &hw->cap_flag); 654 __set_bit(CN10K_RPM, &hw->cap_flag); 655 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag); 656 __set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag); 657 } 658 } 659 660 /* Register read/write APIs */ 661 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 662 { 663 u64 blkaddr; 664 665 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 666 case BLKTYPE_NIX: 667 blkaddr = nic->nix_blkaddr; 668 break; 669 case BLKTYPE_NPA: 670 blkaddr = BLKADDR_NPA; 671 break; 672 case BLKTYPE_CPT: 673 blkaddr = BLKADDR_CPT0; 674 break; 675 default: 676 blkaddr = BLKADDR_RVUM; 677 break; 678 } 679 680 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 681 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 682 683 return nic->reg_base + offset; 684 } 685 686 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 687 { 688 void __iomem *addr = otx2_get_regaddr(nic, offset); 689 690 writeq(val, addr); 691 } 692 693 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 694 { 695 void __iomem *addr = otx2_get_regaddr(nic, offset); 696 697 return readq(addr); 698 } 699 700 /* Mbox bounce buffer APIs */ 701 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 702 { 703 struct otx2_mbox *otx2_mbox; 704 struct otx2_mbox_dev *mdev; 705 706 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 707 if (!mbox->bbuf_base) 708 return -ENOMEM; 709 710 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 711 * prepare all mbox messages in bounce buffer instead of directly 712 * in hw mbox memory. 713 */ 714 otx2_mbox = &mbox->mbox; 715 mdev = &otx2_mbox->dev[0]; 716 mdev->mbase = mbox->bbuf_base; 717 718 otx2_mbox = &mbox->mbox_up; 719 mdev = &otx2_mbox->dev[0]; 720 mdev->mbase = mbox->bbuf_base; 721 return 0; 722 } 723 724 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 725 { 726 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 727 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 728 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 729 struct mbox_hdr *hdr; 730 u64 msg_size; 731 732 if (mdev->mbase == hw_mbase) 733 return; 734 735 hdr = hw_mbase + mbox->rx_start; 736 msg_size = hdr->msg_size; 737 738 if (msg_size > mbox->rx_size - msgs_offset) 739 msg_size = mbox->rx_size - msgs_offset; 740 741 /* Copy mbox messages from mbox memory to bounce buffer */ 742 memcpy(mdev->mbase + mbox->rx_start, 743 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 744 } 745 746 /* With the absence of API for 128-bit IO memory access for arm64, 747 * implement required operations at place. 748 */ 749 #if defined(CONFIG_ARM64) 750 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 751 { 752 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 753 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 754 } 755 756 static inline u64 otx2_atomic64_add(u64 incr, void __iomem *addr) 757 { 758 u64 __iomem *ptr = addr; 759 u64 result; 760 761 __asm__ volatile(".cpu generic+lse\n" 762 "ldadd %x[i], %x[r], [%[b]]" 763 : [r]"=r"(result), "+m"(*ptr) 764 : [i]"r"(incr), [b]"r"(ptr) 765 : "memory"); 766 return result; 767 } 768 769 #else 770 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 771 772 static inline u64 otx2_atomic64_add(u64 incr, void __iomem *addr) 773 { 774 return 0; 775 } 776 #endif 777 778 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 779 u64 *ptrs, u64 num_ptrs) 780 { 781 struct otx2_lmt_info *lmt_info; 782 u64 size = 0, count_eot = 0; 783 u64 tar_addr, val = 0; 784 785 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); 786 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 787 /* LMTID is same as AURA Id */ 788 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); 789 /* Set if [127:64] of last 128bit word has a valid pointer */ 790 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 791 /* Set AURA ID to free pointer */ 792 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 793 /* Target address for LMTST flush tells HW how many 128bit 794 * words are valid from NPA_LF_AURA_BATCH_FREE0. 795 * 796 * tar_addr[6:4] is LMTST size-1 in units of 128b. 797 */ 798 if (num_ptrs > 2) { 799 size = (sizeof(u64) * num_ptrs) / 16; 800 if (!count_eot) 801 size++; 802 tar_addr |= ((size - 1) & 0x7) << 4; 803 } 804 dma_wmb(); 805 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); 806 /* Perform LMTST flush */ 807 cn10k_lmt_flush(val, tar_addr); 808 } 809 810 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 811 { 812 struct otx2_nic *pfvf = dev; 813 u64 ptrs[2]; 814 815 ptrs[1] = buf; 816 get_cpu(); 817 /* Free only one buffer at time during init and teardown */ 818 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); 819 put_cpu(); 820 } 821 822 /* Alloc pointer from pool/aura */ 823 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 824 { 825 void __iomem *ptr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_ALLOCX(0)); 826 u64 incr = (u64)aura | BIT_ULL(63); 827 828 return otx2_atomic64_add(incr, ptr); 829 } 830 831 /* Free pointer to a pool/aura */ 832 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 833 { 834 struct otx2_nic *pfvf = dev; 835 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 836 837 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 838 } 839 840 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 841 { 842 if (type == AURA_NIX_SQ) 843 return pfvf->hw.rqpool_cnt + idx; 844 845 /* AURA_NIX_RQ */ 846 return idx; 847 } 848 849 /* Mbox APIs */ 850 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 851 { 852 int err; 853 854 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 855 return 0; 856 otx2_mbox_msg_send(&mbox->mbox, 0); 857 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 858 if (err) 859 return err; 860 861 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 862 } 863 864 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 865 { 866 int err; 867 868 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 869 return 0; 870 otx2_mbox_msg_send_up(&mbox->mbox_up, devid); 871 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 872 if (err) 873 return err; 874 875 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 876 } 877 878 /* Use this API to send mbox msgs in atomic context 879 * where sleeping is not allowed 880 */ 881 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 882 { 883 int err; 884 885 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 886 return 0; 887 otx2_mbox_msg_send(&mbox->mbox, 0); 888 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 889 if (err) 890 return err; 891 892 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 893 } 894 895 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 896 static struct _req_type __maybe_unused \ 897 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 898 { \ 899 struct _req_type *req; \ 900 u16 pcifunc = mbox->pfvf->pcifunc; \ 901 \ 902 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 903 &mbox->mbox, 0, sizeof(struct _req_type), \ 904 sizeof(struct _rsp_type)); \ 905 if (!req) \ 906 return NULL; \ 907 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 908 req->hdr.id = _id; \ 909 req->hdr.pcifunc = pcifunc; \ 910 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req), pcifunc); \ 911 return req; \ 912 } 913 914 MBOX_MESSAGES 915 #undef M 916 917 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 918 int \ 919 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 920 struct _req_type *req, \ 921 struct _rsp_type *rsp); \ 922 923 MBOX_UP_CGX_MESSAGES 924 MBOX_UP_MCS_MESSAGES 925 #undef M 926 927 /* Time to wait before watchdog kicks off */ 928 #define OTX2_TX_TIMEOUT (100 * HZ) 929 930 static inline bool is_otx2_vf(u16 pcifunc) 931 { 932 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 933 } 934 935 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 936 struct page *page, 937 size_t offset, size_t size, 938 enum dma_data_direction dir) 939 { 940 dma_addr_t iova; 941 942 iova = dma_map_page_attrs(pfvf->dev, page, 943 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 944 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 945 return (dma_addr_t)NULL; 946 return iova; 947 } 948 949 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 950 dma_addr_t addr, size_t size, 951 enum dma_data_direction dir) 952 { 953 dma_unmap_page_attrs(pfvf->dev, addr, size, 954 dir, DMA_ATTR_SKIP_CPU_SYNC); 955 } 956 957 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx) 958 { 959 u16 smq; 960 int idx; 961 962 #ifdef CONFIG_DCB 963 if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx]) 964 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx]; 965 #endif 966 /* check if qidx falls under QOS queues */ 967 if (qidx >= pfvf->hw.non_qos_queues) { 968 smq = pfvf->qos.qid_to_sqmap[qidx - pfvf->hw.non_qos_queues]; 969 } else { 970 idx = qidx % pfvf->hw.txschq_cnt[NIX_TXSCH_LVL_SMQ]; 971 smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][idx]; 972 } 973 974 return smq; 975 } 976 977 static inline u16 otx2_get_total_tx_queues(struct otx2_nic *pfvf) 978 { 979 return pfvf->hw.non_qos_queues + pfvf->hw.tc_tx_queues; 980 } 981 982 static inline u64 otx2_convert_rate(u64 rate) 983 { 984 u64 converted_rate; 985 986 /* Convert bytes per second to Mbps */ 987 converted_rate = rate * 8; 988 converted_rate = max_t(u64, converted_rate / 1000000, 1); 989 990 return converted_rate; 991 } 992 993 static inline int otx2_tc_flower_rule_cnt(struct otx2_nic *pfvf) 994 { 995 /* return here if MCAM entries not allocated */ 996 if (!pfvf->flow_cfg) 997 return 0; 998 999 return pfvf->flow_cfg->nr_flows; 1000 } 1001 1002 /* MSI-X APIs */ 1003 void otx2_free_cints(struct otx2_nic *pfvf, int n); 1004 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 1005 int otx2_set_mac_address(struct net_device *netdev, void *p); 1006 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 1007 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 1008 void otx2_get_mac_from_af(struct net_device *netdev); 1009 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 1010 int otx2_config_pause_frm(struct otx2_nic *pfvf); 1011 void otx2_setup_segmentation(struct otx2_nic *pfvf); 1012 int otx2_reset_mac_stats(struct otx2_nic *pfvf); 1013 1014 /* RVU block related APIs */ 1015 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 1016 int otx2_detach_resources(struct mbox *mbox); 1017 int otx2_config_npa(struct otx2_nic *pfvf); 1018 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 1019 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 1020 void otx2_aura_pool_free(struct otx2_nic *pfvf); 1021 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 1022 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 1023 int otx2_config_nix(struct otx2_nic *pfvf); 1024 int otx2_config_nix_queues(struct otx2_nic *pfvf); 1025 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en); 1026 int otx2_txsch_alloc(struct otx2_nic *pfvf); 1027 void otx2_txschq_stop(struct otx2_nic *pfvf); 1028 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq); 1029 void otx2_free_pending_sqe(struct otx2_nic *pfvf); 1030 void otx2_sqb_flush(struct otx2_nic *pfvf); 1031 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 1032 dma_addr_t *dma, int qidx, int idx); 1033 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 1034 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 1035 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 1036 int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable); 1037 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx); 1038 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 1039 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura); 1040 int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); 1041 int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); 1042 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 1043 dma_addr_t *dma); 1044 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1045 int stack_pages, int numptrs, int buf_size, int type); 1046 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1047 int pool_id, int numptrs); 1048 int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf); 1049 void otx2_free_queue_mem(struct otx2_qset *qset); 1050 int otx2_alloc_queue_mem(struct otx2_nic *pf); 1051 int otx2_init_hw_resources(struct otx2_nic *pfvf); 1052 void otx2_free_hw_resources(struct otx2_nic *pf); 1053 int otx2_wq_init(struct otx2_nic *pf); 1054 int otx2_check_pf_usable(struct otx2_nic *pf); 1055 int otx2_pfaf_mbox_init(struct otx2_nic *pf); 1056 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af); 1057 int otx2_realloc_msix_vectors(struct otx2_nic *pf); 1058 void otx2_pfaf_mbox_destroy(struct otx2_nic *pf); 1059 void otx2_disable_mbox_intr(struct otx2_nic *pf); 1060 void otx2_disable_napi(struct otx2_nic *pf); 1061 irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq); 1062 int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura); 1063 int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx); 1064 int otx2_set_hw_capabilities(struct otx2_nic *pfvf); 1065 1066 /* RSS configuration APIs*/ 1067 int otx2_rss_init(struct otx2_nic *pfvf); 1068 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 1069 void otx2_set_rss_key(struct otx2_nic *pfvf); 1070 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 1071 1072 /* Mbox handlers */ 1073 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1074 struct msix_offset_rsp *rsp); 1075 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1076 struct npa_lf_alloc_rsp *rsp); 1077 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1078 struct nix_lf_alloc_rsp *rsp); 1079 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1080 struct nix_txsch_alloc_rsp *rsp); 1081 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1082 struct cgx_stats_rsp *rsp); 1083 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1084 struct cgx_fec_stats_rsp *rsp); 1085 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 1086 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1087 struct nix_bp_cfg_rsp *rsp); 1088 1089 /* Device stats APIs */ 1090 void otx2_get_dev_stats(struct otx2_nic *pfvf); 1091 void otx2_get_stats64(struct net_device *netdev, 1092 struct rtnl_link_stats64 *stats); 1093 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 1094 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 1095 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 1096 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 1097 void otx2_set_ethtool_ops(struct net_device *netdev); 1098 void otx2vf_set_ethtool_ops(struct net_device *netdev); 1099 1100 int otx2_open(struct net_device *netdev); 1101 int otx2_stop(struct net_device *netdev); 1102 int otx2_set_real_num_queues(struct net_device *netdev, 1103 int tx_queues, int rx_queues); 1104 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd); 1105 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr); 1106 1107 /* MCAM filter related APIs */ 1108 int otx2_mcam_flow_init(struct otx2_nic *pf); 1109 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 1110 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 1111 void otx2_mcam_flow_del(struct otx2_nic *pf); 1112 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 1113 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 1114 int otx2_get_flow(struct otx2_nic *pfvf, 1115 struct ethtool_rxnfc *nfc, u32 location); 1116 int otx2_get_all_flows(struct otx2_nic *pfvf, 1117 struct ethtool_rxnfc *nfc, u32 *rule_locs); 1118 int otx2_add_flow(struct otx2_nic *pfvf, 1119 struct ethtool_rxnfc *nfc); 1120 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 1121 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 1122 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 1123 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 1124 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 1125 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 1126 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 1127 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, struct xdp_frame *xdpf, 1128 u64 iova, int len, u16 qidx, u16 flags); 1129 void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, struct xdp_frame *xdpf, 1130 u64 dma_addr, int len, int *offset, u16 flags); 1131 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 1132 int otx2_handle_ntuple_tc_features(struct net_device *netdev, 1133 netdev_features_t features); 1134 int otx2_smq_flush(struct otx2_nic *pfvf, int smq); 1135 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1136 u64 iova, int size); 1137 int otx2_mcam_entry_init(struct otx2_nic *pfvf); 1138 1139 /* tc support */ 1140 int otx2_init_tc(struct otx2_nic *nic); 1141 void otx2_shutdown_tc(struct otx2_nic *nic); 1142 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 1143 void *type_data); 1144 void otx2_tc_apply_ingress_police_rules(struct otx2_nic *nic); 1145 1146 /* CGX/RPM DMAC filters support */ 1147 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 1148 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1149 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1150 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos); 1151 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 1152 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 1153 1154 #ifdef CONFIG_DCB 1155 /* DCB support*/ 1156 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable); 1157 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf); 1158 int otx2_dcbnl_set_ops(struct net_device *dev); 1159 /* PFC support */ 1160 int otx2_pfc_txschq_config(struct otx2_nic *pfvf); 1161 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf); 1162 int otx2_pfc_txschq_update(struct otx2_nic *pfvf); 1163 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf); 1164 #endif 1165 1166 #if IS_ENABLED(CONFIG_MACSEC) 1167 /* MACSEC offload support */ 1168 int cn10k_mcs_init(struct otx2_nic *pfvf); 1169 void cn10k_mcs_free(struct otx2_nic *pfvf); 1170 void cn10k_handle_mcs_event(struct otx2_nic *pfvf, struct mcs_intr_info *event); 1171 #else 1172 static inline int cn10k_mcs_init(struct otx2_nic *pfvf) { return 0; } 1173 static inline void cn10k_mcs_free(struct otx2_nic *pfvf) {} 1174 static inline void cn10k_handle_mcs_event(struct otx2_nic *pfvf, 1175 struct mcs_intr_info *event) 1176 {} 1177 #endif /* CONFIG_MACSEC */ 1178 1179 /* qos support */ 1180 static inline void otx2_qos_init(struct otx2_nic *pfvf, int qos_txqs) 1181 { 1182 struct otx2_hw *hw = &pfvf->hw; 1183 1184 hw->tc_tx_queues = qos_txqs; 1185 INIT_LIST_HEAD(&pfvf->qos.qos_tree); 1186 mutex_init(&pfvf->qos.qos_lock); 1187 } 1188 1189 static inline void otx2_shutdown_qos(struct otx2_nic *pfvf) 1190 { 1191 mutex_destroy(&pfvf->qos.qos_lock); 1192 } 1193 1194 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1195 struct net_device *sb_dev); 1196 int otx2_get_txq_by_classid(struct otx2_nic *pfvf, u16 classid); 1197 void otx2_qos_config_txschq(struct otx2_nic *pfvf); 1198 void otx2_clean_qos_queues(struct otx2_nic *pfvf); 1199 int rvu_event_up_notify(struct otx2_nic *pf, struct rep_event *info); 1200 int otx2_setup_tc_cls_flower(struct otx2_nic *nic, 1201 struct flow_cls_offload *cls_flower); 1202 1203 static inline int mcam_entry_cmp(const void *a, const void *b) 1204 { 1205 return *(u16 *)a - *(u16 *)b; 1206 } 1207 1208 dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 1209 struct sk_buff *skb, int seg, int *len); 1210 void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg); 1211 int otx2_read_free_sqe(struct otx2_nic *pfvf, u16 qidx); 1212 void otx2_queue_vf_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 1213 int first, int mdevs, u64 intr); 1214 #endif /* OTX2_COMMON_H */ 1215