1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 #include <net/page_pool/helpers.h> 11 #include <net/tso.h> 12 #include <linux/bitfield.h> 13 #include <linux/dcbnl.h> 14 #include <net/xfrm.h> 15 16 #include "otx2_reg.h" 17 #include "otx2_common.h" 18 #include "otx2_struct.h" 19 #include "cn10k.h" 20 #include "otx2_xsk.h" 21 22 static bool otx2_is_pfc_enabled(struct otx2_nic *pfvf) 23 { 24 return IS_ENABLED(CONFIG_DCB) && !!pfvf->pfc_en; 25 } 26 27 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 28 struct otx2_nic *pfvf, int qidx) 29 { 30 u64 incr = (u64)qidx << 32; 31 void __iomem *ptr; 32 33 ptr = otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 34 stats->bytes = otx2_atomic64_add(incr, ptr); 35 36 ptr = otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 37 stats->pkts = otx2_atomic64_add(incr, ptr); 38 } 39 40 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 41 struct otx2_nic *pfvf, int qidx) 42 { 43 u64 incr = (u64)qidx << 32; 44 void __iomem *ptr; 45 46 ptr = otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 47 stats->bytes = otx2_atomic64_add(incr, ptr); 48 49 ptr = otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 50 stats->pkts = otx2_atomic64_add(incr, ptr); 51 } 52 53 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 54 { 55 struct msg_req *req; 56 57 if (!netif_running(pfvf->netdev)) 58 return; 59 60 mutex_lock(&pfvf->mbox.lock); 61 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 62 if (!req) { 63 mutex_unlock(&pfvf->mbox.lock); 64 return; 65 } 66 67 otx2_sync_mbox_msg(&pfvf->mbox); 68 mutex_unlock(&pfvf->mbox.lock); 69 } 70 71 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 72 { 73 struct msg_req *req; 74 75 if (!netif_running(pfvf->netdev)) 76 return; 77 mutex_lock(&pfvf->mbox.lock); 78 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 79 if (req) 80 otx2_sync_mbox_msg(&pfvf->mbox); 81 mutex_unlock(&pfvf->mbox.lock); 82 } 83 84 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 85 { 86 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 87 88 if (!pfvf->qset.rq) 89 return 0; 90 91 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 92 return 1; 93 } 94 EXPORT_SYMBOL(otx2_update_rq_stats); 95 96 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 97 { 98 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 99 100 if (!pfvf->qset.sq) 101 return 0; 102 103 if (qidx >= pfvf->hw.non_qos_queues) { 104 if (!test_bit(qidx - pfvf->hw.non_qos_queues, pfvf->qos.qos_sq_bmap)) 105 return 0; 106 } 107 108 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 109 return 1; 110 } 111 EXPORT_SYMBOL(otx2_update_sq_stats); 112 113 void otx2_get_dev_stats(struct otx2_nic *pfvf) 114 { 115 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 116 117 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 118 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 119 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 120 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 121 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 122 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 123 dev_stats->rx_mcast_frames + 124 dev_stats->rx_ucast_frames; 125 126 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 127 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 128 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 129 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 130 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 131 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 132 dev_stats->tx_mcast_frames + 133 dev_stats->tx_ucast_frames; 134 } 135 136 void otx2_get_stats64(struct net_device *netdev, 137 struct rtnl_link_stats64 *stats) 138 { 139 struct otx2_nic *pfvf = netdev_priv(netdev); 140 struct otx2_dev_stats *dev_stats; 141 142 otx2_get_dev_stats(pfvf); 143 144 dev_stats = &pfvf->hw.dev_stats; 145 stats->rx_bytes = dev_stats->rx_bytes; 146 stats->rx_packets = dev_stats->rx_frames; 147 stats->rx_dropped = dev_stats->rx_drops; 148 stats->multicast = dev_stats->rx_mcast_frames; 149 150 stats->tx_bytes = dev_stats->tx_bytes; 151 stats->tx_packets = dev_stats->tx_frames; 152 stats->tx_dropped = dev_stats->tx_drops; 153 } 154 EXPORT_SYMBOL(otx2_get_stats64); 155 156 /* Sync MAC address with RVU AF */ 157 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 158 { 159 struct nix_set_mac_addr *req; 160 int err; 161 162 mutex_lock(&pfvf->mbox.lock); 163 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 164 if (!req) { 165 mutex_unlock(&pfvf->mbox.lock); 166 return -ENOMEM; 167 } 168 169 ether_addr_copy(req->mac_addr, mac); 170 171 err = otx2_sync_mbox_msg(&pfvf->mbox); 172 mutex_unlock(&pfvf->mbox.lock); 173 return err; 174 } 175 176 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 177 struct net_device *netdev) 178 { 179 struct nix_get_mac_addr_rsp *rsp; 180 struct mbox_msghdr *msghdr; 181 struct msg_req *req; 182 int err; 183 184 mutex_lock(&pfvf->mbox.lock); 185 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 186 if (!req) { 187 mutex_unlock(&pfvf->mbox.lock); 188 return -ENOMEM; 189 } 190 191 err = otx2_sync_mbox_msg(&pfvf->mbox); 192 if (err) { 193 mutex_unlock(&pfvf->mbox.lock); 194 return err; 195 } 196 197 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 198 if (IS_ERR(msghdr)) { 199 mutex_unlock(&pfvf->mbox.lock); 200 return PTR_ERR(msghdr); 201 } 202 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 203 eth_hw_addr_set(netdev, rsp->mac_addr); 204 mutex_unlock(&pfvf->mbox.lock); 205 206 return 0; 207 } 208 209 int otx2_set_mac_address(struct net_device *netdev, void *p) 210 { 211 struct otx2_nic *pfvf = netdev_priv(netdev); 212 struct sockaddr *addr = p; 213 214 if (!is_valid_ether_addr(addr->sa_data)) 215 return -EADDRNOTAVAIL; 216 217 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 218 eth_hw_addr_set(netdev, addr->sa_data); 219 /* update dmac field in vlan offload rule */ 220 if (netif_running(netdev) && 221 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 222 otx2_install_rxvlan_offload_flow(pfvf); 223 /* update dmac address in ntuple and DMAC filter list */ 224 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 225 otx2_dmacflt_update_pfmac_flow(pfvf); 226 } else { 227 return -EPERM; 228 } 229 230 return 0; 231 } 232 EXPORT_SYMBOL(otx2_set_mac_address); 233 234 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 235 { 236 struct nix_frs_cfg *req; 237 u16 maxlen; 238 int err; 239 240 maxlen = pfvf->hw.max_mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 241 242 mutex_lock(&pfvf->mbox.lock); 243 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 244 if (!req) { 245 mutex_unlock(&pfvf->mbox.lock); 246 return -ENOMEM; 247 } 248 249 req->maxlen = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 250 251 /* Use max receive length supported by hardware for loopback devices */ 252 if (is_otx2_lbkvf(pfvf->pdev)) 253 req->maxlen = maxlen; 254 255 err = otx2_sync_mbox_msg(&pfvf->mbox); 256 mutex_unlock(&pfvf->mbox.lock); 257 return err; 258 } 259 EXPORT_SYMBOL(otx2_hw_set_mtu); 260 261 int otx2_config_pause_frm(struct otx2_nic *pfvf) 262 { 263 struct cgx_pause_frm_cfg *req; 264 int err; 265 266 if (is_otx2_lbkvf(pfvf->pdev) || is_otx2_sdp_rep(pfvf->pdev)) 267 return 0; 268 269 mutex_lock(&pfvf->mbox.lock); 270 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 271 if (!req) { 272 err = -ENOMEM; 273 goto unlock; 274 } 275 276 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 277 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 278 req->set = 1; 279 280 err = otx2_sync_mbox_msg(&pfvf->mbox); 281 unlock: 282 mutex_unlock(&pfvf->mbox.lock); 283 return err; 284 } 285 EXPORT_SYMBOL(otx2_config_pause_frm); 286 287 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 288 { 289 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 290 struct nix_rss_flowkey_cfg_rsp *rsp; 291 struct nix_rss_flowkey_cfg *req; 292 int err; 293 294 mutex_lock(&pfvf->mbox.lock); 295 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 296 if (!req) { 297 mutex_unlock(&pfvf->mbox.lock); 298 return -ENOMEM; 299 } 300 req->mcam_index = -1; /* Default or reserved index */ 301 req->flowkey_cfg = rss->flowkey_cfg; 302 req->group = DEFAULT_RSS_CONTEXT_GROUP; 303 304 err = otx2_sync_mbox_msg(&pfvf->mbox); 305 if (err) 306 goto fail; 307 308 rsp = (struct nix_rss_flowkey_cfg_rsp *) 309 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 310 if (IS_ERR(rsp)) { 311 err = PTR_ERR(rsp); 312 goto fail; 313 } 314 315 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 316 fail: 317 mutex_unlock(&pfvf->mbox.lock); 318 return err; 319 } 320 321 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 322 { 323 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 324 const int index = rss->rss_size * ctx_id; 325 struct mbox *mbox = &pfvf->mbox; 326 struct otx2_rss_ctx *rss_ctx; 327 struct nix_aq_enq_req *aq; 328 int idx, err; 329 330 mutex_lock(&mbox->lock); 331 rss_ctx = rss->rss_ctx[ctx_id]; 332 /* Get memory to put this msg */ 333 for (idx = 0; idx < rss->rss_size; idx++) { 334 /* Ignore the queue if AF_XDP zero copy is enabled */ 335 if (test_bit(rss_ctx->ind_tbl[idx], pfvf->af_xdp_zc_qidx)) 336 continue; 337 338 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 339 if (!aq) { 340 /* The shared memory buffer can be full. 341 * Flush it and retry 342 */ 343 err = otx2_sync_mbox_msg(mbox); 344 if (err) { 345 mutex_unlock(&mbox->lock); 346 return err; 347 } 348 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 349 if (!aq) { 350 mutex_unlock(&mbox->lock); 351 return -ENOMEM; 352 } 353 } 354 355 aq->rss.rq = rss_ctx->ind_tbl[idx]; 356 357 /* Fill AQ info */ 358 aq->qidx = index + idx; 359 aq->ctype = NIX_AQ_CTYPE_RSS; 360 aq->op = NIX_AQ_INSTOP_INIT; 361 } 362 err = otx2_sync_mbox_msg(mbox); 363 mutex_unlock(&mbox->lock); 364 return err; 365 } 366 367 void otx2_set_rss_key(struct otx2_nic *pfvf) 368 { 369 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 370 u64 *key = (u64 *)&rss->key[4]; 371 int idx; 372 373 /* 352bit or 44byte key needs to be configured as below 374 * NIX_LF_RX_SECRETX0 = key<351:288> 375 * NIX_LF_RX_SECRETX1 = key<287:224> 376 * NIX_LF_RX_SECRETX2 = key<223:160> 377 * NIX_LF_RX_SECRETX3 = key<159:96> 378 * NIX_LF_RX_SECRETX4 = key<95:32> 379 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 380 */ 381 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 382 (u64)(*((u32 *)&rss->key)) << 32); 383 idx = sizeof(rss->key) / sizeof(u64); 384 while (idx > 0) { 385 idx--; 386 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 387 } 388 } 389 390 int otx2_rss_init(struct otx2_nic *pfvf) 391 { 392 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 393 struct otx2_rss_ctx *rss_ctx; 394 int idx, ret = 0; 395 396 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 397 398 /* Init RSS key if it is not setup already */ 399 if (!rss->enable) 400 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 401 otx2_set_rss_key(pfvf); 402 403 if (!netif_is_rxfh_configured(pfvf->netdev)) { 404 /* Set RSS group 0 as default indirection table */ 405 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 406 GFP_KERNEL); 407 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 408 return -ENOMEM; 409 410 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 411 for (idx = 0; idx < rss->rss_size; idx++) 412 rss_ctx->ind_tbl[idx] = 413 ethtool_rxfh_indir_default(idx, 414 pfvf->hw.rx_queues); 415 } 416 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 417 if (ret) 418 return ret; 419 420 /* Flowkey or hash config to be used for generating flow tag */ 421 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 422 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 423 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 424 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 425 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 426 427 ret = otx2_set_flowkey_cfg(pfvf); 428 if (ret) 429 return ret; 430 431 rss->enable = true; 432 return 0; 433 } 434 435 /* Setup UDP segmentation algorithm in HW */ 436 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 437 { 438 struct nix_lso_format *field; 439 440 field = (struct nix_lso_format *)&lso->fields[0]; 441 lso->field_mask = GENMASK(18, 0); 442 443 /* IP's Length field */ 444 field->layer = NIX_TXLAYER_OL3; 445 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 446 field->offset = v4 ? 2 : 4; 447 field->sizem1 = 1; /* i.e 2 bytes */ 448 field->alg = NIX_LSOALG_ADD_PAYLEN; 449 field++; 450 451 /* No ID field in IPv6 header */ 452 if (v4) { 453 /* Increment IPID */ 454 field->layer = NIX_TXLAYER_OL3; 455 field->offset = 4; 456 field->sizem1 = 1; /* i.e 2 bytes */ 457 field->alg = NIX_LSOALG_ADD_SEGNUM; 458 field++; 459 } 460 461 /* Update length in UDP header */ 462 field->layer = NIX_TXLAYER_OL4; 463 field->offset = 4; 464 field->sizem1 = 1; 465 field->alg = NIX_LSOALG_ADD_PAYLEN; 466 } 467 468 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 469 void otx2_setup_segmentation(struct otx2_nic *pfvf) 470 { 471 struct nix_lso_format_cfg_rsp *rsp; 472 struct nix_lso_format_cfg *lso; 473 struct otx2_hw *hw = &pfvf->hw; 474 int err; 475 476 mutex_lock(&pfvf->mbox.lock); 477 478 /* UDPv4 segmentation */ 479 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 480 if (!lso) 481 goto fail; 482 483 /* Setup UDP/IP header fields that HW should update per segment */ 484 otx2_setup_udp_segmentation(lso, true); 485 486 err = otx2_sync_mbox_msg(&pfvf->mbox); 487 if (err) 488 goto fail; 489 490 rsp = (struct nix_lso_format_cfg_rsp *) 491 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 492 if (IS_ERR(rsp)) 493 goto fail; 494 495 hw->lso_udpv4_idx = rsp->lso_format_idx; 496 497 /* UDPv6 segmentation */ 498 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 499 if (!lso) 500 goto fail; 501 502 /* Setup UDP/IP header fields that HW should update per segment */ 503 otx2_setup_udp_segmentation(lso, false); 504 505 err = otx2_sync_mbox_msg(&pfvf->mbox); 506 if (err) 507 goto fail; 508 509 rsp = (struct nix_lso_format_cfg_rsp *) 510 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 511 if (IS_ERR(rsp)) 512 goto fail; 513 514 hw->lso_udpv6_idx = rsp->lso_format_idx; 515 mutex_unlock(&pfvf->mbox.lock); 516 return; 517 fail: 518 mutex_unlock(&pfvf->mbox.lock); 519 netdev_info(pfvf->netdev, 520 "Failed to get LSO index for UDP GSO offload, disabling\n"); 521 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 522 } 523 524 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 525 { 526 /* Configure CQE interrupt coalescing parameters 527 * 528 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 529 * set 1 less than cq_ecount_wait. And cq_time_wait is in 530 * usecs, convert that to 100ns count. 531 */ 532 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 533 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 534 ((u64)pfvf->hw.cq_qcount_wait << 32) | 535 (pfvf->hw.cq_ecount_wait - 1)); 536 } 537 538 static int otx2_alloc_pool_buf(struct otx2_nic *pfvf, struct otx2_pool *pool, 539 dma_addr_t *dma) 540 { 541 unsigned int offset = 0; 542 struct page *page; 543 size_t sz; 544 545 sz = SKB_DATA_ALIGN(pool->rbsize); 546 sz = ALIGN(sz, OTX2_ALIGN); 547 548 page = page_pool_alloc_frag(pool->page_pool, &offset, sz, GFP_ATOMIC); 549 if (unlikely(!page)) 550 return -ENOMEM; 551 552 *dma = page_pool_get_dma_addr(page) + offset; 553 return 0; 554 } 555 556 static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 557 dma_addr_t *dma, int qidx, int idx) 558 { 559 u8 *buf; 560 561 if (pool->xsk_pool) 562 return otx2_xsk_pool_alloc_buf(pfvf, pool, dma, idx); 563 564 if (pool->page_pool) 565 return otx2_alloc_pool_buf(pfvf, pool, dma); 566 567 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 568 if (unlikely(!buf)) 569 return -ENOMEM; 570 571 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 572 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 573 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 574 page_frag_free(buf); 575 return -ENOMEM; 576 } 577 578 return 0; 579 } 580 581 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 582 dma_addr_t *dma, int qidx, int idx) 583 { 584 int ret; 585 586 local_bh_disable(); 587 ret = __otx2_alloc_rbuf(pfvf, pool, dma, qidx, idx); 588 local_bh_enable(); 589 return ret; 590 } 591 592 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 593 dma_addr_t *dma) 594 { 595 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma, 596 cq->cq_idx, cq->pool_ptrs - 1))) 597 return -ENOMEM; 598 return 0; 599 } 600 601 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 602 { 603 struct otx2_nic *pfvf = netdev_priv(netdev); 604 605 schedule_work(&pfvf->reset_task); 606 } 607 EXPORT_SYMBOL(otx2_tx_timeout); 608 609 void otx2_get_mac_from_af(struct net_device *netdev) 610 { 611 struct otx2_nic *pfvf = netdev_priv(netdev); 612 int err; 613 614 err = otx2_hw_get_mac_addr(pfvf, netdev); 615 if (err) 616 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 617 618 /* If AF doesn't provide a valid MAC, generate a random one */ 619 if (!is_valid_ether_addr(netdev->dev_addr)) 620 eth_hw_addr_random(netdev); 621 } 622 EXPORT_SYMBOL(otx2_get_mac_from_af); 623 624 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc) 625 { 626 u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC]; 627 struct otx2_hw *hw = &pfvf->hw; 628 struct nix_txschq_config *req; 629 u64 schq, parent; 630 u64 dwrr_val; 631 632 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 633 634 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 635 if (!req) 636 return -ENOMEM; 637 638 req->lvl = lvl; 639 req->num_regs = 1; 640 641 schq_list = hw->txschq_list; 642 #ifdef CONFIG_DCB 643 if (txschq_for_pfc) 644 schq_list = pfvf->pfc_schq_list; 645 #endif 646 647 schq = schq_list[lvl][prio]; 648 /* Set topology e.t.c configuration */ 649 if (lvl == NIX_TXSCH_LVL_SMQ) { 650 req->reg[0] = NIX_AF_SMQX_CFG(schq); 651 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU; 652 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 653 (0x2ULL << 36); 654 /* Set link type for DWRR MTU selection on CN10K silicons */ 655 if (!is_dev_otx2(pfvf->pdev)) 656 req->regval[0] |= FIELD_PREP(GENMASK_ULL(58, 57), 657 (u64)hw->smq_link_type); 658 req->num_regs++; 659 /* MDQ config */ 660 parent = schq_list[NIX_TXSCH_LVL_TL4][prio]; 661 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 662 req->regval[1] = parent << 16; 663 req->num_regs++; 664 /* Set DWRR quantum */ 665 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 666 req->regval[2] = dwrr_val; 667 } else if (lvl == NIX_TXSCH_LVL_TL4) { 668 int sdp_chan = hw->tx_chan_base + prio; 669 670 if (is_otx2_sdp_rep(pfvf->pdev)) 671 prio = 0; 672 parent = schq_list[NIX_TXSCH_LVL_TL3][prio]; 673 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 674 req->regval[0] = (u64)parent << 16; 675 req->num_regs++; 676 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 677 req->regval[1] = dwrr_val; 678 if (is_otx2_sdp_rep(pfvf->pdev)) { 679 req->num_regs++; 680 req->reg[2] = NIX_AF_TL4X_SDP_LINK_CFG(schq); 681 req->regval[2] = BIT_ULL(12) | BIT_ULL(13) | 682 (sdp_chan & 0xff); 683 } 684 } else if (lvl == NIX_TXSCH_LVL_TL3) { 685 parent = schq_list[NIX_TXSCH_LVL_TL2][prio]; 686 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 687 req->regval[0] = (u64)parent << 16; 688 req->num_regs++; 689 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 690 req->regval[1] = dwrr_val; 691 if (lvl == hw->txschq_link_cfg_lvl && 692 !is_otx2_sdp_rep(pfvf->pdev)) { 693 req->num_regs++; 694 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 695 /* Enable this queue and backpressure 696 * and set relative channel 697 */ 698 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 699 } 700 } else if (lvl == NIX_TXSCH_LVL_TL2) { 701 parent = schq_list[NIX_TXSCH_LVL_TL1][prio]; 702 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 703 req->regval[0] = (u64)parent << 16; 704 705 req->num_regs++; 706 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 707 req->regval[1] = (u64)hw->txschq_aggr_lvl_rr_prio << 24 | dwrr_val; 708 709 if (lvl == hw->txschq_link_cfg_lvl && 710 !is_otx2_sdp_rep(pfvf->pdev)) { 711 req->num_regs++; 712 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 713 /* Enable this queue and backpressure 714 * and set relative channel 715 */ 716 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 717 } 718 } else if (lvl == NIX_TXSCH_LVL_TL1) { 719 /* Default config for TL1. 720 * For VF this is always ignored. 721 */ 722 723 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 724 * clip it to 16384, so configuring a 24bit max value 725 * will work on both OTx2 and CN10K. 726 */ 727 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 728 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 729 730 req->num_regs++; 731 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 732 req->regval[1] = hw->txschq_aggr_lvl_rr_prio << 1; 733 734 req->num_regs++; 735 req->reg[2] = NIX_AF_TL1X_CIR(schq); 736 req->regval[2] = 0; 737 } 738 739 return otx2_sync_mbox_msg(&pfvf->mbox); 740 } 741 EXPORT_SYMBOL(otx2_txschq_config); 742 743 int otx2_smq_flush(struct otx2_nic *pfvf, int smq) 744 { 745 struct nix_txschq_config *req; 746 int rc; 747 748 mutex_lock(&pfvf->mbox.lock); 749 750 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 751 if (!req) { 752 mutex_unlock(&pfvf->mbox.lock); 753 return -ENOMEM; 754 } 755 756 req->lvl = NIX_TXSCH_LVL_SMQ; 757 req->reg[0] = NIX_AF_SMQX_CFG(smq); 758 req->regval[0] |= BIT_ULL(49); 759 req->num_regs++; 760 761 rc = otx2_sync_mbox_msg(&pfvf->mbox); 762 mutex_unlock(&pfvf->mbox.lock); 763 return rc; 764 } 765 EXPORT_SYMBOL(otx2_smq_flush); 766 767 int otx2_txsch_alloc(struct otx2_nic *pfvf) 768 { 769 int chan_cnt = pfvf->hw.tx_chan_cnt; 770 struct nix_txsch_alloc_req *req; 771 struct nix_txsch_alloc_rsp *rsp; 772 int lvl, schq, rc; 773 774 /* Get memory to put this msg */ 775 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 776 if (!req) 777 return -ENOMEM; 778 779 /* Request one schq per level */ 780 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 781 req->schq[lvl] = 1; 782 783 if (is_otx2_sdp_rep(pfvf->pdev) && chan_cnt > 1) { 784 req->schq[NIX_TXSCH_LVL_SMQ] = chan_cnt; 785 req->schq[NIX_TXSCH_LVL_TL4] = chan_cnt; 786 } 787 788 rc = otx2_sync_mbox_msg(&pfvf->mbox); 789 if (rc) 790 return rc; 791 792 rsp = (struct nix_txsch_alloc_rsp *) 793 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 794 if (IS_ERR(rsp)) 795 return PTR_ERR(rsp); 796 797 /* Setup transmit scheduler list */ 798 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 799 pfvf->hw.txschq_cnt[lvl] = rsp->schq[lvl]; 800 for (schq = 0; schq < rsp->schq[lvl]; schq++) 801 pfvf->hw.txschq_list[lvl][schq] = 802 rsp->schq_list[lvl][schq]; 803 } 804 805 pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl; 806 pfvf->hw.txschq_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio; 807 808 return 0; 809 } 810 811 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq) 812 { 813 struct nix_txsch_free_req *free_req; 814 int err; 815 816 mutex_lock(&pfvf->mbox.lock); 817 818 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 819 if (!free_req) { 820 mutex_unlock(&pfvf->mbox.lock); 821 netdev_err(pfvf->netdev, 822 "Failed alloc txschq free req\n"); 823 return; 824 } 825 826 free_req->schq_lvl = lvl; 827 free_req->schq = schq; 828 829 err = otx2_sync_mbox_msg(&pfvf->mbox); 830 if (err) { 831 netdev_err(pfvf->netdev, 832 "Failed stop txschq %d at level %d\n", schq, lvl); 833 } 834 835 mutex_unlock(&pfvf->mbox.lock); 836 } 837 EXPORT_SYMBOL(otx2_txschq_free_one); 838 839 void otx2_txschq_stop(struct otx2_nic *pfvf) 840 { 841 int lvl, schq, idx; 842 843 /* free non QOS TLx nodes */ 844 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 845 for (idx = 0; idx < pfvf->hw.txschq_cnt[lvl]; idx++) { 846 otx2_txschq_free_one(pfvf, lvl, 847 pfvf->hw.txschq_list[lvl][idx]); 848 } 849 } 850 851 /* Clear the txschq list */ 852 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 853 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 854 pfvf->hw.txschq_list[lvl][schq] = 0; 855 } 856 857 } 858 859 void otx2_sqb_flush(struct otx2_nic *pfvf) 860 { 861 int qidx, sqe_tail, sqe_head; 862 struct otx2_snd_queue *sq; 863 void __iomem *ptr; 864 u64 incr, val; 865 866 ptr = otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 867 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 868 sq = &pfvf->qset.sq[qidx]; 869 if (!sq->sqb_ptrs) 870 continue; 871 872 incr = (u64)qidx << 32; 873 val = otx2_atomic64_add(incr, ptr); 874 sqe_head = (val >> 20) & 0x3F; 875 sqe_tail = (val >> 28) & 0x3F; 876 if (sqe_head != sqe_tail) 877 usleep_range(50, 60); 878 } 879 } 880 881 /* RED and drop levels of CQ on packet reception. 882 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 883 */ 884 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 885 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 886 887 /* RED and drop levels of AURA for packet reception. 888 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 889 * Eg: For RQ length 1K, for pass/drop level 204/230. 890 * RED accepts pkts if free pointers > 102 & <= 205. 891 * Drops pkts if free pointers < 102. 892 */ 893 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 894 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 895 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 896 897 int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 898 { 899 struct otx2_qset *qset = &pfvf->qset; 900 struct nix_aq_enq_req *aq; 901 902 /* Get memory to put this msg */ 903 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 904 if (!aq) 905 return -ENOMEM; 906 907 aq->rq.cq = qidx; 908 aq->rq.ena = 1; 909 aq->rq.pb_caching = 1; 910 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 911 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 912 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 913 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 914 aq->rq.qint_idx = 0; 915 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 916 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 917 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 918 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 919 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 920 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 921 922 /* Fill AQ info */ 923 aq->qidx = qidx; 924 aq->ctype = NIX_AQ_CTYPE_RQ; 925 aq->op = NIX_AQ_INSTOP_INIT; 926 927 return otx2_sync_mbox_msg(&pfvf->mbox); 928 } 929 930 int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura) 931 { 932 struct otx2_nic *pfvf = dev; 933 struct otx2_snd_queue *sq; 934 struct nix_aq_enq_req *aq; 935 936 sq = &pfvf->qset.sq[qidx]; 937 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 938 /* Get memory to put this msg */ 939 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 940 if (!aq) 941 return -ENOMEM; 942 943 aq->sq.cq = pfvf->hw.rx_queues + qidx; 944 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 945 aq->sq.cq_ena = 1; 946 aq->sq.ena = 1; 947 aq->sq.smq = otx2_get_smq_idx(pfvf, qidx); 948 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 949 aq->sq.default_chan = pfvf->hw.tx_chan_base + chan_offset; 950 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 951 aq->sq.sqb_aura = sqb_aura; 952 aq->sq.sq_int_ena = NIX_SQINT_BITS; 953 aq->sq.qint_idx = 0; 954 /* Due pipelining impact minimum 2000 unused SQ CQE's 955 * need to maintain to avoid CQ overflow. 956 */ 957 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 958 959 /* Fill AQ info */ 960 aq->qidx = qidx; 961 aq->ctype = NIX_AQ_CTYPE_SQ; 962 aq->op = NIX_AQ_INSTOP_INIT; 963 964 return otx2_sync_mbox_msg(&pfvf->mbox); 965 } 966 967 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 968 { 969 struct otx2_qset *qset = &pfvf->qset; 970 struct otx2_snd_queue *sq; 971 struct otx2_pool *pool; 972 u8 chan_offset; 973 int err; 974 975 pool = &pfvf->qset.pool[sqb_aura]; 976 sq = &qset->sq[qidx]; 977 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 978 sq->sqe_cnt = qset->sqe_cnt; 979 980 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 981 if (err) 982 return err; 983 984 /* Allocate memory for NIX SQE (which includes NIX SG) and CPT SG. 985 * SG of NIX and CPT are same in size. Allocate memory for CPT SG 986 * same as NIX SQE for base address alignment. 987 * Layout of a NIX SQE and CPT SG entry: 988 * ----------------------------- 989 * | CPT Scatter Gather | 990 * | (SQE SIZE) | 991 * | | 992 * ----------------------------- 993 * | NIX SQE | 994 * | (SQE SIZE) | 995 * | | 996 * ----------------------------- 997 */ 998 err = qmem_alloc(pfvf->dev, &sq->sqe_ring, qset->sqe_cnt, 999 sq->sqe_size * 2); 1000 if (err) 1001 return err; 1002 1003 err = qmem_alloc(pfvf->dev, &sq->cpt_resp, qset->sqe_cnt, 64); 1004 if (err) 1005 return err; 1006 1007 if (qidx < pfvf->hw.tx_queues) { 1008 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 1009 TSO_HEADER_SIZE); 1010 if (err) 1011 return err; 1012 } 1013 1014 sq->sqe_base = sq->sqe->base; 1015 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 1016 if (!sq->sg) 1017 return -ENOMEM; 1018 1019 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) { 1020 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 1021 sizeof(*sq->timestamps)); 1022 if (err) { 1023 kfree(sq->sg); 1024 sq->sg = NULL; 1025 return err; 1026 } 1027 } 1028 1029 sq->head = 0; 1030 sq->cons_head = 0; 1031 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 1032 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 1033 /* Set SQE threshold to 10% of total SQEs */ 1034 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 1035 sq->aura_id = sqb_aura; 1036 sq->aura_fc_addr = pool->fc_addr->base; 1037 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 1038 1039 sq->stats.bytes = 0; 1040 sq->stats.pkts = 0; 1041 /* Attach XSK_BUFF_POOL to XDP queue */ 1042 if (qidx > pfvf->hw.xdp_queues) 1043 otx2_attach_xsk_buff(pfvf, sq, (qidx - pfvf->hw.xdp_queues)); 1044 1045 1046 chan_offset = qidx % pfvf->hw.tx_chan_cnt; 1047 err = pfvf->hw_ops->sq_aq_init(pfvf, qidx, chan_offset, sqb_aura); 1048 if (err) { 1049 kfree(sq->sg); 1050 sq->sg = NULL; 1051 return err; 1052 } 1053 1054 return 0; 1055 1056 } 1057 1058 int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 1059 { 1060 struct otx2_qset *qset = &pfvf->qset; 1061 int err, pool_id, non_xdp_queues; 1062 struct nix_aq_enq_req *aq; 1063 struct otx2_cq_queue *cq; 1064 struct otx2_pool *pool; 1065 1066 cq = &qset->cq[qidx]; 1067 cq->cq_idx = qidx; 1068 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues; 1069 if (qidx < pfvf->hw.rx_queues) { 1070 cq->cq_type = CQ_RX; 1071 cq->cint_idx = qidx; 1072 cq->cqe_cnt = qset->rqe_cnt; 1073 if (pfvf->xdp_prog) { 1074 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0); 1075 pool = &qset->pool[qidx]; 1076 if (pool->xsk_pool) { 1077 xdp_rxq_info_reg_mem_model(&cq->xdp_rxq, 1078 MEM_TYPE_XSK_BUFF_POOL, 1079 NULL); 1080 xsk_pool_set_rxq_info(pool->xsk_pool, &cq->xdp_rxq); 1081 } else if (pool->page_pool) { 1082 xdp_rxq_info_reg_mem_model(&cq->xdp_rxq, 1083 MEM_TYPE_PAGE_POOL, 1084 pool->page_pool); 1085 } 1086 } 1087 } else if (qidx < non_xdp_queues) { 1088 cq->cq_type = CQ_TX; 1089 cq->cint_idx = qidx - pfvf->hw.rx_queues; 1090 cq->cqe_cnt = qset->sqe_cnt; 1091 } else { 1092 if (pfvf->hw.xdp_queues && 1093 qidx < non_xdp_queues + pfvf->hw.xdp_queues) { 1094 cq->cq_type = CQ_XDP; 1095 cq->cint_idx = qidx - non_xdp_queues; 1096 cq->cqe_cnt = qset->sqe_cnt; 1097 } else { 1098 cq->cq_type = CQ_QOS; 1099 cq->cint_idx = qidx - non_xdp_queues - 1100 pfvf->hw.xdp_queues; 1101 cq->cqe_cnt = qset->sqe_cnt; 1102 } 1103 } 1104 cq->cqe_size = pfvf->qset.xqe_size; 1105 1106 /* Allocate memory for CQEs */ 1107 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 1108 if (err) 1109 return err; 1110 1111 /* Save CQE CPU base for faster reference */ 1112 cq->cqe_base = cq->cqe->base; 1113 /* In case where all RQs auras point to single pool, 1114 * all CQs receive buffer pool also point to same pool. 1115 */ 1116 pool_id = ((cq->cq_type == CQ_RX) && 1117 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 1118 cq->rbpool = &qset->pool[pool_id]; 1119 cq->refill_task_sched = false; 1120 1121 /* Get memory to put this msg */ 1122 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 1123 if (!aq) 1124 return -ENOMEM; 1125 1126 aq->cq.ena = 1; 1127 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 1128 aq->cq.caching = 1; 1129 aq->cq.base = cq->cqe->iova; 1130 aq->cq.cint_idx = cq->cint_idx; 1131 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 1132 aq->cq.qint_idx = 0; 1133 aq->cq.avg_level = 255; 1134 1135 if (qidx < pfvf->hw.rx_queues) { 1136 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 1137 aq->cq.drop_ena = 1; 1138 1139 if (!is_otx2_lbkvf(pfvf->pdev)) { 1140 /* Enable receive CQ backpressure */ 1141 aq->cq.bp_ena = 1; 1142 #ifdef CONFIG_DCB 1143 aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]]; 1144 #else 1145 aq->cq.bpid = pfvf->bpid[0]; 1146 #endif 1147 1148 /* Set backpressure level is same as cq pass level */ 1149 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 1150 } 1151 } 1152 1153 /* Fill AQ info */ 1154 aq->qidx = qidx; 1155 aq->ctype = NIX_AQ_CTYPE_CQ; 1156 aq->op = NIX_AQ_INSTOP_INIT; 1157 1158 return otx2_sync_mbox_msg(&pfvf->mbox); 1159 } 1160 1161 static void otx2_pool_refill_task(struct work_struct *work) 1162 { 1163 struct otx2_cq_queue *cq; 1164 struct refill_work *wrk; 1165 struct otx2_nic *pfvf; 1166 int qidx; 1167 1168 wrk = container_of(work, struct refill_work, pool_refill_work.work); 1169 pfvf = wrk->pf; 1170 qidx = wrk - pfvf->refill_wrk; 1171 cq = &pfvf->qset.cq[qidx]; 1172 1173 cq->refill_task_sched = false; 1174 1175 local_bh_disable(); 1176 napi_schedule(wrk->napi); 1177 local_bh_enable(); 1178 } 1179 1180 int otx2_config_nix_queues(struct otx2_nic *pfvf) 1181 { 1182 int qidx, err; 1183 1184 /* Initialize RX queues */ 1185 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 1186 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 1187 1188 err = otx2_rq_init(pfvf, qidx, lpb_aura); 1189 if (err) 1190 return err; 1191 } 1192 1193 /* Initialize TX queues */ 1194 for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) { 1195 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1196 1197 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1198 if (err) 1199 return err; 1200 } 1201 1202 /* Initialize completion queues */ 1203 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1204 err = otx2_cq_init(pfvf, qidx); 1205 if (err) 1206 return err; 1207 } 1208 1209 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, 1210 NIX_LF_CQ_OP_STATUS); 1211 1212 /* Initialize work queue for receive buffer refill */ 1213 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1214 sizeof(struct refill_work), GFP_KERNEL); 1215 if (!pfvf->refill_wrk) 1216 return -ENOMEM; 1217 1218 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1219 pfvf->refill_wrk[qidx].pf = pfvf; 1220 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1221 otx2_pool_refill_task); 1222 } 1223 return 0; 1224 } 1225 1226 int otx2_config_nix(struct otx2_nic *pfvf) 1227 { 1228 struct nix_lf_alloc_req *nixlf; 1229 struct nix_lf_alloc_rsp *rsp; 1230 int err; 1231 1232 pfvf->qset.xqe_size = pfvf->hw.xqe_size; 1233 1234 /* Get memory to put this msg */ 1235 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1236 if (!nixlf) 1237 return -ENOMEM; 1238 1239 /* Set RQ/SQ/CQ counts */ 1240 nixlf->rq_cnt = pfvf->hw.rx_queues; 1241 nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf); 1242 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1243 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1244 nixlf->rss_grps = MAX_RSS_GROUPS; 1245 nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64; 1246 /* We don't know absolute NPA LF idx attached. 1247 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1248 * NPA LF attached to this RVU PF/VF. 1249 */ 1250 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1251 /* Disable alignment pad, enable L2 length check, 1252 * enable L4 TCP/UDP checksum verification. 1253 */ 1254 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1255 1256 err = otx2_sync_mbox_msg(&pfvf->mbox); 1257 if (err) 1258 return err; 1259 1260 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1261 &nixlf->hdr); 1262 if (IS_ERR(rsp)) 1263 return PTR_ERR(rsp); 1264 1265 if (rsp->qints < 1) 1266 return -ENXIO; 1267 1268 return rsp->hdr.rc; 1269 } 1270 1271 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1272 { 1273 struct otx2_qset *qset = &pfvf->qset; 1274 struct otx2_hw *hw = &pfvf->hw; 1275 struct otx2_snd_queue *sq; 1276 int sqb, qidx; 1277 u64 iova, pa; 1278 1279 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 1280 sq = &qset->sq[qidx]; 1281 if (!sq->sqb_ptrs) 1282 continue; 1283 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1284 if (!sq->sqb_ptrs[sqb]) 1285 continue; 1286 iova = sq->sqb_ptrs[sqb]; 1287 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1288 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1289 DMA_FROM_DEVICE, 1290 DMA_ATTR_SKIP_CPU_SYNC); 1291 put_page(virt_to_page(phys_to_virt(pa))); 1292 } 1293 sq->sqb_count = 0; 1294 } 1295 } 1296 1297 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1298 u64 iova, int size) 1299 { 1300 struct page *page; 1301 u64 pa; 1302 1303 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1304 page = virt_to_head_page(phys_to_virt(pa)); 1305 if (pool->page_pool) { 1306 page_pool_put_full_page(pool->page_pool, page, true); 1307 } else if (pool->xsk_pool) { 1308 /* Note: No way of identifying xdp_buff */ 1309 } else { 1310 dma_unmap_page_attrs(pfvf->dev, iova, size, 1311 DMA_FROM_DEVICE, 1312 DMA_ATTR_SKIP_CPU_SYNC); 1313 1314 put_page(page); 1315 } 1316 } 1317 1318 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1319 { 1320 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1321 struct otx2_pool *pool; 1322 u64 iova; 1323 int idx; 1324 1325 if (type == AURA_NIX_SQ) { 1326 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1327 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1328 size = pfvf->hw.sqb_size; 1329 } 1330 if (type == AURA_NIX_RQ) { 1331 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1332 pool_end = pfvf->hw.rqpool_cnt; 1333 size = pfvf->rbsize; 1334 } 1335 1336 /* Free SQB and RQB pointers from the aura pool */ 1337 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1338 pool = &pfvf->qset.pool[pool_id]; 1339 iova = otx2_aura_allocptr(pfvf, pool_id); 1340 while (iova) { 1341 if (type == AURA_NIX_RQ) 1342 iova -= OTX2_HEAD_ROOM; 1343 otx2_free_bufs(pfvf, pool, iova, size); 1344 iova = otx2_aura_allocptr(pfvf, pool_id); 1345 } 1346 1347 for (idx = 0 ; idx < pool->xdp_cnt; idx++) { 1348 if (!pool->xdp[idx]) 1349 continue; 1350 1351 xsk_buff_free(pool->xdp[idx]); 1352 } 1353 } 1354 } 1355 1356 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1357 { 1358 struct otx2_pool *pool; 1359 int pool_id; 1360 1361 if (!pfvf->qset.pool) 1362 return; 1363 1364 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1365 pool = &pfvf->qset.pool[pool_id]; 1366 qmem_free(pfvf->dev, pool->stack); 1367 qmem_free(pfvf->dev, pool->fc_addr); 1368 page_pool_destroy(pool->page_pool); 1369 devm_kfree(pfvf->dev, pool->xdp); 1370 pool->xsk_pool = NULL; 1371 } 1372 devm_kfree(pfvf->dev, pfvf->qset.pool); 1373 pfvf->qset.pool = NULL; 1374 } 1375 1376 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1377 int pool_id, int numptrs) 1378 { 1379 struct npa_aq_enq_req *aq; 1380 struct otx2_pool *pool; 1381 int err; 1382 1383 pool = &pfvf->qset.pool[pool_id]; 1384 1385 /* Allocate memory for HW to update Aura count. 1386 * Alloc one cache line, so that it fits all FC_STYPE modes. 1387 */ 1388 if (!pool->fc_addr) { 1389 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1390 if (err) 1391 return err; 1392 } 1393 1394 /* Initialize this aura's context via AF */ 1395 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1396 if (!aq) { 1397 /* Shared mbox memory buffer is full, flush it and retry */ 1398 err = otx2_sync_mbox_msg(&pfvf->mbox); 1399 if (err) 1400 return err; 1401 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1402 if (!aq) 1403 return -ENOMEM; 1404 } 1405 1406 aq->aura_id = aura_id; 1407 /* Will be filled by AF with correct pool context address */ 1408 aq->aura.pool_addr = pool_id; 1409 aq->aura.pool_caching = 1; 1410 aq->aura.shift = ilog2(numptrs) - 8; 1411 aq->aura.count = numptrs; 1412 aq->aura.limit = numptrs; 1413 aq->aura.avg_level = 255; 1414 aq->aura.ena = 1; 1415 aq->aura.fc_ena = 1; 1416 aq->aura.fc_addr = pool->fc_addr->iova; 1417 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1418 1419 /* Enable backpressure for RQ aura */ 1420 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1421 aq->aura.bp_ena = 0; 1422 /* If NIX1 LF is attached then specify NIX1_RX. 1423 * 1424 * Below NPA_AURA_S[BP_ENA] is set according to the 1425 * NPA_BPINTF_E enumeration given as: 1426 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1427 * NIX0_RX is 0x0 + 0*0x1 = 0 1428 * NIX1_RX is 0x0 + 1*0x1 = 1 1429 * But in HRM it is given that 1430 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1431 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1432 * enumerated by NPA_BPINTF_E." 1433 */ 1434 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1435 aq->aura.bp_ena = 1; 1436 #ifdef CONFIG_DCB 1437 aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]]; 1438 #else 1439 aq->aura.nix0_bpid = pfvf->bpid[0]; 1440 #endif 1441 1442 /* Set backpressure level for RQ's Aura */ 1443 aq->aura.bp = RQ_BP_LVL_AURA; 1444 } 1445 1446 /* Fill AQ info */ 1447 aq->ctype = NPA_AQ_CTYPE_AURA; 1448 aq->op = NPA_AQ_INSTOP_INIT; 1449 1450 return 0; 1451 } 1452 1453 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1454 int stack_pages, int numptrs, int buf_size, int type) 1455 { 1456 struct page_pool_params pp_params = { 0 }; 1457 struct xsk_buff_pool *xsk_pool; 1458 struct npa_aq_enq_req *aq; 1459 struct otx2_pool *pool; 1460 int err; 1461 1462 pool = &pfvf->qset.pool[pool_id]; 1463 /* Alloc memory for stack which is used to store buffer pointers */ 1464 err = qmem_alloc(pfvf->dev, &pool->stack, 1465 stack_pages, pfvf->hw.stack_pg_bytes); 1466 if (err) 1467 return err; 1468 1469 pool->rbsize = buf_size; 1470 1471 /* Initialize this pool's context via AF */ 1472 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1473 if (!aq) { 1474 /* Shared mbox memory buffer is full, flush it and retry */ 1475 err = otx2_sync_mbox_msg(&pfvf->mbox); 1476 if (err) { 1477 qmem_free(pfvf->dev, pool->stack); 1478 return err; 1479 } 1480 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1481 if (!aq) { 1482 qmem_free(pfvf->dev, pool->stack); 1483 return -ENOMEM; 1484 } 1485 } 1486 1487 aq->aura_id = pool_id; 1488 aq->pool.stack_base = pool->stack->iova; 1489 aq->pool.stack_caching = 1; 1490 aq->pool.ena = 1; 1491 aq->pool.buf_size = buf_size / 128; 1492 aq->pool.stack_max_pages = stack_pages; 1493 aq->pool.shift = ilog2(numptrs) - 8; 1494 aq->pool.ptr_start = 0; 1495 aq->pool.ptr_end = ~0ULL; 1496 1497 /* Fill AQ info */ 1498 aq->ctype = NPA_AQ_CTYPE_POOL; 1499 aq->op = NPA_AQ_INSTOP_INIT; 1500 1501 if (type != AURA_NIX_RQ) 1502 return 0; 1503 1504 if (!test_bit(pool_id, pfvf->af_xdp_zc_qidx)) { 1505 pp_params.order = get_order(buf_size); 1506 pp_params.flags = PP_FLAG_DMA_MAP; 1507 pp_params.pool_size = min(OTX2_PAGE_POOL_SZ, numptrs); 1508 pp_params.nid = NUMA_NO_NODE; 1509 pp_params.dev = pfvf->dev; 1510 pp_params.dma_dir = DMA_FROM_DEVICE; 1511 pool->page_pool = page_pool_create(&pp_params); 1512 if (IS_ERR(pool->page_pool)) { 1513 netdev_err(pfvf->netdev, "Creation of page pool failed\n"); 1514 return PTR_ERR(pool->page_pool); 1515 } 1516 return 0; 1517 } 1518 1519 /* Set XSK pool to support AF_XDP zero-copy */ 1520 xsk_pool = xsk_get_pool_from_qid(pfvf->netdev, pool_id); 1521 if (xsk_pool) { 1522 pool->xsk_pool = xsk_pool; 1523 pool->xdp_cnt = numptrs; 1524 pool->xdp = devm_kcalloc(pfvf->dev, 1525 numptrs, sizeof(struct xdp_buff *), GFP_KERNEL); 1526 if (IS_ERR(pool->xdp)) { 1527 netdev_err(pfvf->netdev, "Creation of xsk pool failed\n"); 1528 return PTR_ERR(pool->xdp); 1529 } 1530 } 1531 1532 return 0; 1533 } 1534 1535 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1536 { 1537 int qidx, pool_id, stack_pages, num_sqbs; 1538 struct otx2_qset *qset = &pfvf->qset; 1539 struct otx2_hw *hw = &pfvf->hw; 1540 struct otx2_snd_queue *sq; 1541 struct otx2_pool *pool; 1542 dma_addr_t bufptr; 1543 int err, ptr; 1544 1545 /* Calculate number of SQBs needed. 1546 * 1547 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1548 * Last SQE is used for pointing to next SQB. 1549 */ 1550 num_sqbs = (hw->sqb_size / 128) - 1; 1551 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1552 1553 /* Get no of stack pages needed */ 1554 stack_pages = 1555 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1556 1557 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1558 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1559 /* Initialize aura context */ 1560 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1561 if (err) 1562 goto fail; 1563 1564 /* Initialize pool context */ 1565 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1566 num_sqbs, hw->sqb_size, AURA_NIX_SQ); 1567 if (err) 1568 goto fail; 1569 } 1570 1571 /* Flush accumulated messages */ 1572 err = otx2_sync_mbox_msg(&pfvf->mbox); 1573 if (err) 1574 goto fail; 1575 1576 /* Allocate pointers and free them to aura/pool */ 1577 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1578 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1579 pool = &pfvf->qset.pool[pool_id]; 1580 1581 sq = &qset->sq[qidx]; 1582 sq->sqb_count = 0; 1583 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1584 if (!sq->sqb_ptrs) { 1585 err = -ENOMEM; 1586 goto err_mem; 1587 } 1588 1589 for (ptr = 0; ptr < num_sqbs; ptr++) { 1590 err = otx2_alloc_rbuf(pfvf, pool, &bufptr, pool_id, ptr); 1591 if (err) { 1592 if (pool->xsk_pool) { 1593 ptr--; 1594 while (ptr >= 0) { 1595 xsk_buff_free(pool->xdp[ptr]); 1596 ptr--; 1597 } 1598 } 1599 goto err_mem; 1600 } 1601 1602 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1603 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1604 } 1605 } 1606 1607 err_mem: 1608 return err ? -ENOMEM : 0; 1609 1610 fail: 1611 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1612 otx2_aura_pool_free(pfvf); 1613 return err; 1614 } 1615 1616 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1617 { 1618 struct otx2_hw *hw = &pfvf->hw; 1619 int stack_pages, pool_id, rq; 1620 struct otx2_pool *pool; 1621 int err, ptr, num_ptrs; 1622 dma_addr_t bufptr; 1623 1624 num_ptrs = pfvf->qset.rqe_cnt; 1625 1626 stack_pages = 1627 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1628 1629 for (rq = 0; rq < hw->rx_queues; rq++) { 1630 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1631 /* Initialize aura context */ 1632 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1633 if (err) 1634 goto fail; 1635 } 1636 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1637 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1638 num_ptrs, pfvf->rbsize, AURA_NIX_RQ); 1639 if (err) 1640 goto fail; 1641 } 1642 1643 /* Flush accumulated messages */ 1644 err = otx2_sync_mbox_msg(&pfvf->mbox); 1645 if (err) 1646 goto fail; 1647 1648 /* Allocate pointers and free them to aura/pool */ 1649 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1650 pool = &pfvf->qset.pool[pool_id]; 1651 1652 for (ptr = 0; ptr < num_ptrs; ptr++) { 1653 err = otx2_alloc_rbuf(pfvf, pool, &bufptr, pool_id, ptr); 1654 if (err) { 1655 if (pool->xsk_pool) { 1656 while (ptr) 1657 xsk_buff_free(pool->xdp[--ptr]); 1658 } 1659 return -ENOMEM; 1660 } 1661 1662 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1663 pool->xsk_pool ? bufptr : 1664 bufptr + OTX2_HEAD_ROOM); 1665 } 1666 } 1667 return 0; 1668 fail: 1669 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1670 otx2_aura_pool_free(pfvf); 1671 return err; 1672 } 1673 1674 int otx2_config_npa(struct otx2_nic *pfvf) 1675 { 1676 struct otx2_qset *qset = &pfvf->qset; 1677 struct npa_lf_alloc_req *npalf; 1678 struct otx2_hw *hw = &pfvf->hw; 1679 int aura_cnt; 1680 1681 /* Pool - Stack of free buffer pointers 1682 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1683 */ 1684 1685 if (!hw->pool_cnt) 1686 return -EINVAL; 1687 1688 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1689 sizeof(struct otx2_pool), GFP_KERNEL); 1690 if (!qset->pool) 1691 return -ENOMEM; 1692 1693 /* Get memory to put this msg */ 1694 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1695 if (!npalf) 1696 return -ENOMEM; 1697 1698 /* Set aura and pool counts */ 1699 npalf->nr_pools = hw->pool_cnt; 1700 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1701 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1702 1703 return otx2_sync_mbox_msg(&pfvf->mbox); 1704 } 1705 1706 int otx2_detach_resources(struct mbox *mbox) 1707 { 1708 struct rsrc_detach *detach; 1709 1710 mutex_lock(&mbox->lock); 1711 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1712 if (!detach) { 1713 mutex_unlock(&mbox->lock); 1714 return -ENOMEM; 1715 } 1716 1717 /* detach all */ 1718 detach->partial = false; 1719 1720 /* Send detach request to AF */ 1721 otx2_sync_mbox_msg(mbox); 1722 mutex_unlock(&mbox->lock); 1723 return 0; 1724 } 1725 EXPORT_SYMBOL(otx2_detach_resources); 1726 1727 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1728 { 1729 struct rsrc_attach *attach; 1730 struct msg_req *msix; 1731 int err; 1732 1733 mutex_lock(&pfvf->mbox.lock); 1734 /* Get memory to put this msg */ 1735 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1736 if (!attach) { 1737 mutex_unlock(&pfvf->mbox.lock); 1738 return -ENOMEM; 1739 } 1740 1741 attach->npalf = true; 1742 attach->nixlf = true; 1743 1744 /* Send attach request to AF */ 1745 err = otx2_sync_mbox_msg(&pfvf->mbox); 1746 if (err) { 1747 mutex_unlock(&pfvf->mbox.lock); 1748 return err; 1749 } 1750 1751 pfvf->nix_blkaddr = BLKADDR_NIX0; 1752 1753 /* If the platform has two NIX blocks then LF may be 1754 * allocated from NIX1. 1755 */ 1756 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1757 pfvf->nix_blkaddr = BLKADDR_NIX1; 1758 1759 /* Get NPA and NIX MSIX vector offsets */ 1760 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1761 if (!msix) { 1762 mutex_unlock(&pfvf->mbox.lock); 1763 return -ENOMEM; 1764 } 1765 1766 err = otx2_sync_mbox_msg(&pfvf->mbox); 1767 if (err) { 1768 mutex_unlock(&pfvf->mbox.lock); 1769 return err; 1770 } 1771 mutex_unlock(&pfvf->mbox.lock); 1772 1773 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1774 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1775 dev_err(pfvf->dev, 1776 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1777 return -EINVAL; 1778 } 1779 1780 return 0; 1781 } 1782 EXPORT_SYMBOL(otx2_attach_npa_nix); 1783 1784 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1785 { 1786 struct hwctx_disable_req *req; 1787 1788 mutex_lock(&mbox->lock); 1789 /* Request AQ to disable this context */ 1790 if (npa) 1791 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1792 else 1793 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1794 1795 if (!req) { 1796 mutex_unlock(&mbox->lock); 1797 return; 1798 } 1799 1800 req->ctype = type; 1801 1802 if (otx2_sync_mbox_msg(mbox)) 1803 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1804 __func__); 1805 1806 mutex_unlock(&mbox->lock); 1807 } 1808 1809 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1810 { 1811 struct nix_bp_cfg_req *req; 1812 1813 if (enable) 1814 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1815 else 1816 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1817 1818 if (!req) 1819 return -ENOMEM; 1820 1821 req->chan_base = 0; 1822 if (otx2_is_pfc_enabled(pfvf)) { 1823 req->chan_cnt = IEEE_8021QAZ_MAX_TCS; 1824 req->bpid_per_chan = 1; 1825 } else { 1826 req->chan_cnt = pfvf->hw.rx_chan_cnt; 1827 req->bpid_per_chan = 0; 1828 } 1829 1830 return otx2_sync_mbox_msg(&pfvf->mbox); 1831 } 1832 EXPORT_SYMBOL(otx2_nix_config_bp); 1833 1834 int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable) 1835 { 1836 struct nix_bp_cfg_req *req; 1837 1838 if (enable) 1839 req = otx2_mbox_alloc_msg_nix_cpt_bp_enable(&pfvf->mbox); 1840 else 1841 req = otx2_mbox_alloc_msg_nix_cpt_bp_disable(&pfvf->mbox); 1842 1843 if (!req) 1844 return -ENOMEM; 1845 1846 req->chan_base = 0; 1847 if (otx2_is_pfc_enabled(pfvf)) { 1848 req->chan_cnt = IEEE_8021QAZ_MAX_TCS; 1849 req->bpid_per_chan = 1; 1850 } else { 1851 req->chan_cnt = pfvf->hw.rx_chan_cnt; 1852 req->bpid_per_chan = 0; 1853 } 1854 1855 return otx2_sync_mbox_msg(&pfvf->mbox); 1856 } 1857 EXPORT_SYMBOL(otx2_nix_cpt_config_bp); 1858 1859 /* Mbox message handlers */ 1860 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1861 struct cgx_stats_rsp *rsp) 1862 { 1863 int id; 1864 1865 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1866 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1867 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1868 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1869 } 1870 1871 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1872 struct cgx_fec_stats_rsp *rsp) 1873 { 1874 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1875 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1876 } 1877 1878 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1879 struct npa_lf_alloc_rsp *rsp) 1880 { 1881 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1882 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1883 } 1884 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1885 1886 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1887 struct nix_lf_alloc_rsp *rsp) 1888 { 1889 pfvf->hw.sqb_size = rsp->sqb_size; 1890 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1891 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1892 pfvf->hw.rx_chan_cnt = rsp->rx_chan_cnt; 1893 pfvf->hw.tx_chan_cnt = rsp->tx_chan_cnt; 1894 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1895 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1896 pfvf->hw.cgx_links = rsp->cgx_links; 1897 pfvf->hw.lbk_links = rsp->lbk_links; 1898 pfvf->hw.tx_link = rsp->tx_link; 1899 } 1900 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1901 1902 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1903 struct msix_offset_rsp *rsp) 1904 { 1905 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1906 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1907 } 1908 EXPORT_SYMBOL(mbox_handler_msix_offset); 1909 1910 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1911 struct nix_bp_cfg_rsp *rsp) 1912 { 1913 int chan, chan_id; 1914 1915 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1916 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1917 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1918 } 1919 } 1920 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1921 1922 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1923 { 1924 struct otx2_qset *qset = &pfvf->qset; 1925 struct otx2_hw *hw = &pfvf->hw; 1926 int irq, qidx; 1927 1928 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1929 qidx < n; 1930 qidx++, irq++) { 1931 int vector = pci_irq_vector(pfvf->pdev, irq); 1932 1933 irq_set_affinity_hint(vector, NULL); 1934 free_cpumask_var(hw->affinity_mask[irq]); 1935 free_irq(vector, &qset->napi[qidx]); 1936 } 1937 } 1938 EXPORT_SYMBOL(otx2_free_cints); 1939 1940 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1941 { 1942 struct otx2_hw *hw = &pfvf->hw; 1943 int vec, cpu, irq, cint; 1944 1945 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1946 cpu = cpumask_first(cpu_online_mask); 1947 1948 /* CQ interrupts */ 1949 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1950 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1951 return; 1952 1953 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1954 1955 irq = pci_irq_vector(pfvf->pdev, vec); 1956 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1957 1958 cpu = cpumask_next(cpu, cpu_online_mask); 1959 if (unlikely(cpu >= nr_cpu_ids)) 1960 cpu = 0; 1961 } 1962 } 1963 1964 static u32 get_dwrr_mtu(struct otx2_nic *pfvf, struct nix_hw_info *hw) 1965 { 1966 if (is_otx2_lbkvf(pfvf->pdev)) { 1967 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_LBK; 1968 return hw->lbk_dwrr_mtu; 1969 } 1970 1971 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_RPM; 1972 return hw->rpm_dwrr_mtu; 1973 } 1974 1975 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1976 { 1977 struct nix_hw_info *rsp; 1978 struct msg_req *req; 1979 u16 max_mtu; 1980 int rc; 1981 1982 mutex_lock(&pfvf->mbox.lock); 1983 1984 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1985 if (!req) { 1986 rc = -ENOMEM; 1987 goto out; 1988 } 1989 1990 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1991 if (!rc) { 1992 rsp = (struct nix_hw_info *) 1993 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1994 if (IS_ERR(rsp)) { 1995 rc = PTR_ERR(rsp); 1996 goto out; 1997 } 1998 1999 /* HW counts VLAN insertion bytes (8 for double tag) 2000 * irrespective of whether SQE is requesting to insert VLAN 2001 * in the packet or not. Hence these 8 bytes have to be 2002 * discounted from max packet size otherwise HW will throw 2003 * SMQ errors 2004 */ 2005 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 2006 2007 /* Also save DWRR MTU, needed for DWRR weight calculation */ 2008 pfvf->hw.dwrr_mtu = get_dwrr_mtu(pfvf, rsp); 2009 if (!pfvf->hw.dwrr_mtu) 2010 pfvf->hw.dwrr_mtu = 1; 2011 } 2012 2013 out: 2014 mutex_unlock(&pfvf->mbox.lock); 2015 if (rc) { 2016 dev_warn(pfvf->dev, 2017 "Failed to get MTU from hardware setting default value(1500)\n"); 2018 max_mtu = 1500; 2019 } 2020 return max_mtu; 2021 } 2022 EXPORT_SYMBOL(otx2_get_max_mtu); 2023 2024 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features) 2025 { 2026 netdev_features_t changed = features ^ netdev->features; 2027 struct otx2_nic *pfvf = netdev_priv(netdev); 2028 bool ntuple = !!(features & NETIF_F_NTUPLE); 2029 bool tc = !!(features & NETIF_F_HW_TC); 2030 2031 if ((changed & NETIF_F_NTUPLE) && !ntuple) 2032 otx2_destroy_ntuple_flows(pfvf); 2033 2034 if ((changed & NETIF_F_NTUPLE) && ntuple) { 2035 if (!pfvf->flow_cfg->max_flows) { 2036 netdev_err(netdev, 2037 "Can't enable NTUPLE, MCAM entries not allocated\n"); 2038 return -EINVAL; 2039 } 2040 } 2041 2042 if ((changed & NETIF_F_HW_TC) && !tc && 2043 otx2_tc_flower_rule_cnt(pfvf)) { 2044 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 2045 return -EBUSY; 2046 } 2047 2048 if ((changed & NETIF_F_NTUPLE) && ntuple && 2049 otx2_tc_flower_rule_cnt(pfvf) && !(changed & NETIF_F_HW_TC)) { 2050 netdev_err(netdev, 2051 "Can't enable NTUPLE when TC flower offload is active, disable TC rules and retry\n"); 2052 return -EINVAL; 2053 } 2054 2055 return 0; 2056 } 2057 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features); 2058 2059 int otx2_set_hw_capabilities(struct otx2_nic *pfvf) 2060 { 2061 struct mbox *mbox = &pfvf->mbox; 2062 struct otx2_hw *hw = &pfvf->hw; 2063 struct get_hw_cap_rsp *rsp; 2064 struct msg_req *req; 2065 int ret = -ENOMEM; 2066 2067 mutex_lock(&mbox->lock); 2068 2069 req = otx2_mbox_alloc_msg_get_hw_cap(mbox); 2070 if (!req) 2071 goto fail; 2072 2073 ret = otx2_sync_mbox_msg(mbox); 2074 if (ret) 2075 goto fail; 2076 2077 rsp = (struct get_hw_cap_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 2078 0, &req->hdr); 2079 if (IS_ERR(rsp)) { 2080 ret = -EINVAL; 2081 goto fail; 2082 } 2083 2084 if (rsp->hw_caps & HW_CAP_MACSEC) 2085 __set_bit(CN10K_HW_MACSEC, &hw->cap_flag); 2086 2087 mutex_unlock(&mbox->lock); 2088 2089 return 0; 2090 fail: 2091 dev_err(pfvf->dev, "Cannot get MACSEC capability from AF\n"); 2092 mutex_unlock(&mbox->lock); 2093 return ret; 2094 } 2095 2096 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 2097 int __weak \ 2098 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 2099 struct _req_type *req, \ 2100 struct _rsp_type *rsp) \ 2101 { \ 2102 /* Nothing to do here */ \ 2103 return 0; \ 2104 } \ 2105 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 2106 MBOX_UP_CGX_MESSAGES 2107 MBOX_UP_MCS_MESSAGES 2108 #undef M 2109 2110 dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 2111 struct sk_buff *skb, int seg, int *len) 2112 { 2113 enum dma_data_direction dir = DMA_TO_DEVICE; 2114 const skb_frag_t *frag; 2115 struct page *page; 2116 int offset; 2117 2118 /* Crypto hardware need write permission for ipsec crypto offload */ 2119 if (unlikely(xfrm_offload(skb))) { 2120 dir = DMA_BIDIRECTIONAL; 2121 skb = skb_unshare(skb, GFP_ATOMIC); 2122 } 2123 2124 /* First segment is always skb->data */ 2125 if (!seg) { 2126 page = virt_to_page(skb->data); 2127 offset = offset_in_page(skb->data); 2128 *len = skb_headlen(skb); 2129 } else { 2130 frag = &skb_shinfo(skb)->frags[seg - 1]; 2131 page = skb_frag_page(frag); 2132 offset = skb_frag_off(frag); 2133 *len = skb_frag_size(frag); 2134 } 2135 return otx2_dma_map_page(pfvf, page, offset, *len, dir); 2136 } 2137 2138 void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg) 2139 { 2140 enum dma_data_direction dir = DMA_TO_DEVICE; 2141 struct sk_buff *skb = NULL; 2142 int seg; 2143 2144 skb = (struct sk_buff *)sg->skb; 2145 if (unlikely(xfrm_offload(skb))) 2146 dir = DMA_BIDIRECTIONAL; 2147 2148 for (seg = 0; seg < sg->num_segs; seg++) { 2149 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg], 2150 sg->size[seg], dir); 2151 } 2152 sg->num_segs = 0; 2153 } 2154