1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 #include <net/page_pool/helpers.h> 11 #include <net/tso.h> 12 #include <linux/bitfield.h> 13 14 #include "otx2_reg.h" 15 #include "otx2_common.h" 16 #include "otx2_struct.h" 17 #include "cn10k.h" 18 19 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 20 struct otx2_nic *pfvf, int qidx) 21 { 22 u64 incr = (u64)qidx << 32; 23 u64 *ptr; 24 25 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 26 stats->bytes = otx2_atomic64_add(incr, ptr); 27 28 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 29 stats->pkts = otx2_atomic64_add(incr, ptr); 30 } 31 32 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 33 struct otx2_nic *pfvf, int qidx) 34 { 35 u64 incr = (u64)qidx << 32; 36 u64 *ptr; 37 38 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 39 stats->bytes = otx2_atomic64_add(incr, ptr); 40 41 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 42 stats->pkts = otx2_atomic64_add(incr, ptr); 43 } 44 45 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 46 { 47 struct msg_req *req; 48 49 if (!netif_running(pfvf->netdev)) 50 return; 51 52 mutex_lock(&pfvf->mbox.lock); 53 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 54 if (!req) { 55 mutex_unlock(&pfvf->mbox.lock); 56 return; 57 } 58 59 otx2_sync_mbox_msg(&pfvf->mbox); 60 mutex_unlock(&pfvf->mbox.lock); 61 } 62 63 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 64 { 65 struct msg_req *req; 66 67 if (!netif_running(pfvf->netdev)) 68 return; 69 mutex_lock(&pfvf->mbox.lock); 70 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 71 if (req) 72 otx2_sync_mbox_msg(&pfvf->mbox); 73 mutex_unlock(&pfvf->mbox.lock); 74 } 75 76 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 77 { 78 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 79 80 if (!pfvf->qset.rq) 81 return 0; 82 83 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 84 return 1; 85 } 86 EXPORT_SYMBOL(otx2_update_rq_stats); 87 88 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 89 { 90 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 91 92 if (!pfvf->qset.sq) 93 return 0; 94 95 if (qidx >= pfvf->hw.non_qos_queues) { 96 if (!test_bit(qidx - pfvf->hw.non_qos_queues, pfvf->qos.qos_sq_bmap)) 97 return 0; 98 } 99 100 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 101 return 1; 102 } 103 EXPORT_SYMBOL(otx2_update_sq_stats); 104 105 void otx2_get_dev_stats(struct otx2_nic *pfvf) 106 { 107 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 108 109 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 110 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 111 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 112 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 113 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 114 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 115 dev_stats->rx_mcast_frames + 116 dev_stats->rx_ucast_frames; 117 118 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 119 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 120 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 121 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 122 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 123 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 124 dev_stats->tx_mcast_frames + 125 dev_stats->tx_ucast_frames; 126 } 127 128 void otx2_get_stats64(struct net_device *netdev, 129 struct rtnl_link_stats64 *stats) 130 { 131 struct otx2_nic *pfvf = netdev_priv(netdev); 132 struct otx2_dev_stats *dev_stats; 133 134 otx2_get_dev_stats(pfvf); 135 136 dev_stats = &pfvf->hw.dev_stats; 137 stats->rx_bytes = dev_stats->rx_bytes; 138 stats->rx_packets = dev_stats->rx_frames; 139 stats->rx_dropped = dev_stats->rx_drops; 140 stats->multicast = dev_stats->rx_mcast_frames; 141 142 stats->tx_bytes = dev_stats->tx_bytes; 143 stats->tx_packets = dev_stats->tx_frames; 144 stats->tx_dropped = dev_stats->tx_drops; 145 } 146 EXPORT_SYMBOL(otx2_get_stats64); 147 148 /* Sync MAC address with RVU AF */ 149 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 150 { 151 struct nix_set_mac_addr *req; 152 int err; 153 154 mutex_lock(&pfvf->mbox.lock); 155 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 156 if (!req) { 157 mutex_unlock(&pfvf->mbox.lock); 158 return -ENOMEM; 159 } 160 161 ether_addr_copy(req->mac_addr, mac); 162 163 err = otx2_sync_mbox_msg(&pfvf->mbox); 164 mutex_unlock(&pfvf->mbox.lock); 165 return err; 166 } 167 168 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 169 struct net_device *netdev) 170 { 171 struct nix_get_mac_addr_rsp *rsp; 172 struct mbox_msghdr *msghdr; 173 struct msg_req *req; 174 int err; 175 176 mutex_lock(&pfvf->mbox.lock); 177 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 178 if (!req) { 179 mutex_unlock(&pfvf->mbox.lock); 180 return -ENOMEM; 181 } 182 183 err = otx2_sync_mbox_msg(&pfvf->mbox); 184 if (err) { 185 mutex_unlock(&pfvf->mbox.lock); 186 return err; 187 } 188 189 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 190 if (IS_ERR(msghdr)) { 191 mutex_unlock(&pfvf->mbox.lock); 192 return PTR_ERR(msghdr); 193 } 194 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 195 eth_hw_addr_set(netdev, rsp->mac_addr); 196 mutex_unlock(&pfvf->mbox.lock); 197 198 return 0; 199 } 200 201 int otx2_set_mac_address(struct net_device *netdev, void *p) 202 { 203 struct otx2_nic *pfvf = netdev_priv(netdev); 204 struct sockaddr *addr = p; 205 206 if (!is_valid_ether_addr(addr->sa_data)) 207 return -EADDRNOTAVAIL; 208 209 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 210 eth_hw_addr_set(netdev, addr->sa_data); 211 /* update dmac field in vlan offload rule */ 212 if (netif_running(netdev) && 213 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 214 otx2_install_rxvlan_offload_flow(pfvf); 215 /* update dmac address in ntuple and DMAC filter list */ 216 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 217 otx2_dmacflt_update_pfmac_flow(pfvf); 218 } else { 219 return -EPERM; 220 } 221 222 return 0; 223 } 224 EXPORT_SYMBOL(otx2_set_mac_address); 225 226 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 227 { 228 struct nix_frs_cfg *req; 229 u16 maxlen; 230 int err; 231 232 maxlen = pfvf->hw.max_mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 233 234 mutex_lock(&pfvf->mbox.lock); 235 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 236 if (!req) { 237 mutex_unlock(&pfvf->mbox.lock); 238 return -ENOMEM; 239 } 240 241 req->maxlen = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 242 243 /* Use max receive length supported by hardware for loopback devices */ 244 if (is_otx2_lbkvf(pfvf->pdev)) 245 req->maxlen = maxlen; 246 247 err = otx2_sync_mbox_msg(&pfvf->mbox); 248 mutex_unlock(&pfvf->mbox.lock); 249 return err; 250 } 251 EXPORT_SYMBOL(otx2_hw_set_mtu); 252 253 int otx2_config_pause_frm(struct otx2_nic *pfvf) 254 { 255 struct cgx_pause_frm_cfg *req; 256 int err; 257 258 if (is_otx2_lbkvf(pfvf->pdev) || is_otx2_sdp_rep(pfvf->pdev)) 259 return 0; 260 261 mutex_lock(&pfvf->mbox.lock); 262 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 263 if (!req) { 264 err = -ENOMEM; 265 goto unlock; 266 } 267 268 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 269 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 270 req->set = 1; 271 272 err = otx2_sync_mbox_msg(&pfvf->mbox); 273 unlock: 274 mutex_unlock(&pfvf->mbox.lock); 275 return err; 276 } 277 EXPORT_SYMBOL(otx2_config_pause_frm); 278 279 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 280 { 281 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 282 struct nix_rss_flowkey_cfg_rsp *rsp; 283 struct nix_rss_flowkey_cfg *req; 284 int err; 285 286 mutex_lock(&pfvf->mbox.lock); 287 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 288 if (!req) { 289 mutex_unlock(&pfvf->mbox.lock); 290 return -ENOMEM; 291 } 292 req->mcam_index = -1; /* Default or reserved index */ 293 req->flowkey_cfg = rss->flowkey_cfg; 294 req->group = DEFAULT_RSS_CONTEXT_GROUP; 295 296 err = otx2_sync_mbox_msg(&pfvf->mbox); 297 if (err) 298 goto fail; 299 300 rsp = (struct nix_rss_flowkey_cfg_rsp *) 301 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 302 if (IS_ERR(rsp)) { 303 err = PTR_ERR(rsp); 304 goto fail; 305 } 306 307 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 308 fail: 309 mutex_unlock(&pfvf->mbox.lock); 310 return err; 311 } 312 313 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 314 { 315 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 316 const int index = rss->rss_size * ctx_id; 317 struct mbox *mbox = &pfvf->mbox; 318 struct otx2_rss_ctx *rss_ctx; 319 struct nix_aq_enq_req *aq; 320 int idx, err; 321 322 mutex_lock(&mbox->lock); 323 rss_ctx = rss->rss_ctx[ctx_id]; 324 /* Get memory to put this msg */ 325 for (idx = 0; idx < rss->rss_size; idx++) { 326 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 327 if (!aq) { 328 /* The shared memory buffer can be full. 329 * Flush it and retry 330 */ 331 err = otx2_sync_mbox_msg(mbox); 332 if (err) { 333 mutex_unlock(&mbox->lock); 334 return err; 335 } 336 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 337 if (!aq) { 338 mutex_unlock(&mbox->lock); 339 return -ENOMEM; 340 } 341 } 342 343 aq->rss.rq = rss_ctx->ind_tbl[idx]; 344 345 /* Fill AQ info */ 346 aq->qidx = index + idx; 347 aq->ctype = NIX_AQ_CTYPE_RSS; 348 aq->op = NIX_AQ_INSTOP_INIT; 349 } 350 err = otx2_sync_mbox_msg(mbox); 351 mutex_unlock(&mbox->lock); 352 return err; 353 } 354 355 void otx2_set_rss_key(struct otx2_nic *pfvf) 356 { 357 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 358 u64 *key = (u64 *)&rss->key[4]; 359 int idx; 360 361 /* 352bit or 44byte key needs to be configured as below 362 * NIX_LF_RX_SECRETX0 = key<351:288> 363 * NIX_LF_RX_SECRETX1 = key<287:224> 364 * NIX_LF_RX_SECRETX2 = key<223:160> 365 * NIX_LF_RX_SECRETX3 = key<159:96> 366 * NIX_LF_RX_SECRETX4 = key<95:32> 367 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 368 */ 369 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 370 (u64)(*((u32 *)&rss->key)) << 32); 371 idx = sizeof(rss->key) / sizeof(u64); 372 while (idx > 0) { 373 idx--; 374 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 375 } 376 } 377 378 int otx2_rss_init(struct otx2_nic *pfvf) 379 { 380 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 381 struct otx2_rss_ctx *rss_ctx; 382 int idx, ret = 0; 383 384 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 385 386 /* Init RSS key if it is not setup already */ 387 if (!rss->enable) 388 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 389 otx2_set_rss_key(pfvf); 390 391 if (!netif_is_rxfh_configured(pfvf->netdev)) { 392 /* Set RSS group 0 as default indirection table */ 393 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 394 GFP_KERNEL); 395 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 396 return -ENOMEM; 397 398 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 399 for (idx = 0; idx < rss->rss_size; idx++) 400 rss_ctx->ind_tbl[idx] = 401 ethtool_rxfh_indir_default(idx, 402 pfvf->hw.rx_queues); 403 } 404 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 405 if (ret) 406 return ret; 407 408 /* Flowkey or hash config to be used for generating flow tag */ 409 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 410 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 411 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 412 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 413 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 414 415 ret = otx2_set_flowkey_cfg(pfvf); 416 if (ret) 417 return ret; 418 419 rss->enable = true; 420 return 0; 421 } 422 423 /* Setup UDP segmentation algorithm in HW */ 424 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 425 { 426 struct nix_lso_format *field; 427 428 field = (struct nix_lso_format *)&lso->fields[0]; 429 lso->field_mask = GENMASK(18, 0); 430 431 /* IP's Length field */ 432 field->layer = NIX_TXLAYER_OL3; 433 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 434 field->offset = v4 ? 2 : 4; 435 field->sizem1 = 1; /* i.e 2 bytes */ 436 field->alg = NIX_LSOALG_ADD_PAYLEN; 437 field++; 438 439 /* No ID field in IPv6 header */ 440 if (v4) { 441 /* Increment IPID */ 442 field->layer = NIX_TXLAYER_OL3; 443 field->offset = 4; 444 field->sizem1 = 1; /* i.e 2 bytes */ 445 field->alg = NIX_LSOALG_ADD_SEGNUM; 446 field++; 447 } 448 449 /* Update length in UDP header */ 450 field->layer = NIX_TXLAYER_OL4; 451 field->offset = 4; 452 field->sizem1 = 1; 453 field->alg = NIX_LSOALG_ADD_PAYLEN; 454 } 455 456 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 457 void otx2_setup_segmentation(struct otx2_nic *pfvf) 458 { 459 struct nix_lso_format_cfg_rsp *rsp; 460 struct nix_lso_format_cfg *lso; 461 struct otx2_hw *hw = &pfvf->hw; 462 int err; 463 464 mutex_lock(&pfvf->mbox.lock); 465 466 /* UDPv4 segmentation */ 467 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 468 if (!lso) 469 goto fail; 470 471 /* Setup UDP/IP header fields that HW should update per segment */ 472 otx2_setup_udp_segmentation(lso, true); 473 474 err = otx2_sync_mbox_msg(&pfvf->mbox); 475 if (err) 476 goto fail; 477 478 rsp = (struct nix_lso_format_cfg_rsp *) 479 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 480 if (IS_ERR(rsp)) 481 goto fail; 482 483 hw->lso_udpv4_idx = rsp->lso_format_idx; 484 485 /* UDPv6 segmentation */ 486 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 487 if (!lso) 488 goto fail; 489 490 /* Setup UDP/IP header fields that HW should update per segment */ 491 otx2_setup_udp_segmentation(lso, false); 492 493 err = otx2_sync_mbox_msg(&pfvf->mbox); 494 if (err) 495 goto fail; 496 497 rsp = (struct nix_lso_format_cfg_rsp *) 498 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 499 if (IS_ERR(rsp)) 500 goto fail; 501 502 hw->lso_udpv6_idx = rsp->lso_format_idx; 503 mutex_unlock(&pfvf->mbox.lock); 504 return; 505 fail: 506 mutex_unlock(&pfvf->mbox.lock); 507 netdev_info(pfvf->netdev, 508 "Failed to get LSO index for UDP GSO offload, disabling\n"); 509 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 510 } 511 512 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 513 { 514 /* Configure CQE interrupt coalescing parameters 515 * 516 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 517 * set 1 less than cq_ecount_wait. And cq_time_wait is in 518 * usecs, convert that to 100ns count. 519 */ 520 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 521 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 522 ((u64)pfvf->hw.cq_qcount_wait << 32) | 523 (pfvf->hw.cq_ecount_wait - 1)); 524 } 525 526 static int otx2_alloc_pool_buf(struct otx2_nic *pfvf, struct otx2_pool *pool, 527 dma_addr_t *dma) 528 { 529 unsigned int offset = 0; 530 struct page *page; 531 size_t sz; 532 533 sz = SKB_DATA_ALIGN(pool->rbsize); 534 sz = ALIGN(sz, OTX2_ALIGN); 535 536 page = page_pool_alloc_frag(pool->page_pool, &offset, sz, GFP_ATOMIC); 537 if (unlikely(!page)) 538 return -ENOMEM; 539 540 *dma = page_pool_get_dma_addr(page) + offset; 541 return 0; 542 } 543 544 static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 545 dma_addr_t *dma) 546 { 547 u8 *buf; 548 549 if (pool->page_pool) 550 return otx2_alloc_pool_buf(pfvf, pool, dma); 551 552 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 553 if (unlikely(!buf)) 554 return -ENOMEM; 555 556 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 557 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 558 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 559 page_frag_free(buf); 560 return -ENOMEM; 561 } 562 563 return 0; 564 } 565 566 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 567 dma_addr_t *dma) 568 { 569 int ret; 570 571 local_bh_disable(); 572 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 573 local_bh_enable(); 574 return ret; 575 } 576 577 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 578 dma_addr_t *dma) 579 { 580 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) 581 return -ENOMEM; 582 return 0; 583 } 584 585 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 586 { 587 struct otx2_nic *pfvf = netdev_priv(netdev); 588 589 schedule_work(&pfvf->reset_task); 590 } 591 EXPORT_SYMBOL(otx2_tx_timeout); 592 593 void otx2_get_mac_from_af(struct net_device *netdev) 594 { 595 struct otx2_nic *pfvf = netdev_priv(netdev); 596 int err; 597 598 err = otx2_hw_get_mac_addr(pfvf, netdev); 599 if (err) 600 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 601 602 /* If AF doesn't provide a valid MAC, generate a random one */ 603 if (!is_valid_ether_addr(netdev->dev_addr)) 604 eth_hw_addr_random(netdev); 605 } 606 EXPORT_SYMBOL(otx2_get_mac_from_af); 607 608 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc) 609 { 610 u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC]; 611 struct otx2_hw *hw = &pfvf->hw; 612 struct nix_txschq_config *req; 613 u64 schq, parent; 614 u64 dwrr_val; 615 616 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 617 618 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 619 if (!req) 620 return -ENOMEM; 621 622 req->lvl = lvl; 623 req->num_regs = 1; 624 625 schq_list = hw->txschq_list; 626 #ifdef CONFIG_DCB 627 if (txschq_for_pfc) 628 schq_list = pfvf->pfc_schq_list; 629 #endif 630 631 schq = schq_list[lvl][prio]; 632 /* Set topology e.t.c configuration */ 633 if (lvl == NIX_TXSCH_LVL_SMQ) { 634 req->reg[0] = NIX_AF_SMQX_CFG(schq); 635 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU; 636 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 637 (0x2ULL << 36); 638 /* Set link type for DWRR MTU selection on CN10K silicons */ 639 if (!is_dev_otx2(pfvf->pdev)) 640 req->regval[0] |= FIELD_PREP(GENMASK_ULL(58, 57), 641 (u64)hw->smq_link_type); 642 req->num_regs++; 643 /* MDQ config */ 644 parent = schq_list[NIX_TXSCH_LVL_TL4][prio]; 645 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 646 req->regval[1] = parent << 16; 647 req->num_regs++; 648 /* Set DWRR quantum */ 649 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 650 req->regval[2] = dwrr_val; 651 } else if (lvl == NIX_TXSCH_LVL_TL4) { 652 int sdp_chan = hw->tx_chan_base + prio; 653 654 if (is_otx2_sdp_rep(pfvf->pdev)) 655 prio = 0; 656 parent = schq_list[NIX_TXSCH_LVL_TL3][prio]; 657 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 658 req->regval[0] = (u64)parent << 16; 659 req->num_regs++; 660 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 661 req->regval[1] = dwrr_val; 662 if (is_otx2_sdp_rep(pfvf->pdev)) { 663 req->num_regs++; 664 req->reg[2] = NIX_AF_TL4X_SDP_LINK_CFG(schq); 665 req->regval[2] = BIT_ULL(12) | BIT_ULL(13) | 666 (sdp_chan & 0xff); 667 } 668 } else if (lvl == NIX_TXSCH_LVL_TL3) { 669 parent = schq_list[NIX_TXSCH_LVL_TL2][prio]; 670 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 671 req->regval[0] = (u64)parent << 16; 672 req->num_regs++; 673 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 674 req->regval[1] = dwrr_val; 675 if (lvl == hw->txschq_link_cfg_lvl && 676 !is_otx2_sdp_rep(pfvf->pdev)) { 677 req->num_regs++; 678 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 679 /* Enable this queue and backpressure 680 * and set relative channel 681 */ 682 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 683 } 684 } else if (lvl == NIX_TXSCH_LVL_TL2) { 685 parent = schq_list[NIX_TXSCH_LVL_TL1][prio]; 686 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 687 req->regval[0] = (u64)parent << 16; 688 689 req->num_regs++; 690 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 691 req->regval[1] = (u64)hw->txschq_aggr_lvl_rr_prio << 24 | dwrr_val; 692 693 if (lvl == hw->txschq_link_cfg_lvl && 694 !is_otx2_sdp_rep(pfvf->pdev)) { 695 req->num_regs++; 696 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 697 /* Enable this queue and backpressure 698 * and set relative channel 699 */ 700 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 701 } 702 } else if (lvl == NIX_TXSCH_LVL_TL1) { 703 /* Default config for TL1. 704 * For VF this is always ignored. 705 */ 706 707 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 708 * clip it to 16384, so configuring a 24bit max value 709 * will work on both OTx2 and CN10K. 710 */ 711 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 712 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 713 714 req->num_regs++; 715 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 716 req->regval[1] = hw->txschq_aggr_lvl_rr_prio << 1; 717 718 req->num_regs++; 719 req->reg[2] = NIX_AF_TL1X_CIR(schq); 720 req->regval[2] = 0; 721 } 722 723 return otx2_sync_mbox_msg(&pfvf->mbox); 724 } 725 EXPORT_SYMBOL(otx2_txschq_config); 726 727 int otx2_smq_flush(struct otx2_nic *pfvf, int smq) 728 { 729 struct nix_txschq_config *req; 730 int rc; 731 732 mutex_lock(&pfvf->mbox.lock); 733 734 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 735 if (!req) { 736 mutex_unlock(&pfvf->mbox.lock); 737 return -ENOMEM; 738 } 739 740 req->lvl = NIX_TXSCH_LVL_SMQ; 741 req->reg[0] = NIX_AF_SMQX_CFG(smq); 742 req->regval[0] |= BIT_ULL(49); 743 req->num_regs++; 744 745 rc = otx2_sync_mbox_msg(&pfvf->mbox); 746 mutex_unlock(&pfvf->mbox.lock); 747 return rc; 748 } 749 EXPORT_SYMBOL(otx2_smq_flush); 750 751 int otx2_txsch_alloc(struct otx2_nic *pfvf) 752 { 753 int chan_cnt = pfvf->hw.tx_chan_cnt; 754 struct nix_txsch_alloc_req *req; 755 struct nix_txsch_alloc_rsp *rsp; 756 int lvl, schq, rc; 757 758 /* Get memory to put this msg */ 759 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 760 if (!req) 761 return -ENOMEM; 762 763 /* Request one schq per level */ 764 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 765 req->schq[lvl] = 1; 766 767 if (is_otx2_sdp_rep(pfvf->pdev) && chan_cnt > 1) { 768 req->schq[NIX_TXSCH_LVL_SMQ] = chan_cnt; 769 req->schq[NIX_TXSCH_LVL_TL4] = chan_cnt; 770 } 771 772 rc = otx2_sync_mbox_msg(&pfvf->mbox); 773 if (rc) 774 return rc; 775 776 rsp = (struct nix_txsch_alloc_rsp *) 777 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 778 if (IS_ERR(rsp)) 779 return PTR_ERR(rsp); 780 781 /* Setup transmit scheduler list */ 782 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 783 pfvf->hw.txschq_cnt[lvl] = rsp->schq[lvl]; 784 for (schq = 0; schq < rsp->schq[lvl]; schq++) 785 pfvf->hw.txschq_list[lvl][schq] = 786 rsp->schq_list[lvl][schq]; 787 } 788 789 pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl; 790 pfvf->hw.txschq_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio; 791 792 return 0; 793 } 794 795 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq) 796 { 797 struct nix_txsch_free_req *free_req; 798 int err; 799 800 mutex_lock(&pfvf->mbox.lock); 801 802 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 803 if (!free_req) { 804 mutex_unlock(&pfvf->mbox.lock); 805 netdev_err(pfvf->netdev, 806 "Failed alloc txschq free req\n"); 807 return; 808 } 809 810 free_req->schq_lvl = lvl; 811 free_req->schq = schq; 812 813 err = otx2_sync_mbox_msg(&pfvf->mbox); 814 if (err) { 815 netdev_err(pfvf->netdev, 816 "Failed stop txschq %d at level %d\n", schq, lvl); 817 } 818 819 mutex_unlock(&pfvf->mbox.lock); 820 } 821 EXPORT_SYMBOL(otx2_txschq_free_one); 822 823 void otx2_txschq_stop(struct otx2_nic *pfvf) 824 { 825 int lvl, schq, idx; 826 827 /* free non QOS TLx nodes */ 828 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 829 for (idx = 0; idx < pfvf->hw.txschq_cnt[lvl]; idx++) { 830 otx2_txschq_free_one(pfvf, lvl, 831 pfvf->hw.txschq_list[lvl][idx]); 832 } 833 } 834 835 /* Clear the txschq list */ 836 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 837 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 838 pfvf->hw.txschq_list[lvl][schq] = 0; 839 } 840 841 } 842 843 void otx2_sqb_flush(struct otx2_nic *pfvf) 844 { 845 int qidx, sqe_tail, sqe_head; 846 struct otx2_snd_queue *sq; 847 u64 incr, *ptr, val; 848 849 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 850 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 851 sq = &pfvf->qset.sq[qidx]; 852 if (!sq->sqb_ptrs) 853 continue; 854 855 incr = (u64)qidx << 32; 856 val = otx2_atomic64_add(incr, ptr); 857 sqe_head = (val >> 20) & 0x3F; 858 sqe_tail = (val >> 28) & 0x3F; 859 if (sqe_head != sqe_tail) 860 usleep_range(50, 60); 861 } 862 } 863 864 /* RED and drop levels of CQ on packet reception. 865 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 866 */ 867 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 868 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 869 870 /* RED and drop levels of AURA for packet reception. 871 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 872 * Eg: For RQ length 1K, for pass/drop level 204/230. 873 * RED accepts pkts if free pointers > 102 & <= 205. 874 * Drops pkts if free pointers < 102. 875 */ 876 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 877 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 878 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 879 880 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 881 { 882 struct otx2_qset *qset = &pfvf->qset; 883 struct nix_aq_enq_req *aq; 884 885 /* Get memory to put this msg */ 886 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 887 if (!aq) 888 return -ENOMEM; 889 890 aq->rq.cq = qidx; 891 aq->rq.ena = 1; 892 aq->rq.pb_caching = 1; 893 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 894 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 895 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 896 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 897 aq->rq.qint_idx = 0; 898 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 899 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 900 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 901 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 902 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 903 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 904 905 /* Fill AQ info */ 906 aq->qidx = qidx; 907 aq->ctype = NIX_AQ_CTYPE_RQ; 908 aq->op = NIX_AQ_INSTOP_INIT; 909 910 return otx2_sync_mbox_msg(&pfvf->mbox); 911 } 912 913 int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura) 914 { 915 struct otx2_nic *pfvf = dev; 916 struct otx2_snd_queue *sq; 917 struct nix_aq_enq_req *aq; 918 919 sq = &pfvf->qset.sq[qidx]; 920 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 921 /* Get memory to put this msg */ 922 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 923 if (!aq) 924 return -ENOMEM; 925 926 aq->sq.cq = pfvf->hw.rx_queues + qidx; 927 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 928 aq->sq.cq_ena = 1; 929 aq->sq.ena = 1; 930 aq->sq.smq = otx2_get_smq_idx(pfvf, qidx); 931 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 932 aq->sq.default_chan = pfvf->hw.tx_chan_base + chan_offset; 933 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 934 aq->sq.sqb_aura = sqb_aura; 935 aq->sq.sq_int_ena = NIX_SQINT_BITS; 936 aq->sq.qint_idx = 0; 937 /* Due pipelining impact minimum 2000 unused SQ CQE's 938 * need to maintain to avoid CQ overflow. 939 */ 940 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 941 942 /* Fill AQ info */ 943 aq->qidx = qidx; 944 aq->ctype = NIX_AQ_CTYPE_SQ; 945 aq->op = NIX_AQ_INSTOP_INIT; 946 947 return otx2_sync_mbox_msg(&pfvf->mbox); 948 } 949 950 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 951 { 952 struct otx2_qset *qset = &pfvf->qset; 953 struct otx2_snd_queue *sq; 954 struct otx2_pool *pool; 955 u8 chan_offset; 956 int err; 957 958 pool = &pfvf->qset.pool[sqb_aura]; 959 sq = &qset->sq[qidx]; 960 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 961 sq->sqe_cnt = qset->sqe_cnt; 962 963 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 964 if (err) 965 return err; 966 967 if (qidx < pfvf->hw.tx_queues) { 968 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 969 TSO_HEADER_SIZE); 970 if (err) 971 return err; 972 } 973 974 sq->sqe_base = sq->sqe->base; 975 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 976 if (!sq->sg) 977 return -ENOMEM; 978 979 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) { 980 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 981 sizeof(*sq->timestamps)); 982 if (err) { 983 kfree(sq->sg); 984 sq->sg = NULL; 985 return err; 986 } 987 } 988 989 sq->head = 0; 990 sq->cons_head = 0; 991 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 992 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 993 /* Set SQE threshold to 10% of total SQEs */ 994 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 995 sq->aura_id = sqb_aura; 996 sq->aura_fc_addr = pool->fc_addr->base; 997 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 998 999 sq->stats.bytes = 0; 1000 sq->stats.pkts = 0; 1001 1002 chan_offset = qidx % pfvf->hw.tx_chan_cnt; 1003 err = pfvf->hw_ops->sq_aq_init(pfvf, qidx, chan_offset, sqb_aura); 1004 if (err) { 1005 kfree(sq->sg); 1006 sq->sg = NULL; 1007 return err; 1008 } 1009 1010 return 0; 1011 1012 } 1013 1014 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 1015 { 1016 struct otx2_qset *qset = &pfvf->qset; 1017 int err, pool_id, non_xdp_queues; 1018 struct nix_aq_enq_req *aq; 1019 struct otx2_cq_queue *cq; 1020 1021 cq = &qset->cq[qidx]; 1022 cq->cq_idx = qidx; 1023 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues; 1024 if (qidx < pfvf->hw.rx_queues) { 1025 cq->cq_type = CQ_RX; 1026 cq->cint_idx = qidx; 1027 cq->cqe_cnt = qset->rqe_cnt; 1028 if (pfvf->xdp_prog) 1029 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0); 1030 } else if (qidx < non_xdp_queues) { 1031 cq->cq_type = CQ_TX; 1032 cq->cint_idx = qidx - pfvf->hw.rx_queues; 1033 cq->cqe_cnt = qset->sqe_cnt; 1034 } else { 1035 if (pfvf->hw.xdp_queues && 1036 qidx < non_xdp_queues + pfvf->hw.xdp_queues) { 1037 cq->cq_type = CQ_XDP; 1038 cq->cint_idx = qidx - non_xdp_queues; 1039 cq->cqe_cnt = qset->sqe_cnt; 1040 } else { 1041 cq->cq_type = CQ_QOS; 1042 cq->cint_idx = qidx - non_xdp_queues - 1043 pfvf->hw.xdp_queues; 1044 cq->cqe_cnt = qset->sqe_cnt; 1045 } 1046 } 1047 cq->cqe_size = pfvf->qset.xqe_size; 1048 1049 /* Allocate memory for CQEs */ 1050 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 1051 if (err) 1052 return err; 1053 1054 /* Save CQE CPU base for faster reference */ 1055 cq->cqe_base = cq->cqe->base; 1056 /* In case where all RQs auras point to single pool, 1057 * all CQs receive buffer pool also point to same pool. 1058 */ 1059 pool_id = ((cq->cq_type == CQ_RX) && 1060 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 1061 cq->rbpool = &qset->pool[pool_id]; 1062 cq->refill_task_sched = false; 1063 1064 /* Get memory to put this msg */ 1065 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 1066 if (!aq) 1067 return -ENOMEM; 1068 1069 aq->cq.ena = 1; 1070 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 1071 aq->cq.caching = 1; 1072 aq->cq.base = cq->cqe->iova; 1073 aq->cq.cint_idx = cq->cint_idx; 1074 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 1075 aq->cq.qint_idx = 0; 1076 aq->cq.avg_level = 255; 1077 1078 if (qidx < pfvf->hw.rx_queues) { 1079 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 1080 aq->cq.drop_ena = 1; 1081 1082 if (!is_otx2_lbkvf(pfvf->pdev)) { 1083 /* Enable receive CQ backpressure */ 1084 aq->cq.bp_ena = 1; 1085 #ifdef CONFIG_DCB 1086 aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]]; 1087 #else 1088 aq->cq.bpid = pfvf->bpid[0]; 1089 #endif 1090 1091 /* Set backpressure level is same as cq pass level */ 1092 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 1093 } 1094 } 1095 1096 /* Fill AQ info */ 1097 aq->qidx = qidx; 1098 aq->ctype = NIX_AQ_CTYPE_CQ; 1099 aq->op = NIX_AQ_INSTOP_INIT; 1100 1101 return otx2_sync_mbox_msg(&pfvf->mbox); 1102 } 1103 1104 static void otx2_pool_refill_task(struct work_struct *work) 1105 { 1106 struct otx2_cq_queue *cq; 1107 struct refill_work *wrk; 1108 struct otx2_nic *pfvf; 1109 int qidx; 1110 1111 wrk = container_of(work, struct refill_work, pool_refill_work.work); 1112 pfvf = wrk->pf; 1113 qidx = wrk - pfvf->refill_wrk; 1114 cq = &pfvf->qset.cq[qidx]; 1115 1116 cq->refill_task_sched = false; 1117 1118 local_bh_disable(); 1119 napi_schedule(wrk->napi); 1120 local_bh_enable(); 1121 } 1122 1123 int otx2_config_nix_queues(struct otx2_nic *pfvf) 1124 { 1125 int qidx, err; 1126 1127 /* Initialize RX queues */ 1128 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 1129 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 1130 1131 err = otx2_rq_init(pfvf, qidx, lpb_aura); 1132 if (err) 1133 return err; 1134 } 1135 1136 /* Initialize TX queues */ 1137 for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) { 1138 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1139 1140 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1141 if (err) 1142 return err; 1143 } 1144 1145 /* Initialize completion queues */ 1146 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1147 err = otx2_cq_init(pfvf, qidx); 1148 if (err) 1149 return err; 1150 } 1151 1152 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, 1153 NIX_LF_CQ_OP_STATUS); 1154 1155 /* Initialize work queue for receive buffer refill */ 1156 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1157 sizeof(struct refill_work), GFP_KERNEL); 1158 if (!pfvf->refill_wrk) 1159 return -ENOMEM; 1160 1161 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1162 pfvf->refill_wrk[qidx].pf = pfvf; 1163 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1164 otx2_pool_refill_task); 1165 } 1166 return 0; 1167 } 1168 1169 int otx2_config_nix(struct otx2_nic *pfvf) 1170 { 1171 struct nix_lf_alloc_req *nixlf; 1172 struct nix_lf_alloc_rsp *rsp; 1173 int err; 1174 1175 pfvf->qset.xqe_size = pfvf->hw.xqe_size; 1176 1177 /* Get memory to put this msg */ 1178 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1179 if (!nixlf) 1180 return -ENOMEM; 1181 1182 /* Set RQ/SQ/CQ counts */ 1183 nixlf->rq_cnt = pfvf->hw.rx_queues; 1184 nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf); 1185 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1186 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1187 nixlf->rss_grps = MAX_RSS_GROUPS; 1188 nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64; 1189 /* We don't know absolute NPA LF idx attached. 1190 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1191 * NPA LF attached to this RVU PF/VF. 1192 */ 1193 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1194 /* Disable alignment pad, enable L2 length check, 1195 * enable L4 TCP/UDP checksum verification. 1196 */ 1197 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1198 1199 err = otx2_sync_mbox_msg(&pfvf->mbox); 1200 if (err) 1201 return err; 1202 1203 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1204 &nixlf->hdr); 1205 if (IS_ERR(rsp)) 1206 return PTR_ERR(rsp); 1207 1208 if (rsp->qints < 1) 1209 return -ENXIO; 1210 1211 return rsp->hdr.rc; 1212 } 1213 1214 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1215 { 1216 struct otx2_qset *qset = &pfvf->qset; 1217 struct otx2_hw *hw = &pfvf->hw; 1218 struct otx2_snd_queue *sq; 1219 int sqb, qidx; 1220 u64 iova, pa; 1221 1222 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 1223 sq = &qset->sq[qidx]; 1224 if (!sq->sqb_ptrs) 1225 continue; 1226 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1227 if (!sq->sqb_ptrs[sqb]) 1228 continue; 1229 iova = sq->sqb_ptrs[sqb]; 1230 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1231 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1232 DMA_FROM_DEVICE, 1233 DMA_ATTR_SKIP_CPU_SYNC); 1234 put_page(virt_to_page(phys_to_virt(pa))); 1235 } 1236 sq->sqb_count = 0; 1237 } 1238 } 1239 1240 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1241 u64 iova, int size) 1242 { 1243 struct page *page; 1244 u64 pa; 1245 1246 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1247 page = virt_to_head_page(phys_to_virt(pa)); 1248 1249 if (pool->page_pool) { 1250 page_pool_put_full_page(pool->page_pool, page, true); 1251 } else { 1252 dma_unmap_page_attrs(pfvf->dev, iova, size, 1253 DMA_FROM_DEVICE, 1254 DMA_ATTR_SKIP_CPU_SYNC); 1255 1256 put_page(page); 1257 } 1258 } 1259 1260 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1261 { 1262 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1263 struct otx2_pool *pool; 1264 u64 iova; 1265 1266 if (type == AURA_NIX_SQ) { 1267 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1268 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1269 size = pfvf->hw.sqb_size; 1270 } 1271 if (type == AURA_NIX_RQ) { 1272 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1273 pool_end = pfvf->hw.rqpool_cnt; 1274 size = pfvf->rbsize; 1275 } 1276 1277 /* Free SQB and RQB pointers from the aura pool */ 1278 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1279 iova = otx2_aura_allocptr(pfvf, pool_id); 1280 pool = &pfvf->qset.pool[pool_id]; 1281 while (iova) { 1282 if (type == AURA_NIX_RQ) 1283 iova -= OTX2_HEAD_ROOM; 1284 1285 otx2_free_bufs(pfvf, pool, iova, size); 1286 1287 iova = otx2_aura_allocptr(pfvf, pool_id); 1288 } 1289 } 1290 } 1291 1292 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1293 { 1294 struct otx2_pool *pool; 1295 int pool_id; 1296 1297 if (!pfvf->qset.pool) 1298 return; 1299 1300 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1301 pool = &pfvf->qset.pool[pool_id]; 1302 qmem_free(pfvf->dev, pool->stack); 1303 qmem_free(pfvf->dev, pool->fc_addr); 1304 page_pool_destroy(pool->page_pool); 1305 pool->page_pool = NULL; 1306 } 1307 devm_kfree(pfvf->dev, pfvf->qset.pool); 1308 pfvf->qset.pool = NULL; 1309 } 1310 1311 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1312 int pool_id, int numptrs) 1313 { 1314 struct npa_aq_enq_req *aq; 1315 struct otx2_pool *pool; 1316 int err; 1317 1318 pool = &pfvf->qset.pool[pool_id]; 1319 1320 /* Allocate memory for HW to update Aura count. 1321 * Alloc one cache line, so that it fits all FC_STYPE modes. 1322 */ 1323 if (!pool->fc_addr) { 1324 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1325 if (err) 1326 return err; 1327 } 1328 1329 /* Initialize this aura's context via AF */ 1330 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1331 if (!aq) { 1332 /* Shared mbox memory buffer is full, flush it and retry */ 1333 err = otx2_sync_mbox_msg(&pfvf->mbox); 1334 if (err) 1335 return err; 1336 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1337 if (!aq) 1338 return -ENOMEM; 1339 } 1340 1341 aq->aura_id = aura_id; 1342 /* Will be filled by AF with correct pool context address */ 1343 aq->aura.pool_addr = pool_id; 1344 aq->aura.pool_caching = 1; 1345 aq->aura.shift = ilog2(numptrs) - 8; 1346 aq->aura.count = numptrs; 1347 aq->aura.limit = numptrs; 1348 aq->aura.avg_level = 255; 1349 aq->aura.ena = 1; 1350 aq->aura.fc_ena = 1; 1351 aq->aura.fc_addr = pool->fc_addr->iova; 1352 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1353 1354 /* Enable backpressure for RQ aura */ 1355 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1356 aq->aura.bp_ena = 0; 1357 /* If NIX1 LF is attached then specify NIX1_RX. 1358 * 1359 * Below NPA_AURA_S[BP_ENA] is set according to the 1360 * NPA_BPINTF_E enumeration given as: 1361 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1362 * NIX0_RX is 0x0 + 0*0x1 = 0 1363 * NIX1_RX is 0x0 + 1*0x1 = 1 1364 * But in HRM it is given that 1365 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1366 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1367 * enumerated by NPA_BPINTF_E." 1368 */ 1369 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1370 aq->aura.bp_ena = 1; 1371 #ifdef CONFIG_DCB 1372 aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]]; 1373 #else 1374 aq->aura.nix0_bpid = pfvf->bpid[0]; 1375 #endif 1376 1377 /* Set backpressure level for RQ's Aura */ 1378 aq->aura.bp = RQ_BP_LVL_AURA; 1379 } 1380 1381 /* Fill AQ info */ 1382 aq->ctype = NPA_AQ_CTYPE_AURA; 1383 aq->op = NPA_AQ_INSTOP_INIT; 1384 1385 return 0; 1386 } 1387 1388 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1389 int stack_pages, int numptrs, int buf_size, int type) 1390 { 1391 struct page_pool_params pp_params = { 0 }; 1392 struct npa_aq_enq_req *aq; 1393 struct otx2_pool *pool; 1394 int err; 1395 1396 pool = &pfvf->qset.pool[pool_id]; 1397 /* Alloc memory for stack which is used to store buffer pointers */ 1398 err = qmem_alloc(pfvf->dev, &pool->stack, 1399 stack_pages, pfvf->hw.stack_pg_bytes); 1400 if (err) 1401 return err; 1402 1403 pool->rbsize = buf_size; 1404 1405 /* Initialize this pool's context via AF */ 1406 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1407 if (!aq) { 1408 /* Shared mbox memory buffer is full, flush it and retry */ 1409 err = otx2_sync_mbox_msg(&pfvf->mbox); 1410 if (err) { 1411 qmem_free(pfvf->dev, pool->stack); 1412 return err; 1413 } 1414 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1415 if (!aq) { 1416 qmem_free(pfvf->dev, pool->stack); 1417 return -ENOMEM; 1418 } 1419 } 1420 1421 aq->aura_id = pool_id; 1422 aq->pool.stack_base = pool->stack->iova; 1423 aq->pool.stack_caching = 1; 1424 aq->pool.ena = 1; 1425 aq->pool.buf_size = buf_size / 128; 1426 aq->pool.stack_max_pages = stack_pages; 1427 aq->pool.shift = ilog2(numptrs) - 8; 1428 aq->pool.ptr_start = 0; 1429 aq->pool.ptr_end = ~0ULL; 1430 1431 /* Fill AQ info */ 1432 aq->ctype = NPA_AQ_CTYPE_POOL; 1433 aq->op = NPA_AQ_INSTOP_INIT; 1434 1435 if (type != AURA_NIX_RQ) { 1436 pool->page_pool = NULL; 1437 return 0; 1438 } 1439 1440 pp_params.order = get_order(buf_size); 1441 pp_params.flags = PP_FLAG_DMA_MAP; 1442 pp_params.pool_size = min(OTX2_PAGE_POOL_SZ, numptrs); 1443 pp_params.nid = NUMA_NO_NODE; 1444 pp_params.dev = pfvf->dev; 1445 pp_params.dma_dir = DMA_FROM_DEVICE; 1446 pool->page_pool = page_pool_create(&pp_params); 1447 if (IS_ERR(pool->page_pool)) { 1448 netdev_err(pfvf->netdev, "Creation of page pool failed\n"); 1449 return PTR_ERR(pool->page_pool); 1450 } 1451 1452 return 0; 1453 } 1454 1455 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1456 { 1457 int qidx, pool_id, stack_pages, num_sqbs; 1458 struct otx2_qset *qset = &pfvf->qset; 1459 struct otx2_hw *hw = &pfvf->hw; 1460 struct otx2_snd_queue *sq; 1461 struct otx2_pool *pool; 1462 dma_addr_t bufptr; 1463 int err, ptr; 1464 1465 /* Calculate number of SQBs needed. 1466 * 1467 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1468 * Last SQE is used for pointing to next SQB. 1469 */ 1470 num_sqbs = (hw->sqb_size / 128) - 1; 1471 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1472 1473 /* Get no of stack pages needed */ 1474 stack_pages = 1475 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1476 1477 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1478 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1479 /* Initialize aura context */ 1480 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1481 if (err) 1482 goto fail; 1483 1484 /* Initialize pool context */ 1485 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1486 num_sqbs, hw->sqb_size, AURA_NIX_SQ); 1487 if (err) 1488 goto fail; 1489 } 1490 1491 /* Flush accumulated messages */ 1492 err = otx2_sync_mbox_msg(&pfvf->mbox); 1493 if (err) 1494 goto fail; 1495 1496 /* Allocate pointers and free them to aura/pool */ 1497 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1498 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1499 pool = &pfvf->qset.pool[pool_id]; 1500 1501 sq = &qset->sq[qidx]; 1502 sq->sqb_count = 0; 1503 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1504 if (!sq->sqb_ptrs) { 1505 err = -ENOMEM; 1506 goto err_mem; 1507 } 1508 1509 for (ptr = 0; ptr < num_sqbs; ptr++) { 1510 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1511 if (err) 1512 goto err_mem; 1513 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1514 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1515 } 1516 } 1517 1518 err_mem: 1519 return err ? -ENOMEM : 0; 1520 1521 fail: 1522 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1523 otx2_aura_pool_free(pfvf); 1524 return err; 1525 } 1526 1527 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1528 { 1529 struct otx2_hw *hw = &pfvf->hw; 1530 int stack_pages, pool_id, rq; 1531 struct otx2_pool *pool; 1532 int err, ptr, num_ptrs; 1533 dma_addr_t bufptr; 1534 1535 num_ptrs = pfvf->qset.rqe_cnt; 1536 1537 stack_pages = 1538 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1539 1540 for (rq = 0; rq < hw->rx_queues; rq++) { 1541 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1542 /* Initialize aura context */ 1543 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1544 if (err) 1545 goto fail; 1546 } 1547 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1548 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1549 num_ptrs, pfvf->rbsize, AURA_NIX_RQ); 1550 if (err) 1551 goto fail; 1552 } 1553 1554 /* Flush accumulated messages */ 1555 err = otx2_sync_mbox_msg(&pfvf->mbox); 1556 if (err) 1557 goto fail; 1558 1559 /* Allocate pointers and free them to aura/pool */ 1560 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1561 pool = &pfvf->qset.pool[pool_id]; 1562 for (ptr = 0; ptr < num_ptrs; ptr++) { 1563 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1564 if (err) 1565 return -ENOMEM; 1566 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1567 bufptr + OTX2_HEAD_ROOM); 1568 } 1569 } 1570 return 0; 1571 fail: 1572 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1573 otx2_aura_pool_free(pfvf); 1574 return err; 1575 } 1576 1577 int otx2_config_npa(struct otx2_nic *pfvf) 1578 { 1579 struct otx2_qset *qset = &pfvf->qset; 1580 struct npa_lf_alloc_req *npalf; 1581 struct otx2_hw *hw = &pfvf->hw; 1582 int aura_cnt; 1583 1584 /* Pool - Stack of free buffer pointers 1585 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1586 */ 1587 1588 if (!hw->pool_cnt) 1589 return -EINVAL; 1590 1591 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1592 sizeof(struct otx2_pool), GFP_KERNEL); 1593 if (!qset->pool) 1594 return -ENOMEM; 1595 1596 /* Get memory to put this msg */ 1597 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1598 if (!npalf) 1599 return -ENOMEM; 1600 1601 /* Set aura and pool counts */ 1602 npalf->nr_pools = hw->pool_cnt; 1603 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1604 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1605 1606 return otx2_sync_mbox_msg(&pfvf->mbox); 1607 } 1608 1609 int otx2_detach_resources(struct mbox *mbox) 1610 { 1611 struct rsrc_detach *detach; 1612 1613 mutex_lock(&mbox->lock); 1614 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1615 if (!detach) { 1616 mutex_unlock(&mbox->lock); 1617 return -ENOMEM; 1618 } 1619 1620 /* detach all */ 1621 detach->partial = false; 1622 1623 /* Send detach request to AF */ 1624 otx2_sync_mbox_msg(mbox); 1625 mutex_unlock(&mbox->lock); 1626 return 0; 1627 } 1628 EXPORT_SYMBOL(otx2_detach_resources); 1629 1630 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1631 { 1632 struct rsrc_attach *attach; 1633 struct msg_req *msix; 1634 int err; 1635 1636 mutex_lock(&pfvf->mbox.lock); 1637 /* Get memory to put this msg */ 1638 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1639 if (!attach) { 1640 mutex_unlock(&pfvf->mbox.lock); 1641 return -ENOMEM; 1642 } 1643 1644 attach->npalf = true; 1645 attach->nixlf = true; 1646 1647 /* Send attach request to AF */ 1648 err = otx2_sync_mbox_msg(&pfvf->mbox); 1649 if (err) { 1650 mutex_unlock(&pfvf->mbox.lock); 1651 return err; 1652 } 1653 1654 pfvf->nix_blkaddr = BLKADDR_NIX0; 1655 1656 /* If the platform has two NIX blocks then LF may be 1657 * allocated from NIX1. 1658 */ 1659 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1660 pfvf->nix_blkaddr = BLKADDR_NIX1; 1661 1662 /* Get NPA and NIX MSIX vector offsets */ 1663 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1664 if (!msix) { 1665 mutex_unlock(&pfvf->mbox.lock); 1666 return -ENOMEM; 1667 } 1668 1669 err = otx2_sync_mbox_msg(&pfvf->mbox); 1670 if (err) { 1671 mutex_unlock(&pfvf->mbox.lock); 1672 return err; 1673 } 1674 mutex_unlock(&pfvf->mbox.lock); 1675 1676 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1677 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1678 dev_err(pfvf->dev, 1679 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1680 return -EINVAL; 1681 } 1682 1683 return 0; 1684 } 1685 EXPORT_SYMBOL(otx2_attach_npa_nix); 1686 1687 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1688 { 1689 struct hwctx_disable_req *req; 1690 1691 mutex_lock(&mbox->lock); 1692 /* Request AQ to disable this context */ 1693 if (npa) 1694 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1695 else 1696 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1697 1698 if (!req) { 1699 mutex_unlock(&mbox->lock); 1700 return; 1701 } 1702 1703 req->ctype = type; 1704 1705 if (otx2_sync_mbox_msg(mbox)) 1706 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1707 __func__); 1708 1709 mutex_unlock(&mbox->lock); 1710 } 1711 1712 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1713 { 1714 struct nix_bp_cfg_req *req; 1715 1716 if (enable) 1717 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1718 else 1719 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1720 1721 if (!req) 1722 return -ENOMEM; 1723 1724 req->chan_base = 0; 1725 #ifdef CONFIG_DCB 1726 req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1; 1727 req->bpid_per_chan = pfvf->pfc_en ? 1 : 0; 1728 #else 1729 req->chan_cnt = 1; 1730 req->bpid_per_chan = 0; 1731 #endif 1732 1733 return otx2_sync_mbox_msg(&pfvf->mbox); 1734 } 1735 EXPORT_SYMBOL(otx2_nix_config_bp); 1736 1737 /* Mbox message handlers */ 1738 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1739 struct cgx_stats_rsp *rsp) 1740 { 1741 int id; 1742 1743 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1744 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1745 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1746 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1747 } 1748 1749 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1750 struct cgx_fec_stats_rsp *rsp) 1751 { 1752 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1753 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1754 } 1755 1756 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1757 struct npa_lf_alloc_rsp *rsp) 1758 { 1759 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1760 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1761 } 1762 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1763 1764 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1765 struct nix_lf_alloc_rsp *rsp) 1766 { 1767 pfvf->hw.sqb_size = rsp->sqb_size; 1768 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1769 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1770 pfvf->hw.rx_chan_cnt = rsp->rx_chan_cnt; 1771 pfvf->hw.tx_chan_cnt = rsp->tx_chan_cnt; 1772 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1773 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1774 pfvf->hw.cgx_links = rsp->cgx_links; 1775 pfvf->hw.lbk_links = rsp->lbk_links; 1776 pfvf->hw.tx_link = rsp->tx_link; 1777 } 1778 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1779 1780 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1781 struct msix_offset_rsp *rsp) 1782 { 1783 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1784 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1785 } 1786 EXPORT_SYMBOL(mbox_handler_msix_offset); 1787 1788 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1789 struct nix_bp_cfg_rsp *rsp) 1790 { 1791 int chan, chan_id; 1792 1793 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1794 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1795 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1796 } 1797 } 1798 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1799 1800 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1801 { 1802 struct otx2_qset *qset = &pfvf->qset; 1803 struct otx2_hw *hw = &pfvf->hw; 1804 int irq, qidx; 1805 1806 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1807 qidx < n; 1808 qidx++, irq++) { 1809 int vector = pci_irq_vector(pfvf->pdev, irq); 1810 1811 irq_set_affinity_hint(vector, NULL); 1812 free_cpumask_var(hw->affinity_mask[irq]); 1813 free_irq(vector, &qset->napi[qidx]); 1814 } 1815 } 1816 EXPORT_SYMBOL(otx2_free_cints); 1817 1818 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1819 { 1820 struct otx2_hw *hw = &pfvf->hw; 1821 int vec, cpu, irq, cint; 1822 1823 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1824 cpu = cpumask_first(cpu_online_mask); 1825 1826 /* CQ interrupts */ 1827 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1828 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1829 return; 1830 1831 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1832 1833 irq = pci_irq_vector(pfvf->pdev, vec); 1834 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1835 1836 cpu = cpumask_next(cpu, cpu_online_mask); 1837 if (unlikely(cpu >= nr_cpu_ids)) 1838 cpu = 0; 1839 } 1840 } 1841 1842 static u32 get_dwrr_mtu(struct otx2_nic *pfvf, struct nix_hw_info *hw) 1843 { 1844 if (is_otx2_lbkvf(pfvf->pdev)) { 1845 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_LBK; 1846 return hw->lbk_dwrr_mtu; 1847 } 1848 1849 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_RPM; 1850 return hw->rpm_dwrr_mtu; 1851 } 1852 1853 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1854 { 1855 struct nix_hw_info *rsp; 1856 struct msg_req *req; 1857 u16 max_mtu; 1858 int rc; 1859 1860 mutex_lock(&pfvf->mbox.lock); 1861 1862 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1863 if (!req) { 1864 rc = -ENOMEM; 1865 goto out; 1866 } 1867 1868 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1869 if (!rc) { 1870 rsp = (struct nix_hw_info *) 1871 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1872 if (IS_ERR(rsp)) { 1873 rc = PTR_ERR(rsp); 1874 goto out; 1875 } 1876 1877 /* HW counts VLAN insertion bytes (8 for double tag) 1878 * irrespective of whether SQE is requesting to insert VLAN 1879 * in the packet or not. Hence these 8 bytes have to be 1880 * discounted from max packet size otherwise HW will throw 1881 * SMQ errors 1882 */ 1883 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1884 1885 /* Also save DWRR MTU, needed for DWRR weight calculation */ 1886 pfvf->hw.dwrr_mtu = get_dwrr_mtu(pfvf, rsp); 1887 if (!pfvf->hw.dwrr_mtu) 1888 pfvf->hw.dwrr_mtu = 1; 1889 } 1890 1891 out: 1892 mutex_unlock(&pfvf->mbox.lock); 1893 if (rc) { 1894 dev_warn(pfvf->dev, 1895 "Failed to get MTU from hardware setting default value(1500)\n"); 1896 max_mtu = 1500; 1897 } 1898 return max_mtu; 1899 } 1900 EXPORT_SYMBOL(otx2_get_max_mtu); 1901 1902 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features) 1903 { 1904 netdev_features_t changed = features ^ netdev->features; 1905 struct otx2_nic *pfvf = netdev_priv(netdev); 1906 bool ntuple = !!(features & NETIF_F_NTUPLE); 1907 bool tc = !!(features & NETIF_F_HW_TC); 1908 1909 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1910 otx2_destroy_ntuple_flows(pfvf); 1911 1912 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1913 if (!pfvf->flow_cfg->max_flows) { 1914 netdev_err(netdev, 1915 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1916 return -EINVAL; 1917 } 1918 } 1919 1920 if ((changed & NETIF_F_HW_TC) && !tc && 1921 otx2_tc_flower_rule_cnt(pfvf)) { 1922 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1923 return -EBUSY; 1924 } 1925 1926 if ((changed & NETIF_F_NTUPLE) && ntuple && 1927 otx2_tc_flower_rule_cnt(pfvf) && !(changed & NETIF_F_HW_TC)) { 1928 netdev_err(netdev, 1929 "Can't enable NTUPLE when TC flower offload is active, disable TC rules and retry\n"); 1930 return -EINVAL; 1931 } 1932 1933 return 0; 1934 } 1935 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features); 1936 1937 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1938 int __weak \ 1939 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1940 struct _req_type *req, \ 1941 struct _rsp_type *rsp) \ 1942 { \ 1943 /* Nothing to do here */ \ 1944 return 0; \ 1945 } \ 1946 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1947 MBOX_UP_CGX_MESSAGES 1948 MBOX_UP_MCS_MESSAGES 1949 #undef M 1950