1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <net/tso.h> 14 15 #include "otx2_reg.h" 16 #include "otx2_common.h" 17 #include "otx2_struct.h" 18 19 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 20 struct otx2_nic *pfvf, int qidx) 21 { 22 u64 incr = (u64)qidx << 32; 23 u64 *ptr; 24 25 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 26 stats->bytes = otx2_atomic64_add(incr, ptr); 27 28 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 29 stats->pkts = otx2_atomic64_add(incr, ptr); 30 } 31 32 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 33 struct otx2_nic *pfvf, int qidx) 34 { 35 u64 incr = (u64)qidx << 32; 36 u64 *ptr; 37 38 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 39 stats->bytes = otx2_atomic64_add(incr, ptr); 40 41 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 42 stats->pkts = otx2_atomic64_add(incr, ptr); 43 } 44 45 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 46 { 47 struct msg_req *req; 48 49 if (!netif_running(pfvf->netdev)) 50 return; 51 52 otx2_mbox_lock(&pfvf->mbox); 53 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 54 if (!req) { 55 otx2_mbox_unlock(&pfvf->mbox); 56 return; 57 } 58 59 otx2_sync_mbox_msg(&pfvf->mbox); 60 otx2_mbox_unlock(&pfvf->mbox); 61 } 62 63 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 64 { 65 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 66 67 if (!pfvf->qset.rq) 68 return 0; 69 70 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 71 return 1; 72 } 73 74 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 75 { 76 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 77 78 if (!pfvf->qset.sq) 79 return 0; 80 81 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 82 return 1; 83 } 84 85 void otx2_get_dev_stats(struct otx2_nic *pfvf) 86 { 87 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 88 89 #define OTX2_GET_RX_STATS(reg) \ 90 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 91 #define OTX2_GET_TX_STATS(reg) \ 92 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 93 94 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 95 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 96 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 97 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 98 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 99 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 100 dev_stats->rx_mcast_frames + 101 dev_stats->rx_ucast_frames; 102 103 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 104 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 105 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 106 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 107 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 108 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 109 dev_stats->tx_mcast_frames + 110 dev_stats->tx_ucast_frames; 111 } 112 113 void otx2_get_stats64(struct net_device *netdev, 114 struct rtnl_link_stats64 *stats) 115 { 116 struct otx2_nic *pfvf = netdev_priv(netdev); 117 struct otx2_dev_stats *dev_stats; 118 119 otx2_get_dev_stats(pfvf); 120 121 dev_stats = &pfvf->hw.dev_stats; 122 stats->rx_bytes = dev_stats->rx_bytes; 123 stats->rx_packets = dev_stats->rx_frames; 124 stats->rx_dropped = dev_stats->rx_drops; 125 stats->multicast = dev_stats->rx_mcast_frames; 126 127 stats->tx_bytes = dev_stats->tx_bytes; 128 stats->tx_packets = dev_stats->tx_frames; 129 stats->tx_dropped = dev_stats->tx_drops; 130 } 131 132 /* Sync MAC address with RVU AF */ 133 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 134 { 135 struct nix_set_mac_addr *req; 136 int err; 137 138 otx2_mbox_lock(&pfvf->mbox); 139 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 140 if (!req) { 141 otx2_mbox_unlock(&pfvf->mbox); 142 return -ENOMEM; 143 } 144 145 ether_addr_copy(req->mac_addr, mac); 146 147 err = otx2_sync_mbox_msg(&pfvf->mbox); 148 otx2_mbox_unlock(&pfvf->mbox); 149 return err; 150 } 151 152 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 153 struct net_device *netdev) 154 { 155 struct nix_get_mac_addr_rsp *rsp; 156 struct mbox_msghdr *msghdr; 157 struct msg_req *req; 158 int err; 159 160 otx2_mbox_lock(&pfvf->mbox); 161 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 162 if (!req) { 163 otx2_mbox_unlock(&pfvf->mbox); 164 return -ENOMEM; 165 } 166 167 err = otx2_sync_mbox_msg(&pfvf->mbox); 168 if (err) { 169 otx2_mbox_unlock(&pfvf->mbox); 170 return err; 171 } 172 173 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 174 if (IS_ERR(msghdr)) { 175 otx2_mbox_unlock(&pfvf->mbox); 176 return PTR_ERR(msghdr); 177 } 178 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 179 ether_addr_copy(netdev->dev_addr, rsp->mac_addr); 180 otx2_mbox_unlock(&pfvf->mbox); 181 182 return 0; 183 } 184 185 int otx2_set_mac_address(struct net_device *netdev, void *p) 186 { 187 struct otx2_nic *pfvf = netdev_priv(netdev); 188 struct sockaddr *addr = p; 189 190 if (!is_valid_ether_addr(addr->sa_data)) 191 return -EADDRNOTAVAIL; 192 193 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) 194 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 195 else 196 return -EPERM; 197 198 return 0; 199 } 200 201 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 202 { 203 struct nix_frs_cfg *req; 204 int err; 205 206 otx2_mbox_lock(&pfvf->mbox); 207 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 208 if (!req) { 209 otx2_mbox_unlock(&pfvf->mbox); 210 return -ENOMEM; 211 } 212 213 /* SMQ config limits maximum pkt size that can be transmitted */ 214 req->update_smq = true; 215 pfvf->max_frs = mtu + OTX2_ETH_HLEN; 216 req->maxlen = pfvf->max_frs; 217 218 err = otx2_sync_mbox_msg(&pfvf->mbox); 219 otx2_mbox_unlock(&pfvf->mbox); 220 return err; 221 } 222 223 int otx2_config_pause_frm(struct otx2_nic *pfvf) 224 { 225 struct cgx_pause_frm_cfg *req; 226 int err; 227 228 otx2_mbox_lock(&pfvf->mbox); 229 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 230 if (!req) { 231 err = -ENOMEM; 232 goto unlock; 233 } 234 235 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 236 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 237 req->set = 1; 238 239 err = otx2_sync_mbox_msg(&pfvf->mbox); 240 unlock: 241 otx2_mbox_unlock(&pfvf->mbox); 242 return err; 243 } 244 245 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 246 { 247 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 248 struct nix_rss_flowkey_cfg *req; 249 int err; 250 251 otx2_mbox_lock(&pfvf->mbox); 252 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 253 if (!req) { 254 otx2_mbox_unlock(&pfvf->mbox); 255 return -ENOMEM; 256 } 257 req->mcam_index = -1; /* Default or reserved index */ 258 req->flowkey_cfg = rss->flowkey_cfg; 259 req->group = DEFAULT_RSS_CONTEXT_GROUP; 260 261 err = otx2_sync_mbox_msg(&pfvf->mbox); 262 otx2_mbox_unlock(&pfvf->mbox); 263 return err; 264 } 265 266 int otx2_set_rss_table(struct otx2_nic *pfvf) 267 { 268 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 269 struct mbox *mbox = &pfvf->mbox; 270 struct nix_aq_enq_req *aq; 271 int idx, err; 272 273 otx2_mbox_lock(mbox); 274 /* Get memory to put this msg */ 275 for (idx = 0; idx < rss->rss_size; idx++) { 276 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 277 if (!aq) { 278 /* The shared memory buffer can be full. 279 * Flush it and retry 280 */ 281 err = otx2_sync_mbox_msg(mbox); 282 if (err) { 283 otx2_mbox_unlock(mbox); 284 return err; 285 } 286 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 287 if (!aq) { 288 otx2_mbox_unlock(mbox); 289 return -ENOMEM; 290 } 291 } 292 293 aq->rss.rq = rss->ind_tbl[idx]; 294 295 /* Fill AQ info */ 296 aq->qidx = idx; 297 aq->ctype = NIX_AQ_CTYPE_RSS; 298 aq->op = NIX_AQ_INSTOP_INIT; 299 } 300 err = otx2_sync_mbox_msg(mbox); 301 otx2_mbox_unlock(mbox); 302 return err; 303 } 304 305 void otx2_set_rss_key(struct otx2_nic *pfvf) 306 { 307 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 308 u64 *key = (u64 *)&rss->key[4]; 309 int idx; 310 311 /* 352bit or 44byte key needs to be configured as below 312 * NIX_LF_RX_SECRETX0 = key<351:288> 313 * NIX_LF_RX_SECRETX1 = key<287:224> 314 * NIX_LF_RX_SECRETX2 = key<223:160> 315 * NIX_LF_RX_SECRETX3 = key<159:96> 316 * NIX_LF_RX_SECRETX4 = key<95:32> 317 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 318 */ 319 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 320 (u64)(*((u32 *)&rss->key)) << 32); 321 idx = sizeof(rss->key) / sizeof(u64); 322 while (idx > 0) { 323 idx--; 324 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 325 } 326 } 327 328 int otx2_rss_init(struct otx2_nic *pfvf) 329 { 330 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 331 int idx, ret = 0; 332 333 rss->rss_size = sizeof(rss->ind_tbl); 334 335 /* Init RSS key if it is not setup already */ 336 if (!rss->enable) 337 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 338 otx2_set_rss_key(pfvf); 339 340 if (!netif_is_rxfh_configured(pfvf->netdev)) { 341 /* Default indirection table */ 342 for (idx = 0; idx < rss->rss_size; idx++) 343 rss->ind_tbl[idx] = 344 ethtool_rxfh_indir_default(idx, 345 pfvf->hw.rx_queues); 346 } 347 ret = otx2_set_rss_table(pfvf); 348 if (ret) 349 return ret; 350 351 /* Flowkey or hash config to be used for generating flow tag */ 352 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 353 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 354 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 355 NIX_FLOW_KEY_TYPE_SCTP; 356 357 ret = otx2_set_flowkey_cfg(pfvf); 358 if (ret) 359 return ret; 360 361 rss->enable = true; 362 return 0; 363 } 364 365 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 366 { 367 /* Configure CQE interrupt coalescing parameters 368 * 369 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 370 * set 1 less than cq_ecount_wait. And cq_time_wait is in 371 * usecs, convert that to 100ns count. 372 */ 373 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 374 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 375 ((u64)pfvf->hw.cq_qcount_wait << 32) | 376 (pfvf->hw.cq_ecount_wait - 1)); 377 } 378 379 dma_addr_t otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 380 gfp_t gfp) 381 { 382 dma_addr_t iova; 383 384 /* Check if request can be accommodated in previous allocated page */ 385 if (pool->page && ((pool->page_offset + pool->rbsize) <= 386 (PAGE_SIZE << pool->rbpage_order))) { 387 pool->pageref++; 388 goto ret; 389 } 390 391 otx2_get_page(pool); 392 393 /* Allocate a new page */ 394 pool->page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN, 395 pool->rbpage_order); 396 if (unlikely(!pool->page)) 397 return -ENOMEM; 398 399 pool->page_offset = 0; 400 ret: 401 iova = (u64)otx2_dma_map_page(pfvf, pool->page, pool->page_offset, 402 pool->rbsize, DMA_FROM_DEVICE); 403 if (!iova) { 404 if (!pool->page_offset) 405 __free_pages(pool->page, pool->rbpage_order); 406 pool->page = NULL; 407 return -ENOMEM; 408 } 409 pool->page_offset += pool->rbsize; 410 return iova; 411 } 412 413 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 414 { 415 struct otx2_nic *pfvf = netdev_priv(netdev); 416 417 schedule_work(&pfvf->reset_task); 418 } 419 420 void otx2_get_mac_from_af(struct net_device *netdev) 421 { 422 struct otx2_nic *pfvf = netdev_priv(netdev); 423 int err; 424 425 err = otx2_hw_get_mac_addr(pfvf, netdev); 426 if (err) 427 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 428 429 /* If AF doesn't provide a valid MAC, generate a random one */ 430 if (!is_valid_ether_addr(netdev->dev_addr)) 431 eth_hw_addr_random(netdev); 432 } 433 434 static int otx2_get_link(struct otx2_nic *pfvf) 435 { 436 int link = 0; 437 u16 map; 438 439 /* cgx lmac link */ 440 if (pfvf->hw.tx_chan_base >= CGX_CHAN_BASE) { 441 map = pfvf->hw.tx_chan_base & 0x7FF; 442 link = 4 * ((map >> 8) & 0xF) + ((map >> 4) & 0xF); 443 } 444 /* LBK channel */ 445 if (pfvf->hw.tx_chan_base < SDP_CHAN_BASE) 446 link = 12; 447 448 return link; 449 } 450 451 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl) 452 { 453 struct otx2_hw *hw = &pfvf->hw; 454 struct nix_txschq_config *req; 455 u64 schq, parent; 456 457 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 458 if (!req) 459 return -ENOMEM; 460 461 req->lvl = lvl; 462 req->num_regs = 1; 463 464 schq = hw->txschq_list[lvl][0]; 465 /* Set topology e.t.c configuration */ 466 if (lvl == NIX_TXSCH_LVL_SMQ) { 467 req->reg[0] = NIX_AF_SMQX_CFG(schq); 468 req->regval[0] = ((pfvf->netdev->mtu + OTX2_ETH_HLEN) << 8) | 469 OTX2_MIN_MTU; 470 471 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 472 (0x2ULL << 36); 473 req->num_regs++; 474 /* MDQ config */ 475 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0]; 476 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 477 req->regval[1] = parent << 16; 478 req->num_regs++; 479 /* Set DWRR quantum */ 480 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 481 req->regval[2] = DFLT_RR_QTM; 482 } else if (lvl == NIX_TXSCH_LVL_TL4) { 483 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0]; 484 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 485 req->regval[0] = parent << 16; 486 req->num_regs++; 487 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 488 req->regval[1] = DFLT_RR_QTM; 489 } else if (lvl == NIX_TXSCH_LVL_TL3) { 490 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0]; 491 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 492 req->regval[0] = parent << 16; 493 req->num_regs++; 494 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 495 req->regval[1] = DFLT_RR_QTM; 496 } else if (lvl == NIX_TXSCH_LVL_TL2) { 497 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0]; 498 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 499 req->regval[0] = parent << 16; 500 501 req->num_regs++; 502 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 503 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | DFLT_RR_QTM; 504 505 req->num_regs++; 506 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, 507 otx2_get_link(pfvf)); 508 /* Enable this queue and backpressure */ 509 req->regval[2] = BIT_ULL(13) | BIT_ULL(12); 510 511 } else if (lvl == NIX_TXSCH_LVL_TL1) { 512 /* Default config for TL1. 513 * For VF this is always ignored. 514 */ 515 516 /* Set DWRR quantum */ 517 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 518 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 519 520 req->num_regs++; 521 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 522 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 523 524 req->num_regs++; 525 req->reg[2] = NIX_AF_TL1X_CIR(schq); 526 req->regval[2] = 0; 527 } 528 529 return otx2_sync_mbox_msg(&pfvf->mbox); 530 } 531 532 int otx2_txsch_alloc(struct otx2_nic *pfvf) 533 { 534 struct nix_txsch_alloc_req *req; 535 int lvl; 536 537 /* Get memory to put this msg */ 538 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 539 if (!req) 540 return -ENOMEM; 541 542 /* Request one schq per level */ 543 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 544 req->schq[lvl] = 1; 545 546 return otx2_sync_mbox_msg(&pfvf->mbox); 547 } 548 549 int otx2_txschq_stop(struct otx2_nic *pfvf) 550 { 551 struct nix_txsch_free_req *free_req; 552 int lvl, schq, err; 553 554 otx2_mbox_lock(&pfvf->mbox); 555 /* Free the transmit schedulers */ 556 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 557 if (!free_req) { 558 otx2_mbox_unlock(&pfvf->mbox); 559 return -ENOMEM; 560 } 561 562 free_req->flags = TXSCHQ_FREE_ALL; 563 err = otx2_sync_mbox_msg(&pfvf->mbox); 564 otx2_mbox_unlock(&pfvf->mbox); 565 566 /* Clear the txschq list */ 567 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 568 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 569 pfvf->hw.txschq_list[lvl][schq] = 0; 570 } 571 return err; 572 } 573 574 void otx2_sqb_flush(struct otx2_nic *pfvf) 575 { 576 int qidx, sqe_tail, sqe_head; 577 u64 incr, *ptr, val; 578 579 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 580 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 581 incr = (u64)qidx << 32; 582 while (1) { 583 val = otx2_atomic64_add(incr, ptr); 584 sqe_head = (val >> 20) & 0x3F; 585 sqe_tail = (val >> 28) & 0x3F; 586 if (sqe_head == sqe_tail) 587 break; 588 usleep_range(1, 3); 589 } 590 } 591 } 592 593 /* RED and drop levels of CQ on packet reception. 594 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 595 */ 596 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 597 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 598 599 /* RED and drop levels of AURA for packet reception. 600 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 601 * Eg: For RQ length 1K, for pass/drop level 204/230. 602 * RED accepts pkts if free pointers > 102 & <= 205. 603 * Drops pkts if free pointers < 102. 604 */ 605 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 606 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 607 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 608 609 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 610 #define SEND_CQ_SKID 2000 611 612 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 613 { 614 struct otx2_qset *qset = &pfvf->qset; 615 struct nix_aq_enq_req *aq; 616 617 /* Get memory to put this msg */ 618 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 619 if (!aq) 620 return -ENOMEM; 621 622 aq->rq.cq = qidx; 623 aq->rq.ena = 1; 624 aq->rq.pb_caching = 1; 625 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 626 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 627 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 628 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 629 aq->rq.qint_idx = 0; 630 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 631 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 632 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 633 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 634 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 635 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 636 637 /* Fill AQ info */ 638 aq->qidx = qidx; 639 aq->ctype = NIX_AQ_CTYPE_RQ; 640 aq->op = NIX_AQ_INSTOP_INIT; 641 642 return otx2_sync_mbox_msg(&pfvf->mbox); 643 } 644 645 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 646 { 647 struct otx2_qset *qset = &pfvf->qset; 648 struct otx2_snd_queue *sq; 649 struct nix_aq_enq_req *aq; 650 struct otx2_pool *pool; 651 int err; 652 653 pool = &pfvf->qset.pool[sqb_aura]; 654 sq = &qset->sq[qidx]; 655 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 656 sq->sqe_cnt = qset->sqe_cnt; 657 658 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 659 if (err) 660 return err; 661 662 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 663 TSO_HEADER_SIZE); 664 if (err) 665 return err; 666 667 sq->sqe_base = sq->sqe->base; 668 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 669 if (!sq->sg) 670 return -ENOMEM; 671 672 sq->head = 0; 673 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 674 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 675 /* Set SQE threshold to 10% of total SQEs */ 676 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 677 sq->aura_id = sqb_aura; 678 sq->aura_fc_addr = pool->fc_addr->base; 679 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 680 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 681 682 sq->stats.bytes = 0; 683 sq->stats.pkts = 0; 684 685 /* Get memory to put this msg */ 686 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 687 if (!aq) 688 return -ENOMEM; 689 690 aq->sq.cq = pfvf->hw.rx_queues + qidx; 691 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 692 aq->sq.cq_ena = 1; 693 aq->sq.ena = 1; 694 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 695 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 696 aq->sq.smq_rr_quantum = DFLT_RR_QTM; 697 aq->sq.default_chan = pfvf->hw.tx_chan_base; 698 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 699 aq->sq.sqb_aura = sqb_aura; 700 aq->sq.sq_int_ena = NIX_SQINT_BITS; 701 aq->sq.qint_idx = 0; 702 /* Due pipelining impact minimum 2000 unused SQ CQE's 703 * need to maintain to avoid CQ overflow. 704 */ 705 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (sq->sqe_cnt)); 706 707 /* Fill AQ info */ 708 aq->qidx = qidx; 709 aq->ctype = NIX_AQ_CTYPE_SQ; 710 aq->op = NIX_AQ_INSTOP_INIT; 711 712 return otx2_sync_mbox_msg(&pfvf->mbox); 713 } 714 715 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 716 { 717 struct otx2_qset *qset = &pfvf->qset; 718 struct nix_aq_enq_req *aq; 719 struct otx2_cq_queue *cq; 720 int err, pool_id; 721 722 cq = &qset->cq[qidx]; 723 cq->cq_idx = qidx; 724 if (qidx < pfvf->hw.rx_queues) { 725 cq->cq_type = CQ_RX; 726 cq->cint_idx = qidx; 727 cq->cqe_cnt = qset->rqe_cnt; 728 } else { 729 cq->cq_type = CQ_TX; 730 cq->cint_idx = qidx - pfvf->hw.rx_queues; 731 cq->cqe_cnt = qset->sqe_cnt; 732 } 733 cq->cqe_size = pfvf->qset.xqe_size; 734 735 /* Allocate memory for CQEs */ 736 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 737 if (err) 738 return err; 739 740 /* Save CQE CPU base for faster reference */ 741 cq->cqe_base = cq->cqe->base; 742 /* In case where all RQs auras point to single pool, 743 * all CQs receive buffer pool also point to same pool. 744 */ 745 pool_id = ((cq->cq_type == CQ_RX) && 746 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 747 cq->rbpool = &qset->pool[pool_id]; 748 cq->refill_task_sched = false; 749 750 /* Get memory to put this msg */ 751 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 752 if (!aq) 753 return -ENOMEM; 754 755 aq->cq.ena = 1; 756 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 757 aq->cq.caching = 1; 758 aq->cq.base = cq->cqe->iova; 759 aq->cq.cint_idx = cq->cint_idx; 760 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 761 aq->cq.qint_idx = 0; 762 aq->cq.avg_level = 255; 763 764 if (qidx < pfvf->hw.rx_queues) { 765 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 766 aq->cq.drop_ena = 1; 767 768 /* Enable receive CQ backpressure */ 769 aq->cq.bp_ena = 1; 770 aq->cq.bpid = pfvf->bpid[0]; 771 772 /* Set backpressure level is same as cq pass level */ 773 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 774 } 775 776 /* Fill AQ info */ 777 aq->qidx = qidx; 778 aq->ctype = NIX_AQ_CTYPE_CQ; 779 aq->op = NIX_AQ_INSTOP_INIT; 780 781 return otx2_sync_mbox_msg(&pfvf->mbox); 782 } 783 784 static void otx2_pool_refill_task(struct work_struct *work) 785 { 786 struct otx2_cq_queue *cq; 787 struct otx2_pool *rbpool; 788 struct refill_work *wrk; 789 int qidx, free_ptrs = 0; 790 struct otx2_nic *pfvf; 791 s64 bufptr; 792 793 wrk = container_of(work, struct refill_work, pool_refill_work.work); 794 pfvf = wrk->pf; 795 qidx = wrk - pfvf->refill_wrk; 796 cq = &pfvf->qset.cq[qidx]; 797 rbpool = cq->rbpool; 798 free_ptrs = cq->pool_ptrs; 799 800 while (cq->pool_ptrs) { 801 bufptr = otx2_alloc_rbuf(pfvf, rbpool, GFP_KERNEL); 802 if (bufptr <= 0) { 803 /* Schedule a WQ if we fails to free atleast half of the 804 * pointers else enable napi for this RQ. 805 */ 806 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 807 struct delayed_work *dwork; 808 809 dwork = &wrk->pool_refill_work; 810 schedule_delayed_work(dwork, 811 msecs_to_jiffies(100)); 812 } else { 813 cq->refill_task_sched = false; 814 } 815 return; 816 } 817 otx2_aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 818 cq->pool_ptrs--; 819 } 820 cq->refill_task_sched = false; 821 } 822 823 int otx2_config_nix_queues(struct otx2_nic *pfvf) 824 { 825 int qidx, err; 826 827 /* Initialize RX queues */ 828 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 829 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 830 831 err = otx2_rq_init(pfvf, qidx, lpb_aura); 832 if (err) 833 return err; 834 } 835 836 /* Initialize TX queues */ 837 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 838 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 839 840 err = otx2_sq_init(pfvf, qidx, sqb_aura); 841 if (err) 842 return err; 843 } 844 845 /* Initialize completion queues */ 846 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 847 err = otx2_cq_init(pfvf, qidx); 848 if (err) 849 return err; 850 } 851 852 /* Initialize work queue for receive buffer refill */ 853 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 854 sizeof(struct refill_work), GFP_KERNEL); 855 if (!pfvf->refill_wrk) 856 return -ENOMEM; 857 858 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 859 pfvf->refill_wrk[qidx].pf = pfvf; 860 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 861 otx2_pool_refill_task); 862 } 863 return 0; 864 } 865 866 int otx2_config_nix(struct otx2_nic *pfvf) 867 { 868 struct nix_lf_alloc_req *nixlf; 869 struct nix_lf_alloc_rsp *rsp; 870 int err; 871 872 pfvf->qset.xqe_size = NIX_XQESZ_W16 ? 128 : 512; 873 874 /* Get memory to put this msg */ 875 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 876 if (!nixlf) 877 return -ENOMEM; 878 879 /* Set RQ/SQ/CQ counts */ 880 nixlf->rq_cnt = pfvf->hw.rx_queues; 881 nixlf->sq_cnt = pfvf->hw.tx_queues; 882 nixlf->cq_cnt = pfvf->qset.cq_cnt; 883 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 884 nixlf->rss_grps = 1; /* Single RSS indir table supported, for now */ 885 nixlf->xqe_sz = NIX_XQESZ_W16; 886 /* We don't know absolute NPA LF idx attached. 887 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 888 * NPA LF attached to this RVU PF/VF. 889 */ 890 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 891 /* Disable alignment pad, enable L2 length check, 892 * enable L4 TCP/UDP checksum verification. 893 */ 894 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 895 896 err = otx2_sync_mbox_msg(&pfvf->mbox); 897 if (err) 898 return err; 899 900 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 901 &nixlf->hdr); 902 if (IS_ERR(rsp)) 903 return PTR_ERR(rsp); 904 905 if (rsp->qints < 1) 906 return -ENXIO; 907 908 return rsp->hdr.rc; 909 } 910 911 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 912 { 913 struct otx2_qset *qset = &pfvf->qset; 914 struct otx2_hw *hw = &pfvf->hw; 915 struct otx2_snd_queue *sq; 916 int sqb, qidx; 917 u64 iova, pa; 918 919 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 920 sq = &qset->sq[qidx]; 921 if (!sq->sqb_ptrs) 922 continue; 923 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 924 if (!sq->sqb_ptrs[sqb]) 925 continue; 926 iova = sq->sqb_ptrs[sqb]; 927 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 928 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 929 DMA_FROM_DEVICE, 930 DMA_ATTR_SKIP_CPU_SYNC); 931 put_page(virt_to_page(phys_to_virt(pa))); 932 } 933 sq->sqb_count = 0; 934 } 935 } 936 937 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 938 { 939 int pool_id, pool_start = 0, pool_end = 0, size = 0; 940 u64 iova, pa; 941 942 if (type == AURA_NIX_SQ) { 943 pool_start = otx2_get_pool_idx(pfvf, type, 0); 944 pool_end = pool_start + pfvf->hw.sqpool_cnt; 945 size = pfvf->hw.sqb_size; 946 } 947 if (type == AURA_NIX_RQ) { 948 pool_start = otx2_get_pool_idx(pfvf, type, 0); 949 pool_end = pfvf->hw.rqpool_cnt; 950 size = pfvf->rbsize; 951 } 952 953 /* Free SQB and RQB pointers from the aura pool */ 954 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 955 iova = otx2_aura_allocptr(pfvf, pool_id); 956 while (iova) { 957 if (type == AURA_NIX_RQ) 958 iova -= OTX2_HEAD_ROOM; 959 960 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 961 dma_unmap_page_attrs(pfvf->dev, iova, size, 962 DMA_FROM_DEVICE, 963 DMA_ATTR_SKIP_CPU_SYNC); 964 put_page(virt_to_page(phys_to_virt(pa))); 965 iova = otx2_aura_allocptr(pfvf, pool_id); 966 } 967 } 968 } 969 970 void otx2_aura_pool_free(struct otx2_nic *pfvf) 971 { 972 struct otx2_pool *pool; 973 int pool_id; 974 975 if (!pfvf->qset.pool) 976 return; 977 978 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 979 pool = &pfvf->qset.pool[pool_id]; 980 qmem_free(pfvf->dev, pool->stack); 981 qmem_free(pfvf->dev, pool->fc_addr); 982 } 983 devm_kfree(pfvf->dev, pfvf->qset.pool); 984 } 985 986 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 987 int pool_id, int numptrs) 988 { 989 struct npa_aq_enq_req *aq; 990 struct otx2_pool *pool; 991 int err; 992 993 pool = &pfvf->qset.pool[pool_id]; 994 995 /* Allocate memory for HW to update Aura count. 996 * Alloc one cache line, so that it fits all FC_STYPE modes. 997 */ 998 if (!pool->fc_addr) { 999 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1000 if (err) 1001 return err; 1002 } 1003 1004 /* Initialize this aura's context via AF */ 1005 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1006 if (!aq) { 1007 /* Shared mbox memory buffer is full, flush it and retry */ 1008 err = otx2_sync_mbox_msg(&pfvf->mbox); 1009 if (err) 1010 return err; 1011 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1012 if (!aq) 1013 return -ENOMEM; 1014 } 1015 1016 aq->aura_id = aura_id; 1017 /* Will be filled by AF with correct pool context address */ 1018 aq->aura.pool_addr = pool_id; 1019 aq->aura.pool_caching = 1; 1020 aq->aura.shift = ilog2(numptrs) - 8; 1021 aq->aura.count = numptrs; 1022 aq->aura.limit = numptrs; 1023 aq->aura.avg_level = 255; 1024 aq->aura.ena = 1; 1025 aq->aura.fc_ena = 1; 1026 aq->aura.fc_addr = pool->fc_addr->iova; 1027 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1028 1029 /* Enable backpressure for RQ aura */ 1030 if (aura_id < pfvf->hw.rqpool_cnt) { 1031 aq->aura.bp_ena = 0; 1032 aq->aura.nix0_bpid = pfvf->bpid[0]; 1033 /* Set backpressure level for RQ's Aura */ 1034 aq->aura.bp = RQ_BP_LVL_AURA; 1035 } 1036 1037 /* Fill AQ info */ 1038 aq->ctype = NPA_AQ_CTYPE_AURA; 1039 aq->op = NPA_AQ_INSTOP_INIT; 1040 1041 return 0; 1042 } 1043 1044 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1045 int stack_pages, int numptrs, int buf_size) 1046 { 1047 struct npa_aq_enq_req *aq; 1048 struct otx2_pool *pool; 1049 int err; 1050 1051 pool = &pfvf->qset.pool[pool_id]; 1052 /* Alloc memory for stack which is used to store buffer pointers */ 1053 err = qmem_alloc(pfvf->dev, &pool->stack, 1054 stack_pages, pfvf->hw.stack_pg_bytes); 1055 if (err) 1056 return err; 1057 1058 pool->rbsize = buf_size; 1059 pool->rbpage_order = get_order(buf_size); 1060 1061 /* Initialize this pool's context via AF */ 1062 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1063 if (!aq) { 1064 /* Shared mbox memory buffer is full, flush it and retry */ 1065 err = otx2_sync_mbox_msg(&pfvf->mbox); 1066 if (err) { 1067 qmem_free(pfvf->dev, pool->stack); 1068 return err; 1069 } 1070 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1071 if (!aq) { 1072 qmem_free(pfvf->dev, pool->stack); 1073 return -ENOMEM; 1074 } 1075 } 1076 1077 aq->aura_id = pool_id; 1078 aq->pool.stack_base = pool->stack->iova; 1079 aq->pool.stack_caching = 1; 1080 aq->pool.ena = 1; 1081 aq->pool.buf_size = buf_size / 128; 1082 aq->pool.stack_max_pages = stack_pages; 1083 aq->pool.shift = ilog2(numptrs) - 8; 1084 aq->pool.ptr_start = 0; 1085 aq->pool.ptr_end = ~0ULL; 1086 1087 /* Fill AQ info */ 1088 aq->ctype = NPA_AQ_CTYPE_POOL; 1089 aq->op = NPA_AQ_INSTOP_INIT; 1090 1091 return 0; 1092 } 1093 1094 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1095 { 1096 int qidx, pool_id, stack_pages, num_sqbs; 1097 struct otx2_qset *qset = &pfvf->qset; 1098 struct otx2_hw *hw = &pfvf->hw; 1099 struct otx2_snd_queue *sq; 1100 struct otx2_pool *pool; 1101 int err, ptr; 1102 s64 bufptr; 1103 1104 /* Calculate number of SQBs needed. 1105 * 1106 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1107 * Last SQE is used for pointing to next SQB. 1108 */ 1109 num_sqbs = (hw->sqb_size / 128) - 1; 1110 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1111 1112 /* Get no of stack pages needed */ 1113 stack_pages = 1114 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1115 1116 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1117 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1118 /* Initialize aura context */ 1119 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1120 if (err) 1121 goto fail; 1122 1123 /* Initialize pool context */ 1124 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1125 num_sqbs, hw->sqb_size); 1126 if (err) 1127 goto fail; 1128 } 1129 1130 /* Flush accumulated messages */ 1131 err = otx2_sync_mbox_msg(&pfvf->mbox); 1132 if (err) 1133 goto fail; 1134 1135 /* Allocate pointers and free them to aura/pool */ 1136 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1137 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1138 pool = &pfvf->qset.pool[pool_id]; 1139 1140 sq = &qset->sq[qidx]; 1141 sq->sqb_count = 0; 1142 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(u64 *), GFP_KERNEL); 1143 if (!sq->sqb_ptrs) 1144 return -ENOMEM; 1145 1146 for (ptr = 0; ptr < num_sqbs; ptr++) { 1147 bufptr = otx2_alloc_rbuf(pfvf, pool, GFP_KERNEL); 1148 if (bufptr <= 0) 1149 return bufptr; 1150 otx2_aura_freeptr(pfvf, pool_id, bufptr); 1151 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1152 } 1153 otx2_get_page(pool); 1154 } 1155 1156 return 0; 1157 fail: 1158 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1159 otx2_aura_pool_free(pfvf); 1160 return err; 1161 } 1162 1163 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1164 { 1165 struct otx2_hw *hw = &pfvf->hw; 1166 int stack_pages, pool_id, rq; 1167 struct otx2_pool *pool; 1168 int err, ptr, num_ptrs; 1169 s64 bufptr; 1170 1171 num_ptrs = pfvf->qset.rqe_cnt; 1172 1173 stack_pages = 1174 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1175 1176 for (rq = 0; rq < hw->rx_queues; rq++) { 1177 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1178 /* Initialize aura context */ 1179 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1180 if (err) 1181 goto fail; 1182 } 1183 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1184 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1185 num_ptrs, pfvf->rbsize); 1186 if (err) 1187 goto fail; 1188 } 1189 1190 /* Flush accumulated messages */ 1191 err = otx2_sync_mbox_msg(&pfvf->mbox); 1192 if (err) 1193 goto fail; 1194 1195 /* Allocate pointers and free them to aura/pool */ 1196 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1197 pool = &pfvf->qset.pool[pool_id]; 1198 for (ptr = 0; ptr < num_ptrs; ptr++) { 1199 bufptr = otx2_alloc_rbuf(pfvf, pool, GFP_KERNEL); 1200 if (bufptr <= 0) 1201 return bufptr; 1202 otx2_aura_freeptr(pfvf, pool_id, 1203 bufptr + OTX2_HEAD_ROOM); 1204 } 1205 otx2_get_page(pool); 1206 } 1207 1208 return 0; 1209 fail: 1210 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1211 otx2_aura_pool_free(pfvf); 1212 return err; 1213 } 1214 1215 int otx2_config_npa(struct otx2_nic *pfvf) 1216 { 1217 struct otx2_qset *qset = &pfvf->qset; 1218 struct npa_lf_alloc_req *npalf; 1219 struct otx2_hw *hw = &pfvf->hw; 1220 int aura_cnt; 1221 1222 /* Pool - Stack of free buffer pointers 1223 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1224 */ 1225 1226 if (!hw->pool_cnt) 1227 return -EINVAL; 1228 1229 qset->pool = devm_kzalloc(pfvf->dev, sizeof(struct otx2_pool) * 1230 hw->pool_cnt, GFP_KERNEL); 1231 if (!qset->pool) 1232 return -ENOMEM; 1233 1234 /* Get memory to put this msg */ 1235 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1236 if (!npalf) 1237 return -ENOMEM; 1238 1239 /* Set aura and pool counts */ 1240 npalf->nr_pools = hw->pool_cnt; 1241 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1242 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1243 1244 return otx2_sync_mbox_msg(&pfvf->mbox); 1245 } 1246 1247 int otx2_detach_resources(struct mbox *mbox) 1248 { 1249 struct rsrc_detach *detach; 1250 1251 otx2_mbox_lock(mbox); 1252 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1253 if (!detach) { 1254 otx2_mbox_unlock(mbox); 1255 return -ENOMEM; 1256 } 1257 1258 /* detach all */ 1259 detach->partial = false; 1260 1261 /* Send detach request to AF */ 1262 otx2_mbox_msg_send(&mbox->mbox, 0); 1263 otx2_mbox_unlock(mbox); 1264 return 0; 1265 } 1266 1267 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1268 { 1269 struct rsrc_attach *attach; 1270 struct msg_req *msix; 1271 int err; 1272 1273 otx2_mbox_lock(&pfvf->mbox); 1274 /* Get memory to put this msg */ 1275 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1276 if (!attach) { 1277 otx2_mbox_unlock(&pfvf->mbox); 1278 return -ENOMEM; 1279 } 1280 1281 attach->npalf = true; 1282 attach->nixlf = true; 1283 1284 /* Send attach request to AF */ 1285 err = otx2_sync_mbox_msg(&pfvf->mbox); 1286 if (err) { 1287 otx2_mbox_unlock(&pfvf->mbox); 1288 return err; 1289 } 1290 1291 pfvf->nix_blkaddr = BLKADDR_NIX0; 1292 1293 /* If the platform has two NIX blocks then LF may be 1294 * allocated from NIX1. 1295 */ 1296 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1297 pfvf->nix_blkaddr = BLKADDR_NIX1; 1298 1299 /* Get NPA and NIX MSIX vector offsets */ 1300 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1301 if (!msix) { 1302 otx2_mbox_unlock(&pfvf->mbox); 1303 return -ENOMEM; 1304 } 1305 1306 err = otx2_sync_mbox_msg(&pfvf->mbox); 1307 if (err) { 1308 otx2_mbox_unlock(&pfvf->mbox); 1309 return err; 1310 } 1311 otx2_mbox_unlock(&pfvf->mbox); 1312 1313 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1314 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1315 dev_err(pfvf->dev, 1316 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1317 return -EINVAL; 1318 } 1319 1320 return 0; 1321 } 1322 1323 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1324 { 1325 struct hwctx_disable_req *req; 1326 1327 otx2_mbox_lock(mbox); 1328 /* Request AQ to disable this context */ 1329 if (npa) 1330 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1331 else 1332 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1333 1334 if (!req) { 1335 otx2_mbox_unlock(mbox); 1336 return; 1337 } 1338 1339 req->ctype = type; 1340 1341 if (otx2_sync_mbox_msg(mbox)) 1342 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1343 __func__); 1344 1345 otx2_mbox_unlock(mbox); 1346 } 1347 1348 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1349 { 1350 struct nix_bp_cfg_req *req; 1351 1352 if (enable) 1353 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1354 else 1355 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1356 1357 if (!req) 1358 return -ENOMEM; 1359 1360 req->chan_base = 0; 1361 req->chan_cnt = 1; 1362 req->bpid_per_chan = 0; 1363 1364 return otx2_sync_mbox_msg(&pfvf->mbox); 1365 } 1366 1367 /* Mbox message handlers */ 1368 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1369 struct cgx_stats_rsp *rsp) 1370 { 1371 int id; 1372 1373 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1374 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1375 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1376 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1377 } 1378 1379 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1380 struct nix_txsch_alloc_rsp *rsp) 1381 { 1382 int lvl, schq; 1383 1384 /* Setup transmit scheduler list */ 1385 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 1386 for (schq = 0; schq < rsp->schq[lvl]; schq++) 1387 pf->hw.txschq_list[lvl][schq] = 1388 rsp->schq_list[lvl][schq]; 1389 } 1390 1391 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1392 struct npa_lf_alloc_rsp *rsp) 1393 { 1394 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1395 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1396 } 1397 1398 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1399 struct nix_lf_alloc_rsp *rsp) 1400 { 1401 pfvf->hw.sqb_size = rsp->sqb_size; 1402 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1403 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1404 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1405 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1406 } 1407 1408 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1409 struct msix_offset_rsp *rsp) 1410 { 1411 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1412 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1413 } 1414 1415 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1416 struct nix_bp_cfg_rsp *rsp) 1417 { 1418 int chan, chan_id; 1419 1420 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1421 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1422 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1423 } 1424 } 1425 1426 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1427 { 1428 struct otx2_qset *qset = &pfvf->qset; 1429 struct otx2_hw *hw = &pfvf->hw; 1430 int irq, qidx; 1431 1432 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1433 qidx < n; 1434 qidx++, irq++) { 1435 int vector = pci_irq_vector(pfvf->pdev, irq); 1436 1437 irq_set_affinity_hint(vector, NULL); 1438 free_cpumask_var(hw->affinity_mask[irq]); 1439 free_irq(vector, &qset->napi[qidx]); 1440 } 1441 } 1442 1443 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1444 { 1445 struct otx2_hw *hw = &pfvf->hw; 1446 int vec, cpu, irq, cint; 1447 1448 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1449 cpu = cpumask_first(cpu_online_mask); 1450 1451 /* CQ interrupts */ 1452 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1453 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1454 return; 1455 1456 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1457 1458 irq = pci_irq_vector(pfvf->pdev, vec); 1459 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1460 1461 cpu = cpumask_next(cpu, cpu_online_mask); 1462 if (unlikely(cpu >= nr_cpu_ids)) 1463 cpu = 0; 1464 } 1465 } 1466 1467 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1468 int __weak \ 1469 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1470 struct _req_type *req, \ 1471 struct _rsp_type *rsp) \ 1472 { \ 1473 /* Nothing to do here */ \ 1474 return 0; \ 1475 } \ 1476 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1477 MBOX_UP_CGX_MESSAGES 1478 #undef M 1479