1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 #include <net/page_pool/helpers.h> 11 #include <net/tso.h> 12 #include <linux/bitfield.h> 13 #include <linux/dcbnl.h> 14 #include <net/xfrm.h> 15 16 #include "otx2_reg.h" 17 #include "otx2_common.h" 18 #include "otx2_struct.h" 19 #include "cn10k.h" 20 21 static bool otx2_is_pfc_enabled(struct otx2_nic *pfvf) 22 { 23 return IS_ENABLED(CONFIG_DCB) && !!pfvf->pfc_en; 24 } 25 26 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 27 struct otx2_nic *pfvf, int qidx) 28 { 29 u64 incr = (u64)qidx << 32; 30 u64 *ptr; 31 32 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 33 stats->bytes = otx2_atomic64_add(incr, ptr); 34 35 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 36 stats->pkts = otx2_atomic64_add(incr, ptr); 37 } 38 39 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 40 struct otx2_nic *pfvf, int qidx) 41 { 42 u64 incr = (u64)qidx << 32; 43 u64 *ptr; 44 45 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 46 stats->bytes = otx2_atomic64_add(incr, ptr); 47 48 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 49 stats->pkts = otx2_atomic64_add(incr, ptr); 50 } 51 52 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 53 { 54 struct msg_req *req; 55 56 if (!netif_running(pfvf->netdev)) 57 return; 58 59 mutex_lock(&pfvf->mbox.lock); 60 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 61 if (!req) { 62 mutex_unlock(&pfvf->mbox.lock); 63 return; 64 } 65 66 otx2_sync_mbox_msg(&pfvf->mbox); 67 mutex_unlock(&pfvf->mbox.lock); 68 } 69 70 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 71 { 72 struct msg_req *req; 73 74 if (!netif_running(pfvf->netdev)) 75 return; 76 mutex_lock(&pfvf->mbox.lock); 77 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 78 if (req) 79 otx2_sync_mbox_msg(&pfvf->mbox); 80 mutex_unlock(&pfvf->mbox.lock); 81 } 82 83 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 84 { 85 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 86 87 if (!pfvf->qset.rq) 88 return 0; 89 90 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 91 return 1; 92 } 93 EXPORT_SYMBOL(otx2_update_rq_stats); 94 95 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 96 { 97 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 98 99 if (!pfvf->qset.sq) 100 return 0; 101 102 if (qidx >= pfvf->hw.non_qos_queues) { 103 if (!test_bit(qidx - pfvf->hw.non_qos_queues, pfvf->qos.qos_sq_bmap)) 104 return 0; 105 } 106 107 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 108 return 1; 109 } 110 EXPORT_SYMBOL(otx2_update_sq_stats); 111 112 void otx2_get_dev_stats(struct otx2_nic *pfvf) 113 { 114 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 115 116 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 117 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 118 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 119 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 120 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 121 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 122 dev_stats->rx_mcast_frames + 123 dev_stats->rx_ucast_frames; 124 125 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 126 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 127 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 128 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 129 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 130 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 131 dev_stats->tx_mcast_frames + 132 dev_stats->tx_ucast_frames; 133 } 134 135 void otx2_get_stats64(struct net_device *netdev, 136 struct rtnl_link_stats64 *stats) 137 { 138 struct otx2_nic *pfvf = netdev_priv(netdev); 139 struct otx2_dev_stats *dev_stats; 140 141 otx2_get_dev_stats(pfvf); 142 143 dev_stats = &pfvf->hw.dev_stats; 144 stats->rx_bytes = dev_stats->rx_bytes; 145 stats->rx_packets = dev_stats->rx_frames; 146 stats->rx_dropped = dev_stats->rx_drops; 147 stats->multicast = dev_stats->rx_mcast_frames; 148 149 stats->tx_bytes = dev_stats->tx_bytes; 150 stats->tx_packets = dev_stats->tx_frames; 151 stats->tx_dropped = dev_stats->tx_drops; 152 } 153 EXPORT_SYMBOL(otx2_get_stats64); 154 155 /* Sync MAC address with RVU AF */ 156 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 157 { 158 struct nix_set_mac_addr *req; 159 int err; 160 161 mutex_lock(&pfvf->mbox.lock); 162 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 163 if (!req) { 164 mutex_unlock(&pfvf->mbox.lock); 165 return -ENOMEM; 166 } 167 168 ether_addr_copy(req->mac_addr, mac); 169 170 err = otx2_sync_mbox_msg(&pfvf->mbox); 171 mutex_unlock(&pfvf->mbox.lock); 172 return err; 173 } 174 175 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 176 struct net_device *netdev) 177 { 178 struct nix_get_mac_addr_rsp *rsp; 179 struct mbox_msghdr *msghdr; 180 struct msg_req *req; 181 int err; 182 183 mutex_lock(&pfvf->mbox.lock); 184 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 185 if (!req) { 186 mutex_unlock(&pfvf->mbox.lock); 187 return -ENOMEM; 188 } 189 190 err = otx2_sync_mbox_msg(&pfvf->mbox); 191 if (err) { 192 mutex_unlock(&pfvf->mbox.lock); 193 return err; 194 } 195 196 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 197 if (IS_ERR(msghdr)) { 198 mutex_unlock(&pfvf->mbox.lock); 199 return PTR_ERR(msghdr); 200 } 201 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 202 eth_hw_addr_set(netdev, rsp->mac_addr); 203 mutex_unlock(&pfvf->mbox.lock); 204 205 return 0; 206 } 207 208 int otx2_set_mac_address(struct net_device *netdev, void *p) 209 { 210 struct otx2_nic *pfvf = netdev_priv(netdev); 211 struct sockaddr *addr = p; 212 213 if (!is_valid_ether_addr(addr->sa_data)) 214 return -EADDRNOTAVAIL; 215 216 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 217 eth_hw_addr_set(netdev, addr->sa_data); 218 /* update dmac field in vlan offload rule */ 219 if (netif_running(netdev) && 220 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 221 otx2_install_rxvlan_offload_flow(pfvf); 222 /* update dmac address in ntuple and DMAC filter list */ 223 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 224 otx2_dmacflt_update_pfmac_flow(pfvf); 225 } else { 226 return -EPERM; 227 } 228 229 return 0; 230 } 231 EXPORT_SYMBOL(otx2_set_mac_address); 232 233 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 234 { 235 struct nix_frs_cfg *req; 236 u16 maxlen; 237 int err; 238 239 maxlen = pfvf->hw.max_mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 240 241 mutex_lock(&pfvf->mbox.lock); 242 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 243 if (!req) { 244 mutex_unlock(&pfvf->mbox.lock); 245 return -ENOMEM; 246 } 247 248 req->maxlen = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 249 250 /* Use max receive length supported by hardware for loopback devices */ 251 if (is_otx2_lbkvf(pfvf->pdev)) 252 req->maxlen = maxlen; 253 254 err = otx2_sync_mbox_msg(&pfvf->mbox); 255 mutex_unlock(&pfvf->mbox.lock); 256 return err; 257 } 258 EXPORT_SYMBOL(otx2_hw_set_mtu); 259 260 int otx2_config_pause_frm(struct otx2_nic *pfvf) 261 { 262 struct cgx_pause_frm_cfg *req; 263 int err; 264 265 if (is_otx2_lbkvf(pfvf->pdev) || is_otx2_sdp_rep(pfvf->pdev)) 266 return 0; 267 268 mutex_lock(&pfvf->mbox.lock); 269 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 270 if (!req) { 271 err = -ENOMEM; 272 goto unlock; 273 } 274 275 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 276 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 277 req->set = 1; 278 279 err = otx2_sync_mbox_msg(&pfvf->mbox); 280 unlock: 281 mutex_unlock(&pfvf->mbox.lock); 282 return err; 283 } 284 EXPORT_SYMBOL(otx2_config_pause_frm); 285 286 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 287 { 288 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 289 struct nix_rss_flowkey_cfg_rsp *rsp; 290 struct nix_rss_flowkey_cfg *req; 291 int err; 292 293 mutex_lock(&pfvf->mbox.lock); 294 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 295 if (!req) { 296 mutex_unlock(&pfvf->mbox.lock); 297 return -ENOMEM; 298 } 299 req->mcam_index = -1; /* Default or reserved index */ 300 req->flowkey_cfg = rss->flowkey_cfg; 301 req->group = DEFAULT_RSS_CONTEXT_GROUP; 302 303 err = otx2_sync_mbox_msg(&pfvf->mbox); 304 if (err) 305 goto fail; 306 307 rsp = (struct nix_rss_flowkey_cfg_rsp *) 308 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 309 if (IS_ERR(rsp)) { 310 err = PTR_ERR(rsp); 311 goto fail; 312 } 313 314 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 315 fail: 316 mutex_unlock(&pfvf->mbox.lock); 317 return err; 318 } 319 320 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 321 { 322 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 323 const int index = rss->rss_size * ctx_id; 324 struct mbox *mbox = &pfvf->mbox; 325 struct otx2_rss_ctx *rss_ctx; 326 struct nix_aq_enq_req *aq; 327 int idx, err; 328 329 mutex_lock(&mbox->lock); 330 rss_ctx = rss->rss_ctx[ctx_id]; 331 /* Get memory to put this msg */ 332 for (idx = 0; idx < rss->rss_size; idx++) { 333 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 334 if (!aq) { 335 /* The shared memory buffer can be full. 336 * Flush it and retry 337 */ 338 err = otx2_sync_mbox_msg(mbox); 339 if (err) { 340 mutex_unlock(&mbox->lock); 341 return err; 342 } 343 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 344 if (!aq) { 345 mutex_unlock(&mbox->lock); 346 return -ENOMEM; 347 } 348 } 349 350 aq->rss.rq = rss_ctx->ind_tbl[idx]; 351 352 /* Fill AQ info */ 353 aq->qidx = index + idx; 354 aq->ctype = NIX_AQ_CTYPE_RSS; 355 aq->op = NIX_AQ_INSTOP_INIT; 356 } 357 err = otx2_sync_mbox_msg(mbox); 358 mutex_unlock(&mbox->lock); 359 return err; 360 } 361 362 void otx2_set_rss_key(struct otx2_nic *pfvf) 363 { 364 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 365 u64 *key = (u64 *)&rss->key[4]; 366 int idx; 367 368 /* 352bit or 44byte key needs to be configured as below 369 * NIX_LF_RX_SECRETX0 = key<351:288> 370 * NIX_LF_RX_SECRETX1 = key<287:224> 371 * NIX_LF_RX_SECRETX2 = key<223:160> 372 * NIX_LF_RX_SECRETX3 = key<159:96> 373 * NIX_LF_RX_SECRETX4 = key<95:32> 374 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 375 */ 376 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 377 (u64)(*((u32 *)&rss->key)) << 32); 378 idx = sizeof(rss->key) / sizeof(u64); 379 while (idx > 0) { 380 idx--; 381 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 382 } 383 } 384 385 int otx2_rss_init(struct otx2_nic *pfvf) 386 { 387 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 388 struct otx2_rss_ctx *rss_ctx; 389 int idx, ret = 0; 390 391 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 392 393 /* Init RSS key if it is not setup already */ 394 if (!rss->enable) 395 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 396 otx2_set_rss_key(pfvf); 397 398 if (!netif_is_rxfh_configured(pfvf->netdev)) { 399 /* Set RSS group 0 as default indirection table */ 400 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 401 GFP_KERNEL); 402 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 403 return -ENOMEM; 404 405 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 406 for (idx = 0; idx < rss->rss_size; idx++) 407 rss_ctx->ind_tbl[idx] = 408 ethtool_rxfh_indir_default(idx, 409 pfvf->hw.rx_queues); 410 } 411 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 412 if (ret) 413 return ret; 414 415 /* Flowkey or hash config to be used for generating flow tag */ 416 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 417 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 418 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 419 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 420 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 421 422 ret = otx2_set_flowkey_cfg(pfvf); 423 if (ret) 424 return ret; 425 426 rss->enable = true; 427 return 0; 428 } 429 430 /* Setup UDP segmentation algorithm in HW */ 431 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 432 { 433 struct nix_lso_format *field; 434 435 field = (struct nix_lso_format *)&lso->fields[0]; 436 lso->field_mask = GENMASK(18, 0); 437 438 /* IP's Length field */ 439 field->layer = NIX_TXLAYER_OL3; 440 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 441 field->offset = v4 ? 2 : 4; 442 field->sizem1 = 1; /* i.e 2 bytes */ 443 field->alg = NIX_LSOALG_ADD_PAYLEN; 444 field++; 445 446 /* No ID field in IPv6 header */ 447 if (v4) { 448 /* Increment IPID */ 449 field->layer = NIX_TXLAYER_OL3; 450 field->offset = 4; 451 field->sizem1 = 1; /* i.e 2 bytes */ 452 field->alg = NIX_LSOALG_ADD_SEGNUM; 453 field++; 454 } 455 456 /* Update length in UDP header */ 457 field->layer = NIX_TXLAYER_OL4; 458 field->offset = 4; 459 field->sizem1 = 1; 460 field->alg = NIX_LSOALG_ADD_PAYLEN; 461 } 462 463 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 464 void otx2_setup_segmentation(struct otx2_nic *pfvf) 465 { 466 struct nix_lso_format_cfg_rsp *rsp; 467 struct nix_lso_format_cfg *lso; 468 struct otx2_hw *hw = &pfvf->hw; 469 int err; 470 471 mutex_lock(&pfvf->mbox.lock); 472 473 /* UDPv4 segmentation */ 474 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 475 if (!lso) 476 goto fail; 477 478 /* Setup UDP/IP header fields that HW should update per segment */ 479 otx2_setup_udp_segmentation(lso, true); 480 481 err = otx2_sync_mbox_msg(&pfvf->mbox); 482 if (err) 483 goto fail; 484 485 rsp = (struct nix_lso_format_cfg_rsp *) 486 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 487 if (IS_ERR(rsp)) 488 goto fail; 489 490 hw->lso_udpv4_idx = rsp->lso_format_idx; 491 492 /* UDPv6 segmentation */ 493 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 494 if (!lso) 495 goto fail; 496 497 /* Setup UDP/IP header fields that HW should update per segment */ 498 otx2_setup_udp_segmentation(lso, false); 499 500 err = otx2_sync_mbox_msg(&pfvf->mbox); 501 if (err) 502 goto fail; 503 504 rsp = (struct nix_lso_format_cfg_rsp *) 505 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 506 if (IS_ERR(rsp)) 507 goto fail; 508 509 hw->lso_udpv6_idx = rsp->lso_format_idx; 510 mutex_unlock(&pfvf->mbox.lock); 511 return; 512 fail: 513 mutex_unlock(&pfvf->mbox.lock); 514 netdev_info(pfvf->netdev, 515 "Failed to get LSO index for UDP GSO offload, disabling\n"); 516 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 517 } 518 519 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 520 { 521 /* Configure CQE interrupt coalescing parameters 522 * 523 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 524 * set 1 less than cq_ecount_wait. And cq_time_wait is in 525 * usecs, convert that to 100ns count. 526 */ 527 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 528 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 529 ((u64)pfvf->hw.cq_qcount_wait << 32) | 530 (pfvf->hw.cq_ecount_wait - 1)); 531 } 532 533 static int otx2_alloc_pool_buf(struct otx2_nic *pfvf, struct otx2_pool *pool, 534 dma_addr_t *dma) 535 { 536 unsigned int offset = 0; 537 struct page *page; 538 size_t sz; 539 540 sz = SKB_DATA_ALIGN(pool->rbsize); 541 sz = ALIGN(sz, OTX2_ALIGN); 542 543 page = page_pool_alloc_frag(pool->page_pool, &offset, sz, GFP_ATOMIC); 544 if (unlikely(!page)) 545 return -ENOMEM; 546 547 *dma = page_pool_get_dma_addr(page) + offset; 548 return 0; 549 } 550 551 static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 552 dma_addr_t *dma) 553 { 554 u8 *buf; 555 556 if (pool->page_pool) 557 return otx2_alloc_pool_buf(pfvf, pool, dma); 558 559 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 560 if (unlikely(!buf)) 561 return -ENOMEM; 562 563 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 564 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 565 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 566 page_frag_free(buf); 567 return -ENOMEM; 568 } 569 570 return 0; 571 } 572 573 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 574 dma_addr_t *dma) 575 { 576 int ret; 577 578 local_bh_disable(); 579 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 580 local_bh_enable(); 581 return ret; 582 } 583 584 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 585 dma_addr_t *dma) 586 { 587 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) 588 return -ENOMEM; 589 return 0; 590 } 591 592 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 593 { 594 struct otx2_nic *pfvf = netdev_priv(netdev); 595 596 schedule_work(&pfvf->reset_task); 597 } 598 EXPORT_SYMBOL(otx2_tx_timeout); 599 600 void otx2_get_mac_from_af(struct net_device *netdev) 601 { 602 struct otx2_nic *pfvf = netdev_priv(netdev); 603 int err; 604 605 err = otx2_hw_get_mac_addr(pfvf, netdev); 606 if (err) 607 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 608 609 /* If AF doesn't provide a valid MAC, generate a random one */ 610 if (!is_valid_ether_addr(netdev->dev_addr)) 611 eth_hw_addr_random(netdev); 612 } 613 EXPORT_SYMBOL(otx2_get_mac_from_af); 614 615 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc) 616 { 617 u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC]; 618 struct otx2_hw *hw = &pfvf->hw; 619 struct nix_txschq_config *req; 620 u64 schq, parent; 621 u64 dwrr_val; 622 623 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 624 625 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 626 if (!req) 627 return -ENOMEM; 628 629 req->lvl = lvl; 630 req->num_regs = 1; 631 632 schq_list = hw->txschq_list; 633 #ifdef CONFIG_DCB 634 if (txschq_for_pfc) 635 schq_list = pfvf->pfc_schq_list; 636 #endif 637 638 schq = schq_list[lvl][prio]; 639 /* Set topology e.t.c configuration */ 640 if (lvl == NIX_TXSCH_LVL_SMQ) { 641 req->reg[0] = NIX_AF_SMQX_CFG(schq); 642 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU; 643 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 644 (0x2ULL << 36); 645 /* Set link type for DWRR MTU selection on CN10K silicons */ 646 if (!is_dev_otx2(pfvf->pdev)) 647 req->regval[0] |= FIELD_PREP(GENMASK_ULL(58, 57), 648 (u64)hw->smq_link_type); 649 req->num_regs++; 650 /* MDQ config */ 651 parent = schq_list[NIX_TXSCH_LVL_TL4][prio]; 652 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 653 req->regval[1] = parent << 16; 654 req->num_regs++; 655 /* Set DWRR quantum */ 656 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 657 req->regval[2] = dwrr_val; 658 } else if (lvl == NIX_TXSCH_LVL_TL4) { 659 int sdp_chan = hw->tx_chan_base + prio; 660 661 if (is_otx2_sdp_rep(pfvf->pdev)) 662 prio = 0; 663 parent = schq_list[NIX_TXSCH_LVL_TL3][prio]; 664 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 665 req->regval[0] = (u64)parent << 16; 666 req->num_regs++; 667 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 668 req->regval[1] = dwrr_val; 669 if (is_otx2_sdp_rep(pfvf->pdev)) { 670 req->num_regs++; 671 req->reg[2] = NIX_AF_TL4X_SDP_LINK_CFG(schq); 672 req->regval[2] = BIT_ULL(12) | BIT_ULL(13) | 673 (sdp_chan & 0xff); 674 } 675 } else if (lvl == NIX_TXSCH_LVL_TL3) { 676 parent = schq_list[NIX_TXSCH_LVL_TL2][prio]; 677 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 678 req->regval[0] = (u64)parent << 16; 679 req->num_regs++; 680 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 681 req->regval[1] = dwrr_val; 682 if (lvl == hw->txschq_link_cfg_lvl && 683 !is_otx2_sdp_rep(pfvf->pdev)) { 684 req->num_regs++; 685 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 686 /* Enable this queue and backpressure 687 * and set relative channel 688 */ 689 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 690 } 691 } else if (lvl == NIX_TXSCH_LVL_TL2) { 692 parent = schq_list[NIX_TXSCH_LVL_TL1][prio]; 693 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 694 req->regval[0] = (u64)parent << 16; 695 696 req->num_regs++; 697 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 698 req->regval[1] = (u64)hw->txschq_aggr_lvl_rr_prio << 24 | dwrr_val; 699 700 if (lvl == hw->txschq_link_cfg_lvl && 701 !is_otx2_sdp_rep(pfvf->pdev)) { 702 req->num_regs++; 703 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 704 /* Enable this queue and backpressure 705 * and set relative channel 706 */ 707 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 708 } 709 } else if (lvl == NIX_TXSCH_LVL_TL1) { 710 /* Default config for TL1. 711 * For VF this is always ignored. 712 */ 713 714 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 715 * clip it to 16384, so configuring a 24bit max value 716 * will work on both OTx2 and CN10K. 717 */ 718 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 719 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 720 721 req->num_regs++; 722 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 723 req->regval[1] = hw->txschq_aggr_lvl_rr_prio << 1; 724 725 req->num_regs++; 726 req->reg[2] = NIX_AF_TL1X_CIR(schq); 727 req->regval[2] = 0; 728 } 729 730 return otx2_sync_mbox_msg(&pfvf->mbox); 731 } 732 EXPORT_SYMBOL(otx2_txschq_config); 733 734 int otx2_smq_flush(struct otx2_nic *pfvf, int smq) 735 { 736 struct nix_txschq_config *req; 737 int rc; 738 739 mutex_lock(&pfvf->mbox.lock); 740 741 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 742 if (!req) { 743 mutex_unlock(&pfvf->mbox.lock); 744 return -ENOMEM; 745 } 746 747 req->lvl = NIX_TXSCH_LVL_SMQ; 748 req->reg[0] = NIX_AF_SMQX_CFG(smq); 749 req->regval[0] |= BIT_ULL(49); 750 req->num_regs++; 751 752 rc = otx2_sync_mbox_msg(&pfvf->mbox); 753 mutex_unlock(&pfvf->mbox.lock); 754 return rc; 755 } 756 EXPORT_SYMBOL(otx2_smq_flush); 757 758 int otx2_txsch_alloc(struct otx2_nic *pfvf) 759 { 760 int chan_cnt = pfvf->hw.tx_chan_cnt; 761 struct nix_txsch_alloc_req *req; 762 struct nix_txsch_alloc_rsp *rsp; 763 int lvl, schq, rc; 764 765 /* Get memory to put this msg */ 766 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 767 if (!req) 768 return -ENOMEM; 769 770 /* Request one schq per level */ 771 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 772 req->schq[lvl] = 1; 773 774 if (is_otx2_sdp_rep(pfvf->pdev) && chan_cnt > 1) { 775 req->schq[NIX_TXSCH_LVL_SMQ] = chan_cnt; 776 req->schq[NIX_TXSCH_LVL_TL4] = chan_cnt; 777 } 778 779 rc = otx2_sync_mbox_msg(&pfvf->mbox); 780 if (rc) 781 return rc; 782 783 rsp = (struct nix_txsch_alloc_rsp *) 784 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 785 if (IS_ERR(rsp)) 786 return PTR_ERR(rsp); 787 788 /* Setup transmit scheduler list */ 789 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 790 pfvf->hw.txschq_cnt[lvl] = rsp->schq[lvl]; 791 for (schq = 0; schq < rsp->schq[lvl]; schq++) 792 pfvf->hw.txschq_list[lvl][schq] = 793 rsp->schq_list[lvl][schq]; 794 } 795 796 pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl; 797 pfvf->hw.txschq_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio; 798 799 return 0; 800 } 801 802 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq) 803 { 804 struct nix_txsch_free_req *free_req; 805 int err; 806 807 mutex_lock(&pfvf->mbox.lock); 808 809 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 810 if (!free_req) { 811 mutex_unlock(&pfvf->mbox.lock); 812 netdev_err(pfvf->netdev, 813 "Failed alloc txschq free req\n"); 814 return; 815 } 816 817 free_req->schq_lvl = lvl; 818 free_req->schq = schq; 819 820 err = otx2_sync_mbox_msg(&pfvf->mbox); 821 if (err) { 822 netdev_err(pfvf->netdev, 823 "Failed stop txschq %d at level %d\n", schq, lvl); 824 } 825 826 mutex_unlock(&pfvf->mbox.lock); 827 } 828 EXPORT_SYMBOL(otx2_txschq_free_one); 829 830 void otx2_txschq_stop(struct otx2_nic *pfvf) 831 { 832 int lvl, schq, idx; 833 834 /* free non QOS TLx nodes */ 835 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 836 for (idx = 0; idx < pfvf->hw.txschq_cnt[lvl]; idx++) { 837 otx2_txschq_free_one(pfvf, lvl, 838 pfvf->hw.txschq_list[lvl][idx]); 839 } 840 } 841 842 /* Clear the txschq list */ 843 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 844 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 845 pfvf->hw.txschq_list[lvl][schq] = 0; 846 } 847 848 } 849 850 void otx2_sqb_flush(struct otx2_nic *pfvf) 851 { 852 int qidx, sqe_tail, sqe_head; 853 struct otx2_snd_queue *sq; 854 u64 incr, *ptr, val; 855 856 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 857 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 858 sq = &pfvf->qset.sq[qidx]; 859 if (!sq->sqb_ptrs) 860 continue; 861 862 incr = (u64)qidx << 32; 863 val = otx2_atomic64_add(incr, ptr); 864 sqe_head = (val >> 20) & 0x3F; 865 sqe_tail = (val >> 28) & 0x3F; 866 if (sqe_head != sqe_tail) 867 usleep_range(50, 60); 868 } 869 } 870 871 /* RED and drop levels of CQ on packet reception. 872 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 873 */ 874 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 875 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 876 877 /* RED and drop levels of AURA for packet reception. 878 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 879 * Eg: For RQ length 1K, for pass/drop level 204/230. 880 * RED accepts pkts if free pointers > 102 & <= 205. 881 * Drops pkts if free pointers < 102. 882 */ 883 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 884 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 885 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 886 887 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 888 { 889 struct otx2_qset *qset = &pfvf->qset; 890 struct nix_aq_enq_req *aq; 891 892 /* Get memory to put this msg */ 893 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 894 if (!aq) 895 return -ENOMEM; 896 897 aq->rq.cq = qidx; 898 aq->rq.ena = 1; 899 aq->rq.pb_caching = 1; 900 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 901 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 902 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 903 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 904 aq->rq.qint_idx = 0; 905 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 906 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 907 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 908 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 909 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 910 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 911 912 /* Fill AQ info */ 913 aq->qidx = qidx; 914 aq->ctype = NIX_AQ_CTYPE_RQ; 915 aq->op = NIX_AQ_INSTOP_INIT; 916 917 return otx2_sync_mbox_msg(&pfvf->mbox); 918 } 919 920 int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura) 921 { 922 struct otx2_nic *pfvf = dev; 923 struct otx2_snd_queue *sq; 924 struct nix_aq_enq_req *aq; 925 926 sq = &pfvf->qset.sq[qidx]; 927 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 928 /* Get memory to put this msg */ 929 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 930 if (!aq) 931 return -ENOMEM; 932 933 aq->sq.cq = pfvf->hw.rx_queues + qidx; 934 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 935 aq->sq.cq_ena = 1; 936 aq->sq.ena = 1; 937 aq->sq.smq = otx2_get_smq_idx(pfvf, qidx); 938 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 939 aq->sq.default_chan = pfvf->hw.tx_chan_base + chan_offset; 940 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 941 aq->sq.sqb_aura = sqb_aura; 942 aq->sq.sq_int_ena = NIX_SQINT_BITS; 943 aq->sq.qint_idx = 0; 944 /* Due pipelining impact minimum 2000 unused SQ CQE's 945 * need to maintain to avoid CQ overflow. 946 */ 947 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 948 949 /* Fill AQ info */ 950 aq->qidx = qidx; 951 aq->ctype = NIX_AQ_CTYPE_SQ; 952 aq->op = NIX_AQ_INSTOP_INIT; 953 954 return otx2_sync_mbox_msg(&pfvf->mbox); 955 } 956 957 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 958 { 959 struct otx2_qset *qset = &pfvf->qset; 960 struct otx2_snd_queue *sq; 961 struct otx2_pool *pool; 962 u8 chan_offset; 963 int err; 964 965 pool = &pfvf->qset.pool[sqb_aura]; 966 sq = &qset->sq[qidx]; 967 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 968 sq->sqe_cnt = qset->sqe_cnt; 969 970 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 971 if (err) 972 return err; 973 974 /* Allocate memory for NIX SQE (which includes NIX SG) and CPT SG. 975 * SG of NIX and CPT are same in size. Allocate memory for CPT SG 976 * same as NIX SQE for base address alignment. 977 * Layout of a NIX SQE and CPT SG entry: 978 * ----------------------------- 979 * | CPT Scatter Gather | 980 * | (SQE SIZE) | 981 * | | 982 * ----------------------------- 983 * | NIX SQE | 984 * | (SQE SIZE) | 985 * | | 986 * ----------------------------- 987 */ 988 err = qmem_alloc(pfvf->dev, &sq->sqe_ring, qset->sqe_cnt, 989 sq->sqe_size * 2); 990 if (err) 991 return err; 992 993 err = qmem_alloc(pfvf->dev, &sq->cpt_resp, qset->sqe_cnt, 64); 994 if (err) 995 return err; 996 997 if (qidx < pfvf->hw.tx_queues) { 998 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 999 TSO_HEADER_SIZE); 1000 if (err) 1001 return err; 1002 } 1003 1004 sq->sqe_base = sq->sqe->base; 1005 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 1006 if (!sq->sg) 1007 return -ENOMEM; 1008 1009 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) { 1010 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 1011 sizeof(*sq->timestamps)); 1012 if (err) { 1013 kfree(sq->sg); 1014 sq->sg = NULL; 1015 return err; 1016 } 1017 } 1018 1019 sq->head = 0; 1020 sq->cons_head = 0; 1021 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 1022 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 1023 /* Set SQE threshold to 10% of total SQEs */ 1024 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 1025 sq->aura_id = sqb_aura; 1026 sq->aura_fc_addr = pool->fc_addr->base; 1027 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 1028 1029 sq->stats.bytes = 0; 1030 sq->stats.pkts = 0; 1031 1032 chan_offset = qidx % pfvf->hw.tx_chan_cnt; 1033 err = pfvf->hw_ops->sq_aq_init(pfvf, qidx, chan_offset, sqb_aura); 1034 if (err) { 1035 kfree(sq->sg); 1036 sq->sg = NULL; 1037 return err; 1038 } 1039 1040 return 0; 1041 1042 } 1043 1044 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 1045 { 1046 struct otx2_qset *qset = &pfvf->qset; 1047 int err, pool_id, non_xdp_queues; 1048 struct nix_aq_enq_req *aq; 1049 struct otx2_cq_queue *cq; 1050 1051 cq = &qset->cq[qidx]; 1052 cq->cq_idx = qidx; 1053 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues; 1054 if (qidx < pfvf->hw.rx_queues) { 1055 cq->cq_type = CQ_RX; 1056 cq->cint_idx = qidx; 1057 cq->cqe_cnt = qset->rqe_cnt; 1058 if (pfvf->xdp_prog) 1059 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0); 1060 } else if (qidx < non_xdp_queues) { 1061 cq->cq_type = CQ_TX; 1062 cq->cint_idx = qidx - pfvf->hw.rx_queues; 1063 cq->cqe_cnt = qset->sqe_cnt; 1064 } else { 1065 if (pfvf->hw.xdp_queues && 1066 qidx < non_xdp_queues + pfvf->hw.xdp_queues) { 1067 cq->cq_type = CQ_XDP; 1068 cq->cint_idx = qidx - non_xdp_queues; 1069 cq->cqe_cnt = qset->sqe_cnt; 1070 } else { 1071 cq->cq_type = CQ_QOS; 1072 cq->cint_idx = qidx - non_xdp_queues - 1073 pfvf->hw.xdp_queues; 1074 cq->cqe_cnt = qset->sqe_cnt; 1075 } 1076 } 1077 cq->cqe_size = pfvf->qset.xqe_size; 1078 1079 /* Allocate memory for CQEs */ 1080 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 1081 if (err) 1082 return err; 1083 1084 /* Save CQE CPU base for faster reference */ 1085 cq->cqe_base = cq->cqe->base; 1086 /* In case where all RQs auras point to single pool, 1087 * all CQs receive buffer pool also point to same pool. 1088 */ 1089 pool_id = ((cq->cq_type == CQ_RX) && 1090 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 1091 cq->rbpool = &qset->pool[pool_id]; 1092 cq->refill_task_sched = false; 1093 1094 /* Get memory to put this msg */ 1095 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 1096 if (!aq) 1097 return -ENOMEM; 1098 1099 aq->cq.ena = 1; 1100 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 1101 aq->cq.caching = 1; 1102 aq->cq.base = cq->cqe->iova; 1103 aq->cq.cint_idx = cq->cint_idx; 1104 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 1105 aq->cq.qint_idx = 0; 1106 aq->cq.avg_level = 255; 1107 1108 if (qidx < pfvf->hw.rx_queues) { 1109 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 1110 aq->cq.drop_ena = 1; 1111 1112 if (!is_otx2_lbkvf(pfvf->pdev)) { 1113 /* Enable receive CQ backpressure */ 1114 aq->cq.bp_ena = 1; 1115 #ifdef CONFIG_DCB 1116 aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]]; 1117 #else 1118 aq->cq.bpid = pfvf->bpid[0]; 1119 #endif 1120 1121 /* Set backpressure level is same as cq pass level */ 1122 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 1123 } 1124 } 1125 1126 /* Fill AQ info */ 1127 aq->qidx = qidx; 1128 aq->ctype = NIX_AQ_CTYPE_CQ; 1129 aq->op = NIX_AQ_INSTOP_INIT; 1130 1131 return otx2_sync_mbox_msg(&pfvf->mbox); 1132 } 1133 1134 static void otx2_pool_refill_task(struct work_struct *work) 1135 { 1136 struct otx2_cq_queue *cq; 1137 struct refill_work *wrk; 1138 struct otx2_nic *pfvf; 1139 int qidx; 1140 1141 wrk = container_of(work, struct refill_work, pool_refill_work.work); 1142 pfvf = wrk->pf; 1143 qidx = wrk - pfvf->refill_wrk; 1144 cq = &pfvf->qset.cq[qidx]; 1145 1146 cq->refill_task_sched = false; 1147 1148 local_bh_disable(); 1149 napi_schedule(wrk->napi); 1150 local_bh_enable(); 1151 } 1152 1153 int otx2_config_nix_queues(struct otx2_nic *pfvf) 1154 { 1155 int qidx, err; 1156 1157 /* Initialize RX queues */ 1158 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 1159 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 1160 1161 err = otx2_rq_init(pfvf, qidx, lpb_aura); 1162 if (err) 1163 return err; 1164 } 1165 1166 /* Initialize TX queues */ 1167 for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) { 1168 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1169 1170 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1171 if (err) 1172 return err; 1173 } 1174 1175 /* Initialize completion queues */ 1176 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1177 err = otx2_cq_init(pfvf, qidx); 1178 if (err) 1179 return err; 1180 } 1181 1182 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, 1183 NIX_LF_CQ_OP_STATUS); 1184 1185 /* Initialize work queue for receive buffer refill */ 1186 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1187 sizeof(struct refill_work), GFP_KERNEL); 1188 if (!pfvf->refill_wrk) 1189 return -ENOMEM; 1190 1191 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1192 pfvf->refill_wrk[qidx].pf = pfvf; 1193 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1194 otx2_pool_refill_task); 1195 } 1196 return 0; 1197 } 1198 1199 int otx2_config_nix(struct otx2_nic *pfvf) 1200 { 1201 struct nix_lf_alloc_req *nixlf; 1202 struct nix_lf_alloc_rsp *rsp; 1203 int err; 1204 1205 pfvf->qset.xqe_size = pfvf->hw.xqe_size; 1206 1207 /* Get memory to put this msg */ 1208 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1209 if (!nixlf) 1210 return -ENOMEM; 1211 1212 /* Set RQ/SQ/CQ counts */ 1213 nixlf->rq_cnt = pfvf->hw.rx_queues; 1214 nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf); 1215 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1216 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1217 nixlf->rss_grps = MAX_RSS_GROUPS; 1218 nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64; 1219 /* We don't know absolute NPA LF idx attached. 1220 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1221 * NPA LF attached to this RVU PF/VF. 1222 */ 1223 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1224 /* Disable alignment pad, enable L2 length check, 1225 * enable L4 TCP/UDP checksum verification. 1226 */ 1227 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1228 1229 err = otx2_sync_mbox_msg(&pfvf->mbox); 1230 if (err) 1231 return err; 1232 1233 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1234 &nixlf->hdr); 1235 if (IS_ERR(rsp)) 1236 return PTR_ERR(rsp); 1237 1238 if (rsp->qints < 1) 1239 return -ENXIO; 1240 1241 return rsp->hdr.rc; 1242 } 1243 1244 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1245 { 1246 struct otx2_qset *qset = &pfvf->qset; 1247 struct otx2_hw *hw = &pfvf->hw; 1248 struct otx2_snd_queue *sq; 1249 int sqb, qidx; 1250 u64 iova, pa; 1251 1252 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 1253 sq = &qset->sq[qidx]; 1254 if (!sq->sqb_ptrs) 1255 continue; 1256 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1257 if (!sq->sqb_ptrs[sqb]) 1258 continue; 1259 iova = sq->sqb_ptrs[sqb]; 1260 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1261 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1262 DMA_FROM_DEVICE, 1263 DMA_ATTR_SKIP_CPU_SYNC); 1264 put_page(virt_to_page(phys_to_virt(pa))); 1265 } 1266 sq->sqb_count = 0; 1267 } 1268 } 1269 1270 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1271 u64 iova, int size) 1272 { 1273 struct page *page; 1274 u64 pa; 1275 1276 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1277 page = virt_to_head_page(phys_to_virt(pa)); 1278 1279 if (pool->page_pool) { 1280 page_pool_put_full_page(pool->page_pool, page, true); 1281 } else { 1282 dma_unmap_page_attrs(pfvf->dev, iova, size, 1283 DMA_FROM_DEVICE, 1284 DMA_ATTR_SKIP_CPU_SYNC); 1285 1286 put_page(page); 1287 } 1288 } 1289 1290 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1291 { 1292 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1293 struct otx2_pool *pool; 1294 u64 iova; 1295 1296 if (type == AURA_NIX_SQ) { 1297 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1298 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1299 size = pfvf->hw.sqb_size; 1300 } 1301 if (type == AURA_NIX_RQ) { 1302 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1303 pool_end = pfvf->hw.rqpool_cnt; 1304 size = pfvf->rbsize; 1305 } 1306 1307 /* Free SQB and RQB pointers from the aura pool */ 1308 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1309 iova = otx2_aura_allocptr(pfvf, pool_id); 1310 pool = &pfvf->qset.pool[pool_id]; 1311 while (iova) { 1312 if (type == AURA_NIX_RQ) 1313 iova -= OTX2_HEAD_ROOM; 1314 1315 otx2_free_bufs(pfvf, pool, iova, size); 1316 1317 iova = otx2_aura_allocptr(pfvf, pool_id); 1318 } 1319 } 1320 } 1321 1322 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1323 { 1324 struct otx2_pool *pool; 1325 int pool_id; 1326 1327 if (!pfvf->qset.pool) 1328 return; 1329 1330 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1331 pool = &pfvf->qset.pool[pool_id]; 1332 qmem_free(pfvf->dev, pool->stack); 1333 qmem_free(pfvf->dev, pool->fc_addr); 1334 page_pool_destroy(pool->page_pool); 1335 pool->page_pool = NULL; 1336 } 1337 devm_kfree(pfvf->dev, pfvf->qset.pool); 1338 pfvf->qset.pool = NULL; 1339 } 1340 1341 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1342 int pool_id, int numptrs) 1343 { 1344 struct npa_aq_enq_req *aq; 1345 struct otx2_pool *pool; 1346 int err; 1347 1348 pool = &pfvf->qset.pool[pool_id]; 1349 1350 /* Allocate memory for HW to update Aura count. 1351 * Alloc one cache line, so that it fits all FC_STYPE modes. 1352 */ 1353 if (!pool->fc_addr) { 1354 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1355 if (err) 1356 return err; 1357 } 1358 1359 /* Initialize this aura's context via AF */ 1360 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1361 if (!aq) { 1362 /* Shared mbox memory buffer is full, flush it and retry */ 1363 err = otx2_sync_mbox_msg(&pfvf->mbox); 1364 if (err) 1365 return err; 1366 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1367 if (!aq) 1368 return -ENOMEM; 1369 } 1370 1371 aq->aura_id = aura_id; 1372 /* Will be filled by AF with correct pool context address */ 1373 aq->aura.pool_addr = pool_id; 1374 aq->aura.pool_caching = 1; 1375 aq->aura.shift = ilog2(numptrs) - 8; 1376 aq->aura.count = numptrs; 1377 aq->aura.limit = numptrs; 1378 aq->aura.avg_level = 255; 1379 aq->aura.ena = 1; 1380 aq->aura.fc_ena = 1; 1381 aq->aura.fc_addr = pool->fc_addr->iova; 1382 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1383 1384 /* Enable backpressure for RQ aura */ 1385 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1386 aq->aura.bp_ena = 0; 1387 /* If NIX1 LF is attached then specify NIX1_RX. 1388 * 1389 * Below NPA_AURA_S[BP_ENA] is set according to the 1390 * NPA_BPINTF_E enumeration given as: 1391 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1392 * NIX0_RX is 0x0 + 0*0x1 = 0 1393 * NIX1_RX is 0x0 + 1*0x1 = 1 1394 * But in HRM it is given that 1395 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1396 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1397 * enumerated by NPA_BPINTF_E." 1398 */ 1399 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1400 aq->aura.bp_ena = 1; 1401 #ifdef CONFIG_DCB 1402 aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]]; 1403 #else 1404 aq->aura.nix0_bpid = pfvf->bpid[0]; 1405 #endif 1406 1407 /* Set backpressure level for RQ's Aura */ 1408 aq->aura.bp = RQ_BP_LVL_AURA; 1409 } 1410 1411 /* Fill AQ info */ 1412 aq->ctype = NPA_AQ_CTYPE_AURA; 1413 aq->op = NPA_AQ_INSTOP_INIT; 1414 1415 return 0; 1416 } 1417 1418 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1419 int stack_pages, int numptrs, int buf_size, int type) 1420 { 1421 struct page_pool_params pp_params = { 0 }; 1422 struct npa_aq_enq_req *aq; 1423 struct otx2_pool *pool; 1424 int err; 1425 1426 pool = &pfvf->qset.pool[pool_id]; 1427 /* Alloc memory for stack which is used to store buffer pointers */ 1428 err = qmem_alloc(pfvf->dev, &pool->stack, 1429 stack_pages, pfvf->hw.stack_pg_bytes); 1430 if (err) 1431 return err; 1432 1433 pool->rbsize = buf_size; 1434 1435 /* Initialize this pool's context via AF */ 1436 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1437 if (!aq) { 1438 /* Shared mbox memory buffer is full, flush it and retry */ 1439 err = otx2_sync_mbox_msg(&pfvf->mbox); 1440 if (err) { 1441 qmem_free(pfvf->dev, pool->stack); 1442 return err; 1443 } 1444 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1445 if (!aq) { 1446 qmem_free(pfvf->dev, pool->stack); 1447 return -ENOMEM; 1448 } 1449 } 1450 1451 aq->aura_id = pool_id; 1452 aq->pool.stack_base = pool->stack->iova; 1453 aq->pool.stack_caching = 1; 1454 aq->pool.ena = 1; 1455 aq->pool.buf_size = buf_size / 128; 1456 aq->pool.stack_max_pages = stack_pages; 1457 aq->pool.shift = ilog2(numptrs) - 8; 1458 aq->pool.ptr_start = 0; 1459 aq->pool.ptr_end = ~0ULL; 1460 1461 /* Fill AQ info */ 1462 aq->ctype = NPA_AQ_CTYPE_POOL; 1463 aq->op = NPA_AQ_INSTOP_INIT; 1464 1465 if (type != AURA_NIX_RQ) { 1466 pool->page_pool = NULL; 1467 return 0; 1468 } 1469 1470 pp_params.order = get_order(buf_size); 1471 pp_params.flags = PP_FLAG_DMA_MAP; 1472 pp_params.pool_size = min(OTX2_PAGE_POOL_SZ, numptrs); 1473 pp_params.nid = NUMA_NO_NODE; 1474 pp_params.dev = pfvf->dev; 1475 pp_params.dma_dir = DMA_FROM_DEVICE; 1476 pool->page_pool = page_pool_create(&pp_params); 1477 if (IS_ERR(pool->page_pool)) { 1478 netdev_err(pfvf->netdev, "Creation of page pool failed\n"); 1479 return PTR_ERR(pool->page_pool); 1480 } 1481 1482 return 0; 1483 } 1484 1485 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1486 { 1487 int qidx, pool_id, stack_pages, num_sqbs; 1488 struct otx2_qset *qset = &pfvf->qset; 1489 struct otx2_hw *hw = &pfvf->hw; 1490 struct otx2_snd_queue *sq; 1491 struct otx2_pool *pool; 1492 dma_addr_t bufptr; 1493 int err, ptr; 1494 1495 /* Calculate number of SQBs needed. 1496 * 1497 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1498 * Last SQE is used for pointing to next SQB. 1499 */ 1500 num_sqbs = (hw->sqb_size / 128) - 1; 1501 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1502 1503 /* Get no of stack pages needed */ 1504 stack_pages = 1505 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1506 1507 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1508 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1509 /* Initialize aura context */ 1510 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1511 if (err) 1512 goto fail; 1513 1514 /* Initialize pool context */ 1515 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1516 num_sqbs, hw->sqb_size, AURA_NIX_SQ); 1517 if (err) 1518 goto fail; 1519 } 1520 1521 /* Flush accumulated messages */ 1522 err = otx2_sync_mbox_msg(&pfvf->mbox); 1523 if (err) 1524 goto fail; 1525 1526 /* Allocate pointers and free them to aura/pool */ 1527 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1528 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1529 pool = &pfvf->qset.pool[pool_id]; 1530 1531 sq = &qset->sq[qidx]; 1532 sq->sqb_count = 0; 1533 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1534 if (!sq->sqb_ptrs) { 1535 err = -ENOMEM; 1536 goto err_mem; 1537 } 1538 1539 for (ptr = 0; ptr < num_sqbs; ptr++) { 1540 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1541 if (err) 1542 goto err_mem; 1543 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1544 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1545 } 1546 } 1547 1548 err_mem: 1549 return err ? -ENOMEM : 0; 1550 1551 fail: 1552 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1553 otx2_aura_pool_free(pfvf); 1554 return err; 1555 } 1556 1557 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1558 { 1559 struct otx2_hw *hw = &pfvf->hw; 1560 int stack_pages, pool_id, rq; 1561 struct otx2_pool *pool; 1562 int err, ptr, num_ptrs; 1563 dma_addr_t bufptr; 1564 1565 num_ptrs = pfvf->qset.rqe_cnt; 1566 1567 stack_pages = 1568 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1569 1570 for (rq = 0; rq < hw->rx_queues; rq++) { 1571 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1572 /* Initialize aura context */ 1573 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1574 if (err) 1575 goto fail; 1576 } 1577 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1578 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1579 num_ptrs, pfvf->rbsize, AURA_NIX_RQ); 1580 if (err) 1581 goto fail; 1582 } 1583 1584 /* Flush accumulated messages */ 1585 err = otx2_sync_mbox_msg(&pfvf->mbox); 1586 if (err) 1587 goto fail; 1588 1589 /* Allocate pointers and free them to aura/pool */ 1590 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1591 pool = &pfvf->qset.pool[pool_id]; 1592 for (ptr = 0; ptr < num_ptrs; ptr++) { 1593 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1594 if (err) 1595 return -ENOMEM; 1596 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1597 bufptr + OTX2_HEAD_ROOM); 1598 } 1599 } 1600 return 0; 1601 fail: 1602 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1603 otx2_aura_pool_free(pfvf); 1604 return err; 1605 } 1606 1607 int otx2_config_npa(struct otx2_nic *pfvf) 1608 { 1609 struct otx2_qset *qset = &pfvf->qset; 1610 struct npa_lf_alloc_req *npalf; 1611 struct otx2_hw *hw = &pfvf->hw; 1612 int aura_cnt; 1613 1614 /* Pool - Stack of free buffer pointers 1615 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1616 */ 1617 1618 if (!hw->pool_cnt) 1619 return -EINVAL; 1620 1621 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1622 sizeof(struct otx2_pool), GFP_KERNEL); 1623 if (!qset->pool) 1624 return -ENOMEM; 1625 1626 /* Get memory to put this msg */ 1627 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1628 if (!npalf) 1629 return -ENOMEM; 1630 1631 /* Set aura and pool counts */ 1632 npalf->nr_pools = hw->pool_cnt; 1633 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1634 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1635 1636 return otx2_sync_mbox_msg(&pfvf->mbox); 1637 } 1638 1639 int otx2_detach_resources(struct mbox *mbox) 1640 { 1641 struct rsrc_detach *detach; 1642 1643 mutex_lock(&mbox->lock); 1644 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1645 if (!detach) { 1646 mutex_unlock(&mbox->lock); 1647 return -ENOMEM; 1648 } 1649 1650 /* detach all */ 1651 detach->partial = false; 1652 1653 /* Send detach request to AF */ 1654 otx2_sync_mbox_msg(mbox); 1655 mutex_unlock(&mbox->lock); 1656 return 0; 1657 } 1658 EXPORT_SYMBOL(otx2_detach_resources); 1659 1660 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1661 { 1662 struct rsrc_attach *attach; 1663 struct msg_req *msix; 1664 int err; 1665 1666 mutex_lock(&pfvf->mbox.lock); 1667 /* Get memory to put this msg */ 1668 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1669 if (!attach) { 1670 mutex_unlock(&pfvf->mbox.lock); 1671 return -ENOMEM; 1672 } 1673 1674 attach->npalf = true; 1675 attach->nixlf = true; 1676 1677 /* Send attach request to AF */ 1678 err = otx2_sync_mbox_msg(&pfvf->mbox); 1679 if (err) { 1680 mutex_unlock(&pfvf->mbox.lock); 1681 return err; 1682 } 1683 1684 pfvf->nix_blkaddr = BLKADDR_NIX0; 1685 1686 /* If the platform has two NIX blocks then LF may be 1687 * allocated from NIX1. 1688 */ 1689 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1690 pfvf->nix_blkaddr = BLKADDR_NIX1; 1691 1692 /* Get NPA and NIX MSIX vector offsets */ 1693 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1694 if (!msix) { 1695 mutex_unlock(&pfvf->mbox.lock); 1696 return -ENOMEM; 1697 } 1698 1699 err = otx2_sync_mbox_msg(&pfvf->mbox); 1700 if (err) { 1701 mutex_unlock(&pfvf->mbox.lock); 1702 return err; 1703 } 1704 mutex_unlock(&pfvf->mbox.lock); 1705 1706 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1707 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1708 dev_err(pfvf->dev, 1709 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1710 return -EINVAL; 1711 } 1712 1713 return 0; 1714 } 1715 EXPORT_SYMBOL(otx2_attach_npa_nix); 1716 1717 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1718 { 1719 struct hwctx_disable_req *req; 1720 1721 mutex_lock(&mbox->lock); 1722 /* Request AQ to disable this context */ 1723 if (npa) 1724 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1725 else 1726 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1727 1728 if (!req) { 1729 mutex_unlock(&mbox->lock); 1730 return; 1731 } 1732 1733 req->ctype = type; 1734 1735 if (otx2_sync_mbox_msg(mbox)) 1736 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1737 __func__); 1738 1739 mutex_unlock(&mbox->lock); 1740 } 1741 1742 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1743 { 1744 struct nix_bp_cfg_req *req; 1745 1746 if (enable) 1747 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1748 else 1749 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1750 1751 if (!req) 1752 return -ENOMEM; 1753 1754 req->chan_base = 0; 1755 if (otx2_is_pfc_enabled(pfvf)) { 1756 req->chan_cnt = IEEE_8021QAZ_MAX_TCS; 1757 req->bpid_per_chan = 1; 1758 } else { 1759 req->chan_cnt = 1; 1760 req->bpid_per_chan = 0; 1761 } 1762 1763 return otx2_sync_mbox_msg(&pfvf->mbox); 1764 } 1765 EXPORT_SYMBOL(otx2_nix_config_bp); 1766 1767 int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable) 1768 { 1769 struct nix_bp_cfg_req *req; 1770 1771 if (enable) 1772 req = otx2_mbox_alloc_msg_nix_cpt_bp_enable(&pfvf->mbox); 1773 else 1774 req = otx2_mbox_alloc_msg_nix_cpt_bp_disable(&pfvf->mbox); 1775 1776 if (!req) 1777 return -ENOMEM; 1778 1779 req->chan_base = 0; 1780 if (otx2_is_pfc_enabled(pfvf)) { 1781 req->chan_cnt = IEEE_8021QAZ_MAX_TCS; 1782 req->bpid_per_chan = 1; 1783 } else { 1784 req->chan_cnt = 1; 1785 req->bpid_per_chan = 0; 1786 } 1787 1788 return otx2_sync_mbox_msg(&pfvf->mbox); 1789 } 1790 EXPORT_SYMBOL(otx2_nix_cpt_config_bp); 1791 1792 /* Mbox message handlers */ 1793 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1794 struct cgx_stats_rsp *rsp) 1795 { 1796 int id; 1797 1798 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1799 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1800 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1801 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1802 } 1803 1804 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1805 struct cgx_fec_stats_rsp *rsp) 1806 { 1807 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1808 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1809 } 1810 1811 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1812 struct npa_lf_alloc_rsp *rsp) 1813 { 1814 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1815 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1816 } 1817 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1818 1819 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1820 struct nix_lf_alloc_rsp *rsp) 1821 { 1822 pfvf->hw.sqb_size = rsp->sqb_size; 1823 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1824 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1825 pfvf->hw.rx_chan_cnt = rsp->rx_chan_cnt; 1826 pfvf->hw.tx_chan_cnt = rsp->tx_chan_cnt; 1827 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1828 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1829 pfvf->hw.cgx_links = rsp->cgx_links; 1830 pfvf->hw.lbk_links = rsp->lbk_links; 1831 pfvf->hw.tx_link = rsp->tx_link; 1832 } 1833 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1834 1835 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1836 struct msix_offset_rsp *rsp) 1837 { 1838 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1839 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1840 } 1841 EXPORT_SYMBOL(mbox_handler_msix_offset); 1842 1843 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1844 struct nix_bp_cfg_rsp *rsp) 1845 { 1846 int chan, chan_id; 1847 1848 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1849 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1850 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1851 } 1852 } 1853 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1854 1855 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1856 { 1857 struct otx2_qset *qset = &pfvf->qset; 1858 struct otx2_hw *hw = &pfvf->hw; 1859 int irq, qidx; 1860 1861 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1862 qidx < n; 1863 qidx++, irq++) { 1864 int vector = pci_irq_vector(pfvf->pdev, irq); 1865 1866 irq_set_affinity_hint(vector, NULL); 1867 free_cpumask_var(hw->affinity_mask[irq]); 1868 free_irq(vector, &qset->napi[qidx]); 1869 } 1870 } 1871 EXPORT_SYMBOL(otx2_free_cints); 1872 1873 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1874 { 1875 struct otx2_hw *hw = &pfvf->hw; 1876 int vec, cpu, irq, cint; 1877 1878 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1879 cpu = cpumask_first(cpu_online_mask); 1880 1881 /* CQ interrupts */ 1882 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1883 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1884 return; 1885 1886 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1887 1888 irq = pci_irq_vector(pfvf->pdev, vec); 1889 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1890 1891 cpu = cpumask_next(cpu, cpu_online_mask); 1892 if (unlikely(cpu >= nr_cpu_ids)) 1893 cpu = 0; 1894 } 1895 } 1896 1897 static u32 get_dwrr_mtu(struct otx2_nic *pfvf, struct nix_hw_info *hw) 1898 { 1899 if (is_otx2_lbkvf(pfvf->pdev)) { 1900 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_LBK; 1901 return hw->lbk_dwrr_mtu; 1902 } 1903 1904 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_RPM; 1905 return hw->rpm_dwrr_mtu; 1906 } 1907 1908 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1909 { 1910 struct nix_hw_info *rsp; 1911 struct msg_req *req; 1912 u16 max_mtu; 1913 int rc; 1914 1915 mutex_lock(&pfvf->mbox.lock); 1916 1917 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1918 if (!req) { 1919 rc = -ENOMEM; 1920 goto out; 1921 } 1922 1923 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1924 if (!rc) { 1925 rsp = (struct nix_hw_info *) 1926 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1927 if (IS_ERR(rsp)) { 1928 rc = PTR_ERR(rsp); 1929 goto out; 1930 } 1931 1932 /* HW counts VLAN insertion bytes (8 for double tag) 1933 * irrespective of whether SQE is requesting to insert VLAN 1934 * in the packet or not. Hence these 8 bytes have to be 1935 * discounted from max packet size otherwise HW will throw 1936 * SMQ errors 1937 */ 1938 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1939 1940 /* Also save DWRR MTU, needed for DWRR weight calculation */ 1941 pfvf->hw.dwrr_mtu = get_dwrr_mtu(pfvf, rsp); 1942 if (!pfvf->hw.dwrr_mtu) 1943 pfvf->hw.dwrr_mtu = 1; 1944 } 1945 1946 out: 1947 mutex_unlock(&pfvf->mbox.lock); 1948 if (rc) { 1949 dev_warn(pfvf->dev, 1950 "Failed to get MTU from hardware setting default value(1500)\n"); 1951 max_mtu = 1500; 1952 } 1953 return max_mtu; 1954 } 1955 EXPORT_SYMBOL(otx2_get_max_mtu); 1956 1957 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features) 1958 { 1959 netdev_features_t changed = features ^ netdev->features; 1960 struct otx2_nic *pfvf = netdev_priv(netdev); 1961 bool ntuple = !!(features & NETIF_F_NTUPLE); 1962 bool tc = !!(features & NETIF_F_HW_TC); 1963 1964 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1965 otx2_destroy_ntuple_flows(pfvf); 1966 1967 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1968 if (!pfvf->flow_cfg->max_flows) { 1969 netdev_err(netdev, 1970 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1971 return -EINVAL; 1972 } 1973 } 1974 1975 if ((changed & NETIF_F_HW_TC) && !tc && 1976 otx2_tc_flower_rule_cnt(pfvf)) { 1977 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1978 return -EBUSY; 1979 } 1980 1981 if ((changed & NETIF_F_NTUPLE) && ntuple && 1982 otx2_tc_flower_rule_cnt(pfvf) && !(changed & NETIF_F_HW_TC)) { 1983 netdev_err(netdev, 1984 "Can't enable NTUPLE when TC flower offload is active, disable TC rules and retry\n"); 1985 return -EINVAL; 1986 } 1987 1988 return 0; 1989 } 1990 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features); 1991 1992 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1993 int __weak \ 1994 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1995 struct _req_type *req, \ 1996 struct _rsp_type *rsp) \ 1997 { \ 1998 /* Nothing to do here */ \ 1999 return 0; \ 2000 } \ 2001 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 2002 MBOX_UP_CGX_MESSAGES 2003 MBOX_UP_MCS_MESSAGES 2004 #undef M 2005 2006 dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 2007 struct sk_buff *skb, int seg, int *len) 2008 { 2009 enum dma_data_direction dir = DMA_TO_DEVICE; 2010 const skb_frag_t *frag; 2011 struct page *page; 2012 int offset; 2013 2014 /* Crypto hardware need write permission for ipsec crypto offload */ 2015 if (unlikely(xfrm_offload(skb))) { 2016 dir = DMA_BIDIRECTIONAL; 2017 skb = skb_unshare(skb, GFP_ATOMIC); 2018 } 2019 2020 /* First segment is always skb->data */ 2021 if (!seg) { 2022 page = virt_to_page(skb->data); 2023 offset = offset_in_page(skb->data); 2024 *len = skb_headlen(skb); 2025 } else { 2026 frag = &skb_shinfo(skb)->frags[seg - 1]; 2027 page = skb_frag_page(frag); 2028 offset = skb_frag_off(frag); 2029 *len = skb_frag_size(frag); 2030 } 2031 return otx2_dma_map_page(pfvf, page, offset, *len, dir); 2032 } 2033 2034 void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg) 2035 { 2036 enum dma_data_direction dir = DMA_TO_DEVICE; 2037 struct sk_buff *skb = NULL; 2038 int seg; 2039 2040 skb = (struct sk_buff *)sg->skb; 2041 if (unlikely(xfrm_offload(skb))) 2042 dir = DMA_BIDIRECTIONAL; 2043 2044 for (seg = 0; seg < sg->num_segs; seg++) { 2045 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg], 2046 sg->size[seg], dir); 2047 } 2048 sg->num_segs = 0; 2049 } 2050