1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2020 Marvell. 5 */ 6 7 #include <linux/bitfield.h> 8 9 #include "rvu_struct.h" 10 #include "rvu_reg.h" 11 #include "rvu.h" 12 #include "npc.h" 13 #include "rvu_npc_fs.h" 14 #include "rvu_npc_hash.h" 15 16 static const char * const npc_flow_names[] = { 17 [NPC_DMAC] = "dmac", 18 [NPC_SMAC] = "smac", 19 [NPC_ETYPE] = "ether type", 20 [NPC_VLAN_ETYPE_CTAG] = "vlan ether type ctag", 21 [NPC_VLAN_ETYPE_STAG] = "vlan ether type stag", 22 [NPC_OUTER_VID] = "outer vlan id", 23 [NPC_INNER_VID] = "inner vlan id", 24 [NPC_TOS] = "tos", 25 [NPC_IPFRAG_IPV4] = "fragmented IPv4 header ", 26 [NPC_SIP_IPV4] = "ipv4 source ip", 27 [NPC_DIP_IPV4] = "ipv4 destination ip", 28 [NPC_IPFRAG_IPV6] = "fragmented IPv6 header ", 29 [NPC_SIP_IPV6] = "ipv6 source ip", 30 [NPC_DIP_IPV6] = "ipv6 destination ip", 31 [NPC_IPPROTO_TCP] = "ip proto tcp", 32 [NPC_IPPROTO_UDP] = "ip proto udp", 33 [NPC_IPPROTO_SCTP] = "ip proto sctp", 34 [NPC_IPPROTO_ICMP] = "ip proto icmp", 35 [NPC_IPPROTO_ICMP6] = "ip proto icmp6", 36 [NPC_IPPROTO_AH] = "ip proto AH", 37 [NPC_IPPROTO_ESP] = "ip proto ESP", 38 [NPC_SPORT_TCP] = "tcp source port", 39 [NPC_DPORT_TCP] = "tcp destination port", 40 [NPC_SPORT_UDP] = "udp source port", 41 [NPC_DPORT_UDP] = "udp destination port", 42 [NPC_SPORT_SCTP] = "sctp source port", 43 [NPC_DPORT_SCTP] = "sctp destination port", 44 [NPC_LXMB] = "Mcast/Bcast header ", 45 [NPC_IPSEC_SPI] = "SPI ", 46 [NPC_MPLS1_LBTCBOS] = "lse depth 1 label tc bos", 47 [NPC_MPLS1_TTL] = "lse depth 1 ttl", 48 [NPC_MPLS2_LBTCBOS] = "lse depth 2 label tc bos", 49 [NPC_MPLS2_TTL] = "lse depth 2 ttl", 50 [NPC_MPLS3_LBTCBOS] = "lse depth 3 label tc bos", 51 [NPC_MPLS3_TTL] = "lse depth 3 ttl", 52 [NPC_MPLS4_LBTCBOS] = "lse depth 4 label tc bos", 53 [NPC_MPLS4_TTL] = "lse depth 4", 54 [NPC_TYPE_ICMP] = "icmp type", 55 [NPC_CODE_ICMP] = "icmp code", 56 [NPC_UNKNOWN] = "unknown", 57 }; 58 59 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf) 60 { 61 struct npc_mcam *mcam = &rvu->hw->mcam; 62 u64 mcam_features; 63 u64 unsupported; 64 65 mcam_features = is_npc_intf_tx(intf) ? mcam->tx_features : mcam->rx_features; 66 unsupported = (mcam_features ^ features) & ~mcam_features; 67 68 /* Return false if at least one of the input flows is not extracted */ 69 return !unsupported; 70 } 71 72 const char *npc_get_field_name(u8 hdr) 73 { 74 if (hdr >= ARRAY_SIZE(npc_flow_names)) 75 return npc_flow_names[NPC_UNKNOWN]; 76 77 return npc_flow_names[hdr]; 78 } 79 80 /* Compute keyword masks and figure out the number of keywords a field 81 * spans in the key. 82 */ 83 static void npc_set_kw_masks(struct npc_mcam *mcam, u8 type, 84 u8 nr_bits, int start_kwi, int offset, u8 intf) 85 { 86 struct npc_key_field *field = &mcam->rx_key_fields[type]; 87 u8 bits_in_kw; 88 int max_kwi; 89 90 if (mcam->banks_per_entry == 1) 91 max_kwi = 1; /* NPC_MCAM_KEY_X1 */ 92 else if (mcam->banks_per_entry == 2) 93 max_kwi = 3; /* NPC_MCAM_KEY_X2 */ 94 else 95 max_kwi = 6; /* NPC_MCAM_KEY_X4 */ 96 97 if (is_npc_intf_tx(intf)) 98 field = &mcam->tx_key_fields[type]; 99 100 if (offset + nr_bits <= 64) { 101 /* one KW only */ 102 if (start_kwi > max_kwi) 103 return; 104 field->kw_mask[start_kwi] |= GENMASK_ULL(nr_bits - 1, 0) 105 << offset; 106 field->nr_kws = 1; 107 } else if (offset + nr_bits > 64 && 108 offset + nr_bits <= 128) { 109 /* two KWs */ 110 if (start_kwi + 1 > max_kwi) 111 return; 112 /* first KW mask */ 113 bits_in_kw = 64 - offset; 114 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0) 115 << offset; 116 /* second KW mask i.e. mask for rest of bits */ 117 bits_in_kw = nr_bits + offset - 64; 118 field->kw_mask[start_kwi + 1] |= GENMASK_ULL(bits_in_kw - 1, 0); 119 field->nr_kws = 2; 120 } else { 121 /* three KWs */ 122 if (start_kwi + 2 > max_kwi) 123 return; 124 /* first KW mask */ 125 bits_in_kw = 64 - offset; 126 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0) 127 << offset; 128 /* second KW mask */ 129 field->kw_mask[start_kwi + 1] = ~0ULL; 130 /* third KW mask i.e. mask for rest of bits */ 131 bits_in_kw = nr_bits + offset - 128; 132 field->kw_mask[start_kwi + 2] |= GENMASK_ULL(bits_in_kw - 1, 0); 133 field->nr_kws = 3; 134 } 135 } 136 137 /* Helper function to figure out whether field exists in the key */ 138 static bool npc_is_field_present(struct rvu *rvu, enum key_fields type, u8 intf) 139 { 140 struct npc_mcam *mcam = &rvu->hw->mcam; 141 struct npc_key_field *input; 142 143 input = &mcam->rx_key_fields[type]; 144 if (is_npc_intf_tx(intf)) 145 input = &mcam->tx_key_fields[type]; 146 147 return input->nr_kws > 0; 148 } 149 150 static bool npc_is_same(struct npc_key_field *input, 151 struct npc_key_field *field) 152 { 153 return memcmp(&input->layer_mdata, &field->layer_mdata, 154 sizeof(struct npc_layer_mdata)) == 0; 155 } 156 157 static void npc_set_layer_mdata(struct npc_mcam *mcam, enum key_fields type, 158 u64 cfg, u8 lid, u8 lt, u8 intf) 159 { 160 struct npc_key_field *input = &mcam->rx_key_fields[type]; 161 162 if (is_npc_intf_tx(intf)) 163 input = &mcam->tx_key_fields[type]; 164 165 input->layer_mdata.hdr = FIELD_GET(NPC_HDR_OFFSET, cfg); 166 input->layer_mdata.key = FIELD_GET(NPC_KEY_OFFSET, cfg); 167 input->layer_mdata.len = FIELD_GET(NPC_BYTESM, cfg) + 1; 168 input->layer_mdata.ltype = lt; 169 input->layer_mdata.lid = lid; 170 } 171 172 static bool npc_check_overlap_fields(struct npc_key_field *input1, 173 struct npc_key_field *input2) 174 { 175 int kwi; 176 177 /* Fields with same layer id and different ltypes are mutually 178 * exclusive hence they can be overlapped 179 */ 180 if (input1->layer_mdata.lid == input2->layer_mdata.lid && 181 input1->layer_mdata.ltype != input2->layer_mdata.ltype) 182 return false; 183 184 for (kwi = 0; kwi < NPC_MAX_KWS_IN_KEY; kwi++) { 185 if (input1->kw_mask[kwi] & input2->kw_mask[kwi]) 186 return true; 187 } 188 189 return false; 190 } 191 192 /* Helper function to check whether given field overlaps with any other fields 193 * in the key. Due to limitations on key size and the key extraction profile in 194 * use higher layers can overwrite lower layer's header fields. Hence overlap 195 * needs to be checked. 196 */ 197 static bool npc_check_overlap(struct rvu *rvu, int blkaddr, 198 enum key_fields type, u8 start_lid, u8 intf) 199 { 200 struct npc_mcam *mcam = &rvu->hw->mcam; 201 struct npc_key_field *dummy, *input; 202 int start_kwi, offset; 203 u8 nr_bits, lid, lt, ld; 204 u64 cfg; 205 206 dummy = &mcam->rx_key_fields[NPC_UNKNOWN]; 207 input = &mcam->rx_key_fields[type]; 208 209 if (is_npc_intf_tx(intf)) { 210 dummy = &mcam->tx_key_fields[NPC_UNKNOWN]; 211 input = &mcam->tx_key_fields[type]; 212 } 213 214 for (lid = start_lid; lid < NPC_MAX_LID; lid++) { 215 for (lt = 0; lt < NPC_MAX_LT; lt++) { 216 for (ld = 0; ld < NPC_MAX_LD; ld++) { 217 cfg = rvu_read64(rvu, blkaddr, 218 NPC_AF_INTFX_LIDX_LTX_LDX_CFG 219 (intf, lid, lt, ld)); 220 if (!FIELD_GET(NPC_LDATA_EN, cfg)) 221 continue; 222 memset(dummy, 0, sizeof(struct npc_key_field)); 223 npc_set_layer_mdata(mcam, NPC_UNKNOWN, cfg, 224 lid, lt, intf); 225 /* exclude input */ 226 if (npc_is_same(input, dummy)) 227 continue; 228 start_kwi = dummy->layer_mdata.key / 8; 229 offset = (dummy->layer_mdata.key * 8) % 64; 230 nr_bits = dummy->layer_mdata.len * 8; 231 /* form KW masks */ 232 npc_set_kw_masks(mcam, NPC_UNKNOWN, nr_bits, 233 start_kwi, offset, intf); 234 /* check any input field bits falls in any 235 * other field bits. 236 */ 237 if (npc_check_overlap_fields(dummy, input)) 238 return true; 239 } 240 } 241 } 242 243 return false; 244 } 245 246 static bool npc_check_field(struct rvu *rvu, int blkaddr, enum key_fields type, 247 u8 intf) 248 { 249 if (!npc_is_field_present(rvu, type, intf) || 250 npc_check_overlap(rvu, blkaddr, type, 0, intf)) 251 return false; 252 return true; 253 } 254 255 static void npc_scan_exact_result(struct npc_mcam *mcam, u8 bit_number, 256 u8 key_nibble, u8 intf) 257 { 258 u8 offset = (key_nibble * 4) % 64; /* offset within key word */ 259 u8 kwi = (key_nibble * 4) / 64; /* which word in key */ 260 u8 nr_bits = 4; /* bits in a nibble */ 261 u8 type; 262 263 switch (bit_number) { 264 case 40 ... 43: 265 type = NPC_EXACT_RESULT; 266 break; 267 268 default: 269 return; 270 } 271 npc_set_kw_masks(mcam, type, nr_bits, kwi, offset, intf); 272 } 273 274 static void npc_scan_parse_result(struct npc_mcam *mcam, u8 bit_number, 275 u8 key_nibble, u8 intf) 276 { 277 u8 offset = (key_nibble * 4) % 64; /* offset within key word */ 278 u8 kwi = (key_nibble * 4) / 64; /* which word in key */ 279 u8 nr_bits = 4; /* bits in a nibble */ 280 u8 type; 281 282 switch (bit_number) { 283 case 0 ... 2: 284 type = NPC_CHAN; 285 break; 286 case 3: 287 type = NPC_ERRLEV; 288 break; 289 case 4 ... 5: 290 type = NPC_ERRCODE; 291 break; 292 case 6: 293 type = NPC_LXMB; 294 break; 295 /* check for LTYPE only as of now */ 296 case 9: 297 type = NPC_LA; 298 break; 299 case 12: 300 type = NPC_LB; 301 break; 302 case 15: 303 type = NPC_LC; 304 break; 305 case 18: 306 type = NPC_LD; 307 break; 308 case 21: 309 type = NPC_LE; 310 break; 311 case 24: 312 type = NPC_LF; 313 break; 314 case 27: 315 type = NPC_LG; 316 break; 317 case 30: 318 type = NPC_LH; 319 break; 320 default: 321 return; 322 } 323 324 npc_set_kw_masks(mcam, type, nr_bits, kwi, offset, intf); 325 } 326 327 static void npc_handle_multi_layer_fields(struct rvu *rvu, int blkaddr, u8 intf) 328 { 329 struct npc_mcam *mcam = &rvu->hw->mcam; 330 struct npc_key_field *key_fields; 331 /* Ether type can come from three layers 332 * (ethernet, single tagged, double tagged) 333 */ 334 struct npc_key_field *etype_ether; 335 struct npc_key_field *etype_tag1; 336 struct npc_key_field *etype_tag2; 337 /* Outer VLAN TCI can come from two layers 338 * (single tagged, double tagged) 339 */ 340 struct npc_key_field *vlan_tag1; 341 struct npc_key_field *vlan_tag2; 342 /* Inner VLAN TCI for double tagged frames */ 343 struct npc_key_field *vlan_tag3; 344 u64 *features; 345 u8 start_lid; 346 int i; 347 348 key_fields = mcam->rx_key_fields; 349 features = &mcam->rx_features; 350 351 if (is_npc_intf_tx(intf)) { 352 key_fields = mcam->tx_key_fields; 353 features = &mcam->tx_features; 354 } 355 356 /* Handle header fields which can come from multiple layers like 357 * etype, outer vlan tci. These fields should have same position in 358 * the key otherwise to install a mcam rule more than one entry is 359 * needed which complicates mcam space management. 360 */ 361 etype_ether = &key_fields[NPC_ETYPE_ETHER]; 362 etype_tag1 = &key_fields[NPC_ETYPE_TAG1]; 363 etype_tag2 = &key_fields[NPC_ETYPE_TAG2]; 364 vlan_tag1 = &key_fields[NPC_VLAN_TAG1]; 365 vlan_tag2 = &key_fields[NPC_VLAN_TAG2]; 366 vlan_tag3 = &key_fields[NPC_VLAN_TAG3]; 367 368 /* if key profile programmed does not extract Ethertype at all */ 369 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws) { 370 dev_err(rvu->dev, "mkex: Ethertype is not extracted.\n"); 371 goto vlan_tci; 372 } 373 374 /* if key profile programmed extracts Ethertype from one layer */ 375 if (etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws) 376 key_fields[NPC_ETYPE] = *etype_ether; 377 if (!etype_ether->nr_kws && etype_tag1->nr_kws && !etype_tag2->nr_kws) 378 key_fields[NPC_ETYPE] = *etype_tag1; 379 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && etype_tag2->nr_kws) 380 key_fields[NPC_ETYPE] = *etype_tag2; 381 382 /* if key profile programmed extracts Ethertype from multiple layers */ 383 if (etype_ether->nr_kws && etype_tag1->nr_kws) { 384 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 385 if (etype_ether->kw_mask[i] != etype_tag1->kw_mask[i]) { 386 dev_err(rvu->dev, "mkex: Etype pos is different for untagged and tagged pkts.\n"); 387 goto vlan_tci; 388 } 389 } 390 key_fields[NPC_ETYPE] = *etype_tag1; 391 } 392 if (etype_ether->nr_kws && etype_tag2->nr_kws) { 393 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 394 if (etype_ether->kw_mask[i] != etype_tag2->kw_mask[i]) { 395 dev_err(rvu->dev, "mkex: Etype pos is different for untagged and double tagged pkts.\n"); 396 goto vlan_tci; 397 } 398 } 399 key_fields[NPC_ETYPE] = *etype_tag2; 400 } 401 if (etype_tag1->nr_kws && etype_tag2->nr_kws) { 402 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 403 if (etype_tag1->kw_mask[i] != etype_tag2->kw_mask[i]) { 404 dev_err(rvu->dev, "mkex: Etype pos is different for tagged and double tagged pkts.\n"); 405 goto vlan_tci; 406 } 407 } 408 key_fields[NPC_ETYPE] = *etype_tag2; 409 } 410 411 /* check none of higher layers overwrite Ethertype */ 412 start_lid = key_fields[NPC_ETYPE].layer_mdata.lid + 1; 413 if (npc_check_overlap(rvu, blkaddr, NPC_ETYPE, start_lid, intf)) { 414 dev_err(rvu->dev, "mkex: Ethertype is overwritten by higher layers.\n"); 415 goto vlan_tci; 416 } 417 *features |= BIT_ULL(NPC_ETYPE); 418 vlan_tci: 419 /* if key profile does not extract outer vlan tci at all */ 420 if (!vlan_tag1->nr_kws && !vlan_tag2->nr_kws) { 421 dev_err(rvu->dev, "mkex: Outer vlan tci is not extracted.\n"); 422 goto done; 423 } 424 425 /* if key profile extracts outer vlan tci from one layer */ 426 if (vlan_tag1->nr_kws && !vlan_tag2->nr_kws) 427 key_fields[NPC_OUTER_VID] = *vlan_tag1; 428 if (!vlan_tag1->nr_kws && vlan_tag2->nr_kws) 429 key_fields[NPC_OUTER_VID] = *vlan_tag2; 430 431 /* if key profile extracts outer vlan tci from multiple layers */ 432 if (vlan_tag1->nr_kws && vlan_tag2->nr_kws) { 433 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 434 if (vlan_tag1->kw_mask[i] != vlan_tag2->kw_mask[i]) { 435 dev_err(rvu->dev, "mkex: Out vlan tci pos is different for tagged and double tagged pkts.\n"); 436 goto done; 437 } 438 } 439 key_fields[NPC_OUTER_VID] = *vlan_tag2; 440 } 441 /* check none of higher layers overwrite outer vlan tci */ 442 start_lid = key_fields[NPC_OUTER_VID].layer_mdata.lid + 1; 443 if (npc_check_overlap(rvu, blkaddr, NPC_OUTER_VID, start_lid, intf)) { 444 dev_err(rvu->dev, "mkex: Outer vlan tci is overwritten by higher layers.\n"); 445 goto done; 446 } 447 *features |= BIT_ULL(NPC_OUTER_VID); 448 449 /* If key profile extracts inner vlan tci */ 450 if (vlan_tag3->nr_kws) { 451 key_fields[NPC_INNER_VID] = *vlan_tag3; 452 *features |= BIT_ULL(NPC_INNER_VID); 453 } 454 done: 455 return; 456 } 457 458 static void npc_scan_ldata(struct rvu *rvu, int blkaddr, u8 lid, 459 u8 lt, u64 cfg, u8 intf) 460 { 461 struct npc_mcam_kex_hash *mkex_hash = rvu->kpu.mkex_hash; 462 struct npc_mcam *mcam = &rvu->hw->mcam; 463 u8 hdr, key, nr_bytes, bit_offset; 464 u8 la_ltype, la_start; 465 /* starting KW index and starting bit position */ 466 int start_kwi, offset; 467 468 nr_bytes = FIELD_GET(NPC_BYTESM, cfg) + 1; 469 hdr = FIELD_GET(NPC_HDR_OFFSET, cfg); 470 key = FIELD_GET(NPC_KEY_OFFSET, cfg); 471 472 /* For Tx, Layer A has NIX_INST_HDR_S(64 bytes) preceding 473 * ethernet header. 474 */ 475 if (is_npc_intf_tx(intf)) { 476 la_ltype = NPC_LT_LA_IH_NIX_ETHER; 477 la_start = 8; 478 } else { 479 la_ltype = NPC_LT_LA_ETHER; 480 la_start = 0; 481 } 482 483 #define NPC_SCAN_HDR(name, hlid, hlt, hstart, hlen) \ 484 do { \ 485 start_kwi = key / 8; \ 486 offset = (key * 8) % 64; \ 487 if (lid == (hlid) && lt == (hlt)) { \ 488 if ((hstart) >= hdr && \ 489 ((hstart) + (hlen)) <= (hdr + nr_bytes)) { \ 490 bit_offset = (hdr + nr_bytes - (hstart) - (hlen)) * 8; \ 491 npc_set_layer_mdata(mcam, (name), cfg, lid, lt, intf); \ 492 offset += bit_offset; \ 493 start_kwi += offset / 64; \ 494 offset %= 64; \ 495 npc_set_kw_masks(mcam, (name), (hlen) * 8, \ 496 start_kwi, offset, intf); \ 497 } \ 498 } \ 499 } while (0) 500 501 /* List LID, LTYPE, start offset from layer and length(in bytes) of 502 * packet header fields below. 503 * Example: Source IP is 4 bytes and starts at 12th byte of IP header 504 */ 505 NPC_SCAN_HDR(NPC_TOS, NPC_LID_LC, NPC_LT_LC_IP, 1, 1); 506 NPC_SCAN_HDR(NPC_IPFRAG_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 6, 1); 507 NPC_SCAN_HDR(NPC_SIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 12, 4); 508 NPC_SCAN_HDR(NPC_DIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 16, 4); 509 NPC_SCAN_HDR(NPC_IPFRAG_IPV6, NPC_LID_LC, NPC_LT_LC_IP6_EXT, 6, 1); 510 if (rvu->hw->cap.npc_hash_extract) { 511 if (mkex_hash->lid_lt_ld_hash_en[intf][lid][lt][0]) 512 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 4); 513 else 514 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16); 515 516 if (mkex_hash->lid_lt_ld_hash_en[intf][lid][lt][1]) 517 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 4); 518 else 519 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16); 520 } else { 521 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16); 522 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16); 523 } 524 525 NPC_SCAN_HDR(NPC_SPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 0, 2); 526 NPC_SCAN_HDR(NPC_DPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 2, 2); 527 NPC_SCAN_HDR(NPC_SPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 0, 2); 528 NPC_SCAN_HDR(NPC_DPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 2, 2); 529 NPC_SCAN_HDR(NPC_SPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 0, 2); 530 NPC_SCAN_HDR(NPC_DPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 2, 2); 531 NPC_SCAN_HDR(NPC_TYPE_ICMP, NPC_LID_LD, NPC_LT_LD_ICMP, 0, 1); 532 NPC_SCAN_HDR(NPC_CODE_ICMP, NPC_LID_LD, NPC_LT_LD_ICMP, 1, 1); 533 NPC_SCAN_HDR(NPC_ETYPE_ETHER, NPC_LID_LA, NPC_LT_LA_ETHER, 12, 2); 534 NPC_SCAN_HDR(NPC_ETYPE_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 4, 2); 535 NPC_SCAN_HDR(NPC_ETYPE_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 8, 2); 536 NPC_SCAN_HDR(NPC_VLAN_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 2, 2); 537 NPC_SCAN_HDR(NPC_VLAN_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 2, 2); 538 NPC_SCAN_HDR(NPC_VLAN_TAG3, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 6, 2); 539 NPC_SCAN_HDR(NPC_DMAC, NPC_LID_LA, la_ltype, la_start, 6); 540 541 NPC_SCAN_HDR(NPC_IPSEC_SPI, NPC_LID_LD, NPC_LT_LD_AH, 4, 4); 542 NPC_SCAN_HDR(NPC_IPSEC_SPI, NPC_LID_LE, NPC_LT_LE_ESP, 0, 4); 543 NPC_SCAN_HDR(NPC_MPLS1_LBTCBOS, NPC_LID_LC, NPC_LT_LC_MPLS, 0, 3); 544 NPC_SCAN_HDR(NPC_MPLS1_TTL, NPC_LID_LC, NPC_LT_LC_MPLS, 3, 1); 545 NPC_SCAN_HDR(NPC_MPLS2_LBTCBOS, NPC_LID_LC, NPC_LT_LC_MPLS, 4, 3); 546 NPC_SCAN_HDR(NPC_MPLS2_TTL, NPC_LID_LC, NPC_LT_LC_MPLS, 7, 1); 547 NPC_SCAN_HDR(NPC_MPLS3_LBTCBOS, NPC_LID_LC, NPC_LT_LC_MPLS, 8, 3); 548 NPC_SCAN_HDR(NPC_MPLS3_TTL, NPC_LID_LC, NPC_LT_LC_MPLS, 11, 1); 549 NPC_SCAN_HDR(NPC_MPLS4_LBTCBOS, NPC_LID_LC, NPC_LT_LC_MPLS, 12, 3); 550 NPC_SCAN_HDR(NPC_MPLS4_TTL, NPC_LID_LC, NPC_LT_LC_MPLS, 15, 1); 551 552 /* SMAC follows the DMAC(which is 6 bytes) */ 553 NPC_SCAN_HDR(NPC_SMAC, NPC_LID_LA, la_ltype, la_start + 6, 6); 554 /* PF_FUNC is 2 bytes at 0th byte of NPC_LT_LA_IH_NIX_ETHER */ 555 NPC_SCAN_HDR(NPC_PF_FUNC, NPC_LID_LA, NPC_LT_LA_IH_NIX_ETHER, 0, 2); 556 } 557 558 static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf) 559 { 560 struct npc_mcam *mcam = &rvu->hw->mcam; 561 u64 *features = &mcam->rx_features; 562 u64 proto_flags; 563 int hdr; 564 565 if (is_npc_intf_tx(intf)) 566 features = &mcam->tx_features; 567 568 for (hdr = NPC_DMAC; hdr < NPC_HEADER_FIELDS_MAX; hdr++) { 569 if (npc_check_field(rvu, blkaddr, hdr, intf)) 570 *features |= BIT_ULL(hdr); 571 } 572 573 proto_flags = BIT_ULL(NPC_SPORT_TCP) | BIT_ULL(NPC_SPORT_UDP) | 574 BIT_ULL(NPC_DPORT_TCP) | BIT_ULL(NPC_DPORT_UDP) | 575 BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP) | 576 BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP) | 577 BIT_ULL(NPC_TYPE_ICMP) | BIT_ULL(NPC_CODE_ICMP); 578 579 /* for tcp/udp/sctp corresponding layer type should be in the key */ 580 if (*features & proto_flags) { 581 if (!npc_check_field(rvu, blkaddr, NPC_LD, intf)) 582 *features &= ~proto_flags; 583 else 584 *features |= BIT_ULL(NPC_IPPROTO_TCP) | 585 BIT_ULL(NPC_IPPROTO_UDP) | 586 BIT_ULL(NPC_IPPROTO_SCTP) | 587 BIT_ULL(NPC_IPPROTO_ICMP); 588 } 589 590 /* for AH/ICMP/ICMPv6/, check if corresponding layer type is present in the key */ 591 if (npc_check_field(rvu, blkaddr, NPC_LD, intf)) { 592 *features |= BIT_ULL(NPC_IPPROTO_AH); 593 *features |= BIT_ULL(NPC_IPPROTO_ICMP); 594 *features |= BIT_ULL(NPC_IPPROTO_ICMP6); 595 } 596 597 /* for ESP, check if corresponding layer type is present in the key */ 598 if (npc_check_field(rvu, blkaddr, NPC_LE, intf)) 599 *features |= BIT_ULL(NPC_IPPROTO_ESP); 600 601 /* for vlan corresponding layer type should be in the key */ 602 if (*features & BIT_ULL(NPC_OUTER_VID)) 603 if (!npc_check_field(rvu, blkaddr, NPC_LB, intf)) 604 *features &= ~BIT_ULL(NPC_OUTER_VID); 605 606 /* Set SPI flag only if AH/ESP and IPSEC_SPI are in the key */ 607 if (npc_check_field(rvu, blkaddr, NPC_IPSEC_SPI, intf) && 608 (*features & (BIT_ULL(NPC_IPPROTO_ESP) | BIT_ULL(NPC_IPPROTO_AH)))) 609 *features |= BIT_ULL(NPC_IPSEC_SPI); 610 611 /* for vlan ethertypes corresponding layer type should be in the key */ 612 if (npc_check_field(rvu, blkaddr, NPC_LB, intf)) 613 *features |= BIT_ULL(NPC_VLAN_ETYPE_CTAG) | 614 BIT_ULL(NPC_VLAN_ETYPE_STAG); 615 616 /* for L2M/L2B/L3M/L3B, check if the type is present in the key */ 617 if (npc_check_field(rvu, blkaddr, NPC_LXMB, intf)) 618 *features |= BIT_ULL(NPC_LXMB); 619 620 for (hdr = NPC_MPLS1_LBTCBOS; hdr <= NPC_MPLS4_TTL; hdr++) { 621 if (npc_check_field(rvu, blkaddr, hdr, intf)) 622 *features |= BIT_ULL(hdr); 623 } 624 } 625 626 /* Scan key extraction profile and record how fields of our interest 627 * fill the key structure. Also verify Channel and DMAC exists in 628 * key and not overwritten by other header fields. 629 */ 630 static int npc_scan_kex(struct rvu *rvu, int blkaddr, u8 intf) 631 { 632 struct npc_mcam *mcam = &rvu->hw->mcam; 633 u8 lid, lt, ld, bitnr; 634 u64 cfg, masked_cfg; 635 u8 key_nibble = 0; 636 637 /* Scan and note how parse result is going to be in key. 638 * A bit set in PARSE_NIBBLE_ENA corresponds to a nibble from 639 * parse result in the key. The enabled nibbles from parse result 640 * will be concatenated in key. 641 */ 642 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf)); 643 masked_cfg = cfg & NPC_PARSE_NIBBLE; 644 for_each_set_bit(bitnr, (unsigned long *)&masked_cfg, 31) { 645 npc_scan_parse_result(mcam, bitnr, key_nibble, intf); 646 key_nibble++; 647 } 648 649 /* Ignore exact match bits for mcam entries except the first rule 650 * which is drop on hit. This first rule is configured explitcitly by 651 * exact match code. 652 */ 653 masked_cfg = cfg & NPC_EXACT_NIBBLE; 654 bitnr = NPC_EXACT_NIBBLE_START; 655 for_each_set_bit_from(bitnr, (unsigned long *)&masked_cfg, NPC_EXACT_NIBBLE_END + 1) { 656 npc_scan_exact_result(mcam, bitnr, key_nibble, intf); 657 key_nibble++; 658 } 659 660 /* Scan and note how layer data is going to be in key */ 661 for (lid = 0; lid < NPC_MAX_LID; lid++) { 662 for (lt = 0; lt < NPC_MAX_LT; lt++) { 663 for (ld = 0; ld < NPC_MAX_LD; ld++) { 664 cfg = rvu_read64(rvu, blkaddr, 665 NPC_AF_INTFX_LIDX_LTX_LDX_CFG 666 (intf, lid, lt, ld)); 667 if (!FIELD_GET(NPC_LDATA_EN, cfg)) 668 continue; 669 npc_scan_ldata(rvu, blkaddr, lid, lt, cfg, 670 intf); 671 } 672 } 673 } 674 675 return 0; 676 } 677 678 static int npc_scan_verify_kex(struct rvu *rvu, int blkaddr) 679 { 680 int err; 681 682 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_RX); 683 if (err) 684 return err; 685 686 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_TX); 687 if (err) 688 return err; 689 690 /* Channel is mandatory */ 691 if (!npc_is_field_present(rvu, NPC_CHAN, NIX_INTF_RX)) { 692 dev_err(rvu->dev, "Channel not present in Key\n"); 693 return -EINVAL; 694 } 695 /* check that none of the fields overwrite channel */ 696 if (npc_check_overlap(rvu, blkaddr, NPC_CHAN, 0, NIX_INTF_RX)) { 697 dev_err(rvu->dev, "Channel cannot be overwritten\n"); 698 return -EINVAL; 699 } 700 701 npc_set_features(rvu, blkaddr, NIX_INTF_TX); 702 npc_set_features(rvu, blkaddr, NIX_INTF_RX); 703 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_TX); 704 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_RX); 705 706 return 0; 707 } 708 709 int npc_flow_steering_init(struct rvu *rvu, int blkaddr) 710 { 711 struct npc_mcam *mcam = &rvu->hw->mcam; 712 713 INIT_LIST_HEAD(&mcam->mcam_rules); 714 715 return npc_scan_verify_kex(rvu, blkaddr); 716 } 717 718 static int npc_check_unsupported_flows(struct rvu *rvu, u64 features, u8 intf) 719 { 720 struct npc_mcam *mcam = &rvu->hw->mcam; 721 u64 *mcam_features = &mcam->rx_features; 722 u64 unsupported; 723 u8 bit; 724 725 if (is_npc_intf_tx(intf)) 726 mcam_features = &mcam->tx_features; 727 728 unsupported = (*mcam_features ^ features) & ~(*mcam_features); 729 if (unsupported) { 730 dev_warn(rvu->dev, "Unsupported flow(s):\n"); 731 for_each_set_bit(bit, (unsigned long *)&unsupported, 64) 732 dev_warn(rvu->dev, "%s ", npc_get_field_name(bit)); 733 return -EOPNOTSUPP; 734 } 735 736 return 0; 737 } 738 739 /* npc_update_entry - Based on the masks generated during 740 * the key scanning, updates the given entry with value and 741 * masks for the field of interest. Maximum 16 bytes of a packet 742 * header can be extracted by HW hence lo and hi are sufficient. 743 * When field bytes are less than or equal to 8 then hi should be 744 * 0 for value and mask. 745 * 746 * If exact match of value is required then mask should be all 1's. 747 * If any bits in mask are 0 then corresponding bits in value are 748 * dont care. 749 */ 750 void npc_update_entry(struct rvu *rvu, enum key_fields type, 751 struct mcam_entry *entry, u64 val_lo, 752 u64 val_hi, u64 mask_lo, u64 mask_hi, u8 intf) 753 { 754 struct npc_mcam *mcam = &rvu->hw->mcam; 755 struct mcam_entry dummy = { {0} }; 756 struct npc_key_field *field; 757 u64 kw1, kw2, kw3; 758 u8 shift; 759 int i; 760 761 field = &mcam->rx_key_fields[type]; 762 if (is_npc_intf_tx(intf)) 763 field = &mcam->tx_key_fields[type]; 764 765 if (!field->nr_kws) 766 return; 767 768 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 769 if (!field->kw_mask[i]) 770 continue; 771 /* place key value in kw[x] */ 772 shift = __ffs64(field->kw_mask[i]); 773 /* update entry value */ 774 kw1 = (val_lo << shift) & field->kw_mask[i]; 775 dummy.kw[i] = kw1; 776 /* update entry mask */ 777 kw1 = (mask_lo << shift) & field->kw_mask[i]; 778 dummy.kw_mask[i] = kw1; 779 780 if (field->nr_kws == 1) 781 break; 782 /* place remaining bits of key value in kw[x + 1] */ 783 if (field->nr_kws == 2) { 784 /* update entry value */ 785 kw2 = shift ? val_lo >> (64 - shift) : 0; 786 kw2 |= (val_hi << shift); 787 kw2 &= field->kw_mask[i + 1]; 788 dummy.kw[i + 1] = kw2; 789 /* update entry mask */ 790 kw2 = shift ? mask_lo >> (64 - shift) : 0; 791 kw2 |= (mask_hi << shift); 792 kw2 &= field->kw_mask[i + 1]; 793 dummy.kw_mask[i + 1] = kw2; 794 break; 795 } 796 /* place remaining bits of key value in kw[x + 1], kw[x + 2] */ 797 if (field->nr_kws == 3) { 798 /* update entry value */ 799 kw2 = shift ? val_lo >> (64 - shift) : 0; 800 kw2 |= (val_hi << shift); 801 kw2 &= field->kw_mask[i + 1]; 802 kw3 = shift ? val_hi >> (64 - shift) : 0; 803 kw3 &= field->kw_mask[i + 2]; 804 dummy.kw[i + 1] = kw2; 805 dummy.kw[i + 2] = kw3; 806 /* update entry mask */ 807 kw2 = shift ? mask_lo >> (64 - shift) : 0; 808 kw2 |= (mask_hi << shift); 809 kw2 &= field->kw_mask[i + 1]; 810 kw3 = shift ? mask_hi >> (64 - shift) : 0; 811 kw3 &= field->kw_mask[i + 2]; 812 dummy.kw_mask[i + 1] = kw2; 813 dummy.kw_mask[i + 2] = kw3; 814 break; 815 } 816 } 817 /* dummy is ready with values and masks for given key 818 * field now clear and update input entry with those 819 */ 820 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 821 if (!field->kw_mask[i]) 822 continue; 823 entry->kw[i] &= ~field->kw_mask[i]; 824 entry->kw_mask[i] &= ~field->kw_mask[i]; 825 826 entry->kw[i] |= dummy.kw[i]; 827 entry->kw_mask[i] |= dummy.kw_mask[i]; 828 } 829 } 830 831 static void npc_update_ipv6_flow(struct rvu *rvu, struct mcam_entry *entry, 832 u64 features, struct flow_msg *pkt, 833 struct flow_msg *mask, 834 struct rvu_npc_mcam_rule *output, u8 intf) 835 { 836 u32 src_ip[IPV6_WORDS], src_ip_mask[IPV6_WORDS]; 837 u32 dst_ip[IPV6_WORDS], dst_ip_mask[IPV6_WORDS]; 838 struct flow_msg *opkt = &output->packet; 839 struct flow_msg *omask = &output->mask; 840 u64 mask_lo, mask_hi; 841 u64 val_lo, val_hi; 842 843 /* For an ipv6 address fe80::2c68:63ff:fe5e:2d0a the packet 844 * values to be programmed in MCAM should as below: 845 * val_high: 0xfe80000000000000 846 * val_low: 0x2c6863fffe5e2d0a 847 */ 848 if (features & BIT_ULL(NPC_SIP_IPV6)) { 849 be32_to_cpu_array(src_ip_mask, mask->ip6src, IPV6_WORDS); 850 be32_to_cpu_array(src_ip, pkt->ip6src, IPV6_WORDS); 851 852 mask_hi = (u64)src_ip_mask[0] << 32 | src_ip_mask[1]; 853 mask_lo = (u64)src_ip_mask[2] << 32 | src_ip_mask[3]; 854 val_hi = (u64)src_ip[0] << 32 | src_ip[1]; 855 val_lo = (u64)src_ip[2] << 32 | src_ip[3]; 856 857 npc_update_entry(rvu, NPC_SIP_IPV6, entry, val_lo, val_hi, 858 mask_lo, mask_hi, intf); 859 memcpy(opkt->ip6src, pkt->ip6src, sizeof(opkt->ip6src)); 860 memcpy(omask->ip6src, mask->ip6src, sizeof(omask->ip6src)); 861 } 862 if (features & BIT_ULL(NPC_DIP_IPV6)) { 863 be32_to_cpu_array(dst_ip_mask, mask->ip6dst, IPV6_WORDS); 864 be32_to_cpu_array(dst_ip, pkt->ip6dst, IPV6_WORDS); 865 866 mask_hi = (u64)dst_ip_mask[0] << 32 | dst_ip_mask[1]; 867 mask_lo = (u64)dst_ip_mask[2] << 32 | dst_ip_mask[3]; 868 val_hi = (u64)dst_ip[0] << 32 | dst_ip[1]; 869 val_lo = (u64)dst_ip[2] << 32 | dst_ip[3]; 870 871 npc_update_entry(rvu, NPC_DIP_IPV6, entry, val_lo, val_hi, 872 mask_lo, mask_hi, intf); 873 memcpy(opkt->ip6dst, pkt->ip6dst, sizeof(opkt->ip6dst)); 874 memcpy(omask->ip6dst, mask->ip6dst, sizeof(omask->ip6dst)); 875 } 876 } 877 878 static void npc_update_vlan_features(struct rvu *rvu, struct mcam_entry *entry, 879 u64 features, u8 intf) 880 { 881 bool ctag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_CTAG)); 882 bool stag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_STAG)); 883 bool vid = !!(features & BIT_ULL(NPC_OUTER_VID)); 884 885 /* If only VLAN id is given then always match outer VLAN id */ 886 if (vid && !ctag && !stag) { 887 npc_update_entry(rvu, NPC_LB, entry, 888 NPC_LT_LB_STAG_QINQ | NPC_LT_LB_CTAG, 0, 889 NPC_LT_LB_STAG_QINQ & NPC_LT_LB_CTAG, 0, intf); 890 return; 891 } 892 if (ctag) 893 npc_update_entry(rvu, NPC_LB, entry, NPC_LT_LB_CTAG, 0, 894 ~0ULL, 0, intf); 895 if (stag) 896 npc_update_entry(rvu, NPC_LB, entry, NPC_LT_LB_STAG_QINQ, 0, 897 ~0ULL, 0, intf); 898 } 899 900 static void npc_update_flow(struct rvu *rvu, struct mcam_entry *entry, 901 u64 features, struct flow_msg *pkt, 902 struct flow_msg *mask, 903 struct rvu_npc_mcam_rule *output, u8 intf, 904 int blkaddr) 905 { 906 u64 dmac_mask = ether_addr_to_u64(mask->dmac); 907 u64 smac_mask = ether_addr_to_u64(mask->smac); 908 u64 dmac_val = ether_addr_to_u64(pkt->dmac); 909 u64 smac_val = ether_addr_to_u64(pkt->smac); 910 struct flow_msg *opkt = &output->packet; 911 struct flow_msg *omask = &output->mask; 912 913 if (!features) 914 return; 915 916 /* For tcp/udp/sctp LTYPE should be present in entry */ 917 if (features & BIT_ULL(NPC_IPPROTO_TCP)) 918 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_TCP, 919 0, ~0ULL, 0, intf); 920 if (features & BIT_ULL(NPC_IPPROTO_UDP)) 921 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_UDP, 922 0, ~0ULL, 0, intf); 923 if (features & BIT_ULL(NPC_IPPROTO_SCTP)) 924 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_SCTP, 925 0, ~0ULL, 0, intf); 926 if (features & BIT_ULL(NPC_IPPROTO_ICMP)) 927 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_ICMP, 928 0, ~0ULL, 0, intf); 929 if (features & BIT_ULL(NPC_IPPROTO_ICMP6)) 930 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_ICMP6, 931 0, ~0ULL, 0, intf); 932 933 /* For AH, LTYPE should be present in entry */ 934 if (features & BIT_ULL(NPC_IPPROTO_AH)) 935 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_AH, 936 0, ~0ULL, 0, intf); 937 /* For ESP, LTYPE should be present in entry */ 938 if (features & BIT_ULL(NPC_IPPROTO_ESP)) 939 npc_update_entry(rvu, NPC_LE, entry, NPC_LT_LE_ESP, 940 0, ~0ULL, 0, intf); 941 942 if (features & BIT_ULL(NPC_LXMB)) { 943 output->lxmb = is_broadcast_ether_addr(pkt->dmac) ? 2 : 1; 944 npc_update_entry(rvu, NPC_LXMB, entry, output->lxmb, 0, 945 output->lxmb, 0, intf); 946 } 947 #define NPC_WRITE_FLOW(field, member, val_lo, val_hi, mask_lo, mask_hi) \ 948 do { \ 949 if (features & BIT_ULL((field))) { \ 950 npc_update_entry(rvu, (field), entry, (val_lo), (val_hi), \ 951 (mask_lo), (mask_hi), intf); \ 952 memcpy(&opkt->member, &pkt->member, sizeof(pkt->member)); \ 953 memcpy(&omask->member, &mask->member, sizeof(mask->member)); \ 954 } \ 955 } while (0) 956 957 NPC_WRITE_FLOW(NPC_DMAC, dmac, dmac_val, 0, dmac_mask, 0); 958 959 NPC_WRITE_FLOW(NPC_SMAC, smac, smac_val, 0, smac_mask, 0); 960 NPC_WRITE_FLOW(NPC_ETYPE, etype, ntohs(pkt->etype), 0, 961 ntohs(mask->etype), 0); 962 NPC_WRITE_FLOW(NPC_TOS, tos, pkt->tos, 0, mask->tos, 0); 963 NPC_WRITE_FLOW(NPC_IPFRAG_IPV4, ip_flag, pkt->ip_flag, 0, 964 mask->ip_flag, 0); 965 NPC_WRITE_FLOW(NPC_SIP_IPV4, ip4src, ntohl(pkt->ip4src), 0, 966 ntohl(mask->ip4src), 0); 967 NPC_WRITE_FLOW(NPC_DIP_IPV4, ip4dst, ntohl(pkt->ip4dst), 0, 968 ntohl(mask->ip4dst), 0); 969 NPC_WRITE_FLOW(NPC_SPORT_TCP, sport, ntohs(pkt->sport), 0, 970 ntohs(mask->sport), 0); 971 NPC_WRITE_FLOW(NPC_SPORT_UDP, sport, ntohs(pkt->sport), 0, 972 ntohs(mask->sport), 0); 973 NPC_WRITE_FLOW(NPC_DPORT_TCP, dport, ntohs(pkt->dport), 0, 974 ntohs(mask->dport), 0); 975 NPC_WRITE_FLOW(NPC_DPORT_UDP, dport, ntohs(pkt->dport), 0, 976 ntohs(mask->dport), 0); 977 NPC_WRITE_FLOW(NPC_SPORT_SCTP, sport, ntohs(pkt->sport), 0, 978 ntohs(mask->sport), 0); 979 NPC_WRITE_FLOW(NPC_DPORT_SCTP, dport, ntohs(pkt->dport), 0, 980 ntohs(mask->dport), 0); 981 NPC_WRITE_FLOW(NPC_TYPE_ICMP, icmp_type, pkt->icmp_type, 0, 982 mask->icmp_type, 0); 983 NPC_WRITE_FLOW(NPC_CODE_ICMP, icmp_code, pkt->icmp_code, 0, 984 mask->icmp_code, 0); 985 986 NPC_WRITE_FLOW(NPC_IPSEC_SPI, spi, ntohl(pkt->spi), 0, 987 ntohl(mask->spi), 0); 988 989 NPC_WRITE_FLOW(NPC_OUTER_VID, vlan_tci, ntohs(pkt->vlan_tci), 0, 990 ntohs(mask->vlan_tci), 0); 991 NPC_WRITE_FLOW(NPC_INNER_VID, vlan_itci, ntohs(pkt->vlan_itci), 0, 992 ntohs(mask->vlan_itci), 0); 993 994 NPC_WRITE_FLOW(NPC_MPLS1_LBTCBOS, mpls_lse, 995 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 996 pkt->mpls_lse[0]), 0, 997 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 998 mask->mpls_lse[0]), 0); 999 NPC_WRITE_FLOW(NPC_MPLS1_TTL, mpls_lse, 1000 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1001 pkt->mpls_lse[0]), 0, 1002 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1003 mask->mpls_lse[0]), 0); 1004 NPC_WRITE_FLOW(NPC_MPLS2_LBTCBOS, mpls_lse, 1005 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1006 pkt->mpls_lse[1]), 0, 1007 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1008 mask->mpls_lse[1]), 0); 1009 NPC_WRITE_FLOW(NPC_MPLS2_TTL, mpls_lse, 1010 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1011 pkt->mpls_lse[1]), 0, 1012 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1013 mask->mpls_lse[1]), 0); 1014 NPC_WRITE_FLOW(NPC_MPLS3_LBTCBOS, mpls_lse, 1015 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1016 pkt->mpls_lse[2]), 0, 1017 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1018 mask->mpls_lse[2]), 0); 1019 NPC_WRITE_FLOW(NPC_MPLS3_TTL, mpls_lse, 1020 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1021 pkt->mpls_lse[2]), 0, 1022 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1023 mask->mpls_lse[2]), 0); 1024 NPC_WRITE_FLOW(NPC_MPLS4_LBTCBOS, mpls_lse, 1025 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1026 pkt->mpls_lse[3]), 0, 1027 FIELD_GET(OTX2_FLOWER_MASK_MPLS_NON_TTL, 1028 mask->mpls_lse[3]), 0); 1029 NPC_WRITE_FLOW(NPC_MPLS4_TTL, mpls_lse, 1030 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1031 pkt->mpls_lse[3]), 0, 1032 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, 1033 mask->mpls_lse[3]), 0); 1034 1035 NPC_WRITE_FLOW(NPC_IPFRAG_IPV6, next_header, pkt->next_header, 0, 1036 mask->next_header, 0); 1037 npc_update_ipv6_flow(rvu, entry, features, pkt, mask, output, intf); 1038 npc_update_vlan_features(rvu, entry, features, intf); 1039 1040 npc_update_field_hash(rvu, intf, entry, blkaddr, features, 1041 pkt, mask, opkt, omask); 1042 } 1043 1044 static struct rvu_npc_mcam_rule *rvu_mcam_find_rule(struct npc_mcam *mcam, u16 entry) 1045 { 1046 struct rvu_npc_mcam_rule *iter; 1047 1048 mutex_lock(&mcam->lock); 1049 list_for_each_entry(iter, &mcam->mcam_rules, list) { 1050 if (iter->entry == entry) { 1051 mutex_unlock(&mcam->lock); 1052 return iter; 1053 } 1054 } 1055 mutex_unlock(&mcam->lock); 1056 1057 return NULL; 1058 } 1059 1060 static void rvu_mcam_add_rule(struct npc_mcam *mcam, 1061 struct rvu_npc_mcam_rule *rule) 1062 { 1063 struct list_head *head = &mcam->mcam_rules; 1064 struct rvu_npc_mcam_rule *iter; 1065 1066 mutex_lock(&mcam->lock); 1067 list_for_each_entry(iter, &mcam->mcam_rules, list) { 1068 if (iter->entry > rule->entry) 1069 break; 1070 head = &iter->list; 1071 } 1072 1073 list_add(&rule->list, head); 1074 mutex_unlock(&mcam->lock); 1075 } 1076 1077 static void rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, 1078 struct rvu_npc_mcam_rule *rule) 1079 { 1080 struct npc_mcam_oper_counter_req free_req = { 0 }; 1081 struct msg_rsp free_rsp; 1082 1083 if (!rule->has_cntr) 1084 return; 1085 1086 free_req.hdr.pcifunc = pcifunc; 1087 free_req.cntr = rule->cntr; 1088 1089 rvu_mbox_handler_npc_mcam_free_counter(rvu, &free_req, &free_rsp); 1090 rule->has_cntr = false; 1091 } 1092 1093 static void rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, 1094 struct rvu_npc_mcam_rule *rule, 1095 struct npc_install_flow_rsp *rsp) 1096 { 1097 struct npc_mcam_alloc_counter_req cntr_req = { 0 }; 1098 struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 }; 1099 int err; 1100 1101 cntr_req.hdr.pcifunc = pcifunc; 1102 cntr_req.contig = true; 1103 cntr_req.count = 1; 1104 1105 /* we try to allocate a counter to track the stats of this 1106 * rule. If counter could not be allocated then proceed 1107 * without counter because counters are limited than entries. 1108 */ 1109 err = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, 1110 &cntr_rsp); 1111 if (!err && cntr_rsp.count) { 1112 rule->cntr = cntr_rsp.cntr; 1113 rule->has_cntr = true; 1114 rsp->counter = rule->cntr; 1115 } else { 1116 rsp->counter = err; 1117 } 1118 } 1119 1120 static int npc_mcast_update_action_index(struct rvu *rvu, struct npc_install_flow_req *req, 1121 u64 op, void *action) 1122 { 1123 int mce_index; 1124 1125 /* If a PF/VF is installing a multicast rule then it is expected 1126 * that the PF/VF should have created a group for the multicast/mirror 1127 * list. Otherwise reject the configuration. 1128 * During this scenario, req->index is set as multicast/mirror 1129 * group index. 1130 */ 1131 if (req->hdr.pcifunc && 1132 (op == NIX_RX_ACTIONOP_MCAST || op == NIX_TX_ACTIONOP_MCAST)) { 1133 mce_index = rvu_nix_mcast_get_mce_index(rvu, req->hdr.pcifunc, req->index); 1134 if (mce_index < 0) 1135 return mce_index; 1136 1137 if (op == NIX_RX_ACTIONOP_MCAST) 1138 ((struct nix_rx_action *)action)->index = mce_index; 1139 else 1140 ((struct nix_tx_action *)action)->index = mce_index; 1141 } 1142 1143 return 0; 1144 } 1145 1146 static int npc_update_rx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf, 1147 struct mcam_entry *entry, 1148 struct npc_install_flow_req *req, 1149 u16 target, bool pf_set_vfs_mac) 1150 { 1151 struct rvu_switch *rswitch = &rvu->rswitch; 1152 struct nix_rx_action action; 1153 int ret; 1154 1155 if (rswitch->mode == DEVLINK_ESWITCH_MODE_SWITCHDEV && pf_set_vfs_mac) 1156 req->chan_mask = 0x0; /* Do not care channel */ 1157 1158 npc_update_entry(rvu, NPC_CHAN, entry, req->channel, 0, req->chan_mask, 1159 0, NIX_INTF_RX); 1160 1161 *(u64 *)&action = 0x00; 1162 action.pf_func = target; 1163 action.op = req->op; 1164 action.index = req->index; 1165 1166 ret = npc_mcast_update_action_index(rvu, req, action.op, (void *)&action); 1167 if (ret) 1168 return ret; 1169 1170 action.match_id = req->match_id; 1171 action.flow_key_alg = req->flow_key_alg; 1172 1173 if (req->op == NIX_RX_ACTION_DEFAULT) { 1174 if (pfvf->def_ucast_rule) { 1175 action = pfvf->def_ucast_rule->rx_action; 1176 } else { 1177 /* For profiles which do not extract DMAC, the default 1178 * unicast entry is unused. Hence modify action for the 1179 * requests which use same action as default unicast 1180 * entry 1181 */ 1182 *(u64 *)&action = 0; 1183 action.pf_func = target; 1184 action.op = NIX_RX_ACTIONOP_UCAST; 1185 } 1186 } 1187 1188 entry->action = *(u64 *)&action; 1189 1190 /* VTAG0 starts at 0th byte of LID_B. 1191 * VTAG1 starts at 4th byte of LID_B. 1192 */ 1193 entry->vtag_action = FIELD_PREP(RX_VTAG0_VALID_BIT, req->vtag0_valid) | 1194 FIELD_PREP(RX_VTAG0_TYPE_MASK, req->vtag0_type) | 1195 FIELD_PREP(RX_VTAG0_LID_MASK, NPC_LID_LB) | 1196 FIELD_PREP(RX_VTAG0_RELPTR_MASK, 0) | 1197 FIELD_PREP(RX_VTAG1_VALID_BIT, req->vtag1_valid) | 1198 FIELD_PREP(RX_VTAG1_TYPE_MASK, req->vtag1_type) | 1199 FIELD_PREP(RX_VTAG1_LID_MASK, NPC_LID_LB) | 1200 FIELD_PREP(RX_VTAG1_RELPTR_MASK, 4); 1201 1202 return 0; 1203 } 1204 1205 static int npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf, 1206 struct mcam_entry *entry, 1207 struct npc_install_flow_req *req, u16 target) 1208 { 1209 struct nix_tx_action action; 1210 u64 mask = ~0ULL; 1211 int ret; 1212 1213 /* If AF is installing then do not care about 1214 * PF_FUNC in Send Descriptor 1215 */ 1216 if (is_pffunc_af(req->hdr.pcifunc)) 1217 mask = 0; 1218 1219 npc_update_entry(rvu, NPC_PF_FUNC, entry, (__force u16)htons(target), 1220 0, mask, 0, NIX_INTF_TX); 1221 1222 *(u64 *)&action = 0x00; 1223 action.op = req->op; 1224 action.index = req->index; 1225 1226 ret = npc_mcast_update_action_index(rvu, req, action.op, (void *)&action); 1227 if (ret) 1228 return ret; 1229 1230 action.match_id = req->match_id; 1231 1232 entry->action = *(u64 *)&action; 1233 1234 /* VTAG0 starts at 0th byte of LID_B. 1235 * VTAG1 starts at 4th byte of LID_B. 1236 */ 1237 entry->vtag_action = FIELD_PREP(TX_VTAG0_DEF_MASK, req->vtag0_def) | 1238 FIELD_PREP(TX_VTAG0_OP_MASK, req->vtag0_op) | 1239 FIELD_PREP(TX_VTAG0_LID_MASK, NPC_LID_LA) | 1240 FIELD_PREP(TX_VTAG0_RELPTR_MASK, 20) | 1241 FIELD_PREP(TX_VTAG1_DEF_MASK, req->vtag1_def) | 1242 FIELD_PREP(TX_VTAG1_OP_MASK, req->vtag1_op) | 1243 FIELD_PREP(TX_VTAG1_LID_MASK, NPC_LID_LA) | 1244 FIELD_PREP(TX_VTAG1_RELPTR_MASK, 24); 1245 1246 return 0; 1247 } 1248 1249 static int npc_install_flow(struct rvu *rvu, int blkaddr, u16 target, 1250 int nixlf, struct rvu_pfvf *pfvf, 1251 struct npc_install_flow_req *req, 1252 struct npc_install_flow_rsp *rsp, bool enable, 1253 bool pf_set_vfs_mac) 1254 { 1255 struct rvu_npc_mcam_rule *def_ucast_rule = pfvf->def_ucast_rule; 1256 u64 features, installed_features, missing_features = 0; 1257 struct npc_mcam_write_entry_req write_req = { 0 }; 1258 struct npc_mcam *mcam = &rvu->hw->mcam; 1259 struct rvu_npc_mcam_rule dummy = { 0 }; 1260 struct rvu_npc_mcam_rule *rule; 1261 u16 owner = req->hdr.pcifunc; 1262 struct msg_rsp write_rsp; 1263 struct mcam_entry *entry; 1264 bool new = false; 1265 u16 entry_index; 1266 int err; 1267 1268 installed_features = req->features; 1269 features = req->features; 1270 entry = &write_req.entry_data; 1271 entry_index = req->entry; 1272 1273 npc_update_flow(rvu, entry, features, &req->packet, &req->mask, &dummy, 1274 req->intf, blkaddr); 1275 1276 if (is_npc_intf_rx(req->intf)) { 1277 err = npc_update_rx_entry(rvu, pfvf, entry, req, target, pf_set_vfs_mac); 1278 if (err) 1279 return err; 1280 } else { 1281 err = npc_update_tx_entry(rvu, pfvf, entry, req, target); 1282 if (err) 1283 return err; 1284 } 1285 1286 /* Default unicast rules do not exist for TX */ 1287 if (is_npc_intf_tx(req->intf)) 1288 goto find_rule; 1289 1290 if (req->default_rule) { 1291 entry_index = npc_get_nixlf_mcam_index(mcam, target, nixlf, 1292 NIXLF_UCAST_ENTRY); 1293 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, entry_index); 1294 } 1295 1296 /* update mcam entry with default unicast rule attributes */ 1297 if (def_ucast_rule && (req->default_rule && req->append)) { 1298 missing_features = (def_ucast_rule->features ^ features) & 1299 def_ucast_rule->features; 1300 if (missing_features) 1301 npc_update_flow(rvu, entry, missing_features, 1302 &def_ucast_rule->packet, 1303 &def_ucast_rule->mask, 1304 &dummy, req->intf, 1305 blkaddr); 1306 installed_features = req->features | missing_features; 1307 } 1308 1309 find_rule: 1310 rule = rvu_mcam_find_rule(mcam, entry_index); 1311 if (!rule) { 1312 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 1313 if (!rule) 1314 return -ENOMEM; 1315 new = true; 1316 } 1317 1318 /* allocate new counter if rule has no counter */ 1319 if (!req->default_rule && req->set_cntr && !rule->has_cntr) 1320 rvu_mcam_add_counter_to_rule(rvu, owner, rule, rsp); 1321 1322 /* if user wants to delete an existing counter for a rule then 1323 * free the counter 1324 */ 1325 if (!req->set_cntr && rule->has_cntr) 1326 rvu_mcam_remove_counter_from_rule(rvu, owner, rule); 1327 1328 write_req.hdr.pcifunc = owner; 1329 1330 /* AF owns the default rules so change the owner just to relax 1331 * the checks in rvu_mbox_handler_npc_mcam_write_entry 1332 */ 1333 if (req->default_rule) 1334 write_req.hdr.pcifunc = 0; 1335 1336 write_req.entry = entry_index; 1337 write_req.intf = req->intf; 1338 write_req.enable_entry = (u8)enable; 1339 /* if counter is available then clear and use it */ 1340 if (req->set_cntr && rule->has_cntr) { 1341 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(rule->cntr), req->cntr_val); 1342 write_req.set_cntr = 1; 1343 write_req.cntr = rule->cntr; 1344 } 1345 1346 /* update rule */ 1347 memcpy(&rule->packet, &dummy.packet, sizeof(rule->packet)); 1348 memcpy(&rule->mask, &dummy.mask, sizeof(rule->mask)); 1349 rule->entry = entry_index; 1350 memcpy(&rule->rx_action, &entry->action, sizeof(struct nix_rx_action)); 1351 if (is_npc_intf_tx(req->intf)) 1352 memcpy(&rule->tx_action, &entry->action, 1353 sizeof(struct nix_tx_action)); 1354 rule->vtag_action = entry->vtag_action; 1355 rule->features = installed_features; 1356 rule->default_rule = req->default_rule; 1357 rule->owner = owner; 1358 rule->enable = enable; 1359 rule->chan_mask = write_req.entry_data.kw_mask[0] & NPC_KEX_CHAN_MASK; 1360 rule->chan = write_req.entry_data.kw[0] & NPC_KEX_CHAN_MASK; 1361 rule->chan &= rule->chan_mask; 1362 rule->lxmb = dummy.lxmb; 1363 if (is_npc_intf_tx(req->intf)) 1364 rule->intf = pfvf->nix_tx_intf; 1365 else 1366 rule->intf = pfvf->nix_rx_intf; 1367 1368 if (new) 1369 rvu_mcam_add_rule(mcam, rule); 1370 if (req->default_rule) 1371 pfvf->def_ucast_rule = rule; 1372 1373 /* write to mcam entry registers */ 1374 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, 1375 &write_rsp); 1376 if (err) { 1377 rvu_mcam_remove_counter_from_rule(rvu, owner, rule); 1378 if (new) { 1379 list_del(&rule->list); 1380 kfree(rule); 1381 } 1382 return err; 1383 } 1384 1385 /* VF's MAC address is being changed via PF */ 1386 if (pf_set_vfs_mac) { 1387 ether_addr_copy(pfvf->default_mac, req->packet.dmac); 1388 ether_addr_copy(pfvf->mac_addr, req->packet.dmac); 1389 set_bit(PF_SET_VF_MAC, &pfvf->flags); 1390 } 1391 1392 if (test_bit(PF_SET_VF_CFG, &pfvf->flags) && 1393 req->vtag0_type == NIX_AF_LFX_RX_VTAG_TYPE7) 1394 rule->vfvlan_cfg = true; 1395 1396 if (is_npc_intf_rx(req->intf) && req->match_id && 1397 (req->op == NIX_RX_ACTIONOP_UCAST || req->op == NIX_RX_ACTIONOP_RSS)) 1398 return rvu_nix_setup_ratelimit_aggr(rvu, req->hdr.pcifunc, 1399 req->index, req->match_id); 1400 1401 if (owner && req->op == NIX_RX_ACTIONOP_MCAST) 1402 return rvu_nix_mcast_update_mcam_entry(rvu, req->hdr.pcifunc, 1403 req->index, entry_index); 1404 1405 return 0; 1406 } 1407 1408 int rvu_mbox_handler_npc_install_flow(struct rvu *rvu, 1409 struct npc_install_flow_req *req, 1410 struct npc_install_flow_rsp *rsp) 1411 { 1412 bool from_vf = !!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK); 1413 struct rvu_switch *rswitch = &rvu->rswitch; 1414 int blkaddr, nixlf, err; 1415 struct rvu_pfvf *pfvf; 1416 bool pf_set_vfs_mac = false; 1417 bool enable = true; 1418 u16 target; 1419 1420 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1421 if (blkaddr < 0) { 1422 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 1423 return NPC_MCAM_INVALID_REQ; 1424 } 1425 1426 if (!is_npc_interface_valid(rvu, req->intf)) 1427 return NPC_FLOW_INTF_INVALID; 1428 1429 /* If DMAC is not extracted in MKEX, rules installed by AF 1430 * can rely on L2MB bit set by hardware protocol checker for 1431 * broadcast and multicast addresses. 1432 */ 1433 if (npc_check_field(rvu, blkaddr, NPC_DMAC, req->intf)) 1434 goto process_flow; 1435 1436 if (is_pffunc_af(req->hdr.pcifunc) && 1437 req->features & BIT_ULL(NPC_DMAC)) { 1438 if (is_unicast_ether_addr(req->packet.dmac)) { 1439 dev_warn(rvu->dev, 1440 "%s: mkex profile does not support ucast flow\n", 1441 __func__); 1442 return NPC_FLOW_NOT_SUPPORTED; 1443 } 1444 1445 if (!npc_is_field_present(rvu, NPC_LXMB, req->intf)) { 1446 dev_warn(rvu->dev, 1447 "%s: mkex profile does not support bcast/mcast flow", 1448 __func__); 1449 return NPC_FLOW_NOT_SUPPORTED; 1450 } 1451 1452 /* Modify feature to use LXMB instead of DMAC */ 1453 req->features &= ~BIT_ULL(NPC_DMAC); 1454 req->features |= BIT_ULL(NPC_LXMB); 1455 } 1456 1457 process_flow: 1458 if (from_vf && req->default_rule) 1459 return NPC_FLOW_VF_PERM_DENIED; 1460 1461 /* Each PF/VF info is maintained in struct rvu_pfvf. 1462 * rvu_pfvf for the target PF/VF needs to be retrieved 1463 * hence modify pcifunc accordingly. 1464 */ 1465 1466 /* AF installing for a PF/VF */ 1467 if (!req->hdr.pcifunc) 1468 target = req->vf; 1469 /* PF installing for its VF */ 1470 else if (!from_vf && req->vf) { 1471 target = (req->hdr.pcifunc & ~RVU_PFVF_FUNC_MASK) | req->vf; 1472 pf_set_vfs_mac = req->default_rule && 1473 (req->features & BIT_ULL(NPC_DMAC)); 1474 } 1475 /* msg received from PF/VF */ 1476 else 1477 target = req->hdr.pcifunc; 1478 1479 /* ignore chan_mask in case pf func is not AF, revisit later */ 1480 if (!is_pffunc_af(req->hdr.pcifunc)) 1481 req->chan_mask = 0xFFF; 1482 1483 err = npc_check_unsupported_flows(rvu, req->features, req->intf); 1484 if (err) 1485 return NPC_FLOW_NOT_SUPPORTED; 1486 1487 pfvf = rvu_get_pfvf(rvu, target); 1488 1489 /* PF installing for its VF */ 1490 if (req->hdr.pcifunc && !from_vf && req->vf) 1491 set_bit(PF_SET_VF_CFG, &pfvf->flags); 1492 1493 /* update req destination mac addr */ 1494 if ((req->features & BIT_ULL(NPC_DMAC)) && is_npc_intf_rx(req->intf) && 1495 is_zero_ether_addr(req->packet.dmac)) { 1496 ether_addr_copy(req->packet.dmac, pfvf->mac_addr); 1497 eth_broadcast_addr((u8 *)&req->mask.dmac); 1498 } 1499 1500 /* Proceed if NIXLF is attached or not for TX rules */ 1501 err = nix_get_nixlf(rvu, target, &nixlf, NULL); 1502 if (err && is_npc_intf_rx(req->intf) && !pf_set_vfs_mac) 1503 return NPC_FLOW_NO_NIXLF; 1504 1505 /* don't enable rule when nixlf not attached or initialized */ 1506 if (!(is_nixlf_attached(rvu, target) && 1507 test_bit(NIXLF_INITIALIZED, &pfvf->flags))) 1508 enable = false; 1509 1510 /* Packets reaching NPC in Tx path implies that a 1511 * NIXLF is properly setup and transmitting. 1512 * Hence rules can be enabled for Tx. 1513 */ 1514 if (is_npc_intf_tx(req->intf)) 1515 enable = true; 1516 1517 /* Do not allow requests from uninitialized VFs */ 1518 if (from_vf && !enable) 1519 return NPC_FLOW_VF_NOT_INIT; 1520 1521 /* PF sets VF mac & VF NIXLF is not attached, update the mac addr */ 1522 if (pf_set_vfs_mac && !enable) { 1523 ether_addr_copy(pfvf->default_mac, req->packet.dmac); 1524 ether_addr_copy(pfvf->mac_addr, req->packet.dmac); 1525 set_bit(PF_SET_VF_MAC, &pfvf->flags); 1526 return 0; 1527 } 1528 1529 mutex_lock(&rswitch->switch_lock); 1530 err = npc_install_flow(rvu, blkaddr, target, nixlf, pfvf, 1531 req, rsp, enable, pf_set_vfs_mac); 1532 mutex_unlock(&rswitch->switch_lock); 1533 1534 return err; 1535 } 1536 1537 static int npc_delete_flow(struct rvu *rvu, struct rvu_npc_mcam_rule *rule, 1538 u16 pcifunc) 1539 { 1540 struct npc_mcam_ena_dis_entry_req dis_req = { 0 }; 1541 struct msg_rsp dis_rsp; 1542 1543 if (rule->default_rule) 1544 return 0; 1545 1546 if (rule->has_cntr) 1547 rvu_mcam_remove_counter_from_rule(rvu, pcifunc, rule); 1548 1549 dis_req.hdr.pcifunc = pcifunc; 1550 dis_req.entry = rule->entry; 1551 1552 list_del(&rule->list); 1553 kfree(rule); 1554 1555 return rvu_mbox_handler_npc_mcam_dis_entry(rvu, &dis_req, &dis_rsp); 1556 } 1557 1558 int rvu_mbox_handler_npc_delete_flow(struct rvu *rvu, 1559 struct npc_delete_flow_req *req, 1560 struct npc_delete_flow_rsp *rsp) 1561 { 1562 struct npc_mcam *mcam = &rvu->hw->mcam; 1563 struct rvu_npc_mcam_rule *iter, *tmp; 1564 u16 pcifunc = req->hdr.pcifunc; 1565 struct list_head del_list; 1566 int blkaddr; 1567 1568 INIT_LIST_HEAD(&del_list); 1569 1570 mutex_lock(&mcam->lock); 1571 list_for_each_entry_safe(iter, tmp, &mcam->mcam_rules, list) { 1572 if (iter->owner == pcifunc) { 1573 /* All rules */ 1574 if (req->all) { 1575 list_move_tail(&iter->list, &del_list); 1576 /* Range of rules */ 1577 } else if (req->end && iter->entry >= req->start && 1578 iter->entry <= req->end) { 1579 list_move_tail(&iter->list, &del_list); 1580 /* single rule */ 1581 } else if (req->entry == iter->entry) { 1582 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1583 if (blkaddr) 1584 rsp->cntr_val = rvu_read64(rvu, blkaddr, 1585 NPC_AF_MATCH_STATX(iter->cntr)); 1586 list_move_tail(&iter->list, &del_list); 1587 break; 1588 } 1589 } 1590 } 1591 mutex_unlock(&mcam->lock); 1592 1593 list_for_each_entry_safe(iter, tmp, &del_list, list) { 1594 u16 entry = iter->entry; 1595 1596 /* clear the mcam entry target pcifunc */ 1597 mcam->entry2target_pffunc[entry] = 0x0; 1598 if (npc_delete_flow(rvu, iter, pcifunc)) 1599 dev_err(rvu->dev, "rule deletion failed for entry:%u", 1600 entry); 1601 } 1602 1603 return 0; 1604 } 1605 1606 static int npc_update_dmac_value(struct rvu *rvu, int npcblkaddr, 1607 struct rvu_npc_mcam_rule *rule, 1608 struct rvu_pfvf *pfvf) 1609 { 1610 struct npc_mcam_write_entry_req write_req = { 0 }; 1611 struct mcam_entry *entry = &write_req.entry_data; 1612 struct npc_mcam *mcam = &rvu->hw->mcam; 1613 struct msg_rsp rsp; 1614 u8 intf, enable; 1615 int err; 1616 1617 ether_addr_copy(rule->packet.dmac, pfvf->mac_addr); 1618 1619 npc_read_mcam_entry(rvu, mcam, npcblkaddr, rule->entry, 1620 entry, &intf, &enable); 1621 1622 npc_update_entry(rvu, NPC_DMAC, entry, 1623 ether_addr_to_u64(pfvf->mac_addr), 0, 1624 0xffffffffffffull, 0, intf); 1625 1626 write_req.hdr.pcifunc = rule->owner; 1627 write_req.entry = rule->entry; 1628 write_req.intf = pfvf->nix_rx_intf; 1629 1630 mutex_unlock(&mcam->lock); 1631 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, &rsp); 1632 mutex_lock(&mcam->lock); 1633 1634 return err; 1635 } 1636 1637 void npc_mcam_enable_flows(struct rvu *rvu, u16 target) 1638 { 1639 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, target); 1640 struct rvu_npc_mcam_rule *def_ucast_rule; 1641 struct npc_mcam *mcam = &rvu->hw->mcam; 1642 struct rvu_npc_mcam_rule *rule; 1643 int blkaddr, bank, index; 1644 u64 def_action; 1645 1646 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1647 if (blkaddr < 0) 1648 return; 1649 1650 def_ucast_rule = pfvf->def_ucast_rule; 1651 1652 mutex_lock(&mcam->lock); 1653 list_for_each_entry(rule, &mcam->mcam_rules, list) { 1654 if (is_npc_intf_rx(rule->intf) && 1655 rule->rx_action.pf_func == target && !rule->enable) { 1656 if (rule->default_rule) { 1657 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1658 rule->entry, true); 1659 rule->enable = true; 1660 continue; 1661 } 1662 1663 if (rule->vfvlan_cfg) 1664 npc_update_dmac_value(rvu, blkaddr, rule, pfvf); 1665 1666 if (rule->rx_action.op == NIX_RX_ACTION_DEFAULT) { 1667 if (!def_ucast_rule) 1668 continue; 1669 /* Use default unicast entry action */ 1670 rule->rx_action = def_ucast_rule->rx_action; 1671 def_action = *(u64 *)&def_ucast_rule->rx_action; 1672 bank = npc_get_bank(mcam, rule->entry); 1673 rvu_write64(rvu, blkaddr, 1674 NPC_AF_MCAMEX_BANKX_ACTION 1675 (rule->entry, bank), def_action); 1676 } 1677 1678 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1679 rule->entry, true); 1680 rule->enable = true; 1681 } 1682 } 1683 1684 /* Enable MCAM entries installed by PF with target as VF pcifunc */ 1685 for (index = 0; index < mcam->bmap_entries; index++) { 1686 if (mcam->entry2target_pffunc[index] == target) 1687 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1688 index, true); 1689 } 1690 mutex_unlock(&mcam->lock); 1691 } 1692 1693 void npc_mcam_disable_flows(struct rvu *rvu, u16 target) 1694 { 1695 struct npc_mcam *mcam = &rvu->hw->mcam; 1696 int blkaddr, index; 1697 1698 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1699 if (blkaddr < 0) 1700 return; 1701 1702 mutex_lock(&mcam->lock); 1703 /* Disable MCAM entries installed by PF with target as VF pcifunc */ 1704 for (index = 0; index < mcam->bmap_entries; index++) { 1705 if (mcam->entry2target_pffunc[index] == target) 1706 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1707 index, false); 1708 } 1709 mutex_unlock(&mcam->lock); 1710 } 1711 1712 /* single drop on non hit rule starting from 0th index. This an extension 1713 * to RPM mac filter to support more rules. 1714 */ 1715 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 1716 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 1717 u64 bcast_mcast_val, u64 bcast_mcast_mask) 1718 { 1719 struct npc_mcam_alloc_counter_req cntr_req = { 0 }; 1720 struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 }; 1721 struct npc_mcam_write_entry_req req = { 0 }; 1722 struct npc_mcam *mcam = &rvu->hw->mcam; 1723 struct rvu_npc_mcam_rule *rule; 1724 struct msg_rsp rsp; 1725 bool enabled; 1726 int blkaddr; 1727 int err; 1728 1729 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1730 if (blkaddr < 0) { 1731 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 1732 return -ENODEV; 1733 } 1734 1735 /* Bail out if no exact match support */ 1736 if (!rvu_npc_exact_has_match_table(rvu)) { 1737 dev_info(rvu->dev, "%s: No support for exact match feature\n", __func__); 1738 return -EINVAL; 1739 } 1740 1741 /* If 0th entry is already used, return err */ 1742 enabled = is_mcam_entry_enabled(rvu, mcam, blkaddr, mcam_idx); 1743 if (enabled) { 1744 dev_err(rvu->dev, "%s: failed to add single drop on non hit rule at %d th index\n", 1745 __func__, mcam_idx); 1746 return -EINVAL; 1747 } 1748 1749 /* Add this entry to mcam rules list */ 1750 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 1751 if (!rule) 1752 return -ENOMEM; 1753 1754 /* Disable rule by default. Enable rule when first dmac filter is 1755 * installed 1756 */ 1757 rule->enable = false; 1758 rule->chan = chan_val; 1759 rule->chan_mask = chan_mask; 1760 rule->entry = mcam_idx; 1761 rvu_mcam_add_rule(mcam, rule); 1762 1763 /* Reserve slot 0 */ 1764 npc_mcam_rsrcs_reserve(rvu, blkaddr, mcam_idx); 1765 1766 /* Allocate counter for this single drop on non hit rule */ 1767 cntr_req.hdr.pcifunc = 0; /* AF request */ 1768 cntr_req.contig = true; 1769 cntr_req.count = 1; 1770 err = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp); 1771 if (err) { 1772 dev_err(rvu->dev, "%s: Err to allocate cntr for drop rule (err=%d)\n", 1773 __func__, err); 1774 return -EFAULT; 1775 } 1776 *counter_idx = cntr_rsp.cntr; 1777 1778 /* Fill in fields for this mcam entry */ 1779 npc_update_entry(rvu, NPC_EXACT_RESULT, &req.entry_data, exact_val, 0, 1780 exact_mask, 0, NIX_INTF_RX); 1781 npc_update_entry(rvu, NPC_CHAN, &req.entry_data, chan_val, 0, 1782 chan_mask, 0, NIX_INTF_RX); 1783 npc_update_entry(rvu, NPC_LXMB, &req.entry_data, bcast_mcast_val, 0, 1784 bcast_mcast_mask, 0, NIX_INTF_RX); 1785 1786 req.intf = NIX_INTF_RX; 1787 req.set_cntr = true; 1788 req.cntr = cntr_rsp.cntr; 1789 req.entry = mcam_idx; 1790 1791 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &req, &rsp); 1792 if (err) { 1793 dev_err(rvu->dev, "%s: Installation of single drop on non hit rule at %d failed\n", 1794 __func__, mcam_idx); 1795 return err; 1796 } 1797 1798 dev_err(rvu->dev, "%s: Installed single drop on non hit rule at %d, cntr=%d\n", 1799 __func__, mcam_idx, req.cntr); 1800 1801 /* disable entry at Bank 0, index 0 */ 1802 npc_enable_mcam_entry(rvu, mcam, blkaddr, mcam_idx, false); 1803 1804 return 0; 1805 } 1806 1807 int rvu_mbox_handler_npc_get_field_status(struct rvu *rvu, 1808 struct npc_get_field_status_req *req, 1809 struct npc_get_field_status_rsp *rsp) 1810 { 1811 int blkaddr; 1812 1813 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1814 if (blkaddr < 0) 1815 return NPC_MCAM_INVALID_REQ; 1816 1817 if (!is_npc_interface_valid(rvu, req->intf)) 1818 return NPC_FLOW_INTF_INVALID; 1819 1820 if (npc_check_field(rvu, blkaddr, req->field, req->intf)) 1821 rsp->enable = 1; 1822 1823 return 0; 1824 } 1825