1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 12 #include "rvu_struct.h" 13 #include "rvu_reg.h" 14 #include "rvu.h" 15 #include "npc.h" 16 #include "cgx.h" 17 #include "npc_profile.h" 18 #include "rvu_npc_hash.h" 19 20 #define RSVD_MCAM_ENTRIES_PER_PF 3 /* Broadcast, Promisc and AllMulticast */ 21 #define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */ 22 23 #define NPC_PARSE_RESULT_DMAC_OFFSET 8 24 #define NPC_HW_TSTAMP_OFFSET 8ULL 25 #define NPC_KEX_CHAN_MASK 0xFFFULL 26 #define NPC_KEX_PF_FUNC_MASK 0xFFFFULL 27 28 #define ALIGN_8B_CEIL(__a) (((__a) + 7) & (-8)) 29 30 static const char def_pfl_name[] = "default"; 31 32 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, 33 int blkaddr, u16 pcifunc); 34 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, 35 u16 pcifunc); 36 37 bool is_npc_intf_tx(u8 intf) 38 { 39 return !!(intf & 0x1); 40 } 41 42 bool is_npc_intf_rx(u8 intf) 43 { 44 return !(intf & 0x1); 45 } 46 47 bool is_npc_interface_valid(struct rvu *rvu, u8 intf) 48 { 49 struct rvu_hwinfo *hw = rvu->hw; 50 51 return intf < hw->npc_intfs; 52 } 53 54 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena) 55 { 56 /* Due to a HW issue in these silicon versions, parse nibble enable 57 * configuration has to be identical for both Rx and Tx interfaces. 58 */ 59 if (is_rvu_96xx_B0(rvu)) 60 return nibble_ena; 61 return 0; 62 } 63 64 static int npc_mcam_verify_pf_func(struct rvu *rvu, 65 struct mcam_entry *entry_data, u8 intf, 66 u16 pcifunc) 67 { 68 u16 pf_func, pf_func_mask; 69 70 if (is_npc_intf_rx(intf)) 71 return 0; 72 73 pf_func_mask = (entry_data->kw_mask[0] >> 32) & 74 NPC_KEX_PF_FUNC_MASK; 75 pf_func = (entry_data->kw[0] >> 32) & NPC_KEX_PF_FUNC_MASK; 76 77 pf_func = be16_to_cpu((__force __be16)pf_func); 78 if (pf_func_mask != NPC_KEX_PF_FUNC_MASK || 79 ((pf_func & ~RVU_PFVF_FUNC_MASK) != 80 (pcifunc & ~RVU_PFVF_FUNC_MASK))) 81 return -EINVAL; 82 83 return 0; 84 } 85 86 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf) 87 { 88 int blkaddr; 89 u64 val = 0; 90 91 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 92 if (blkaddr < 0) 93 return; 94 95 /* Config CPI base for the PKIND */ 96 val = pkind | 1ULL << 62; 97 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); 98 } 99 100 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf) 101 { 102 struct npc_pkind *pkind = &rvu->hw->pkind; 103 u32 map; 104 int i; 105 106 for (i = 0; i < pkind->rsrc.max; i++) { 107 map = pkind->pfchan_map[i]; 108 if (((map >> 16) & 0x3F) == pf) 109 return i; 110 } 111 return -1; 112 } 113 114 #define NPC_AF_ACTION0_PTR_ADVANCE GENMASK_ULL(27, 20) 115 116 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable) 117 { 118 int pkind, blkaddr; 119 u64 val; 120 121 pkind = rvu_npc_get_pkind(rvu, pf); 122 if (pkind < 0) { 123 dev_err(rvu->dev, "%s: pkind not mapped\n", __func__); 124 return -EINVAL; 125 } 126 127 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc); 128 if (blkaddr < 0) { 129 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 130 return -EINVAL; 131 } 132 133 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind)); 134 val &= ~NPC_AF_ACTION0_PTR_ADVANCE; 135 /* If timestamp is enabled then configure NPC to shift 8 bytes */ 136 if (enable) 137 val |= FIELD_PREP(NPC_AF_ACTION0_PTR_ADVANCE, 138 NPC_HW_TSTAMP_OFFSET); 139 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val); 140 141 return 0; 142 } 143 144 static int npc_get_ucast_mcam_index(struct npc_mcam *mcam, u16 pcifunc, 145 int nixlf) 146 { 147 struct rvu_hwinfo *hw = container_of(mcam, struct rvu_hwinfo, mcam); 148 struct rvu *rvu = hw->rvu; 149 int blkaddr = 0, max = 0; 150 struct rvu_block *block; 151 struct rvu_pfvf *pfvf; 152 153 pfvf = rvu_get_pfvf(rvu, pcifunc); 154 /* Given a PF/VF and NIX LF number calculate the unicast mcam 155 * entry index based on the NIX block assigned to the PF/VF. 156 */ 157 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 158 while (blkaddr) { 159 if (pfvf->nix_blkaddr == blkaddr) 160 break; 161 block = &rvu->hw->block[blkaddr]; 162 max += block->lf.max; 163 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 164 } 165 166 return mcam->nixlf_offset + (max + nixlf) * RSVD_MCAM_ENTRIES_PER_NIXLF; 167 } 168 169 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, 170 u16 pcifunc, int nixlf, int type) 171 { 172 int pf = rvu_get_pf(pcifunc); 173 int index; 174 175 /* Check if this is for a PF */ 176 if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) { 177 /* Reserved entries exclude PF0 */ 178 pf--; 179 index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF); 180 /* Broadcast address matching entry should be first so 181 * that the packet can be replicated to all VFs. 182 */ 183 if (type == NIXLF_BCAST_ENTRY) 184 return index; 185 else if (type == NIXLF_ALLMULTI_ENTRY) 186 return index + 1; 187 else if (type == NIXLF_PROMISC_ENTRY) 188 return index + 2; 189 } 190 191 return npc_get_ucast_mcam_index(mcam, pcifunc, nixlf); 192 } 193 194 int npc_get_bank(struct npc_mcam *mcam, int index) 195 { 196 int bank = index / mcam->banksize; 197 198 /* 0,1 & 2,3 banks are combined for this keysize */ 199 if (mcam->keysize == NPC_MCAM_KEY_X2) 200 return bank ? 2 : 0; 201 202 return bank; 203 } 204 205 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, 206 int blkaddr, int index) 207 { 208 int bank = npc_get_bank(mcam, index); 209 u64 cfg; 210 211 index &= (mcam->banksize - 1); 212 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank)); 213 return (cfg & 1); 214 } 215 216 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 217 int blkaddr, int index, bool enable) 218 { 219 int bank = npc_get_bank(mcam, index); 220 int actbank = bank; 221 222 index &= (mcam->banksize - 1); 223 for (; bank < (actbank + mcam->banks_per_entry); bank++) { 224 rvu_write64(rvu, blkaddr, 225 NPC_AF_MCAMEX_BANKX_CFG(index, bank), 226 enable ? 1 : 0); 227 } 228 } 229 230 static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 231 int blkaddr, int index) 232 { 233 int bank = npc_get_bank(mcam, index); 234 int actbank = bank; 235 236 index &= (mcam->banksize - 1); 237 for (; bank < (actbank + mcam->banks_per_entry); bank++) { 238 rvu_write64(rvu, blkaddr, 239 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0); 240 rvu_write64(rvu, blkaddr, 241 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0); 242 243 rvu_write64(rvu, blkaddr, 244 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0); 245 rvu_write64(rvu, blkaddr, 246 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0); 247 248 rvu_write64(rvu, blkaddr, 249 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0); 250 rvu_write64(rvu, blkaddr, 251 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0); 252 } 253 } 254 255 static void npc_get_keyword(struct mcam_entry *entry, int idx, 256 u64 *cam0, u64 *cam1) 257 { 258 u64 kw_mask = 0x00; 259 260 #define CAM_MASK(n) (BIT_ULL(n) - 1) 261 262 /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and 263 * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1. 264 * 265 * Also, only 48 bits of BANKX_CAMX_W1 are valid. 266 */ 267 switch (idx) { 268 case 0: 269 /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */ 270 *cam1 = entry->kw[0]; 271 kw_mask = entry->kw_mask[0]; 272 break; 273 case 1: 274 /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */ 275 *cam1 = entry->kw[1] & CAM_MASK(48); 276 kw_mask = entry->kw_mask[1] & CAM_MASK(48); 277 break; 278 case 2: 279 /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48> 280 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0> 281 */ 282 *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16); 283 *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16); 284 kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16); 285 kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16); 286 break; 287 case 3: 288 /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48> 289 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0> 290 */ 291 *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16); 292 *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16); 293 kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16); 294 kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16); 295 break; 296 case 4: 297 /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32> 298 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0> 299 */ 300 *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32); 301 *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32); 302 kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32); 303 kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32); 304 break; 305 case 5: 306 /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32> 307 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0> 308 */ 309 *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32); 310 *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32); 311 kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32); 312 kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32); 313 break; 314 case 6: 315 /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16> 316 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0> 317 */ 318 *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48); 319 *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48); 320 kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48); 321 kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48); 322 break; 323 case 7: 324 /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */ 325 *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48); 326 kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48); 327 break; 328 } 329 330 *cam1 &= kw_mask; 331 *cam0 = ~*cam1 & kw_mask; 332 } 333 334 static void npc_fill_entryword(struct mcam_entry *entry, int idx, 335 u64 cam0, u64 cam1) 336 { 337 /* Similar to npc_get_keyword, but fills mcam_entry structure from 338 * CAM registers. 339 */ 340 switch (idx) { 341 case 0: 342 entry->kw[0] = cam1; 343 entry->kw_mask[0] = cam1 ^ cam0; 344 break; 345 case 1: 346 entry->kw[1] = cam1; 347 entry->kw_mask[1] = cam1 ^ cam0; 348 break; 349 case 2: 350 entry->kw[1] |= (cam1 & CAM_MASK(16)) << 48; 351 entry->kw[2] = (cam1 >> 16) & CAM_MASK(48); 352 entry->kw_mask[1] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48; 353 entry->kw_mask[2] = ((cam1 ^ cam0) >> 16) & CAM_MASK(48); 354 break; 355 case 3: 356 entry->kw[2] |= (cam1 & CAM_MASK(16)) << 48; 357 entry->kw[3] = (cam1 >> 16) & CAM_MASK(32); 358 entry->kw_mask[2] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48; 359 entry->kw_mask[3] = ((cam1 ^ cam0) >> 16) & CAM_MASK(32); 360 break; 361 case 4: 362 entry->kw[3] |= (cam1 & CAM_MASK(32)) << 32; 363 entry->kw[4] = (cam1 >> 32) & CAM_MASK(32); 364 entry->kw_mask[3] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32; 365 entry->kw_mask[4] = ((cam1 ^ cam0) >> 32) & CAM_MASK(32); 366 break; 367 case 5: 368 entry->kw[4] |= (cam1 & CAM_MASK(32)) << 32; 369 entry->kw[5] = (cam1 >> 32) & CAM_MASK(16); 370 entry->kw_mask[4] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32; 371 entry->kw_mask[5] = ((cam1 ^ cam0) >> 32) & CAM_MASK(16); 372 break; 373 case 6: 374 entry->kw[5] |= (cam1 & CAM_MASK(48)) << 16; 375 entry->kw[6] = (cam1 >> 48) & CAM_MASK(16); 376 entry->kw_mask[5] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16; 377 entry->kw_mask[6] = ((cam1 ^ cam0) >> 48) & CAM_MASK(16); 378 break; 379 case 7: 380 entry->kw[6] |= (cam1 & CAM_MASK(48)) << 16; 381 entry->kw_mask[6] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16; 382 break; 383 } 384 } 385 386 static u64 npc_get_default_entry_action(struct rvu *rvu, struct npc_mcam *mcam, 387 int blkaddr, u16 pf_func) 388 { 389 int bank, nixlf, index; 390 391 /* get ucast entry rule entry index */ 392 if (nix_get_nixlf(rvu, pf_func, &nixlf, NULL)) { 393 dev_err(rvu->dev, "%s: nixlf not attached to pcifunc:0x%x\n", 394 __func__, pf_func); 395 /* Action 0 is drop */ 396 return 0; 397 } 398 399 index = npc_get_nixlf_mcam_index(mcam, pf_func, nixlf, 400 NIXLF_UCAST_ENTRY); 401 bank = npc_get_bank(mcam, index); 402 index &= (mcam->banksize - 1); 403 404 return rvu_read64(rvu, blkaddr, 405 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 406 } 407 408 static void npc_fixup_vf_rule(struct rvu *rvu, struct npc_mcam *mcam, 409 int blkaddr, int index, struct mcam_entry *entry, 410 bool *enable) 411 { 412 struct rvu_npc_mcam_rule *rule; 413 u16 owner, target_func; 414 struct rvu_pfvf *pfvf; 415 u64 rx_action; 416 417 owner = mcam->entry2pfvf_map[index]; 418 target_func = (entry->action >> 4) & 0xffff; 419 /* do nothing when target is LBK/PF or owner is not PF */ 420 if (is_pffunc_af(owner) || is_afvf(target_func) || 421 (owner & RVU_PFVF_FUNC_MASK) || 422 !(target_func & RVU_PFVF_FUNC_MASK)) 423 return; 424 425 /* save entry2target_pffunc */ 426 pfvf = rvu_get_pfvf(rvu, target_func); 427 mcam->entry2target_pffunc[index] = target_func; 428 429 /* don't enable rule when nixlf not attached or initialized */ 430 if (!(is_nixlf_attached(rvu, target_func) && 431 test_bit(NIXLF_INITIALIZED, &pfvf->flags))) 432 *enable = false; 433 434 /* fix up not needed for the rules added by user(ntuple filters) */ 435 list_for_each_entry(rule, &mcam->mcam_rules, list) { 436 if (rule->entry == index) 437 return; 438 } 439 440 /* copy VF default entry action to the VF mcam entry */ 441 rx_action = npc_get_default_entry_action(rvu, mcam, blkaddr, 442 target_func); 443 if (rx_action) 444 entry->action = rx_action; 445 } 446 447 static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 448 int blkaddr, int index, u8 intf, 449 struct mcam_entry *entry, bool enable) 450 { 451 int bank = npc_get_bank(mcam, index); 452 int kw = 0, actbank, actindex; 453 u8 tx_intf_mask = ~intf & 0x3; 454 u8 tx_intf = intf; 455 u64 cam0, cam1; 456 457 actbank = bank; /* Save bank id, to set action later on */ 458 actindex = index; 459 index &= (mcam->banksize - 1); 460 461 /* Disable before mcam entry update */ 462 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false); 463 464 /* Clear mcam entry to avoid writes being suppressed by NPC */ 465 npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex); 466 467 /* CAM1 takes the comparison value and 468 * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'. 469 * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0 470 * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1 471 * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare. 472 */ 473 for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) { 474 /* Interface should be set in all banks */ 475 if (is_npc_intf_tx(intf)) { 476 /* Last bit must be set and rest don't care 477 * for TX interfaces 478 */ 479 tx_intf_mask = 0x1; 480 tx_intf = intf & tx_intf_mask; 481 tx_intf_mask = ~tx_intf & tx_intf_mask; 482 } 483 484 rvu_write64(rvu, blkaddr, 485 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 486 tx_intf); 487 rvu_write64(rvu, blkaddr, 488 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 489 tx_intf_mask); 490 491 /* Set the match key */ 492 npc_get_keyword(entry, kw, &cam0, &cam1); 493 rvu_write64(rvu, blkaddr, 494 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1); 495 rvu_write64(rvu, blkaddr, 496 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0); 497 498 npc_get_keyword(entry, kw + 1, &cam0, &cam1); 499 rvu_write64(rvu, blkaddr, 500 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1); 501 rvu_write64(rvu, blkaddr, 502 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0); 503 } 504 505 /* PF installing VF rule */ 506 if (is_npc_intf_rx(intf) && actindex < mcam->bmap_entries) 507 npc_fixup_vf_rule(rvu, mcam, blkaddr, actindex, entry, &enable); 508 509 /* Set 'action' */ 510 rvu_write64(rvu, blkaddr, 511 NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action); 512 513 /* Set TAG 'action' */ 514 rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank), 515 entry->vtag_action); 516 517 /* Enable the entry */ 518 if (enable) 519 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true); 520 } 521 522 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 523 int blkaddr, u16 src, 524 struct mcam_entry *entry, u8 *intf, u8 *ena) 525 { 526 int sbank = npc_get_bank(mcam, src); 527 int bank, kw = 0; 528 u64 cam0, cam1; 529 530 src &= (mcam->banksize - 1); 531 bank = sbank; 532 533 for (; bank < (sbank + mcam->banks_per_entry); bank++, kw = kw + 2) { 534 cam1 = rvu_read64(rvu, blkaddr, 535 NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1)); 536 cam0 = rvu_read64(rvu, blkaddr, 537 NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0)); 538 npc_fill_entryword(entry, kw, cam0, cam1); 539 540 cam1 = rvu_read64(rvu, blkaddr, 541 NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1)); 542 cam0 = rvu_read64(rvu, blkaddr, 543 NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0)); 544 npc_fill_entryword(entry, kw + 1, cam0, cam1); 545 } 546 547 entry->action = rvu_read64(rvu, blkaddr, 548 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank)); 549 entry->vtag_action = 550 rvu_read64(rvu, blkaddr, 551 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank)); 552 *intf = rvu_read64(rvu, blkaddr, 553 NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank, 1)) & 3; 554 *ena = rvu_read64(rvu, blkaddr, 555 NPC_AF_MCAMEX_BANKX_CFG(src, sbank)) & 1; 556 } 557 558 static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 559 int blkaddr, u16 src, u16 dest) 560 { 561 int dbank = npc_get_bank(mcam, dest); 562 int sbank = npc_get_bank(mcam, src); 563 u64 cfg, sreg, dreg; 564 int bank, i; 565 566 src &= (mcam->banksize - 1); 567 dest &= (mcam->banksize - 1); 568 569 /* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */ 570 for (bank = 0; bank < mcam->banks_per_entry; bank++) { 571 sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0); 572 dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0); 573 for (i = 0; i < 6; i++) { 574 cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8)); 575 rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg); 576 } 577 } 578 579 /* Copy action */ 580 cfg = rvu_read64(rvu, blkaddr, 581 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank)); 582 rvu_write64(rvu, blkaddr, 583 NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg); 584 585 /* Copy TAG action */ 586 cfg = rvu_read64(rvu, blkaddr, 587 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank)); 588 rvu_write64(rvu, blkaddr, 589 NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg); 590 591 /* Enable or disable */ 592 cfg = rvu_read64(rvu, blkaddr, 593 NPC_AF_MCAMEX_BANKX_CFG(src, sbank)); 594 rvu_write64(rvu, blkaddr, 595 NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg); 596 } 597 598 u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 599 int blkaddr, int index) 600 { 601 int bank = npc_get_bank(mcam, index); 602 603 index &= (mcam->banksize - 1); 604 return rvu_read64(rvu, blkaddr, 605 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 606 } 607 608 void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 609 int blkaddr, int index, u64 cfg) 610 { 611 int bank = npc_get_bank(mcam, index); 612 613 index &= (mcam->banksize - 1); 614 return rvu_write64(rvu, blkaddr, 615 NPC_AF_MCAMEX_BANKX_ACTION(index, bank), cfg); 616 } 617 618 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 619 int nixlf, u64 chan, u8 *mac_addr) 620 { 621 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 622 struct npc_install_flow_req req = { 0 }; 623 struct npc_install_flow_rsp rsp = { 0 }; 624 struct npc_mcam *mcam = &rvu->hw->mcam; 625 struct nix_rx_action action = { 0 }; 626 int blkaddr, index; 627 628 /* AF's and SDP VFs work in promiscuous mode */ 629 if (is_afvf(pcifunc) || is_sdp_vf(pcifunc)) 630 return; 631 632 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 633 if (blkaddr < 0) 634 return; 635 636 /* Ucast rule should not be installed if DMAC 637 * extraction is not supported by the profile. 638 */ 639 if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf)) 640 return; 641 642 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 643 nixlf, NIXLF_UCAST_ENTRY); 644 645 /* Don't change the action if entry is already enabled 646 * Otherwise RSS action may get overwritten. 647 */ 648 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) { 649 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 650 blkaddr, index); 651 } else { 652 action.op = NIX_RX_ACTIONOP_UCAST; 653 action.pf_func = pcifunc; 654 } 655 656 req.default_rule = 1; 657 ether_addr_copy(req.packet.dmac, mac_addr); 658 eth_broadcast_addr((u8 *)&req.mask.dmac); 659 req.features = BIT_ULL(NPC_DMAC); 660 req.channel = chan; 661 req.chan_mask = 0xFFFU; 662 req.intf = pfvf->nix_rx_intf; 663 req.op = action.op; 664 req.hdr.pcifunc = 0; /* AF is requester */ 665 req.vf = action.pf_func; 666 req.index = action.index; 667 req.match_id = action.match_id; 668 req.flow_key_alg = action.flow_key_alg; 669 670 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 671 } 672 673 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 674 int nixlf, u64 chan, u8 chan_cnt) 675 { 676 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 677 struct npc_install_flow_req req = { 0 }; 678 struct npc_install_flow_rsp rsp = { 0 }; 679 struct npc_mcam *mcam = &rvu->hw->mcam; 680 struct rvu_hwinfo *hw = rvu->hw; 681 int blkaddr, ucast_idx, index; 682 struct nix_rx_action action = { 0 }; 683 u64 relaxed_mask; 684 u8 flow_key_alg; 685 686 if (!hw->cap.nix_rx_multicast && is_cgx_vf(rvu, pcifunc)) 687 return; 688 689 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 690 if (blkaddr < 0) 691 return; 692 693 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 694 nixlf, NIXLF_PROMISC_ENTRY); 695 696 if (is_cgx_vf(rvu, pcifunc)) 697 index = npc_get_nixlf_mcam_index(mcam, 698 pcifunc & ~RVU_PFVF_FUNC_MASK, 699 nixlf, NIXLF_PROMISC_ENTRY); 700 701 /* If the corresponding PF's ucast action is RSS, 702 * use the same action for promisc also 703 */ 704 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc, 705 nixlf, NIXLF_UCAST_ENTRY); 706 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx)) 707 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 708 blkaddr, ucast_idx); 709 710 if (action.op != NIX_RX_ACTIONOP_RSS) { 711 *(u64 *)&action = 0; 712 action.op = NIX_RX_ACTIONOP_UCAST; 713 } 714 715 flow_key_alg = action.flow_key_alg; 716 717 /* RX_ACTION set to MCAST for CGX PF's */ 718 if (hw->cap.nix_rx_multicast && pfvf->use_mce_list && 719 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 720 *(u64 *)&action = 0; 721 action.op = NIX_RX_ACTIONOP_MCAST; 722 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 723 action.index = pfvf->promisc_mce_idx; 724 } 725 726 /* For cn10k the upper two bits of the channel number are 727 * cpt channel number. with masking out these bits in the 728 * mcam entry, same entry used for NIX will allow packets 729 * received from cpt for parsing. 730 */ 731 if (!is_rvu_otx2(rvu)) { 732 req.chan_mask = NIX_CHAN_CPT_X2P_MASK; 733 } else { 734 req.chan_mask = 0xFFFU; 735 } 736 737 if (chan_cnt > 1) { 738 if (!is_power_of_2(chan_cnt)) { 739 dev_err(rvu->dev, 740 "%s: channel count more than 1, must be power of 2\n", __func__); 741 return; 742 } 743 relaxed_mask = GENMASK_ULL(BITS_PER_LONG_LONG - 1, 744 ilog2(chan_cnt)); 745 req.chan_mask &= relaxed_mask; 746 } 747 748 req.channel = chan; 749 req.intf = pfvf->nix_rx_intf; 750 req.entry = index; 751 req.op = action.op; 752 req.hdr.pcifunc = 0; /* AF is requester */ 753 req.vf = pcifunc; 754 req.index = action.index; 755 req.match_id = action.match_id; 756 req.flow_key_alg = flow_key_alg; 757 758 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 759 } 760 761 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, 762 int nixlf, bool enable) 763 { 764 struct npc_mcam *mcam = &rvu->hw->mcam; 765 int blkaddr, index; 766 767 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 768 if (blkaddr < 0) 769 return; 770 771 /* Get 'pcifunc' of PF device */ 772 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 773 774 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 775 nixlf, NIXLF_PROMISC_ENTRY); 776 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 777 } 778 779 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 780 int nixlf, u64 chan) 781 { 782 struct rvu_pfvf *pfvf; 783 struct npc_install_flow_req req = { 0 }; 784 struct npc_install_flow_rsp rsp = { 0 }; 785 struct npc_mcam *mcam = &rvu->hw->mcam; 786 struct rvu_hwinfo *hw = rvu->hw; 787 int blkaddr, index; 788 789 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 790 if (blkaddr < 0) 791 return; 792 793 /* Skip LBK VFs */ 794 if (is_afvf(pcifunc)) 795 return; 796 797 /* If pkt replication is not supported, 798 * then only PF is allowed to add a bcast match entry. 799 */ 800 if (!hw->cap.nix_rx_multicast && is_vf(pcifunc)) 801 return; 802 803 /* Get 'pcifunc' of PF device */ 804 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 805 pfvf = rvu_get_pfvf(rvu, pcifunc); 806 807 /* Bcast rule should not be installed if both DMAC 808 * and LXMB extraction is not supported by the profile. 809 */ 810 if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf) && 811 !npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), pfvf->nix_rx_intf)) 812 return; 813 814 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 815 nixlf, NIXLF_BCAST_ENTRY); 816 817 if (!hw->cap.nix_rx_multicast) { 818 /* Early silicon doesn't support pkt replication, 819 * so install entry with UCAST action, so that PF 820 * receives all broadcast packets. 821 */ 822 req.op = NIX_RX_ACTIONOP_UCAST; 823 } else { 824 req.op = NIX_RX_ACTIONOP_MCAST; 825 req.index = pfvf->bcast_mce_idx; 826 } 827 828 eth_broadcast_addr((u8 *)&req.packet.dmac); 829 eth_broadcast_addr((u8 *)&req.mask.dmac); 830 req.features = BIT_ULL(NPC_DMAC); 831 req.channel = chan; 832 req.chan_mask = 0xFFFU; 833 req.intf = pfvf->nix_rx_intf; 834 req.entry = index; 835 req.hdr.pcifunc = 0; /* AF is requester */ 836 req.vf = pcifunc; 837 838 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 839 } 840 841 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 842 bool enable) 843 { 844 struct npc_mcam *mcam = &rvu->hw->mcam; 845 int blkaddr, index; 846 847 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 848 if (blkaddr < 0) 849 return; 850 851 /* Get 'pcifunc' of PF device */ 852 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 853 854 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, 855 NIXLF_BCAST_ENTRY); 856 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 857 } 858 859 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 860 u64 chan) 861 { 862 struct npc_install_flow_req req = { 0 }; 863 struct npc_install_flow_rsp rsp = { 0 }; 864 struct npc_mcam *mcam = &rvu->hw->mcam; 865 struct rvu_hwinfo *hw = rvu->hw; 866 int blkaddr, ucast_idx, index; 867 u8 mac_addr[ETH_ALEN] = { 0 }; 868 struct nix_rx_action action = { 0 }; 869 struct rvu_pfvf *pfvf; 870 u8 flow_key_alg; 871 u16 vf_func; 872 873 /* Only CGX PF/VF can add allmulticast entry */ 874 if (is_afvf(pcifunc) && is_sdp_vf(pcifunc)) 875 return; 876 877 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 878 if (blkaddr < 0) 879 return; 880 881 /* Get 'pcifunc' of PF device */ 882 vf_func = pcifunc & RVU_PFVF_FUNC_MASK; 883 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 884 pfvf = rvu_get_pfvf(rvu, pcifunc); 885 886 /* Mcast rule should not be installed if both DMAC 887 * and LXMB extraction is not supported by the profile. 888 */ 889 if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf) && 890 !npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), pfvf->nix_rx_intf)) 891 return; 892 893 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 894 nixlf, NIXLF_ALLMULTI_ENTRY); 895 896 /* If the corresponding PF's ucast action is RSS, 897 * use the same action for multicast entry also 898 */ 899 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc, 900 nixlf, NIXLF_UCAST_ENTRY); 901 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx)) 902 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 903 blkaddr, ucast_idx); 904 905 flow_key_alg = action.flow_key_alg; 906 if (action.op != NIX_RX_ACTIONOP_RSS) { 907 *(u64 *)&action = 0; 908 action.op = NIX_RX_ACTIONOP_UCAST; 909 action.pf_func = pcifunc; 910 } 911 912 /* RX_ACTION set to MCAST for CGX PF's */ 913 if (hw->cap.nix_rx_multicast && pfvf->use_mce_list) { 914 *(u64 *)&action = 0; 915 action.op = NIX_RX_ACTIONOP_MCAST; 916 action.index = pfvf->mcast_mce_idx; 917 } 918 919 mac_addr[0] = 0x01; /* LSB bit of 1st byte in DMAC */ 920 ether_addr_copy(req.packet.dmac, mac_addr); 921 ether_addr_copy(req.mask.dmac, mac_addr); 922 req.features = BIT_ULL(NPC_DMAC); 923 924 /* For cn10k the upper two bits of the channel number are 925 * cpt channel number. with masking out these bits in the 926 * mcam entry, same entry used for NIX will allow packets 927 * received from cpt for parsing. 928 */ 929 if (!is_rvu_otx2(rvu)) 930 req.chan_mask = NIX_CHAN_CPT_X2P_MASK; 931 else 932 req.chan_mask = 0xFFFU; 933 934 req.channel = chan; 935 req.intf = pfvf->nix_rx_intf; 936 req.entry = index; 937 req.op = action.op; 938 req.hdr.pcifunc = 0; /* AF is requester */ 939 req.vf = pcifunc | vf_func; 940 req.index = action.index; 941 req.match_id = action.match_id; 942 req.flow_key_alg = flow_key_alg; 943 944 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 945 } 946 947 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 948 bool enable) 949 { 950 struct npc_mcam *mcam = &rvu->hw->mcam; 951 int blkaddr, index; 952 953 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 954 if (blkaddr < 0) 955 return; 956 957 /* Get 'pcifunc' of PF device */ 958 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 959 960 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, 961 NIXLF_ALLMULTI_ENTRY); 962 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 963 } 964 965 static void npc_update_vf_flow_entry(struct rvu *rvu, struct npc_mcam *mcam, 966 int blkaddr, u16 pcifunc, u64 rx_action) 967 { 968 int actindex, index, bank, entry; 969 struct rvu_npc_mcam_rule *rule; 970 bool enable, update; 971 972 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 973 return; 974 975 mutex_lock(&mcam->lock); 976 for (index = 0; index < mcam->bmap_entries; index++) { 977 if (mcam->entry2target_pffunc[index] == pcifunc) { 978 update = true; 979 /* update not needed for the rules added via ntuple filters */ 980 list_for_each_entry(rule, &mcam->mcam_rules, list) { 981 if (rule->entry == index) 982 update = false; 983 } 984 if (!update) 985 continue; 986 bank = npc_get_bank(mcam, index); 987 actindex = index; 988 entry = index & (mcam->banksize - 1); 989 990 /* read vf flow entry enable status */ 991 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, 992 actindex); 993 /* disable before mcam entry update */ 994 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, 995 false); 996 /* update 'action' */ 997 rvu_write64(rvu, blkaddr, 998 NPC_AF_MCAMEX_BANKX_ACTION(entry, bank), 999 rx_action); 1000 if (enable) 1001 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1002 actindex, true); 1003 } 1004 } 1005 mutex_unlock(&mcam->lock); 1006 } 1007 1008 static void npc_update_rx_action_with_alg_idx(struct rvu *rvu, struct nix_rx_action action, 1009 struct rvu_pfvf *pfvf, int mcam_index, int blkaddr, 1010 int alg_idx) 1011 1012 { 1013 struct npc_mcam *mcam = &rvu->hw->mcam; 1014 struct rvu_hwinfo *hw = rvu->hw; 1015 int bank, op_rss; 1016 1017 if (!is_mcam_entry_enabled(rvu, mcam, blkaddr, mcam_index)) 1018 return; 1019 1020 op_rss = (!hw->cap.nix_rx_multicast || !pfvf->use_mce_list); 1021 1022 bank = npc_get_bank(mcam, mcam_index); 1023 mcam_index &= (mcam->banksize - 1); 1024 1025 /* If Rx action is MCAST update only RSS algorithm index */ 1026 if (!op_rss) { 1027 *(u64 *)&action = rvu_read64(rvu, blkaddr, 1028 NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank)); 1029 1030 action.flow_key_alg = alg_idx; 1031 } 1032 rvu_write64(rvu, blkaddr, 1033 NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank), *(u64 *)&action); 1034 } 1035 1036 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 1037 int group, int alg_idx, int mcam_index) 1038 { 1039 struct npc_mcam *mcam = &rvu->hw->mcam; 1040 struct nix_rx_action action; 1041 int blkaddr, index, bank; 1042 struct rvu_pfvf *pfvf; 1043 1044 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1045 if (blkaddr < 0) 1046 return; 1047 1048 /* Check if this is for reserved default entry */ 1049 if (mcam_index < 0) { 1050 if (group != DEFAULT_RSS_CONTEXT_GROUP) 1051 return; 1052 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1053 nixlf, NIXLF_UCAST_ENTRY); 1054 } else { 1055 /* TODO: validate this mcam index */ 1056 index = mcam_index; 1057 } 1058 1059 if (index >= mcam->total_entries) 1060 return; 1061 1062 bank = npc_get_bank(mcam, index); 1063 index &= (mcam->banksize - 1); 1064 1065 *(u64 *)&action = rvu_read64(rvu, blkaddr, 1066 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 1067 /* Ignore if no action was set earlier */ 1068 if (!*(u64 *)&action) 1069 return; 1070 1071 action.op = NIX_RX_ACTIONOP_RSS; 1072 action.pf_func = pcifunc; 1073 action.index = group; 1074 action.flow_key_alg = alg_idx; 1075 1076 rvu_write64(rvu, blkaddr, 1077 NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action); 1078 1079 /* update the VF flow rule action with the VF default entry action */ 1080 if (mcam_index < 0) 1081 npc_update_vf_flow_entry(rvu, mcam, blkaddr, pcifunc, 1082 *(u64 *)&action); 1083 1084 /* update the action change in default rule */ 1085 pfvf = rvu_get_pfvf(rvu, pcifunc); 1086 if (pfvf->def_ucast_rule) 1087 pfvf->def_ucast_rule->rx_action = action; 1088 1089 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1090 nixlf, NIXLF_PROMISC_ENTRY); 1091 1092 /* If PF's promiscuous entry is enabled, 1093 * Set RSS action for that entry as well 1094 */ 1095 npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, blkaddr, 1096 alg_idx); 1097 1098 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1099 nixlf, NIXLF_ALLMULTI_ENTRY); 1100 /* If PF's allmulti entry is enabled, 1101 * Set RSS action for that entry as well 1102 */ 1103 npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, blkaddr, 1104 alg_idx); 1105 } 1106 1107 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 1108 int nixlf, int type, bool enable) 1109 { 1110 struct npc_mcam *mcam = &rvu->hw->mcam; 1111 struct rvu_hwinfo *hw = rvu->hw; 1112 struct nix_mce_list *mce_list; 1113 int index, blkaddr, mce_idx; 1114 struct rvu_pfvf *pfvf; 1115 1116 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1117 if (blkaddr < 0) 1118 return; 1119 1120 index = npc_get_nixlf_mcam_index(mcam, pcifunc & ~RVU_PFVF_FUNC_MASK, 1121 nixlf, type); 1122 1123 /* disable MCAM entry when packet replication is not supported by hw */ 1124 if (!hw->cap.nix_rx_multicast && !is_vf(pcifunc)) { 1125 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 1126 return; 1127 } 1128 1129 /* return incase mce list is not enabled */ 1130 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1131 if (hw->cap.nix_rx_multicast && is_vf(pcifunc) && 1132 type != NIXLF_BCAST_ENTRY && !pfvf->use_mce_list) 1133 return; 1134 1135 nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx); 1136 1137 nix_update_mce_list(rvu, pcifunc, mce_list, 1138 mce_idx, index, enable); 1139 if (enable) 1140 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 1141 } 1142 1143 static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc, 1144 int nixlf, bool enable) 1145 { 1146 struct npc_mcam *mcam = &rvu->hw->mcam; 1147 int index, blkaddr; 1148 1149 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1150 if (blkaddr < 0) 1151 return; 1152 1153 /* Ucast MCAM match entry of this PF/VF */ 1154 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1155 nixlf, NIXLF_UCAST_ENTRY); 1156 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 1157 1158 /* Nothing to do for VFs, on platforms where pkt replication 1159 * is not supported 1160 */ 1161 if ((pcifunc & RVU_PFVF_FUNC_MASK) && !rvu->hw->cap.nix_rx_multicast) 1162 return; 1163 1164 /* add/delete pf_func to broadcast MCE list */ 1165 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, 1166 NIXLF_BCAST_ENTRY, enable); 1167 } 1168 1169 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1170 { 1171 if (nixlf < 0) 1172 return; 1173 1174 npc_enadis_default_entries(rvu, pcifunc, nixlf, false); 1175 1176 /* Delete multicast and promisc MCAM entries */ 1177 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, 1178 NIXLF_ALLMULTI_ENTRY, false); 1179 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, 1180 NIXLF_PROMISC_ENTRY, false); 1181 } 1182 1183 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable) 1184 { 1185 int blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1186 struct npc_mcam *mcam = &rvu->hw->mcam; 1187 struct rvu_npc_mcam_rule *rule, *tmp; 1188 1189 mutex_lock(&mcam->lock); 1190 1191 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { 1192 if (rule->intf != intf) 1193 continue; 1194 1195 if (rule->entry != entry) 1196 continue; 1197 1198 rule->enable = enable; 1199 mutex_unlock(&mcam->lock); 1200 1201 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1202 entry, enable); 1203 1204 return true; 1205 } 1206 1207 mutex_unlock(&mcam->lock); 1208 return false; 1209 } 1210 1211 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1212 { 1213 if (nixlf < 0) 1214 return; 1215 1216 /* Enables only broadcast match entry. Promisc/Allmulti are enabled 1217 * in set_rx_mode mbox handler. 1218 */ 1219 npc_enadis_default_entries(rvu, pcifunc, nixlf, true); 1220 } 1221 1222 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1223 { 1224 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1225 struct npc_mcam *mcam = &rvu->hw->mcam; 1226 struct rvu_npc_mcam_rule *rule, *tmp; 1227 int blkaddr; 1228 1229 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1230 if (blkaddr < 0) 1231 return; 1232 1233 mutex_lock(&mcam->lock); 1234 1235 /* Disable MCAM entries directing traffic to this 'pcifunc' */ 1236 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { 1237 if (is_npc_intf_rx(rule->intf) && 1238 rule->rx_action.pf_func == pcifunc && 1239 rule->rx_action.op != NIX_RX_ACTIONOP_MCAST) { 1240 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1241 rule->entry, false); 1242 rule->enable = false; 1243 /* Indicate that default rule is disabled */ 1244 if (rule->default_rule) { 1245 pfvf->def_ucast_rule = NULL; 1246 list_del(&rule->list); 1247 kfree(rule); 1248 } 1249 } 1250 } 1251 1252 mutex_unlock(&mcam->lock); 1253 1254 npc_mcam_disable_flows(rvu, pcifunc); 1255 1256 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 1257 } 1258 1259 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1260 { 1261 struct npc_mcam *mcam = &rvu->hw->mcam; 1262 struct rvu_npc_mcam_rule *rule, *tmp; 1263 int blkaddr; 1264 1265 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1266 if (blkaddr < 0) 1267 return; 1268 1269 mutex_lock(&mcam->lock); 1270 1271 /* Free all MCAM entries owned by this 'pcifunc' */ 1272 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); 1273 1274 /* Free all MCAM counters owned by this 'pcifunc' */ 1275 npc_mcam_free_all_counters(rvu, mcam, pcifunc); 1276 1277 /* Delete MCAM entries owned by this 'pcifunc' */ 1278 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { 1279 if (rule->owner == pcifunc && !rule->default_rule) { 1280 list_del(&rule->list); 1281 kfree(rule); 1282 } 1283 } 1284 1285 mutex_unlock(&mcam->lock); 1286 1287 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 1288 } 1289 1290 static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr, 1291 struct npc_mcam_kex *mkex, u8 intf) 1292 { 1293 int lid, lt, ld, fl; 1294 1295 if (is_npc_intf_tx(intf)) 1296 return; 1297 1298 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 1299 mkex->keyx_cfg[NIX_INTF_RX]); 1300 1301 /* Program LDATA */ 1302 for (lid = 0; lid < NPC_MAX_LID; lid++) { 1303 for (lt = 0; lt < NPC_MAX_LT; lt++) { 1304 for (ld = 0; ld < NPC_MAX_LD; ld++) 1305 SET_KEX_LD(intf, lid, lt, ld, 1306 mkex->intf_lid_lt_ld[NIX_INTF_RX] 1307 [lid][lt][ld]); 1308 } 1309 } 1310 /* Program LFLAGS */ 1311 for (ld = 0; ld < NPC_MAX_LD; ld++) { 1312 for (fl = 0; fl < NPC_MAX_LFL; fl++) 1313 SET_KEX_LDFLAGS(intf, ld, fl, 1314 mkex->intf_ld_flags[NIX_INTF_RX] 1315 [ld][fl]); 1316 } 1317 } 1318 1319 static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr, 1320 struct npc_mcam_kex *mkex, u8 intf) 1321 { 1322 int lid, lt, ld, fl; 1323 1324 if (is_npc_intf_rx(intf)) 1325 return; 1326 1327 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 1328 mkex->keyx_cfg[NIX_INTF_TX]); 1329 1330 /* Program LDATA */ 1331 for (lid = 0; lid < NPC_MAX_LID; lid++) { 1332 for (lt = 0; lt < NPC_MAX_LT; lt++) { 1333 for (ld = 0; ld < NPC_MAX_LD; ld++) 1334 SET_KEX_LD(intf, lid, lt, ld, 1335 mkex->intf_lid_lt_ld[NIX_INTF_TX] 1336 [lid][lt][ld]); 1337 } 1338 } 1339 /* Program LFLAGS */ 1340 for (ld = 0; ld < NPC_MAX_LD; ld++) { 1341 for (fl = 0; fl < NPC_MAX_LFL; fl++) 1342 SET_KEX_LDFLAGS(intf, ld, fl, 1343 mkex->intf_ld_flags[NIX_INTF_TX] 1344 [ld][fl]); 1345 } 1346 } 1347 1348 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr, 1349 struct npc_mcam_kex *mkex) 1350 { 1351 struct rvu_hwinfo *hw = rvu->hw; 1352 u8 intf; 1353 int ld; 1354 1355 for (ld = 0; ld < NPC_MAX_LD; ld++) 1356 rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld), 1357 mkex->kex_ld_flags[ld]); 1358 1359 for (intf = 0; intf < hw->npc_intfs; intf++) { 1360 npc_program_mkex_rx(rvu, blkaddr, mkex, intf); 1361 npc_program_mkex_tx(rvu, blkaddr, mkex, intf); 1362 } 1363 1364 /* Programme mkex hash profile */ 1365 npc_program_mkex_hash(rvu, blkaddr); 1366 } 1367 1368 static int npc_fwdb_prfl_img_map(struct rvu *rvu, void __iomem **prfl_img_addr, 1369 u64 *size) 1370 { 1371 u64 prfl_addr, prfl_sz; 1372 1373 if (!rvu->fwdata) 1374 return -EINVAL; 1375 1376 prfl_addr = rvu->fwdata->mcam_addr; 1377 prfl_sz = rvu->fwdata->mcam_sz; 1378 1379 if (!prfl_addr || !prfl_sz) 1380 return -EINVAL; 1381 1382 *prfl_img_addr = ioremap_wc(prfl_addr, prfl_sz); 1383 if (!(*prfl_img_addr)) 1384 return -ENOMEM; 1385 1386 *size = prfl_sz; 1387 1388 return 0; 1389 } 1390 1391 /* strtoull of "mkexprof" with base:36 */ 1392 #define MKEX_END_SIGN 0xdeadbeef 1393 1394 static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr, 1395 const char *mkex_profile) 1396 { 1397 struct device *dev = &rvu->pdev->dev; 1398 struct npc_mcam_kex *mcam_kex; 1399 void __iomem *mkex_prfl_addr = NULL; 1400 u64 prfl_sz; 1401 int ret; 1402 1403 /* If user not selected mkex profile */ 1404 if (rvu->kpu_fwdata_sz || 1405 !strncmp(mkex_profile, def_pfl_name, MKEX_NAME_LEN)) 1406 goto program_mkex; 1407 1408 /* Setting up the mapping for mkex profile image */ 1409 ret = npc_fwdb_prfl_img_map(rvu, &mkex_prfl_addr, &prfl_sz); 1410 if (ret < 0) 1411 goto program_mkex; 1412 1413 mcam_kex = (struct npc_mcam_kex __force *)mkex_prfl_addr; 1414 1415 while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) { 1416 /* Compare with mkex mod_param name string */ 1417 if (mcam_kex->mkex_sign == MKEX_SIGN && 1418 !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) { 1419 /* Due to an errata (35786) in A0/B0 pass silicon, 1420 * parse nibble enable configuration has to be 1421 * identical for both Rx and Tx interfaces. 1422 */ 1423 if (!is_rvu_96xx_B0(rvu) || 1424 mcam_kex->keyx_cfg[NIX_INTF_RX] == mcam_kex->keyx_cfg[NIX_INTF_TX]) 1425 rvu->kpu.mkex = mcam_kex; 1426 goto program_mkex; 1427 } 1428 1429 mcam_kex++; 1430 prfl_sz -= sizeof(struct npc_mcam_kex); 1431 } 1432 dev_warn(dev, "Failed to load requested profile: %s\n", mkex_profile); 1433 1434 program_mkex: 1435 dev_info(rvu->dev, "Using %s mkex profile\n", rvu->kpu.mkex->name); 1436 /* Program selected mkex profile */ 1437 npc_program_mkex_profile(rvu, blkaddr, rvu->kpu.mkex); 1438 if (mkex_prfl_addr) 1439 iounmap(mkex_prfl_addr); 1440 } 1441 1442 static void npc_config_kpuaction(struct rvu *rvu, int blkaddr, 1443 const struct npc_kpu_profile_action *kpuaction, 1444 int kpu, int entry, bool pkind) 1445 { 1446 struct npc_kpu_action0 action0 = {0}; 1447 struct npc_kpu_action1 action1 = {0}; 1448 u64 reg; 1449 1450 action1.errlev = kpuaction->errlev; 1451 action1.errcode = kpuaction->errcode; 1452 action1.dp0_offset = kpuaction->dp0_offset; 1453 action1.dp1_offset = kpuaction->dp1_offset; 1454 action1.dp2_offset = kpuaction->dp2_offset; 1455 1456 if (pkind) 1457 reg = NPC_AF_PKINDX_ACTION1(entry); 1458 else 1459 reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry); 1460 1461 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1); 1462 1463 action0.byp_count = kpuaction->bypass_count; 1464 action0.capture_ena = kpuaction->cap_ena; 1465 action0.parse_done = kpuaction->parse_done; 1466 action0.next_state = kpuaction->next_state; 1467 action0.capture_lid = kpuaction->lid; 1468 action0.capture_ltype = kpuaction->ltype; 1469 action0.capture_flags = kpuaction->flags; 1470 action0.ptr_advance = kpuaction->ptr_advance; 1471 action0.var_len_offset = kpuaction->offset; 1472 action0.var_len_mask = kpuaction->mask; 1473 action0.var_len_right = kpuaction->right; 1474 action0.var_len_shift = kpuaction->shift; 1475 1476 if (pkind) 1477 reg = NPC_AF_PKINDX_ACTION0(entry); 1478 else 1479 reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry); 1480 1481 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0); 1482 } 1483 1484 static void npc_config_kpucam(struct rvu *rvu, int blkaddr, 1485 const struct npc_kpu_profile_cam *kpucam, 1486 int kpu, int entry) 1487 { 1488 struct npc_kpu_cam cam0 = {0}; 1489 struct npc_kpu_cam cam1 = {0}; 1490 1491 cam1.state = kpucam->state & kpucam->state_mask; 1492 cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask; 1493 cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask; 1494 cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask; 1495 1496 cam0.state = ~kpucam->state & kpucam->state_mask; 1497 cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask; 1498 cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask; 1499 cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask; 1500 1501 rvu_write64(rvu, blkaddr, 1502 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0); 1503 rvu_write64(rvu, blkaddr, 1504 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1); 1505 } 1506 1507 static inline u64 enable_mask(int count) 1508 { 1509 return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL)); 1510 } 1511 1512 static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu, 1513 const struct npc_kpu_profile *profile) 1514 { 1515 int entry, num_entries, max_entries; 1516 u64 entry_mask; 1517 1518 if (profile->cam_entries != profile->action_entries) { 1519 dev_err(rvu->dev, 1520 "KPU%d: CAM and action entries [%d != %d] not equal\n", 1521 kpu, profile->cam_entries, profile->action_entries); 1522 } 1523 1524 max_entries = rvu->hw->npc_kpu_entries; 1525 1526 /* Program CAM match entries for previous KPU extracted data */ 1527 num_entries = min_t(int, profile->cam_entries, max_entries); 1528 for (entry = 0; entry < num_entries; entry++) 1529 npc_config_kpucam(rvu, blkaddr, 1530 &profile->cam[entry], kpu, entry); 1531 1532 /* Program this KPU's actions */ 1533 num_entries = min_t(int, profile->action_entries, max_entries); 1534 for (entry = 0; entry < num_entries; entry++) 1535 npc_config_kpuaction(rvu, blkaddr, &profile->action[entry], 1536 kpu, entry, false); 1537 1538 /* Enable all programmed entries */ 1539 num_entries = min_t(int, profile->action_entries, profile->cam_entries); 1540 entry_mask = enable_mask(num_entries); 1541 /* Disable first KPU_MAX_CST_ENT entries for built-in profile */ 1542 if (!rvu->kpu.custom) 1543 entry_mask |= GENMASK_ULL(KPU_MAX_CST_ENT - 1, 0); 1544 rvu_write64(rvu, blkaddr, 1545 NPC_AF_KPUX_ENTRY_DISX(kpu, 0), entry_mask); 1546 if (num_entries > 64) { 1547 rvu_write64(rvu, blkaddr, 1548 NPC_AF_KPUX_ENTRY_DISX(kpu, 1), 1549 enable_mask(num_entries - 64)); 1550 } 1551 1552 /* Enable this KPU */ 1553 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01); 1554 } 1555 1556 static int npc_prepare_default_kpu(struct npc_kpu_profile_adapter *profile) 1557 { 1558 profile->custom = 0; 1559 profile->name = def_pfl_name; 1560 profile->version = NPC_KPU_PROFILE_VER; 1561 profile->ikpu = ikpu_action_entries; 1562 profile->pkinds = ARRAY_SIZE(ikpu_action_entries); 1563 profile->kpu = npc_kpu_profiles; 1564 profile->kpus = ARRAY_SIZE(npc_kpu_profiles); 1565 profile->lt_def = &npc_lt_defaults; 1566 profile->mkex = &npc_mkex_default; 1567 profile->mkex_hash = &npc_mkex_hash_default; 1568 1569 return 0; 1570 } 1571 1572 static int npc_apply_custom_kpu(struct rvu *rvu, 1573 struct npc_kpu_profile_adapter *profile) 1574 { 1575 size_t hdr_sz = sizeof(struct npc_kpu_profile_fwdata), offset = 0; 1576 struct npc_kpu_profile_fwdata *fw = rvu->kpu_fwdata; 1577 struct npc_kpu_profile_action *action; 1578 struct npc_kpu_profile_cam *cam; 1579 struct npc_kpu_fwdata *fw_kpu; 1580 int entries; 1581 u16 kpu, entry; 1582 1583 if (rvu->kpu_fwdata_sz < hdr_sz) { 1584 dev_warn(rvu->dev, "Invalid KPU profile size\n"); 1585 return -EINVAL; 1586 } 1587 if (le64_to_cpu(fw->signature) != KPU_SIGN) { 1588 dev_warn(rvu->dev, "Invalid KPU profile signature %llx\n", 1589 fw->signature); 1590 return -EINVAL; 1591 } 1592 /* Verify if the using known profile structure */ 1593 if (NPC_KPU_VER_MAJ(profile->version) > 1594 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)) { 1595 dev_warn(rvu->dev, "Not supported Major version: %d > %d\n", 1596 NPC_KPU_VER_MAJ(profile->version), 1597 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)); 1598 return -EINVAL; 1599 } 1600 /* Verify if profile is aligned with the required kernel changes */ 1601 if (NPC_KPU_VER_MIN(profile->version) < 1602 NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER)) { 1603 dev_warn(rvu->dev, 1604 "Invalid KPU profile version: %d.%d.%d expected version <= %d.%d.%d\n", 1605 NPC_KPU_VER_MAJ(profile->version), 1606 NPC_KPU_VER_MIN(profile->version), 1607 NPC_KPU_VER_PATCH(profile->version), 1608 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER), 1609 NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER), 1610 NPC_KPU_VER_PATCH(NPC_KPU_PROFILE_VER)); 1611 return -EINVAL; 1612 } 1613 /* Verify if profile fits the HW */ 1614 if (fw->kpus > profile->kpus) { 1615 dev_warn(rvu->dev, "Not enough KPUs: %d > %ld\n", fw->kpus, 1616 profile->kpus); 1617 return -EINVAL; 1618 } 1619 1620 profile->custom = 1; 1621 profile->name = fw->name; 1622 profile->version = le64_to_cpu(fw->version); 1623 profile->mkex = &fw->mkex; 1624 profile->lt_def = &fw->lt_def; 1625 1626 for (kpu = 0; kpu < fw->kpus; kpu++) { 1627 fw_kpu = (struct npc_kpu_fwdata *)(fw->data + offset); 1628 if (fw_kpu->entries > KPU_MAX_CST_ENT) 1629 dev_warn(rvu->dev, 1630 "Too many custom entries on KPU%d: %d > %d\n", 1631 kpu, fw_kpu->entries, KPU_MAX_CST_ENT); 1632 entries = min(fw_kpu->entries, KPU_MAX_CST_ENT); 1633 cam = (struct npc_kpu_profile_cam *)fw_kpu->data; 1634 offset += sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam); 1635 action = (struct npc_kpu_profile_action *)(fw->data + offset); 1636 offset += fw_kpu->entries * sizeof(*action); 1637 if (rvu->kpu_fwdata_sz < hdr_sz + offset) { 1638 dev_warn(rvu->dev, 1639 "Profile size mismatch on KPU%i parsing.\n", 1640 kpu + 1); 1641 return -EINVAL; 1642 } 1643 for (entry = 0; entry < entries; entry++) { 1644 profile->kpu[kpu].cam[entry] = cam[entry]; 1645 profile->kpu[kpu].action[entry] = action[entry]; 1646 } 1647 } 1648 1649 return 0; 1650 } 1651 1652 static int npc_load_kpu_prfl_img(struct rvu *rvu, void __iomem *prfl_addr, 1653 u64 prfl_sz, const char *kpu_profile) 1654 { 1655 struct npc_kpu_profile_fwdata *kpu_data = NULL; 1656 int rc = -EINVAL; 1657 1658 kpu_data = (struct npc_kpu_profile_fwdata __force *)prfl_addr; 1659 if (le64_to_cpu(kpu_data->signature) == KPU_SIGN && 1660 !strncmp(kpu_data->name, kpu_profile, KPU_NAME_LEN)) { 1661 dev_info(rvu->dev, "Loading KPU profile from firmware db: %s\n", 1662 kpu_profile); 1663 rvu->kpu_fwdata = kpu_data; 1664 rvu->kpu_fwdata_sz = prfl_sz; 1665 rvu->kpu_prfl_addr = prfl_addr; 1666 rc = 0; 1667 } 1668 1669 return rc; 1670 } 1671 1672 static int npc_fwdb_detect_load_prfl_img(struct rvu *rvu, uint64_t prfl_sz, 1673 const char *kpu_profile) 1674 { 1675 struct npc_coalesced_kpu_prfl *img_data = NULL; 1676 int i = 0, rc = -EINVAL; 1677 void __iomem *kpu_prfl_addr; 1678 u16 offset; 1679 1680 img_data = (struct npc_coalesced_kpu_prfl __force *)rvu->kpu_prfl_addr; 1681 if (le64_to_cpu(img_data->signature) == KPU_SIGN && 1682 !strncmp(img_data->name, kpu_profile, KPU_NAME_LEN)) { 1683 /* Loaded profile is a single KPU profile. */ 1684 rc = npc_load_kpu_prfl_img(rvu, rvu->kpu_prfl_addr, 1685 prfl_sz, kpu_profile); 1686 goto done; 1687 } 1688 1689 /* Loaded profile is coalesced image, offset of first KPU profile.*/ 1690 offset = offsetof(struct npc_coalesced_kpu_prfl, prfl_sz) + 1691 (img_data->num_prfl * sizeof(uint16_t)); 1692 /* Check if mapped image is coalesced image. */ 1693 while (i < img_data->num_prfl) { 1694 /* Profile image offsets are rounded up to next 8 multiple.*/ 1695 offset = ALIGN_8B_CEIL(offset); 1696 kpu_prfl_addr = (void __iomem *)((uintptr_t)rvu->kpu_prfl_addr + 1697 offset); 1698 rc = npc_load_kpu_prfl_img(rvu, kpu_prfl_addr, 1699 img_data->prfl_sz[i], kpu_profile); 1700 if (!rc) 1701 break; 1702 /* Calculating offset of profile image based on profile size.*/ 1703 offset += img_data->prfl_sz[i]; 1704 i++; 1705 } 1706 done: 1707 return rc; 1708 } 1709 1710 static int npc_load_kpu_profile_fwdb(struct rvu *rvu, const char *kpu_profile) 1711 { 1712 int ret = -EINVAL; 1713 u64 prfl_sz; 1714 1715 /* Setting up the mapping for NPC profile image */ 1716 ret = npc_fwdb_prfl_img_map(rvu, &rvu->kpu_prfl_addr, &prfl_sz); 1717 if (ret < 0) 1718 goto done; 1719 1720 /* Detect if profile is coalesced or single KPU profile and load */ 1721 ret = npc_fwdb_detect_load_prfl_img(rvu, prfl_sz, kpu_profile); 1722 if (ret == 0) 1723 goto done; 1724 1725 /* Cleaning up if KPU profile image from fwdata is not valid. */ 1726 if (rvu->kpu_prfl_addr) { 1727 iounmap(rvu->kpu_prfl_addr); 1728 rvu->kpu_prfl_addr = NULL; 1729 rvu->kpu_fwdata_sz = 0; 1730 rvu->kpu_fwdata = NULL; 1731 } 1732 1733 done: 1734 return ret; 1735 } 1736 1737 static void npc_load_kpu_profile(struct rvu *rvu) 1738 { 1739 struct npc_kpu_profile_adapter *profile = &rvu->kpu; 1740 const char *kpu_profile = rvu->kpu_pfl_name; 1741 const struct firmware *fw = NULL; 1742 bool retry_fwdb = false; 1743 1744 /* If user not specified profile customization */ 1745 if (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN)) 1746 goto revert_to_default; 1747 /* First prepare default KPU, then we'll customize top entries. */ 1748 npc_prepare_default_kpu(profile); 1749 1750 /* Order of preceedence for load loading NPC profile (high to low) 1751 * Firmware binary in filesystem. 1752 * Firmware database method. 1753 * Default KPU profile. 1754 */ 1755 if (!request_firmware_direct(&fw, kpu_profile, rvu->dev)) { 1756 dev_info(rvu->dev, "Loading KPU profile from firmware: %s\n", 1757 kpu_profile); 1758 rvu->kpu_fwdata = kzalloc(fw->size, GFP_KERNEL); 1759 if (rvu->kpu_fwdata) { 1760 memcpy(rvu->kpu_fwdata, fw->data, fw->size); 1761 rvu->kpu_fwdata_sz = fw->size; 1762 } 1763 release_firmware(fw); 1764 retry_fwdb = true; 1765 goto program_kpu; 1766 } 1767 1768 load_image_fwdb: 1769 /* Loading the KPU profile using firmware database */ 1770 if (npc_load_kpu_profile_fwdb(rvu, kpu_profile)) 1771 goto revert_to_default; 1772 1773 program_kpu: 1774 /* Apply profile customization if firmware was loaded. */ 1775 if (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile)) { 1776 /* If image from firmware filesystem fails to load or invalid 1777 * retry with firmware database method. 1778 */ 1779 if (rvu->kpu_fwdata || rvu->kpu_fwdata_sz) { 1780 /* Loading image from firmware database failed. */ 1781 if (rvu->kpu_prfl_addr) { 1782 iounmap(rvu->kpu_prfl_addr); 1783 rvu->kpu_prfl_addr = NULL; 1784 } else { 1785 kfree(rvu->kpu_fwdata); 1786 } 1787 rvu->kpu_fwdata = NULL; 1788 rvu->kpu_fwdata_sz = 0; 1789 if (retry_fwdb) { 1790 retry_fwdb = false; 1791 goto load_image_fwdb; 1792 } 1793 } 1794 1795 dev_warn(rvu->dev, 1796 "Can't load KPU profile %s. Using default.\n", 1797 kpu_profile); 1798 kfree(rvu->kpu_fwdata); 1799 rvu->kpu_fwdata = NULL; 1800 goto revert_to_default; 1801 } 1802 1803 dev_info(rvu->dev, "Using custom profile '%s', version %d.%d.%d\n", 1804 profile->name, NPC_KPU_VER_MAJ(profile->version), 1805 NPC_KPU_VER_MIN(profile->version), 1806 NPC_KPU_VER_PATCH(profile->version)); 1807 1808 return; 1809 1810 revert_to_default: 1811 npc_prepare_default_kpu(profile); 1812 } 1813 1814 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr) 1815 { 1816 struct rvu_hwinfo *hw = rvu->hw; 1817 int num_pkinds, num_kpus, idx; 1818 1819 /* Disable all KPUs and their entries */ 1820 for (idx = 0; idx < hw->npc_kpus; idx++) { 1821 rvu_write64(rvu, blkaddr, 1822 NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL); 1823 rvu_write64(rvu, blkaddr, 1824 NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL); 1825 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00); 1826 } 1827 1828 /* Load and customize KPU profile. */ 1829 npc_load_kpu_profile(rvu); 1830 1831 /* First program IKPU profile i.e PKIND configs. 1832 * Check HW max count to avoid configuring junk or 1833 * writing to unsupported CSR addresses. 1834 */ 1835 num_pkinds = rvu->kpu.pkinds; 1836 num_pkinds = min_t(int, hw->npc_pkinds, num_pkinds); 1837 1838 for (idx = 0; idx < num_pkinds; idx++) 1839 npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true); 1840 1841 /* Program KPU CAM and Action profiles */ 1842 num_kpus = rvu->kpu.kpus; 1843 num_kpus = min_t(int, hw->npc_kpus, num_kpus); 1844 1845 for (idx = 0; idx < num_kpus; idx++) 1846 npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]); 1847 } 1848 1849 void npc_mcam_rsrcs_deinit(struct rvu *rvu) 1850 { 1851 struct npc_mcam *mcam = &rvu->hw->mcam; 1852 1853 bitmap_free(mcam->bmap); 1854 bitmap_free(mcam->bmap_reverse); 1855 kfree(mcam->entry2pfvf_map); 1856 kfree(mcam->cntr2pfvf_map); 1857 kfree(mcam->entry2cntr_map); 1858 kfree(mcam->cntr_refcnt); 1859 kfree(mcam->entry2target_pffunc); 1860 kfree(mcam->counters.bmap); 1861 } 1862 1863 int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr) 1864 { 1865 int nixlf_count = rvu_get_nixlf_count(rvu); 1866 struct npc_mcam *mcam = &rvu->hw->mcam; 1867 int rsvd, err; 1868 u16 index; 1869 int cntr; 1870 u64 cfg; 1871 1872 /* Actual number of MCAM entries vary by entry size */ 1873 cfg = (rvu_read64(rvu, blkaddr, 1874 NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07; 1875 mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize; 1876 mcam->keysize = cfg; 1877 1878 /* Number of banks combined per MCAM entry */ 1879 if (cfg == NPC_MCAM_KEY_X4) 1880 mcam->banks_per_entry = 4; 1881 else if (cfg == NPC_MCAM_KEY_X2) 1882 mcam->banks_per_entry = 2; 1883 else 1884 mcam->banks_per_entry = 1; 1885 1886 /* Reserve one MCAM entry for each of the NIX LF to 1887 * guarantee space to install default matching DMAC rule. 1888 * Also reserve 2 MCAM entries for each PF for default 1889 * channel based matching or 'bcast & promisc' matching to 1890 * support BCAST and PROMISC modes of operation for PFs. 1891 * PF0 is excluded. 1892 */ 1893 rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) + 1894 ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF); 1895 if (mcam->total_entries <= rsvd) { 1896 dev_warn(rvu->dev, 1897 "Insufficient NPC MCAM size %d for pkt I/O, exiting\n", 1898 mcam->total_entries); 1899 return -ENOMEM; 1900 } 1901 1902 mcam->bmap_entries = mcam->total_entries - rsvd; 1903 mcam->nixlf_offset = mcam->bmap_entries; 1904 mcam->pf_offset = mcam->nixlf_offset + nixlf_count; 1905 1906 /* Allocate bitmaps for managing MCAM entries */ 1907 mcam->bmap = bitmap_zalloc(mcam->bmap_entries, GFP_KERNEL); 1908 if (!mcam->bmap) 1909 return -ENOMEM; 1910 1911 mcam->bmap_reverse = bitmap_zalloc(mcam->bmap_entries, GFP_KERNEL); 1912 if (!mcam->bmap_reverse) 1913 goto free_bmap; 1914 1915 mcam->bmap_fcnt = mcam->bmap_entries; 1916 1917 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */ 1918 mcam->entry2pfvf_map = kcalloc(mcam->bmap_entries, sizeof(u16), 1919 GFP_KERNEL); 1920 1921 if (!mcam->entry2pfvf_map) 1922 goto free_bmap_reverse; 1923 1924 /* Reserve 1/8th of MCAM entries at the bottom for low priority 1925 * allocations and another 1/8th at the top for high priority 1926 * allocations. 1927 */ 1928 mcam->lprio_count = mcam->bmap_entries / 8; 1929 if (mcam->lprio_count > BITS_PER_LONG) 1930 mcam->lprio_count = round_down(mcam->lprio_count, 1931 BITS_PER_LONG); 1932 mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count; 1933 mcam->hprio_count = mcam->lprio_count; 1934 mcam->hprio_end = mcam->hprio_count; 1935 1936 /* Allocate bitmap for managing MCAM counters and memory 1937 * for saving counter to RVU PFFUNC allocation mapping. 1938 */ 1939 err = rvu_alloc_bitmap(&mcam->counters); 1940 if (err) 1941 goto free_entry_map; 1942 1943 mcam->cntr2pfvf_map = kcalloc(mcam->counters.max, sizeof(u16), 1944 GFP_KERNEL); 1945 if (!mcam->cntr2pfvf_map) 1946 goto free_cntr_bmap; 1947 1948 /* Alloc memory for MCAM entry to counter mapping and for tracking 1949 * counter's reference count. 1950 */ 1951 mcam->entry2cntr_map = kcalloc(mcam->bmap_entries, sizeof(u16), 1952 GFP_KERNEL); 1953 if (!mcam->entry2cntr_map) 1954 goto free_cntr_map; 1955 1956 mcam->cntr_refcnt = kcalloc(mcam->counters.max, sizeof(u16), 1957 GFP_KERNEL); 1958 if (!mcam->cntr_refcnt) 1959 goto free_entry_cntr_map; 1960 1961 /* Alloc memory for saving target device of mcam rule */ 1962 mcam->entry2target_pffunc = kmalloc_array(mcam->total_entries, 1963 sizeof(u16), GFP_KERNEL); 1964 if (!mcam->entry2target_pffunc) 1965 goto free_cntr_refcnt; 1966 1967 for (index = 0; index < mcam->bmap_entries; index++) { 1968 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP; 1969 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP; 1970 } 1971 1972 for (cntr = 0; cntr < mcam->counters.max; cntr++) 1973 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP; 1974 1975 mutex_init(&mcam->lock); 1976 1977 return 0; 1978 1979 free_cntr_refcnt: 1980 kfree(mcam->cntr_refcnt); 1981 free_entry_cntr_map: 1982 kfree(mcam->entry2cntr_map); 1983 free_cntr_map: 1984 kfree(mcam->cntr2pfvf_map); 1985 free_cntr_bmap: 1986 kfree(mcam->counters.bmap); 1987 free_entry_map: 1988 kfree(mcam->entry2pfvf_map); 1989 free_bmap_reverse: 1990 bitmap_free(mcam->bmap_reverse); 1991 free_bmap: 1992 bitmap_free(mcam->bmap); 1993 1994 return -ENOMEM; 1995 } 1996 1997 static void rvu_npc_hw_init(struct rvu *rvu, int blkaddr) 1998 { 1999 struct npc_pkind *pkind = &rvu->hw->pkind; 2000 struct npc_mcam *mcam = &rvu->hw->mcam; 2001 struct rvu_hwinfo *hw = rvu->hw; 2002 u64 npc_const, npc_const1; 2003 u64 npc_const2 = 0; 2004 2005 npc_const = rvu_read64(rvu, blkaddr, NPC_AF_CONST); 2006 npc_const1 = rvu_read64(rvu, blkaddr, NPC_AF_CONST1); 2007 if (npc_const1 & BIT_ULL(63)) 2008 npc_const2 = rvu_read64(rvu, blkaddr, NPC_AF_CONST2); 2009 2010 pkind->rsrc.max = NPC_UNRESERVED_PKIND_COUNT; 2011 hw->npc_pkinds = (npc_const1 >> 12) & 0xFFULL; 2012 hw->npc_kpu_entries = npc_const1 & 0xFFFULL; 2013 hw->npc_kpus = (npc_const >> 8) & 0x1FULL; 2014 hw->npc_intfs = npc_const & 0xFULL; 2015 hw->npc_counters = (npc_const >> 48) & 0xFFFFULL; 2016 2017 mcam->banks = (npc_const >> 44) & 0xFULL; 2018 mcam->banksize = (npc_const >> 28) & 0xFFFFULL; 2019 hw->npc_stat_ena = BIT_ULL(9); 2020 /* Extended set */ 2021 if (npc_const2) { 2022 hw->npc_ext_set = true; 2023 /* 96xx supports only match_stats and npc_counters 2024 * reflected in NPC_AF_CONST reg. 2025 * STAT_SEL and ENA are at [0:8] and 9 bit positions. 2026 * 98xx has both match_stat and ext and npc_counter 2027 * reflected in NPC_AF_CONST2 2028 * STAT_SEL_EXT added at [12:14] bit position. 2029 * cn10k supports only ext and hence npc_counters in 2030 * NPC_AF_CONST is 0 and npc_counters reflected in NPC_AF_CONST2. 2031 * STAT_SEL bitpos incremented from [0:8] to [0:11] and ENA bit moved to 63 2032 */ 2033 if (!hw->npc_counters) 2034 hw->npc_stat_ena = BIT_ULL(63); 2035 hw->npc_counters = (npc_const2 >> 16) & 0xFFFFULL; 2036 mcam->banksize = npc_const2 & 0xFFFFULL; 2037 } 2038 2039 mcam->counters.max = hw->npc_counters; 2040 } 2041 2042 static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr) 2043 { 2044 struct npc_mcam_kex *mkex = rvu->kpu.mkex; 2045 struct npc_mcam *mcam = &rvu->hw->mcam; 2046 struct rvu_hwinfo *hw = rvu->hw; 2047 u64 nibble_ena, rx_kex, tx_kex; 2048 u8 intf; 2049 2050 /* Reserve last counter for MCAM RX miss action which is set to 2051 * drop packet. This way we will know how many pkts didn't match 2052 * any MCAM entry. 2053 */ 2054 mcam->counters.max--; 2055 mcam->rx_miss_act_cntr = mcam->counters.max; 2056 2057 rx_kex = mkex->keyx_cfg[NIX_INTF_RX]; 2058 tx_kex = mkex->keyx_cfg[NIX_INTF_TX]; 2059 nibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex); 2060 2061 nibble_ena = rvu_npc_get_tx_nibble_cfg(rvu, nibble_ena); 2062 if (nibble_ena) { 2063 tx_kex &= ~NPC_PARSE_NIBBLE; 2064 tx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena); 2065 mkex->keyx_cfg[NIX_INTF_TX] = tx_kex; 2066 } 2067 2068 /* Configure RX interfaces */ 2069 for (intf = 0; intf < hw->npc_intfs; intf++) { 2070 if (is_npc_intf_tx(intf)) 2071 continue; 2072 2073 /* Set RX MCAM search key size. LA..LE (ltype only) + Channel */ 2074 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 2075 rx_kex); 2076 2077 /* If MCAM lookup doesn't result in a match, drop the received 2078 * packet. And map this action to a counter to count dropped 2079 * packets. 2080 */ 2081 rvu_write64(rvu, blkaddr, 2082 NPC_AF_INTFX_MISS_ACT(intf), NIX_RX_ACTIONOP_DROP); 2083 2084 /* NPC_AF_INTFX_MISS_STAT_ACT[14:12] - counter[11:9] 2085 * NPC_AF_INTFX_MISS_STAT_ACT[8:0] - counter[8:0] 2086 */ 2087 rvu_write64(rvu, blkaddr, 2088 NPC_AF_INTFX_MISS_STAT_ACT(intf), 2089 ((mcam->rx_miss_act_cntr >> 9) << 12) | 2090 hw->npc_stat_ena | mcam->rx_miss_act_cntr); 2091 } 2092 2093 /* Configure TX interfaces */ 2094 for (intf = 0; intf < hw->npc_intfs; intf++) { 2095 if (is_npc_intf_rx(intf)) 2096 continue; 2097 2098 /* Extract Ltypes LID_LA to LID_LE */ 2099 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 2100 tx_kex); 2101 2102 /* Set TX miss action to UCAST_DEFAULT i.e 2103 * transmit the packet on NIX LF SQ's default channel. 2104 */ 2105 rvu_write64(rvu, blkaddr, 2106 NPC_AF_INTFX_MISS_ACT(intf), 2107 NIX_TX_ACTIONOP_UCAST_DEFAULT); 2108 } 2109 } 2110 2111 int rvu_npc_init(struct rvu *rvu) 2112 { 2113 struct npc_kpu_profile_adapter *kpu = &rvu->kpu; 2114 struct npc_pkind *pkind = &rvu->hw->pkind; 2115 struct npc_mcam *mcam = &rvu->hw->mcam; 2116 int blkaddr, entry, bank, err; 2117 2118 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2119 if (blkaddr < 0) { 2120 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 2121 return -ENODEV; 2122 } 2123 2124 rvu_npc_hw_init(rvu, blkaddr); 2125 2126 /* First disable all MCAM entries, to stop traffic towards NIXLFs */ 2127 for (bank = 0; bank < mcam->banks; bank++) { 2128 for (entry = 0; entry < mcam->banksize; entry++) 2129 rvu_write64(rvu, blkaddr, 2130 NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0); 2131 } 2132 2133 err = rvu_alloc_bitmap(&pkind->rsrc); 2134 if (err) 2135 return err; 2136 /* Reserve PKIND#0 for LBKs. Power reset value of LBK_CH_PKIND is '0', 2137 * no need to configure PKIND for all LBKs separately. 2138 */ 2139 rvu_alloc_rsrc(&pkind->rsrc); 2140 2141 /* Allocate mem for pkind to PF and channel mapping info */ 2142 pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max, 2143 sizeof(u32), GFP_KERNEL); 2144 if (!pkind->pfchan_map) 2145 return -ENOMEM; 2146 2147 /* Configure KPU profile */ 2148 npc_parser_profile_init(rvu, blkaddr); 2149 2150 /* Config Outer L2, IPv4's NPC layer info */ 2151 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2, 2152 (kpu->lt_def->pck_ol2.lid << 8) | (kpu->lt_def->pck_ol2.ltype_match << 4) | 2153 kpu->lt_def->pck_ol2.ltype_mask); 2154 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4, 2155 (kpu->lt_def->pck_oip4.lid << 8) | (kpu->lt_def->pck_oip4.ltype_match << 4) | 2156 kpu->lt_def->pck_oip4.ltype_mask); 2157 2158 /* Config Inner IPV4 NPC layer info */ 2159 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4, 2160 (kpu->lt_def->pck_iip4.lid << 8) | (kpu->lt_def->pck_iip4.ltype_match << 4) | 2161 kpu->lt_def->pck_iip4.ltype_mask); 2162 2163 /* Enable below for Rx pkts. 2164 * - Outer IPv4 header checksum validation. 2165 * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2B]. 2166 * - Detect outer L2 multicast address and set NPC_RESULT_S[L2M]. 2167 * - Inner IPv4 header checksum validation. 2168 * - Set non zero checksum error code value 2169 */ 2170 rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG, 2171 rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) | 2172 ((u64)NPC_EC_OIP4_CSUM << 32) | (NPC_EC_IIP4_CSUM << 24) | 2173 BIT_ULL(7) | BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1)); 2174 2175 rvu_npc_setup_interfaces(rvu, blkaddr); 2176 2177 npc_config_secret_key(rvu, blkaddr); 2178 /* Configure MKEX profile */ 2179 npc_load_mkex_profile(rvu, blkaddr, rvu->mkex_pfl_name); 2180 2181 err = npc_mcam_rsrcs_init(rvu, blkaddr); 2182 if (err) 2183 return err; 2184 2185 err = npc_flow_steering_init(rvu, blkaddr); 2186 if (err) { 2187 dev_err(rvu->dev, 2188 "Incorrect mkex profile loaded using default mkex\n"); 2189 npc_load_mkex_profile(rvu, blkaddr, def_pfl_name); 2190 } 2191 2192 return 0; 2193 } 2194 2195 void rvu_npc_freemem(struct rvu *rvu) 2196 { 2197 struct npc_pkind *pkind = &rvu->hw->pkind; 2198 struct npc_mcam *mcam = &rvu->hw->mcam; 2199 2200 kfree(pkind->rsrc.bmap); 2201 npc_mcam_rsrcs_deinit(rvu); 2202 kfree(mcam->counters.bmap); 2203 if (rvu->kpu_prfl_addr) 2204 iounmap(rvu->kpu_prfl_addr); 2205 else 2206 kfree(rvu->kpu_fwdata); 2207 mutex_destroy(&mcam->lock); 2208 } 2209 2210 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 2211 int blkaddr, int *alloc_cnt, 2212 int *enable_cnt) 2213 { 2214 struct npc_mcam *mcam = &rvu->hw->mcam; 2215 int entry; 2216 2217 *alloc_cnt = 0; 2218 *enable_cnt = 0; 2219 2220 for (entry = 0; entry < mcam->bmap_entries; entry++) { 2221 if (mcam->entry2pfvf_map[entry] == pcifunc) { 2222 (*alloc_cnt)++; 2223 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry)) 2224 (*enable_cnt)++; 2225 } 2226 } 2227 } 2228 2229 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 2230 int blkaddr, int *alloc_cnt, 2231 int *enable_cnt) 2232 { 2233 struct npc_mcam *mcam = &rvu->hw->mcam; 2234 int cntr; 2235 2236 *alloc_cnt = 0; 2237 *enable_cnt = 0; 2238 2239 for (cntr = 0; cntr < mcam->counters.max; cntr++) { 2240 if (mcam->cntr2pfvf_map[cntr] == pcifunc) { 2241 (*alloc_cnt)++; 2242 if (mcam->cntr_refcnt[cntr]) 2243 (*enable_cnt)++; 2244 } 2245 } 2246 } 2247 2248 static int npc_mcam_verify_entry(struct npc_mcam *mcam, 2249 u16 pcifunc, int entry) 2250 { 2251 /* verify AF installed entries */ 2252 if (is_pffunc_af(pcifunc)) 2253 return 0; 2254 /* Verify if entry is valid and if it is indeed 2255 * allocated to the requesting PFFUNC. 2256 */ 2257 if (entry >= mcam->bmap_entries) 2258 return NPC_MCAM_INVALID_REQ; 2259 2260 if (pcifunc != mcam->entry2pfvf_map[entry]) 2261 return NPC_MCAM_PERM_DENIED; 2262 2263 return 0; 2264 } 2265 2266 static int npc_mcam_verify_counter(struct npc_mcam *mcam, 2267 u16 pcifunc, int cntr) 2268 { 2269 /* Verify if counter is valid and if it is indeed 2270 * allocated to the requesting PFFUNC. 2271 */ 2272 if (cntr >= mcam->counters.max) 2273 return NPC_MCAM_INVALID_REQ; 2274 2275 if (pcifunc != mcam->cntr2pfvf_map[cntr]) 2276 return NPC_MCAM_PERM_DENIED; 2277 2278 return 0; 2279 } 2280 2281 static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam, 2282 int blkaddr, u16 entry, u16 cntr) 2283 { 2284 u16 index = entry & (mcam->banksize - 1); 2285 u32 bank = npc_get_bank(mcam, entry); 2286 struct rvu_hwinfo *hw = rvu->hw; 2287 2288 /* Set mapping and increment counter's refcnt */ 2289 mcam->entry2cntr_map[entry] = cntr; 2290 mcam->cntr_refcnt[cntr]++; 2291 /* Enable stats */ 2292 rvu_write64(rvu, blkaddr, 2293 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 2294 ((cntr >> 9) << 12) | hw->npc_stat_ena | cntr); 2295 } 2296 2297 static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu, 2298 struct npc_mcam *mcam, 2299 int blkaddr, u16 entry, u16 cntr) 2300 { 2301 u16 index = entry & (mcam->banksize - 1); 2302 u32 bank = npc_get_bank(mcam, entry); 2303 2304 /* Remove mapping and reduce counter's refcnt */ 2305 mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP; 2306 mcam->cntr_refcnt[cntr]--; 2307 /* Disable stats */ 2308 rvu_write64(rvu, blkaddr, 2309 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00); 2310 } 2311 2312 /* Sets MCAM entry in bitmap as used. Update 2313 * reverse bitmap too. Should be called with 2314 * 'mcam->lock' held. 2315 */ 2316 static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index) 2317 { 2318 u16 entry, rentry; 2319 2320 entry = index; 2321 rentry = mcam->bmap_entries - index - 1; 2322 2323 __set_bit(entry, mcam->bmap); 2324 __set_bit(rentry, mcam->bmap_reverse); 2325 mcam->bmap_fcnt--; 2326 } 2327 2328 /* Sets MCAM entry in bitmap as free. Update 2329 * reverse bitmap too. Should be called with 2330 * 'mcam->lock' held. 2331 */ 2332 static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index) 2333 { 2334 u16 entry, rentry; 2335 2336 entry = index; 2337 rentry = mcam->bmap_entries - index - 1; 2338 2339 __clear_bit(entry, mcam->bmap); 2340 __clear_bit(rentry, mcam->bmap_reverse); 2341 mcam->bmap_fcnt++; 2342 } 2343 2344 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, 2345 int blkaddr, u16 pcifunc) 2346 { 2347 u16 index, cntr; 2348 2349 /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */ 2350 for (index = 0; index < mcam->bmap_entries; index++) { 2351 if (mcam->entry2pfvf_map[index] == pcifunc) { 2352 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP; 2353 /* Free the entry in bitmap */ 2354 npc_mcam_clear_bit(mcam, index); 2355 /* Disable the entry */ 2356 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); 2357 2358 /* Update entry2counter mapping */ 2359 cntr = mcam->entry2cntr_map[index]; 2360 if (cntr != NPC_MCAM_INVALID_MAP) 2361 npc_unmap_mcam_entry_and_cntr(rvu, mcam, 2362 blkaddr, index, 2363 cntr); 2364 mcam->entry2target_pffunc[index] = 0x0; 2365 } 2366 } 2367 } 2368 2369 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, 2370 u16 pcifunc) 2371 { 2372 u16 cntr; 2373 2374 /* Scan all MCAM counters and free the ones mapped to 'pcifunc' */ 2375 for (cntr = 0; cntr < mcam->counters.max; cntr++) { 2376 if (mcam->cntr2pfvf_map[cntr] == pcifunc) { 2377 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP; 2378 mcam->cntr_refcnt[cntr] = 0; 2379 rvu_free_rsrc(&mcam->counters, cntr); 2380 /* This API is expected to be called after freeing 2381 * MCAM entries, which inturn will remove 2382 * 'entry to counter' mapping. 2383 * No need to do it again. 2384 */ 2385 } 2386 } 2387 } 2388 2389 /* Find area of contiguous free entries of size 'nr'. 2390 * If not found return max contiguous free entries available. 2391 */ 2392 static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start, 2393 u16 nr, u16 *max_area) 2394 { 2395 u16 max_area_start = 0; 2396 u16 index, next, end; 2397 2398 *max_area = 0; 2399 2400 again: 2401 index = find_next_zero_bit(map, size, start); 2402 if (index >= size) 2403 return max_area_start; 2404 2405 end = ((index + nr) >= size) ? size : index + nr; 2406 next = find_next_bit(map, end, index); 2407 if (*max_area < (next - index)) { 2408 *max_area = next - index; 2409 max_area_start = index; 2410 } 2411 2412 if (next < end) { 2413 start = next + 1; 2414 goto again; 2415 } 2416 2417 return max_area_start; 2418 } 2419 2420 /* Find number of free MCAM entries available 2421 * within range i.e in between 'start' and 'end'. 2422 */ 2423 static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end) 2424 { 2425 u16 index, next; 2426 u16 fcnt = 0; 2427 2428 again: 2429 if (start >= end) 2430 return fcnt; 2431 2432 index = find_next_zero_bit(map, end, start); 2433 if (index >= end) 2434 return fcnt; 2435 2436 next = find_next_bit(map, end, index); 2437 if (next <= end) { 2438 fcnt += next - index; 2439 start = next + 1; 2440 goto again; 2441 } 2442 2443 fcnt += end - index; 2444 return fcnt; 2445 } 2446 2447 static void 2448 npc_get_mcam_search_range_priority(struct npc_mcam *mcam, 2449 struct npc_mcam_alloc_entry_req *req, 2450 u16 *start, u16 *end, bool *reverse) 2451 { 2452 u16 fcnt; 2453 2454 if (req->priority == NPC_MCAM_HIGHER_PRIO) 2455 goto hprio; 2456 2457 /* For a low priority entry allocation 2458 * - If reference entry is not in hprio zone then 2459 * search range: ref_entry to end. 2460 * - If reference entry is in hprio zone and if 2461 * request can be accomodated in non-hprio zone then 2462 * search range: 'start of middle zone' to 'end' 2463 * - else search in reverse, so that less number of hprio 2464 * zone entries are allocated. 2465 */ 2466 2467 *reverse = false; 2468 *start = req->ref_entry + 1; 2469 *end = mcam->bmap_entries; 2470 2471 if (req->ref_entry >= mcam->hprio_end) 2472 return; 2473 2474 fcnt = npc_mcam_get_free_count(mcam->bmap, 2475 mcam->hprio_end, mcam->bmap_entries); 2476 if (fcnt > req->count) 2477 *start = mcam->hprio_end; 2478 else 2479 *reverse = true; 2480 return; 2481 2482 hprio: 2483 /* For a high priority entry allocation, search is always 2484 * in reverse to preserve hprio zone entries. 2485 * - If reference entry is not in lprio zone then 2486 * search range: 0 to ref_entry. 2487 * - If reference entry is in lprio zone and if 2488 * request can be accomodated in middle zone then 2489 * search range: 'hprio_end' to 'lprio_start' 2490 */ 2491 2492 *reverse = true; 2493 *start = 0; 2494 *end = req->ref_entry; 2495 2496 if (req->ref_entry <= mcam->lprio_start) 2497 return; 2498 2499 fcnt = npc_mcam_get_free_count(mcam->bmap, 2500 mcam->hprio_end, mcam->lprio_start); 2501 if (fcnt < req->count) 2502 return; 2503 *start = mcam->hprio_end; 2504 *end = mcam->lprio_start; 2505 } 2506 2507 static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc, 2508 struct npc_mcam_alloc_entry_req *req, 2509 struct npc_mcam_alloc_entry_rsp *rsp) 2510 { 2511 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 2512 u16 fcnt, hp_fcnt, lp_fcnt; 2513 u16 start, end, index; 2514 int entry, next_start; 2515 bool reverse = false; 2516 unsigned long *bmap; 2517 u16 max_contig; 2518 2519 mutex_lock(&mcam->lock); 2520 2521 /* Check if there are any free entries */ 2522 if (!mcam->bmap_fcnt) { 2523 mutex_unlock(&mcam->lock); 2524 return NPC_MCAM_ALLOC_FAILED; 2525 } 2526 2527 /* MCAM entries are divided into high priority, middle and 2528 * low priority zones. Idea is to not allocate top and lower 2529 * most entries as much as possible, this is to increase 2530 * probability of honouring priority allocation requests. 2531 * 2532 * Two bitmaps are used for mcam entry management, 2533 * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'. 2534 * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'. 2535 * 2536 * Reverse bitmap is used to allocate entries 2537 * - when a higher priority entry is requested 2538 * - when available free entries are less. 2539 * Lower priority ones out of avaialble free entries are always 2540 * chosen when 'high vs low' question arises. 2541 */ 2542 2543 /* Get the search range for priority allocation request */ 2544 if (req->priority) { 2545 npc_get_mcam_search_range_priority(mcam, req, 2546 &start, &end, &reverse); 2547 goto alloc; 2548 } 2549 2550 /* For a VF base MCAM match rule is set by its PF. And all the 2551 * further MCAM rules installed by VF on its own are 2552 * concatenated with the base rule set by its PF. Hence PF entries 2553 * should be at lower priority compared to VF entries. Otherwise 2554 * base rule is hit always and rules installed by VF will be of 2555 * no use. Hence if the request is from PF and NOT a priority 2556 * allocation request then allocate low priority entries. 2557 */ 2558 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 2559 goto lprio_alloc; 2560 2561 /* Find out the search range for non-priority allocation request 2562 * 2563 * Get MCAM free entry count in middle zone. 2564 */ 2565 lp_fcnt = npc_mcam_get_free_count(mcam->bmap, 2566 mcam->lprio_start, 2567 mcam->bmap_entries); 2568 hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end); 2569 fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt; 2570 2571 /* Check if request can be accomodated in the middle zone */ 2572 if (fcnt > req->count) { 2573 start = mcam->hprio_end; 2574 end = mcam->lprio_start; 2575 } else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) { 2576 /* Expand search zone from half of hprio zone to 2577 * half of lprio zone. 2578 */ 2579 start = mcam->hprio_end / 2; 2580 end = mcam->bmap_entries - (mcam->lprio_count / 2); 2581 reverse = true; 2582 } else { 2583 /* Not enough free entries, search all entries in reverse, 2584 * so that low priority ones will get used up. 2585 */ 2586 lprio_alloc: 2587 reverse = true; 2588 start = 0; 2589 end = mcam->bmap_entries; 2590 } 2591 2592 alloc: 2593 if (reverse) { 2594 bmap = mcam->bmap_reverse; 2595 start = mcam->bmap_entries - start; 2596 end = mcam->bmap_entries - end; 2597 swap(start, end); 2598 } else { 2599 bmap = mcam->bmap; 2600 } 2601 2602 if (req->contig) { 2603 /* Allocate requested number of contiguous entries, if 2604 * unsuccessful find max contiguous entries available. 2605 */ 2606 index = npc_mcam_find_zero_area(bmap, end, start, 2607 req->count, &max_contig); 2608 rsp->count = max_contig; 2609 if (reverse) 2610 rsp->entry = mcam->bmap_entries - index - max_contig; 2611 else 2612 rsp->entry = index; 2613 } else { 2614 /* Allocate requested number of non-contiguous entries, 2615 * if unsuccessful allocate as many as possible. 2616 */ 2617 rsp->count = 0; 2618 next_start = start; 2619 for (entry = 0; entry < req->count; entry++) { 2620 index = find_next_zero_bit(bmap, end, next_start); 2621 if (index >= end) 2622 break; 2623 2624 next_start = start + (index - start) + 1; 2625 2626 /* Save the entry's index */ 2627 if (reverse) 2628 index = mcam->bmap_entries - index - 1; 2629 entry_list[entry] = index; 2630 rsp->count++; 2631 } 2632 } 2633 2634 /* If allocating requested no of entries is unsucessful, 2635 * expand the search range to full bitmap length and retry. 2636 */ 2637 if (!req->priority && (rsp->count < req->count) && 2638 ((end - start) != mcam->bmap_entries)) { 2639 reverse = true; 2640 start = 0; 2641 end = mcam->bmap_entries; 2642 goto alloc; 2643 } 2644 2645 /* For priority entry allocation requests, if allocation is 2646 * failed then expand search to max possible range and retry. 2647 */ 2648 if (req->priority && rsp->count < req->count) { 2649 if (req->priority == NPC_MCAM_LOWER_PRIO && 2650 (start != (req->ref_entry + 1))) { 2651 start = req->ref_entry + 1; 2652 end = mcam->bmap_entries; 2653 reverse = false; 2654 goto alloc; 2655 } else if ((req->priority == NPC_MCAM_HIGHER_PRIO) && 2656 ((end - start) != req->ref_entry)) { 2657 start = 0; 2658 end = req->ref_entry; 2659 reverse = true; 2660 goto alloc; 2661 } 2662 } 2663 2664 /* Copy MCAM entry indices into mbox response entry_list. 2665 * Requester always expects indices in ascending order, so 2666 * reverse the list if reverse bitmap is used for allocation. 2667 */ 2668 if (!req->contig && rsp->count) { 2669 index = 0; 2670 for (entry = rsp->count - 1; entry >= 0; entry--) { 2671 if (reverse) 2672 rsp->entry_list[index++] = entry_list[entry]; 2673 else 2674 rsp->entry_list[entry] = entry_list[entry]; 2675 } 2676 } 2677 2678 /* Mark the allocated entries as used and set nixlf mapping */ 2679 for (entry = 0; entry < rsp->count; entry++) { 2680 index = req->contig ? 2681 (rsp->entry + entry) : rsp->entry_list[entry]; 2682 npc_mcam_set_bit(mcam, index); 2683 mcam->entry2pfvf_map[index] = pcifunc; 2684 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP; 2685 } 2686 2687 /* Update available free count in mbox response */ 2688 rsp->free_count = mcam->bmap_fcnt; 2689 2690 mutex_unlock(&mcam->lock); 2691 return 0; 2692 } 2693 2694 /* Marks bitmaps to reserved the mcam slot */ 2695 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx) 2696 { 2697 struct npc_mcam *mcam = &rvu->hw->mcam; 2698 2699 npc_mcam_set_bit(mcam, entry_idx); 2700 } 2701 2702 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu, 2703 struct npc_mcam_alloc_entry_req *req, 2704 struct npc_mcam_alloc_entry_rsp *rsp) 2705 { 2706 struct npc_mcam *mcam = &rvu->hw->mcam; 2707 u16 pcifunc = req->hdr.pcifunc; 2708 int blkaddr; 2709 2710 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2711 if (blkaddr < 0) 2712 return NPC_MCAM_INVALID_REQ; 2713 2714 rsp->entry = NPC_MCAM_ENTRY_INVALID; 2715 rsp->free_count = 0; 2716 2717 /* Check if ref_entry is greater that the range 2718 * then set it to max value. 2719 */ 2720 if (req->ref_entry > mcam->bmap_entries) 2721 req->ref_entry = mcam->bmap_entries; 2722 2723 /* ref_entry can't be '0' if requested priority is high. 2724 * Can't be last entry if requested priority is low. 2725 */ 2726 if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) || 2727 ((req->ref_entry == mcam->bmap_entries) && 2728 req->priority == NPC_MCAM_LOWER_PRIO)) 2729 return NPC_MCAM_INVALID_REQ; 2730 2731 /* Since list of allocated indices needs to be sent to requester, 2732 * max number of non-contiguous entries per mbox msg is limited. 2733 */ 2734 if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES) { 2735 dev_err(rvu->dev, 2736 "%s: %d Non-contiguous MCAM entries requested is more than max (%d) allowed\n", 2737 __func__, req->count, NPC_MAX_NONCONTIG_ENTRIES); 2738 return NPC_MCAM_INVALID_REQ; 2739 } 2740 2741 /* Alloc request from PFFUNC with no NIXLF attached should be denied */ 2742 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) 2743 return NPC_MCAM_ALLOC_DENIED; 2744 2745 return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp); 2746 } 2747 2748 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu, 2749 struct npc_mcam_free_entry_req *req, 2750 struct msg_rsp *rsp) 2751 { 2752 struct npc_mcam *mcam = &rvu->hw->mcam; 2753 u16 pcifunc = req->hdr.pcifunc; 2754 int blkaddr, rc = 0; 2755 u16 cntr; 2756 2757 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2758 if (blkaddr < 0) 2759 return NPC_MCAM_INVALID_REQ; 2760 2761 /* Free request from PFFUNC with no NIXLF attached, ignore */ 2762 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) 2763 return NPC_MCAM_INVALID_REQ; 2764 2765 mutex_lock(&mcam->lock); 2766 2767 if (req->all) 2768 goto free_all; 2769 2770 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2771 if (rc) 2772 goto exit; 2773 2774 mcam->entry2pfvf_map[req->entry] = NPC_MCAM_INVALID_MAP; 2775 mcam->entry2target_pffunc[req->entry] = 0x0; 2776 npc_mcam_clear_bit(mcam, req->entry); 2777 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false); 2778 2779 /* Update entry2counter mapping */ 2780 cntr = mcam->entry2cntr_map[req->entry]; 2781 if (cntr != NPC_MCAM_INVALID_MAP) 2782 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2783 req->entry, cntr); 2784 2785 goto exit; 2786 2787 free_all: 2788 /* Free up all entries allocated to requesting PFFUNC */ 2789 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); 2790 exit: 2791 mutex_unlock(&mcam->lock); 2792 return rc; 2793 } 2794 2795 int rvu_mbox_handler_npc_mcam_read_entry(struct rvu *rvu, 2796 struct npc_mcam_read_entry_req *req, 2797 struct npc_mcam_read_entry_rsp *rsp) 2798 { 2799 struct npc_mcam *mcam = &rvu->hw->mcam; 2800 u16 pcifunc = req->hdr.pcifunc; 2801 int blkaddr, rc; 2802 2803 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2804 if (blkaddr < 0) 2805 return NPC_MCAM_INVALID_REQ; 2806 2807 mutex_lock(&mcam->lock); 2808 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2809 if (!rc) { 2810 npc_read_mcam_entry(rvu, mcam, blkaddr, req->entry, 2811 &rsp->entry_data, 2812 &rsp->intf, &rsp->enable); 2813 } 2814 2815 mutex_unlock(&mcam->lock); 2816 return rc; 2817 } 2818 2819 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu, 2820 struct npc_mcam_write_entry_req *req, 2821 struct msg_rsp *rsp) 2822 { 2823 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 2824 struct npc_mcam *mcam = &rvu->hw->mcam; 2825 u16 pcifunc = req->hdr.pcifunc; 2826 int blkaddr, rc; 2827 u8 nix_intf; 2828 2829 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2830 if (blkaddr < 0) 2831 return NPC_MCAM_INVALID_REQ; 2832 2833 mutex_lock(&mcam->lock); 2834 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2835 if (rc) 2836 goto exit; 2837 2838 if (req->set_cntr && 2839 npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) { 2840 rc = NPC_MCAM_INVALID_REQ; 2841 goto exit; 2842 } 2843 2844 if (!is_npc_interface_valid(rvu, req->intf)) { 2845 rc = NPC_MCAM_INVALID_REQ; 2846 goto exit; 2847 } 2848 2849 if (is_npc_intf_tx(req->intf)) 2850 nix_intf = pfvf->nix_tx_intf; 2851 else 2852 nix_intf = pfvf->nix_rx_intf; 2853 2854 if (!is_pffunc_af(pcifunc) && 2855 npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf, pcifunc)) { 2856 rc = NPC_MCAM_INVALID_REQ; 2857 goto exit; 2858 } 2859 2860 /* For AF installed rules, the nix_intf should be set to target NIX */ 2861 if (is_pffunc_af(req->hdr.pcifunc)) 2862 nix_intf = req->intf; 2863 2864 npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, nix_intf, 2865 &req->entry_data, req->enable_entry); 2866 2867 if (req->set_cntr) 2868 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2869 req->entry, req->cntr); 2870 2871 rc = 0; 2872 exit: 2873 mutex_unlock(&mcam->lock); 2874 return rc; 2875 } 2876 2877 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu, 2878 struct npc_mcam_ena_dis_entry_req *req, 2879 struct msg_rsp *rsp) 2880 { 2881 struct npc_mcam *mcam = &rvu->hw->mcam; 2882 u16 pcifunc = req->hdr.pcifunc; 2883 int blkaddr, rc; 2884 2885 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2886 if (blkaddr < 0) 2887 return NPC_MCAM_INVALID_REQ; 2888 2889 mutex_lock(&mcam->lock); 2890 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2891 mutex_unlock(&mcam->lock); 2892 if (rc) 2893 return rc; 2894 2895 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true); 2896 2897 return 0; 2898 } 2899 2900 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu, 2901 struct npc_mcam_ena_dis_entry_req *req, 2902 struct msg_rsp *rsp) 2903 { 2904 struct npc_mcam *mcam = &rvu->hw->mcam; 2905 u16 pcifunc = req->hdr.pcifunc; 2906 int blkaddr, rc; 2907 2908 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2909 if (blkaddr < 0) 2910 return NPC_MCAM_INVALID_REQ; 2911 2912 mutex_lock(&mcam->lock); 2913 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2914 mutex_unlock(&mcam->lock); 2915 if (rc) 2916 return rc; 2917 2918 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false); 2919 2920 return 0; 2921 } 2922 2923 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu, 2924 struct npc_mcam_shift_entry_req *req, 2925 struct npc_mcam_shift_entry_rsp *rsp) 2926 { 2927 struct npc_mcam *mcam = &rvu->hw->mcam; 2928 u16 pcifunc = req->hdr.pcifunc; 2929 u16 old_entry, new_entry; 2930 int blkaddr, rc = 0; 2931 u16 index, cntr; 2932 2933 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2934 if (blkaddr < 0) 2935 return NPC_MCAM_INVALID_REQ; 2936 2937 if (req->shift_count > NPC_MCAM_MAX_SHIFTS) 2938 return NPC_MCAM_INVALID_REQ; 2939 2940 mutex_lock(&mcam->lock); 2941 for (index = 0; index < req->shift_count; index++) { 2942 old_entry = req->curr_entry[index]; 2943 new_entry = req->new_entry[index]; 2944 2945 /* Check if both old and new entries are valid and 2946 * does belong to this PFFUNC or not. 2947 */ 2948 rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry); 2949 if (rc) 2950 break; 2951 2952 rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry); 2953 if (rc) 2954 break; 2955 2956 /* new_entry should not have a counter mapped */ 2957 if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) { 2958 rc = NPC_MCAM_PERM_DENIED; 2959 break; 2960 } 2961 2962 /* Disable the new_entry */ 2963 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false); 2964 2965 /* Copy rule from old entry to new entry */ 2966 npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry); 2967 2968 /* Copy counter mapping, if any */ 2969 cntr = mcam->entry2cntr_map[old_entry]; 2970 if (cntr != NPC_MCAM_INVALID_MAP) { 2971 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2972 old_entry, cntr); 2973 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2974 new_entry, cntr); 2975 } 2976 2977 /* Enable new_entry and disable old_entry */ 2978 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true); 2979 npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false); 2980 } 2981 2982 /* If shift has failed then report the failed index */ 2983 if (index != req->shift_count) { 2984 rc = NPC_MCAM_PERM_DENIED; 2985 rsp->failed_entry_idx = index; 2986 } 2987 2988 mutex_unlock(&mcam->lock); 2989 return rc; 2990 } 2991 2992 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, 2993 struct npc_mcam_alloc_counter_req *req, 2994 struct npc_mcam_alloc_counter_rsp *rsp) 2995 { 2996 struct npc_mcam *mcam = &rvu->hw->mcam; 2997 u16 pcifunc = req->hdr.pcifunc; 2998 u16 max_contig, cntr; 2999 int blkaddr, index; 3000 3001 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3002 if (blkaddr < 0) 3003 return NPC_MCAM_INVALID_REQ; 3004 3005 /* If the request is from a PFFUNC with no NIXLF attached, ignore */ 3006 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) 3007 return NPC_MCAM_INVALID_REQ; 3008 3009 /* Since list of allocated counter IDs needs to be sent to requester, 3010 * max number of non-contiguous counters per mbox msg is limited. 3011 */ 3012 if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS) 3013 return NPC_MCAM_INVALID_REQ; 3014 3015 mutex_lock(&mcam->lock); 3016 3017 /* Check if unused counters are available or not */ 3018 if (!rvu_rsrc_free_count(&mcam->counters)) { 3019 mutex_unlock(&mcam->lock); 3020 return NPC_MCAM_ALLOC_FAILED; 3021 } 3022 3023 rsp->count = 0; 3024 3025 if (req->contig) { 3026 /* Allocate requested number of contiguous counters, if 3027 * unsuccessful find max contiguous entries available. 3028 */ 3029 index = npc_mcam_find_zero_area(mcam->counters.bmap, 3030 mcam->counters.max, 0, 3031 req->count, &max_contig); 3032 rsp->count = max_contig; 3033 rsp->cntr = index; 3034 for (cntr = index; cntr < (index + max_contig); cntr++) { 3035 __set_bit(cntr, mcam->counters.bmap); 3036 mcam->cntr2pfvf_map[cntr] = pcifunc; 3037 } 3038 } else { 3039 /* Allocate requested number of non-contiguous counters, 3040 * if unsuccessful allocate as many as possible. 3041 */ 3042 for (cntr = 0; cntr < req->count; cntr++) { 3043 index = rvu_alloc_rsrc(&mcam->counters); 3044 if (index < 0) 3045 break; 3046 rsp->cntr_list[cntr] = index; 3047 rsp->count++; 3048 mcam->cntr2pfvf_map[index] = pcifunc; 3049 } 3050 } 3051 3052 mutex_unlock(&mcam->lock); 3053 return 0; 3054 } 3055 3056 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, 3057 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) 3058 { 3059 struct npc_mcam *mcam = &rvu->hw->mcam; 3060 u16 index, entry = 0; 3061 int blkaddr, err; 3062 3063 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3064 if (blkaddr < 0) 3065 return NPC_MCAM_INVALID_REQ; 3066 3067 mutex_lock(&mcam->lock); 3068 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3069 if (err) { 3070 mutex_unlock(&mcam->lock); 3071 return err; 3072 } 3073 3074 /* Mark counter as free/unused */ 3075 mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP; 3076 rvu_free_rsrc(&mcam->counters, req->cntr); 3077 3078 /* Disable all MCAM entry's stats which are using this counter */ 3079 while (entry < mcam->bmap_entries) { 3080 if (!mcam->cntr_refcnt[req->cntr]) 3081 break; 3082 3083 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry); 3084 if (index >= mcam->bmap_entries) 3085 break; 3086 entry = index + 1; 3087 if (mcam->entry2cntr_map[index] != req->cntr) 3088 continue; 3089 3090 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 3091 index, req->cntr); 3092 } 3093 3094 mutex_unlock(&mcam->lock); 3095 return 0; 3096 } 3097 3098 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, 3099 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp) 3100 { 3101 struct npc_mcam *mcam = &rvu->hw->mcam; 3102 u16 index, entry = 0; 3103 int blkaddr, rc; 3104 3105 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3106 if (blkaddr < 0) 3107 return NPC_MCAM_INVALID_REQ; 3108 3109 mutex_lock(&mcam->lock); 3110 rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3111 if (rc) 3112 goto exit; 3113 3114 /* Unmap the MCAM entry and counter */ 3115 if (!req->all) { 3116 rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry); 3117 if (rc) 3118 goto exit; 3119 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 3120 req->entry, req->cntr); 3121 goto exit; 3122 } 3123 3124 /* Disable all MCAM entry's stats which are using this counter */ 3125 while (entry < mcam->bmap_entries) { 3126 if (!mcam->cntr_refcnt[req->cntr]) 3127 break; 3128 3129 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry); 3130 if (index >= mcam->bmap_entries) 3131 break; 3132 entry = index + 1; 3133 3134 if (mcam->entry2cntr_map[index] != req->cntr) 3135 continue; 3136 3137 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 3138 index, req->cntr); 3139 } 3140 exit: 3141 mutex_unlock(&mcam->lock); 3142 return rc; 3143 } 3144 3145 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu, 3146 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) 3147 { 3148 struct npc_mcam *mcam = &rvu->hw->mcam; 3149 int blkaddr, err; 3150 3151 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3152 if (blkaddr < 0) 3153 return NPC_MCAM_INVALID_REQ; 3154 3155 mutex_lock(&mcam->lock); 3156 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3157 mutex_unlock(&mcam->lock); 3158 if (err) 3159 return err; 3160 3161 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00); 3162 3163 return 0; 3164 } 3165 3166 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu, 3167 struct npc_mcam_oper_counter_req *req, 3168 struct npc_mcam_oper_counter_rsp *rsp) 3169 { 3170 struct npc_mcam *mcam = &rvu->hw->mcam; 3171 int blkaddr, err; 3172 3173 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3174 if (blkaddr < 0) 3175 return NPC_MCAM_INVALID_REQ; 3176 3177 mutex_lock(&mcam->lock); 3178 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3179 mutex_unlock(&mcam->lock); 3180 if (err) 3181 return err; 3182 3183 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr)); 3184 rsp->stat &= BIT_ULL(48) - 1; 3185 3186 return 0; 3187 } 3188 3189 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu, 3190 struct npc_mcam_alloc_and_write_entry_req *req, 3191 struct npc_mcam_alloc_and_write_entry_rsp *rsp) 3192 { 3193 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 3194 struct npc_mcam_alloc_counter_req cntr_req; 3195 struct npc_mcam_alloc_counter_rsp cntr_rsp; 3196 struct npc_mcam_alloc_entry_req entry_req; 3197 struct npc_mcam_alloc_entry_rsp entry_rsp; 3198 struct npc_mcam *mcam = &rvu->hw->mcam; 3199 u16 entry = NPC_MCAM_ENTRY_INVALID; 3200 u16 cntr = NPC_MCAM_ENTRY_INVALID; 3201 int blkaddr, rc; 3202 u8 nix_intf; 3203 3204 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3205 if (blkaddr < 0) 3206 return NPC_MCAM_INVALID_REQ; 3207 3208 if (!is_npc_interface_valid(rvu, req->intf)) 3209 return NPC_MCAM_INVALID_REQ; 3210 3211 if (npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf, 3212 req->hdr.pcifunc)) 3213 return NPC_MCAM_INVALID_REQ; 3214 3215 /* Try to allocate a MCAM entry */ 3216 entry_req.hdr.pcifunc = req->hdr.pcifunc; 3217 entry_req.contig = true; 3218 entry_req.priority = req->priority; 3219 entry_req.ref_entry = req->ref_entry; 3220 entry_req.count = 1; 3221 3222 rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, 3223 &entry_req, &entry_rsp); 3224 if (rc) 3225 return rc; 3226 3227 if (!entry_rsp.count) 3228 return NPC_MCAM_ALLOC_FAILED; 3229 3230 entry = entry_rsp.entry; 3231 3232 if (!req->alloc_cntr) 3233 goto write_entry; 3234 3235 /* Now allocate counter */ 3236 cntr_req.hdr.pcifunc = req->hdr.pcifunc; 3237 cntr_req.contig = true; 3238 cntr_req.count = 1; 3239 3240 rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp); 3241 if (rc) { 3242 /* Free allocated MCAM entry */ 3243 mutex_lock(&mcam->lock); 3244 mcam->entry2pfvf_map[entry] = NPC_MCAM_INVALID_MAP; 3245 npc_mcam_clear_bit(mcam, entry); 3246 mutex_unlock(&mcam->lock); 3247 return rc; 3248 } 3249 3250 cntr = cntr_rsp.cntr; 3251 3252 write_entry: 3253 mutex_lock(&mcam->lock); 3254 3255 if (is_npc_intf_tx(req->intf)) 3256 nix_intf = pfvf->nix_tx_intf; 3257 else 3258 nix_intf = pfvf->nix_rx_intf; 3259 3260 npc_config_mcam_entry(rvu, mcam, blkaddr, entry, nix_intf, 3261 &req->entry_data, req->enable_entry); 3262 3263 if (req->alloc_cntr) 3264 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr); 3265 mutex_unlock(&mcam->lock); 3266 3267 rsp->entry = entry; 3268 rsp->cntr = cntr; 3269 3270 return 0; 3271 } 3272 3273 #define GET_KEX_CFG(intf) \ 3274 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf)) 3275 3276 #define GET_KEX_FLAGS(ld) \ 3277 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld)) 3278 3279 #define GET_KEX_LD(intf, lid, lt, ld) \ 3280 rvu_read64(rvu, BLKADDR_NPC, \ 3281 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld)) 3282 3283 #define GET_KEX_LDFLAGS(intf, ld, fl) \ 3284 rvu_read64(rvu, BLKADDR_NPC, \ 3285 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl)) 3286 3287 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req, 3288 struct npc_get_kex_cfg_rsp *rsp) 3289 { 3290 int lid, lt, ld, fl; 3291 3292 rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX); 3293 rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX); 3294 for (lid = 0; lid < NPC_MAX_LID; lid++) { 3295 for (lt = 0; lt < NPC_MAX_LT; lt++) { 3296 for (ld = 0; ld < NPC_MAX_LD; ld++) { 3297 rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] = 3298 GET_KEX_LD(NIX_INTF_RX, lid, lt, ld); 3299 rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] = 3300 GET_KEX_LD(NIX_INTF_TX, lid, lt, ld); 3301 } 3302 } 3303 } 3304 for (ld = 0; ld < NPC_MAX_LD; ld++) 3305 rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld); 3306 3307 for (ld = 0; ld < NPC_MAX_LD; ld++) { 3308 for (fl = 0; fl < NPC_MAX_LFL; fl++) { 3309 rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] = 3310 GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl); 3311 rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] = 3312 GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl); 3313 } 3314 } 3315 memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN); 3316 return 0; 3317 } 3318 3319 static int 3320 npc_set_var_len_offset_pkind(struct rvu *rvu, u16 pcifunc, u64 pkind, 3321 u8 var_len_off, u8 var_len_off_mask, u8 shift_dir) 3322 { 3323 struct npc_kpu_action0 *act0; 3324 u8 shift_count = 0; 3325 int blkaddr; 3326 u64 val; 3327 3328 if (!var_len_off_mask) 3329 return -EINVAL; 3330 3331 if (var_len_off_mask != 0xff) { 3332 if (shift_dir) 3333 shift_count = __ffs(var_len_off_mask); 3334 else 3335 shift_count = (8 - __fls(var_len_off_mask)); 3336 } 3337 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc); 3338 if (blkaddr < 0) { 3339 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 3340 return -EINVAL; 3341 } 3342 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind)); 3343 act0 = (struct npc_kpu_action0 *)&val; 3344 act0->var_len_shift = shift_count; 3345 act0->var_len_right = shift_dir; 3346 act0->var_len_mask = var_len_off_mask; 3347 act0->var_len_offset = var_len_off; 3348 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val); 3349 return 0; 3350 } 3351 3352 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 3353 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 3354 u8 shift_dir) 3355 3356 { 3357 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 3358 int blkaddr, nixlf, rc, intf_mode; 3359 int pf = rvu_get_pf(pcifunc); 3360 u64 rxpkind, txpkind; 3361 u8 cgx_id, lmac_id; 3362 3363 /* use default pkind to disable edsa/higig */ 3364 rxpkind = rvu_npc_get_pkind(rvu, pf); 3365 txpkind = NPC_TX_DEF_PKIND; 3366 intf_mode = NPC_INTF_MODE_DEF; 3367 3368 if (mode & OTX2_PRIV_FLAGS_CUSTOM) { 3369 if (pkind == NPC_RX_CUSTOM_PRE_L2_PKIND) { 3370 rc = npc_set_var_len_offset_pkind(rvu, pcifunc, pkind, 3371 var_len_off, 3372 var_len_off_mask, 3373 shift_dir); 3374 if (rc) 3375 return rc; 3376 } 3377 rxpkind = pkind; 3378 txpkind = pkind; 3379 } 3380 3381 if (dir & PKIND_RX) { 3382 /* rx pkind set req valid only for cgx mapped PFs */ 3383 if (!is_cgx_config_permitted(rvu, pcifunc)) 3384 return 0; 3385 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 3386 3387 rc = cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, 3388 rxpkind); 3389 if (rc) 3390 return rc; 3391 } 3392 3393 if (dir & PKIND_TX) { 3394 /* Tx pkind set request valid if PCIFUNC has NIXLF attached */ 3395 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3396 if (rc) 3397 return rc; 3398 3399 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), 3400 txpkind); 3401 } 3402 3403 pfvf->intf_mode = intf_mode; 3404 return 0; 3405 } 3406 3407 int rvu_mbox_handler_npc_set_pkind(struct rvu *rvu, struct npc_set_pkind *req, 3408 struct msg_rsp *rsp) 3409 { 3410 return rvu_npc_set_parse_mode(rvu, req->hdr.pcifunc, req->mode, 3411 req->dir, req->pkind, req->var_len_off, 3412 req->var_len_off_mask, req->shift_dir); 3413 } 3414 3415 int rvu_mbox_handler_npc_read_base_steer_rule(struct rvu *rvu, 3416 struct msg_req *req, 3417 struct npc_mcam_read_base_rule_rsp *rsp) 3418 { 3419 struct npc_mcam *mcam = &rvu->hw->mcam; 3420 int index, blkaddr, nixlf, rc = 0; 3421 u16 pcifunc = req->hdr.pcifunc; 3422 struct rvu_pfvf *pfvf; 3423 u8 intf, enable; 3424 3425 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3426 if (blkaddr < 0) 3427 return NPC_MCAM_INVALID_REQ; 3428 3429 /* Return the channel number in case of PF */ 3430 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) { 3431 pfvf = rvu_get_pfvf(rvu, pcifunc); 3432 rsp->entry.kw[0] = pfvf->rx_chan_base; 3433 rsp->entry.kw_mask[0] = 0xFFFULL; 3434 goto out; 3435 } 3436 3437 /* Find the pkt steering rule installed by PF to this VF */ 3438 mutex_lock(&mcam->lock); 3439 for (index = 0; index < mcam->bmap_entries; index++) { 3440 if (mcam->entry2target_pffunc[index] == pcifunc) 3441 goto read_entry; 3442 } 3443 3444 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 3445 if (rc < 0) { 3446 mutex_unlock(&mcam->lock); 3447 goto out; 3448 } 3449 /* Read the default ucast entry if there is no pkt steering rule */ 3450 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, 3451 NIXLF_UCAST_ENTRY); 3452 read_entry: 3453 /* Read the mcam entry */ 3454 npc_read_mcam_entry(rvu, mcam, blkaddr, index, &rsp->entry, &intf, 3455 &enable); 3456 mutex_unlock(&mcam->lock); 3457 out: 3458 return rc; 3459 } 3460 3461 int rvu_mbox_handler_npc_mcam_entry_stats(struct rvu *rvu, 3462 struct npc_mcam_get_stats_req *req, 3463 struct npc_mcam_get_stats_rsp *rsp) 3464 { 3465 struct npc_mcam *mcam = &rvu->hw->mcam; 3466 u16 index, cntr; 3467 int blkaddr; 3468 u64 regval; 3469 u32 bank; 3470 3471 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3472 if (blkaddr < 0) 3473 return NPC_MCAM_INVALID_REQ; 3474 3475 mutex_lock(&mcam->lock); 3476 3477 index = req->entry & (mcam->banksize - 1); 3478 bank = npc_get_bank(mcam, req->entry); 3479 3480 /* read MCAM entry STAT_ACT register */ 3481 regval = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank)); 3482 3483 if (!(regval & rvu->hw->npc_stat_ena)) { 3484 rsp->stat_ena = 0; 3485 mutex_unlock(&mcam->lock); 3486 return 0; 3487 } 3488 3489 cntr = regval & 0x1FF; 3490 3491 rsp->stat_ena = 1; 3492 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(cntr)); 3493 rsp->stat &= BIT_ULL(48) - 1; 3494 3495 mutex_unlock(&mcam->lock); 3496 3497 return 0; 3498 } 3499