1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 14 #include "rvu_struct.h" 15 #include "rvu_reg.h" 16 #include "rvu.h" 17 #include "npc.h" 18 #include "npc_profile.h" 19 20 #define RSVD_MCAM_ENTRIES_PER_PF 2 /* Bcast & Promisc */ 21 #define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */ 22 23 #define NIXLF_UCAST_ENTRY 0 24 #define NIXLF_BCAST_ENTRY 1 25 #define NIXLF_PROMISC_ENTRY 2 26 27 #define NPC_PARSE_RESULT_DMAC_OFFSET 8 28 29 struct mcam_entry { 30 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 31 u64 kw[NPC_MAX_KWS_IN_KEY]; 32 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 33 u64 action; 34 u64 vtag_action; 35 }; 36 37 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf) 38 { 39 int blkaddr; 40 u64 val = 0; 41 42 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 43 if (blkaddr < 0) 44 return; 45 46 /* Config CPI base for the PKIND */ 47 val = pkind | 1ULL << 62; 48 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); 49 } 50 51 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf) 52 { 53 struct npc_pkind *pkind = &rvu->hw->pkind; 54 u32 map; 55 int i; 56 57 for (i = 0; i < pkind->rsrc.max; i++) { 58 map = pkind->pfchan_map[i]; 59 if (((map >> 16) & 0x3F) == pf) 60 return i; 61 } 62 return -1; 63 } 64 65 static int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, 66 u16 pcifunc, int nixlf, int type) 67 { 68 int pf = rvu_get_pf(pcifunc); 69 int index; 70 71 /* Check if this is for a PF */ 72 if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) { 73 /* Reserved entries exclude PF0 */ 74 pf--; 75 index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF); 76 /* Broadcast address matching entry should be first so 77 * that the packet can be replicated to all VFs. 78 */ 79 if (type == NIXLF_BCAST_ENTRY) 80 return index; 81 else if (type == NIXLF_PROMISC_ENTRY) 82 return index + 1; 83 } 84 85 return (mcam->nixlf_offset + (nixlf * RSVD_MCAM_ENTRIES_PER_NIXLF)); 86 } 87 88 static int npc_get_bank(struct npc_mcam *mcam, int index) 89 { 90 int bank = index / mcam->banksize; 91 92 /* 0,1 & 2,3 banks are combined for this keysize */ 93 if (mcam->keysize == NPC_MCAM_KEY_X2) 94 return bank ? 2 : 0; 95 96 return bank; 97 } 98 99 static bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, 100 int blkaddr, int index) 101 { 102 int bank = npc_get_bank(mcam, index); 103 u64 cfg; 104 105 index &= (mcam->banksize - 1); 106 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank)); 107 return (cfg & 1); 108 } 109 110 static void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 111 int blkaddr, int index, bool enable) 112 { 113 int bank = npc_get_bank(mcam, index); 114 int actbank = bank; 115 116 index &= (mcam->banksize - 1); 117 for (; bank < (actbank + mcam->banks_per_entry); bank++) { 118 rvu_write64(rvu, blkaddr, 119 NPC_AF_MCAMEX_BANKX_CFG(index, bank), 120 enable ? 1 : 0); 121 } 122 } 123 124 static void npc_get_keyword(struct mcam_entry *entry, int idx, 125 u64 *cam0, u64 *cam1) 126 { 127 u64 kw_mask = 0x00; 128 129 #define CAM_MASK(n) (BIT_ULL(n) - 1) 130 131 /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and 132 * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1. 133 * 134 * Also, only 48 bits of BANKX_CAMX_W1 are valid. 135 */ 136 switch (idx) { 137 case 0: 138 /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */ 139 *cam1 = entry->kw[0]; 140 kw_mask = entry->kw_mask[0]; 141 break; 142 case 1: 143 /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */ 144 *cam1 = entry->kw[1] & CAM_MASK(48); 145 kw_mask = entry->kw_mask[1] & CAM_MASK(48); 146 break; 147 case 2: 148 /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48> 149 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0> 150 */ 151 *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16); 152 *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16); 153 kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16); 154 kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16); 155 break; 156 case 3: 157 /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48> 158 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0> 159 */ 160 *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16); 161 *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16); 162 kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16); 163 kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16); 164 break; 165 case 4: 166 /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32> 167 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0> 168 */ 169 *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32); 170 *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32); 171 kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32); 172 kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32); 173 break; 174 case 5: 175 /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32> 176 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0> 177 */ 178 *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32); 179 *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32); 180 kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32); 181 kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32); 182 break; 183 case 6: 184 /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16> 185 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0> 186 */ 187 *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48); 188 *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48); 189 kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48); 190 kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48); 191 break; 192 case 7: 193 /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */ 194 *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48); 195 kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48); 196 break; 197 } 198 199 *cam1 &= kw_mask; 200 *cam0 = ~*cam1 & kw_mask; 201 } 202 203 static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 204 int blkaddr, int index, u8 intf, 205 struct mcam_entry *entry, bool enable) 206 { 207 int bank = npc_get_bank(mcam, index); 208 int kw = 0, actbank, actindex; 209 u64 cam0, cam1; 210 211 actbank = bank; /* Save bank id, to set action later on */ 212 actindex = index; 213 index &= (mcam->banksize - 1); 214 215 /* CAM1 takes the comparison value and 216 * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'. 217 * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0 218 * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1 219 * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare. 220 */ 221 for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) { 222 /* Interface should be set in all banks */ 223 rvu_write64(rvu, blkaddr, 224 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 225 intf); 226 rvu_write64(rvu, blkaddr, 227 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 228 ~intf & 0x3); 229 230 /* Set the match key */ 231 npc_get_keyword(entry, kw, &cam0, &cam1); 232 rvu_write64(rvu, blkaddr, 233 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1); 234 rvu_write64(rvu, blkaddr, 235 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0); 236 237 npc_get_keyword(entry, kw + 1, &cam0, &cam1); 238 rvu_write64(rvu, blkaddr, 239 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1); 240 rvu_write64(rvu, blkaddr, 241 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0); 242 } 243 244 /* Set 'action' */ 245 rvu_write64(rvu, blkaddr, 246 NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action); 247 248 /* Set TAG 'action' */ 249 rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank), 250 entry->vtag_action); 251 252 /* Enable the entry */ 253 if (enable) 254 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true); 255 else 256 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false); 257 } 258 259 static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 260 int blkaddr, int index) 261 { 262 int bank = npc_get_bank(mcam, index); 263 264 index &= (mcam->banksize - 1); 265 return rvu_read64(rvu, blkaddr, 266 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 267 } 268 269 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 270 int nixlf, u64 chan, u8 *mac_addr) 271 { 272 struct npc_mcam *mcam = &rvu->hw->mcam; 273 struct mcam_entry entry = { {0} }; 274 struct nix_rx_action action; 275 int blkaddr, index, kwi; 276 u64 mac = 0; 277 278 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 279 if (blkaddr < 0) 280 return; 281 282 for (index = ETH_ALEN - 1; index >= 0; index--) 283 mac |= ((u64)*mac_addr++) << (8 * index); 284 285 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 286 nixlf, NIXLF_UCAST_ENTRY); 287 288 /* Match ingress channel and DMAC */ 289 entry.kw[0] = chan; 290 entry.kw_mask[0] = 0xFFFULL; 291 292 kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64); 293 entry.kw[kwi] = mac; 294 entry.kw_mask[kwi] = BIT_ULL(48) - 1; 295 296 /* Don't change the action if entry is already enabled 297 * Otherwise RSS action may get overwritten. 298 */ 299 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) { 300 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 301 blkaddr, index); 302 } else { 303 *(u64 *)&action = 0x00; 304 action.op = NIX_RX_ACTIONOP_UCAST; 305 action.pf_func = pcifunc; 306 } 307 308 entry.action = *(u64 *)&action; 309 npc_config_mcam_entry(rvu, mcam, blkaddr, index, 310 NIX_INTF_RX, &entry, true); 311 } 312 313 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 314 int nixlf, u64 chan, bool allmulti) 315 { 316 struct npc_mcam *mcam = &rvu->hw->mcam; 317 struct mcam_entry entry = { {0} }; 318 struct nix_rx_action action; 319 int blkaddr, index, kwi; 320 321 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 322 if (blkaddr < 0) 323 return; 324 325 /* Only PF or AF VF can add a promiscuous entry */ 326 if (pcifunc & RVU_PFVF_FUNC_MASK) 327 return; 328 329 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 330 nixlf, NIXLF_PROMISC_ENTRY); 331 332 entry.kw[0] = chan; 333 entry.kw_mask[0] = 0xFFFULL; 334 335 if (allmulti) { 336 kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64); 337 entry.kw[kwi] = BIT_ULL(40); /* LSB bit of 1st byte in DMAC */ 338 entry.kw_mask[kwi] = BIT_ULL(40); 339 } 340 341 *(u64 *)&action = 0x00; 342 action.op = NIX_RX_ACTIONOP_UCAST; 343 action.pf_func = pcifunc; 344 345 entry.action = *(u64 *)&action; 346 npc_config_mcam_entry(rvu, mcam, blkaddr, index, 347 NIX_INTF_RX, &entry, true); 348 } 349 350 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf) 351 { 352 struct npc_mcam *mcam = &rvu->hw->mcam; 353 int blkaddr, index; 354 355 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 356 if (blkaddr < 0) 357 return; 358 359 /* Only PF's have a promiscuous entry */ 360 if (pcifunc & RVU_PFVF_FUNC_MASK) 361 return; 362 363 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 364 nixlf, NIXLF_PROMISC_ENTRY); 365 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); 366 } 367 368 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 369 int nixlf, u64 chan) 370 { 371 struct npc_mcam *mcam = &rvu->hw->mcam; 372 struct mcam_entry entry = { {0} }; 373 struct nix_rx_action action; 374 #ifdef MCAST_MCE 375 struct rvu_pfvf *pfvf; 376 #endif 377 int blkaddr, index; 378 379 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 380 if (blkaddr < 0) 381 return; 382 383 /* Only PF can add a bcast match entry */ 384 if (pcifunc & RVU_PFVF_FUNC_MASK) 385 return; 386 #ifdef MCAST_MCE 387 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 388 #endif 389 390 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 391 nixlf, NIXLF_BCAST_ENTRY); 392 393 /* Check for L2B bit and LMAC channel */ 394 entry.kw[0] = BIT_ULL(25) | chan; 395 entry.kw_mask[0] = BIT_ULL(25) | 0xFFFULL; 396 397 *(u64 *)&action = 0x00; 398 #ifdef MCAST_MCE 399 /* Early silicon doesn't support pkt replication, 400 * so install entry with UCAST action, so that PF 401 * receives all broadcast packets. 402 */ 403 action.op = NIX_RX_ACTIONOP_MCAST; 404 action.pf_func = pcifunc; 405 action.index = pfvf->bcast_mce_idx; 406 #else 407 action.op = NIX_RX_ACTIONOP_UCAST; 408 action.pf_func = pcifunc; 409 #endif 410 411 entry.action = *(u64 *)&action; 412 npc_config_mcam_entry(rvu, mcam, blkaddr, index, 413 NIX_INTF_RX, &entry, true); 414 } 415 416 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 417 int group, int alg_idx, int mcam_index) 418 { 419 struct npc_mcam *mcam = &rvu->hw->mcam; 420 struct nix_rx_action action; 421 int blkaddr, index, bank; 422 423 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 424 if (blkaddr < 0) 425 return; 426 427 /* Check if this is for reserved default entry */ 428 if (mcam_index < 0) { 429 if (group != DEFAULT_RSS_CONTEXT_GROUP) 430 return; 431 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 432 nixlf, NIXLF_UCAST_ENTRY); 433 } else { 434 /* TODO: validate this mcam index */ 435 index = mcam_index; 436 } 437 438 if (index >= mcam->total_entries) 439 return; 440 441 bank = npc_get_bank(mcam, index); 442 index &= (mcam->banksize - 1); 443 444 *(u64 *)&action = rvu_read64(rvu, blkaddr, 445 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 446 /* Ignore if no action was set earlier */ 447 if (!*(u64 *)&action) 448 return; 449 450 action.op = NIX_RX_ACTIONOP_RSS; 451 action.pf_func = pcifunc; 452 action.index = group; 453 action.flow_key_alg = alg_idx; 454 455 rvu_write64(rvu, blkaddr, 456 NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action); 457 } 458 459 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 460 { 461 struct npc_mcam *mcam = &rvu->hw->mcam; 462 struct nix_rx_action action; 463 int blkaddr, index, bank; 464 465 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 466 if (blkaddr < 0) 467 return; 468 469 /* Disable ucast MCAM match entry of this PF/VF */ 470 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 471 nixlf, NIXLF_UCAST_ENTRY); 472 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); 473 474 /* For PF, disable promisc and bcast MCAM match entries */ 475 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) { 476 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 477 nixlf, NIXLF_BCAST_ENTRY); 478 /* For bcast, disable only if it's action is not 479 * packet replication, incase if action is replication 480 * then this PF's nixlf is removed from bcast replication 481 * list. 482 */ 483 bank = npc_get_bank(mcam, index); 484 index &= (mcam->banksize - 1); 485 *(u64 *)&action = rvu_read64(rvu, blkaddr, 486 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 487 if (action.op != NIX_RX_ACTIONOP_MCAST) 488 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); 489 490 rvu_npc_disable_promisc_entry(rvu, pcifunc, nixlf); 491 } 492 } 493 494 #define LDATA_EXTRACT_CONFIG(intf, lid, ltype, ld, cfg) \ 495 rvu_write64(rvu, blkaddr, \ 496 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg) 497 498 #define LDATA_FLAGS_CONFIG(intf, ld, flags, cfg) \ 499 rvu_write64(rvu, blkaddr, \ 500 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg) 501 502 static void npc_config_ldata_extract(struct rvu *rvu, int blkaddr) 503 { 504 struct npc_mcam *mcam = &rvu->hw->mcam; 505 int lid, ltype; 506 int lid_count; 507 u64 cfg; 508 509 cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST); 510 lid_count = (cfg >> 4) & 0xF; 511 512 /* First clear any existing config i.e 513 * disable LDATA and FLAGS extraction. 514 */ 515 for (lid = 0; lid < lid_count; lid++) { 516 for (ltype = 0; ltype < 16; ltype++) { 517 LDATA_EXTRACT_CONFIG(NIX_INTF_RX, lid, ltype, 0, 0ULL); 518 LDATA_EXTRACT_CONFIG(NIX_INTF_RX, lid, ltype, 1, 0ULL); 519 LDATA_EXTRACT_CONFIG(NIX_INTF_TX, lid, ltype, 0, 0ULL); 520 LDATA_EXTRACT_CONFIG(NIX_INTF_TX, lid, ltype, 1, 0ULL); 521 522 LDATA_FLAGS_CONFIG(NIX_INTF_RX, 0, ltype, 0ULL); 523 LDATA_FLAGS_CONFIG(NIX_INTF_RX, 1, ltype, 0ULL); 524 LDATA_FLAGS_CONFIG(NIX_INTF_TX, 0, ltype, 0ULL); 525 LDATA_FLAGS_CONFIG(NIX_INTF_TX, 1, ltype, 0ULL); 526 } 527 } 528 529 /* If we plan to extract Outer IPv4 tuple for TCP/UDP pkts 530 * then 112bit key is not sufficient 531 */ 532 if (mcam->keysize != NPC_MCAM_KEY_X2) 533 return; 534 535 /* Start placing extracted data/flags from 64bit onwards, for now */ 536 /* Extract DMAC from the packet */ 537 cfg = (0x05 << 16) | BIT_ULL(7) | NPC_PARSE_RESULT_DMAC_OFFSET; 538 LDATA_EXTRACT_CONFIG(NIX_INTF_RX, NPC_LID_LA, NPC_LT_LA_ETHER, 0, cfg); 539 } 540 541 static void npc_config_kpuaction(struct rvu *rvu, int blkaddr, 542 struct npc_kpu_profile_action *kpuaction, 543 int kpu, int entry, bool pkind) 544 { 545 struct npc_kpu_action0 action0 = {0}; 546 struct npc_kpu_action1 action1 = {0}; 547 u64 reg; 548 549 action1.errlev = kpuaction->errlev; 550 action1.errcode = kpuaction->errcode; 551 action1.dp0_offset = kpuaction->dp0_offset; 552 action1.dp1_offset = kpuaction->dp1_offset; 553 action1.dp2_offset = kpuaction->dp2_offset; 554 555 if (pkind) 556 reg = NPC_AF_PKINDX_ACTION1(entry); 557 else 558 reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry); 559 560 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1); 561 562 action0.byp_count = kpuaction->bypass_count; 563 action0.capture_ena = kpuaction->cap_ena; 564 action0.parse_done = kpuaction->parse_done; 565 action0.next_state = kpuaction->next_state; 566 action0.capture_lid = kpuaction->lid; 567 action0.capture_ltype = kpuaction->ltype; 568 action0.capture_flags = kpuaction->flags; 569 action0.ptr_advance = kpuaction->ptr_advance; 570 action0.var_len_offset = kpuaction->offset; 571 action0.var_len_mask = kpuaction->mask; 572 action0.var_len_right = kpuaction->right; 573 action0.var_len_shift = kpuaction->shift; 574 575 if (pkind) 576 reg = NPC_AF_PKINDX_ACTION0(entry); 577 else 578 reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry); 579 580 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0); 581 } 582 583 static void npc_config_kpucam(struct rvu *rvu, int blkaddr, 584 struct npc_kpu_profile_cam *kpucam, 585 int kpu, int entry) 586 { 587 struct npc_kpu_cam cam0 = {0}; 588 struct npc_kpu_cam cam1 = {0}; 589 590 cam1.state = kpucam->state & kpucam->state_mask; 591 cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask; 592 cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask; 593 cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask; 594 595 cam0.state = ~kpucam->state & kpucam->state_mask; 596 cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask; 597 cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask; 598 cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask; 599 600 rvu_write64(rvu, blkaddr, 601 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0); 602 rvu_write64(rvu, blkaddr, 603 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1); 604 } 605 606 static inline u64 enable_mask(int count) 607 { 608 return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL)); 609 } 610 611 static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu, 612 struct npc_kpu_profile *profile) 613 { 614 int entry, num_entries, max_entries; 615 616 if (profile->cam_entries != profile->action_entries) { 617 dev_err(rvu->dev, 618 "KPU%d: CAM and action entries [%d != %d] not equal\n", 619 kpu, profile->cam_entries, profile->action_entries); 620 } 621 622 max_entries = rvu_read64(rvu, blkaddr, NPC_AF_CONST1) & 0xFFF; 623 624 /* Program CAM match entries for previous KPU extracted data */ 625 num_entries = min_t(int, profile->cam_entries, max_entries); 626 for (entry = 0; entry < num_entries; entry++) 627 npc_config_kpucam(rvu, blkaddr, 628 &profile->cam[entry], kpu, entry); 629 630 /* Program this KPU's actions */ 631 num_entries = min_t(int, profile->action_entries, max_entries); 632 for (entry = 0; entry < num_entries; entry++) 633 npc_config_kpuaction(rvu, blkaddr, &profile->action[entry], 634 kpu, entry, false); 635 636 /* Enable all programmed entries */ 637 num_entries = min_t(int, profile->action_entries, profile->cam_entries); 638 rvu_write64(rvu, blkaddr, 639 NPC_AF_KPUX_ENTRY_DISX(kpu, 0), enable_mask(num_entries)); 640 if (num_entries > 64) { 641 rvu_write64(rvu, blkaddr, 642 NPC_AF_KPUX_ENTRY_DISX(kpu, 1), 643 enable_mask(num_entries - 64)); 644 } 645 646 /* Enable this KPU */ 647 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01); 648 } 649 650 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr) 651 { 652 struct rvu_hwinfo *hw = rvu->hw; 653 int num_pkinds, num_kpus, idx; 654 struct npc_pkind *pkind; 655 656 /* Get HW limits */ 657 hw->npc_kpus = (rvu_read64(rvu, blkaddr, NPC_AF_CONST) >> 8) & 0x1F; 658 659 /* Disable all KPUs and their entries */ 660 for (idx = 0; idx < hw->npc_kpus; idx++) { 661 rvu_write64(rvu, blkaddr, 662 NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL); 663 rvu_write64(rvu, blkaddr, 664 NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL); 665 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00); 666 } 667 668 /* First program IKPU profile i.e PKIND configs. 669 * Check HW max count to avoid configuring junk or 670 * writing to unsupported CSR addresses. 671 */ 672 pkind = &hw->pkind; 673 num_pkinds = ARRAY_SIZE(ikpu_action_entries); 674 num_pkinds = min_t(int, pkind->rsrc.max, num_pkinds); 675 676 for (idx = 0; idx < num_pkinds; idx++) 677 npc_config_kpuaction(rvu, blkaddr, 678 &ikpu_action_entries[idx], 0, idx, true); 679 680 /* Program KPU CAM and Action profiles */ 681 num_kpus = ARRAY_SIZE(npc_kpu_profiles); 682 num_kpus = min_t(int, hw->npc_kpus, num_kpus); 683 684 for (idx = 0; idx < num_kpus; idx++) 685 npc_program_kpu_profile(rvu, blkaddr, 686 idx, &npc_kpu_profiles[idx]); 687 } 688 689 static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr) 690 { 691 int nixlf_count = rvu_get_nixlf_count(rvu); 692 struct npc_mcam *mcam = &rvu->hw->mcam; 693 int rsvd; 694 u64 cfg; 695 696 /* Get HW limits */ 697 cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST); 698 mcam->banks = (cfg >> 44) & 0xF; 699 mcam->banksize = (cfg >> 28) & 0xFFFF; 700 701 /* Actual number of MCAM entries vary by entry size */ 702 cfg = (rvu_read64(rvu, blkaddr, 703 NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07; 704 mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize; 705 mcam->keysize = cfg; 706 707 /* Number of banks combined per MCAM entry */ 708 if (cfg == NPC_MCAM_KEY_X4) 709 mcam->banks_per_entry = 4; 710 else if (cfg == NPC_MCAM_KEY_X2) 711 mcam->banks_per_entry = 2; 712 else 713 mcam->banks_per_entry = 1; 714 715 /* Reserve one MCAM entry for each of the NIX LF to 716 * guarantee space to install default matching DMAC rule. 717 * Also reserve 2 MCAM entries for each PF for default 718 * channel based matching or 'bcast & promisc' matching to 719 * support BCAST and PROMISC modes of operation for PFs. 720 * PF0 is excluded. 721 */ 722 rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) + 723 ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF); 724 if (mcam->total_entries <= rsvd) { 725 dev_warn(rvu->dev, 726 "Insufficient NPC MCAM size %d for pkt I/O, exiting\n", 727 mcam->total_entries); 728 return -ENOMEM; 729 } 730 731 mcam->entries = mcam->total_entries - rsvd; 732 mcam->nixlf_offset = mcam->entries; 733 mcam->pf_offset = mcam->nixlf_offset + nixlf_count; 734 735 spin_lock_init(&mcam->lock); 736 737 return 0; 738 } 739 740 int rvu_npc_init(struct rvu *rvu) 741 { 742 struct npc_pkind *pkind = &rvu->hw->pkind; 743 u64 keyz = NPC_MCAM_KEY_X2; 744 int blkaddr, err; 745 746 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 747 if (blkaddr < 0) { 748 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 749 return -ENODEV; 750 } 751 752 /* Allocate resource bimap for pkind*/ 753 pkind->rsrc.max = (rvu_read64(rvu, blkaddr, 754 NPC_AF_CONST1) >> 12) & 0xFF; 755 err = rvu_alloc_bitmap(&pkind->rsrc); 756 if (err) 757 return err; 758 759 /* Allocate mem for pkind to PF and channel mapping info */ 760 pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max, 761 sizeof(u32), GFP_KERNEL); 762 if (!pkind->pfchan_map) 763 return -ENOMEM; 764 765 /* Configure KPU profile */ 766 npc_parser_profile_init(rvu, blkaddr); 767 768 /* Config Outer L2, IPv4's NPC layer info */ 769 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2, 770 (NPC_LID_LA << 8) | (NPC_LT_LA_ETHER << 4) | 0x0F); 771 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4, 772 (NPC_LID_LC << 8) | (NPC_LT_LC_IP << 4) | 0x0F); 773 774 /* Enable below for Rx pkts. 775 * - Outer IPv4 header checksum validation. 776 * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2M]. 777 */ 778 rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG, 779 rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) | 780 BIT_ULL(6) | BIT_ULL(2)); 781 782 /* Set RX and TX side MCAM search key size. 783 * Also enable parse key extract nibbles suchthat except 784 * layer E to H, rest of the key is included for MCAM search. 785 */ 786 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX), 787 ((keyz & 0x3) << 32) | ((1ULL << 20) - 1)); 788 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX), 789 ((keyz & 0x3) << 32) | ((1ULL << 20) - 1)); 790 791 err = npc_mcam_rsrcs_init(rvu, blkaddr); 792 if (err) 793 return err; 794 795 /* Config packet data and flags extraction into PARSE result */ 796 npc_config_ldata_extract(rvu, blkaddr); 797 798 /* Set TX miss action to UCAST_DEFAULT i.e 799 * transmit the packet on NIX LF SQ's default channel. 800 */ 801 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_TX), 802 NIX_TX_ACTIONOP_UCAST_DEFAULT); 803 804 /* If MCAM lookup doesn't result in a match, drop the received packet */ 805 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_RX), 806 NIX_RX_ACTIONOP_DROP); 807 808 return 0; 809 } 810 811 void rvu_npc_freemem(struct rvu *rvu) 812 { 813 struct npc_pkind *pkind = &rvu->hw->pkind; 814 815 kfree(pkind->rsrc.bmap); 816 } 817