1 /* SPDX-License-Identifier: GPL-2.0 2 * Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef RVU_H 12 #define RVU_H 13 14 #include "rvu_struct.h" 15 #include "mbox.h" 16 17 /* PCI device IDs */ 18 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 19 20 /* PCI BAR nos */ 21 #define PCI_AF_REG_BAR_NUM 0 22 #define PCI_PF_REG_BAR_NUM 2 23 #define PCI_MBOX_BAR_NUM 4 24 25 #define NAME_SIZE 32 26 27 /* PF_FUNC */ 28 #define RVU_PFVF_PF_SHIFT 10 29 #define RVU_PFVF_PF_MASK 0x3F 30 #define RVU_PFVF_FUNC_SHIFT 0 31 #define RVU_PFVF_FUNC_MASK 0x3FF 32 33 struct rvu_work { 34 struct work_struct work; 35 struct rvu *rvu; 36 }; 37 38 struct rsrc_bmap { 39 unsigned long *bmap; /* Pointer to resource bitmap */ 40 u16 max; /* Max resource id or count */ 41 }; 42 43 struct rvu_block { 44 struct rsrc_bmap lf; 45 u16 *fn_map; /* LF to pcifunc mapping */ 46 bool multislot; 47 bool implemented; 48 u8 addr; /* RVU_BLOCK_ADDR_E */ 49 u8 type; /* RVU_BLOCK_TYPE_E */ 50 u8 lfshift; 51 u64 lookup_reg; 52 u64 pf_lfcnt_reg; 53 u64 vf_lfcnt_reg; 54 u64 lfcfg_reg; 55 u64 msixcfg_reg; 56 u64 lfreset_reg; 57 unsigned char name[NAME_SIZE]; 58 }; 59 60 /* Structure for per RVU func info ie PF/VF */ 61 struct rvu_pfvf { 62 bool npalf; /* Only one NPALF per RVU_FUNC */ 63 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 64 u16 sso; 65 u16 ssow; 66 u16 cptlfs; 67 u16 timlfs; 68 69 /* Block LF's MSIX vector info */ 70 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 71 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 72 u16 *msix_lfmap; /* Vector to block LF mapping */ 73 }; 74 75 struct rvu_hwinfo { 76 u8 total_pfs; /* MAX RVU PFs HW supports */ 77 u16 total_vfs; /* Max RVU VFs HW supports */ 78 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 79 80 struct rvu_block block[BLK_COUNT]; /* Block info */ 81 }; 82 83 struct rvu { 84 void __iomem *afreg_base; 85 void __iomem *pfreg_base; 86 struct pci_dev *pdev; 87 struct device *dev; 88 struct rvu_hwinfo *hw; 89 struct rvu_pfvf *pf; 90 struct rvu_pfvf *hwvf; 91 spinlock_t rsrc_lock; /* Serialize resource alloc/free */ 92 93 /* Mbox */ 94 struct otx2_mbox mbox; 95 struct rvu_work *mbox_wrk; 96 struct workqueue_struct *mbox_wq; 97 98 /* MSI-X */ 99 u16 num_vec; 100 char *irq_name; 101 bool *irq_allocated; 102 dma_addr_t msix_base_iova; 103 104 /* CGX */ 105 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 106 u8 cgx_mapped_pfs; 107 u8 cgx_cnt; /* available cgx ports */ 108 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 109 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 110 * every cgx lmac port 111 */ 112 void **cgx_idmap; /* cgx id to cgx data map table */ 113 struct work_struct cgx_evh_work; 114 struct workqueue_struct *cgx_evh_wq; 115 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 116 struct list_head cgx_evq_head; /* cgx event queue head */ 117 }; 118 119 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 120 { 121 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 122 } 123 124 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 125 { 126 return readq(rvu->afreg_base + ((block << 28) | offset)); 127 } 128 129 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 130 { 131 writeq(val, rvu->pfreg_base + offset); 132 } 133 134 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 135 { 136 return readq(rvu->pfreg_base + offset); 137 } 138 139 /* Function Prototypes 140 * RVU 141 */ 142 143 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 144 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 145 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 146 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 147 int rvu_get_pf(u16 pcifunc); 148 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 149 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 150 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 151 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 152 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 153 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 154 155 /* CGX APIs */ 156 int rvu_cgx_probe(struct rvu *rvu); 157 void rvu_cgx_wq_destroy(struct rvu *rvu); 158 #endif /* RVU_H */ 159