1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef RVU_H 9 #define RVU_H 10 11 #include <linux/pci.h> 12 #include <net/devlink.h> 13 14 #include "rvu_struct.h" 15 #include "rvu_devlink.h" 16 #include "common.h" 17 #include "mbox.h" 18 #include "npc.h" 19 #include "rvu_reg.h" 20 #include "ptp.h" 21 22 /* PCI device IDs */ 23 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 24 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 25 26 /* Subsystem Device ID */ 27 #define PCI_SUBSYS_DEVID_98XX 0xB100 28 #define PCI_SUBSYS_DEVID_96XX 0xB200 29 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 30 #define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00 31 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00 32 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00 33 34 /* PCI BAR nos */ 35 #define PCI_AF_REG_BAR_NUM 0 36 #define PCI_PF_REG_BAR_NUM 2 37 #define PCI_MBOX_BAR_NUM 4 38 39 #define NAME_SIZE 32 40 #define MAX_NIX_BLKS 2 41 #define MAX_CPT_BLKS 2 42 43 /* PF_FUNC */ 44 #define RVU_PFVF_PF_SHIFT 10 45 #define RVU_PFVF_PF_MASK 0x3F 46 #define RVU_PFVF_FUNC_SHIFT 0 47 #define RVU_PFVF_FUNC_MASK 0x3FF 48 49 #ifdef CONFIG_DEBUG_FS 50 struct dump_ctx { 51 int lf; 52 int id; 53 bool all; 54 }; 55 56 struct cpt_ctx { 57 int blkaddr; 58 struct rvu *rvu; 59 }; 60 61 struct rvu_debugfs { 62 struct dentry *root; 63 struct dentry *cgx_root; 64 struct dentry *cgx; 65 struct dentry *lmac; 66 struct dentry *npa; 67 struct dentry *nix; 68 struct dentry *npc; 69 struct dentry *cpt; 70 struct dentry *mcs_root; 71 struct dentry *mcs; 72 struct dentry *mcs_rx; 73 struct dentry *mcs_tx; 74 struct dump_ctx npa_aura_ctx; 75 struct dump_ctx npa_pool_ctx; 76 struct dump_ctx nix_cq_ctx; 77 struct dump_ctx nix_rq_ctx; 78 struct dump_ctx nix_sq_ctx; 79 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 80 int npa_qsize_id; 81 int nix_qsize_id; 82 }; 83 #endif 84 85 struct rvu_work { 86 struct work_struct work; 87 struct rvu *rvu; 88 int num_msgs; 89 int up_num_msgs; 90 }; 91 92 struct rsrc_bmap { 93 unsigned long *bmap; /* Pointer to resource bitmap */ 94 u16 max; /* Max resource id or count */ 95 }; 96 97 struct rvu_block { 98 struct rsrc_bmap lf; 99 struct admin_queue *aq; /* NIX/NPA AQ */ 100 u16 *fn_map; /* LF to pcifunc mapping */ 101 bool multislot; 102 bool implemented; 103 u8 addr; /* RVU_BLOCK_ADDR_E */ 104 u8 type; /* RVU_BLOCK_TYPE_E */ 105 u8 lfshift; 106 u64 lookup_reg; 107 u64 pf_lfcnt_reg; 108 u64 vf_lfcnt_reg; 109 u64 lfcfg_reg; 110 u64 msixcfg_reg; 111 u64 lfreset_reg; 112 unsigned char name[NAME_SIZE]; 113 struct rvu *rvu; 114 u64 cpt_flt_eng_map[3]; 115 u64 cpt_rcvrd_eng_map[3]; 116 }; 117 118 struct nix_mcast { 119 struct qmem *mce_ctx; 120 struct qmem *mcast_buf; 121 int replay_pkind; 122 struct rsrc_bmap mce_counter[2]; 123 /* Counters for both ingress and egress mcast lists */ 124 struct mutex mce_lock; /* Serialize MCE updates */ 125 }; 126 127 struct nix_mce_list { 128 struct hlist_head head; 129 int count; 130 int max; 131 }; 132 133 struct nix_mcast_grp_elem { 134 struct nix_mce_list mcast_mce_list; 135 u32 mcast_grp_idx; 136 u32 pcifunc; 137 int mcam_index; 138 int mce_start_index; 139 struct list_head list; 140 u8 dir; 141 }; 142 143 struct nix_mcast_grp { 144 struct list_head mcast_grp_head; 145 int count; 146 int next_grp_index; 147 struct mutex mcast_grp_lock; /* Serialize MCE updates */ 148 }; 149 150 /* layer metadata to uniquely identify a packet header field */ 151 struct npc_layer_mdata { 152 u8 lid; 153 u8 ltype; 154 u8 hdr; 155 u8 key; 156 u8 len; 157 }; 158 159 /* Structure to represent a field present in the 160 * generated key. A key field may present anywhere and can 161 * be of any size in the generated key. Once this structure 162 * is populated for fields of interest then field's presence 163 * and location (if present) can be known. 164 */ 165 struct npc_key_field { 166 /* Masks where all set bits indicate position 167 * of a field in the key 168 */ 169 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 170 /* Number of words in the key a field spans. If a field is 171 * of 16 bytes and key offset is 4 then the field will use 172 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 173 * nr_kws will be 3(KW0, KW1 and KW2). 174 */ 175 int nr_kws; 176 /* used by packet header fields */ 177 struct npc_layer_mdata layer_mdata; 178 }; 179 180 struct npc_mcam { 181 struct rsrc_bmap counters; 182 struct mutex lock; /* MCAM entries and counters update lock */ 183 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 184 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 185 u16 bmap_entries; /* Number of unreserved MCAM entries */ 186 u16 bmap_fcnt; /* MCAM entries free count */ 187 u16 *entry2pfvf_map; 188 u16 *entry2cntr_map; 189 u16 *cntr2pfvf_map; 190 u16 *cntr_refcnt; 191 u16 *entry2target_pffunc; 192 u8 keysize; /* MCAM keysize 112/224/448 bits */ 193 u8 banks; /* Number of MCAM banks */ 194 u8 banks_per_entry;/* Number of keywords in key */ 195 u16 banksize; /* Number of MCAM entries in each bank */ 196 u16 total_entries; /* Total number of MCAM entries */ 197 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 198 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 199 u16 lprio_count; 200 u16 lprio_start; 201 u16 hprio_count; 202 u16 hprio_end; 203 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 204 /* fields present in the generated key */ 205 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 206 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 207 u64 tx_features; 208 u64 rx_features; 209 struct list_head mcam_rules; 210 }; 211 212 /* Structure for per RVU func info ie PF/VF */ 213 struct rvu_pfvf { 214 bool npalf; /* Only one NPALF per RVU_FUNC */ 215 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 216 u16 sso; 217 u16 ssow; 218 u16 cptlfs; 219 u16 timlfs; 220 u16 cpt1_lfs; 221 u8 cgx_lmac; 222 223 /* Block LF's MSIX vector info */ 224 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 225 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 226 u16 *msix_lfmap; /* Vector to block LF mapping */ 227 228 /* NPA contexts */ 229 struct qmem *aura_ctx; 230 struct qmem *pool_ctx; 231 struct qmem *npa_qints_ctx; 232 unsigned long *aura_bmap; 233 unsigned long *pool_bmap; 234 235 /* NIX contexts */ 236 struct qmem *rq_ctx; 237 struct qmem *sq_ctx; 238 struct qmem *cq_ctx; 239 struct qmem *rss_ctx; 240 struct qmem *cq_ints_ctx; 241 struct qmem *nix_qints_ctx; 242 unsigned long *sq_bmap; 243 unsigned long *rq_bmap; 244 unsigned long *cq_bmap; 245 246 u16 rx_chan_base; 247 u16 tx_chan_base; 248 u8 rx_chan_cnt; /* total number of RX channels */ 249 u8 tx_chan_cnt; /* total number of TX channels */ 250 u16 maxlen; 251 u16 minlen; 252 253 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */ 254 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 255 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 256 257 /* Broadcast/Multicast/Promisc pkt replication info */ 258 u16 bcast_mce_idx; 259 u16 mcast_mce_idx; 260 u16 promisc_mce_idx; 261 struct nix_mce_list bcast_mce_list; 262 struct nix_mce_list mcast_mce_list; 263 struct nix_mce_list promisc_mce_list; 264 bool use_mce_list; 265 266 struct rvu_npc_mcam_rule *def_ucast_rule; 267 268 bool cgx_in_use; /* this PF/VF using CGX? */ 269 int cgx_users; /* number of cgx users - used only by PFs */ 270 271 int intf_mode; 272 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 273 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 274 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 275 u8 lbkid; /* NIX0/1 lbk link ID */ 276 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 277 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ 278 unsigned long flags; 279 struct sdp_node_info *sdp_info; 280 }; 281 282 enum rvu_pfvf_flags { 283 NIXLF_INITIALIZED = 0, 284 PF_SET_VF_MAC, 285 PF_SET_VF_CFG, 286 PF_SET_VF_TRUSTED, 287 }; 288 289 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 290 291 struct nix_bp { 292 struct rsrc_bmap bpids; /* free bpids bitmap */ 293 u16 cgx_bpid_cnt; 294 u16 sdp_bpid_cnt; 295 u16 free_pool_base; 296 u16 *fn_map; /* pcifunc mapping */ 297 u8 *intf_map; /* interface type map */ 298 u8 *ref_cnt; 299 }; 300 301 struct nix_txsch { 302 struct rsrc_bmap schq; 303 u8 lvl; 304 #define NIX_TXSCHQ_FREE BIT_ULL(1) 305 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 306 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 307 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 308 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 309 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 310 u32 *pfvf_map; 311 }; 312 313 struct nix_mark_format { 314 u8 total; 315 u8 in_use; 316 u32 *cfg; 317 }; 318 319 /* smq(flush) to tl1 cir/pir info */ 320 struct nix_smq_tree_ctx { 321 u64 cir_off; 322 u64 cir_val; 323 u64 pir_off; 324 u64 pir_val; 325 }; 326 327 /* smq flush context */ 328 struct nix_smq_flush_ctx { 329 int smq; 330 u16 tl1_schq; 331 u16 tl2_schq; 332 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT]; 333 }; 334 335 struct npc_pkind { 336 struct rsrc_bmap rsrc; 337 u32 *pfchan_map; 338 }; 339 340 struct nix_flowkey { 341 #define NIX_FLOW_KEY_ALG_MAX 32 342 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 343 int in_use; 344 }; 345 346 struct nix_lso { 347 u8 total; 348 u8 in_use; 349 }; 350 351 struct nix_txvlan { 352 #define NIX_TX_VTAG_DEF_MAX 0x400 353 struct rsrc_bmap rsrc; 354 u16 *entry2pfvf_map; 355 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 356 }; 357 358 struct nix_ipolicer { 359 struct rsrc_bmap band_prof; 360 u16 *pfvf_map; 361 u16 *match_id; 362 u16 *ref_count; 363 }; 364 365 struct nix_hw { 366 int blkaddr; 367 struct rvu *rvu; 368 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 369 struct nix_mcast mcast; 370 struct nix_mcast_grp mcast_grp; 371 struct nix_flowkey flowkey; 372 struct nix_mark_format mark_format; 373 struct nix_lso lso; 374 struct nix_txvlan txvlan; 375 struct nix_ipolicer *ipolicer; 376 struct nix_bp bp; 377 u64 *tx_credits; 378 u8 cc_mcs_cnt; 379 }; 380 381 /* RVU block's capabilities or functionality, 382 * which vary by silicon version/skew. 383 */ 384 struct hw_cap { 385 /* Transmit side supported functionality */ 386 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 387 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 388 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 389 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 390 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 391 bool nix_shaping; /* Is shaping and coloring supported */ 392 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 393 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 394 bool nix_rx_multicast; /* Rx packet replication support */ 395 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 396 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 397 bool programmable_chans; /* Channels programmable ? */ 398 bool ipolicer; 399 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */ 400 bool npc_hash_extract; /* Hash extract enabled ? */ 401 bool npc_exact_match_enabled; /* Exact match supported ? */ 402 }; 403 404 struct rvu_hwinfo { 405 u8 total_pfs; /* MAX RVU PFs HW supports */ 406 u16 total_vfs; /* Max RVU VFs HW supports */ 407 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 408 u8 cgx; 409 u8 lmac_per_cgx; 410 u16 cgx_chan_base; /* CGX base channel number */ 411 u16 lbk_chan_base; /* LBK base channel number */ 412 u16 sdp_chan_base; /* SDP base channel number */ 413 u16 cpt_chan_base; /* CPT base channel number */ 414 u8 cgx_links; 415 u8 lbk_links; 416 u8 sdp_links; 417 u8 cpt_links; /* Number of CPT links */ 418 u8 npc_kpus; /* No of parser units */ 419 u8 npc_pkinds; /* No of port kinds */ 420 u8 npc_intfs; /* No of interfaces */ 421 u8 npc_kpu_entries; /* No of KPU entries */ 422 u16 npc_counters; /* No of match stats counters */ 423 u32 lbk_bufsize; /* FIFO size supported by LBK */ 424 bool npc_ext_set; /* Extended register set */ 425 u64 npc_stat_ena; /* Match stats enable bit */ 426 427 struct hw_cap cap; 428 struct rvu_block block[BLK_COUNT]; /* Block info */ 429 struct nix_hw *nix; 430 struct rvu *rvu; 431 struct npc_pkind pkind; 432 struct npc_mcam mcam; 433 struct npc_exact_table *table; 434 }; 435 436 struct mbox_wq_info { 437 struct otx2_mbox mbox; 438 struct rvu_work *mbox_wrk; 439 440 struct otx2_mbox mbox_up; 441 struct rvu_work *mbox_wrk_up; 442 443 struct workqueue_struct *mbox_wq; 444 }; 445 446 struct rvu_fwdata { 447 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 448 #define RVU_FWDATA_VERSION 0x0001 449 u32 header_magic; 450 u32 version; /* version id */ 451 452 /* MAC address */ 453 #define PF_MACNUM_MAX 32 454 #define VF_MACNUM_MAX 256 455 u64 pf_macs[PF_MACNUM_MAX]; 456 u64 vf_macs[VF_MACNUM_MAX]; 457 u64 sclk; 458 u64 rclk; 459 u64 mcam_addr; 460 u64 mcam_sz; 461 u64 msixtr_base; 462 u32 ptp_ext_clk_rate; 463 u32 ptp_ext_tstamp; 464 #define FWDATA_RESERVED_MEM 1022 465 u64 reserved[FWDATA_RESERVED_MEM]; 466 #define CGX_MAX 9 467 #define CGX_LMACS_MAX 4 468 #define CGX_LMACS_USX 8 469 union { 470 struct cgx_lmac_fwdata_s 471 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 472 struct cgx_lmac_fwdata_s 473 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX]; 474 }; 475 /* Do not add new fields below this line */ 476 }; 477 478 struct ptp; 479 480 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 481 * source where it came from. 482 */ 483 struct npc_kpu_profile_adapter { 484 const char *name; 485 u64 version; 486 const struct npc_lt_def_cfg *lt_def; 487 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 488 const struct npc_kpu_profile *kpu; /* array[kpus] */ 489 struct npc_mcam_kex *mkex; 490 struct npc_mcam_kex_hash *mkex_hash; 491 bool custom; 492 size_t pkinds; 493 size_t kpus; 494 }; 495 496 #define RVU_SWITCH_LBK_CHAN 63 497 498 struct rvu_switch { 499 struct mutex switch_lock; /* Serialize flow installation */ 500 u32 used_entries; 501 u16 *entry2pcifunc; 502 u16 mode; 503 u16 start_entry; 504 }; 505 506 struct rvu { 507 void __iomem *afreg_base; 508 void __iomem *pfreg_base; 509 struct pci_dev *pdev; 510 struct device *dev; 511 struct rvu_hwinfo *hw; 512 struct rvu_pfvf *pf; 513 struct rvu_pfvf *hwvf; 514 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 515 struct mutex alias_lock; /* Serialize bar2 alias access */ 516 int vfs; /* Number of VFs attached to RVU */ 517 u16 vf_devid; /* VF devices id */ 518 int nix_blkaddr[MAX_NIX_BLKS]; 519 520 /* Mbox */ 521 struct mbox_wq_info afpf_wq_info; 522 struct mbox_wq_info afvf_wq_info; 523 524 /* PF FLR */ 525 struct rvu_work *flr_wrk; 526 struct workqueue_struct *flr_wq; 527 struct mutex flr_lock; /* Serialize FLRs */ 528 529 /* MSI-X */ 530 u16 num_vec; 531 char *irq_name; 532 bool *irq_allocated; 533 dma_addr_t msix_base_iova; 534 u64 msixtr_base_phy; /* Register reset value */ 535 536 /* CGX */ 537 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 538 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 539 u8 cgx_mapped_pfs; 540 u8 cgx_cnt_max; /* CGX port count max */ 541 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 542 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for 543 * every cgx lmac port 544 */ 545 unsigned long pf_notify_bmap; /* Flags for PF notification */ 546 void **cgx_idmap; /* cgx id to cgx data map table */ 547 struct work_struct cgx_evh_work; 548 struct workqueue_struct *cgx_evh_wq; 549 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 550 struct list_head cgx_evq_head; /* cgx event queue head */ 551 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 552 553 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 554 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 555 556 /* Firmware data */ 557 struct rvu_fwdata *fwdata; 558 void *kpu_fwdata; 559 size_t kpu_fwdata_sz; 560 void __iomem *kpu_prfl_addr; 561 562 /* NPC KPU data */ 563 struct npc_kpu_profile_adapter kpu; 564 565 struct ptp *ptp; 566 567 int mcs_blk_cnt; 568 int cpt_pf_num; 569 570 #ifdef CONFIG_DEBUG_FS 571 struct rvu_debugfs rvu_dbg; 572 #endif 573 struct rvu_devlink *rvu_dl; 574 575 /* RVU switch implementation over NPC with DMAC rules */ 576 struct rvu_switch rswitch; 577 578 struct work_struct mcs_intr_work; 579 struct workqueue_struct *mcs_intr_wq; 580 struct list_head mcs_intrq_head; 581 /* mcs interrupt queue lock */ 582 spinlock_t mcs_intrq_lock; 583 /* CPT interrupt lock */ 584 spinlock_t cpt_intr_lock; 585 }; 586 587 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 588 { 589 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 590 } 591 592 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 593 { 594 return readq(rvu->afreg_base + ((block << 28) | offset)); 595 } 596 597 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 598 { 599 writeq(val, rvu->pfreg_base + offset); 600 } 601 602 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 603 { 604 return readq(rvu->pfreg_base + offset); 605 } 606 607 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 608 { 609 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of 610 * write operation. 611 */ 612 rvu_write64(rvu, block, offset, val); 613 rvu_read64(rvu, block, offset); 614 /* Barrier to ensure read completes before accessing LF registers */ 615 mb(); 616 } 617 618 /* Silicon revisions */ 619 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 620 { 621 struct pci_dev *pdev = rvu->pdev; 622 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 623 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 624 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 625 (pdev->revision == 0x14)); 626 } 627 628 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 629 { 630 struct pci_dev *pdev = rvu->pdev; 631 632 return (pdev->revision == 0x00); 633 } 634 635 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 636 { 637 struct pci_dev *pdev = rvu->pdev; 638 639 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 640 } 641 642 static inline bool is_rvu_95xx_A0(struct rvu *rvu) 643 { 644 struct pci_dev *pdev = rvu->pdev; 645 646 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 647 } 648 649 /* REVID for PCIe devices. 650 * Bits 0..1: minor pass, bit 3..2: major pass 651 * bits 7..4: midr id 652 */ 653 #define PCI_REVISION_ID_96XX 0x00 654 #define PCI_REVISION_ID_95XX 0x10 655 #define PCI_REVISION_ID_95XXN 0x20 656 #define PCI_REVISION_ID_98XX 0x30 657 #define PCI_REVISION_ID_95XXMM 0x40 658 #define PCI_REVISION_ID_95XXO 0xE0 659 660 static inline bool is_rvu_otx2(struct rvu *rvu) 661 { 662 struct pci_dev *pdev = rvu->pdev; 663 664 u8 midr = pdev->revision & 0xF0; 665 666 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 667 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 668 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 669 } 670 671 static inline bool is_cnf10ka_a0(struct rvu *rvu) 672 { 673 struct pci_dev *pdev = rvu->pdev; 674 675 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A && 676 (pdev->revision & 0x0F) == 0x0) 677 return true; 678 return false; 679 } 680 681 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu) 682 { 683 u64 npc_const3; 684 685 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3); 686 if (!(npc_const3 & BIT_ULL(62))) 687 return false; 688 689 return true; 690 } 691 692 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 693 u8 lmacid, u8 chan) 694 { 695 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 696 u16 cgx_chans = nix_const & 0xFFULL; 697 struct rvu_hwinfo *hw = rvu->hw; 698 699 if (!hw->cap.programmable_chans) 700 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 701 702 return rvu->hw->cgx_chan_base + 703 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 704 } 705 706 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 707 u8 chan) 708 { 709 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 710 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 711 struct rvu_hwinfo *hw = rvu->hw; 712 713 if (!hw->cap.programmable_chans) 714 return NIX_CHAN_LBK_CHX(lbkid, chan); 715 716 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 717 } 718 719 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 720 { 721 struct rvu_hwinfo *hw = rvu->hw; 722 723 if (!hw->cap.programmable_chans) 724 return NIX_CHAN_SDP_CHX(chan); 725 726 return hw->sdp_chan_base + chan; 727 } 728 729 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 730 { 731 return rvu->hw->cpt_chan_base + chan; 732 } 733 734 static inline bool is_rvu_supports_nix1(struct rvu *rvu) 735 { 736 struct pci_dev *pdev = rvu->pdev; 737 738 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX) 739 return true; 740 741 return false; 742 } 743 744 /* Function Prototypes 745 * RVU 746 */ 747 #define RVU_LBK_VF_DEVID 0xA0F8 748 static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc) 749 { 750 return (!(pcifunc & ~RVU_PFVF_FUNC_MASK) && 751 (rvu->vf_devid == RVU_LBK_VF_DEVID)); 752 } 753 754 static inline bool is_vf(u16 pcifunc) 755 { 756 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 757 } 758 759 /* check if PF_FUNC is AF */ 760 static inline bool is_pffunc_af(u16 pcifunc) 761 { 762 return !pcifunc; 763 } 764 765 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 766 { 767 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 768 (rvu->fwdata->version == RVU_FWDATA_VERSION); 769 } 770 771 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 772 void rvu_free_bitmap(struct rsrc_bmap *rsrc); 773 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 774 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 775 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 776 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 777 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 778 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start); 779 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 780 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 781 int rvu_get_pf(u16 pcifunc); 782 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 783 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 784 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 785 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 786 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 787 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 788 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 789 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 790 int rvu_get_num_lbk_chans(void); 791 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 792 u16 global_slot, u16 *slot_in_block); 793 794 /* RVU HW reg validation */ 795 enum regmap_block { 796 TXSCHQ_HWREGMAP = 0, 797 MAX_HWREGMAP, 798 }; 799 800 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 801 802 /* NPA/NIX AQ APIs */ 803 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 804 int qsize, int inst_size, int res_size); 805 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 806 807 /* SDP APIs */ 808 int rvu_sdp_init(struct rvu *rvu); 809 bool is_sdp_pfvf(u16 pcifunc); 810 bool is_sdp_pf(u16 pcifunc); 811 bool is_sdp_vf(struct rvu *rvu, u16 pcifunc); 812 813 /* CGX APIs */ 814 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 815 { 816 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 817 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT); 818 } 819 820 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 821 { 822 *cgx_id = (map >> 4) & 0xF; 823 *lmac_id = (map & 0xF); 824 } 825 826 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 827 { 828 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 829 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))); 830 } 831 832 #define M(_name, _id, fn_name, req, rsp) \ 833 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 834 MBOX_MESSAGES 835 #undef M 836 837 int rvu_cgx_init(struct rvu *rvu); 838 int rvu_cgx_exit(struct rvu *rvu); 839 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 840 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 841 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 842 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 843 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 844 int rxtxflag, u64 *stat); 845 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 846 847 /* NPA APIs */ 848 int rvu_npa_init(struct rvu *rvu); 849 void rvu_npa_freemem(struct rvu *rvu); 850 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 851 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 852 struct npa_aq_enq_rsp *rsp); 853 854 /* NIX APIs */ 855 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 856 int rvu_nix_init(struct rvu *rvu); 857 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 858 int blkaddr, u32 cfg); 859 void rvu_nix_freemem(struct rvu *rvu); 860 int rvu_get_nixlf_count(struct rvu *rvu); 861 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 862 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 863 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 864 struct nix_mce_list *mce_list, 865 int mce_idx, int mcam_index, bool add); 866 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 867 struct nix_mce_list **mce_list, int *mce_idx); 868 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 869 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 870 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 871 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 872 struct nix_hw **nix_hw, int *blkaddr); 873 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 874 u16 rq_idx, u16 match_id); 875 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 876 struct nix_cn10k_aq_enq_req *aq_req, 877 struct nix_cn10k_aq_enq_rsp *aq_rsp, 878 u16 pcifunc, u8 ctype, u32 qidx); 879 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 880 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type); 881 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 882 u32 convert_bytes_to_dwrr_mtu(u32 bytes); 883 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc, 884 struct nix_txsch *txsch, bool enable); 885 void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc); 886 int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc, 887 u32 mcast_grp_idx); 888 int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc, 889 u32 mcast_grp_idx, u16 mcam_index); 890 void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc); 891 892 /* NPC APIs */ 893 void rvu_npc_freemem(struct rvu *rvu); 894 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 895 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 896 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 897 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 898 int nixlf, u64 chan, u8 *mac_addr); 899 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 900 int nixlf, u64 chan, u8 chan_cnt); 901 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 902 bool enable); 903 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 904 int nixlf, u64 chan); 905 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 906 bool enable); 907 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 908 u64 chan); 909 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 910 bool enable); 911 912 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 913 int nixlf, int type, bool enable); 914 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 915 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable); 916 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 917 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 918 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 919 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 920 int group, int alg_idx, int mcam_index); 921 922 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 923 int blkaddr, int *alloc_cnt, 924 int *enable_cnt); 925 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 926 int blkaddr, int *alloc_cnt, 927 int *enable_cnt); 928 bool is_npc_intf_tx(u8 intf); 929 bool is_npc_intf_rx(u8 intf); 930 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 931 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 932 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 933 const char *npc_get_field_name(u8 hdr); 934 int npc_get_bank(struct npc_mcam *mcam, int index); 935 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 936 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 937 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 938 int blkaddr, int index, bool enable); 939 u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 940 int blkaddr, int index); 941 void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 942 int blkaddr, int index, u64 cfg); 943 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 944 int blkaddr, u16 src, struct mcam_entry *entry, 945 u8 *intf, u8 *ena); 946 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); 947 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 948 u32 rvu_cgx_get_fifolen(struct rvu *rvu); 949 void *rvu_first_cgx_pdata(struct rvu *rvu); 950 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 951 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); 952 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable); 953 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, 954 u16 pfc_en); 955 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); 956 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc); 957 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); 958 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 959 int type); 960 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 961 int index); 962 int rvu_npc_init(struct rvu *rvu); 963 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 964 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 965 u64 bcast_mcast_val, u64 bcast_mcast_mask); 966 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx); 967 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf); 968 int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr); 969 void npc_mcam_rsrcs_deinit(struct rvu *rvu); 970 971 /* CPT APIs */ 972 int rvu_cpt_register_interrupts(struct rvu *rvu); 973 void rvu_cpt_unregister_interrupts(struct rvu *rvu); 974 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, 975 int slot); 976 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc); 977 int rvu_cpt_init(struct rvu *rvu); 978 979 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0) 980 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16) 981 982 /* CN10K RVU */ 983 int rvu_set_channels_base(struct rvu *rvu); 984 void rvu_program_channels(struct rvu *rvu); 985 986 /* CN10K NIX */ 987 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); 988 989 /* CN10K RVU - LMT*/ 990 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 991 void rvu_apr_block_cn10k_init(struct rvu *rvu); 992 993 #ifdef CONFIG_DEBUG_FS 994 void rvu_dbg_init(struct rvu *rvu); 995 void rvu_dbg_exit(struct rvu *rvu); 996 #else 997 static inline void rvu_dbg_init(struct rvu *rvu) {} 998 static inline void rvu_dbg_exit(struct rvu *rvu) {} 999 #endif 1000 1001 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); 1002 1003 /* RVU Switch */ 1004 void rvu_switch_enable(struct rvu *rvu); 1005 void rvu_switch_disable(struct rvu *rvu); 1006 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc); 1007 1008 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 1009 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 1010 u8 shift_dir); 1011 int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 1012 1013 /* CN10K MCS */ 1014 int rvu_mcs_init(struct rvu *rvu); 1015 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); 1016 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); 1017 void rvu_mcs_exit(struct rvu *rvu); 1018 1019 #endif /* RVU_H */ 1020